4G bits DDR3L SDRAM DATA SHEET

4G bits DDR3L SDRAM DATA SHEET
4G B Die DDRIII SDRAM Specification
P3P4GF4BLF
Deutron Electronics Corp.
8F, 68, Sec. 3, NanKing E. RD., Taipei 104,
Taiwan, R.O.C.
TEL: (886)-2-2517-7768
FAX: (886)-2-2517-4575
4G bits DDR3L SDRAM DATA SHEET
(1024M words x 4 bits)
(512M words x 8 bits)
(256M words x 16 bits)
Specifications
Features
• Density: 4G bits
• Double-data-rate architecture: two data transfers per
clock cycle
• Organization
• The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
— 128M word x4 bits x 8 banks
— 64M word x8 bits x 8 banks
— 32M word x16 bits x 8 banks
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• Package
— 78-ball FBGA(X4/X8)
— 96-ball FBGA(X16)
— Lead-free (RoHS compliant) and Halogen-free
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• Power supply: 1.35V (typ)
— VDD = 1.283V to 1.45V
• DLL aligns DQ and DQS transitions with CK transitions
— Backward compatible for VDD, VDDQ
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
= 1.5V ± 0.075V
• Data mask (DM) for write data
• Data rate
—1600/1333 Mbps (1.35V)
—1866/1600/1333Mbps(1.5V)
• 1KB page size
— Row address: A0 to A15(X4/X8)
— Column address: A0 to A9,A11(X4)
A0 to A9(X8)
• 2KB page size
— Row address: A0 to A14(X16)
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
— Column address: A0 to A9(X16)
• Eight internal banks for concurrent operation
• Burst length (BL): 8 and 4 with Burst Chop (BC)
• Burst type (BT):
— Sequential (8, 4 with BC)
• Multi Purpose Register (MPR) for pre-defined pattern
read out
• On-Die Termination (ODT) for better signal quality
— Synchronous ODT
— Dynamic ODT
— Asynchronous ODT
• ZQ calibration for DQ drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• /RESET pin for Power-up sequence and reset function
— Interleave (8, 4 with BC)
• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11,13(1866)
• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11(1600/1333)
• SRT range:
— Normal/extended
• Programmable Output driver impedance control
• /CAS Write Latency (CWL): 5, 6, 7, 8,9(1866)
• /CAS Write Latency (CWL): 5, 6, 7, 8(1600/1333)
• Precharge: auto precharge option for each burst
access
• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
• Refresh: auto-refresh, self-refresh
• Refresh cycles
— Average refresh period
7.8μs at 0°C  TC +85°C
3.9μs at +85°C < TC +95°C
• Operating case temperature range
— TC = 0°C to +95°C
1
4G Bits DDR3L SDRAM
Part Number
P 3 P 4G F 4 B L F – GJS
Detailed Information
For detailed electrical specification and further information, please refer to the DDR3L SDRAM General Functionality
and Electrical Condition data sheet.
2
4G Bits DDR3L SDRAM
Pin Configurations
Pin Configurations (×4/×8 configuration)
/xxx indicates active low signal.
78-ball FBGA (×4 configuration)
78-ball FBGA (×8 configuration)
1
2
3
7
8
9
VSS
VDD
NC
NC
VSS
VDD
A
1
2
3
7
8
9
VSS
VDD
NC
NU/(/TDQS)
VSS
VDD
VSS
VSSQ
DQ0
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
VSSQ
DQ6
/DQS
VDD
VSS
VSSQ
DQ4
DQ7
DQ5
VDDQ
A
B
B
VSS
VSSQ
DQ0
DM
VSSQ VDDQ
C
DM/TDQS VSSQ
VDDQ
C
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
D
D
VSSQ
NC
/DQS
VDD
VSS
VSSQ
E
E
VREFDQ VDDQ
NC
NC
NC
VDDQ
VREFDQ VDDQ
F
F
NC
VSS
/RAS
CK
VSS
NC
G
NC
VSS
/RAS
CK
VSS
NC
ODT
VDD
/CAS
/CK
VDD
CKE
NC
/CS
/WE
A10(AP)
ZQ
NC
VSS
BA0
BA2
A15
VDD
A3
A0
A12(/BC)
VSS
A5
A2
VDD
A7
G
ODT
VDD
/CAS
/CK
VDD
CKE
H
H
NC
/CS
A10(AP)
/WE
ZQ
NC
J
J
VSS
BA0
BA2
A15
VREFCA VSS
K
VREFCA VSS
K
VDD
A3
A0
A12(/BC) BA1
VDD
L
BA1
VDD
A1
A4
VSS
A9
A11
A6
VDD
A13
A14
A8
VSS
L
VSS
M
A5
VDD
A7
A2
A1
A9
A11
A4
A6
VSS
M
VDD
N
N
VSS
/RESET
A13
A14
A8
VSS
VSS
/RESET
(Top view)
Pin name
Function
A0 to A15*
Address inputs
A10(AP): Auto precharge
3
(Top view)
Pin name
Function
3
RESET*
Active low asynchronous reset
A12(/BC): Burst chop
3
BA0 to BA2*
Bank select
VDD
Supply voltage for internal circuit
DQ0 to DQ7
Data input/output
VSS
Ground for internal circuit
DQS, /DQS
Differential data strobe
VDDQ
Supply voltage for DQ circuit
TDQS, /TDQS
Termination data strobe
VSSQ
Ground for DQ circuit
Chip select
VREFDQ
Reference voltage for DQ
Command input
VREFCA
Reference voltage for CA
Clock enable
ZQ
Reference pin for ZQ calibration
CK, /CK
Differential clock input
NC*
DM
Write data mask
/CS*
3
3
/RAS, /CAS, /WE*
3
CKE*
3
ODT*
Notes: 1.
1
NU*
2
ODT control
Not internally connected with die.
2.
Don't connect. Internally connected.
3.
Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
3
No connection
Not usable
4G Bits DDR3L SDRAM
Pin Configurations (× 16 configuration)
/xxx indicates active low signal.
96-ball FBGA
1
2
3
7
8
9
VDDQ
DQU5
DQU7
DQU4
VDDQ
VSS
VSSQ
VDD
VSS
/DQSU
DQU6
VSSQ
VDDQ
DQU3
DQU1
DQSU
DQU2
VDDQ
VSSQ
VDDQ
DMU
DQU0
VSSQ
VDD
VSSQ
VDDQ
A
B
C
D
E
VSS
VSSQ
DQL0
DML
VDDQ
DQL2
DQSL
DQL1
DQL3
VSSQ
VSSQ
DQL6
/DQSL
VDD
VSS
VSSQ
DQL4
DQL7
DQL5
VDDQ
F
G
H
VREFDQ
VDDQ
J
NC
VSS
/RAS
CK
VSS
NC
ODT
VDD
/CAS
/CK
VDD
CKE
NC
/CS
/WE
A10(AP)
ZQ
NC
VSS
BA0
BA2
NC
VDD
A3
A0
A12(/BC)
VSS
A5
A2
VDD
A7
VSS
/RESET
K
L
M
VREFCA VSS
N
BA1
VDD
A1
A4
VSS
A9
A11
A6
VDD
A13
A14
A8
VSS
P
R
T
(Top view)
Pin name
Function
Pin name
Address inputs
2
A0 to A14*
/RESET*
A10(AP): Auto precharge
Function
2
Active low asynchronous reset
A12(/BC): Burst chop
2
BA0 to BA2*
Bank select
VDD
Supply voltage for internal circuit
DQU0 to DQU7
Data input/output
VSS
Ground for internal circuit
Differential data strobe
VDDQ
Supply voltage for DQ circuit
Chip select
VSSQ
Ground for DQ circuit
Command input
VREFDQ
Reference voltage for DQ
Clock enable
VREFCA
Reference voltage for CA
Differential clock input
ZQ
Reference pin for ZQ calibration
DQL0 to DQL7
DQSU, /DQSU
DQSL, /DQSL
2
/CS*
2
/RAS, /CAS, /WE*
2
CKE*
CK, /CK
DMU, DML
Write data mask
NC*
1
2
ODT control
ODT*
Notes:
1.
Not internally connected with die.
2.
Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
4
No connection
4G Bits DDR3L SDRAM
CONTENTS
Specifications………………………………………………………………………………………………….....1
1
Features .................................................................................................................................................1
1
Ordering Information ..........................................................................................................................….2
2
Part Number . …………………………………………………………………………………………………….2
2
Detailed Information . ……………………………………………………………………………………….......2
2
Pin Configurations(x4/x8) .………………………………………………………………………………………3
3
Pin Configurations(x16).......................................................................................................................….4
4
1. Electrical Conditions ……………………………………………………………………………………..….5
6
1.1 Absolute Maximum Ratings . ………………………………………………………………………………………………
66
1.2 Operating Temperature Condition ………………………………………………………………………………………..
66
1.3 Recommended DC Operating Conditions ………………………………………………………………………………..
77
1.4 IDD and IDDQ Measurement Conditions …………………………………………………………………………………
88
2. Electrical Specifications . ...............................................................................................................19
19
2.1
DC Characteristics(x4/x8/x16)...............................................................................................................................
19
19
2.2
Pin Capacitance . .................................................................................................................................................20
20
2.3 Standard Speed Bins . . ......................................................................................................................................21
..21
3. Package Drawing . . .........................................................................................................................
2525
3.1 78-ball FBGA . ......................................................................................................................................................
2525
3.2 96-ball FBGA . .......................................................................................................................................................26
26
4. Recommended Soldering Conditions . ...........................................................................................27
27
5
4G Bits DDR3L SDRAM
1.
Electrical Conditions
• All voltages are referenced to VSS (GND)
• Execute power-up and Initialization sequence before proper device operation is achieved.
1.1
Absolute Maximum Ratings
Table 1: Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Notes
Power supply voltage
VDD
- 0.4
to +1.975
V
1, 3
Power supply voltage for output
VDDQ
- 0.4
to +1.975
V
1, 3
Input voltage
VIN
- 0.4
to +1.975
V
1
Output voltage
VOUT
- 0.4
to +1.975
V
1
Reference voltage
VREFCA
- 0.4
to x 0.6 x VDD
V
3
Reference voltage for DQ
VREFDQ
- 0.4
to x 0.6 x VDDQ
V
3
Storage temperature
Tstg
-55 to +100
°C
1, 2
Power dissipation
PD
1.0
W
1
Short circuit output current
IOUT
50
mA
1
Notes:
1.
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2.
3.
Storage temperature is the case surface temperature on the center/top side of the DRAM.
VDD and VDDQ must be within 300mV of each other at all times; and VREF must be no greater than 0.6 x VDDQ, When
VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
Caution: Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
1.2
Operating Temperature Condition
Table 2: Operating Temperature Condition
Parameter
Symbol
Rating
Unit
Notes
Operating case temperature
TC
0 to +95
°C
1, 2, 3
Notes:
1.
Operating temperature is the case surface temperature on the center/top side of the DRAM.
2.
The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During
operation, the DRAM case temperature must be maintained between 0°C to +85°C under all operating conditions.
3.
Some applications require operation of the DRAM in the Extended Temperature Range between +85°C and +95°C case
temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9μs. (This double
refresh requirement may not apply for some devices.)
b) If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual
Self-Refresh mode with Extended Temperature Range capability (MR2 bit [A6, A7] = [0, 1]) or enable the optional Auto
Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]).
6
4G Bits DDR3L SDRAM
1.3
Recommended DC Operating Conditions
Table 3: Recommended DC Operating Conditions (TC = 0°C to +85°C), DDR3L Operation
Parameter
Symbol
min.
typ.
max.
Unit
Notes
Supply voltage
VDD
1.283
1.35
1.45
V
1, 2, 3, 4
Supply voltage for DQ
VDDQ
1.283
1.35
1.45
V
1, 2, 3, 4
Notes
: 1.
Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ(t) over a very
long period of time (e.g. 1 sec).
2.
If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
3.
Under these supply voltages, the device operates to this DDR3L specifcation.
4.
Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while
5.
VDD and VDDQ are changed for DDR3 operation shown as following timing wave form.
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK, /CK
tCKSRX
T(min) = 10ns
VDD, VDDQ (DDR3)
VDD, VDDQ (DDR3L)
T(min) = 10ns
T(min) = 200μs
T = 500μs
/RESET
CKE
tIS
T(min) = 10ns
Valid
tDLLK
tXPR
tIS
*1
Command
BA
tMRD
tMRD
tMRD
tMOD
MRS
MRS
MRS
MRS
MR2
MR3
MR1
MR0
tZQinit
ZQCL
tIS
ODT
*1
Valid
Valid
tIS
Static low in case RTT_Nore is enabled at time Tg, otherwise static high or low
Valid
RTT
: VIH or VIL
Note: 1. From time point Td until Tk, NOP or DES commands must be applied between MRS and ZQCL commands.
Figure 1: VDD/VDDQ Voltage Switch between DDR3L and DDR3
7
4G Bits DDR3L SDRAM
1.4
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined.
The figure Measurement Setup and Test Load for IDD and IDDQ Measurements shows the setup and test load for IDD
and IDDQ measurements.
• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W,
IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3
SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of
the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents.
Note:IDDQ values cannot be directly used to calculate I/O power of the DDR3 SDRAM. They can be used to support
correlation of simulated I/O power to actual I/O power as outlined in correlation from simulated channel I/O
power to actual channel I/O power supported by IDDQ measurement.
For IDD and IDDQ measurements, the following definitions apply:
• L and 0: VIN

VIL(AC)max
• H and 1: VIN

VIH(AC)min
• MID-LEVEL: defined as inputs are VREF = VDDQ / 2
• FLOATING: don't care or floating around VREF.
• Timings used for IDD and IDDQ measurement-loop patterns are provided in Timings used for IDD and IDDQ
Measurement-Loop Patterns table.
• Basic IDD and IDDQ measurement conditions are described in Basic IDD and IDDQ Measurement Conditions
table.
Note:The IDD and IDDQ measurement-loop patterns need to be executed at least one time before actual IDD or
IDDQ measurement is started.
• Detailed IDD and IDDQ measurement-loop patterns are described in IDD0 Measurement-Loop Pattern table
through IDD7 Measurement-Loop Pattern table.
• IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting.
RON = RZQ/7 (34Ω in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40Ω in MR1);
RTT_WR = RZQ/2 (120Ω in MR2);
TDQS Feature disabled in MR1
• Define D = {/CS, /RAS, /CAS, /WE} : = {H, L, L, L}
• Define /D = {/CS, /RAS, /CAS, /WE} : = {H, H, H, H}
8
4G Bits DDR3L SDRAM
IDD
IDDQ
VDD
VDDQ
/RESET
CK, /CK
DDR3
SDRAM
CKE
DQS, /DQS,
RTT = 25Ω
VDDQ/2
DQ, DM,
/CS
/RAS, /CAS, /WE
TDQS, /TDQS
Address, BA
ODT
ZQ
VSS
VSSQ
Figure 2: Measurement Setup and Test Load for IDD and IDDQ Measurements
Application specific
memory channel
IDDQ
environment
Test load
Channel
IDDQ
IDDQ
I/O power
measurement
simulation
simulation
Correlation
Correction
Channel I/O power
number
Figure 3: Correlation from Simulated Channel I/O Power to Actual Channel I/O Power
Supported by IDDQ Measurement
9
4G Bits DDR3L SDRAM
1.4.1
Timings Used for IDD and IDDQ Measurement-Loop Patterns
Table 4: Timings Used for IDD and IDDQ Measurement-Loop Patterns
DDR3-1866
Parameter
CL
tCK(min)
13-13-13
13
13
1.07
DDR3-1600
DDR3-1333
11-11-11
9-9-9
Unit
11
9
nCK
1.25
1.5
ns
nRCD(min)
13
11
9
nCK
nRC(min)
45
39
33
nCK
nRAS(min)
32
28
24
nCK
nRP(min)
13
11
9
nCK
nFAW (1KB)
26
24
20
nCK
nFAW (2KB, 4KB)
33
32
30
nCK
nRRD (1KB)
5
5
4
nCK
nRRD (2KB, 4KB)
6
6
5
nCK
nRFC (1Gb)
103
88
74
nCK
nRFC (2Gb)
150
128
107
nCK
nRFC (4Gb)
243
208
174
nCK
10
4G Bits DDR3L SDRAM
1.4.2
Basic IDD and IDDQ Measurement Conditions
Table 5: Basic IDD and IDDQ Measurement Conditions
Parameter
Symbol
Description
1
Operating one bank
active precharge
IDD0
CKE: H; External clock: on; tCK, nRC, nRAS, CL: see Table 5; BL: 8* ; AL: 0; /CS: H
between ACT and PRE; Command, address, bank address inputs: partially toggling
according to Table 7; Data I/O: MID-LEVEL; DM: stable at 0;
Bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 7);
current
2
Output buffer and RTT: enabled in MR*
Table 7
; ODT
signal: stable at 0; Pattern details: see
1 6
CKE: H; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 5; BL: 8* , * ; AL:
0; /CS: H between ACT, RD and PRE; Command, address, bank address inputs, data
Operating one bank
active-read-precharge
IDD1
I/O: partially toggling according to Table 8;
DM: stable at 0; Bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,...
2
current
(see Table 8); Output buffer and RTT: enabled in MR* ; ODT Signal: stable at 0;
Pattern details: see Table 8
1
CKE: H; External clock: on; tCK, CL: see Table 5 BL: 8* ; AL: 0; /CS: stable at 1;
Precharge standby
current
IDD2N
Command, address, bank address Inputs: partially toggling according to Table 9;
data I/O: MID-LEVEL; DM: stable at 0; bank activity: all banks closed; output buffer
2
and RTT: enabled in mode registers* ; ODT signal: stable at 0; pattern details: see
Table 9
1
Precharge standby
ODT current
CKE: H; External clock: on; tCK, CL: see Table 5; BL: 8* ; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: partially toggling according to Table 10;
IDD2NT
data I/O: MID-LEVEL; DM: stable at 0; bank activity: all banks closed; output buffer
2
and RTT: enabled in MR*
details: see Table 10
Precharge standby
ODT IDDQ current
IDDQ2NT
; ODT signal: toggling according to Table 10; pattern
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD
current
1
Precharge power-down
current slow exit
IDD2P0
CKE: L; External clock: on; tCK, CL: see Table 5; BL: 8* ; AL: 0; /CS: stable at 1;
Command, address, bank address inputs: stable at 0; data I/O: MID-LEVEL; DM:
2
stable at 0; bank activity: all banks closed; output buffer and RTT: EMR*
; ODT
3
signal: stable at 0; precharge power down mode: slow exit*
1
Precharge power-down
current fast exit
IDD2P1
CKE: L; External clock: on; tCK, CL: see Table 6; BL: 8* ; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: stable at 0; data I/O: MID-LEVEL;
DM:stable
at 0; bank activity: all banks closed; output buffer and RTT: enabled
in
2
3
MR* ; ODT signal: stable at 0; precharge power down mode: fast exit*
1
Precharge quiet
standby current
IDD2Q
CKE: H; External clock: On; tCK, CL: see Table 5; BL: 8* ; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: stable at 0; data I/O: MID-LEVEL;
DM: stable at 0;bank activity: all banks closed; output buffer and RTT: enabled in
MR*2; ODT signal: stable at 0
1
CKE: H; External clock: on; tCK, CL: see Table 5; BL: 8* ; AL: 0; /CS: stable at 1;
Active standby current
IDD3N
Command, address, bank address Inputs: partially toggling according to Table 9;
2
data I/O: MID-LEVEL; DM: stable at 0;
bank activity: all banks open; output buffer and RTT: enabled in MR* ;
ODT signal: stable at 0; pattern details: see Table 9
1
Active power-down
current
IDD3P
CKE: L; External clock: on; tCK, CL: see Table 5; BL: 8* ; AL: 0; /CS: stable at 1;
Command, address, bank address inputs: stable at 0; data I/O: MID-LEVEL;
DM:stable at 0; bank activity: all banks open; output buffer and RTT:
2
enabled in MR* ; ODT signal: stable at 0
1
6
CKE: H; External clock: on; tCK, CL: see Table 5; BL: 8* , * ; AL: 0; /CS: H between
RD; Command, address, bank address Inputs: partially toggling according to
Table 11; data I/O: seamless read
Operating burst read
current
IDD4R
data burst with different data between one burst and the next one according to
Table 11; DM: stable at 0;
bank activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...
2
(see Table 11); Output buffer and RTT: enabled in MR*
pattern details: see Table 11
Operating burst read
IDDQ current
IDDQ4R
; ODT signal: stable at 0;
Same definition like for IDD4R, however measuring IDDQ current instead of IDD
current
11
4G Bits DDR3L SDRAM
Table 6: Basic IDD and IDDQ Measurement Conditions (cont’d)
Parameter
Symbol
Description
1
CKE: H; External clock: on; tCK, CL: see Table 5; BL: 8* ; AL: 0; /CS: H between WR;
command, address, bank address inputs: partially toggling according to Table 12;
data I/O: seamless write data burst with different data between one burst and the next
one according to IDD4W Measurement-Loop Pattern table; DM: stable at 0; bank
Operating burst write current
IDD4W
activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,.. (see Table 12); Output buffer
2
and RTT: enabled in MR*
; ODT signal: stable
at H; pattern details: see Table 12
1
CKE: H; External clock: on; tCK, CL, nRFC: see Table 5; BL: 8* ; AL: 0; /CS: H
between REF;
Command, address, bank address Inputs: partially toggling according to Table 13;
Burst refresh current
IDD5B
data I/O: MID-LEVEL; DM: stable at 0;
bank activity: REF command every nRFC (Table 13); output buffer and RTT: enabled
2
in MR* ; ODT signal: stable at 0; pattern
details: see Table 13
4
TC: 0 to 85°C; ASR: disabled* ; SRT:
5
Self-refresh current: normal
temperature range
1
Normal* ; CKE: L; External clock: off; CK and /CK: L; CL: see Table 5; BL: 8* ;
IDD6
AL: 0; /CS, command, address, bank address, data I/O: MID-LEVEL; DM: stable
2
at 0; bank activity: Self-refresh operation; output buffer and RTT: enabled in MR*
ODT signal: MID-LEVEL
4
;
5
TC: 0 to 95°C; ASR: Disabled* ; SRT: Extended*
; CKE: L; External clock: off; CK
1
Self-refresh current: extended
temperature range
IDD6ET
and /CK: L; CL: Table 5; BL: 8* ; AL: 0; /CS, command, address, bank address, data
I/O: MID-LEVEL;
DM: stable at 0; bank activity: Extended temperature self-refresh operation; output
2
buffer and RTT: enabled in MR*
; ODT signal: MID-LEVEL
4
5
TC: 0 to 95°C; ASR: Enabled* ; SRT: Normal* ; CKE: L; External clock: off;
Auto self-refresh current
(Optional)
1
IDD6TC
CK and /CK: L; CL: Table 5; BL: 8* ; AL: 0; /CS, command, address, bank address,
data I/O: MID-LEVEL; DM: stable at 0; bank activity: Auto self-refresh operation;
2
output buffer and RTT: enabled in MR*
; ODT signal: MID-LEVEL
CKE: H; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 5;
1
Operating bank interleave
read current
6
BL: 8* , * ; AL: CL-1; /CS: H between ACT and RDA; Command, address, bank
address Inputs: partially toggling according to Table 14; data I/O: read data bursts
IDD7
with different data between one burst and the next one according to Table 14; DM:
stable at 0; bank activity: two times interleaved cycling through banks (0, 1, …7) with
different addressing, see Table 14; output buffer and RTT: enabled in MR*2; ODT
signal: stable at 0; pattern details: see Table 14
/RESET: low; External clock: off; CK and /CK: low; CKE: FLOATING; /CS, command,
RESET low current
IDD8
address, bank address, Data IO: FLOATING; ODT signal: FLOATING
RESET low current reading is valid once power is stable and /RESET has been low
for at least 1ms.
Notes:
1.
Burst Length: BL8 fixed by MRS: MR0 bits [1,0] = [0,0].
2.
MR: Mode Register
Output buffer enable: set MR1 bit A12 = 1 and MR1 bits [5, 1] = [0,1];
RTT_Nom enable: set MR1 bits [9, 6, 2] = [0, 1, 1]; RTT_WR enable: set MR2 bits [10, 9] = [1,0].
3.
Precharge power down mode: set MR0 bit A12= 0 for Slow Exit or MR0 bit A12 = 1 for fast exit.
4.
Auto self-refresh (ASR): set MR2 bit A6 = 0 to disable or 1 to enable feature.
5.
Self-refresh temperature range (SRT): set MR0 bit A7= 0 for normal or 1 for extended temperature range.
6.
Read burst type: nibble sequential, set MR0 bit A3 = 0
12
4G Bits DDR3L SDRAM
Table 7: IDD0 Measurement-Loop Pattern
CK,
Sub
/CK
CKE
-Loop
Cycle
Com-
number
Mand
/CS
A11
0
ACT
0
0
1
1, 2
D, D
1
0
0
3, 4
/D, /D
1
1
1
…
Repeat pattern 1…4 until nRAS
nRAS
PRE
…
Repeat pattern 1...4 until nRC
0
/RAS
0
/CAS
/WE
A7
A3
A0
-Am
A10
-A9
-A6
-A2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ODT
BA*
1
0
0
0
1
0
3
- 1, truncate if necessary
1
0
0
- 1, truncate if necessary
1 X nRC
0
+0
ACT
0
0
1
1
0
0
0
0
0
F
0
D, D
1
0
0
0
0
0
0
0
0
F
0
/D, /D
1
1
1
1
0
0
0
0
0
F
0
0
0
F
0
1 X nRC
+1, 2
1 X nRC
+ 3, 4
Toggling Static H
Repeat pattern nRC + 1,...,4 until 1 x nRC + Nras - 1, truncate if necessary
…
1 X nRC
+ nRAS
0
0
1
0
Repeat nRC + 1,...,4 until 2 x nRC
…
Notes:
PRE
1
2
nRC Repeat Sub-Loop 0, use BA= 1 instead
2
4
nRC Repeat Sub-Loop 0, use BA= 2 instead
3
6
nRC Repeat Sub-Loop 0, use BA= 3 instead
4
8
nRC Repeat Sub-Loop 0, use BA= 4 instead
5
10
nRC Repeat Sub-Loop 0, use BA= 5 instead
6
12
nRC Repeat Sub-Loop 0, use BA= 6 instead
7
14
nRC Repeat Sub-Loop 0, use BA= 7 instead
1.
DM must be driven low all the time. DQS, /DQS are MID-LEVEL.
2.
DQ signals are MID-LEVEL.
3.
BA: BA0 to BA2.
4.
Am: m means Most Significant Bit (MSB) of Row address.
13
0
0
- 1, truncate if necessary
0
2
Data*
4G Bits DDR3L SDRAM
Table 8: IDD1 Measurement-Loop Pattern
CK,
Sub
/CK
CKE
-Loop
Cycle
Com-
number
mand
/CS
A11
0
ACT
0
0
1
1, 2
D, D
1
0
0
3, 4
/D, /D
1
1
1
…
Repeat pattern 1...4 until nRCD - 1, truncate if necessary
nRCD
RD
…
Repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS
PRE
…
Repeat pattern 1...4 until nRC - 1, truncate if necessary
0
0
/RAS /CAS
1
0
0
/WE
1
A0
-A2
0
0
0
_
0
0
0
_
0
0
0
0
_
0
0
0
0
0
0
0
0
0
0
0
_
BA*
1
0
0
0
1
0
1
0
0
0
-A7
A9
A3
-A6
ODT
3
-Am
A10
0
0
0
0
0
0
0
0
0
2
Data*
00000000
1 x nRC
+0
0
ACT
0
0
1
1
0
0
0
0
0
F
0
_
D, D
1
0
0
0
0
0
0
0
0
F
0
_
/D, /D
1
1
1
1
0
0
0
0
0
F
0
_
0
0
F
0
0
0
F
0
1 x nRC
+ 1, 2
1 x nRC
+ 3, 4
Toggling Static H
Repeat pattern nRC + 1,..., 4 until nRC + nRCD - 1, truncate if necessary
…
1 x nRC
+ nRCD
…
RD
0
1
0
1
0
0
0
Repeat pattern nRC + 1,..., 4 until nRC +nRAS
- 1, truncate if necessary
PRE
0
00110011
1 x nRC
0
0
1
0
0
0
+ nRAS
…
Notes:
Repeat pattern nRC + 1,..., 4 until 2
1
2
nRC Repeat Sub-Loop 0, use BA= 1 instead
2
4
nRC Repeat Sub-Loop 0, use BA= 2 instead
3
6
nRC Repeat Sub-Loop 0, use BA= 3 instead
4
8
nRC Repeat Sub-Loop 0, use BA= 4 instead
5
10
nRC Repeat Sub-Loop 0, use BA= 5 instead
6
12
nRC Repeat Sub-Loop 0, use BA= 6 instead
7
14
nRC Repeat Sub-Loop 0, use BA= 7 instead
x nRC
- 1, truncate if necessary
1.
DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise MID-LEVEL.
2.
Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are MID-LEVEL.
3.
BA: BA0 to BA2.
4.
Am: m means Most Significant Bit (MSB) of Row address.
14
_
4G Bits DDR3L SDRAM
Table 9: IDD2N and IDD3N Measurement-Loop Pattern
CK,
Sub
/CK
CKE
-Loop
Cycle
Com-
number
Mand
A11
/CS
/RAS
/CAS
/WE
ODT
BA*
3
A7
A3
A0
-Am
A10
-A9
-A6
-A2
0
D
1
0
0
0
0
0
0
0
0
0
0
1
D
1
0
0
0
0
0
0
0
0
0
0
2
/D
1
1
1
1
0
0
0
0
0
F
0
3
/D
1
1
1
1
0
0
0
0
0
F
0
1
4 to 7
Repeat Sub-Loop 0, use BA= 1 instead
2
8 to 11
Repeat Sub-Loop 0, use BA= 2 instead
3
12 to 15
Repeat Sub-Loop 0, use BA= 3 instead
4
16 to 19
Repeat Sub-Loop 0, use BA= 4 instead
5
20 to 23
Repeat Sub-Loop 0, use BA= 5 instead
6
24 to 27
Repeat Sub-Loop 0, use BA= 6 instead
7
28 to 31
Repeat Sub-Loop 0, use BA= 7 instead
A7
A3
A0
2
Data*
0
Toggling Static H
Notes:
1.
DM must be driven low all the time. DQS, /DQS are MID-LEVEL.
2.
DQ signals are MID-LEVEL.
3.
BA: BA0 to BA2.
4.
Am: m means Most Significant Bit (MSB) of Row address.
Table 10: IDD2NT and IDDQ2NT Measurement-Loop Pattern
CK,
Sub
/CK
CKE
-Loop
Cycle
Com-
A11
-Am
ODT
BA*3
A10
-A9
-A6
-A2
0
D
1
0
0
0
0
0
0
0
0
0
0
1
D
1
0
0
0
0
0
0
0
0
0
0
2
/D
1
1
1
1
0
0
0
0
0
F
0
3
/D
1
1
1
1
0
0
0
0
0
F
0
number
Mand
/CS
/RAS
/CAS
/WE
0
Toggling Static H
Notes:
1
4 to 7
Repeat Sub-Loop 0, but ODT = 0 and BA= 1
2
8 to 11
Repeat Sub-Loop 0, but ODT = 1 and BA= 2
3
12 to 15
Repeat Sub-Loop 0, but ODT = 1 and BA= 3
4
16 to 19
Repeat Sub-Loop 0, but ODT = 0 and BA= 4
5
20 to 23
Repeat Sub-Loop 0, but ODT = 0 and BA= 5
6
24 to 27
Repeat Sub-Loop 0, but ODT = 1 and BA= 6
7
28 to 31
Repeat Sub-Loop 0, but ODT = 1 and BA= 7
1.
DM must be driven low all the time. DQS, /DQS are MID-LEVEL.
2.
DQ signals are MID-LEVEL.
3.
BA: BA0 to BA2.
4.
Am: m means Most Significant Bit (MSB) of Row address.
15
2
Data*
4G Bits DDR3L SDRAM
Table 11: IDD4R and IDDQ4R Measurement-Loop Pattern
CK,
Sub
/CK
CKE
-Loop
Cycle
Com-
number
mand
A11
/CS
/RAS
/CAS
/WE
ODT
BA*
3
A7
A3
A0
-Am
A10
-A9
-A6
-A2
2
Data*
0
RD
0
1
0
1
0
0
0
0
0
0
0
1
D
1
0
0
0
0
0
0
0
0
0
0
00000000
_
2,3
/D, /D
1
1
1
1
0
0
0
0
0
0
0
_
4
RD
0
1
0
1
0
0
0
0
0
F
0
5
D
1
0
0
0
0
0
0
0
0
F
0
_
6,7
/D, /D
1
1
1
1
0
0
0
0
0
F
0
_
1
8 to 15
Repeat Sub-Loop 0, but BA= 1
2
16 to 23
Repeat Sub-Loop 0, but BA= 2
3
24 to 31
Repeat Sub-Loop 0, but BA= 3
4
32 to 39
Repeat Sub-Loop 0, but BA= 4
5
40 to 47
Repeat Sub-Loop 0, but BA= 5
6
48 to 55
Repeat Sub-Loop 0, but BA= 6
7
56 to 63
Repeat Sub-Loop 0, but BA= 7
0
Toggling Static H
Notes:
1.
DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise MID-LEVEL.
2.
Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are MID-LEVEL.
3.
BA: BA0 to BA2.
4.
Am: m means Most Significant Bit (MSB) of Row address.
16
00110011
4G Bits DDR3L SDRAM
Table 12: IDD4W Measurement-Loop Pattern
CK,
Sub
/CK
CKE
-Loop
Cycle
Com-
number
Mand
A11
/CS
/RAS
/CAS
/WE
ODT
BA*
3
A7
A3
A0
-Am
A10
-A9
-A6
-A2
2
Data*
0
WR
0
1
0
0
1
0
0
0
0
0
0
1
D
1
0
0
0
1
0
0
0
0
0
0
00000000
_
2,3
/D, /D
1
1
1
1
1
0
0
0
0
0
0
_
4
WR
0
1
0
0
1
0
0
0
0
F
0
5
D
1
0
0
0
1
0
0
0
0
F
0
_
6,7
/D, /D
1
1
1
1
0
0
0
0
F
0
_
1
8 to 15
Repeat Sub-Loop 0, but BA= 1
2
16 to 23
Repeat Sub-Loop 0, but BA= 2
3
24 to 31
Repeat Sub-Loop 0, but BA= 3
4
32 to 39
Repeat Sub-Loop 0, but BA= 4
5
40 to 47
Repeat Sub-Loop 0, but BA= 5
6
48 to 55
Repeat Sub-Loop 0, but BA= 6
7
56 to 63
Repeat Sub-Loop 0, but BA= 7
0
Toggling Static H
Notes:
1
1.
DM must be driven low all the time. DQS, /DQS are used according to write commands, otherwise MID-LEVEL.
2.
Burst sequence driven on each DQ signal by write command. Outside burst operation, DQ signals are MID-LEVEL.
3.
BA: BA0 to BA2.
4.
Am: m means Most Significant Bit (MSB) of Row address.
00110011
Table 13: IDD5B Measurement-Loop Pattern
CK,
/CK
CKE
Sub
Cycle
Com-
-Loop
number
mand
/CS
0
REF
1, 2
D
3,4
/D, /D
5 to 8
Repeat cycles 1...4, but BA= 1
9 to 12
Repeat cycles 1...4, but BA= 2
13 to 16
Repeat cycles 1...4, but BA= 3
17 to 20
Repeat cycles 1...4, but BA= 4
21 to 24
Repeat cycles 1...4, but BA= 5
25 to 28
Repeat cycles 1...4, but BA= 6
29 to 32
Repeat cycles 1...4, but BA= 7
33 to
nRFC -1
Repeat Sub-Loop 1, until nRFC -1. Truncate, if necessary.
0
Toggling Static H
1
2
Notes: 1.
A11
/RAS
/CAS
0
0
0
1
0
0
1
1
1
DM must be driven low all the time. DQS, /DQS are MID-LEVEL.
2.
DQ signals are MID-LEVEL.
3.
BA: BA0 to BA2.
4.
Am: m means Most Significant Bit (MSB) of Row address.
17
/WE
2
A7
A3
A0
-Am
A10
-A9
-A6
-A2
0
0
0
0
0
0
_
0
0
0
0
0
0
_
0
0
0
0
F
0
_
ODT
BA*
1
0
0
0
1
0
3
Data*
4G Bits DDR3L SDRAM
Table 14: IDD7 Measurement-Loop Pattern
CK,
Sub
/CK
CKE
Cycle
Com-
number
mand
/CS
/RAS
0
ACT
0
0
1
RDA
0
1
2
D
1
0
…
Repeat above D Command until nRRD -1
nRRD
ACT
0
0
1
nRRD + 1
RDA
0
1
0
nRRD + 2
D
1
0
0
…
Repeat above D Command until 2
2
2 x nRRD
Repeat Sub-Loop 0, but BA= 2
3
3 x nRRD
-Loop
/CAS
A11
-Am
A10
A0
-A2
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
F
0
0
1
0
F
0
0
0
1
0
0
0
F
0
_
0
3
0
0
0
F
0
_
0
0
0
F
0
_
_
ODT
BA*3
1
1
0
0
1
0
0
0
A7
-A9
0
1
4
4 x nRRD
5
nFAW
6
2
A3
-A6
/WE
Data*
_
00000000
_
_
00110011
nRRD -1
Repeat Sub-Loop 1, but BA= 3
D
1
0
0
0
Assert and repeat above D Command until nFAW -1, if necessary
nFAW
+ nRRD
Repeat Sub-Loop 0, but BA= 4
Repeat Sub-Loop 1, but BA= 5
7
nFAW
+ 2 x nRRD
Repeat Sub-Loop 0, but BA= 6
8
nFAW
+ 3 x nRRD
Repeat Sub-Loop 1, but BA= 7
9
D
1
0
0
0
0
7
nFAW
+ 4 x nRRD Assert and repeat above D Command until 2 x nFAW -1, if necessary
2 x nFAW
+0
ACT
0
0
1
1
0
0
0
0
0
F
0
RDA
0
1
0
1
0
0
0
1
0
F
0
1
0
0
0
0
0
0
0
0
F
0
_
_
2 x nFAW
Toggling Static H 10
+1
2 x nFAW D
+2
00110011
Repeat above D Command until 2 x nFAW + nRRD -1
2 x nFAW
+ nRRD
ACT
0
0
1
1
0
1
0
0
0
0
0
RDA
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
_
3
0
0
0
0
0
_
0
0
0
0
_
2 x nFAW
11
00000000
+ nRRD + 1
2 x nFAW D
+ nRRD + 2
Repeat above D Command until 2 x nFAW + 2 x nRRD -1
2 x nFAW
12
+2 x nRRD
Repeat Sub-Loop 10, but BA= 2
2 x nFAW
13
+ 3 x nRRD
2 x nFAW D
14
15
Repeat Sub-Loop 11, but BA= 3
1
0
0
0
0
+ 4 x nRRD
Assert and repeat above D Command until 3 x nFAW -1, if necessary
3 x nFAW
Repeat Sub-Loop 10, but BA= 4
3 x nFAW
16
Repeat Sub-Loop 11, but BA= 5
+nRRD
3 x nFAW
17
+ 2 x nRRD
Repeat Sub-Loop 10, but BA= 6
3 x nFAW
18
+ 3 x nRRD
3 x nFAW D
19
Notes:
+ 4 x nRRD
Repeat Sub-Loop 11, but BA= 7
1
0
0
0
0
7
0
Assert and repeat above D Command until 4 x nFAW -1, if necessary
1.
DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise MID-LEVEL.
2.
Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are MID-LEVEL.
3.
BA: BA0 to BA2.
4.
Am: m means Most Significant Bit (MSB) of Row address.
18
4G Bits DDR3L SDRAM
2.
2.1
Electrical Specifications(x4/x8/x16)
DC Characteristics
Table 15: DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.35V)
x8
x16
max.
max.
max
Unit
70
65
70
65
60
80
75
70
mA
85
80
75
100
95
90
mA
Parameter
Symbol
Operating current
(ACT-PRE)
IDD0
Operating current
(ACT-READ-PRE)
IDD1
1866
1600
1333
60
85
80
75
IDD2P1
1866
1600
1333
35
35
35
35
35
35
35
35
35
mA
IDD2P0
1866
1600
1333
20
20
20
20
20
20
20
20
20
mA
Precharge standby current
IDD2N
1866
1600
1333
45
45
45
45
45
45
45
45
45
mA
Precharge standby
ODT current
IDD2NT
1866
1600
1333
45
45
45
45
45
45
45
45
45
mA
Precharge quiet standby
current
IDD2Q
1866
1600
1333
45
45
45
45
45
45
45
45
45
mA
Active power-down current
(Always fast exit)
IDD3P
1866
1600
1333
40
39
37
40
39
37
40
39
37
mA
Active standby current
IDD3N
1866
1600
1333
55
55
55
55
55
55
55
55
55
mA
Operating current
(Burst read operating)
IDD4R
1866
1600
1333
140
120
105
145
125
110
180
160
145
mA
Operating current
(Burst write operating)
IDD4W
1866
1600
1333
145
125
110
150
130
115
205
185
170
mA
Burst refresh current
IDD5B
1866
1600
1333
260
250
250
260
250
250
260
250
250
mA
All bank interleave read
current
IDD7
1866
1600
1333
210
200
190
220
210
200
260
250
230
mA
RESET low current
IDD8
17
17
Precharge power-down
standby current
Data rate (Mbps)
x4
1866
1600
1333
1866/1600/1333
17
Notes
Fast PD Exit
Slow PD Exit
mA
Self-Refresh Current (TC = 0°C to +85°C, VDD, VDDQ = 1.35V)
x4
Parameter
Symbol
Grade
.
x8
x16
max.
max.
max.
Unit
22
22
22
mA
25
25
25
mA
Self-refresh curre
normal temperature range
IDD6
Self-refresh current.
1866/1600/1333
1866/1600/1333
extended temperature range
IDD6E
Auto self-refresh current
(Optional)
IDD6TC
1866/1600/1333
一
19
一
一
mA
Notes
4G Bits DDR3L SDRAM
2.2
Pin Capacitance
Table 16: Pin Capacitance [DDR3-1333 to 1600] (TC = 25°C, VDD, VDDQ = 1.283V to 1.45V)
DDR3L-1866
Parameter
Symbol
Input/output capacitance
Input capacitance,
CK and /CK
Input capacitance delta,
CK and /CK
CIO
CCK
Min
DDR3L-1600
DDR3L-1333
Max
Min
Max
Min
Max
Units Notes
1.4
2.2
1.4
2.2
1.4
2.3
pF
1, 2
0.8
1.4
0.8
1.4
0.8
1.4
pF
2
CDCK
0
0.15
0
0.15
0
0.15
pF
2, 3
CDDQS
0
0.15
0
0.15
0
0.15
pF
2, 4
CI
0.75
1.2
0.75
1.2
0.75
1.3
pF
2, 5
CDI_CTRL _
-0.4
0.2
-0.4
0.2
-0.4
0.2
pF
2, 6, 7
CDI_ADD_
-0.4
0.4
-0.4
0.4
-0.4
0.4
pF
2, 8, 9
CDIO
-0.5
0.3
-0.5
0.3
-0.5
0.3
pF
2, 10
CZQ
_
3
_
3
pF
2, 11
Input/output capacitance
delta,
DQS and /DQS
Input capacitance,
(control, address,
command, input-only
pins)
Input capacitance delta,
(All control input-only
pins)
Input capacitance delta,
(All addres/command
input-only pins)
CMD
Input/output capacitance
delta, DQ,DM, DQS,
/DQS, TDQS, /TDQS
Input/output capacitance
of ZQ pin
Notes:
3
1. Although the DM, TDQS and /TDQS pins have different functions, the loading matches DQ and DQS.
2. VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, /RESET and ODT as
necessary). VDD = VDDQ = 1.35V, VBIAS=VDD/2 and ondie termination off.
3. Absolute value of CCK-C/CK.
4. Absolute value of CIO(DQS)-CIO(/DQS).
5. CI applies to ODT, /CS, CKE, A0-A15, BA0-BA2, /RAS, /CAS and /WE.
6. CDI_CTRL applies to ODT, /CS and CKE.
7. CDI_CTRL = CI(CTRL) -0.5 x (CI(CK)+CI(/CK)).
8. CDI_ADD_CMD applies to A0-A15, BA0-BA2, /RAS, /CAS and /WE.
9. CDI_ADD_CMD = CI(ADD_CMD) -0.5 x (CI(CK)+CI(/CK)).
10. CDIO=CIO(DQ,DM) -0.5 x (CIO(DQS)+CIO(/DQS)).
11. Maximum external load capacitance on ZQ pin: 5pF.
20
_
4G Bits DDR3L SDRAM
2.2
Standard Speed Bins
Table 17: DDR3-1866 Speed Bins
Speed Bin
DDR3-1866
CL-tRCD-tRP
13-13-13
Symbol
/CAS write latency
min
max
Unit
tAA
13.91
20
ns
tRCD
13.91
_
ns
tRP
13.91
_
ns
tRC
47.91
_
ns
34.0
9 x tREFI
ns
8
CWL = 5
3.0
3.3
ns
1, 2, 3, 8
CWL = 6, 7, 8,9
Reserved
Reserved
ns
4
CWL = 5
2.5
3.3
ns
1, 2, 3, 8
CWL = 6
Reserved
Reserved
ns
4
CWL = 7, 8,9
Reserved
Reserved
ns
4
CWL = 5
Reserved
Reserved
ns
4
CWL = 6
1.875
ns
1, 2, 3, 8
CWL = 7,8,9
Reserved
Reserved
ns
4
CWL = 5
Reserved
Reserved
ns
4
CWL = 6
1.875
ns
1, 2, 3, 8
CWL = 7
Reserved
Reserved
ns
4
tRAS
tCK(avg) @CL=5
tCK(avg) @CL=6
tCK(avg) @CL=7
tCK(avg) @CL=8
tCK(avg) @CL=9
tCK(avg) @CL=10
tCK(avg) @CL=12
tCK(avg) @CL=13
2.5
2.5
CWL = 8,9
Reserved
Reserved
ns
4
CWL = 5, 6
Reserved
Reserved
ns
4
CWL= 7
1.5
1.875
ns
1, 2, 3, 8
CWL= 8
Reserved
Reserved
ns
4
CWL= 9
Reserved
Reserved
ns
4
CWL = 5, 6
Reserved
Reserved
ns
4
1.875
ns
1,2,3,8
Reserved
ns
4
CWL= 7
tCK(avg) @CL=11
Notes
1.5
CWL= 8
Reserved
CWL = 5, 6, 7
Reserved
Reserved
ns
4
CWL= 8
1.25
1.5
ns
1, 2, 3, 8
CWL=
CWL= 9
9
Reserved
Reserved
ns
4
CWL = 5, 6, 7,8
Reserved
Reserved
ns
4
CWL= 9
Reserved
Reserved
ns
4
CWL = 5, 6, 7,8
Reserved
Reserved
ns
4
CWL= 9
1.07
1.25
ns
4
nCK
1,2,3,8
5, 6, 7, 8, 9, 10, 11,13
Supported CL settings
5, 6, 7, 8,9
Supported CWL settings
21
nCK
4G Bits DDR3L SDRAM
Table 18: DDR3-1600 Speed Bins
Speed Bin
DDR3-1600
CL-tRCD-tRP
11-11-11
Symbol
/CAS write latency
min
13.75
tAA
(13.125)
13.75
tRCD
13.75
48.75
tCK(avg) @CL=8
tCK(avg) @CL=9
tCK(avg) @CL=10
tCK(avg) @CL=11
20
ns
9
_
ns
9
_
ns
9
_
ns
9
(48.125)
35
9 x tREFI
ns
8
CWL = 5
3.0
3.3
ns
1, 2, 3, 4, 7, 10
CWL = 6, 7, 8
Reserved
Reserved
ns
4
CWL = 5
2.5
3.3
ns
1, 2, 3, 7
CWL = 6
Reserved
Reserved
ns
4
CWL = 7, 8
Reserved
Reserved
ns
4
CWL = 5
Reserved
Reserved
ns
4
CWL = 6
1.875
< 2.5
ns
1, 2, 3, 4, 7
CWL = 7
Reserved
Reserved
ns
4
CWL = 8
Reserved
Reserved
ns
4
CWL = 5
Reserved
Reserved
ns
4
CWL = 6
1.875
< 2.5
ns
1, 2, 3, 7
CWL = 7
Reserved
Reserved
ns
4
tRAS
tCK(avg) @CL=7
Notes
(13.125)
tRC
tCK(avg) @CL=6
Unit
(13.125)
tRP
tCK(avg) @CL=5
max
CWL = 8
Reserved
Reserved
ns
4
CWL = 5, 6
Reserved
Reserved
ns
4
CWL= 7
1.5
< 1.875
ns
1, 2, 3, 4, 7
CWL= 8
Reserved
Reserved
ns
4
CWL = 5, 6
Reserved
Reserved
ns
4
CWL= 7
1.5
< 1.875
ns
1, 2, 3, 7
CWL= 8
Reserved
Reserved
ns
4
CWL = 5, 6, 7
Reserved
Reserved
ns
4
CWL= 8
1.25
< 1.5
ns
Supported CL settings
5, 6, 7, 8, 9, 10, 11
Supported CWL settings
5, 6, 7, 8
22
nCK
nCK
1,2,3
4G Bits DDR3L SDRAM
Table 19 DDR3-1333 Speed Bins
Speed Bin
DDR3-1333
CL-tRCD-tRP
9-9-9
Symbol
/CAS write latency
min
13.5
tAA
(13.125)
max
Unit
Notes
20
ns
9
_
ns
9
_
ns
9
_
ns
9
13.5
tRCD
(13.125)
13.5
tRP
(13.125)
49.5
tRC
(49.125)
36
9 x tREFI
ns
8
CWL = 5
3.0
3.3
ns
1, 2, 3, 4, 6, 10
CWL = 6, 7
Reserved
Reserved
ns
4
CWL = 5
2.5
3.3
ns
1, 2, 3, 6
CWL = 6
Reserved
Reserved
ns
4
CWL = 7
Reserved
Reserved
ns
4
CWL = 5
Reserved
Reserved
ns
4
CWL = 6
1.875
< 2.5
ns
1, 2, 3, 4, 6
CWL = 7
Reserved
Reserved
ns
4
CWL = 5
Reserved
Reserved
ns
4
CWL = 6
1.875
< 2.5
ns
1, 2, 3, 6
CWL = 7
Reserved
Reserved
ns
4
CWL = 5, 6
Reserved
Reserved
ns
4
CWL= 7
1.5
< 1.875
ns
1, 2, 3, 4
CWL = 5, 6
Reserved
Reserved
ns
4
CWL= 7
1.5
< 1.875
ns
1, 2, 3
tRAS
tCK(avg) @CL=5
tCK(avg) @CL=6
tCK(avg) @CL=7
tCK(avg) @CL=8
tCK(avg) @CL=9
tCK(avg) @CL=10
Supported CL settings
5, 6, 7, 8, 9, 10
Supported CWL settings
5, 6, 7
23
nCK
nCK
4G Bits DDR3L SDRAM
Notes:
1. The CL setting and CWL setting result in tCK(avg)min and tCK(avg)max requirements. When making a selection of
tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(avg)min limits: Since /CAS latency is not purely analog - data and strobe output are synchronized by the DLL - all
possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard
tCK(avg) value (3.0, 2.5, 1.875, 1.5, or 1.25ns) when calculating CL(nCK) = tAA(ns) / tCK(avg)(ns), rounding up to the
next ‘Supported CL’.
3. tCK(avg)max limits: Calculate tCK(avg) + tAA(max)/CL selected and round the resulting tCK(avg) down to the next valid
speed bin (i.e. 3.3ns or 2.5ns or 1.875ns or 1.25ns). This result is tCK(avg)max corresponding to CL selected.
4. Reserved’ settings are not allowed. User must program a different value.
5. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1333
Speed Bins which is not subject to production tests but verified by design/characterization.
6. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1600
Speed Bins which is not subject to production tests but verified by design/characterization.
7. tREFI depends on operating case temperature (TC).
8. For devices supporting optional down binning to CL = 7 and CL = 9, tAA/tRCD/tRP(min) must be 13.125 ns or lower. SPD
settings must be programmed to match.
9. DDR3-800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.
24
4G Bits DDR3L SDRAM
3. Package Drawing
3.1
78-ball FBGA
3.2
Solder ball: Lead free (Sn-Ag-Cu)
25
4G Bit DDR3L SDRAM
3.2
96-ball FBGA
Solder ball: Lead free (Sn-Ag-Cu)
26
4G Bits DDR3L SDRAM
4.
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the 4G bits DDR3 SDRAM.
Type of Surface Mount Device
P3P4GF2BLF, P3P4GF3BLF:78-ball FBGA < Lead free (Sn-Ag-Cu) >
P3P4GF4BLF:96-ball FBGA < Lead free (Sn-Ag-Cu) >
27
4G Bits DDR3L SDRAM
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
28
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