ADSP-21161 SHARC DSP Hardware Reference

ADSP-21161 SHARC DSP Hardware Reference
8 SDRAM INTERFACE
Figure 8-0.
Table 8-0.
Listing 8-0.
Overview
The ADSP-21161 processor's synchronous DRAM (SDRAM) interface
enables it to transfer data at either the core clock frequency or one-half the
core clock frequency. The synchronous approach, coupled with the ability
to transfer data at the core clock frequency, supports data transfer at a
high throughput—up to 400 Mbytes/second for a 32-bit bus width, and
600 Mbytes/second for 48-bit bus width.
All inputs are sampled and all outputs are valid on the rising edge of the
clock SDCLK. The SDRAM’s flexible interface allows you to connect
SDRAMs to any one or more of the four external memory banks of the
ADSP-21161 or to all four banks simultaneously.
The ADSP-21161 processor's SDRAM controller provides a glueless
interface with standard SDRAMs. It supports:
• SDRAMs of 16 Mbits, 64 Mbits, 128 Mbits, and 256 Mbits with
configurations 4-bit, 8-bit, 16-bit and 32-bit wide devices
• Additional buffers between ADSP-21161 and SDRAM
• Zero wait state, 100 Mwords/second with some access types
• Up to 254.68 Mwords [3x(64M) + 62.68M] of SDRAM in external
memory
• SDRAM page sizes of 2048, 1024, 512, and 256 words
ADSP-21161 SHARC DSP Hardware Reference
8-1
Overview
• A programmable refresh counter to coordinate between varying
clock frequencies and the SDRAM's required refresh rate
• Buffering for multiple SDRAMs connected in parallel
• Shared SDRAM devices in a multiprocessing system
• A separate A10 pin that enables applications to precharge SDRAM
before issuing a refresh command
• Connection to up to four external memory banks (0 to 3) of the
ADSP-21161
• Self-refresh, low-power mode
• Two power-up options
The following are definitions used throughout this chapter:
• Bank Activate command. Activates the selected bank and latches in
a new row address. It must be applied before a read or write command.
• Burst length. Determines the number of words that the SDRAM
inputs or outputs after detecting a write or read command, respectively.
The processor supports burst length ONE mode only.
During a burst length one cycle, the ADSP-21161 SDRAM controller applies the command every cycle and keeps accessing the data.
See also, page size on page 8-3.
• Burst type. Determines the order in which the SDRAM delivers or
stores burst data after detecting a read or write command, respectively.
The processor supports sequential accesses only.
8-2
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
• CAS latency. The delay, in clock cycles, between when the SDRAM
detects the read command and when it provides the data at its output pins.
The speed grade of the device and the application's clock frequency
determine the value of the CAS latency.
The application must program the CAS latency value into the SDCTL
register after power up.
• CBR Automatic Refresh (CAS before RAS) mode. In this mode,
the SDRAM drives its own refresh cycle with no external control
input. At cycle end, all SDRAM banks are precharged (idle).
• DQM Data I/O Mask function. This signal is asserted during a precharge command or when a burst stop command interrupts a burst
write. When asserted during a write cycle, this signal interrupts and
disables the write operation immediately.
• SDCTL Register. IOP register that contains programmable
SDRAM control and configuration parameters that support different vendor's timing and power-up sequence requirements.
• Mode Register. The SDRAM's configuration register that contains
user-defined parameters corresponding to the processor's SDCTL register. After initial power-up and before executing a read or write
command, the application must program the MODE register.
• Page Size. The size, in words, of the SDRAM's page. The processor
supports 2048-, 1024-, 512-, and 256-word page sizes.
Page size is a programmable option in the SDCTL register.
• Precharge Command. Precharges an active bank.
ADSP-21161 SHARC DSP Hardware Reference
8-3
Overview
• SDRDIV Programmable Refresh Counter. An IOP register containing a refresh counter value. The clock supplied to the SDRAM
can vary between 20 and 100 MHz. This counter enables applications to coordinate CLK rate with the SDRAM's required refresh
rate.
• Self-Refresh. The SDRAM's internal timer initiates automatic
refresh cycles periodically, without external control input. This
command places the SDRAM device in a low-power mode.
Self-refresh is a programmable option in the SDCTL register.
• tRAS. Active Command time. Required delay between issuing an
activate command and issuing a precharge command. A vendor-specific value.
This option is programmable in the SDCTL register.
• tRC. Bank Cycle time. The required delay between successive Bank
Activate commands to the same bank. This vendor-specific value is
defined as follows:
tRC
= tRP + tRAS.
The processor fixes the value of this parameter, so it is a non-programmable option.
• tRCD. RAS to CAS delay. The required delay between a ACT command
and the start of the first read or write operation. This vendor-specific value is programmable in SDCTL.
• tRP. Precharge time. Required delay between issuing a precharge
command and issuing an activate command. This vendor-specific
value is programmable in SDCTL.
Figure 8-1 shows the SDRAM controller's interface between the internal
SHARC core and the external SDRAM device.
8-4
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
The DSP normally generates an external memory address, which then
asserts the corresponding MSx select, along with RD and WR strobes. These
control signals are intercepted by the SDRAM controller. The memory
access to SDRAM is based on the mapping of the addresses and memory
selects. The configuration is programmed in the SDCTL register. The
SDRAM controller can hold off the DSP core or I/O processor with an
internally connected acknowledge signal (ACK), as determined by refresh,
nonsequential access, or page miss latency overhead.
The SDRAM controller provides a glueless interconnection between the
SDRAM control, address, and data pins and the DSP's internal Harvard
Architecture busses. The internal 32-bit address bus is multiplexed by the
SDRAM controller to generate the corresponding chip select, row address,
column address, and bank select signals to the SDRAM.
ADS P-21161
C C LK or 1 /2 C C LK
S D C LK
C LK
RD
S D C KE
CKE
WR
RAS
RAS
RESET
CAS
CAS
AC K
SDWE
WE
D QM
D QM
21 161
CORE
S D A1 0
MSx
D 4 7 :1 6 *
C ontro ller
MSX
A1 3 /A1 4
A2 3 :0
MUX
A1 0
CS
D Q 3 1 :0
B u ffer
A2 3 :0
A2 3 :0
S
D
R
A
M
(JE D E C )
B A0 /B A1
A1 2 :0
D 4 7 :1 6
Figure 8-1. SDRAM Controller Interface*
ADSP-21161 SHARC DSP Hardware Reference
8-5
Overview
Figure 8-2 on page 8-7 shows a block diagram of the ADSP-21161 processor's SDRAM interface to four 8-bit SDRAMs. In this single processor
example, the SDRAM interface connects to four 1M x 8 x2 (2M x 8)
SDRAM devices to use 2M of 32-bit words. The same address and control
bus communicates to all four SDRAM devices. The following connections
are made:
•
SDCKE
connects to the CKE of the SDRAM devices
•
SDCLK0
•
SDWE
•
MSx
SDRAM clock connects to the CLK pins,
connects to all WE
pin connects to all chip selects (CS)
• All CAS, RAS, and DQM signals are connected together between the
DSP and all of the SDRAM devices
Notice that the data bus shows the processor's default bus width,
DATA[47:16]. For full non-packed instruction execution mode, the data
bus can be extended to DATA[47:0] with the use of available disabled link
port data pins. The A[10] pin of all SDRAM devices are connected to a
separate SDA10 pin on the processor to allow the SDRAM controller to
retain control of all SDRAMs for any non-SDRAM accesses during host
bus requests.
*
8-6
In full instruction with/no pack mode, the data bus extends to 48 bits, D47:00.
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
SDWE
CAS
RAS
MSx
WE
CAS
RAS
CS
A [14]
SDA10
A(9:0)
SDCKE
SDCLK0
DQM
A11[BS]
A[10]
A(9:0)
CKE
CLK
DQM
SDRAM #1
2M x 8
DQ[7:0]
SDRAM #2
2M x 8
DQ[7:0]
A11[BS]
A[10]
A[9:0]
CKE
CLK
DQM
DATA
DATA[47:16]
DATA
[23:16]
WE
CAS
RAS
CS
DATA [31:24]
[47:16]
DATA [31-0]
AD SP-21161
LCHH
WE
CAS
RAS
CS
A11[BS]
A[10]
A(9:0)
CKE
CLK
DQM
WE
CAS
RAS
CS
SDRAM #3
2M x 8
DQ[7:0]
DATA
[39:32]
SDRAM #4
DATA [47:40]
2M x 8
DQ[7:0]
A11[BS]
A[10]
A[9:0[
CKE
CLK
DQM
Figure 8-2. ADSP-21161 Processor's Block Diagram
ADSP-21161 SHARC DSP Hardware Reference
8-7
SDRAM Pin Connections
SDRAM Pin Connections
Table 8-1 describes the ADSP-21161 SDRAM controller pins and the
connections for each pin. The pins are defined as Input (I), Output (O),
Synchronous (S), or High Impedance (T).
Table 8-1. SDRAM Pin Connections by Type
Pin
Type
Description
CAS
I/0/T
SDRAM Column Address Select pin. Connect to SDRAM's CAS buffer
pin.
DQM
I/0/T
SDRAM Data Mask pin. Connect to SDRAM's DQM buffer pin.
MSx
I/0/T
Memory select pin of external memory bank configured for SDRAM.
Connect to SDRAM's CS (Chip Select) pin.
RAS
I/0/T
SDRAM Row Address Select pin. Connect to SDRAM's RAS pin.
SDA10
0/T
SDRAM A10 pin. SDRAM interface uses this pin to retain control of the
SDRAM device during host bus requests. Connect to SDRAM's A10
pin.
SDCKE
I/0/T
SDRAM Clock Enable pin. Connect to SDRAM's CKE (Clock Enable)
pin.
SDCLK0
I/0/S/T
SDRAM SDCLKO output pin. Connect to the SDRAM's CLK pin.
SDCLK1
0/S/T
SDRAM SDCLK1 output pin. Connect to the SDRAM's CLK pin.
SDWE
I/0/T
SDRAM Write Enable pin. Connect to SDRAM's WE or W buffer pin.
8-8
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
SDRAM Timing Specifications
To support key timing requirements and power up sequences for different
SDRAM vendors, the ADSP-21161 provides programmability for tRAS,
tRP, tRCD, and a power up sequence mode.
The CAS latency should be programmed in the SDCTL register based on the
frequency of the operation. Refer to the SDRAM data sheet of the vendor
for more details.
For other parameters, the controller assumes:
Bank Cycle Time, tRC =
tRAS
+ tRP
SDRAM Control Register (SDCTL)
SDRAMs are available from several vendors, including IBM, Micron Electronics, Toshiba, Samsung Electronics, and NEC. Each vendor has
different SDRAM product requirements for the power-up sequence and
the timing parameters -tRAS (ACT to PRE command delay), tRCD and tRP ( PRE
to ACT command delay). Use only SDRAMS that comply with Joint Electronic Device Engineering Council (JEDEC) specifications. In order to
support multiple vendors, the ADSP-21161 SDCTL register can be programmed to meet these requirements. The SDCTL register is an I/O
processor register which does not support bitwise operations.
Figure 8-3 shows the SDRAM control register. Table A-22 on page A-85
provides bit descriptions.
ADSP-21161 SHARC DSP Hardware Reference
8-9
SDRAM Configuration for Runtime
S D C TL
(0x00B8)
31 30 29 28 27 26 25 24
23 22 21 20
0
0
0
0
0
0
0
0
0
0
0
0
19 18 17 16
0
0
0
0
SDEM 0
Ext m em Bank0
SD R AM enable
SD TR C D
SD R AM tR C D spec
R AS to C AS dela y
[# of SD C LK cycles: 1 to 7 cycles]
SDEM 1
Ext m em Bank1
SD R AM enable
SDBU F
Pipelining option with external reg buffer
[1 = ext SD R AM ctl /addr buffer enable
0 = no buffe r option]
SDEM 2
Ext m em Bank2
SD R AM enable
SD CKR
SD C LK -to-C C LK ratio
0=H alf C CLK (core clock) freq. (1:2)
1=C CLK C ore clock freq. (1:1)
SDEM 3
Ext m em Bank 3
SD R AM enable
SDBN
SD R AM # of SD R AM device m em banks
0=2 banks, 1=4 banks
15 14
0
0
13 12
0
0
11 10
9
8
7
6
0
0
0
0
0
0
5
0
4
0
3
0
2
0
1
0
0
0
SD SRF
SD R AM self re fresh
comm and enable
SD PSS
SD R AM P ower- up
sequence
SDPGS
SD R AM Page Size
00=256 words
01=512 words
10=1k words
11=2k words
SDPM
SD R AM P ower- up m ode
0 = prechg, 8 C BR refs., m ode reg. set
1 = prechg, m ode reg. set, 8 C BR refs.
SDC L
SD R AM C AS Latency spec
01=1 cycle, 10=2 cycles, 11=3 cycles
D SD C TL
D isable S DC LK0 &C ontrol Signals
1=D isable SD C LK0, R AS~, C A S~ & SD C LKE
0=Activate S DC LK0, RAS~, C AS~ & SD C LKE
DSDC K1
SD C LK1 D isable
1 = disable SD C LK1, 0=SD C LK active
SD TR AS
SD R AM tR A S spec
Activ e C om m and D elay
[# of SD C LK cycle s: 0 to 15 cycle s]
SDTRP
SD R AM tR P spec
Precharge D elay
[# of SD C LK cycles: 1 to 7 cycles]
Figure 8-3. SDCTL Register Definition
SDRAM Configuration for Runtime
The ADSP-21161 supports 16Mbits, 64Mbits, 128Mbits, and 256Mbits
SDRAM devices with 4-bit, 8-bit, 16-bit, and 32-bit configurations. Page
sizes of 256, 512, 1024, and 2048 words are supported in the available the
densities and configurations mentioned above. Each external memory
bank has address space of 64 Mwords for SDRAMs.
8-10
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
The SDCTL register of the ADSP-21161 stores the configuration information of the SDRAM interface. Writing configuration parameters initiates
commands to the SDRAM that take effect immediately.
Before starting the SDRAM powerup sequence, complete the following
steps:
1. Write to the WAIT register to set the waitstates to zero (EBxWS=000)
for each bank that will have SDRAM mapped to it.
2. Write all of the SDRAM configuration parameter values to the
SDCTL register.
3. Set the SDRDIV register at initial power-up. In the SDRDIV register, a
memory-mapped IOP register, configure the value for the SDRAM
refresh counter can be configured.
In the SDCTL register, set the parameter bits as follows:
• Set the SDRAM clock enables (DSDCTL and DSDCK1).
• Select the number of banks that the SDRAM contains (SDBN).
• Select the external memory banks configured for and connected to
an SDRAM (SDEMx).
• Set the SDRAM buffering option (SDBUF).
• Select the CAS latency value (SDCL).
• Select the SDRAM page size (SDPGS).
• Select the SDRAM power-up mode (SDPM).
• Start the SDRAM power-up sequence (SDPSS).
• Start SDRAM self-refresh mode (SDSRF).
• Set the Active Command Delay (SDTRAS).
ADSP-21161 SHARC DSP Hardware Reference
8-11
SDRAM Configuration for Runtime
• Set the precharge delay (SDTRP).
• Set the RAS-to-CAS delay (SDTRCD).
• Set the SDCLK to Core Clock Ratio (SDCKR).
In systems where several SDRAM devices are connected in parallel, buffering may be required to meet overall system timing requirements. The
ADSP-21161 supports the pipelining of the address and control signals to
enable buffering between ADSP-21161 and SDRAM. The pipeline bit
(SDBUF) in the SDCTL register enables this mode. When this bit is set, the
data for write accesses are delayed by one cycle, allowing the address and
controls to be externally latched. In read accesses, data is sampled by
ADSP-21161 one cycle later. To support the higher clock load requirements, two SDCLK pins are provided to eliminate the need for off-chip
clock buffers. An option is provided in the SDCTL register (bits 2 and 3) to
allow the SDRAM controller to three-state one or both the SDCLK pins.
The SDCKR bit in the control register can be used to set the SDCLK to core
clock ratio. The interface can run at full core clock frequency or at half the
core clock frequency, depending upon the setting for this bit.
Setting the Refresh Counter Value (SDRDIV)
Since the clock supplied to the SDRAM can vary between 20 MHz and
100MHz, the processor provides a programmable refresh counter (SDRDIV)
to coordinate the supplied clock rate with the SDRAM device's required
refresh rate.
Write to SDRDIV the delay, in a number of clock cycles, that must occur
between consecutive refresh commands.
the delay value to the
! Write
SDRAM parameter values to the
SDRDIV
register before writing the
register.
SDCTL
To calculate the value of the refresh counter for which to program the
SDRDIV register, use the equation shown in Figure 8-4.
8-12
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
S D R D IV
31 30 29 28 27 26 25 24
23 22 21 20
19 18 17 16
0xB9
15 14 13 12
S D R D IV =
11 10
9
8
7
6
5
f C CLK
S D R A M refres h rate cycle
4
3
2
CL
1
0
tR P
5
Figure 8-4. SDRDIV Register and Calculation
is 1x CCLK or 2x CCLK, as determined by the SDCKR bit and SDCTL
register.
SDCLK
Where:
f CCLK = CLKCFG × f CLKOUT
CL = CAS latency programmed into the SDCTL register
tRP = tRP specification programmed in the SDCTL register
CLK_CFG = 2 for 2:1 CCLK-to- CLKOUT clock ratio
= 3 for 3:1 CCLK-to-CLKOUT clock ratio
= 4 for 4:1 CCLK-to-CLKOUT clock ratio
is defined as the internal core-clock frequency. CLKOUT is 1xCLKIN or
2xCLKIN, depending on whether CLKDBL is tied high or low during RESET.
The signals SDCLK0 and SDCLK1 can operate at either 1xCCLK or 1/2 CCLK, as
determined by the SDCKR in the SDCTL register.
CCLK
For example, for an IBM SDRAM with:
Reference rate = 4096 cycles/64ms
CLKIN
= 25 MHz
CLKDBL
enabled
ADSP-21161 SHARC DSP Hardware Reference
8-13
SDRAM Configuration for Runtime
Therefore, CLKOUT = 50 MHz
CLK_CFG
= 2, for 2:1 PLL ratio
=2
CL
tRP
=2
The equation yields:
50x10 6
SDRDIV = 2x ----------------------------------- – 2 – 2 – 5 = 1554 ( decimal ) = 0x612
s
4096 --------------------64x10 – 3
Setting the SDRAM Clock Enables
Systems with several SDRAM devices connected in parallel require buffering between the processor and multiple SDRAM devices to reduce
capacitive loading. Buffering, however, may also generate increased clock
loads.
To meet higher clock load requirements, the processor provides two
SDRAM clock control pins, SDCLK0 and SDCLK1. These pins eliminate the
need for off-chip clock buffers.
The DSDCTL and DSDCK1 in the SDCTL register provide control for the
SDRAM clock control pins. The DSDCTL bit, if set (=1), enables high
impedance for all of the SDRAM control pins (DQM, CAS, RAS, SDWE, and
SDCKE) and the SDCLK0 pin. The DSDCTL bit, if cleared (=0), disables all
SDRAM control pins.
The DSDCK1 bit, if set (=1), enables the SDCLK1 pin and places it into a high
impedance state only. The DSDCK1 bit, if cleared (=0), disables SDCLK1.
If your system does not use SDRAM, set both DSDCTL and DSDCK1 to 1.
8-14
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
If your system uses SDRAM, but the clock load is minimal, set DSDCTL to
0 and DSDCK1 to 1 This setting enables the SDCLK0 pin and all related
SDRAM control pins, but disables the second clock pin SDCLK1.
If your system uses SDRAM and has a heavy clock load such as a system
using registered buffers and eight 4-bit SDRAMs to get 32-bit data, set
both DSDCTL and DSDCK1 to 0. This setting enables SDCLK0, SDCLK1, and all
SDRAM control pins. In this configuration, SDCLK0 and SDCLK1 can each
share half of the clock load.
Setting the Number of SDRAM Banks (SDBN)
The SDBN bit defines the number of banks in the SDRAM device. The
SDRAM controller uses this value and the value assigned to the SDPGS
(page size) bit to map the address bits on the processor's internal 32-bit
address (DMA/PMA/EPA) bus into SDRAM column address, row
address, and bank select address. The SDBN bits in the SDCTL register select
the number of banks the SDRAM as follows: 0 = 2 banks, 1 = 4 banks.
Setting the External Memory Bank (SDEMx)
The SDCTL register can be programmed to select the external memory
banks that have SDRAM devices by using the SDEMx bits. For example, if
external memory banks 1 and 3 have SDRAMs, SDEM1 and SDEM3 bits are
written with 1. However the controller tracks only the previously accessed
page/bank.
When using SDRAM, connect its CS line to any of the processor's external
memory banks MS3-0. In the SDCTL register, configure that bank for
SDRAM operation.
a zero (0) wait state for the external memory bank to which
! Program
to 000 in the
registhe SDRAM device maps by setting
EBxWS
WAIT
ter.
ADSP-21161 SHARC DSP Hardware Reference
8-15
SDRAM Configuration for Runtime
not use external handshake mode DMA on the external memory
! Do
bank mapped to an SDRAM device.
The SDEMx bits in the SDCTL register configure the processor's external
memory banks for SDRAM operation as follows:
SDEM [0-3] = 0000
bits 16-19, No SDRAM enabled
SDEM0 = 1
Bank 0 SDRAM Enable
SDEM1 = 1
Bank 1 SDRAM Enable
SDEM2 = 1
Bank 2 SDRAM Enable
SDEM3 = 1
Bank 3 SDRAM Enable
Setting the SDRAM Buffering Option (SDBUF)
Systems that use several SDRAM devices connected in parallel may
require buffering between the processor and multiple SDRAM devices in
order to meet overall system timing requirements.
To meet such timing requirements and enable intermediary buffering, the
processor supports pipelining of SDRAM address and control signals.
The pipeline bit SDBUF (bit 23) in the SDCTL register enables this mode:
SDBUF = 0
Disable pipelining
SDBUF = 1
Enable pipelining
When SDBUF is set (=1), the SDRAM controller delays the data in write
accesses by one cycle, enabling the processor to latch the address and controls externally. In read accesses, the SDRAM controller samples data one
cycle later.
Figure 8-5 on page 8-17 shows another single processor example in which
the SDRAM interface connects to multiple banks of SDRAM to provide
512M of SDRAM a in 4-bit I/O configurations. This configuration
8-16
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
results in 16M x 32-bit words. In this example, OxA and OxB output from
the registered buffers are the same signal, but are buffered separately. In
the registered buffers, a delay of one clock cycle occurs between the input
(Ix) and its corresponding output (OxA or OxB).
Addr [14]
Ctrl [6]
D Q 20 SDRAM Bank 1
Addr & Ctrl
D Q
ADSP-21161
C
O
N
T
R
O
L
O0A
CAS
I1
I2
O1A
DQM
SDCKE
I3
O3A
I4
O4A
MS3
I5
O5A
SDWE
A[9:0]
Ix[13:0] Oxa[13:0]
SDRAM #1
4M x 4 x 4
DATA [3:0]
[3:0]
RAS SDRAM #2
4M x 4 x 4
CAS
WE
DQM
O2A
A[13:11]
CS
A[13:0]
CKE
Registered
Buffers
I0
CS
A[13:0]
CAS
WE
DQM
20 SDRAM Bank 2
Addr & Ctrl
RAS
CLK
RAS SDRAM #5
4M x 4 x 4
CAS
WE
DQM
[19:16]
DATA [3:0]
CKE
CLK
RAS
DATA [3:0]
RAS SDRAM #6
4M x 4 x 4
[7:4]
CAS
WE
DQM
DATA [3:0]
CKE
CLK
CKE
CLK
CS
A[13:0]
CS
A[13:0]
[23:20]
Aa[13:0]
SDA10
O0B
O1B
O2B
CAS
WE
O4B
DQM
O5B
Ab[13:0]
Oxb[13:0]
SDCLK0
RAS
O3B
CKE
SDRAM #3
4M x 4 x 4
DATA [3:0]
[11:8]
RAS
CAS
WE
DQM
SDRAM #7
4M x 4 x 4
DATA [3:0]
[27:24]
CKE
CLK
CLK
CS
A[13:0]
Ab[13:0]
CS
A[13:0]
SDCLK1
RAS SDRAM #4
4M x 4 x 4
CLK
RAS SDRAM #8
4M x 4 x 4
CAS
WE
DQM
[31:28]
DATA [3:0]
CKE
CLK
CS
A[13:0]
CS
A[13:0]
CAS
WE
DATA[31-0]
DQM
CKE
DATA [3:0]
[15:12]
Figure 8-5. Uniprocessor System With Multiple SDRAM Devices
Selecting the CAS Latency Value (SDCL)
The CAS latency value defines the delay, in number of clock cycles,
between the time that the SDRAM detects the read command and the
time that it provides the data at its output pins. This parameter facilitates
ADSP-21161 SHARC DSP Hardware Reference
8-17
SDRAM Configuration for Runtime
matching the SDRAM operation with the processor's ability to latch the
data output.
CAS latency does not apply to write cycles.
The SDCL bits in the SDCTL register select the CAS latency value as follows:
01 = 1 clock cycle, 10 = 2 clock cycles and 11= 3 clock cycles.
Generally, the frequency of the operation determines the value of the CAS
latency. For more details, see the SDRAM device documentation.
Selecting the SDRAM's Page Size (SDPGS)
The processor's SDRAM controller SDPGS bit defines for the page size, in
number of words, of the SDRAM's banks. The SDRAM controller uses
this value and the value assigned to the SDBN (number of banks) bit to map
the address bits on the processor's internal 32-bit address
(DMA/PMA/EPA) bus into SDRAM column address, row address, and
bank select address.
Page length depends on the I/O organization and column addressing of
the SDRAM's internal banks. For example, a 16 Mbits SDRAM organized
as 2 M x 4 I/O x 2 banks has a page size of 1024 words.
The SDPGS bits (bits 12 and 13) in the SDCTL register select the SDRAM
page length: 00= 256 words, 01 = 512 words, 10= 1024 words and 11 =
2048 words.
Setting the SDRAM Power-Up Mode (SDPM)
To avoid unpredictable start-up modes, SDRAM devices must follow a
specific initialization sequence during power up. The processor provides
two commonly used power-up options.
The SDPM bit (bit 11) in the SDCTL register selects the SDRAM power-up
mode. When the SDPM bit is cleared (=0), the SDRAM controller sequen-
8-18
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
tially issues: a PRE command, eight CBR refresh cycles, and an MRS (Mode
Register Set) command. When the SDPM bit is set (=1), the SDRAM controller issues, in this order: a PRE command, an MRS (Mode Register Set)
command, and eight CBR refresh cycles.
For details, see the SDRAM device documentation.
Starting the SDRAM Power-Up Sequence (SDPSS)
Before starting the power-up sequence, write to the SDCTL register to configure the SDRAM parameters. Be sure to write to all the register bits,
regardless of the number of parameter values that will not change.
To start the SDRAM power-up sequence, write 1 to the SDPSS bit (bit 14)
in the SDCTL register. The SDPSS bit always reads as zero (0). The initialization sequence executed during power-up depends on the value of the SDPM
bit.
the
register before the DSP starts the SDRAM
! Initialize
power-up sequence. After power up, make sure that the DSP waits
SDRDIV
one cycle before writing the SDCTL register to issue another SDRAM
command.
For more details, see the SDRAM device documentation.
Starting Self-Refresh mode (SDSRF)
The processor supports SDRAM self-refresh mode. In self-refresh mode,
the SDRAM performs refresh operations internally, without external control, which reduces the SDRAM's power consumption.
The SDSRF bit (bit 15) in the SDCTL register enables and disables the
self-refresh option:
SDSRF = 0
Disable self-refresh mode.
SDSRF = 1
Enable self-refresh mode.
ADSP-21161 SHARC DSP Hardware Reference
8-19
SDRAM Configuration for Runtime
When SDSRF is set (=1), the processor's SDRAM controller issues a SREF
command to the SDRAM device or devices, putting them into self-refresh
mode immediately. For details, see “Self Refresh Command (SREF)” on
page 8-41.
Selecting the Active Command Delay (SDTRAS)
The tRAS value (Active Command Delay) defines the required delay, in
number of clock cycles, between the time the SDRAM controller issues an
ACT command and the time it issues a PRE command.
The SDTRAS bits (bits 4, 5, 6, and 7) in the SDCTL register select the tRAS
value. For example:
SDTRAS=0001
SDTRAS=0010
SDTRAS=0111
SDTRAS=1111
1 clock cycle
2 clock cycles
7 clock cycles
15 clock cycles
For more details, see the SDRAM device documentation.
Selecting the Precharge Delay (SDTRP)
The tRP value (precharge delay) defines the required delay, in number of
clock cycles, between the time the SDRAM controller issues a PRE command and the time it issues an ACT command.
The SDTRP bits (bits 8, 9, and 10) in the SDCTL register select the tRP value.
For example:
SDTRP = 001
SDTRP = 010
SDTRP = 111
8-20
1 clock cycle
2 clock cycles
7 clock cycles
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
Selecting the RAS-to-CAS Delay (SDTRCD)
The vendor-specific SDRAM value tRCD defines the required delay in number of clock cycles between an ACT command and the start of the first read
or write operation. The SDTRCD[2:0] bits in the SDCTL register select the
tRCD (RAS to CAS delay) value as follows: 001= 1 clock cycle, 010= 2 clock
cycles, and 111= 7 clock cycles. For more details, see the SDRAM device
documentation.
,
! clock ,or SDRAM
and CL settings represent the number of core
CLK cycles.
SDTRP SDTRAS SDTRCD
ADSP-21161 SHARC DSP Hardware Reference
8-21
SDRAM Controller Standard Operation
SDRAM Controller Standard Operation
The ADSP-21161 SDRAM controller uses a burst length one for page
read/write operations. Burst length determines the maximum number of
column locations that can be accessed for a given read or write operation.
ADSP-21161 supports burst length one mode. This does not
! The
have an adverse impact on the throughput as compared to burst
lengths of 2, 4, 8 and full page. Instead of applying the first address
and continuing access to data on successive clocks (during which the
controller drives the NOP command), the ADSP-21161 SDRAM
controller applies the command at every cycle continuously accessing the data.
Table 8-3 on page 8-10 lists the data throughput rates for the processor's
core or DMA read/write accesses to SDRAM. All SDRAM clock cycles
assume core clock (CCLK) operation. The following parameters are from a
typical SDRAM manufacturer’s data sheet:
• CAS latency = 2 cycles (SDCL=2)
• No SDRAM buffering (SDBUF=0)
• Precharge (tRP) = 2 cycles ( SDTRP=2)
• Active command time (tRAS) = 3 cycles (SDTRAS=3).
•
8-22
tRCD
= 2 cycles
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
Table 8-2. Throughput for Core or DMA Read/Write Operations
Accesses
Operations
Page
Throughput per CCLK
(32-bit words)1 2
Sequential,
uninterrupted
Read
Same
1 word/1 cycle
Sequential,
uninterrupted
Write
Same
1 word/1 cycle
Nonsequential,
Uninterrupted
Read
Same
1 word/5 cycles
Nonsequential,
Uninterrupted
Write
Same
1 word/1 cycle
Both
Alternating
read/write
Same
Average rate = 3 cycles per word
Reads
Different
Nonsequential
(CL + 3)
(reads = 5 cycles, writes = 1 cycle)
1 word/10 cycles
(tRP + CL + tRCD + 4)
Nonsequential
Writes
Different
1 word/7 cycles
(tRP + tRCD + 3)
Auto refresh
before read
Reads
Auto refresh
before write
Writes
Different
1 word/15 cycles
(2tRP + tRAS + CL + t RCD + 4)
Different
1 word/11 cycles
(2tRP + tRAS + tRCD + 2)
1 When executing 48-bit packed instructions from 32-, 16-, or 8-bit SDRAM memories:
- Add one clock cycle to the throughput value or to the average access rate for 32-bit wide SDRAM
- Add three clock cycles to the throughput value or to the average access rate for 16-bit wide SDRAM
- Add six clock cycles to the throughput value or to the average access rate for 8-bit wide SDRAM
2 With SDRAM buffering enabled (SBUF=1), replace any instance of (CL) with (CL + 1).
ADSP-21161 SHARC DSP Hardware Reference
8-23
SDRAM Controller Standard Operation
Understanding DAG and DMA Operation
For either core-driven accesses via the DAGs or DMA data transfers to
and from SDRAM, one full page can be accessed at full throughput if the
data address generator or external address incrementer is equal to one. If
the modify register or external address register is greater than a value of 1,
then one full page can be written at full throughput, but reads increase the
amount of processing time required.
Whenever a page miss happens, the SDRAM controller executes a PRE
command followed by a bank activate command before executing a
read/write command. For SDRAM reads, a latency (equal to CAS latency)
exists from the start of the read command until data is available from the
SDRAM. For the first read in a sequence of reads, the latency will always
exist. Subsequent reads will not have latency if the address is sequential
and uninterrupted.
A refresh access to SDRAM always aligns to the CLKIN rising edge. So,
interrupted access to SDRAM incur the overhead of additional cycles,
depending on the CLK CFG setting. For example, WRT - NOP -WRT - NOP WRT will have a 6-cycle overhead for CLK-CFG - 4:1 and SDCKR=1. Every
write in the above sequence starts at the rising edge of CLKIN, and two core
cycles transpire in every CLKIN. The last WRT completes in the first core
cycle of the third CLKIN cycle (which is the ninth core cycle). If the three
writes had been consecutive, the third write would be over by the third
core cycle of the first CLKIN. As a result, the writes complete six core clock
cycles later.
Programmable refresh counter provides that can be used to set up a count,
depending on the required refresh rate and the clock rate used. The refresh
count is specified in the SDRDIV, a memory mapped IOP register. For more
information on SDRDIV, see “Setting the Refresh Counter Value
(SDRDIV)” on page 8-12.
8-24
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
Multiprocessing Operation
In a multiprocessing environment, the SDRAM is shared among two or
more ADSP-21161s. SDRAM input signals (including clock) are always
driven by the bus master. The slave processors track the commands that
the master processor issues to the SDRAM. This feature or function helps
to synchronize the SDRAM refresh counters and to prevent needless
refreshing operations.
B R 2 -1
BRST
ACK
PA
ID = 0 0 1
A D S P -2 1 1 6 1
1
0
A D S P -2 1 1 6 1
SD RA M
ID 1
1
0
ID = 0 1 0
ID 2
BMSTR
BMSTR
SD R A M
EP
SD R A M
C O N TR O LLER
C O N TR O LLER
C lo c
kR
E
S D R A M C o n tr o l
EP
A D D R 2 3 :0
D A T A 4 7 :1 6
Figure 8-6. Multiprocessing: Dual Processor System Example
Whenever a ADSP-21161 needs to transfer the bus mastership to the
other ADSP-21161, it transfers the bus after meeting (tRAS min - 1) the
number of cycles for the presently active row. When a ADSP-21161
receives the bus mastership, it executes a PRE command prior to the first
access to SDRAM. In the user application code, the SDCTL and SDRDIV registers of both ADSP-21161s must be initialized to the same value. If there
is no SDRAM used in the system (as indicated in SDCTL), then the bus
transition process is the same as in the ADSP-21160.
ADSP-21161 SHARC DSP Hardware Reference
8-25
SDRAM Controller Standard Operation
Accessing SDRAM
To access SDRAM, the SDRAM controller multiplexes the internal 32-bit
non-multiplexed address into a row address, a column address, and a bank
select address for the SDRAM device, as shown in Figure 8-7 below.
Lower bits are mapped into the column, next bit/bits are mapped into the
bank select, and remaining bits are mapped into the row. This mapping is
based on the page size and the number of banks in SDRAM (entered into
the SDCTL register).
27 26 25
Ext. Memory
Bank Select
00 = MS0~
01 = MS1~
10 = MS2~
11 = MS2~
0
Row
Addr.
SDRAM
Bank
Select
Column
Addr.
Figure 8-7. Multiplexed 32-bit SDRAM address
Based on the values programmed in the SDCTL register for page size and
number of SDRAM banks, the SDRAM controller maps bits as follows:
• the lower ADDR bits into the column address
• the next bit or bits into the bank select address
• the remaining higher order bits into the row address
The following tables show how the SDRAM controller maps the SDRAM
address bits on the processor's internal address bus to its external address
pins that connect to the SDRAM. The internal and external address bus
pins in the tables are defined as follows:
EA
IA
8-26
= External address pins
= Internal address bus
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
16M SDRAMs,
is the Bank Select pin. When using a 16M
! For
SDRAM, connect the processor's
pin to the SDRAM's
pin.
A11
A14
A11
Tables: ADSP-21161 Address Mapping for SDRAM
Table 8-3. SDRAM Size = 16 Mbit
16 Mbit SDRAM
(Page Size x No.
of Banks)
Column Address
(Page Access)
Bank Select
Row Address
(Bank Activate)
256 x 2
IA[7:0]=>EA[7:0]
IA[8]=>EA[14]
IA[19:9]=>EA[10:0]
512 x 2
IA[8:0]=>EA[8:0]
IA[9]=>EA[14]
IA[20:10]=>EA[10:0]
1024 x 2
IA[9:0] =>EA[9:0]
IA[10]=>EA[14]
IA[21:11]=>EA[10:0]
Table 8-4. SDRAM Size = 64 Mbit
64 Mbit SDRAM
(Page Size x No.
of Banks)
Column Address
Bank Select
Row Address
256 x 2
IA[7:0]=> EA[7:0]
IA[8] =>EA[14]
IA[21:9]=>EA[12:0]
512 x 2
IA[8:0]=>EA[8:0]
IA[9]=>EA[14]
IA[22:10]=>EA[12:0]
1024 x 2
IA[9:0]=>EA[9:0]
IA[10]=>EA[14]
IA[23:11]=>EA[12:0]
256 x 4
IA[7:0]=>EA[7:0]
IA[9:8]=>EA[14:13]
IA[21:10]=>EA[11:0]
512 x 4
IA[8:0]=>EA[8:0]
IA[10:9]=>EA[14:13]
IA[22:11]=>EA[11:0]
1024 x 4
IA[9:0]=>EA[9:0]
IA[11:10]=>EA[14:13]
IA[23:12]=>EA[11:0]
ADSP-21161 SHARC DSP Hardware Reference
8-27
SDRAM Controller Standard Operation
Table 8-5. SDRAM Size = 128 Mbits
128 Mbit
SDRAM
(Page Size x
No. of
Banks)
Column Address
Bank Select
Row Address
512 x 4
IA[8:0]=>EA[8:0]
IA[10:9]=>EA[14:13]
IA[22:11]=>EA[11:0]
1024 x 4
IA[9:0]=>EA[9:0]
IA[11:10]=>EA[14:13]
IA[23:12]=>EA[11:0]
2048 x 4
IA[10:0]=>EA[11, 9:0]
IA[12:11]=>EA[14:13]
IA[24:13]=>EA[11:0]
Table 8-6. SDRAM Size = 256 Mbit
256 Mbit
SDRAM
(Page Size x
No. of
Banks)
Column Address
Bank Select
Row Address
512 x 4
IA[8:0]=>EA[8:0]
IA[10:9]=>EA[14:13]
IA[23:11]=>EA[12:0]
1024 x 4
IA[9:0]=>EA[9:0]
IA[11:10]=>EA[14:13]
IA[24:12]=>EA[12:0]
2048 x 4
IA[10:0]=>EA[11, 9:0]
IA[12:11]=>EA[14:13]
IA[25:13]=>EA[12:0]
8-28
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
Table 8-7. Address Ranges for Various SDRAM Device Densities and Page
Size Combinations
SDRAM Device Size
16 Mbit1
64 Mbit
128 Mbit2
256 Mbit
1
2
Page Size
Address Range
1Mx16
256
0 - 0x000F FFFF (1 Mwords)
2Mx8
512
0 - 0x001F FFFF (2 Mwords)
4Mx4
1024
0 - 0x003F FFFF (4 Mwords)
2Mx32
512
0 - 0x001F FFFF (2 Mwords)
4Mx16
256
0 - 0x003F FFFF (4 Mwords)
8Mx8
512
0 - 0x007F FFFF (8 Mwords)
16Mx4
1024
0 - 0x00FF FFFF (16 Mwords)
4Mx32
1024
0 - 0x003F FFFF (4 Mwords)
8Mx16
512
0 - 0x007F FFFF (8 Mwords)
16Mx8
1024
0 - 0x00FF FFFF (16 Mwords)
32Mx4
2048
0 - 0x01FF FFFF (32 Mwords)
16Mx16
512
0 - 0x00FF FFFF (16 Mwords)
32Mx8
1024
0 - 0x01FF FFFF (32 Mwords)
64Mx4
2048
0 - 0x03FF FFFF (64 Mwords)
16M and 64M devices do not have a page size of 2048.
128M and 256M devices do not have a page size of 256.
Understanding DQM Operation
The processor's DQM (Data I/O Mask) pin is used only during the SDRAM
powerup sequence and during a precharge command.
ADSP-21161 SHARC DSP Hardware Reference
8-29
SDRAM Controller Standard Operation
Executing a Parallel Refresh Command During
Host Control
The ADSP-21161 processor SDRAM interface includes a separate A10 pin
(SDA10) to enable the controller to execute a parallel refresh command
with any non-SDRAM access. This separate pin allows the SDRAM controller to precharge the SDRAM before it issues a refresh command.
Connecting this pin to the SDRAM's A10 line, instead of ADDR10 to precharge the SDRAM device, enables the processor to retain control of the
SDRAM device while a host requests (using the HBR pin) and controls the
external ADDR23-0 bus. Figure 8-8 shows an example ADSP-21161 system
containing both a host and SDRAM. During host bus requests, the DSP
still retains mastership of the control pins of the SDRAM (RAS, CAS, SDWE,
SDCKE, SDCLK, MSx and SDA10) when the host assumes control of the system
bus—HBG is asserted. As a result, the single processor (or master DSP in a
multiprocessor system) can issue REF commands as required.
8-30
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
ADSP-21161
1X OR 1/2X CCLK
CLK
CKE
SDCLK
SDCKE
RD
WR
RAS
CAS
WE
RAS
CAS
CONTROLLER SDWE
RESET
ACK
DQM
A10
DQM
SDA10
MSX
MSX
21161
CORE
CS
DQ31:0
BUFFER
D31:0
BA0/BA1
A14/A13
MUX
A23:0
REDY
HBG
SBTS
CS
SDRAM
(JEDEC)
A12:0
A23:0
HBR
A23:0
REQUEST
CS
D31:0
HOST
CLEAR DEADLOCK
OE
ENABLE STROBES
Figure 8-8. SDRAM Interface—Bus Slave
Powering Up After Reset
After reset, once the SDCTL register is written to in the user application
code, the controller initiates the selected power-up sequence. The exact
sequence is determined by SDPM bit of the SDCTL register. In a multiprocessing environment, the power-up sequence is initiated by any one of the
ADSP-21161s. Note that a software reset does not reset the controller and
does not re-initiate a power-up sequence.
ADSP-21161 SHARC DSP Hardware Reference
8-31
SDRAM Controller Commands
Entering and Exiting Self-Refresh Mode
Writing 1 to the SDSRF bit in the SDCTL register causes the SDRAM controller to issue an SREF command to the SDRAM device.
During entry into Self refresh, make sure that no SDRAM accesses are
occurring and that the SDRAM has stopped bursting out data.
Once the SDRAM device enters into self-refresh mode, the SDRAM controller resets the SDSRF bit in the SDCTL register. The SDSRF bit always reads
as 0, regardless of a pending request. The SDRAM controller ignores
other self-refresh requests (SDSRF=1) when the SDRAM device is already in
self-refresh mode.
The application cannot clear the SDSRF bit (SDSRF=0) to cancel self-refresh
mode. The SDRAM device exits self-refresh mode only when it receives a
core or DMA access request from the SDRAM controller.
SDRAM Controller Commands
This section describes each command that the SDRAM controller uses to
manage the SDRAM interface. These commands are transparent to
applications.
A summary of the various commands used by the on chip controller for
the SDRAM interface is as follows:
• ACT (bank activate). Activates a page in the required bank
• MRS (mode register set). Initializes the SDRAM operation parameters during the power-up sequence
• PRE (precharge). Precharges the active bank
• Read/Write
8-32
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
• REF (refresh). Causes the SDRAM to enter refresh mode and generate all addresses internally
• SREF (self-refresh). Places the SDRAM in self-refresh mode, in
which it controls its refresh operations internally
Bank Activate (ACT) Command
A Bank Activate (ACT) command is required if the next data access is on a
different page. The SDRAM controller executes a precharge (PRE) command followed by bank active (ACT) command to activate the page in the
required bank. Only one bank is active at a time.
The SDRAM pin state during the ACT command is shown in Table 8-8
below:
Table 8-8. Pin State During ACT Command
Pin
State
MSx
Low
CAS
High
RAS
Low
SDWE
High
SDCKE
High
Mode Register Set (MRS)
Mode Register Set (MRS) is a part of the power up sequence. MRS initializes
SDRAM operation parameters by using address bits A0-A15 of the
SDRAM as data input. An SDRAM power-up sequence is initiated by
ADSP-21161 SHARC DSP Hardware Reference
8-33
SDRAM Controller Commands
writing 1 to the SDPSS bit in SDCTL register. The exact power up sequence
is determined by the SDPM bit of the SDCTL register.
MRS
initializes the following SDRAM parameters:
• Burst length = 1, bits 2-0, hardwired to zero in ADSP-21161.
• Wrap type = sequential, bit 3, hardwired to zero in ADSP-21161.
• Ltmode = latency mode (CAS latency), bits 6-4, programmable in
SDCTL
• Bits (14-7) always 0, hardwired in the ADSP-21161
While executing mode register set command, the SDRAM controller sets
the unused address pins to zero. During the two clock cycles following
MRS, ADSP-21161 will not issue any other command. The SDRAM pin
state during the MRS command is shown in Table 8-9 below:
Table 8-9. Pin State During MRS Command
Pin
State
MSx
Low
CAS
Low
RAS
Low
SDWE
Low
SDCKE
High
Precharge Command (PRE)
The PRE command is issued to precharge the active bank. The SDRAM
controller executes this command if the data to be accessed is located in a
8-34
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
different bank or in a different page in the same bank. After power up, a
PRE command is issued to the SDRAM device's banks.
The SDRAM pin state during the PRE command is shown in Table 8-10
below:
Table 8-10. Table 10. Pin State During PRE Command
Pin
State
MSx
Low
CAS
High
RAS
Low
SDWE
Low
SDCKE
High
SDA10
High
Read / Write Command
The SDRAM controller executes a Read/Write command if the next
read/write data falls in the present (currently active) page.
In general, a Read interrupts a previous Read when the next access is a
nonsequential address but a page miss does not occur. When a page miss
does occur, the SDRAM controller precharges and activates (PRE and ACT
commands) the SDRAM before issuing a Read or Write command. If the
internal refresh counter (SDRDIV) asserts a refresh request, any new access
is delayed until a refresh command is executed.
ADSP-21161 SHARC DSP Hardware Reference
8-35
SDRAM Controller Commands
Read Commands
For the Read command, the CAS, MSx and SDA10 are asserted low to enable
the SDRAM to latch the column address. The start address is set according to the column address. The delay between Active and Read commands
is determined by the tRCD parameter (see “SDRAM Timing Specifications”
on page 8-9). Data is available after the tRCD and CAS latency requirements
are met.
T0
T1
T2
T3
NOP
Act
NOP
T4
T5
T6
T7
T8
T9
Read
Read
Read
NOP
NOP
T10
T11
NOP
NOP
SDCLK
Command
Pre
Read
*
CAS latency = 1
tCKE1 , DQs
tRP
tRCD
CAS latency = 2
tCKE2 , DQs
CAS latency = 3
tCKE3 , DQs
Data
Data
Data
Data
A0
A1
A2
A3
Data
Data
Data
Data
A0
A1
A2
A3
Data
Data
Data
A0
A1
A2
Data
A3
*burst ends after a delay = CAS latency
Figure 8-9. Read Timing Diagram
8-36
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
The SDRAM pin state during the Read command is shown in Table 8-11
below:
Table 8-11. Pin State During a Read Command
Pin
State
MSx
Low
CAS
Low
RAS
High
SDWE
High
SDCKE
High
SDA10
Low
ADSP-21161 SHARC DSP Hardware Reference
8-37
SDRAM Controller Commands
Write Commands
For the Write Command, CAS, MSx, SDWE, and SDA10 are asserted low to
enable the SDRAM to latch the column address. Data is also asserted in
the same cycle. The start address is set according to the column address.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
Pre
NOP
Act
NOP
Write A
Write B
Write C
Write D
NOP
NOP
NOP
NOP
Data
Data
Data
Data
A0
B0
C0
D0
SDCLK
Cmd
tRP
CAS latency = 1, 2, 3
DQs
tRCD
Figure 8-10. Write Timing Diagram
The SDRAM pin state during the Write command is shown in Table 8-12
below:
Table 8-12. Pin State During Write Command
Pin
State
MSx
Low
CAS
Low
RAS
High
8-38
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
Table 8-12. Pin State During Write Command
Pin
State
SDWE
Low
SDCKE
High
SDA10
Low
DMA Transfers
In cases where a DMA channel is performing reads from SDRAM, the
SDRAM controller issues a read command if at least one location is available in the external port DMA buffer (EPBx) FIFO. Whenever the FIFO is
full, a NOP command is issued.
In cases where a DMA channel is performing writes to SDRAM, the
SDRAM controller issues a write command if at least one word is available
in the EPBx buffer. Whenever no data is available to write, an NOP command is issued.
Refresh (REF) Command
This command is a request to the SDRAM to perform a CBR (CAS before
RAS) transaction. REF causes all addresses to be generated internally in the
SDRAM. This command is issued to all the external banks having
SDRAMs as defined by the SDEM bits.
Before executing the REF command, the SDRAM controller executes a
precharge (PRE) command to the active bank (after meeting tRAS min). The
next active (ACT) command is given by the controller only after a minimum delay equal to tRC.
ADSP-21161 SHARC DSP Hardware Reference
8-39
SDRAM Controller Commands
Setting the Delay Between Refresh Commands
The SDRDIV register in the ADSP-21161 is used to set the number of clock
cycles between two REF commands. Program the SDRDIV register before
writing to the SDCTL register. An internal CBR REF request is made to the
SDRAM controller based on this refresh divisor value. The controller
completes the present burst before servicing the refresh request. The master ADSP-21161 always performs the refresh command.
Understanding Multiprocessing Operation
In a multiprocessing environment, all ADSP-21161 processors share the
SDRAM. While the ADSP-21161 bus master always drives SDRAM input
signals (including the clock), the slave ADSP-21161s track the commands
the master processor issues to the SDRAM. This tracking helps to synchronize the SDRAM refresh counters and to prevent needless refreshing
operations.
Whenever a ADSP-21161 needs to transfer the bus mastership to other
ADSP-21161, it transfers the bus only after meeting tRAS min - 1 number
of cycles for the presently active row. If the refresh timer makes a refresh
request during this process, the present bus master executes a refresh command (after executing precharge command to SDRAM). The current bus
master continues to hold the bus for tRAS min - 1 cycles before giving up
the bus to the new bus master.
If the REF request arrives from the refresh counter during a bus transition
cycle, the new bus master immediately issues a REF command. The new
bus master becomes aware of this request because the refresh counter is
running on all ADSP-21161s. The reloading of the refresh counter occurs
synchronously on all ADSP-21161s, as the slaves watch the external
SDRAM control pins to see when the refresh command is executed by the
master. When a ADSP-21161 receives the bus mastership, it executes a
PRE command prior to the first access to the SDRAM.
8-40
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
The current ADSP-21161 bus master retains mastership of the control
pins of the SDRAM (RAS, CAS, SDWE, SDCKE, SDCLK, MSx, SDA10) when the
host assumes control of the system bus - HBG is asserted. This enables the
master ADSP-21161 to issue a REF command as required.
The SDRAM pin state during the REF command is shown in Table 8-13
below:
Table 8-13. Pin State During REF Command
Pin
State
MSx
Low
CAS
Low
RAS
Low
SDWE
High
SDCKE
High
Self Refresh Command (SREF)
The SREF command causes the SDRAM to perform refresh operations
internally, without any external control. Before executing the SREF command, the SDRAM precharges the active bank.
SREF
mode is enabled by writing a 1 to the SDSRF bit of the SDCTL register.
During entry into SREF, make sure that no SDRAM accesses are occurring
and the SDRAM has stopped bursting data. The controller automatically
asserts a SREF exit cycle if a SDRAM access occurs during the SREF period.
After executing a SREF exit command, the controller waits for 2 + tRC
cycles to execute a CBR ( CAS before RAS) refresh cycle if the refresh counter
ADSP-21161 SHARC DSP Hardware Reference
8-41
SDRAM Controller Commands
is expired already. After the CBR refresh command, the SDRAM controller
waits for tRC number of cycle before executing a bank activate command.
The SDRAM pin state during the SREF command is shown in Table 8-14
below.
Table 8-14. Pin State During SREF Command
Pin
State
MSx
Low
CAS
Low
RAS
Low
SDWE
High
SDCKE
Low
Programming Example
This section provides a programming example written for the
ADSP-21161 DSP. The example shown in Listing 8-1 demonstrates how
to set up the SDRAM controller to work with the ADSP-21161 EZ-Kit
Lite.
Listing 8-1. SDRAM Controller Setup for EZ-Kit
/*******************************************************************
*
Setup for the SDRAM Controller for 21161 EZ-KIT Lite
*
*
*
*
Assumes SDRAM part# Micron MT48LC16M16A1-7SE
*
*
SDCLK=100MHz
*
*
tCK=8ns min @ CL=2 -> SDCL=1 [CAS Latency]
*
*
tRAS=50ns min
-> SDTRAS=3 [active command delay]
*
*
tRP=20ns min
-> SDTRP=2 [precharge delay]
*
*
tRCD=20 ns min
-> SDTRCD=2 [CAS-to-RAS delay]
*
8-42
ADSP-21161 SHARC DSP Hardware Reference
SDRAM INTERFACE
* tREF=64ms/4K rows
->SDRDIV=(2(30MHz)-CL-tRP-4)64ms/4096=937cycles*
*
*
* 3 SDRAMs by 16 bits wide total = 16Mbit x 48
*
*
Mapped to MS0 addresses 0x00200000-0x002fffff
*
*
*
*******************************************************************/
#include "def21161.h"
.SEGMENT/PM
.GLOBAL
pm_code;
init_21161_SDRAM_controller;
init_21161_SDRAM_controller:
ustat1=dm(WAIT);
bit clr ustat1 0x000FFFFF;
dm(WAIT)=ustat1;
ustat1=0x1000;
dm(SDRDIV)=ustat1;
// Clear MSx waitstate and mode
//Refresh rate
ustat1=dm(SDCTL);
// Mask in SDRAM settings
// SDCTL = 0x02014231;
// 1/2 CCLK, no SDRAM buffering option, 2 SDRAM banks
// SDRAM mapped to bank 0 only, no self-refresh, page size 256 words
// SDRAM powerup mode is prechrg, 8 CRB refs, and then mode reg set cmd
// tRCD = 2 cycles, tRP=2 cycles, tRAS=3 cycles, SDCL=1 cycle
// SDCLK0, SDCLK1, RAS, CAS and SDCLKE activated
bit set ustat1
SDTRCD2|SDCKR_DIV2|SDBN2|SDEM0|SDPSS|SDPGS256|SDTRP2|SDTRAS3|SDCL1;
bit clr ustat1 SDBUF|SDEM3|SDEM2|SDEM1|SDSRF|SDPM|DSDCK1|DSDCTL;
dm(SDCTL)=ustat1;
rts;
ADSP-21161 SHARC DSP Hardware Reference
8-43
SDRAM Controller Commands
8-44
ADSP-21161 SHARC DSP Hardware Reference
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