DiSEqC™ 2.1 slave microcontroller for LNBs and switchers

DiSEqC™ 2.1 slave microcontroller for LNBs and switchers
ST7LNB0V3
DiSEqC™ 2.1 slave microcontroller for LNBs and switchers
Datasheet - production data
Features
• Clock, reset and supply management
– Reduced power consumption
– Safe power on/off management by low
voltage detector (LVD)
– Internal 8 MHz oscillator
SO16 narrow
• Communication interface
– One DiSEqC™ 2.1 communication
interface
– Analog interface13/18 V voltage detector
– 22 kHz tone detector
Description
The ST7LNB0V3 is an 8-bit microcontroller
dedicated to DiSEqC™ slave operation in LNBs
and switchers. It is compliant with the DiSEqC™
level 2.1. It also supports backwards compatible
mode (13/18 V, 22 kHz tone) and toneburst
signalling.
• I/O ports
– 8 output ports for control of committed and
uncommitted switches
– 1 output port for standby control.
Table 1. Device summary
• Operating voltage 4.5 to 5.5 V
Order code
• Temperature range -40 to +85 °C.
ST7LNBV03
Package
SO16 narrow
Figure 1. Block diagram
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DocID029484 Rev 1
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Contents
ST7LNB0V3
Contents
1
ST7LNB0V3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
ST7LNB0V3 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
ST7LNB0V3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
ST7LNB0V3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2
ST7LNB0V3 switching output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.1
Single polarity output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.2
Decoded output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.3
Complementary output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Supported DiSEqC™ commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
ST7LNB0V3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
5.1
Command 0Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2
Command 0Dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.5
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.6
2/30
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.5.1
Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . . 18
6.5.2
Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.5.3
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 20
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.6.1
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.6.2
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Contents
6.7
Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.8
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1
Data EEPROM option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.2
Option list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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List of figures
ST7LNB0V3
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
4/30
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SO16 narrow pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ST7LNB0V3 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical IDD in Run against fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Typical IPU against VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Typical VOL at VDD=5 V (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Typical VOL at VDD=5 V (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Typical VDD-VOH at VDD=5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pin plastic small outline package, 150-mil width, package outline . . . . . . . . . . . . . . . . . . . 25
Option list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DocID029484 Rev 1
ST7LNB0V3
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ST7LNB0V3 pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Single polarity output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ST7LNB0V3 DiSEqC™ supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Command 0Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Command 0Dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reply to command 0Dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ST7LNB0V3 EEPROM parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output configuration byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating conditions with the DiSEqC™ signalling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pin plastic small outline package, 150-mil width, mechanical data. . . . . . . . . . . . . . . . . . . 25
Soldering compatibility (wave and reflow soldering process) . . . . . . . . . . . . . . . . . . . . . . . 26
Description of data EEPROM option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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ST7LNB0V3 pin description
1
ST7LNB0V3
ST7LNB0V3 pin description
Figure 2. SO16 narrow pinout
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1. NC = not connected
See Table 2 for a description of the pin functions.
Table 2. ST7LNB0V3 pin functions
Pin
number
Function
name
Function description
1
Vss
Ground
2
VDD
Power Supply (+5 volts)
3
RESET
Reset (active low) input
4
DRX
Receive input
5
OP5
Output 5 (uncommitted port)
6
OP6
Output 6 (uncommitted port)
7
OP7
Output 7 (uncommitted port)
8
OP8
Output 8 (uncommitted port)
9
OP4
Output 4 (SO B/A)
(1)
10
OP3
Output 3 (SB/SA)
11
OP2
Output 2 (H/V)
12
OP1
Output 1 (Hi/Lo)
13
SBY
Standby
14
DTX
DiSEqC™ data transmit output
15,16
-
Not used(2)
1. During normal operation this pin must be pulled-up internally or externally to avoid entering ICC mode
unexpectedly during a reset. Using an external pull-up of 10 kΩ is mandatory in noisy environment. In the
final application, a reset will put the pin back in input pull-up configuration even if it was configured as an
output.
2. Unused pins must be tied to ground.
6/30
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ST7LNB0V3
2
ST7LNB0V3 implementation
ST7LNB0V3 implementation
Figure 3 shows a typical application circuit for the ST7LNB0V3.
Figure 3. ST7LNB0V3 typical application circuit
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1. The divider chain connected to the DRX pin must have the following resistance values: 330 kΩ and
100 kΩ.
2. The reset circuitry linked to the RESET pin is optional. In fact the ST7LNB0V3 has an internal voltage level
detector (LVD) which generates a static reset when the VDD supply is below a threshold voltage of 4.1 V.
3. The DiSEqC signalling must have a tone frequency of 22 kHz (±20%) and an amplitude exceeding 150 mV
peak to peak.
4. When the LVD is enabled (default state), it is mandatory not to connect a pull-up resistor. A 10 nF pulldown capacitor is recommended to filter noise on the reset line.
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ST7LNB0V3 functional description
ST7LNB0V3
3
ST7LNB0V3 functional description
3.1
ST7LNB0V3 configuration
Unlike the original slave microcontroller described in the Eutelsat DiSEqC slave
microcontroller specifications version 1.0, the ST7LNB0V3 does not scan the control pins in
order to determine the slave configuration. Instead all configuration parameters must be
programmed for each specific application, and an option list (see Section 8: Device
configuration) must be filled-in to program the necessary options at the manufacturing
stage.
The slave configuration parameters are the following:
3.2
•
The DiSEqC™ slave address: 11h for an LNB, and 15h for a switcher
•
The local oscillator frequency table entry numbers
•
The DiSEqC™ configuration byte (refer to page 15 of DiSEqC slave microcontroller
specifications)
•
The output mode (see next paragraph)
•
22 kHz tone use in backwards compatible mode (SB/SA or Hi/Lo switching)
•
Standby pin use.
ST7LNB0V3 switching output modes
The ST7LNB0V3 has 8 pins, OP1 to OP 8 available to provide ‘TTL’ logic levels to operate
switches. The switches can be are used to select various signal conditions and sources (for
example horizontal polarization, or satellite position).
As listed in Table 2, the committed output port is composed of OP1 to OP4 and the
uncommitted output port is composed of OP5 to OP8.
Depending on the application hardware, the switching control pins OP1 to OP8 may be
operated differently. Three possible output modes can be configured as described in the
following sections.
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ST7LNB0V3
3.2.1
ST7LNB0V3 functional description
Single polarity output mode
In this mode each pin can be controlled individually as described in Table 3.
Table 3. Single polarity output mode
Function name
3.2.2
Function description
OP4
SO B/A
OP3
SB/SA
OP2
Hor/Ver
OP1
Hi/Lo
OP5
SW5
OP6
SW6
OP7
SW7
OP8
SW8
Decoded output mode
This mode offers the possibility to demultiplex three adjacent committed or uncommitted
control lines (Hi/Lo, SB/SA and SOB/A) in order to have a 1 of 8 demux on the output port
OP1 to OP8. For more details refer to page 10 of DiSEqC™ slave microcontroller
specifications.
It is also possible to have a 1 of 4 demux by decoding only 2 control lines, SB/SA and SO
B/A for controlling a 1 of 4 switcher for example.
3.2.3
Complementary output mode
In this mode the state of the uncommitted switching output port pins is the complementary of
the state of the committed output ports pins. For more details refer to page 14 of DiSEqC™
slave microcontroller specifications.
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Supported DiSEqC™ commands
4
ST7LNB0V3
Supported DiSEqC™ commands
Table 4. ST7LNB0V3 DiSEqC™ supported commands
Command number
(Hex byte)
10/30
Command
name
Command function
00h
RESET
Reset DiSEqC™ microcontroller
01h
clr RESET
Clear the RESET flag
02h
STANDBY
Switch peripheral power off
03h
Power on
Switch peripheral power supply off
04h
Set Cont
Set contention flag
05h
Contend
Return address only if contention flag is set
06h
Clr Cont
Clear contention flag
07h
Address
Return address unless contention flag is set
08h
Move C
Change address only if contention flag is set
09h
Move
Change address unless contention flag is set
10h
STATUS
Read STATUS register
11h
Config
Read Configuration register
14h
Group 0
Read switching state (committed port)
15h
Group 1
Read switching state (uncommitted port)
20h
Set Lo
Select the low Local oscillator frequency
21h
Set VR
Select the vertical polarization
22h
Set Pos A
Select satellite position A
23h
Set SO A
Select switch Option A
24h
Set Hi
Select the Hi local oscillator frequency
25h
Set HL
Select the Horizontal polarization
26h
Set Pos B
Select satellite position B
27h
Set SO B
Select the switch Option B
28h
Set S1 A
Select switch S1 input A
29h
Set S2 A
Select switch S2 input A
2Ah
Set S3 A
Select switch S3 input A
2Bh
Set S4 A
Select switch S4 input A
2Ch
Set S1 B
Select switch S1 input B
2Dh
Set S2 B
Select switch S2 input B
2Eh
Set S3 B
Select switch S3 input B
2Fh
Set S4B
Select switch S4 input B
38h
Write N0
Write to port group 0 (committed switches)
39h
Write N1
Write to port group 1 (uncommitted switches)
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Supported DiSEqC™ commands
Table 4. ST7LNB0V3 DiSEqC™ supported commands (continued)
Command number
(Hex byte)
Note:
Command
name
Command function
51h
LO
Read current L.O frequency table entry number
52h
LO Lo
Read Lo L.O frequency table entry number
53h
LO Hi
Read Hi L.O frequency table entry number
After a power-on, the ST7LNB0V3 responds to backwards compatible signalling (13/18 V,
22 kHz, tone burst) until a valid DiSEqC frame is detected.
A RESET command must be sent in order to return to backwards compatible mode.
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ST7LNB0V3 configuration
5
ST7LNB0V3
ST7LNB0V3 configuration
A dedicated DiSEqC command is implemented to configure the ST7LNB0V3 to the required
target application. This configuration is stored in the ST7LNB0V3 embedded EEPROM
location.
5.1
Command 0Fh
ST7LNB0V3 devices are shipped to customers with a default parameter value. These
parameters can be updated using a dedicated 0Fh DiSEqC command.
The format of this command is described in Table 5 where “data” is the parameter value to
be programmed at the “index” location as shown in Table 8.
Table 5. Command 0Fh
E0h
DiSEqC
Slave address
0Fh
index
data
Note:
The special command E0 xx 0F FF FF protects the EEPROM data from any subsequent
write access (where xx is the corresponding DiSEqC Slave address).
5.2
Command 0Dh
A dedicated 0Dh command has been added to read a parameter located in EEPROM.
The format of this command is described in Table 6 where “index” is the address of the byte
to be read in EEPROM area.
Table 6. Command 0Dh
E2h
DiSEqC
Slave address
0Dh
index
The format of the reply frame is given in Table 7 where “data” is the byte read from
EEPROM:
Table 7. Reply to command 0Dh
E4h
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ST7LNB0V3
ST7LNB0V3 configuration
Timings
The time required to update a byte parameter (write followed by read operation) is 130 ms;
whereas the time required to update all the parameters is about 3.5 s.
:
Table 8. ST7LNB0V3 EEPROM parameters
Index
Parameter
Description
Default Value
FFh)(1)
00
Slave address
DiSEqC slave address (00 to
01
L.O frequencies
(2)
00h
02
Output configuration
See Table 9
0Ah
03
14h
1Bh, see note 4
Serial / version number user can enter a value:0000h to FFFFh
04
FFh
1. Besides the address defined in the EEPROM at index 00h, addresses 10h and 00h are recognized also as
valid addresses.
2. L.O frequencies: Local oscillator table entry numbers.
- High nibble: High L.O frequency
- Low nibble: Low L.O frequency
Table 9. Output configuration byte
Bit description(1)
Bit number
Value
0
22 kHz use
0: High/Low switching
1: SB/SA switching
[1:4]
Decoded mode selection
0: mode not selected
[1 to 8]: decoded mode number
5
Complementary mode selection
0: mode not selected
1: mode selected
6
2 lines decoded mode selection
0: mode not selected
1: mode selected
7
Not used
0
1. If neither the Decoded mode nor the Complementary mode is set then the Single polarity mode is selected
by default.
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Electrical characteristics
ST7LNB0V3
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA=25 °C and TA=TAmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5 V for the
4.5 V ≤ VDD ≤ 5.5 V voltage range. They are given only as design guidelines and are not
tested.
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 4.
Figure 4. Pin loading conditions
673,1
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DocID029484 Rev 1
ST7LNB0V3
6.1.5
Electrical characteristics
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 5.
Figure 5. Pin input voltage
673,1
9,1
06Y9
6.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 10. Voltage characteristics
Symbol
Ratings
VDD - VSS
Supply voltage
VIN
Input voltage on any pin(1)(2)
VESD(HBM)
Electrostatic discharge voltage (Human Body
Model)
VESD(MM)
Electrostatic discharge voltage (Machine
Model)
Maximum value
Unit
7.0
V
VSS-0.3 to VDD+0.3
see Section 6.5.3 on page 20
1. Directly connecting the I/O pins to VDD or VSS could damage the device if an unexpected change of the I/O
configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this
connection has to be done through a pull-up or pull-down resistor (typical: 10kΩ for I/Os). Unused I/O pins
must be tied in the same way to VDD or VSS according to their reset configuration.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise
refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is
induced by VIN<VSS.
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Electrical characteristics
ST7LNB0V3
Table 11. Current characteristics
Symbol
Maximum
value
Ratings
IVDD
Total current into VDD power lines (source)(1)
100
IVSS
(1)
100
Total current out of VSS ground lines (sink)
IIO
Output current sunk by any standard I/O and control pin
25
Output current sunk by any high sink I/O pin
50
Unit
mA
IINJ(PIN)(2)(3)
ΣIINJ(PIN)
2)
Output current source by any I/Os and control pin
- 25
Injected current on RESET pin
±5
Injected current on any other pin
(4)(5)
Total injected current (sum of all I/O and control
±5
pins)(4)
± 20
1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise
refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is
induced by VIN<VSS.
3. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents
throughout the device including the analog inputs. To avoid undesirable effects on the analog functions,
care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the
analog voltage is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6 mA. In addition, it is recommended to inject
the current as far as possible from the analog input pins.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
5. True open drain I/O port pins do not accept positive injection.
Table 12. Thermal characteristics
Symbol
16/30
Ratings
Value
Unit
TSTG
Storage temperature range
TJ
Maximum junction temperature (see Section 6.8: Thermal characteristics)
DocID029484 Rev 1
-65 to +150
°C
ST7LNB0V3
6.3
Electrical characteristics
Operating conditions
Table 13. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
Supply voltage
-
4.5
5.5
V
TA
Ambient temperature
-
-40
+85
°C
Table 14. Operating conditions with low voltage detector (LVD)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIT+(LVD)
Reset release threshold
(VDD rise)
-
4.00
4.25
4.50
VIT-(LVD)
Reset generation threshold
(VDD fall)
-
3.80
4.10
4.30
Vhys
LVD voltage threshold
hysteresis
VIT+(LVD)-VIT-(LVD)
-
200
-
VtPOR
VDD rise time rate(1)
-
20
-
tg(VDD)
Filtered glitch delay on VDD
Not detected by the LVD
-
-
150
ns
IDD(LVD)
LVD/AVD current consumption -
-
200
-
µA
V
mV
20000 μs/V
1. Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on
and LVD reset. When the VDD slope is outside these values, the LVD may not ensure a proper reset of the
MCU.
Table 15. Operating conditions with the DiSEqC™ signalling
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fDiSEqC
DiSEqC™ tone frequency
-
17.6
22
26.4
VDiSEqC
DiSEqC™ tone voltage
-
150
650
-
mVPP
-
-
15
-
V
13/18 volt backward
VBackward compatibility voltage
threshold(1)
kHz
1. In backwards compatible mode, bus DC voltage is compared with 15 V. If it exceeds this voltage then it is
considered as 18 V else it is considered as 13 V.
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Electrical characteristics
6.4
ST7LNB0V3
Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added.
Table 16. Supply current
Symbol
Conditions(1)
Parameter
Supply current in Run mode(2)
IDD
VDD=5.5V, fCPU=8MHz
Supply current for LNB
or switcher applications(3)
Typ
Max
4.50
7
-
20
Unit
mA
1. TA = -40 to +125 °C unless otherwise specified.
2. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all
peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
3. Data based on typical ST7LNB0V3 LNB or switcher application software running.
Figure 6. Typical IDD in Run against fCPU
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9GG9
06Y9
6.5
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
6.5.1
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
•
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100pF capacitor, until a functional disturbance occurs. This test
conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
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DocID029484 Rev 1
ST7LNB0V3
Electrical characteristics
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
•
Software recommendations:
The software flowchart must include the management of runaway conditions such as:
•
–
Corrupted program counter
–
Unexpected reset
–
Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 17. EMS characteristics
Symbol
Parameter
Conditions
Level/Class
VFESD
VDD=5 V, TA=+25 °C,
Voltage limits to be applied on any I/O pin to induce a functional fOSC=8 MHz
disturbance
conforms to IEC
1000-4-2
2B
VFFTB
VDD=5 V, TA=+25 °C,
Fast transient voltage burst limits to be applied through 100 pF fOSC=8 MHz
on VDD and VDD pins to induce a functional disturbance
conforms to IEC
1000-4-4
3B
6.5.2
Electromagnetic Interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 18. EMI characteristics
Symbol
SEMI
Parameter
Peak level
Monitored
frequency band
Conditions
VDD=5 V, TA=+25 °C,
SO16 package,
conforming to SAE J 1752/3
Max vs. [fOSC/fCPU](1)
Unit
1/4 MHz
1/8 MHz
0.1 MHz to 30 MHz
8
14
30 MHz to 130 MHz
27
32
130 MHz to 1 GHz
26
28
SAE EMI Level
3.5
4
dBμV
-
1. Data based on characterization results, not tested in production.
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Electrical characteristics
6.5.3
ST7LNB0V3
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU and DLU) using specific measurement methods,
the product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic Discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the JESD22-A114A/A115A standard.
Table 19. Absolute maximum ratings
Symbol
VESD(HBM)
Ratings
Electrostatic discharge voltage
(human body model)
Maximum
value(1)
Conditions
TA=+25 °C
4000
Unit
V
1. Data based on characterization results, not tested in production.
Static and dynamic latch-up
•
LU: 3 complementary static tests are required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
•
DLU: Electrostatic discharges (one positive then one negative test) are applied to each
pin of 3 samples when the micro is running to assess the latch-up performance in
dynamic mode. Power supplies are set to the typical values, the oscillator is connected
as near as possible to the pins of the micro and the component is put in reset mode.
This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details,
refer to the application note AN1181.
Table 20. Electrical sensitivities
Symbol
Parameter
Class(1)
Conditions
LU
Static latch-up class
TA=+25 °C
A
DLU
Dynamic latch-up class
VDD=5.5 V, fOSC=4 MHz,
TA=+25 °C
A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B
Class strictly covers all the JEDEC criteria (international standard).
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ST7LNB0V3
Electrical characteristics
6.6
I/O port characteristics
6.6.1
General characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Table 21. General characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage
-
-
-
0.3VDD
VIH
Input high level voltage
-
0.7VDD
-
-
Vhys
Schmitt trigger voltage
hysteresis(1)
-
-
400
-
IL
Input leakage current
VSS ≤ VIN ≤ VDD
-
-
±1
Floating input mode
-
-
200
VIN = VSS, VDD = 5 V
50
120
250
kΩ
-
5
-
pF
-
25
-
consumption(2)
IS
Static current
RPU
Weak pull-up equivalent
resistor(3)
CIO
I/O pin capacitance
tf(IO)out
Output high to low level fall
time(1)
tr(IO)out
Output low to high level rise
time(1)
CL = 50 pF
Between 10% and 90%
V
mV
μA
ns
-
25
-
1. Data based on characterization results, not tested in production.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of
the I/O for example or an external pull-up or pull-down resistor (see Figure 7). Data based on design
simulation and/or technology characteristics, not tested in production.
3. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current
characteristics described in Figure 8).
Figure 7. Two typical applications with unused I/O pin
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DocID029484 Rev 1
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Electrical characteristics
ST7LNB0V3
Figure 8. Typical IPU against VDD with VIN=VSS
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06Y9
6.6.2
Output driving current
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Table 22. Output driving current characteristics
Symbol
VOL(1)
Parameter
Conditions
VOH
Max
-
1.0
-
0.4
VDD=5V
IIO=+20 mA
-
1.3
VDD=5V
IIO=+8 mA
-
0.75
VDD=5V
IIO=-5 mA
VDD-1.5
-
VDD=5V
IIO=-2 mA
VDD-0.8
-
VDD=5V
IIO=+5 mA
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time (see Figure 9) V =5V
DD
IIO=+2 mA
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time (see
Figure 10)
(2)
Min
Output high level voltage for an I/O pin when 4
pins are sourced at same time (see Figure 11)
Unit
V
1. The IIO current sunk must always respect the absolute maximum rating specified in Section Table 11. and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section Table 11. and the sum of IIO
(I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH.
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Electrical characteristics
Figure 9. Typical VOL at VDD=5 V (standard)
92/DW9'' 9
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Figure 10. Typical VOL at VDD=5 V (high-sink)
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Figure 11. Typical VDD-VOH at VDD=5 V
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DocID029484 Rev 1
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Electrical characteristics
6.7
ST7LNB0V3
Control pin characteristics
Table 23. Asynchronous RESET pin
Symbol
Conditions(1)(2)(3)
Parameter
Min
Typ
Max
Unit
VIL
Input low level voltage
-
-
-
0.3VDD
VIH
Input high level voltage
-
0.7VDD
-
-
Vhys
Schmitt trigger voltage hysteresis(4)
-
-
1
-
VDD = 5 V
IIO = +5 mA
-
0.5
1.0
VDD = 5 V
IIO= +2 mA
-
0.2
0.4
20
40
80
kΩ
-
30
-
μs
-
20
-
-
μs
-
-
200
-
ns
VOL
Output low level voltage(5)
RON
Pull-up equivalent resistor (6)(4)
VDD=5 V
tw(RSTL)out
Generated reset pulse duration
Internal reset sources
th(RSTL)in
External reset pulse hold
tg(RSTL)in
duration(8)
Filtered glitch
time(7)
V
V
V
1. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
2. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the
VIL max. level specified in Table 11 on page 16. Otherwise the reset will not be taken into account internally.
3. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that
the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value specified
for IINJ(RESET) in Table 11 on page 16.
4. Data based on characterization results, not tested in production.
5. The IIO current sunk must always respect the absolute maximum rating specified in Table 11 on page 16 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
6. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltage on RESET pin between VILmax
and VDD
7. 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
8. The reset network protects the device against parasitic resets.
6.8
Thermal characteristics
Table 24. Thermal characteristics
Symbol
Ratings
Value
Unit
RthJA
Package thermal resistance (junction to ambient)
85
°C/W
TJmax
Maximum junction temperature(1)
150
°C
PDmax
Power dissipation(2)
300
mW
1. The maximum chip-junction temperature is based on technology characteristics.
2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA.
The power dissipation of an application can be defined by the user with the formula: PD=PINT+PPORT where PINT is the chip
internal power (IDDxVDD) and PPORT is the port power dissipation depending on the ports used in the application.
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7
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1
Package mechanical data
Figure 12. Pin plastic small outline package, 150-mil width, package outline
L
45°
A1
A
α
e
B
A1
C
H
D
16
9
1
8
E
Table 25. Pin plastic small outline package, 150-mil width, mechanical data
mm
inches
Dim.
Min
Typ
Max
Min
Typ
Max
A
1.35
-
1.75
0.053
-
0.069
A1
0.10
-
0.25
0.004
-
0.010
B
0.33
-
0.51
0.013
-
0.020
C
0.19
-
0.25
0.007
-
0.010
D
9.80
-
10.00
0.386
-
0.394
E
3.80
-
4.00
0.150
-
0.157
e
-
1.27
-
-
0.050
-
H
5.80
-
6.20
0.228
-
0.244
α
0°
-
8°
0°
-
8°
L
0.40
-
1.27
0.016
-
0.050
Number of pins
N
16
DocID029484 Rev 1
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29
Package information
7.2
ST7LNB0V3
Soldering information
In order to meet environmental requirements, ST offers the ST7LNB0V3 in ECOPACK®
package. The package have a Lead-free second level interconnect. The category of second
Level Interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com,
together with specific technical application notes covering the main technical aspects
related to lead-free conversion (AN2033, AN2034, AN2035, AN2036).
Backward and forward compatibility
The main difference between Pb and Pb-free soldering process is the temperature range.
•
ECOPACK LQFP, SDIP, SO and QFN20 packages are fully compatible with Lead (Pb)
containing soldering process (see application note AN2034)
•
TQFP, SDIP and SO Pb-packages are compatible with Lead-free soldering process,
nevertheless it's the customer's duty to verify that the Pb-packages maximum
temperature (mentioned on the Inner box label) is compatible with their Lead-free
soldering temperature.
)
Table 26. Soldering compatibility (wave and reflow soldering process)
Package
Plating material devices
Pb solder paste
Pb-free solder paste
SDIP & PDIP
Sn (pure Tin)
Yes
Yes(1)
QFN
Sn (pure Tin)
Yes
Yes(1)
LQFP and SO
NiPdAu (Nickel-palladium-Gold)
Yes
Yes(1)
1. Assemblers must verify that the Pb-package maximum temperature (mentioned on the Inner box label) is
compatible with their Lead-free soldering process.
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Device configuration
8
Device configuration
8.1
Data EEPROM option bytes
Table 27. Description of data EEPROM option bytes
Byte name
Description
Address
FAM
Device Family Address (11h:LNB; 15h: switcher)
1002h
LOFREQ
Local Oscillator Frequency Table Entry Numbers
1003h
PARAM
Output Mode and 22 kHz Tone Use (Hi/Lo or SB/SA)
1004h
FAM option byte: Device Family Address
11h: Normal LNB
15h: Normal Switcher
LOFREQ option byte Local Oscillator Frequency Table Entry Number
This byte indicates the value of a LNB local oscillator:
Note:
•
Lowest Nibble = Lo Local Oscillator Frequency Table Entry Number
•
Highest Nibble = Hi Local Oscillator Frequency Table Entry Number
See Table 2 on page 8 of the Eutelsat DisEqC slave microcontroller specifications version
1.0.
PARAM option byte: Output Mode and 22 kHz Tone Use (Hi/Lo or SB/SA)
•
Bit 7:8 = Not used
•
Bit 6 = Decoded Mode With Only Two Lines (the lowest line of a selection group is kept
low)
0: Decoded mode with only two lines not selected
1: Decoded mode with only two lines selected
•
Bit 5 = Complementary Mode Selection
0: Complementary Mode not selected
1: Complementary Mode selected
•
Bit 4:1 = Decoded Mode Number
0: Decoded Mode not selected
1 to 8: Decoded Mode Number (refer to table 5a on page 11 of the Eutelsat DisEqC
slave microcontroller speculations version 1.0.
•
Bit 0 = 22 kHz Tone Use
0: 22 kHz tone use for Hi/Lo switching in backwards compatible mode
1: 22 kHz tone use for SB/SA switching in backwards compatible mode
Note:
If neither a decoded mode nor a complementary output mode is selected, the output mode
is the sinGle polarity output mode (refer to Table 3: Single polarity output mode).
DocID029484 Rev 1
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29
Device configuration
8.2
ST7LNB0V3
Option list
Figure 13. Option list
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Revision history
Revision history
Table 28. Document revision history
Date
Revision
09-Jul-2016
1
Changes
Initial release.
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ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
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