CS4232

CS4232
CS4232
Games Compatible Plug-and-Play Audio System
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General Description
Compatible with Sound BlasterTM, Sound Blaster
ProTM, and Windows Sound SystemTM
The CS4232 is a single chip multimedia audio system
controller and codec that provides compatibility with
ISA Plug and Play, the Microsoft Windows Sound System, and will run software written to the Sound Blaster
and Sound Blaster Pro interfaces. The CS4232 integrates an industry-standard Delta-Sigma codec with
extended signal processing in a high-performance
mixed-signal design. The CS4232 also contains expansive mixing capabilities, an MPU-401 UART, joystick
logic, and interfaces for a music synthesizer and a CDROM.
Fully Plug and Play Compatible
Industry Leading Delta-Sigma Data Converters
ADPCM, µ-Law & A-Law
Compression/Decompression
Dual DMA Support w/FIFOs, Full Duplex Operation
MPC Level-2 Compatible Mixer
Joystick Port and MPU-401 Compatible MIDI
Interface
Optional CD-ROM Interface
External FM and Wave Table Synthesizer Support
Serial Audio Data Port
24 mA TTL Bus Drive Capability
Software Programmable Power Management
ORDERING INFORMATION:
CS4232-KQ
100 pin TQFP, 14x14x1.4mm
CS4232-KM
100 pin PQFP, 14x20x2.3mm
16-Bit Address Decode Support
CS4231/CS4248 Register Compatible
XTAL2I XTAL1I XTAL1O XTAL2O
VREF REFFLT LFILT RFILT
VREF
OSCILLATORS
16
Sample
FIFO
Linear
µ-Law
A-Law
ADPCM
Serial Shift
Serial I/F
Control
ISA
Bus
Interface
SD<7:0>
SA<11:0>
8
12
Plug
and
Play
Codec
Reg
I/F
IOR
IOW
AEN
IOCHRDY
IRQ
DRQ
DACK
SA<12:15>
(CDROM)
6
3
Config
IO
IRQ
DMA
3
Gain
A/D
Gain
Mux
8-bit
Dither
Monitor
Atten
Mix
Gain
Mix
Gain
D/A
Linear
µ-Law
A-Law
ADPCM
16
Sample
FIFO
Atten
Mute
Atten
Mute
4
D/A
Atten
Mute
Atten
Mute
4
CD-ROM Logic, or
Upper Address Bits
4
Advanced Product Information
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
MPU-401
UART
with
FIFOS
WSS,
SBPRO
Registers
Synthesis
Interface
4
JOYSTICK
LOUT
Mute
Decode
Logic
Joystick
Logic
LMIC
RMIC
LLINE
RLINE
LAUX1
RAUX1
Gain
A/D
MIDI
SCS SINT
MOUT
ROUT
Mix
Gain
LAUX2
RAUX2
Mix
Gain
MIN
Peripherals
&
8
2
E PROM
Interface
3
XIOW
XIOR
XD<7:0>
XA<2:0>
BRESET
This document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Copyright  Crystal Semiconductor Corporation 1996
(All Rights Reserved)
MAR ’95
DS145PP5
1
CS4232
TABLE OF CONTENTS
CS4232 PERFORMANCE SPECIFICATIONS ... 3
GENERAL DESCRIPTION ................................. 12
ISA Bus Interface............................................. 13
I/O Cycles .................................................... 13
I/O Address Decoding.................................. 13
DMA Cycles ................................................. 14
Interrupts ...................................................... 14
PLUG AND PLAY ............................................... 14
CS4232 PnP Data ........................................... 16
Loading Resource Data................................... 18
The Crystal Key ............................................... 18
Bypassing Plug and Play................................. 19
Hardware Configuration Data .......................... 20
Hostload Procedure ......................................... 21
External E2PROM............................................ 22
WINDOWS SOUND SYSTEM CODEC .............. 23
Enhanced Functions (MODE 2) ...................... 23
FIFOs ............................................................... 23
WSS Codec PIO Register Interface ................ 24
DMA Interface.................................................. 24
DMA Channel Mapping................................ 24
Dual DMA Channel Mode............................ 25
Single DMA Channel (SDC) Mode .............. 25
Sound System Codec Register Interface ........ 26
Direct Mapped Registers ............................. 26
I/O Data Registers ....................................... 30
Indirect Mapped Registers........................... 31
SOUND BLASTER INTERFACE........................ 42
Mode Switching ............................................... 42
Sound Blaster Register Interface .................... 42
Sound Blaster Mixer Registers .................... 43
GAME INTERFACE ............................................ 45
CONTROL INTERFACE ..................................... 46
Control Register Interface................................ 46
MPU-401 INTERFACE ........................................ 48
MPU-401 Register Interface ............................ 48
MIDI UART ...................................................... 49
MPU-401 "UART" Mode Operation ................. 49
EXTERNAL PERIPHERAL PORT...................... 50
Synthesizer Interface ....................................... 50
CDROM Interface ............................................ 50
SERIAL AUDIO DATA PORT ............................ 50
2
WSS CODEC SOFTWARE DESCRIPTION ....... 51
Calibration ........................................................ 53
No Calibration (CAL1,0 = 00) ...................... 53
Converter Calibration (CAL1,0 = 01) ........... 53
DAC Calibration (CAL1,0 = 10) ................... 53
Full Calibration (CAL1,0 = 11) ..................... 53
Changing Sampling Rate................................. 54
Changing Audio Data Formats ........................ 54
Audio Data Formats......................................... 54
16-bit Signed ................................................ 55
8-bit Unsigned .............................................. 55
8-bit Companded ......................................... 55
ADPCM Compressed................................... 58
DMA Registers................................................. 58
Playback DMA Registers ............................. 59
Capture DMA Registers ............................... 59
Digital Loopback .............................................. 59
Timer Registers................................................ 60
WSS Codec Interrupt....................................... 60
Error Conditions ............................................... 60
DIGITAL HARDWARE DESCRIPTION .............. 60
Bus Interface.................................................... 60
FM Synthesis ................................................... 61
Crystals / Clocks .............................................. 62
General Purpose Output Pins.......................... 62
Reset and Power Down................................... 62
Multiplexed Pin Configuration .......................... 62
ANALOG HARDWARE DESCRIPTION ............. 63
Line-Level Inputs Plus MPC Mixer .................. 63
Microphone Level Inputs.................................. 63
Mono Input ....................................................... 64
Line-Level Outputs........................................... 64
Mono Output with Mute Control....................... 64
Miscellaneous Analog Signals ......................... 64
GROUNDING AND LAYOUT.............................. 65
POWER SUPPLIES ............................................ 65
ADC/DAC FILTER RESPONSE ......................... 67
PIN DESCRIPTIONS........................................... 69
ISA Bus Interface Pins..................................... 71
Analog Inputs ................................................... 72
Analog Outputs ................................................ 73
MIDI Interface .................................................. 74
Synthesizer Interface ....................................... 74
External Peripheral Port................................... 74
Joystick/Serial Port Interface ........................... 75
CDROM Interface ............................................ 76
Miscellaneous .................................................. 77
Power Supplies ................................................ 78
PARAMETER DEFINITIONS .............................. 79
PACKAGE PARAMETERS................................. 80
APPENDIX A: E2PROM TYPICAL DATA.......... 81
DS145PP5
CS4232
ANALOG CHARACTERISTICS (TA = 25 °C; VA, VD1-VD2, VDF1-VDF3 = +5V;
Input Levels: Logic 0 = 0V, Logic 1 = VD1-VD2; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz;
Measurement Bandwidth is 10 Hz to 20 kHz, 16-bit linear coding.)
Parameter*
Symbol
Min
Typ
Max
Units
Analog Input Characteristics - Minimum Gain Setting (0dB); unless otherwise specified.
ADC Resolution
(Note 1)
ADC Differential Nonlinearity
(Note 1)
Instantaneous Dynamic Range
Total Harmonic Distortion
Interchannel Isolation
IDR
Line Inputs
Mic Inputs
THD
Programmable Input Gain Span
Line Inputs
Gain Step Size
Full Scale Input Voltage:
80
72
(Note 1)
Input Capacitance
(Note 1)
0.02
0.025
%
%
dB
dB
dB
dB
±0.5
±0.5
dB
dB
21.5
22.5
1.3
1.5
1.7
dB
±10
±100
LSB
0.26
2.6
2.6
Gain Drift
Input Resistance
LSB
dB
dB
80
80
90
90
0 dB gain
(MGE=1) MIC Inputs
(MGE=0) MIC Inputs
LINE, AUX1, AUX2, MIN Inputs
83
79
0.006
0.01
Line to Line Inputs
Line to Mic Inputs
Line-to-AUX1
Line-to-AUX2
Line Inputs
Mic Inputs
Bits
±0.5
Line Inputs
(Note 2) Mic Inputs
Interchannel Gain Mismatch
ADC Offset Error
16
dB
0.28
2.8
2.8
Vpp
Vpp
Vpp
±100
ppm/°C
20
kΩ
15
pF
Notes: 1. This specification is guaranteed by characterization, no production testing.
2. MGE = 1 (see WSS Indirect Reg I0, I1) and a 10 µF capacitor on the VREF pin.
*Parameter definitions are given at the end of this data sheet.
Specifications are subject to change without notice.
Windows and Windows Sound System are registered trademarks of Microsoft Corporation.
Sound Blaster and Sound Blaster Pro are registered trademarks of Creative Labs.
Adlib is a registered trademark of Adlib Corporation.
DS145PP5
3
CS4232
ANALOG CHARACTERISTICS
(Continued)
Parameter*
Symbol
Min
Typ
Max
Units
Analog Output Characteristics - Minimum Attenuation (0dB); unless otherwise specified.
DAC Resolution
(Note 1)
DAC Differential Nonlinearity
(Note 1)
Dynamic Range
-Total
-Instantaneous
Total Harmonic Distortion
Interchannel Isolation
All Outputs
(Note 3)
Line Out
Interchannel Gain Mismatch
±0.5
TDR
IDR
80
THD
0.02
±0.1
±0.5
dB
2.2
2.3
V
100
400
µA
(Notes 1,4)
(Note 3)
dB
93
94.5
1.3
1.0
1.5
1.5
1.7
2
dB
dB
±1
±10
mV
2.9
3.2
Vpp
DAC Offset Voltage
2.6
Gain Drift
dB
100
Deviation from Linear Phase
%
Line Out
0 dB to -81 dB
-82.5 dB to -94.5 dB
OUT, MOUT
dB
dB
95
DAC Programmable Attenuation Span
Full Scale Output Voltage:
LSB
95
85
0.01
2.0
Voltage Reference Output Current - VREF
Bits
(Note 3)
Voltage Reference Output - VREF
DAC Attenuation Step Size
16
(Note 1)
ppm/°C
1
Degree
External Load Impedance
10
kΩ
Mute Attenuation (0 dB)
80
dB
Total Out-of-Band Energy
0.6xFs to 100 kHz
Audible Out-of-Band Energy
0.6xFs to 22 kHz
(Note 1)
-45
dB
(Fs=8kHz)
(Note 1)
-70
dB
110
60
170
200
200
mA
mA
mA
µA
µA
Power Supply
Power Supply Current
Power Supply Rejection
Digital, Operating
Analog, Operating
Total
Digital, Power Down
Analog, Power Down
1 kHz
(Note 1)
61
41
102
50
50
40
dB
Notes: 3. 10 kΩ, 100 pF load.
4. DC current only. If dynamic loading exists, then the voltage reference output must be buffered
or the performance of ADCs and DACs will be degraded.
4
DS145PP5
CS4232
MIXERS (TA = 25 °C; VA, VD1-VD2, VDF1-VDF3 = +5V; Input Levels: Logic 0 = 0V, Logic 1 = VD1-VD2;
1 kHz Input Sine wave)
Parameter
Symbol
Min
Typ
Mixer Gain Range Span
LINE, AUX1, AUX2
MIN
Master
45
42
26
46.5
45
30
Step Size
LINE, AUX1, AUX2
MIN
Master
1.3
2.3
1.6
1.5
3.0
2.0
Max
Units
dB
dB
dB
1.7
3.4
2.4
dB
dB
dB
ABSOLUTE MAXIMUM RATINGS (AGND, DGND, SGND = 0V, all voltages with respect to 0V.)
Parameter
Power Supplies:
Symbol
Digital
VD1-VD2
VDF1-VDF3
Analog VA1,VA2
Total Power Dissipation
Min
Max
Units
-0.3
-0.3
-0.3
6.0
6.0
6.0
V
V
V
1
W
(Supplies, Inputs, Outputs)
Input Current per Pin
(Except Supply Pins)
-10.0
+10.0
mA
Output Current per Pin
(Except Supply Pins)
-50
+50
mA
Analog Input Voltage
-0.3
VA+0.3
V
Digital Input voltage
-0.3
VD+0.3
V
-55
+125
°C
+150
°C
Ambient Temperature
(Power Applied)
Storage Temperature
-65
Warning: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AGND, DGND, SGND = 0V,
all voltages with repect to 0V.)
Parameter
Power Supplies:
Operating Ambient Temperature
DS145PP5
Symbol
Digital VD1-VD2
Digital Filtered VDF1-VDF3
VA
Analog
TA
Min
Typ
Max
Units
4.75
4.75
4.75
5.0
5.0
5.0
5.25
5.25
5.25
V
V
V
0
25
70
°C
5
CS4232
DIGITAL FILTER CHARACTERISTICS (Note 1)
Parameter
Symbol
Passband
Frequency Response
Passband Ripple
Min
Typ
Max
Units
0
0.40xFs
Hz
-1.0
+0.5
dB
±0.1
dB
0.60xFs
Hz
(0-0.40xFs)
Transition Band
0.40xFs
Stop Band
0.60xFs
Hz
74
dB
Stop Band Rejection
Group Delay
8- and 16-bit formats
Stereo ADPCM format
Mono ADPCM format
10/Fs
14/Fs
18/Fs
s
s
s
ADCs
DACs
0.0
0.1/Fs
µs
µs
Group Delay Variation vs. Frequency
DIGITAL CHARACTERISTICS (TA = 25°C; VA, VD1-VD2, VDF1-VDF3 = 5V;
AGND, DGND1-DGND2, SGND1-SGND3 = 0V.)
Parameter
Symbol
Min
Max
Units
VIH
2.0
VD-1.0
VD+0.3
VD+0.3
V
V
VIL
-0.3
0.8
V
ISA Bus Pins I0 = -24.0 mA
IOCHRDY, SDA/XD0 (Note 7)
All Others
I0 = -1.0 mA
VOH
2.4
VD
V
2.4
VD
V
ISA Bus Pins
IOCHRDY
All Others
VOL
0.4
0.4
0.4
V
V
V
High-level Input Voltage
Digital Inputs
XTAL1I/XTAL2I
Low-level Input Voltage
High-level Output Voltage:
Low-level Output Voltage:
Input Leakage Current
Output Leakage Current
Note
6
I0 = 24.0 mA
I0 = 8.0 mA
I0 = 4.0 mA
(Digital Inputs)
-10
10
µA
(High-Z Digital Outputs)
-10
10
µA
7. Open Collector pins. High level output voltage dependent on external pull up (required) used and
number of peripherals (gates) attached.
DS145PP5
CS4232
TIMING PARAMETERS (TA = 25 °C; VA, VD1-VD2, VDF1-VDF3 = +5V; outputs loaded with 30pF
Input Levels: Logic 0 = 0V, Logic 1 = VD1-VD2)
Parameter
IOW or IOR strobe width
Data valid to IOW rising edge
(write cycle)
Symbol
Min
Max
tSTW
90
ns
tWDSU
22
ns
IOR falling edge to data valid (read cycle)
tRDDV
SA <> and AEN setup to IOR or IOW falling edge
tADSU
22
ns
SA <> and AEN hold from IOW or IOR rising edge
tADHD
10
ns
DACK<> inactive to IOW or IOR falling edge (DMA cycle
immediately followed by a non-DMA cycle)
(Note 11)
tSUDK1
60
ns
DACK<> active from IOW or IOR rising edge (non-DMA
cycle completion followed by DMA cycle)
(Note 11)
tSUDK2
0
ns
DACK<> setup to IOR falling edge (DMA cycles)
DACK<> setup to IOW falling edge
tDKSUa
tDKSUb
25
25
ns
ns
tDHD2
15
ns
(Note 11)
Data hold from IOW rising edge
DRQ<> hold from IOW or IOR falling edge
(assumes no more DMA cycles needed)
DTM(I10) = 0
DTM(I10) = 1
60
Units
45
tDRHD
ns
ns
-25
Time between rising edge of IOW or IOR to next falling
edge of IOW or IOR
tBWDN
80
Data hold from IOR rising edge
tDHD1
0
DACK<> hold from IOW rising edge
DACK<> hold from IOR rising edge
tDKHDa
tDKHDb
25
25
ns
ns
RESDRV pulse width high
tRESDRV
40
ms
ns
25
XTAL1I, XTAL2I frequency
(Notes 1,8,9)
XTAL1I, XTAL2I high time
(Notes 1,9)
18
ns
XTAL1I, XTAL2I low time
(Notes 1,9)
18
ns
Sample Frequency
25.6
ns
(Note 1)
Fs
(Note 10)
3.918
MHz
50
kHz
tSCLKW
Fsx64
Hz
SCLK rising to SDOUT valid
tPD1
30
ns
SCLK rising to FSYNC transition
tPD2
-20
20
ns
SDIN valid to SCLK falling
tS1
30
ns
SDIN hold after SCLK falling
tH1
30
ns
Serial Port Timing
SCLK frequency
Notes: 8. The higher frequency crystal should be placed on XTAL1 which is designed for higher loop gains.
9. The Sample frequency specification must not be exceeded.
10. When SF1,0 = 10, 32-bit mode, SCLK is active for the first 32 bit periods of the frame, and remains
low during the last 32 bit periods of the frame.
11. AEN must be high during DMA cycles.
DS145PP5
7
CS4232
t
FSYNC
SF1,0=01,10
FSYNC
SF1,0=00
t
pd2
t
pd2
pd2
SCLK
t
t
sckw
s1
SDIN
t
h1
MSB, Left
MSB, Left
SDOUT
t
pd1
Serial Port Timing
DRQ<>
t DKSUa
t DRHD
DACK<>
t STW
t DKHDb
IOR
t RDDV
t DHD1
SD<7:0>
8-Bit Mono DMA Read/Capture Cycle
8
DS145PP5
CS4232
DRQ<>
t DKSUb
t DRHD
DACK<>
t STW
t DKHDa
IOW
t WDSU
t DHD2
SD<7:0>
8-Bit Mono DMA Write/Playback Cycle
DRQ<>
DACK<>
IO R /IO W
t BWDN
LEFT/LOW
BYTE
SD<7:0>
RIGHT/HIGH
BYTE
8-Bit Stereo or 16-Bit Mono DMA Cycle
DRQ<>
DACK<>
IO R /IO W
t BWDN
SD<7:0>
LEFT/LOW
BYTE
LEFT/HIGH
BYTE
RIGHT/LOW
BYTE
RIGHT/HIGH
BYTE
16-Bit Stereo or ADPCM DMA Cycle
DS145PP5
9
CS4232
DRQ<>
tSUDK1
t SUDK2
DACK<>
IO R
t RDDV
t DHD1
SD<7:0>
t ADSU
t ADHD
SA<>
AEN
I/O Read Cycle
DRQ<>
t SUDK1
t SUDK2
DACK<>
t STW
IO W
tWDSU
t DHD2
SD<7:0>
t ADSU
t ADHD
SA<>
AEN
I/O Write Cycle
10
DS145PP5
CS4232
VD1
VD2 VDF1
VDF2 VDF3 VREF REFFLT
LFILT RFILT
VA
20 dB
I0
I1
VREF
FIFO
16
Samples
ISA
Bus
Interface
Linear
µ-Law
A-Law
ADPCM
A/D
I8 or I28
A/D
Gain
I0
I0
LLINE
RLINE
Mux
Gain
LMIC
RMIC
LAUX1
RAUX1
I1
I1
Serial Shift
Plug
&
Play
Monitor
Atten
I13
Serial I/F
Control
ADC1
ADC0
AGND
Mix I19
Gain I18
8
SD<7:0>
12
SA<11:0>
IOR
IOW
Codec
Reg
I/F
D/A
Linear
µ-Law
A-Law
ADPCM
FIFO
16
Samples
Atten
I27
Atten
I6
I8
Config
IO
IRQ
DMA
10µsec Resolution Timer
Sound System TM Registers
IOCHRDY
Sound Blaster
IRQ<A:F>
DRQ<A:C>
Decode
Logic
MPU-401
I/F
DACK<A:C>
Joystick
I/F
TM
LOUT
Mute
I26
Mix
Atten
I26
D/A
Control Registers
AEN
I3
I2
Mix
Gain
Atten
I7
MIN
Atten
I29
ROUT
Registers
TX FIFO
64 byte
RX FIFO
16 byte
Mix
Gain
U
A
R
T
LAUX2
RAUX2
I4
I5
MIDOUT
MIDIN
JACX
JACY
JBCX/SDOUT
JBCY/SDIN
JAB<1:0>
JBB<1:2>/
<SCLK:FSYNC>
SA12/CDCS
SA13/CDACK
SA14/CDINT
SA15/CDRQ
SCS
SINT/XCTL1
4-level
558-like
Speed
Timer
Control
4 Button I/F
CD-ROM
Port
Synth Port
E2PROM
Port
XD<7:0>/SDA
XA<2:0>/
XCTL0/SCL
BRESET
XIOR
XIOW
8
2
External
Peripheral
Port
RESDRV
MOUT
Oscillators
DGND1 DGND2
XTAL2I XTAL1I XTAL1O XTAL2O
TEST
SGND1
SGND2
SGND3
Figure 1. CS4232 Block Diagram
DS145PP5
11
CS4232
GENERAL DESCRIPTION
The CS4232 is comprised of five physical devices along with Plug-and-Play support for two
additional external devices. The internal devices
are:
Windows Sound System Codec
Sound Blaster Pro Compatible Interface
Game Port (Joystick)
Control
MPU-401
The two external devices are:
Synthesizer
CDROM
In addition, the CS4232 includes a full ISA interface with Plug and Play compatibility and an
External Peripheral Port for interfacing to external devices (i.e. Synthesizer and CDROM).
Since the Synthesizer and CDROM analog inputs are external, mapping as shown in Figure 3,
on page 44, must be used to maintain Sound
Blaster compatibility, i.e. FM analog must be
connected to the LINE analog inputs of the
codec. A Karaoke mode has also been added to
the CS4232 where the Mic input can be mixed
into the output mixer. The bits to control this
mode are found in the Control logical device interface on page 47.
When initially powered up, the CS4232 IC is
isolated from the bus, and each device supported
by the CS4232 must be activated via software.
Once activated, each device responds to the reso urces given (Address, IRQ, and DMA
channels). The seven devices listed above are
grouped into 5 logical devices, as shown in Figure 2. Bracketed features are supported, but
typically not used. The five logical devices are:
LOGICAL DEVICE 0:
Windows Sound System Codec (WSS Codec)
Synthesizer
Sound Blaster Pro Compatible Interface
LOGICAL DEVICE 1: Game Port
12
LOGICAL DEVICE 2: Control
LOGICAL DEVICE 3: MPU401
LOGICAL DEVICE 4: CDROM
Logical Device 0 consists of three physical devices. The WSS Codec and the Synthesizer are
grouped together since the original Windows
Sound System board expected an FM synthesizer
if the codec was present. The Sound Blaster Pro
Compatible interface, SBPro, is also grouped to
allow the WSS Codec and the SBPro to share
Interrupts and DMA channels. The Synthesizer
device is externally located on the Peripheral
Port and could be an FM synthesizer such as the
OPL3, or a wave table synthesizer such as the
CS9233. The WSS Codec and the SBPro compatible devices are internal to the CS4232 IC.
Logical Device 1 is the Game Port that supports
up to two joystick devices.
Logical Device 2 is the Control device that supports global features of the CS4232 IC. This
device uses I/O locations to control power management, joystick rate, and PnP resource data
loading.
Logical Device 3 is the MPU401 interface. The
MPU401 MIDI interface includes a 64-byte
FIFO for data transmitted out the MIDOUT pin
and a 16-byte FIFO for data received from the
MIDIN pin.
Logical Device 4 supports a CDROM connected
to the peripheral port. This interface, on the external peripheral port, can support CDROMs
with up to 8 I/O locations, an interrupt, and a
DMA channel. Although this logical device is
listed as a CDROM, any external device that fits
within the resources listed above may be substituted. If the CDROM port is used for another
device, the PnP resource data must be updated to
reflect the new device.
DS145PP5
CS4232
PnP ISA Bus
Interface
Logical Device 0
Logical Device 1
Logical Device 2
Logical Device 3
WSS Codec:
Game Port:
Control:
MPU-401:
I/O: WSSbase
2 DMA Channels
1 Interrupt
Synthesis:
I/O: GAMEbase
I/O: CTRLbase
[1 Interrupt]
I/O: MPUbase
1 Interrupt
Logical Device 4
CDROM:
I/O: CDbase
[1 Interrupt]
[1 DMA Channel]
Figure 2. CS4232 Logical Devices
I/O: SYNbase
[1 Interrupt]
SBPro:
I/O: SBbase
(DMA shared)
(Interrupt shared)
ISA Bus Interface
The 8-bit parallel I/O and 8-bit parallel DMA
ports of the CS4232 provide an interface which
is compatible with the Industry Standard Architecture (ISA) bus. The ISA Interface enables the
host to communicate with the various functional
blocks within the CS4232 via two types of accesses: Programmed I/O (PIO) access, and DMA
access.
A number of configuration registers must be programmed prior to any accesses by the host
computer. The configuration registers are programmed via a Plug and Play configuration
sequence or via configuration software provided
by Crystal Semiconductor.
DS145PP5
I/O CYCLES
Every device in the CS4232, that is enabled, requires I/O space. An I/O cycle begins when the
CS4232 decodes a valid address on the bus
while the DMA acknowledge signals are inactive
and AEN is low. The IOR and IOW signals determine the direction of the data transfer. For
read cycles, the CS4232 will drive data on the
DATA lines while the host asserts the IOR
strobe. Write cycles require the host to assert
data on the DATA lines and strobe the IOW signal. The CS4232 will latch data on the rising
edge of the IOW strobe.
I/O ADDRESS DECODING
The logical devices inside the CS4232 use 10-bit
or 12-bit address decoding. The Synthesizer,
Sound Blaster, Game Port, MPU-401, and
CDROM devices support 10-bit address decoding, while the Windows Sound System and
Control devices support 12-bit address decoding.
Devices that support 10-bit address decoding, re13
CS4232
quire A10 and A11 be zero for proper decode;
therefore, no aliasing occurs through the 12-bit
address space.
To prevent aliasing into the upper address space,
the CS4232 supports a "16-bit decode" option,
where the upper address bits SA12 through
SA15 can be connected to the CS4232. SA12SA15 are then decoded to be 0,0,0,0 for all
logical device address decoding. When the upper
address bits are used, the CDROM interface is
no longer available since the upper address pins
are multiplexed with the CDROM (See Reset
and Power Down section).
DMA CYCLES
The CS4232 supports up to three 8-bit ISA-compatible DMA channels. The only allowed
configuration, which cannot be modified, is:
DMA A = ISA DMA channel 0
DMA B = ISA DMA channel 1
DMA C = ISA DMA channel 3
The typical configuration would require two
DMA channels. One for the WSS Codec and
Sound Blaster playback, and the other for WSS
Codec capture (to support full-duplex). The
CDROM, if used, can also support a DMA channel, although this is not typical.
DMA cycles are distinguished from control register cycles by the generation of a DRQ (DMA
Request) by the CS4232. The host acknowledges
the request by generating a DACK (DMA Acknowledge) signal. The transfer of audio data
occurs during the DACK cycle. During the
DACK cycle the CS4232 ignores the addresses
on the address lines.
The digital audio data interface uses DMA request/grant pins to transfer the digital audio data
between the CS4232 and the ISA bus. The
CS4232 is responsible for generating a request
signal whenever the CS4232’s internal buffers
require updating. Upon receipt of a DMA re14
quest, the host processor responds with an acknowledge signal and a command strobe which
transfers data to and from the CS4232, eight bits
at a time. The CS4232 holds the request pin active until the appropriate number of 8-bit cycles
have occurred. The number of 8-bit transfers will
vary depending on the digital audio data format,
bit resolution, and operation mode.
The CS4232 may assert the DMA request signal
at any time. Once asserted, the DMA request
will remain asserted until a complete DMA cycle
occurs to the CS4232. A complete DMA cycle
consists of one or more bytes depending on
which device internal to the CS4232 is generating the request.
INTERRUPTS
The CS4232 supports six interrupt pins for Plug
and Play flexibility, although only one or two are
typically used. The only allowed hardware connections, which cannot be modified, are:
IRQ A = ISA Interrupt 5
IRQ B = ISA Interrupt 7
IRQ C = ISA Interrupt 9
IRQ D = ISA Interrupt 11
IRQ E = ISA Interrupt 12
IRQ F = ISA Interrupt 15
The typical configuration would support two interrupt sources: one shared between the WSS
Codec and the Sound Blaster Pro compatible devices, and the other for the MPU401 device.
Interrupts are also supported for the Synthesizer,
Control, and CDROM devices, but are typically
not used.
PLUG AND PLAY
The Plug and Play (PnP) interface provides the
necessary logic to make the CS4232 compatible
with the Intel/Microsoft Plug-and-Play specification for an ISA-bus device. Since the CS4232 is
an ISA-bus device, it only supports ISA-compatible IRQs and DMA channels. Plug and Play
compatibility allows the PC to automatically
DS145PP5
CS4232
configure the CS4232 into the system upon
power up. Plug and Play capability optimally resolves conflicts between Plug and Play and
non-Plug and Play devices within the system.
Alternatively, the PnP feature of the CS4232 can
be bypassed. See the Bypassing PnP section for
more information. The CS4232 PnP interface operates in accordance with the Plug and Play ISA
Specification published by Intel and Microsoft.
For a detailed Plug and Play protocol description, please refer to the latest revision of the
Plug and Play ISA Specification.
To support Plug and Play in ISA systems that do
not have a PnP BIOS or a PnP-aware operating
system, the Configuration Manager (CM) TSR
and an ISA Configuration Utility (ICU) are used
to provide these functions. The CM isolates the
cards, assigns Card Select Numbers, reads PnP
card resource requirements, and allocates resources to the cards based on system resource
availability. The ICU is used to keep the BIOS
and the CM informed of the current system configuration. It also aids users in determining
configurations for non-PnP ISA cards. A more
thorough discussion of the Configuration Manager and the ISA Configuration Utility can be
found in the Product Development Information
document of the Plug and Play Kit by Intel
Corp. In a PnP BIOS system, the BIOS is responsible for configuring at least all system
board PnP devices. Some systems require additional software to aid the BIOS in configuring
PnP ISA cards. The PnP BIOS can execute all
PnP functions independently of the type of operating system. However, if a PnP aware operating
system is present, the PnP responsibilities are
shared between the BIOS and the operating system. For more information regarding PnP BIOS,
please refer to the latest revision of the Plug and
Play BIOS Specification published by Compaq
Computer, Phoenix Technologies, and Intel.
The Plug and Play configuration sequence maps
the various functional blocks of the CS4232
(logical devices) into the host system address
DS145PP5
space and configures both the DMA and interrupt channels. The host has access to the
CS4232 via three 8-bit auto-configuration ports:
Address port (0279h), Write Data port (0A79h),
and relocatable Read Data port (0200h - 03FFh).
The read data port is relocated automatically by
PnP software when a conflict occurs.
The configuration sequence is as follows:
1. Host sends a software key which places all
PnP cards in the sleep state (or Plug-andPlay mode).
2. The CS4232 is isolated from the system using
an isolation sequence.
3. A unique identifier (handle) is assigned to the
CS4232 and the resource data is read.
4. After all cards’ resource requirements are determined, the host uses the handle to assign
conflict free resources to the CS4232
5. After the configuration registers have been
programmed, each configured logical device
is activated.
6. The CS4232 is then removed from Plug-andPlay mode.
Upon power-up, the chip is inactive and must be
enabled via software. The CS4232 hardware
monitors writes to the PnP Auto-Configuration
Address port (0279h). If the host sends a PnP
initiation key, consisting of a series of 32 predefined byte writes, the hardware will detect the
key and place the CS4232 into the Plug-and-Play
(PnP) mode. Another method to program the part
is to use a special Crystal initiation key which
functions like the PnP initiation key, but can be
invoked by the user at any time However, the
Crystal Key only supports one CS4232 per system. The Crystal key and special commands are
detailed in the Crystal Key and Bypassing PnP
sections.
15
CS4232
The isolation sequence uses a unique 72-bit serial identifier which is stored in the CS4232.
The host performs 72 pairs of I/O read accesses
to the Read Data port. The identifier determines
what data is put on the data bus in response to
those read accesses. When the isolation sequence
is complete, the CM assigns a Card Select Number (CSN) to th e CS4232. This number
distinguishes the CS4232 from the other PnP devices in the system. The CM then reads the
resource data from the CS4232. The 72-bit identifier and the resource data is either stored in an
external user-programmable E2PROM, or loaded
via a ’hostload" procedure from BIOS before
PnP software is initiated.
The CM determines the necessary resource requirements for the system and then programs the
CS4232 through the configuration registers. The
configuration register data is written one logical
device at a time. After all logical devices have
been configured, the CM activates each one individually. Each logical device is now available on
the ISA bus and will respond to the programmed
I/O address range, DMA channels, and interrupts
that have been allocated to it.
CS4232 PnP Data
The CS4232 hardware configuration and Plug
and Play configuration data must be loaded into
the CS4232 RAM. The data may be stored in an
external E2PROM or may be downloaded from
the host.
To load the data, refer to the Loading Resource
Data section. The following is the CS4232 Plug
and Play resource data:
The first nine bytes of the PnP resource data are
the Plug and Play ID, which uniquely identifies
the CS4232 from other PnP devices. The Crystal
default is broken down as follows:
0Eh, 63h - Crystal ID - ’CSC’ in compressed
ASCII. (See the PnP Spec for more
information)
16
42h, 32h - Crystal Product Number
01, 00, 00, 00 - Serial number. This can be
modified by each OEM to uniquely
identify their card.
D3h - Checksum. Must be recalculated if the
serial number is changed.
Crystal software uses the first four bytes to indicate the presence of the CS4232 part; therefore,
the first four bytes must not be altered from
those listed above.
The next 3 bytes are the PnP version number.
The default is version 1.0: 0Ah, 10h, 00h.
The next sequence of bytes are the ANSI identifier string. The default is: 82h, 07h, 00h,
’CS4232’, 00h.
The following logical device data must be entered using the PnP ISA Specification format.
The actual logical device values are found in Table 1.
Logical Device 0
Dependent Functions - See Table 1
ANSI String = "WSS/OPL/SB"
Logical Device 1
Dependent Functions - See Table 1
ANSI String = "GAME"
Logical Device 2
Dependent Functions - See Table 1
ANSI String = "CTRL"
Logical Device 3
Dependent Functions - See Table 1
ANSI String = "MPU"
Logical Device 4
Dependent Functions - See Table 1
ANSI String = "CD"
DS145PP5
CS4232
Physical Device
Logical Device
WSS
16-bit address
decode
0
I/O
Length
Alignment
IRQ
high true
edge sensitive
8-bit, count by
byte, type A
same
Synthesis
10-bit address
decode
SB Pro
10-bit address
decode
Game Port
10-bit address
decode
Control
16-bit address
decode
MPU401
10-bit address
decode
CD-ROM
10-bit address
decode
DMA
DMA
0
I/O
Length
Alignment
IRQ
0
I/O
Length
Alignment
1
I/O
Length
Alignment
2
I/O
Length
Alignment
IRQ
3
I/O
Length
Alignment
IRQ
4
I/O
Length
Alignment
IRQ
DMA
Best Choice
Acceptable
Choice 1
Compatible ID = PNPB007
534h-534h
100-FFCh
4
4
4
4
5
5,7,9,11,12,15
(SB share)
(SB share)
1
0, 1, 3
(SB Share)
(SB share)
0, 3
---Compatible ID = PNPB020
388h
100-3FCh
4
4
4
4
------Compatible ID = PNPB002
220h
100-3F0h
16
16
16
16
Compatible ID = PNPB02F
200h
100-3F8h
8
8
8
8
Sub optimal
Sub optimal
Choice 1
Choice 2
ANSI ID = WSS/OPL/SB
ANSI ID = GAME
ANSI ID = CTRL
100-FF8h
8
8
---Compatible ID = PNPB006
330h
100-3FCh
2
2
8
8
9
5,7,9,11,12,15
ANSI ID = MPU
ANSI ID = CD
100-3FCh
4
4
-------
---- Feature not supported in the listed configuration, but is supported through customization.
Table 1. Typical Plug and Play Resource Data
DS145PP5
17
CS4232
Loading Resource Data
The CS4232 provides a serial E2PROM interface
to allow user-programmable serial number and
resource data to be stored in an external
E2PROM. The interface is compatible with devices from a number of vendors and the size
may vary according to specific customer requirements. The largest configuration supported by
the CS4232 internal RAM is 256 bytes of combined hardware configuration and PnP resource
data. With the addition of the 4-byte header, the
maximum amount of E2PROM space used
would be 260 bytes. After power-up, the CS4232
looks for the existence of an E2PROM by reading the first two bytes from the E2PROM
interface. If the data from the E2PROM port
reads 55h and AAh, then the rest of the
E2PROM data is loaded into the CS4232 internal
RAM. If the first two bytes aren’t 55h and AAh,
then a "hostload" procedure must be used to load
the internal RAM. The Hostload procedure can
be found in the Hostload section. If the CS4232
is embedded in a motherboard, an external
E2PROM is not necessary, since the BIOS can
control the bootup sequence and ensure that a
Hostload sequence is performed prior to a PnP
sequence. If the CS4232 is installed on a plug-in
card, then an external E2PROM is strongly recommended to ensure that the proper PnP
resource data is loaded into the CS4232 internal
RAM prior to a PnP sequence. See the External
E2PROM section for more information on the
serial E2PROM interface and E2PROM programming.
18
The format for the data stored in the E2PROM is
as follows:
(CS4232 Hardware Configuration Data:)
2 bytes E2PROM validation: 55h, AAh
2 bytes length of resource data in E2PROM
7 bytes CS4232 hardware configuration
(Plug and Play Resource Data:)
9 bytes Plug and Play ID
3 bytes Plug and Play version number
Variable number of bytes of user defined
ASCII ID string
Logical Device 0 (Windows Sound System,
OPL3, Sound Blaster Pro) data
Logical Device 1 ( Game Port) data
Logical Device 2 ( Control) data
Logical Device 3 ( MPU-401) data
Logical Device 4 ( CD-ROM) data
End of Resource byte & checksum byte
A typical E2PROM data load, in assembly format, can be found in Appendix A.
The Crystal Key
A special Crystal key may be used to place the
CS4232 in the configuration mode. Once the
Crystal key has been initiated, new PnP default
resource data can be downloaded by a hostload
sequence, or an alternate method of programming the configuration registers may be used.
This alternate method is referred to as the
"SLAM" method. The SLAM method allows the
user to directly access the configuration registers, configure, and activate the chip, and then,
optionally, disable the PnP feature of the
DS145PP5
CS4232
CS4232. The SLAM method uses commands
that are similar to the PnP commands; however,
they are different since the user has direct access
to the configuration registers. To use the SLAM
method, see the Bypassing PnP section.
The Crystal Key cannot differentiate between
multiple CS4232 ICs; therefore, it should only
be used in systems that do not plan on supporting multiple CS4232 ICs. To support multiple
parts in a Plug-and-Play environment, the Plugand-Play isolation key should be used, since the
PnP 9-byte identifier can distinguish between
multiple CS4232 ICs.
The following 32 bytes, in hex, are the Crystal
key:
96, 35, 9A, CD, E6, F3, 79, BC,
5E, AF, 57, 2B, 15, 8A, C5, E2
F1, F8, 7C, 3E, 9F, 4F, 27, 13,
09, 84, 42, A1, D0, 68, 34, 1A
3. Host programs the configuration registers of
each logical device by writing to I/O 0279h.
The following data is the maximum amount
of information per device. All current devices
only need a subset of this data:
Logical Device ID (15h, xxh)
I/O Port Base Address 0 (47h, xxh, xxh)
high byte , low byte
I/O Port Base Address 1 (48h, xxh, xxh)
high byte , low byte
I/O Port Base Address 2 (42h, xxh, xxh)
high byte , low byte
Interrupt Select 0 (22h, xxh)
Interrupt Select 1 (27h, xxh)
DMA Select 0 (2Ah, xxh)
DMA Select 1 (25h, xxh)
Activate Device (33h, 01h)
Bypassing Plug and Play
The SLAM method allows the user to bypass the
Plug and Play features, and, optionally, act like a
non-Plug and Play or legacy device; however,
the SLAM method only supports one CS4232 IC
per system. The user directly programs the resources into the CS4232, and then optionally
disables the PnP feature, which forces the
CS4232 to disregard any future PnP initiation
key sequences (All activated logical devices appear as legacy devices to PnP). The CS4232 will
still respond to the Crystal key.
To use the SLAM method, the following sequence must be followed:
1. Host sends 32-byte Crystal key to I/O
0279h, chip enters configuration mode.
4. Repeat #3 for each logical device to be enabled. (Not all devices need be enabled.)
5. Host activates chip/card by writing a 79h to
I/O 0279h .
6. (Optional) Host disables CS4232 PnP feature
by writing a 55h to CTRLbase+5. The
CS4232 will not participate in any future PnP
cycles.
NOTE: To enable the PnP feature after it has
been disabled by the SLAM method, the
CS4232 must be reset by bringing RESDRV
pin to a logic high or by removing power
from the device.
2. Host programs CSN (Card Select Number)
by writing a 06h and xxh to I/O 0279h.
DS145PP5
19
CS4232
The following illustrates typical data sent to the
CS4232 using the SLAM method.
006h, 001h
; CSN=1
015h, 000h
047h, 005h, 034h
048h, 003h, 088h
042h, 002h, 020h
022h, 005h
02Ah, 001h
025h, 003h
033h, 001h
; LOGICAL DEVICE 0
; WSSbase = 0x534
; SYNbase = 0x388
; SBbase = 0x220
; WSS & SB IRQ = 5
; WSS & SB DMA0 = 1
; WSS capture DMA1 = 3
; activate logical device 0
015h, 001h
; LOGICAL DEVICE 1
047h, 002h, 000h ; GAMEbase = 0x200
033h, 001h
; activate logical device 1
015h, 002h
; LOGICAL DEVICE 2
047h, 001h, 020h ; CTRLbase = 0x120
033h, 001h
; activate logical device 2
015h, 003h
; LOGICAL DEVICE 3
047h, 003h, 030h ; MPUbase=0x330
022h, 009h
; MPU IRQ = 9
033h, 001h
; activate logical device 3
079h
; activate CS4232 part
If all the above data is sent to the CS4232, after
the Crystal key, all devices except the CDROM
will respond to the appropriate resources given.
Hardware Configuration Data
The hardware configuration data, or resource
header, contains mapping information that links
interrupt and DMA pins with actual interrupt
numbers used by PnP and SLAM procedures. In
the current silicon, this mapping is fixed and
should not be changed. Future products will allow remapping of the hardware. This data also
controls the XCTL0/XA2 pin functionality. The
hardware configuration data is a resource header
on top of the PnP resource data.
20
The resource header is either seven or eleven
bytes long and contains the data necessary to
configure the CS4232 hardware. If an E2PROM
is not used (Hostload), the first four bytes are
not part of the header, which means the header is
only seven bytes long. The resource header maps
the many functions of the logical devices to the
physical pins of the CS4232 chip. Table 2 contains the CS4232 hardware configuration data.
The first actual byte of hardware resource data is
byte 5 in Table 2. This byte determines the function of the XCTL0/XA2 pin. The default of 0,
forces the pin to the control function XCTL0,
and the external peripheral port supports only 4
I/O locations through XA0-XA1. If this byte is
set to 008h, the pin switches to the XA2 function and the peripheral port supports 8 I/O
locations through XA0-XA2. When using the
hostload procedure, this byte is loaded second,
not first.
The next byte, listed as byte 6, will allow future
support of mixer mapping. This feature is not
currently implemented; therefore, this byte must
be 48h for current silicon. When using the hostload procedure, this byte is loaded first, not
second.
Bytes 7 through 9 map the interrupt number to
the actual interrupt pins A - F. This feature is not
currently supported. The default data must not be
changed.
Bytes 10 and 11 map the DMA channel number
to the actual DMA pins A-C. This feature is not
currently supported. The default data must not be
changed.
DS145PP5
CS4232
BYTE
1
Default
55h
2
3*
4
5†
AAh
00h
DDh
00h
6*†
48h
7*
75h
8*
9*
10*
B9h
FCh
10h
11*
03h
Description
E2PROM validation byte 1.
The first two bytes tell the CS4232 that the E2PROM exists.
E2PROM validation byte 2
High byte for length of resource data in E2PROM- Reserved, must be 00
Low byte for length of resource data in E2PROM
External Peripheral Port I/O Decode Address Length 00 = 4 bytes, 08 = 8 bytes
008h causes XCTL0/XA2 pin to change to peripheral port address bit XA2.
Mixer Mapping B7/6 for LINE, B5/4 for AUX1, B3/2 for AUX2, B1/0 - reserved = 0
Value: 0 - Line In, 1 - FM/SYNTH, 2 - CD, 3 - other
IRQ A/B Selection: Lower nibble = A, Upper nibble = B.
Along with next two bytes - specify hardware interrupts tied to CS4232 pins
IRQ C/D Selection: Lower nibble = C, Upper nibble = D.
IRQ E/F Selection: Lower nibble = E, Upper nibble = F.
DMA A/B Selection: Lower nibble = A, Upper nibble = B.
This byte and the next byte - specify hardware DRQ/DACKs tied to the CS4232 pins
DMA C Selection: Lower nibble = C, Upper nibble = reserved (must be 0).
NOTE:The first four bytes are exclusive to the E2PROM and are not used in the Hostload mode.
* Currently not supported. Must be set to default values given in the table.
† Byte 5 and 6 must be swapped when loading the CS4232 IC directly - Hostload procedure
Table 2. Hardware Resource Data
Hostload Procedure
To download PnP resource data from the host, as
opposed to the E2PROM, to the CS4232 internal
RAM, use the following sequence:
1. Configure Control I/O base address,
CTRLbase, by one of two methods: regular
PnP cycle or Crystal Key method.
a. The host can use the regular PnP cycle to
program the CTRLbase, and then place the
chip in the wait_for_key_state
b. If the Crystal Key method is used:
First, send the 32-byte Crystal key to I/O
address 0279h. (The Crystal Key only
supports one CS4232 IC per system.)
DS145PP5
Second, configure logical device 2 base
address, CTRLbase, by writing to I/O
0279h (15h, 02h, 47h, xxh, xxh, 33h,
01h, 79h).
Note: The two xxh represent the base_address_high and base_address_low
respectively. The default is: 01h, 20h.
2. Download the PnP resource data.
a. Send download command by writing AAh
to CTRLbase+5.
b. Send starting download address (2090h)
by writing low byte (90h) first, and then
high byte (20h) to CTRLbase+5.
c. Send the resource data in successive bytes
to CTRLbase+5. This includes the hardware configuration header and the PnP
resource data. The PnP resource format is
described in the CS4232 PnP Data section.
The resource header should not contain the
first four bytes which are only used for
21
CS4232
E2PROM loads. Bytes 5 and 6 in Table 2
must be swapped when using the hostload
procedure.
d . End download by writing 00h to
CTRLbase+6.
e. If any of the Hardware Configuration
Data (first 7 bytes) has changed, 5Ah
must be written to CTRLbase+5 to force
the CS4232 to internally update this information.
The new PnP data is loaded and CS4232 is ready
for the next PnP cycle.
External E2PROM
The Plug and Play specification defines 32 bits
of the 72 bit Serial Identifier as being a user defined serial number. To support this function, an
interface to an external serial E2PROM is provided. The E2PROM also stores default resource
data for PnP, and hardware configuration data
specific to the CS4232 IC.
The interface is compatible with devices from a
number of vendors, such as Xicor’s X24C02. After power-on the CS4232 IC looks for the
existence of an E2PROM device and loads the
user defined data. This data is read by the PnP
software as part of the 72-bit Serial Identifier
during the Plug and Play Isolation sequence.
The maximum resource data supported by the
CS4232 is 256 bytes, and a four byte header;
therefore, the maximum amount of data storage
in E2PROM would be 260 bytes. If an external
E2PROM exists, it is accessed by the serial interface and is connected to the CS4232 XD0 and
XA0 pins. The two-wire interface is controlled
by three bits in the Control logical device, Hardware Control Register (CTRLbase+1). The serial
data can be written to or read from the E2PROM
by sequentially writing or reading that register.
The three register bits, D0, D1, D2 are labeled
CLK, DOUT, and DIN/EEN respectively. The
22
DIN/EEN bit, when written to a one, enables the
E2PROM serial interface. When the DIN/EEN
bit is written to a zero, the serial interface is disabled. The DIN/EEN bit can also be used to read
back data from the E2PROM. The XD0 pin is a
bi-directional open-drain data line supporting
DIN and DOUT; therefore, to read the correct
data, the DOUT bit must be set to a one prior to
performing a read of the register. Otherwise, the
data read back from DIN/EEN will be all zeros.
The E2PROM data can then be read from the
DIN/EEN bit. The CLK bit timing is controlled
by the host software. This is the clock for the
E2PROM. The DOUT bit is used to write/program the data out to the E2PROM. An external
pull-up resistor is required on XD0 because it is
an open-drain output. Use the guidelines in the
specific E2PROM data sheet to select the value
of the pull-up resistor.
Programming the E2PROM:
1. Configure Control I/O base address by one
of two methods: regular PnP cycle or Crystal
Key method.
a. The host can use the regular PnP cycle to
program the logical device 2 I/O base address, and then place the chip in the
wait_for_key_state
b. If the Crystal Key method is used:
First, write to I/O 0279h, send the 32byte Crystal key. (The Crystal Key only
supports one CS4232 IC per system.)
Second, configure the Control I/O base
address by writing 15h, 02h, 47h, 01h,
20h, 33h, 01h, 79h to 0279h.
2. Refer to the specific data sheet for the
E2PROM you are using for timing requirements and data format. Also, refer to the
Loading Resource Data section of this data
sheet for the E2PROM resource data format.
DS145PP5
CS4232
3. Send the E2PROM data in successive bits to
CTRLbase+1 (Hardware Control Register)
while following the E2PROM data sheet format.
The E2PROM now contains the PnP resource
data. For this new data to take effect, the
CS4232 must be reset, causing the CS4232 to
read the E2PROM during initialization.
WINDOWS SOUND SYSTEM CODEC
The WSS Codec software interface consists of 4
I/O locations starting at the Plug and Play address ’WSSbase’, and supports 12-bit address
decoding. If the upper address bits, SA12-SA15
are used, they must be 0 to decode a valid address. The WSS Codec also requires one
interrupt and one or preferably two DMA channels, one for playback and one for capture. Since
the WSS Codec and Sound Blaster device are
mutually exclusive, the two devices share the
same interrupt and DMA playback channel.
The WSS Codec/Mixer is register compatible
with the Microsoft Windows Sound System.
Functions include stereo Analog-to-Digital and
Digital-to-Analog converters (ADCs and DACs),
analog mixing, anti-aliasing and reconstruction
filters, line and microphone level inputs, optional
A-Law/µ-Law coding, simultaneous capture and
playback (at the same sample rates) and a parallel bus interface. Five analog inputs are provided
and three can be multiplexed to the ADC. The
line input, two auxiliary inputs and a mono input
can be mixed with the output of the DAC with
full volume control. Several data modes are supported including 8- and 16-bit linear as well as
8-bit companded, 4-bit ADPCM compressed, and
16-bit big Endian.
Enhanced Functions (MODE 2)
The CS4232’s initial state is labeled MODE 1
and forces the CS4232 to appear as a CS4248.
Enhanced functionality is provided by a second
mode on the CS4232 which forces the CS4232
DS145PP5
to appear as a CS4231 super set. To switch from
MODE 1 to MODE 2, the MODE2 bit should be
set to one in the MODE and ID register (I12).
When MODE 2 is selected, the bit IA4 in the
Index Address register (R0) will be decoded as a
valid index pointer providing 16 additional registers and increased functionality over the CS4248.
To reverse the procedure, clear the MODE2 bit
and the CS4232 will resume operation in
MODE 1. Except for the Capture Data Format
(I28), Capture Base Count (I30/31), and Alternate Feature Status (I24) registers, all other
Mode 2 functions retain their values when returning to Mode 1. The CS4232’s WSS Codec is
backwards compatible with the CS4231 and
CS4248.
The additional MODE 2 functions are:
1. Full-Duplex DMA support
2. A programmable timer
3. Mono output with mute control
4. Mono input with mixer volume control
5. ADPCM and Big Endian audio data formats
6. Independent selection of capture and playback
audio data formats
FIFOs
The WSS Codec contains 16-sample FIFOs in
both the playback and capture digital audio data
paths. The FIFOs are transparent and have no
programming associated with them.
When playback is enabled, the playback FIFO
continually requests data until the FIFO is full,
and then makes requests as positions inside the
FIFO are emptied, thereby keeping the playback
FIFO as full as possible. Thus when the system
cannot respond within a sample period, the FIFO
23
CS4232
starts to empty, avoiding a momentary loss of
audio data. If the FIFO runs out of data, the last
valid sample can be continuously output to the
DACs (if DACZ in I16 is set) which will eliminate pops from occurring.
When capture is enabled, the capture FIFO tries
to continually stay empty by making requests
every sample period. Thus when the system cannot respond within a sample period, the capture
FIFO starts filling, thereby avoiding a loss of
data in the audio data stream.
WSS Codec PIO Register Interface
Four I/O mapped locations are available for accessing the Codec functions and mixer. The
control registers allow access to status, audio
data, and all indirect registers via the index registers. The IOR and IOW signals are used to
define the read and write cycles respectively. A
PIO access to the Codec begins when the host
puts an address on to the ISA bus which matches
WSSbase and drives AEN low. WSSbase is programmed during a Plug and Play configuration
sequence. Once a valid base address has been
decoded then the assertion of IOR will cause the
WSS Codec to drive data on the ISA data bus
lines. Write cycles require the host to assert data
on the ISA data bus lines and strobe the IOW
signal. The WSS Codec will latch data into the
PIO register on the rising edge of the IOW
strobe.
The audio data interface typically uses DMA request/grant pins to transfer the digital audio data
between the WSS Codec and the bus. The WSS
Codec is responsible for asserting a request signal whenever the Codec’s internal buffers need
updating. The bus responds with an acknowledge
signal and strobes data to and from the Codec, 8
bits at a time. The WSS Codec keeps the request
pin active until the appropriate number of 8-bit
cycles have occurred to transfer one audio sample. Note that different audio data types will
require a different number of 8-bit transfers.
24
DMA Interface
The second type of parallel bus cycle from the
WSS Codec is a DMA transfer. DMA cycles are
distinguished from PIO register cycles by the assertion of a DRQ, while AEN is inactive,
followed by an acknowledgment by the host by
the assertion of DACK. While the acknowledgment is received from the host, the WSS
Codec assumes that any cycles occurring are
DMA cycles and ignores the addresses on the
address lines.
The WSS Codec may assert the DMA request
signal at any time. Once asserted, the DMA request will remain asserted until a complete DMA
cycle occurs to the CS4232. DMA transfers may
be terminated by resetting the PEN and/or CEN
bits in the Interface Configuration register (I9),
depending on the DMA that is in progress (playback, capture, or both). Termination of DMA
transfers may only happen between sample transfers on the bus. If DRQ goes active while
resetting PEN and/or CEN, the request must be
acknowledged with DACK and a final sample
transfer completed.
DMA CHANNEL MAPPING
Mapping of the WSS Codec’s DRQ and DACK
onto the ISA bus is accomplished by the Plug
and Play configuration registers. If the Plug and
Play resource data specifies only one DMA
channel for the Codec (or the codec is placed in
SDC mode) then both the playback and capture
DMA requests should be routed to the same
DRQ/DACK pair (DMA Channel Select 0). If
the Plug and Play resource data specifies two
DMA channels for the Codec, then the playback
DMA request will be routed to the DMA pair
specified by the DMA Channel Select 0 resource
data, and the capture DMA requests will be
routed to the DMA pair specified by the DMA
Channel Select 1 resource data.
DS145PP5
CS4232
DUAL DMA CHANNEL MODE
The WSS Codec supports a single and a dual
DMA channel mode. In dual DMA channel
mode, playback and capture DMA requests and
acknowledges occur on independent DMA channels. In dual DMA mode, SDC should be set to
0. The Playback- and Capture-Enables (PEN,
CEN, I9) can be changed without a Mode
Change Enable (MCE, R0). This allows for
proper full duplex control where applications are
independently using playback and capture.
SINGLE DMA CHANNEL (SDC) MODE
When two DMA channels are not available, the
SDC mode forces all DMA transfers (capture or
playback) to occur on a single DMA channel
(playback channel). The trade-off is that the
WSS Codec will no longer be able to perform
simultaneous DMA capture and playback.
To enable the SDC mode, set the SDC bit in the
Interface Configuration register (I9). With the
SDC bit asserted, the internal workings of the
WSS Codec remain exactly the same as dual
mode, except for the manner in which DMA request and acknowledges are handled.
The playback of audio data will occur on the
playback channel exactly as dual channel operation; however, the capture audio channel is now
diverted to the playback channel. Alternatively
stated, the capture DMA request occurs on DMA
channel select 0 for the WSS Codec. (In
MODE 2, the capture data format is always set
in register I28.) If both playback and capture are
enabled, the default will be playback. SDC does
not have any affect when using PIO accesses.
DS145PP5
25
CS4232
Sound System Codec Register Interface
The Windows Sound System codec is mapped
via four locations. The I/O base address,
WSSbase, is determined by the Plug and Play
configuration. The WSSbase supports four direct
registers, shown in Table 3. The first two direct
registers are used to access 32 indirect registers
shown in Table 4. The Index Address register
(WSSbase+0) points to the indirect register that
is accessed through the Indexed Data register
(WSSbase+1).
This section describes all the direct and indirect
registers for the WSS Codec. Table 5 details a
summary of each bit in each register with Tables 6 through 11 illustrating the majority of
decoding needed when programming the WSS
portion of the CS4232, and are included for reference. Tables 6 through 8 indicate gain settings
at internal nodes. When enabled, the WSS Codec
default state is defined as MODE 1. MODE 1 is
backwards compatible with the CS4248 and only
allows access to the first 16 indirect registers.
Setting the MODE2 bit in the MODE and ID
register (I12) enables MODE 2 which allows access to indirect registers 16 through 31 and
enables all the features of the WSS Codec.
DIRECT MAPPED REGISTERS
The first two WSS Codec registers provide indirect accessing to more codec registers via an
index register. The other two registers provide
status information and allow audio data to be
transferred to and from the WSS Codec without
using DMA cycles or indexing.
Note that register defaults are listed in binary
form with reserved bits marked with ’x’ to indicate unknown. To maintain compatibility with
future parts, these bits must be written as 0, and
must be masked off when the register is read.
The current value read for reserved bits is not
guaranteed on future revisions.
Address
WSSbase+0
WSSbase+1
WSSbase+2
WSSbase+3
Reg.
R0
R1
R2
R3
Register Name
Index Address register
Indexed Data register
Status register
PIO Data register
Table 3. WSS Codec Direct Register
Index
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
I13
I14
I15
I16
I17
I18
I19
I20
I21
I22
I23
I24
I25
I26
I27
I28
I29
I30
I31
Register Name
Left ADC Input Control
Right ADC Input Control
Left Aux #1 Input Control
Right Aux #1 Input Control
Left Aux #2 Input Control
Right Aux #2 Input Control
Left DAC Output Control
Right DAC Output Control
Fs & Playback Data Format
Interface Configuration
Pin Control
Error Status and Initialization
MODE and ID (MODE2 bit)
Loopback Control
Playback Upper Base Count
Playback Lower Base Count
Alternate Feature Enable I
Alternate Feature Enable II
Left Line Input Control
Right Line Input Control
Timer Low Byte
Timer High Byte
Alternate Sample Frequency
Alternate Feature Enable III
Alternate Feature Status
Version/Chip ID
Mono Input & Output Control
Left Output Attenuation Control
Capture Data Format
Right Output Attenuation Control
Capture Upper Base Count
Capture Lower Base Count
Table 4. WSS Codec Indirect Registers
26
DS145PP5
CS4232
During initialization and software power down
(PM1,0 = 01), this register CANNOT be written
and always reads 10000000 (80h)
Index Address Register
(WSSbase+0, R0)
D7
D6
D5
D4
D3
D2
D1
D0
INIT
MCE
TRD
IA4
IA3
IA2
IA1
IA0
IA3-IA0
IA4
TRD
Index Address: These bits define the
address of the indirect register accessed by the Indexed Data register
(R1). These bits are read/write.
Allows access to indirect registers 16
- 31. Only available in MODE 2. In
MODE 1, this bit is reserved.
Transfer Request Disable: This bit,
when set, causes DMA transfers to
cease when the INT bit of the Status
Register (R2) is set. Independent for
playback and capture interrupts.
0 - Transfers Enabled (playback and
capture DRQs occur uninhibited)
1 - Transfers Disabled (playback and
capture DRQ only occur if INT bit
is 0)
MCE
INIT
D7
D6
D5
D4
D3
D2
D1
D0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
ID7-ID0
WSS Codec Initialization: This bit is
read as 1 when the Codec is in a
state in which it cannot respond to
parallel interface cycles. This bit is
read-only.
Indexed Data register: These bits are
the indirect register referenced by
the Indexed Address register (R0).
During initialization and software power down
of the WSS Codec, this register can NOT be
written and is always read 10000000 (80h)
Status Register
(WSSbase+2, R2, Read Only)
D7
D6
D5
D4
CU/L CL/R CRDY SER
INT
Mode Change Enable: This bit must
be set whenever the current mode
of the WSS Codec is changed. The
Data Format (I8, I28) and Interface
Configuration (I9) registers CANNOT
be changed unless this bit is set.
The exceptions are CEN and PEN
which can be changed "on-the-fly".
The DAC output is muted when
MCE is set.
Immediately after RESET (and once the WSS
Codec has left the INIT state), the state of this
register is: 010x0000 (binary - where ’x’ indicates unknown).
DS145PP5
Indexed Data Register
(WSSbase+1, R1)
D3
PU/L
D2
D1
PL/R PRDY
D0
INT
Interrupt Status: This indicates the
status of the internal interrupt logic
of the WSS Codec. This bit is
cleared by any write of any value to
this register. The IEN bit of the Pin
Control register (I10) determines
whether the state of this bit is reflected on the IRQ pin assigned to
the WSS Codec.
Read States
0 - Interrupt inactive
1 - Interrupt active
PRDY
Playback Data Ready. The Playback
Data register (R3) is ready for more
data. This bit would be used when direct programmed I/O data transfers
are desired.
0 - Data still valid. Do not overwrite.
1 - Data stale. Ready for next host
data write value.
27
CS4232
Direct Registers: WSSbase (R0-R3)
ADDRESS
WSSbase+0 R0
WSSbase+1 R1
WSSbase+2 R2
WSSbase+3 R3
D7
INIT
ID7
CU/L
CD7/PD7
D6
MCE
ID6
CL/R
CD6/PD6
D5
TRD
ID5
CRDY
CD5/PD5
D4
†
IA4
ID4
SER
CD4/PD4
D3
D2
D1
D0
IA3
ID3
PU/L
CD3/PD3
IA2
ID2
PL/R
CD2/PD2
IA1
ID1
PRDY
CD1/PD1
IA0
ID0
INT
CD0/PD0
Indirect Registers: (I0-I31)
IA4-IA0
D7
D6
D5
D4
D3
D2
D1
D0
LSS1
LSS0
LMGE
LAG3
LAG2
LAG1
LAG0
0
RSS1
RSS0
RMGE
RAG3
RAG2
RAG1
RAG0
1
LX1M
LX1G4
LX1G3
LX1G2
LX1G1
LX1G0
2
RX1M
RX1G4
RX1G3
RX1G2
RX1G1
RX1G0
3
LX2M
LX2G4
LX2G3
LX2G2
LX2G1
LX2G0
4
RX2M
RX2G4
RX2G3
RX2G2
RX2G1
RX2G0
5
LDM
LDA5
LDA4
LDA3
LDA2
LDA1
LDA0
6
RDM
RDA5
RDA4
RDA3
RDA2
RDA1
RDA0
7
FMT1†
FMT0
C/L
S/M
CSF2
CSF1
CSF0
C2SL
8§
CPIO
PPIO
CAL1
CAL0
SDC
CEN
PEN
9§
XCTL1
XCTL0
OSM1
OSM0
DEN
DTM†
IEN
10
COR
PUR
ACI
DRS
ORR1
ORR0
ORL1
ORL0
11
1
MODE2
ID3
ID2
ID1
ID0
12
LBA5
LBA4
LBA3
LBA2
LBA1
LBA0
LBE
13
PUB7
PUB6
PUB5
PUB4
PUB3
PUB2
PUB1
PUB0
14 *
PLB7
PLB6
PLB5
PLB4
PLB3
PLB2
PLB1
PLB0
15 *
OLB
TE
CMCE
PMCE
SF1
SF0
SPE
DACZ
16 §
TEST
TEST
TEST
TEST
APAR
XTALE
HPF
17
LLM
LLG4
LLG3
LLG2
LLG1
LLG0
18
RLM
RLG4
RLG3
RLG2
RLG1
RLG0
19
TL7
TL6
TL5
TL4
TL3
TL2
TL1
TL0
20
TU7
TU6
TU5
TU4
TU3
TU2
TU1
TU0
21
SRE
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
CS2
22
ACF
23
TI
CI
PI
CU
CO
PO
PU
24
V2
V1
V0
CID2
CID1
CID0
25
MIM
MOM
MBY
MIA3
MIA2
MIA1
MIA0
26
LOM
LOA3
LOA2
LOA1
LOA0
27
FMT1
FMT0
C/L
S/M
28 §
ROM
ROA3
ROA2
ROA1
ROA0
29
CUB7
CUB6
CUB5
CUB4
CUB3
CUB2
CUB1
CUB0
30
CLB7
CLB6
CLB5
CLB4
CLB3
CLB2
CLB1
CLB0
31
† IA4, FMT1, and DTM bits are only available in MODE 2; therefore, regs. 16-31 are only available in MODE 2.
* When in MODE 1, the playback base registers (upper and lower) are used for both playback and capture.
§ For I8, MCE must be set to modify the lower 4 bits. MCE or PMCE must be set to modify the upper 4 bits.
For I9, MCE must be set to modify the upper 6 bits. PEN and CEN can be changed anytime.
For I16, MCE must be set to modify the serial port bits: SF1, SF0, and SPE.
For I28, MCE or CMCE must be set to modify the upper 4 bits.
Table 5. WSS Codec Register Bit Summery
28
DS145PP5
CS4232
bit3
0
0
0
0
.
.
.
1
1
1
1
0
1
2
3
.
.
.
12
13
14
15
bit2
0
0
0
0
.
.
.
1
1
1
1
bit1
0
0
1
1
.
.
.
0
0
1
1
bit0
0
1
0
1
.
.
.
0
1
0
1
Input Gain (I0,I1)
0.0 dB
1.5 dB
3.0 dB
4.5 dB
18.0 dB
19.5 dB
21.0 dB
22.5 dB
Mono In (I26)
0.0 dB
-3.0 dB
-6.0 dB
-9.0 dB
.
.
.
-36.0 dB
-39.0 dB
-42.0 dB
-45.0 dB
Output Att. (I27,I29)
0.0 dB
-2.0 dB
-4.0 dB
-6.0 dB
-24 dB
-26 dB
-28 dB
-30 dB
Table 6. Input Gain, Output Atten., and Mono In Levels
0
1
2
3
.
.
.
60
61
62
63
A5
0
0
0
0
.
.
.
1
1
1
1
A4
0
0
0
0
.
.
.
1
1
1
1
A3
0
0
0
0
.
.
.
1
1
1
1
A2
0
0
0
0
.
.
.
1
1
1
1
A1
0
0
1
1
.
.
.
0
0
1
1
A0
0
1
0
1
.
.
.
0
1
0
1
Level
0.0 dB
-1.5 dB
-3.0 dB
-4.5 dB
.
.
.
-90.0 dB
-91.5 dB
-93.0 dB
-94.5 dB
Table 7. DAC & Loopback Attenuation
0
1
2
3
SS1
0
0
1
1
SS0
0
1
0
1
ADC Input Multiplexer
Line
Auxiliary 1
Microphone
Line Output Loopback
Table 9. ADC Input Selector
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
.
.
.
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
10
11
12
.
.
.
24
25
26
27
28
29
30
31
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
.
.
.
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
.
.
.
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
.
.
.
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
.
.
.
0
1
0
1
0
1
0
1
Level
12.0 dB
10.5 dB
9.0 dB
7.5 dB
6.0 dB
4.5 dB
3.0 dB
1.5 dB
0.0 dB
-1.5 dB
-3.0 dB
-4.5 dB
-6.0 dB
.
.
.
-24.0 dB
-25.5 dB
-27.0 dB
-28.5 dB
-30.0 dB
-31.5 dB
-33.0 dB
-34.5 dB
Table 8. AUX1, AUX2, & LINE Mixer Gain
2
0
0
0
0
1
1
1
1
CSF
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
XTAL1
24.576 MHz
8.0 kHz
16.0 kHz
27.42 kHz
32.0 kHz
N/A
N/A
48.0 kHz
9.6 kHz
XTAL2
16.9344 MHz
5.51 kHz
11.025 kHz
18.9 kHz
22.05 kHz
37.8 kHz
44.1 kHz
33.075 kHz
6.62 kHz
Table 10. Sample Frequencies
DS145PP5
FMT1
FMT0 C/L
0
0
0
0
0
1
0
1
0
0
1
1
1
0
1
1
1
0
Data Format
Linear, 8-bit unsigned
µ-Law, 8-bit companded
Linear, 16-bit two’s
complement, Little Endian
A-Law, 8-bit companded
ADPCM, 4-bit, IMA compatible
Linear, 16-bit two’s
complement, Big Endian
Table 11. WSS Codec Data Format
29
CS4232
PL/R
Playback Left/Right Sample: This bit
indicates whether data needed is for
the Left channel or Right channel in
all data formats except ADPCM. In
ADPCM it indicates whether the first
two or last two bytes of a 4-byte set
(8 ADPCM samples) are needed.
CL/R
0 - Right or 3/4 ADPCM byte needed
1 - Left, Mono, or 1/2 ADPCM byte
needed
PU/L
Playback Upper/Lower Byte: This bit
indicates whether the playback data
needed is for the upper or lower
byte of the channel. In ADPCM it indicates, along with PL/R, which one
of the four ADPCM bytes is needed.
0 - Lower or 1/3 ADPCM byte needed
1 - Upper, any 8-bit format, or 2/4
ADPCM byte needed.
SER
CRDY
Sample Error: This bit indicates that a
sample was not serviced in time and
an error has occurred. The bit indicates an overrun for capture and
underrun for playback. If both the
capture and playback are enabled,
the source which set this bit can not
be determined. However, the Alternate Feature Status register (I24)
can indicate the exact source of the
error.
Capture Data Ready. The Capture
Data register (R3) contains data
ready for reading by the host. This
bit would be used for direct programmed I/O data transfers.
0 - Data is stale. Do not reread the
information.
1 - Data is fresh. Ready for next
host data read.
30
Capture Left/Right Sample: This bit
indicates whether the capture data
waiting is for the Left channel or
Right channel in all audio data formats except ADPCM. In ADPCM it
indicates whether the first two or last
two bytes of a 4-byte set (8 ADPCM
samples) are waiting.
0 - Right or 3/4 ADPCM byte available
1 - Left, Mono, or 1/2 ADPCM byte
available
CU/L
Capture Upper/Lower Byte: This bit
indicates whether the capture data
ready is for the upper or lower byte
of the channel. In ADPCM it indicates, along with CL/R, which one of
four ADPCM bytes is available.
0 - Lower or 1/3 ADPCM byte
available
1 - Upper, any 8-bit format, or 2/4
ADPCM byte available
Note on PRDY/CRDY: These two bits are designed to be read as one when action is required
by the host. For example, when PRDY is set to
one, the device is ready for more data; or when
the CRDY is set to one, data is available to the
host. The definition of the CRDY and PRDY bits
are therefore consistent in this regard.
I/O DATA REGISTERS
The PIO Data register is two registers mapped to
the same address. Writes to this register sends
data to the Playback Data register. Reads from
this register will receive data from the Capture
Data register.
During initialization and software power down
of the WSS Codec, this register CANNOT be
written and is always read 10000000 (80h)
DS145PP5
CS4232
Capture I/O Data Register
(WSSbase+3, R3, Read Only)
D7
D6
D5
D4
D3
D2
D1
D0
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
CD7-CD0
Capture Data Port. This is the control
register where capture data is read
during programmed I/O data transfers.
The reading of this register will increment the
state machine so that the following read will be
from the next appropriate byte in the sample.
The exact byte which is next to be read can be
determined by reading the Status register (R2).
Once all relevant bytes have been read, the state
machine will point to the last byte of the sample
until a new sample is received from the ADCs.
Once the Status register (R2) is read and a new
sample is received from the FIFO, the state machine and Status register (R2) will point to the
first byte of the new sample.
During initialization and software power down
of the WSS Codec, this register can NOT be
written and is always read 10000000 (80h)
Playback I/O Data Register
WSSbase+3, R3, Write Only)
D7
D6
D5
D4
D3
D2
D1
D0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PD7-PD0
Playback Data Port. This is the control
register where playback data is
written during programmed IO data
transfers.
INDIRECT MAPPED REGISTERS
These registers are accessed by placing the appropriate index in the Index Address register
(R0) and then accessing the Indexed Data register (R1). A detailed description of each indirect
register is given below. All reserved bits should
be written zero and may be 0 or 1 when read.
Note that indirect registers 16-31 are only available when the MODE2 bit in MODE and ID
register (I12) is set.
Left ADC Input Control (I0)
Default = 000x0000
D7
D6
D5
D4
LSS1 LSS0 LMGE res
D3
D2
D1
D0
LAG3
LAG2
LAG1
LAG0
LAG3-LAG0
Left ADC Gain. The least significant
bit represents +1.5 dB, with
0000 = 0 dB. See Table 6.
res
Reserved. Must write 0. Could read
as 0 or 1.
LMGE
Left Mic Gain Enable: This bit enables
the 20 dB gain stage of the left mic
input signal, LMIC.
LSS1-LSS0
Left ADC Input Source Select. These
bits select the input source for the
left ADC channel.
0
1
2
3
-
Left Line: LLINE
Left Auxiliary 1: LAUX1
Left Microphone: LMIC
Left Line Output Loopback
Writing data to this register will increment the
playback byte tracking state machine so that the
following write will be to the correct byte of the
sample. Once all bytes of a sample have been
written, subsequent byte writes to this port are
ignored. The state machine is reset after the
Status register (R2) is read, and the current sample is sent to the DACs via the FIFOs.
DS145PP5
31
CS4232
Right ADC Input Control (I1)
Default = 000x0000
D7
D6
D5
D4
D3
Right Auxiliary #1 Input Control (I3)
Default = 1xx01000
D2
D1
D0
RSS1 RSS0 RMGE res RAG3 RAG2 RAG1 RAG0
RAG3-RAG0
Right ADC Gain. The least significant
bit represents +1.5 dB, with
0000 = 0 dB. See Table 6.
res
Reserved. Must write 0. Could read
as 0 or 1.
RMGE
Right Mic Gain Enable: This bit
enables the 20 dB gain stage of the
right mic input signal, RMIC.
RSS1-RSS0
Right ADC Input Select. These bits
select the input source for the right
ADC channel.
0
1
2
3
-
Right Line: RLINE
Right Auxiliary 1: RAUX1
Right Microphone: RMIC
Right Line Out Loopback
D6 D5
D4
D3
D2
D1
D6 D5
D4
D3
D2
D1
D0
RX1G4-RX1G0 Right Auxiliary #1, RAUX1, Mix Gain.
The least significant bit represents
1.5 dB, with 01000 = 0 dB. See Table 8.
res
Reserved. Must write 0. Could read
as 0 or 1.
RX1M
Right Auxiliary #1 Mute. When set to
1, the right Auxiliary #1 input,
RAUX1, to the mixer, is muted.
Left Auxiliary #2 Input Control (I4)
Default = 1xx01000
D7
D6 D5
D4
D3
D2
D1
D0
LX2M res res LX2G4 LX2G3 LX2G2 LX2G1 LX2G0
LX2G4-LX2G0 Left Auxiliary #2, LAUX2, Mix Gain.
The least significant bit represents
1.5 dB, with 01000 = 0 dB. See Table 8.
Left Auxiliary #1 Input Control (I2)
Default = 1xx01000
D7
D7
RX1M res res RX1G4 RX1G3 RX1G2 RX1G1 RX1G0
D0
res
Reserved. Must write 0.
LX2M
Left Auxiliary #2 Mute. When set to 1,
the left Auxiliary #2 input, LAUX2, to
the mixer, is muted.
LX1M res res LX1G4 LX1G3 LX1G2 LX1G1 LX1G0
LX1G4-LX1G0 Left Auxiliary #1, LAUX1, Mix Gain.
The least significant bit represents
1.5 dB, with 01000 = 0 dB. See Table 8.
res
Reserved. Must write 0. Could read
as 0 or 1.
Right Auxiliary #2 Input Control (I5)
Default = 1xx01000
D7
D6 D5
D4
D3
D2
D1
D0
RX2M res res RX2G4 RX2G3 RX2G2 RX2G1 RX2G0
LX1M
32
Left Auxiliary #1 Mute. When set to 1,
the left Auxiliary #1 input, LAUX1, to
the mixer, is muted.
RX2G4-RX2G0 Right Auxiliary #2, RAUX2, Mix Gain.
The least significant bit represents
1.5 dB, with 01000 = 0 dB. See Table 8.
res
Reserved. Must write 0. Could read
as 0 or 1.
RX2M
Right Auxiliary #2 Mute. When set to
1, the right Auxiliary #2 input,
RAUX2, to the mixer, is muted.
DS145PP5
CS4232
CFS2-CFS0
Left DAC Output Control (I6)
Default = 1x000000
D7
LDM
D6
D5
res LDA5
D4
D3
D2
D1
D0
LDA4
LDA3
LDA2
LDA1
LDA0
LDA5-LDA0
Left DAC Attenuator. The least significant bit represents -1.5 dB, with
000000 = 0 dB. See Table 7.
res
Reserved. Must write 0. Could read
as 0 or 1.
LDM
Left DAC Mute. When set to 1, the
left DAC output to the mixer will be
muted.
Right DAC Output Control (I7)
Default = 1x000000
D7
D6
D5
D4
D3
D2
D1
Divide
0 - 3072
1 - 1536
2 - 896
3 - 768
4 - 448
5 - 384
6 - 512
7 - 2560
D0
RDM res RDA5 RDA4 RDA3 RDA2 RDA1 RDA0
RDA5-RDA0
Right DAC Attenuator. The least significant bit represents -1.5 dB, with
000000 = 0 dB. See Table 7.
res
Reserved. Must write 0. Could read
as 0 or 1.
RDM
Right DAC Mute. When set to 1, the
right DAC output to the mixer will be
muted.
Fs and Playback Data Format (I8)
Default = 00000000
D7
D6
FMT1 FMT0
C2SL
D5
D4
C/L
S/M
D2
D1
D0
Clock 2 Source Select: This bit selects
the clock source used for the audio
sample rates for both capture and
playback. Note that this bit can be
disabled by setting SRE in I22.
CAUTION: C2SL can only be
changed while MCE (R0) is set.
0 - XTAL1
1 - XTAL2
DS145PP5
D3
CSF2 CSF1 CSF0 C2SL
Typically 24.576 MHz
Typically 16.9344 MHz
S/M
Clock Frequency Divide Select: These
bits select the audio sample frequency for both capture and
playback. The actual audio sample
frequency depends on which clock
source (C2SL) is selected and its frequency. Frequencies listed as N/A
are not available because their sample frequency violates the maximum
specifications; however, the decodes
are available and may be used with
crystals that do not violate the sample frequency specifications. Note
that these bits can be disabled and
controlled by bits in I22.
CAUTION: CFS2-CFS0 can only be
changed while MCE (R0) is set.
XTAL1
24.576 MHz
8.0 kHz
16.0 kHz
27.42 kHz
32.0 kHz
N/A
N/A
48.0 kHz
9.6 kHz
XTAL2
16.9344 MHz
5.51 kHz
11.025 kHz
18.9 kHz
22.05 kHz
37.8 kHz
44.1 kHz
33.075 kHz
6.62 kHz
Stereo/Mono Select: This bit determines how the audio data streams
are formatted. Selecting stereo will
result in alternating samples representing left and right audio channels.
Mono playback plays the same
audio sample on both channels.
Mono capture only captures data
from the left channel. In MODE 1,
this bit is used for both playback and
capture. In MODE 2, this bit is only
used for playback, and the capture
format is independently selected via
I28. MCE (R0) or PMCE (I16) must
be set to modify S/M. See Changing
Audio Data Formats section for
more details.
0 - Mono
1 - Stereo
33
CS4232
C/L, FMT1, and FMT0 bits set the audio data format
as shown below. In MODE 1, FMT1,
which is forced low, FMT0, and C/L
are used for both playback and capture. In MODE 2, these bits are only
used for playback, and the capture
format is independently selected via
register I28. MCE (R0) or PMCE
(I16) must be set to modify the lower
four bits of this register. See Changing Audio Data Formats section for
more details.
FMT1† FMT0 C/L
D7
D6
D5
0
0
0
0
0
1
0
1
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
1
CEN
0 - Capture Disabled (capture DRQ
and PIO inactive)
1 - Capture Enabled
SDC
Audio Data Format
Linear, 8-bit unsigned
µ-Law, 8-bit companded
Linear, 16-bit two’s
complement, Little Endian
A-Law, 8-bit companded
RESERVED
ADPCM, 4-bit, IMA compatible
Linear, 16-bit two’s
complement, Big Endian
RESERVED
Interface Configuration (I9)
Default = 00x01000
D7
D6
CPIO PPIO
PEN
D5
res
D4
D3
CAL1 CAL0
D2
D1
D0
SDC
CEN
PEN
Playback Enable. This bit enables
playback. The WSS Codec will
generate a DRQ and respond to
DACK signal when this bit is enabled and PPIO=0. If PPIO=1, PEN
enables PIO playback mode. PEN
may be set and reset without setting
the MCE bit.
0 - Playback Disabled (playback DRQ
and PIO inactive)
1 - Playback Enabled
Single DMA Channel: This bit will force
BOTH capture and playback DMA requests to occur on the Playback
DMA channel. This bit forces the
WSS Codec to use one DMA channel. Should both capture and
playback be enabled in this mode,
only the playback will occur. See the
DMA Interface section for further explanation.
0 - Dual DMA channel mode
1 - Single DMA channel mode
CAL1,0
† FMT1 is not available in MODE 1 (forced to 0).
Capture Enabled. This bit enables the
capture of data. The WSS Codec
will generate a DRQ and respond to
DACK signal when CEN is enabled
and CPIO=0. If CPIO=1, CEN enables PIO capture mode. CEN may
be set and reset without setting the
MCE bit.
Calibration: These bits determine
which type of calibration the WSS
Codec performs whenever the Mode
Change Enable (MCE) bit, R0,
changes from 1 to 0. The number of
sample periods required for calibration is listed in parenthesis.
0
1
2
3
PPIO
-
No calibration (0, 40 the first time)
Converter calibration (136)
DAC calibration (40)
Full calibration (168)
Playback PIO Enable: This bit determines whether the playback data is
transferred via DMA or PIO.
0 - DMA transfers
1 - PIO transfers
CPIO
Capture PIO Enable: This bit determines whether the capture data is
transferred via DMA or PIO.
0 - DMA transfers
1 - PIO transfers
34
DS145PP5
CS4232
Caution: This register, except bits CEN and
PEN, can only be written while in Mode Change
Enable (either MCE or PMCE). See the Changing Sampling Rate section for more details..
XCTL1-XCTL0 XCTL Control: These bits are reflected
on the XCTL1,0 pins of the CS4232.
NOTE: These pins are multiplexed
with other functions; therefore, they
may not be available on a particular
design.
Pin Control (I10)
Default = 0000000x
D7
D6
D5
XCTL1
XCTL0
OSM1
res
IEN
0 - TTL logic low on XCTL1,0 pins
1 - TTL logic high on XCTL1,0 pins
D4
D3 D2 D1 D0
OSM0 DEN DTM IEN res
Reserved. Must write 0. Could read
as 0 or 1.
Interrupt Enable: This bit enables the
interrupt pin. The Interrupt pin will reflect the value of the INT bit of the
Status register (R2). The interrupt
pin is active high.
Error Status and Initialization (I11, Read Only)
Default = 00000000
D7
D6
D5
COR
PUR
ACI
ORL1-ORL0
0 - Interrupt disabled
1 - Interrupt enabled
DTM
DEN
DMA Timing Mode. Mode 2 only.
When set, causes the current DMA
request signal to be deasserted on
the rising edge of the IOW or IOR
strobe during the next to last byte of
a DMA transfer. When DTM = 0 the
DMA request is released on the falling edge of the IOW or IOR during
the last byte of a DMA transfer.
Dither Enable: When set, triangular
pdf dither is added before truncating
the ADC 16-bit value to 8-bit, unsigned data. Dither is only active in
the 8-bit unsigned data mode.
These bits are enabled by setting
SRE = 1 in I22. These bits in combination with DIV5-DIV0 and CS2
(I22) determine the current sample
rate of the WSS Codec when
SRE = 1
00 - 12kHz < Fs ≤ 24kHz
01 - Fs > 24kHz
10 - Fs ≤ 12kHz
11 - reserved
DS145PP5
D3
D2
D1
D0
Overrange Left Detect: These bits
determine the overrange on the left
ADC channel. These bits are updated on a sample by sample basis.
0 - Less than -1.5 dB
1 - Between -1.5 dB and 0 dB
2 - Between 0 dB and 1.5 dB
overrange
3 - Greater than 1.5 dB overrange
ORR1-ORR0
Overrange Right Detect: These bits
determine the overrange on the
Right ADC channel.
0 - Less than -1.5 dB
1 - Between -1.5 dB and 0 dB
2 - Between 0 dB and 1.5 dB
overrange
3 - Greater than 1.5 dB overrange
DRS
0 - Dither enabled
1 - Dither disabled
OSM1-OSM0
D4
DRS ORR1 ORR0 ORL1 ORL0
DRQ Status: This bit indicates the
current status of the DRQs assigned
to the WSS Codec.
0 - Capture AND Playback DRQs are
presently inactive
1 - Capture OR Playback DRQs are
presently active
ACI
Auto-calibrate In-Progress: This bit
indicates the state of calibration.
0 - Calibration not in progress
1 - Calibration is in progress
35
CS4232
PUR
Playback underrun: This bit is set
when playback data has not arrived
from the host in time to be played.
As a result, if DACZ = 0, the last
valid sample will be sent to the
DACs. This bit is set when an error
occurs and will not clear until the
Status register (R2) is read.
COR
Capture overrun: This bit is set when
the capture data has not been read
by the host before the next sample
arrives. The old sample will not be
overwritten and the new sample will
be ignored. This bit is set when an
error condition occurs and will not
clear until the Status register (R2) is
read.
Loopback Control (I13)
Default = 000000x0
D7
D6
LBE
D4
D3
D2
D1
D0
res
LBE
Loopback Enable: When set to 1, the
ADC data is digitally mixed with data
sent to the DACs.
0 - Loopback disabled
1 - Loopback enabled
res
Reserved. Must write 0. Could read
as 0 or 1.
LBA5-LBA0
Loopback Attenuation: These bits
determine the attenuation of the loopback from ADC to DAC. The least
significant bit represents -1.5 dB,
with 000000 = 0 dB. See Table 7.
The SER bit in the Status register (R2) is simply
a logical OR of the COR and PUR bits. This
enables a polling host CPU to detect an error
condition while checking other status bits.
Playback Upper Base (I14)
Default = 00000000
MODE and ID (I12)
Default = 10xx1010
D7
D7
D6
D5 D4
D3
D2
D1
D0
1
MODE2
res res
ID3
ID2
ID1
ID0
D6
Codec ID: These four bits indicate the
ID and initial revisions of the codec.
Further revisions are expanded in indirect register 25. These bits are
read only.
0001 - Rev B CS4248/CS4231
1010 - Rev C CS4248/CS4231 and
all CS4232s. See register 25
res
Reserved. Must write 0. Could read
as 0 or 1.
MODE2
MODE 2: Enables the expanded mode
of the CS4232. Must be set to enable access to indirect registers
16-31 and their associated features.
D5
D4
D3
D2
D1
D0
PUB7 PUB6 PUB5 PUB4 PUB3 PUB2 PUB1 PUB0
PUB7-PUB0
ID3-ID0
D5
LBA5 LBA4 LBA3 LBA2 LBA1 LBA0
Playback Upper Base: This register is
the upper byte which represents the
8 most significant bits of the 16-bit
Playback Base register. Reads from
this register return the same value
which was written. The Current
Count registers cannot be read.
When set for MODE 1 or SDC, this
register is used for both the Playback and Capture Base registers.
0 - MODE 1: CS4248 "look-alike".
1 - MODE 2: Expanded features.
36
DS145PP5
CS4232
PMCE
Playback Mode Change Enable.
When set, it allows modification of
the stereo/mono and audio data format bits (D7-D4) for the playback
channel, I8. MCE in R0 must be
used to change the sample frequency.
CMCE
Capture Mode Change Enable.
When set, it allows modification of
the stereo/mono and audio data format bits (D7-D4) for the capture
channel, I28. MCE in R0 must be
used to change the sample frequency in I8.
TE
Timer Enable: This bit, when set, will
enable the timer to run and interrupt
the host at the specified frequency
in the timer registers.
OLB
Output Level Bit: Provided for backwards compatibility. OLB on the
CS4232 is always set internally providing a typical output full-scale
voltage of 2.8 Vpp.
Playback Lower Base (I15)
Default = 00000000
D7
D6
D5
D4
D3
D2
D1
D0
PLB7 PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 PLB0
PLB7-PLB0
Lower Base Bits: This register is the
lower byte which represents the 8
least significant bits of the 16-bit
Playback Base register. Reads from
this register return the same value
which was written. When set for
MODE 1 or SDC, this register is
used for both the Playback and Capture Base registers.
Alternate Feature Enable I (I16)
Default = 00000000
D7
D6
OLB
TE
DACZ
D3
D2
D1
CMCE PMCE SF1
D5
D4
SF0
SPE DACZ
D0
DAC Zero: This bit will force the output of the playback channel to AC
zero when an underrun error occurs
1 - Go to center scale
0 - Hold previous valid sample
SPE
Serial Port Enable. When enabled,
audio data from the ADCs is sent
out SDOUT and audio data from
SDIN is sent to the DACs.
Alternate Feature Enable II (I17)
Default = 0000x000
D7
HPF
1 - Enable serial port
0 - Disable serial port. ISA Bus
used for audio data.
SF1,SF0
Serial Format. Selects the format of
the serial port when enabled by SPE.
0
1
2
3
DS145PP5
-
64-bit enhanced. Figure 6.
64-bit. Figure 7.
32-bit. Figure 8.
Reserved
D6
D5
D4
D3
TEST TEST TEST TEST APAR
D2
D1
D0
res XTALE HPF
High Pass Filter: This bit enables a
DC-blocking high-pass filter in the
digital filter of the ADC. This filter
forces the ADC offset to 0.
0 - disabled
1 - enabled
XTALE
Crystal Enable. Provided for backwards compatibility with the
CS4231A. Both crystals are always
active on the CS4232.
res
Reserved. Must write 0. Could read
as 0 or 1.
APAR
ADPCM Playback Accumulator Reset.
While set, the Playback ADPCM
accumulator is held at zero. Used
when pausing a playback stream.
37
CS4232
TEST
Factory Test. These bits are used for
factory testing and must remain at 0
for normal operation.
Left Line Input Control (I18)
Default = 1xx01000
D7
D6
D5
LLM
res
res
D4
D3
D2
D1
D0
Left Line, LLINE, Mix Gain. The least
significant bit represents 1.5 dB, with
01000 = 0 dB. See Table 8.
res
Reserved. Must write 0. Could read
as 0 or 1.
LLM
Left Line Mute. When set to 1, the left
Line input, LLINE, to the mixer, is
muted.
Right Line Input Control (I19)
Default = 1xx01000
D7
D6
D5
res
res
D7
D6
D5
D4
D3
D2
D1
D0
TL7
TL6
TL5
TL4
TL3
TL2
TL1
TL0
TL7-TL0
Lower Timer Bits: This is the low order
byte of the 16-bit timer base register.
Writes to this register cause both
timer base registers to be loaded
into the internal timer; therefore, the
upper timer register should be
loaded before the lower. Once the
count reaches zero, an interrupt is
generated, if enabled, and the timer
is automatically reloaded with these
base registers.
LLG4 LLG3 LLG2 LLG1 LLG0
LLG4-LLG0
RLM
Timer Lower Base (I20)
Default = 00000000
D4
D3
D2
D1
Timer Upper Base (I21)
Default = 00000000
D7
D6
D5
D4
D3
D2
D1
D0
TU7
TU6
TU5
TU4
TU3
TU2
TU1
TU0
D0
RLG4 RLG3 RLG2 RLG1 RLG0
RLG4-RLG0
Right Line, RLINE, Mix Gain. The least
significant bit represents 1.5 dB, with
01000 = 0 dB. See Table 8.
Upper Timer Bits: This is the high
order byte of the 16-bit timer. The
time base is determined by the clock
source selected from either C2SL in
I8 or CS2 in I22.
res
Reserved. Must write 0. Could read
as 0 or 1.
C2SL = 0 - divide XTAL1 by 245
(24.576 MHz - 9.969 µs)
RLM
Right Line Mute. When set to 1, the
Right Line input, RLINE, to the
mixer, is muted.
C2SL = 1 - divide XTAL2 by 168
(16.9344 MHz - 9.92 µs)
38
TU7-TU0
DS145PP5
CS4232
Alternate Sample Frequency Select (I22)
Default = 00000000
Alternate Feature Status (I24)
Default = x0000000
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SRE
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
CS2
res
TI
CI
PI
CU
CO
PO
PU
CS2
Crystal 2 Select. This bit selects the
clock source used for generating the
audio sample rate.
0 - XTAL1 = 24.576 MHz
1 - XTAL2 = 16.9344 MHz
DIV5 - DIV0
Clock Divider. These bits select the
audio sample frequency for both capture and playback.
Fs = (2*XTAL)/(M*N)
PU
Playback Underrun: This bit, when set,
indicates that the DAC has run out
of data and a sample has been
missed.
PO
Playback Overrun: This bit, when set,
indicates that the host attempted to
write data into a full FIFO and the
data was discarded.
CO
Capture Overrun: This bit, when set,
indicates that the ADC had a sample
to load into the FIFO but the FIFO
was full. In this case, this bit is set
and the new sample is discarded.
CU
Capture Underrun: This bit indicates
that the host has read more data out
of the FIFO than it contained. In this
condition, the bit is set and the last
valid byte is read by the host.
PI
Playback Interrupt: This bit indicates
that an interrupt is pending from the
playback DMA count registers.
CI
Capture Interrupt: This bit indicates
that an interrupt is pending from the
capture DMA count registers.
TI
Timer Interrupt: This bit indicates that
an interrupt is pending from the
timer count registers
res
Reserved. Must write 0. Could read
as 0 or 1.
XTAL = 24.576 MHz
CS2 = 0
XTAL = 16.9344 MHz CS2 = 1
N = DIV5-DIV0
16 ≤ N ≤ 49 for XTAL = 24.576 MHz
12 ≤ N ≤ 33 for XTAL = 16.9344 MHz
(M set by OSM1,0 in I10)
M = 64 for Fs > 24 kHz
M = 128 for 12 kHz < Fs ≤ 24 kHz
M = 256 for Fs ≤ 12 kHz
SRE
Alternate Sample Rate Enable. When
this bit is set to a one, bits 0-3 of I8
will be ignored, and the sample frequency is then determined by CS2,
DIV5-DIV0, and the oversampling
mode bits OSM1, OSM0 in I10.
Alternate Feature Enable III (I23)
Default = xxxxxxx0
D7
D6
D5
D4
D3
D2
D1
D0
res
res
res
res
res
res
res
ACF
ACF
ADPCM Capture Freeze. When set,
the capture ADPCM accumulator
and step size are frozen. This bit
must be set to zero for adaptation to
continue. This bit is used when
pausing a ADPCM capture stream.
res
Reserved. Must write 0. Could read
as 0 or 1.
DS145PP5
The PI, CI, and TI bits are reset by writing a "0"
to the particular interrupt bit or by writing any
value to the Status register (R2).
39
CS4232
MBY
Mono Bypass. MBY connects MIN
directly to MOUT with an attenuation
of 9 dB. When MBY = 1, MIM
should be 1.
Version / ID (I25)
Default = 101xx010
D7
D6
D5
D4
D3
D2
D1
D0
V2
V1
V0
res
res
CID2
CID1
CID0
V2-V0
Version number. As enhancements are
made to the CS4232, the version
number is changed so software can
distinguish between the different versions.
100 - non-released older version.
101 - 1st version, "C", of CS4232.
These bits are only changed if software features are added. Therefore,
future revisions; "D", etc., could
have the same version number.
res
Reserved. Must write 0. Could read
as 0 or 1.
CID2-CID0
Chip Identification. Distinguishes
between this chip and other codec
chips that support this register set.
010 - CS4232. This Data Sheet.
000 - CS4231 or CS4231A
D7
D6
D5
D4
MOM
MBY
res
MIA3-MIA0
res
40
D3
D2
MIA3 MIA2
D1
MOM
Mono Output Mute. The MOM bit will
mute the mono mix output, MOUT.
This mute is independent of the line
output mute.
0 - no mute
1 - mute
MIM
Mono Input Mute. Controls the mute
function on the mono input, MIN.
The mono input provides mix for the
"beeper" function in most personal
computers. When MIM = 0, MBY
should by 0.
0 - no mute
1 - muted
Left Output Attenuation (I27)
Default = 0xxx0000
Mono Input and Output Control (I26)
Default = 101x0000
MIM
0 - MIN not connected directly to
MOUT.
1 - MIN connected directly to MOUT.
D0
D7
D6
D5
D4
LOM
res
res
res
Reserved. Must write 0. Could read
as 0 or 1.
D2
D1
D0
LOA3-LOA0
Left Output Attenuation. LOA0 is the
least significant bit and represents
-2 dB attenuation, with 0000=0dB.
See Table 6.
res
Reserved. Must write 0. Could read
as 0 or 1.
LOM
Left Output Mute. The LOM bit will
mute the left output.
MIA1 MIA0
Mono Input Attenuation. When MIM
is 0, these bits set the level of MIN
summed into the mixer. MIA0 is the
least significant bit and represents
3 dB attenuation, with 0000 = 0 dB.
See Table 6.
D3
LOA3 LOA2 LOA1 LOA0
0 - no mute
1 - mute
DS145PP5
CS4232
Capture Data Format (I28)
Default = 0000xxxx
D7
D6
FMT1 FMT0
Right Output Attenuation (I29)
Default = 0xxx0000
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
C/L
S/M
res
res
res
res
ROM
res
res
res
res
Reserved. Must write 0. Could read
as 0 or 1.
S/M
Stereo/Mono Select: This bit determines how the capture audio data
stream is formatted. Selecting stereo
will result with alternating samples
representing left and right audio
channels. Selecting mono only captures data from the left audio
channel. MCE (R0) or CMCE (I16)
must be set to modify S/M. See
Changing Audio Data Formats section for more details.
0 - Mono
1 - Stereo
D2
D1
D0
ROA3-ROA0
Right Output Attenuation. ROA0 is the
least significant bit and represents
-2 dB attenuation, with 0000 = 0dB.
See Table 6.
res
Reserved. Must write 0. Could read
as 0 or 1.
ROM
Right Output Mute. The ROM bit
will mute the right output.
0 - no mute
1 - mute
Capture Upper Base (I30)
Default = 00000000
D7
C/L, FMT1, FMT0 set the capture data format in
MODE 2. See Table 11 or register I8
for the bit settings and data formats. The capture data format can
be different than the playback data
format; however, the sample frequency must be the same and is set
in I8. MCE (R0) or CMCE (I16) must
be set to modify this register. See
Changing Audio Data Formats section for more details.
D3
ROA3 ROA2 ROA1 ROA0
D6
D5
D4
D3
D2
D1
D0
CUB7 CUB6 CUB5 CUB4 CUB3 CUB2 CUB1 CUB0
CUB7-CUB0
Capture Upper Base: This register is
the upper byte which represents the
8 most significant bits of the 16-bit
Capture Base register. Reads from
this this register returns the same
value that was written.
Capture Lower Base (I31)
Default = 00000000
D7
D6
D5
D4
D3
D2
D1
D0
CLB7 CLB6 CLB5 CLB4 CLB3 CLB2 CLB1 CLB0
CLB7-CLB0
DS145PP5
Lower Base Bits: This register is the
lower byte which represents the 8
least significant bits of the 16-bit
Capture Base register. Reads from
this register returns the same value
which was written.
41
CS4232
SOUND BLASTER INTERFACE
The Sound Blaster Pro compatible interface is
the third physical device in logical device 0.
Since the WSS Codec and the Sound Blaster are
mutually exclusive, the WSS Codec interrupt
and playback DMA channel are shared with the
Sound Blaster interface. To map volume controls
properly, the external devices: FM synthesizer,
CDROM, etc., must be connected to the proper
analog inputs as illustrated in Figure 3.
Mode Switching
To facilitate switching between different functional modes (i.e. Sound Blaster and Windows
Sound System), logic is included in the CS4232
to handle the switch transparently to the host.
No special software is required on the host side
to perform the mode switch.
Sound Blaster Register Interface
The CS4232’s Sound Blaster software interface
utilizes 10-bit address decoding and is compatible with Sound Blaster and Sound Blaster Pro
interfaces. 10-bit addressing requires that the up-
Address
SBbase+0
SBbase+0
SBbase+1
SBbase+2
SBbase+2
SBbase+3
SBbase+4
SBbase+5
SBbase+6
SBbase+8
SBbase+8
SBbase+9
SBbase+A
SBbase+C
SBbase+C
SBbase+E
per address bits be 0 to decode a valid address,
i.e. no aliasing occurs. This device requires 16
I/O locations located at the PnP address
’SBbase’. The following registers, shown in Table 12 are provided for Sound Blaster
compatibility.
Left/Right FM Registers,
SBbase+0 - SBbase+3
These registers are mapped directly to the appropriate FM synthesizer registers on the external
peripheral port.
Mixer Address Register,
SBbase+4, write only
This register is used to specify the index address
for the mixer. This register must be written before any data is accessed from the mixer
registers. The mixer indirect register map is
shown in Table 13.
Mixer Data Port,
SBbase+5
This port provides read/write access to a particular mixer register depending on the index
address specified in the Mixer Address Register.
Description
Left FM Status Port
Left FM Register Status Port
Left FM Data Port
Right FM Status Port
Right FM Register Status Port
Right FM Status Port
Mixer Register Address
Mixer Data Port
Reset
FM Status Port
FM Register port
FM Data Port
Read Data Port
Command/Write Data
Write Buffer Status (Bit 7)
Data Available Status (Bit 7)
Type
Read
Write
Write Only
Read
Write
Write Only
Write Only
Read/Write
Write Only
Read Only
Write
Write Only
Read Only
Write
Read
Read
Table 12. Sound Blaster Pro Compatible I/O Interface
42
DS145PP5
CS4232
Reset
SBbase+6, write only
When bit D[0] of this register is set to a one and
then set to a zero a reset of the Sound Blaster
interface will occur.
Read Data Port
SBbase+A, read only
When bit D[7] of the Data Available Register,
SBbase+E, is set =1 then valid data is available
in this register. The data may be the result of a
Command that was previously written to the
Command/Write Data Register or digital audio
data.
Command/Write Data
SBbase+C, write only
The Command/Write Data register is used to
send Sound Blaster commands to the SBPro interface.
Write Buffer Status,
SBbase+C, read only
The Write Buffer Status register bit D[7] indicates when the SBPro interface is ready to
accept another command to the Command/Write
Data register. D[7]=1 indicates ready. D[7]=0 indicates not ready.
SOUND BLASTER MIXER REGISTERS
The Sound Blaster mixer registers, shown in Table 13 are shadowed and mapped into the WSS
Codec mixer register set. The Sound Blaster
mixer to WSS Codec mixer mapping is shown in
Figure 3.
Reset Register,
Mixer Index 00H
Writing any value to this register will reset the
mixer to default values.
DS145PP5
Voice Volume Register,
Mixer Index 04H, Default = 99H
This register provides 8 steps of voice volume
control each for the right and left channels.
Microphone Mixing Register,
Mixer Index 0AH, Default = 01H
This register provides 4 steps of microphone mix
control.
Input Control Register,
Mixer Index 0CH
This register selects the input source to the ADC.
D2,D1 - 00 - Microphone
01 - CD Audio
10 - Microphone
11 - Line In
Output Control Register,
Mixer Index 0EH
VSTC - 0 - Mono Mode
1 - Stereo Mode
Master Volume Register,
Mixer Index 22H, Default 99H
This register provides 8 steps of master volume
control each for the right and left channels.
FM Volume Register,
Mixer Index 26H, Default = 99H
This register provides 8 steps of FM volume
control each for the right and left channels.
CD Volume Register,
Mixer Index 28H, Default 01H
This register provides 8 steps of CD volume
control each for the right and left channels.
Line-In Volume Register,
Mixer Index 2EH, Default = 01H
This register provides 8 steps of line-in volume
control each for the right and left channels.
43
CS4232
MIC
LINE
FM
MIC
V
O
L
AUX1
LINE
A
D
C
CD
VOL
DIG
ATTN
A
U
X
1
A
U
X
2
Σ
LINE OUT
L
I
N
E
DIG VOICE
Σ
PC SPEAKER
D
A
C
MONO IN
V
O
L
V
O
L
Figure 3. SBPro Mixer Mapping
Register
00H
02H
04H
06H
08H
0AH
0CH
0EH
20H
22H
24H
26H
28H
2AH
2CH
2EH
D7
D6
D5
D4
D3
DATA RESET
RESERVED
VOICE VOLUME LEFT
X
X
X
X
X
X
X
X
D2
D1
D0
VOICE VOLUME RIGHT
RESERVED
RESERVED
X
X
X
X
X
RESERVED
MASTER VOLUME LEFT
MIC MIXING
INPUT SELECT
X
VSTC
X
X
MASTER VOLUME RIGHT
RESERVED
FM VOLUME LEFT
CD VOLUME LEFT
FM VOLUME RIGHT
CD VOLUME RIGHT
RESERVED
RESERVED
LINE VOLUME LEFT
LINE VOLUME RIGHT
Table 13. SBPro Compatible Mixer Interface
44
DS145PP5
CS4232
GAME PORT INTERFACE
The Game Port logical device software interface
utilizes 10-bit address decoding and is located at
PnP address ’GAMEbase’. 10-bit addressing requires that the upper address bits be 0 to decode
a valid address, i.e. no aliasing occurs. For backwards compatibility, the Game Port consists of 8
I/O locations that all alias to the same location,
which consists of one read and one write register.
Plug and Play configuration capability will allow
the joystick I/O base address, GAMEbase, to be
located anywhere within the host I/O address
space. Currently most games software assume
that the joystick I/O port is located at 200h.
Two bits are located in the Control register space
(CTRLbase+0) for defining the speed of the
Game Port Interface. Four different rates are
software selectable for use with various joysticks
and to support older software timing loops with
aliasing (roll-over) problems.
The Game Port hardware interface consists of 8
pins that connect directly to the standard game
port connector. For a detailed hardware description, see the CRD4232-1 Reference Design Data
Sheet.
A write to the GAMEbase register triggers four
timers. A read from the same register returns
four status bits corresponding to the joystick fire
buttons and four bits that correspond to the output from the four timers. Each timer output
remains low for a period of time determined by
the current joystick position.
GAMEbase+0 - GAMEbase+7
D7
D6
D5
D4
D3
D2
D1
D0
JBB2 JBB1 JAB2 JAB1 JBCY JBCX JACY JACX
JACX
Joystick A, Coordinate X
JACY
Joystick A, Coordinate Y
JBCX
Joystick B, Coordinate X
JBCY
Joystick B, Coordinate Y
JAB1
Joystick A, Button 1
JAB2
Joystick A, Button 2
JBB1
Joystick B, Button 1
JBB2
Joystick B, Button 2
DS145PP5
45
CS4232
CONTROL INTERFACE
PDP*
The Control logical device includes registers for
controlling various functions of the CS4232 that
are not included in the other logical device
blocks. These functions include game port rate
control and programmable power management,
as well as extra mixing functions.
Power Down Processor. When set,
places the internal processor in an
idle state. This effects the PnP interface, MPU401, and SBPro devices.
CONSW
controls host interrupt generation
when a context switch occurs
Control Register Interface
The Control logical device software interface occupies 8 I/O locations, utilizes 12-bit address
decoding, and is located at PnP address
’CTRLbase’. If the upper address bits, SA12SA15 are used, they must be 0 to decode a valid
address. This device can also support an interrupt. Table 14 lists the eight Control registers.
Register
Joystick & Power Control
E2PROM Interface & Mixer
Reserved
Reserved
Reserved
Control/Ram Access
Ram Access End
Reserved
Address
CTRLbase+0
CTRLbase+1
CTRLbase+2
CTRLbase+3
CTRLbase+4
CTRLbase+5
CTRLbase+6
CTRLbase+7
Table 14. Control Logical Device Registers
Joystick and Power Control
CTRLbase + 0, Default = 000xxx00
D7
D6
D5
PM1 PM0 CONSW
JR1,0
D4
D3
D2
D1 D0
res
PDP
res
JR1 JR0
Joystick rate control. Selects operating
speed of the joystick.
00 - slowest speed
01 - medium slow speed
10 - medium fast speed
11 - fastest speed
res
46
Reserved. Must write 0. Could read
as 0 or 1.
0 - no interrupt on context switch
1 - Control interrupt generated on
context switch
PM1,0
Power Management. The bits allow
different sections of the CS4232 IC
to power down while still retaining
the PnP data and interface.
00 - All functions active. Typ. 102mA.
01 - A/D and D/A powered down.
Mixer still active. Typ. 74mA.
10 - Reserved
11* - WSS Codec, SBPro, MPU401,
and PnP interfaces, and the analog
mixer are powered down.
Typically 30mA.
* NOTE: The SBPro, PnP, and MPU401 interfaces
are linked together. Setting PM1,0 or
PDP will power all three interfaces
down; however, if any one of the interfaces is written to, they will all
power back up automatically. PM1,0
and PDP always reflects the value
written, not whether the three devices are powered up or not.
E2PROM Interface & Mixer
CTRLbase+1, Default = xx00x000
D7
D6
D5
D4
D3
res
res
ADC1
ADC0
res
D2
D1
DIN/ DOUT
EEN
D0
CLK
CLK
This bit is used to generate the clock
for the Plug and Play E2PROM.
EEN must be set to 1 to make this
bit operational.
DOUT
This bit is used to output serial data
to the Plug and Play E2PROM. EEN
must be set to 1 to make this bit operational.
DS145PP5
CS4232
DIN/EEN
When read (DIN), this bit reflects
the XD0 pin, which should be serial
data output from the Plug and Play
E2PROM. EEN and DOUT must be
1 for this bit to function.
When written (EEN), enables the
E2PROM interface: CLK and DOUT
onto the CS4232 peripheral port
pins. Writing:
0 - E2PROM interface disabled
1 - E2PROM interface enabled
ADC1,0
These two bits are used to control
an additional A/D mux and enable
for an analog loopback path. These
two mixing paths provide Karaoke
support on the CS4232. See Figure 4.
00 - Normal. A/D input from the input
mux.
01 - Codec Input mux is mixed into
output mixer. A/D input is from
the input mux. This facilitates the
Mic mixed to output, but only Mic
recorded.
10 - Codec Input mux is mixed into
output mixer. A/D input is from
line outputs. This facilitates the Mic
mixed to output, and the output
recorded by the ADCs.
11 - reserved.
res
Reserved. Must write 0. Could read
as 0 or 1.
Reserved
CTRLbase+2, Default = xxxxxxxx
D7
D6
D5
D4
D3
D2
D1
D0
res
res
res
res
res
res
res
res
res
Reserved. Could read as 0 or 1.
D7
D6
D5
D4
D3
D2
D1
D0
res
res
res
res
res
res
res
res
DS145PP5
Reserved. Could read as 0 or 1.
Reserved
CTRLbase+4, Default = xxxxxxxx
D7
D6
D5
D4
D3
D2
D1
D0
res
res
res
res
res
res
res
res
res
Reserved. Could read as 0 or 1.
Control/RAM Access
CTRLbase+5, Default = xxxxxxxx
D7
D6
D5
D4
D3
D2
D1
D0
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
CR7-CR0
Reserved
CTRLbase+3, Default = xxxxxxxx
res
Figure 4. Mixer Addition
This register controls the loading of
CS4232 internal RAM. RAM support
includes hardware configuration and
PnP default resource data, as well
as program memory. See the Hostload Procedure section for more
information. Commands are followed
by address and data.
47
CS4232
RAM Access End
CTRLbase+6, Default = xxxxxxxx
D7
D6
D5
D4
D3
D2
D1
D0
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
RE7-RE0
A 00 written to this location resets the
previous location, CTRLbase+5,
from data download to command
mode.
Reserved
CTRLbase+7, Default = xxxxxxxx
MIDI Transmit/Receive Port,
MPUbase+0, default = xxxxxxxx
D7
D6
D5
D4
D3
D2
D1
D0
TR7
TR6
TR5
TR4
TR3
TR2
TR1
TR0
TR7-TR0
D7
D6
D5
D4
D3
D2
D1
D0
res
res
res
res
res
res
res
res
res
MPUbase+0 is the MIDI Transmit/Receive port
and MPUbase+1 is the Command/Status port. In
addition to I/O decodes the only additional functionality required from an ISA bus viewpoint is
the generation of a hardware interrupt whenever
data has been received into the receive buffer.
Reserved. Could read as 0 or 1.
MPU-401 INTERFACE
The MPU-401 is an intelligent MIDI interface
that was introduced by Roland in 1984. Voyetra
Technologies subsequently introduced an IBMPC plug in card that incorporated the MPU-401
functionality. The MPU-401 has become the defacto standard for controlling MIDI devices via
IBM-PC compatible personal computers.
Although the MPU-401 does have some intelligence, a non-intelligent mode is available in
which the MPU-401 operates as a basic UART.
All MIDI transmit data is transferred through a
64-byte FIFO and receive data through a 16-byte
FIFO. The FIFO gives the ISA interface time to
respond to the asynchronous MIDI transfer rate
of 31.25K baud.
The Command/Status Registers occupy the same
address and are used to send instructions to and
receive status information from the MPU-401.
Command Register, write only
MPUbase+1
D7
D6
D5
D4
D3
D2
D1
D0
CS7
CS6
CS5
CS4
CS3
CS2
CS1
CS0
CS7-CS0
By incorporating hardware to emulate the MPU401 in UART mode, the CS4232 provides users
with MIDI capability.
MPU-401 Register Interface
The MPU401 logical device software interface
occupies 2 I/O locations, utilizes 10-bit address
decoding, and is located at PnP address
’MPUbase’. 10-bit addressing requires that the
upper address bits be 0 to decode a valid address, i.e. no aliasing occurs. The standard base
address is 330h. This device also requires an interrupt, typically 9.
48
The MIDI Transmit/Receive Port is
used to send and receive MIDI data
as well as status information that
was returned from a previously sent
command.
Each write to the Command/Status
Register must be monitored and the
appropriate acknowledge generated.
Status Register, read only
MPUbase+1, Default = xxxxxxxx
D7
D6
D5
D4
D3
D2
D1
D0
RXS
TXS
CS5
CS4
CS3
CS2
CS1
CS0
CS5-CS1
D0-D5 are the 6 LSBs of the last
command written to this port.
DS145PP5
CS4232
TXS
Transmit Buffer Status Flag.
0 - Transmit buffer not full
1 - Transmit buffer full
RXS
Receive Buffer Status Flag
0 - Data in Receive buffer
1 - Receive buffer empty
When in "UART" mode, data is received into the
receive buffer FIFO and a hardware interrupt is
generated. Data is can be received from two
sources: MIDI data via the UART serial input or
acknowledge data that is the result of a write to
the Command Register (MPUbase+1). The interrupt is cleared by a read of the MIDI Receive
Port (MPUbase+0).
MIDI UART
The UART is used to convert parallel data to the
serial data required by MIDI. The serial data rate
is fixed at 31.25K baud (±1%). The serial data
format is RS-232 like: 1 start bit, 8 data bits, and
1 stop bit.
The UART to MIDI external interface should be
comprised of a TTL buffer on the transmit line
and an off chip OPTO-ISOLATOR on the receive line. In multimedia systems, the MIDI pins
are typically connected to the joystick connector.
See the CRD4232-1 Reference Design Data
Sheet for detailed information.
MPU-401 "UART" Mode Operation
After power-up reset, the interface is in "nonUART" mode. Non-UART mode operation is
defined as follows:
1. All writes to the Transmit Port, MPUbase+0,
are ignored.
2. All reads of the Receive Port, MPUbase+0,
return the last received buffer data.
3. All writes to the Command Port, MPUbase+1,
are monitored and acknowledged as follows:
a. A write of 3Fh sets the interface into
UART operating mode. An acknowledge
is generated by putting an FEh into the
receive buffer FIFO which generates an
interrupt.
b. A write of A0-A7, ABh, ACh, ADh, AFh
places an FEh into the receive buffer
FIFO (which generates an interrupt) followed by a one byte write to the receive
buffer FIFO of 00h for A0-A7, and ABh
commands, 15h for ACh, 01h for ADh,
and 64h for AFh commands.
c. All other writes to the Command Port are
ignored and an acknowledge is generated by putting an FEh into the receive
buffer FIFO which generates an interrupt.
UART mode operation is defined as follows:
1. All writes to the Transmit Port, MPUbase+0,
are placed in the transmit buffer FIFO.
Whenever the transmit buffer FIFO is not
empty, the next byte is read from the buffer
and sent out the MIDOUT pin. The Status
Register, MPUbase+1, bit 6, TXS is updated
to reflect the transmit buffer FIFO status.
2. All reads of the Receive Port, MPUbase+0,
return the next byte in the receive buffer
FIFO. When serial data is received from the
MIDIN pin, it is placed in the next receive
buffer FIFO location. If the buffer is full,
the last location is overwritten with the new
data. The Status Register, MPUbase+1,
bit 7, RXS is updated to reflect the new receive buffer FIFO state.
3. A write to the Command Register,
MPUbase+1, of FFh will return the interface
to non-UART mode.
4. All other writes to the Command Register,
MPUbase+1, are ignored.
DS145PP5
49
CS4232
EXTERNAL PERIPHERAL PORT
An external peripheral port is provided for interfacing devices external to the CS4232. These
may include the OPL3 or CS9233 synthesizer,
CDROM interface, and Plug and Play E2PROM.
The External Peripheral Port consists of the following signals: 8-bit data bus, 2 or 3 address
lines, read strobe, write strobe, and reset signal.
Synthesizer Interface
The CS4232 supports the current FM type synthesizer chips such as the Yamaha OPL3, as well
as the Crystal Semiconductor CS9233 wave table synthesizer chip. This interface consists of:
SCS - chip select
SINT - Synthesizer Interrupt
The other signals such as address bits, data
strobes, data, and reset are provided by the External Peripheral Port. The interface allows the
host computer to access up to eight I/O mapped
locations. The synthesizer interface is compatible
with the Adlib and Sound Blaster standards. The
typical Adlib I/O address is SYNbase = 338h.
Since the typical FM interface only requires four
I/O address and does not use an interrupt, the
XA2 address and the SINT pins are multifunction pins that default to XCTL0 and XCTL1. To
use XCTL0/XA2 as an address pin, the hardware
resource data must be changed. See the Hardware Configuration Data section for more
information. To use XCTL1/SINT as an interrupt
for the synthesizer, a pulldown resistor must be
placed on the XIOW pin.
Standard Adlib Synthesizer I/O Map
Address
SYNbase+0
SYNbase+0
SYNbase+1
SYNbase+2
SYNbase+3
50
Name
FM Status
FM Address 0
FM Data 0
FM Address 1
FM Data 1
Type
Read Only
Write Only
Write Only
Write Only
Read Only
CDROM Interface
The CS4232 provides a typical CDROM controller interface that is compatible with the Sony,
Mitsumi, and with some external logic, the Panasonic CDROM drives. This interface includes a
programmable chip select and on-chip hardware
to map DMA and interrupt signals to the ISA
bus.
The four CDROM interface pins are multifunction pins that default to the upper address bits
SA12 - SA15. To use the pins as a CDROM interface, a pulldown resistor must be placed on
XIOR (XIOR must be buffered if driving TTL
logic). Secondly, the default address space for
the peripheral port is 4 I/O locations with
XCTL0/XA2 defaulting to the control pin
XCTL0. To use XCTL0/XA2 as the XA2 address pin, thereby increasing the address range of
the peripheral port to 8 locations, the hardware
resource data must be changed. See the Hardware Configuration Data section.
SERIAL AUDIO DATA PORT
The WSS Codec includes a serial audio interface
for transferring digital audio data between the
CS4232 and a external serial device such as a
DSP processor. The serial port connections exist
on the #2 joystick inputs of the Game Port interface. Once the serial port operation is enabled,
the second joystick function is no longer available.
The audio serial port is software enabled via the
SPE bit in the WSS Codec indirect register I16.
Once enabled, the data from the ADCs is sent to
the SDOUT pin and the audio data input on the
SDIN pin is routed to the DACs. The ISA interface is active in this mode to allow control of
volume and format control. While the serial port
is enabled, audio data may still be read from the
ADCs over the ISA bus, but the DACs only accept data from the SDIN pin.
DS145PP5
CS4232
FSYNC and SCLK are always output from the
CS4232 when the serial port is enabled. The serial port can be configured in one of three serial
port formats, shown in Figures 6-8. SF1 and SF0
in I16 select the particular format. Both left and
right audio words are always 16 bits wide with
the audio data left justified. (i.e. ADPCM occupies the first four bits). Unused bits are output as
zeros after the LSB. The justification is illustrated in Figure 5. When the mono audio format
is selected, the right channel output is set to zero
and the left channel input is sent to both DAC
channels.
The third serial format - SPF2, shown in Figure 8, is called 32-bit mode. This format has 32
SCLKs per frame and FSYNC is high for the
left channel and low for the right channel. The
absolute time is similar to the other two modes
but SCLK is stopped after the right channel is
finished. SCLK is held stopped until the start of
the next frame (stopped for 32 bit period times).
This mode is useful for DSPs that do not want
the interrupt overhead of the 32 unused bit periods. As an example, if a DSP serial word length
is 16 bits, then four interrupts will occur in SPF0
and SPF1 modes. In mode SPF2 the DSP will
only be interrupted twice.
The first format - SPF0, shown in Figure 6, is
called 64-bit enhanced. This format has 64
SCLK’s per frame with a one bit period wide
FSYNC that precedes the frame. The first 16 bits
occupy the left word and the second 16 bits occupy the right word. The last 32 bits contain four
status bits and 28 zeros. This is the only mode
that contains status information.
WSS CODEC SOFTWARE DESCRIPTION
The WSS Codec must be in Mode Change Enable Mode (MCE=1) before any changes to the
Interface Configuration register (I9) or the Sample Frequency (lower four bits) in the Fs &
Playback Data Format registers (I8) are allowed.
The actual audio data formats, which are the upper four bits of I8 for playback and I28 for
capture, can be changed by setting MCE (R0) or
PMCE/CMCE (I16) high. The exceptions are
CEN and PEN which can be changed "on-thefly" via programmed I/O writes to these bits. All
outstanding DMA transfers must be completed
before new values of CEN or PEN are recognized.
The second serial format - SPF1, shown in Figure 7, is called 64-bit mode. This format also has
64 SCLK’s per frame, but has FSYNC transitioning high at the start of the left data word and
low at the start of the right data word. Both the
left and right data words are followed by 16 zeros.
A u d io W o rd
B its
15
16
MSB
8
MSB
4
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LSB
LSB
X
X
X
LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X : S D IN - D o n 't c a re , S D O U T - 0
Figure 5. Serial Audio Data Justification
DS145PP5
51
CS4232
FSYNC
SCLK
SDOUT
...
15 14 13
... 0
12
16 Bits
Left Data
SDIN
15 14 13
...
15 14
8 zeros
0
IN T
7 zeros
16 Bits
Right Data
... 0
12
15 14
16 Bits
Left Data
...
13 zeros
CEN PEN OVR
32 Bits
0
16 Bits
Right Data
INT = Interrupt Bit
CEN = Capture Enable
PEN = Playback Enable
OVR = Left Overrange or
Right Overrange
Figure 6. 64-bit Enhanced Mode (SF1,0 = 00)
FSYNC
SCLK
SDOUT
15 14 13
...
0
15 14 13
16 C locks
16 C locks
...
0
16 C locks
Left D a ta
15
16 C locks
R ight D ata
Figure 7. 64-bit Mode (SF1,0 = 01)
FSYNC
SCLK
SDOUT
...
1 5 14 1 3
32 N o-C lo ck b it pe rio d s
...
...
0
16 C locks
15 1 4 1 3
...
0
...
15 1 4
1 6 C locks
Le ft D ata
R igh t D a ta
Le ft D a ta
Figure 8. 32-bit Mode (SF1,0 = 10)
52
DS145PP5
CS4232
Calibration
The WSS Codec has four different calibration
modes. The selected calibration occurs whenever the Mode Change Enable (MCE, R0) bit
goes form 1 to 0
The completion of calibration can be determined
by polling the Auto-Calibrate In-Progress bit in
the Error Status and Initialization register (ACI,
I11). This bit will be high while the calibration is
in progress and low once completed. Transfers
enabled during calibrate will not begin until the
calibration cycle has completed.
The Calibration procedure is as follows:
1) Place the CS4232 in Mode Change Enable using the MCE bit of the Index Address
register (R0).
2) Set the CAL1,0 bits in the Interface Configuration register (I9).
3) Return from Mode Change Enable by resetting the MCE bit of the Index Address
register (R0).
4) Wait until 80h NOT returned
5) Wait until ACI (I11) cleared to proceed
NO CALIBRATION (CAL1,0 = 00)
This is the fastest mode since no calibration is
performed. This mode is useful for games which
require the sample frequency be changed
quickly. This mode is also useful when the codec
is operating full-duplex and an ADC data format
change is desired. This is the only calibration
mode that does not affect the DACs (i.e. mute
the DACs). Changing from any other calibration
mode to No Calibration mode will take 40 sample periods to complete; however, subsequent
MCE cycles will take 0 sample periods. The FIFOs are not flushed in this calibration mode;
DS145PP5
therefore, MCE should not be enabled until the
FIFOs are empty. If stale data is left in the FIFOs, and a data format change is made, the
output could produce an audible pop.
CONVERTER CALIBRATION (CAL1,0 = 01)
This calibration mode calibrates the ADCs and
the DACs, but does not calibrate any of the analog mixing channels. This is the second longest
calibration mode, taking 136 sample periods.
Because the analog mixer is not calibrated in this
mode, any signals fed through the mixer will be
unaffected. The calibration sequence is as follows:
The DACs are muted
The ADCs are calibrated
The DACs are calibrated
The DACs are unmuted
DAC CALIBRATION (CAL1,0 = 10)
This calibration mode only clears the DACs
(playback) interpolation filters leaving the ADC
unaffected. This is the second fastest calibration
mode (no cal. is the fastest) taking 40 sample
periods to complete. The calibration sequence is
as follows:
The DACs are muted
The DAC filters are cleared
The DACs are unmuted
FULL CALIBRATION (CAL1, 0 = 11)
This calibration mode calibrates all offsets,
ADCs, DACs, and analog mixers. Full calibration will be automatically be initiated on power
up or anytime the CS4232 exits from a full
power down state. This is the longest calibration
mode and takes 168 sample periods to complete.
The calibration sequence is as follows:
All outputs are muted (DACs and mixer)
The mixer is calibrated
The ADCs are calibrated
The DACs are calibrated
All outputs are unmuted
53
CS4232
Changing Sampling Rate
The internal states of the WSS Codec are synchronized by the selected sampling frequency.
The sample frequency can be set in one of two
fashions. The standard WSS Codec method uses
the Fs & Playback Data Format register (I8) to
set the sample frequency. The changing of either
the clock source or the clock frequency divide
requires a special sequence for proper WSS
Codec operation:
1) Place the WSS Codec in Mode Change Enable using the MCE bit of the Index Address
register (R0).
2) During a single write cycle, change the Clock
Frequency Divide Select (CFS) and/or
Clock 2 Source Select (C2SL) bits of the Fs
& Playback Data Format register (I8) to the
desired value. (The data format may also be
changed.)
3) The CS4232 resynchronizes its internal states
to the new clock. During this time the
CS4232 will be unable to respond at its parallel interface. Writes to the CS4232 will not
be recognized and reads will always return
the value 80 hex.
4) The host now polls the WSS Codec’s Index
Address register (R0) until the value 80 hex
is no longer returned. Since both crystals are
always running in the CS4232, 80h may occur to fast for ISA bus reads; therefore, it
may never be seen by software.
5) Once the CS4232 is no longer responding to
reads with a value of 80 hex, normal operation can resume and the CS4232 can be
removed from MCE.
The C2SL and CFS bits cannot be changed
unless the MCE bit has been set. Attempts
to change the Data Format registers (I8, I28)
or Interface Configuration register (I9, except CEN and PEN) without MCE set, will
not be recognized.
A second method of changing the sample frequency is to disable the sample frequency bits in
I8 (lower four bits) by setting SRE in I22. When
this bit is set, OSM1 and OSM0 in I10, along
with the rest of the bits in I22, are used to set the
sample frequency. Once enabled, these bits can
be changed without doing an MCE cycle. They
also support a finer resolution of sample frequencies, albeit with a more complicated
algorithm.
Changing Audio Data Formats
In MODE 1, MCE must be used to select the
audio data format in I8. Since MCE causes a
calibration cycle, it is not ideal for full-duplex
operation. In MODE2, individual Mode Change
Enable bits for capture and playback are provided in register I16. MCE (R0) must still be
used to select the sample frequency, but PMCE
(playback) and CMCE (capture) allow changing
the respective data formats without causing a
calibration to occur. Setting PMCE (I16) clears
the playback FIFO and allows the upper four
bits of I8 to be changed. Setting CMCE (I16)
clears the capture FIFO and allows the upper
four bits of I28 to be changed.
Audio Data Formats
In MODE 1 operation, all data formats of the
WSS Codec are in "little endian" format. This
format defines the byte ordering of a multibyte
word as having the least significant byte occupying the lowest memory address. Likewise, the
most significant byte of a little endian word occupies the highest memory address.
The sample frequency is always selected in the
Fs & Playback Data Format register (I8). In
54
DS145PP5
CS4232
MODE 1 the same register, I8, determines the
audio data format for both playback and capture;
however, in MODE 2, I8 only selects the playback data format and the capture data format is
independently selectable in the Capture Data
Format register (I28).
The WSS Codec always orders the left channel
data before the right channel. Note that these
definitions apply regardless of the specific format of the data. For example, 8-bit linear data
streams look exactly like 8-bit companded data
streams. Also, the left sample always comes first
in the data stream regardless of whether the sample is 16-bit or 8-bit in size.
There are four data formats supported by the
WSS Codec during MODE 1 operation: 16-bit
signed (little endian), 8-bit unsigned, 8-bit companded µ-Law, and 8-bit companded A-Law.
See Figures 11-14.
Additional data formats are supported in
MODE 2 operation: 4-bit ADPCM, and 16-bit
signed Big Endian. See Figures 15 through 18.
With the addition of the Big Endian and
ADPCM audio data formats, the CS4232 is compliant with the IMA recommendations for digital
audio data formats (and sample frequencies).
16-BIT SIGNED
The 16-bit signed format (also called 16-bit 2’s
complement) is the standard method of representing 16-bit digital audio. This format gives
96 dB theoretical dynamic range and is the
standard for compact disk audio players. This
format uses the value -32768 (8000h) to represent maximum negative analog amplitude, 0 for
center scale, and 32767 (7FFFh) to represent
maximum positive analog amplitude.
8-BIT UNSIGNED
The 8-bit unsigned format is commonly used in
the personal computer industry. This format delivers a theoretical dynamic range of 48 dB. This
format uses the value 0 (00h) to represent maximum negative analog amplitude, 128 for center
scale, and 255 (FFh) to represent maximum
positive analog amplitude. The 16-bit signed and
8-bit unsigned transfer functions are shown in
Figure 9.
8-BIT COMPANDED
The 8-bit companded formats (A-Law and µLaw) come from the telephone industry. µ-Law
is the standard for the United States/Japan while
A-Law is used in Europe. Companded audio al-
ANALOG VALUE
+FS
0
-FS
A-Law: 2Ah
u-Law: 00h
Figure 9. Linear Transfer Functions
DS145PP5
15h
3Fh
55h/D5h
7Fh/FFh
DIGITAL CODE
95h
BFh
AAh
80h
Figure 10. Companded Transfer Functions
55
CS4232
32-bit Word
sample 6
sample 5
MONO
sample 4
MONO
31
sample 3
Time
sample 2
MONO
24 23
sample 1
MONO
16 15
8 7
0
Figure 11. 8-bit Mono, Unsigned Audio Data
32-bit Word
sample 3
sample 3
RIGHT
sample 2
LEFT
31
sample 2
sample 1
RIGHT
24 23
Time
sample 1
LEFT
16 15
8 7
0
Figure 12. 8-bit Stereo, Unsigned Audio Data
32-bit Word Time
sample 6
sample 5
sample 4
sample 3
sample 2
MONO
31
24 23
sample 1
MONO
16 15
8 7
0
Figure 13. 16-bit Mono, Signed Little Endian Audio Data
32-bit Word Time
sample 3
sample 3
sample 2
sample 2
sample 1
RIGHT
31
24 23
sample 1
LEFT
16 15
8 7
0
Figure 14. 16-bit Stereo, Signed Little Endian Audio Data
56
DS145PP5
CS4232
32-bit Word
sample 8
MONO
31
MONO
28 27
sample 7
MONO
24 23
sample 6
MONO
20 19
sample 5
MONO
16 15
Time
sample 4
sample 3
MONO
12 11
sample 2
MONO
8 7
sample 1
MONO
4 3
0
Figure 15. 4-bit Mono, ADPCM Audio Data
32-bit Word
sample 4
RIGHT
31
LEFT
28 27
sample 4
RIGHT
24 23
sample 3
LEFT
20 19
sample 3
RIGHT
16 15
Time
sample 2
sample 2
LEFT
12 11
sample 1
RIGHT
8 7
sample 1
LEFT
4 3
0
Figure 16. 4-bit Stereo, ADPCM Audio Data
32-bit Word
sample 4
sample 4
sample 3
MONO LO
23
sample 3
sample 2
MONO HI
16 31
sample 2
sample 1
MONO LO
24 7
Time
sample 1
MONO HI
0 15
8
Figure 17. 16-bit Mono, Signed Big Endian Audio Data
32-bit Word
sample 2
sample 2
sample 2
RIGHT LO
23
sample 2
sample 1
RIGHT HI
16 31
sample 1
sample 1
LEFT LO
24 7
Time
sample 1
LEFT HI
0 15
8
Figure 18. 16-bit Stereo, Signed Big Endian Audio Data
DS145PP5
57
CS4232
lows either 64 dB or 72 dB of dynamic range
using only 8-bits per sample. This is accomplished using a non-linear companding transfer
function which assigns more digital codes to
lower amplitude analog signals with the sacrifice
of precision on higher amplitude signals. The µLaw and A-Law formats of the WSS Codec
conform to the CCITT G.711 specifications. Figure 10 illustrates the transfer function for both
A- and µ-Law. Please refer to the standards mentioned above for an exact definition.
ADPCM COMPRESSION/DECOMPRESSION
In MODE 2, the WSS Codec also contains
Adaptive Differential Pulse Code Modulation
(ADPCM) for improved performance and compression ratios over µ-Law or A-Law. The
ADPCM format is compliant with the IMA
standard and provides a 4-to-1 compression ratio
(i.e. 4 bits are saved for each 16-bit sample captured). For more information on the specifics of
the format, contact the IMA at (410) 626-1380.
Figures 15 and 16 illustrate the ADPCM data
flow.
The ADPCM format is unique with respect to
the FIFO depth and the DMA Base register
value. The ADPCM format fills the FIFOs completely (64 bytes); therefore, the FIFOs hold 64
stereo samples and 128 mono samples. When
samples are being transferred using DMA, the
DMA request stays active for four bytes, similar
to the 16-bit stereo data mode. In PIO mode, the
Status register (R2) indicates which of the four
bytes is being transferred.
When CEN is 0 (capture disabled), the ADPCM
block’s accumulator and step size are cleared.
When CEN is enabled, the ADPCM block will
start converting. Care should be taken to insure
that the "overrun" condition never occurs, otherwise the data may not be constructed properly
upon playback. If pausing the capture sequence
is desired, the ADPCM Capture Freeze bit (ACF,
I23) should be set. When this bit is set, the
58
ADPCM algorithm will continue to operate until
a complete word (4 bytes) is written to the FIFO.
Then the ADPCM’s block accumulator and step
size will be frozen. The software must continue
reading until the FIFO is empty, at which time
the requests will stop. When ACF is cleared, the
ADPCM adaptation will continue.
When PEN is 0 (playback disabled), the
ADPCM block’s accumulator and step size are
cleared. When PEN is set, the ADPCM block
will start converting. When pausing the playback
stream is desired, audio data should not be sent
to the codec, causing an underrun. This can be
accomplished by disabling the DMA controller
or not sending data in PIO mode. The underrun
will be detected by the WSS Codec and the adaptation will freeze. When data is sent to the
codec, adaptation will resume. It is critical that
all playback ADPCM samples are sent to the
codec, since dropped samples will cause errors
in adaptation. Whereas toggling PEN resets the
accumulator and step size, the APAR bit (I17)
only resets the accumulator without affecting the
step size.
DMA Registers
The DMA registers allow easy integration of the
CS4232 into ISA systems. Peculiarities of the
ISA DMA controller require an external count
mechanism to notify the host CPU of a full
DMA buffer via interrupt. The programmable
DMA Base registers provide this service.
The act of writing a value to the Upper Base
register causes both Base registers to load the
Current Count register. DMA transfers are enabled by setting the PEN/CEN bit while
PPIO/CPIO is clear. (PPIO/CPIO can only be
changed while the MCE bit is set.) Once transfers are enabled, each sample that is transferred
by a DMA cycle will decrement the Current
Count register (with the exception of the
ADPCM format) until zero is reached. The next
DS145PP5
CS4232
sample after zero generates an interrupt and reloads the Current Count registers with the values
in the Base registers.
is cleared by a write of any value to the Status
register (R2), or writing a "0" to the Playback
Interrupt bit, PI (I24).
For all data formats except ADPCM, the DMA
Base registers must be loaded with the number
of samples, minus one, to be transferred between
"DMA Interrupts". Stereo data contains twice as
many samples as mono data; however, 8-bit data
and 16-bit data contain the same number of samples. Symbolically:
CAPTURE DMA REGISTERS
The Capture DMA Base registers (I30/31) provide a second pair of Base registers that allow
full-duplex DMA operation. With full-duplex operation capture and playback can occur
simultaneously. These registers are provided in
MODE 2 operation only.
DMA Base register16 = NS - 1
When the capture Current Count register rolls
under, the Capture Interrupt bit, CI, (I24) is set
causing the INT bit (R2) to be set. The interrupt
is cleared by a write of any value to the Status
register (R2), or writing a "0" to the Capture Interrupt bit, CI (I24).
Where NS is the number of samples transferred
between interrupts and the "DMA Base register16" consists of the concatenation of the upper
and lower DMA Base registers.
For the ADPCM data format, the contents of the
DMA Base registers is calculated differently
from any other data format. The Base registers
must be loaded with the number of BYTES to be
transferred between "DMA interrupts", divided
by four, minus one. The same equation is used
whether the data format is stereo or mono
ADPCM. Symbolically:
DMA Base register16 = Nb/4 - 1
Where Nb is the number of BYTES transferred
between interrupts and the "DMA Base register16" consists of the concatenation of the upper
and lower DMA Base registers.
PLAYBACK DMA REGISTERS
The playback DMA registers (I14/15) are used
for sending playback data to the DACs in
MODE 2. In MODE 1, these registers (I14/15)
are used for both playback and capture; therefore, full-duplex DMA operation is not possible.
When the playback Current Count register rolls
under, the Playback Interrupt bit, PI, (I24) is set
causing the INT bit (R2) to be set. The interrupt
DS145PP5
Digital Loopback
Digital Loopback is enabled via the LBE bit in
the Loopback Control register (I13). This loopback routes the digital data from the ADCs to
the DACs. This loopback can be digitally attenuated via additional bits in the Loopback Control
register (I13). Loopback is then summed with
DAC data supplied at the digital bus interface.
When loopback is enabled, it will "freerun" synchronous with the sample rate. The digital
loopback is shown in the CS4232 Block Diagram at the beginning of this data sheet. This
loopback can be used to mix the incoming microphone data with data from the DACs. Since
the WSS Codec allows selection of different data
formats between capture and playback, if the
capture channel is set to mono and the playback
channel set to stereo, the mono input (mic) data
will be mixed into both channels of the output
mixer.
If the sum of the loopback and bus data are
greater than full scale, WSS Codec will send the
appropriate full scale value to the DACs (clipping).
59
CS4232
Timer Registers
The Timer registers are provided for synchronization, watch dog and other functions where a
high resolution time reference is required. This
counter is 16 bits and the exact time base, listed
in the register description, is determined by the
crystal selected.
The Timer register is set by loading the high and
low registers to the appropriate values and setting the Timer Enable bit, TE, in the Alternate
Feature Enable register (I16). This value will be
loaded into an internal Current Count register
and will decrement at approximately a 10 µsec
rate. When the value of the Current Count register reaches zero, an interrupt will be posted to
the host and the Timer Interrupt bit, TI, is set in
the Alternate Feature Status register (I24). On
the next timer clock the value of the Timer registers will be loaded into the internal Current
Count register and the process will begin again.
The interrupt is cleared by any write to the
Status register (R2) or by writing a "0" to the
Timer Interrupt bit, TI, in the Alternate Feature
Status register (I24).
WSS Codec Interrupt
The INT bit of the Status register (R2) always
reflects the status of the WSS Codec’s internal
interrupt state. A roll-over from any Current
Count register (DMA playback, DMA capture, or
Timer) sets the INT bit. This bit remains set until
cleared by a write of ANY value to Status register (R2), or by clearing the appropriate bit or bits
(PI, CI, TI) in the Alternate Feature Status register (I24).
The Interrupt Enable (IEN) bit in the Pin Control
register (I10) determines whether the interrupt
assigned to the WSS Codec responds to the interrupt event. When the IEN bit is low, the
interrupt is masked and the IRQ pin assigned to
60
the WSS Codec is held low. However, the INT
bit in the Status register (R2) always responds to
the counter.
Error Conditions
Data overrun or underrun could occur if data is
not supplied to or read from the WSS Codec in
an appropriate amount of time. The amount of
time for such data transfers depends on the frequency selected within the WSS Codec.
Should an overrun condition occur during data
capture, the last whole sample (before the overrun condition) will be read by the DMA
interface. A sample will not be overwritten while
the DMA interface is in the process of transferring the sample.
Should an underrun condition occur in a playback case the last valid sample will be output
(assuming DACZ = 0) to the digital mixer. This
will mask short duration error conditions. When
the next complete sample arrives from the host
computer the data stream will resume on the
next sample clock.
DIGITAL HARDWARE DESCRIPTION
The best example of hardware connection for the
different sections of the CS4232 such as joystick
connector, ISA bus, and peripheral port connections is the CRD4232-1 reference design. This is
a low-cost two-layer ISA card that supports all
the features of the CS4232. The CRD4232-1
Data Sheet contains all the schematics, layout
plots and a Bill of Materials; thereby providing a
complete example.
Bus Interface
The CS4232 ISA bus interface is capable of
driving a 24mA data bus load and therefore does
not require any external data bus buffering. See
the CRD4232-1 Reference Design for a typical
connection diagram.
DS145PP5
CS4232
VDD
33.9MHz
6
VSS
24.6MHz
16.9MHz
4
XTAL2I
(OPL3L)
YMF289B-S
48 Pin SQFP
BRESET
5.6 kΩ
LLINE
RLINE
560 pF
NPO
17
VSS
37
BCO
DO
VA
33
35 32 36
1
2
8 AOUTL
5.6 kΩ
560 pF
8.2 kΩ
NPO
3
VSS
SCLK
XIOW
0.33 µF
0.1 µF
VSS
XIOR
0.33 µF
47
VDD
13 14 15 24
SCS
0.1 µF
SDATAI
D0
A1
A0
3
48
5V/3V
XI
IC
XD4
XD3
XD2
XD1
XD0
XA1
XA0
D7
D6
D5
D4
D3
D2
D1
WR
11
10
9
8
6
5
4
26
25
RD
XD6
XD5
CS
12
VD
1 kΩ
1
XD7
2
CLKO
XTAL1I
MK1420S
8-Pin Clock Source
5 AOUTR
3
4
MCLK
5
XI
LRO
1
14.318 MHz
data lines, along with a read strobe, write strobe,
and an active low reset pin. Figure 19 illustrates
an example circuit that uses the OPL3L from
Yamaha for FM synthesis, with the Crystal
CS4333 8-pin DAC. Since the OPL3L requires a
33 MHz fundamental-mode crystal - which is
not easily obtainable - the Micro Clock
MK1420S is used for clock generation. This chip
takes the 14 MHz signal from a crystal or the
ISA bus, and generates the clocks needed by the
OPL3L as well as the CS4232.
LRCK
FM Synthesis
If the external synthesizer is not a high quality
wave-table synthesizer such as the CS9233, then
an FM synthesizer is needed to support the synthesis portion of the Windows Sound System and
Sound Blaster Compatible interfaces. The synthesizer has a chip select, SCS, and an optional
interrupt SINT which is multiplexed with the
control pin XCTL1. Since the FM synthesizer
interrupt is typically not used, the pin defaults to
XCTL1. To change the pin to support SINT, see
the Multiplexed Pin Configuration section. The
rest of the synthesizer interface uses the external
peripheral port pins which include address and
0.1 µF
7
VA+
CS4333
8-pin
DAC
AGND
8.2 kΩ
6
Figure 19. FM Synthesis Circuit
DS145PP5
61
CS4232
Crystals / Clocks
Four pins have been allocated to allow the interfacing of two crystal oscillators to the CS4232:
XTAL1I, XTAL1O, XTAL2I, XTAL2O. The
crystals should be designed as fundamental
mode, parallel resonant, with a load capacitor of
between 10 and 20 pF. The capacitors connected
to each of the crystal pins should be twice the
load capacitance specified to the crystal manufacturer. The XTAL1 oscillator is designed with
slightly more gain to handle higher frequencies,
but any crystal with the above specifications
should suffice. The standard crystals for audio
are:
XTAL1: 24.576 MHz
Fundamental Mode
Parallel Resonant, CL = 20 pF
XTAL2: 16.9344 MHz
Fundamental Mode
Parallel Resonant, CL = 20 pF
These crystal frequencies support the standard
sample frequencies listed in Table 10.
External CMOS clocks may be connected to the
crystal inputs (XTAL1I, XTAL2I) in lieu of the
crystals. When using external CMOS clocks, the
XTAL out pins should be left floating. Extreme
care should be used when laying out a board using external clocks since coupling between
clocks can degrade analog performance.
General Purpose Output Pins
Two general purpose outputs are provided to enable control of circuitry external to the CS4232
(i.e. mute function). XCTL1 and XCTL0 in the
WSS Codec register I10 are output directly to
the appropriate pin when enabled.
Pin XCTL0/XA2 becomes an output for XCTL0
whenever the resource data for the CDROM or
Synthesizer specifies a logical device address
range that is four bytes. If the address range is
specified to be eight bytes, then XA2 becomes
an output for SA2 from the ISA bus.
Pin XCTL1/SINT becomes an output for XCTL1
when the state of the XIOW pin is sampled high
during a high to low transition of the RESDRV
pin. If XIOW is sampled low, SINT becomes an
input for the Synthesizer interrupt. XIOW has an
internal pullup resistor.
Reset and Power Down
A RESDRV pin places the CS4232 into maximum power conservation mode. When RESDRV
goes high, the PnP registers are reset - all logical
devices are disabled, all analog outputs are
muted, and the voltage reference then slowly decays to ground. When RESDRV is brought low,
an initialization procedure begins which causes a
full calibration cycle to occur. While the WSS
Codec is initializing, any reads from the WSS
interface will return 80 hex and writes will be
ignored. When initialization is completed, the
registers will contain their reset value as stated
in the register section of the data sheet and the
part will be isolated from the bus.
Software low-power states are available through
bits in the Control logical device register space.
These power-down modes retain all the internal
registers such that the chip will be ready for operation, immediately after power up, without
having to re-program the registers.
Multiplexed Pin Configuration
On the high to low transition of the RESDRV
pin, the CS4232 samples the state of the XIOR
and XIOW pins. Both of these pins have internal
100kΩ pullups to +5V. If either of these pins is
pulled low externally, they must be buffered before connecting to a TTL input (as in a CDROM
port) since TTL cannot be pulled low.
The state of XIOR at the time RESDRV is
brought low determines the function of the
62
DS145PP5
CS4232
CDROM interface pins. If XIOR is sampled low
(external pulldown) then CDCS, CDACK,
CDINT, CDRQ become the standard CDROM
interface pins. If XIOR is sampled high, then
CDCS, CDACK, CDINT, CDRQ are used to input SA12, SA13, SA14, SA15 respectively.
The state of XIOW at the time RESDRV is
brought low determines the function of the
XCTL1/SINT pin. If XIOW is sampled low (external pulldown) then XCTL1/SINT functions as
an input for the synthesizer interrupt. If XIOW is
sampled high (pin left unconnected) then
XCTL1/SINT becomes an output for XCTL1.
ANALOG HARDWARE DESCRIPTION
The analog hardware consist of an MPC
Level 2-compatible mixer (four stereo mix
sources), three line-level stereo inputs, a stereo
microphone input, a mono input, a mono output,
and a stereo line output. This section describes
the analog hardware needed to interface with
these pins.
Line-Level Inputs Plus MPC Mixer
The analog inputs consist of four stereo analog
inputs, and one mono input. As shown on this
data sheet cover, the input to the ADCs comes
from a multiplexer that selects between two analo g line-level in puts (LINE, AUX1), a
microphone level input (MIC), and the output
from the MPC-compatible mixer. The LINE and
AUX1 lines also feed the MPC mixer and include individual volume controls. Unused analog
inputs should be connected together and then
connected through a capacitor to analog ground.
The analog input interface is designed to accommodate four stereo inputs and one mono input.
Three of these sources are multiplexed to the
ADC. These inputs are: a stereo line-level input
(LINE), a stereo microphone input (MIC), and a
stereo auxiliary line-level input (AUX1). The
LINE and AUX1 inputs have a separate path,
with volume control, to the output analog mixer
DS145PP5
which has the additional inputs of a stereo
AUX2 channel, a mono input channel, and the
output of the DACs. All audio inputs should be
capacitively coupled to the CS4232.
To obtain Sound Blaster mixer compatibility, the
mapping of external devices to analog inputs is
important. The external FM or Wave-Table synthesizer analog outputs must be connected to the
LINE inputs. The CDROM analog outputs must
be connected to the AUX2 inputs, and the external Line Inputs must be connected to the AUX1
analog inputs.
Since some analog inputs can be as large as
2 VRMS, the circuit shown in Figure 20 can be
used to attenuate the analog input to 1 VRMS
which is the maximum voltage allowed for the
line-level inputs on the CS4232.
5.6 kΩ
1.0 µF
R
1.0 µF
5.6 kΩ
5.6 kΩ
L
5.6 kΩ
Figure 20. Line Inputs
Microphone Level Inputs
The microphone level inputs, LMIC and RMIC,
include a selectable +20dB gain stage for interfacing to an external microphone. The 20dB gain
block can be turned off to provide another stereo
line-level input. Figure 21 illustrates a singleended microphone input buffer circuit that will
support lower gain mics. If a mono microphone
is all that is desired, the RMIC input should be
connected to the output of the mono op amp,
used for LMIC, through its own AC coupling capacitor.
63
CS4232
+5VA (Low Noise) or
AGND - if CMOS Source
Similar circuit for stereo or
connect to Left for mono
2.2 kΩ
1 µF
Tant.
+
15 kΩ
220 pF
NPO
0.1 µF
4.7 kΩ
1
0.33 µF
RMIC
X7R
47 kΩ
0.1 µF
MIN
2.7 nF
LMIC
0.33 µF
MC33078 or
MC33178
Figure 22. Mono Input
VREF
47 kΩ
+
10 µF
Figure 21. Left or Mono Microphone Input
Mono Input
The mono input, MIN, is useful for mixing the
output of the "beeper" (timer chip), provided in
all PCs, with the rest of the audio signals. The
attenuation control allows 16 levels in -3dB
steps. In addition, a mute control is provided.
The attenuator is a single channel block with the
resulting signal sent to the output mixer where it
is mixed with the left and right outputs. Figure 22 illustrates a typical input circuit for the
Mono In. If MIN is driven from a CMOS gate,
the 4.7kΩ should be tied to AGND instead of
VA+. Although this input is described for a lowquality beeper, the input is of the same
high-quality as all other analog inputs and may
be used for other purposes. At power-up, the
MIN line is connected directly to the MOUT pin
(with 9 dB of attenuation) allowing the initial
beeps, heard when the computer is initializing, to
pass through.
Line Level Outputs
The analog output section of the CS4232 provides a stereo line-level output. The other output
types (headphone and speaker) can be implemented with external circuitry. LOUT and
ROUT outputs should be capacitively coupled to
external circuitry. Both LOUT and ROUT need
1000 pF NPO capacitors between the pin and
AGND.
Mono Output with Mute Control
The mono output, MOUT, is a sum of the left
and right output channels, attenuated by 6dB to
prevent clipping at full scale. The mono out
channel can be used to drive the PC-internal
mono speaker using an appropriate drive circuit.
This approach allows the traditional PC-sounds
to be integrated with the rest of the audio system. Figure 23 illustrates a typical speaker driver
circuit. The mute control is independent of the
line outputs allowing the mono channel to mute
the speaker without muting the line outputs. The
power-up default has MIN connected to MOUT
providing a pass-through for the beeps heard at
power-up.
Miscellaneous Analog Signals
The LFILT and RFILT pins must have a 1000 pF
NPO capacitor to analog ground. These capacitors, along with an internal resistor, provide a
single-pole low-pass filter used at the inputs to
the ADCs. By placing these filters at the input to
the ADCs, low-pass filters at each analog input
pin are avoided.
64
DS145PP5
CS4232
switching. Figure 25 shows the recommended
positioning of the decoupling capacitors. The
capacitors must be on the same layer as, and
close to, the CS4232. The vias shown go
through to the ground plane layer. Vias, power
supply traces, and VREF traces should be as
large as possible to minimize the impedance.
+5V
Ferrite Bead
CS4232
470 pF
MOUT
1 µF +
6
5
8
16 kΩ
2 1 7
1 µF +
47 Ω
0.22 µF
4
3
47 Ω
0.1 µF
10 kΩ
RESDRV
MC34119
0.1 µF
0.1 µF
Figure 23. Mono Output
The REFFLT pin is used to lower the noise of
the internal voltage reference. A 10µF and 0.1µF
capacitor to analog ground should be connected
with a short wide trace to this pin. No other connection should be made, as any coupling onto
this pin will degrade the analog performance of
the codec. Likewise, digital signals should be
kept away from REFFLT for similar reasons.
The VREF pin is typically 2.1 V and provides a
common mode signal for single-supply external
circuits. VREF only supports light DC loads and
should be buffered if AC loading is needed. For
typical use, a 0.47 µF capacitor should be connected to VREF. High-gain microphone circuits
can be improved by increasing the capacitance to
10 µF.
GROUNDING AND LAYOUT
Figure 24 is a suggested layout for the CS4232.
Similar to other Crystal codecs, it is recommended that the device be located on a separate
analog ground plane. With the CS4232’s parallel
data interface, however, optimum performance is
achieved by extending the digital ground plane
across pins 17 and 54. Pins 18, 46, and 53 are
grounds for the data bus and should be electrically connected to the digital ground plane
which will minimize the effects of the bus interface due to transient currents during bus
DS145PP5
POWER SUPPLIES
The power supply providing analog power
should be as clean as possible to minimize coupling into the analog section and degrading
analog performance. The VD1 and VD2 pins are
isolated from the rest of the power pins and provide digital power for the asynchronous parallel
bus. These two pins can be connected directly to
the digital power supply. VDF1 through VDF3
provide power to internal sections of the codec
and should be quieter than VD1 and VD2. This
can be achieved by using a ferrite bead as shown
in the CRD4232-1 Reference Design Data Sheet.
Grounding is covered in the Grounding and Layout section.
65
CS4232
≥1/8"
Digital
Ground
Plane
CS4232
Digital Analog
VD1
DGND1
Pins
DGND2
VD2
Pins
Ground
Connection
+5VD
Ferrite
Bead
VDF
Analog
Ground
Plane
Codec
Codec
digital analog signals
signals
&
Components
CPU & Digital
Logic
Figure 24. Suggested Layout Guideline
VDF1
1.0 µF
0.1 µF
VDF3
0.1 µF
0.1 µF
1.0 µF
0.1 µF
1.0 µF
= vias through to
ground plane
VA
BUS VD1
1.0 µF
0.1 µF
BUS VD2
0.1 µF
VDF2
Figure 25. Recommended Decoupling Capacitor Positions
66
DS145PP5
CS4232
ADC/DAC FILTER RESPONSE PLOTS
Figures 26 through 31 show the overall frequency response, passband ripple, and transition
band for the CS4232 ADCs and DACs. Figure 32 shows the DACs’ deviation from linear
phase. Since the CS4232 scales filter response
based on sample frequency selected, all frequency response plots x-axis’ are shown from 0
to 1 where 1 is equivalent to Fs. Therefore, for
any given sample frequency, multiply the x-axis
values by the sample frequency selected to get
the actual frequency.
10
0
-10
Magnitude (dB)
-20
-30
-40
-50
-60
-70
-80
-90
-100
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Input Frequency (×Fs)
0.2
0
0.1
-10
-0.0
-20
-0.1
-30
Magnitude (dB)
Magnitude (dB)
Figure 26. ADC Filter Response
-0.2
-0.3
-0.4
-40
-50
-60
-0.5
-70
-0.6
-80
-0.7
-90
-100
-0.8
0.00
0.05
0.10 0.15 0.20 0.25
0.30 0.35 0.40 0.45
Input Frequency (×Fs)
Figure 27. ADC Passband Ripple
DS145PP5
0.50
0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70
Input Frequency (×Fs)
Figure 28. ADC Transition Band
67
10
0.2
0
-10
0.1
-0.0
-20
-0.1
Magnitude (dB)
Magnitude (dB)
CS4232
-30
-40
-50
-60
-0.2
-0.3
-0.4
-70
-80
-0.5
-90
-0.7
-100
-0.8
-0.6
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Input Frequency (×Fs)
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (×Fs)
Figure 30. DAC Passband Ripple
0
2.5
-10
2.0
-20
1.5
-30
1.0
Phase (degrees)
Magnitude (dB)
Figure 29. DAC Filter Response
-40
-50
-60
-70
0.5
0.0
-0.5
-1.0
-80
-1.5
-90
-2.0
-100
-2.5
0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70
Input Frequency (×Fs)
Figure 31. DAC Transition Band
68
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (×Fs)
Figure 32. DAC Phase Response
DS145PP5
CS4232
AG ND
R E FF LT
VREF
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
SGND3
X T A L1O
X T A L1I
S A 1 2 */C D C S
S A13*/C D A C K
S A 14*/C D IN T
SA1 5*/C D R Q
RESDRV
MOUT
M IN
LLIN E
R LIN E
LA U X 2
RAUX2
L M IC
R M IC
VA
PIN DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CS4232
100-PIN
PQFP
(M)
TOP VIEW
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
L F IL T
R FILT
LAU X1
RAUX1
LOUT
ROUT
TEST
JA B 1
J B B 1 */F S Y N C
JA C X
JB C X */S D O U T
SGND2
V D F2
JB C Y */S D IN
JA C Y
JB B 2*/S C LK
JA B 2
M ID O U T
M ID IN
D A C K A (D A C K 0 *)
D A C K C (D A C K 3 *)
D A C K B (D A C K 1 *)
D R Q A (D R Q 0 *)
VD2
DGND2
D R Q C (D R Q 3 *)
D R Q B (D R Q 1 *)
SD7
SD6
SD5
IO R
IO W
A EN
IO C H R D Y
SD0
SD1
SD2
SD3
VD1
DGND1
SD4
SA6
SA7
SA8
SA9
S A 10
SA11
SA3
SA4
SA5
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDF3
X T A L2O
X T A L2I
XD7
XD6
XD5
XD4
XD3
XD2
XD1
S D A /X D 0
SCS
X IO R
X IO W
X C T L 0 */X A 2
XA1
S C L /X A 0
BRESET
X C T L 1 */S IN T
VDF1
SGND1
(IN T 1 5 *) IR Q F
(IN T 1 2 *) IR Q E
(IN T 1 1 *) IR Q D
(IN T 9 *) IR Q C
(IN T 7 *) IR Q B
(IN T 5 *) IR Q A
SA0
SA1
SA2
* Defaults - Cannot be changed
DS145PP5
69
AG ND
R E F FLT
VREF
L F IL T
R FIL T
S A 14*/C D IN T
S A 15*/C D R Q
RESDRV
MOUT
M IN
LL IN E
R LIN E
LA U X 2
RAU X2
LM IC
R M IC
VA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
X T A L2I
X T A L2 O
VDF3
SGND3
X TA L1 O
X T A L1 I
S A 1 2 */C D C S
S A 13*/C D A C K
CS4232
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CS4232
100-PIN
TQFP
(Q)
TOP VIEW
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
LAUX1
RAUX1
LOUT
ROUT
TEST
JA B 1
JB B 1 */F S Y N C
JA C X
JB C X */S D O U T
SGND2
V D F2
JB C Y */S D IN
JA C Y
JB B 2*/S C LK
JA B2
M ID O U T
M ID IN
D A C K A (D A C K 0 *)
D A C K C (D A C K 3 *)
D A C K B (D A C K 1 *)
D R Q A (D R Q 0 *)
VD2
DGND2
D R Q C (D R Q 3*)
D R Q B (D R Q 1*)
IO C H R D Y
SD0
SD 1
SD 2
SD3
VD1
DGND1
SD4
SD5
SD6
SD7
S A 10
SA11
IO R
IO W
AEN
SA 6
SA 7
SA 8
SA 9
SA1
SA2
SA3
SA4
SA5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
XD7
XD6
XD5
XD4
XD3
XD2
XD1
S D A /X D 0
SCS
X IO R
X IO W
X C T L0 */X A 2
XA1
S C L /X A 0
BRESET
X C T L 1*/S IN T
V D F1
SGND1
(IN T 1 5 *) IR Q F
(IN T 1 2 *) IR Q E
(IN T 1 1 *) IR Q D
(IN T 9 *) IR Q C
(IN T 7 *) IR Q B
(IN T 5 *) IR Q A
SA0
* Defaults - See individual pin descriptions for more details
70
DS145PP5
CS4232
ISA Bus Interface Pins
SA<11:0> - System Address Bus, Inputs
These signals are decoded during I/O cycles to determine access to the various functional
blocks within the CS4232 as defined by the configuration data written during a Plug And Play
configuration sequence.
SA<15:12> - Upper System Address Bus, Inputs
These signals are dual function pins, shared with the CDROM interface, that default to the
upper address bits SA12 through SA15. These pins are generally used for motherboard designs
that want to eliminate address decode aliasing. Using these pins as upper address bits forces the
CS4232 to only accept valid address decodes when A12-A15 = 0. If these pins are not used for
address decodes (or for CDROM support), they should be tied to SGND.
SD<7:0> - System Data Bus, Bi-directional, 24mA drive
These signals are used to transfer data to and from the CS4232 and associated peripheral
devices.
AEN - Address Enable, Input
This signal indicates whether the current bus cycle is an I/O cycle or a DMA cycle. This signal
is low during an I/O cycle and high during a DMA cycle.
IOR - Read Command Strobe, Input
This active low signal defines a read cycle to the CS4232. The cycle may be a register read or a
read from the CS4232 DMA registers.
IOW - Write Command Strobe, Input
This active low signal indicates a write cycle to the CS4232. The cycle may be a write to a
control register or a CS4232 DMA register.
IOCHRDY - I/O Channel Ready, Open Drain Output, 8mA drive
This signal is driven low by the CS4232 during ISA bus cycles in which the CS4232 is not able
to respond within a minimum cycle time. IOCHRDY is forced low to extend the current bus
cycle. The bus cycle is extended until IOCHRDY is brought high.
DRQ<A,B,C> - DMA Requests, Outputs, 24mA drive
These active high outputs are generated when the CS4232 is requesting a DMA transfer. This
signal remains high until all the bytes have been transferred as defined by the current transfer
data type. The DRQ<A,B,C> outputs must be connected to 8-bit DMA channel request signals
only. The defaults on the ISA bus are DRQA = DRQ0, DRQB = DRQ1, and DRQC = DRQ3.
The defaults cannot be changed. If all the defaults are not used and the design supports Plug
and Play, the Plug and Play resource data MUST be modified.
DS145PP5
71
CS4232
DACK<A,B,C> - DMA Acknowledge, Inputs
The assertion of these active low signals indicate that the current DMA request is being
acknowledged and the CS4232 will respond by either latching the data present on the data bus
(write) or putting data on the bus (read). The DACK<A,B,C> inputs must be connected to 8-bit
DMA channel acknowledge lines only. The defaults on the ISA bus are DACKA = DACK0,
DACKB = DACK1, and DACKC = DACK3. The defaults cannot be changed. If all the
defaults are not used and the design supports Plug and Play, the Plug and Play resource data
MUST be modified.
IRQ <A:F>- Host Interrupt Pins, Outputs, 24mA drive
These signals are used to notify the host of events which need servicing. They are connected to
specific interrupt lines on the ISA bus. The IRQ<A:F> are individually enabled as per
configuration data that is generated during a Plug and Play configuration sequence. The defaults
on the ISA bus are IRQA = INT5, IRQB = INT7, IRQC = INT9, IRQD = INT11,
IRQE = INT12, IRQF = INT15. The defaults cannot be changed. If all the defaults are not used
and the design supports Plug and Play, the Plug and Play resource data MUST be modified.
Analog Inputs
LLINE - Left Line Input
Nominally 1 VRMS max analog input for the Left LINE channel, centered around VREF. The
LINE inputs may be selected for A/D conversion via the input multiplexer (I0). A
programmable gain block (I18) also allows routing to the mixer. Typically used for Left
Channel Synthesis (FM or Wave Table).
RLINE - Right Line Input
Nominally 1 VRMS max analog input for the Right LINE channel, centered around VREF. The
LINE inputs may be selected for A/D conversion via the input multiplexer (I1). A
programmable gain block (I19) also allows routing to the mixer. Typically used for Right
Channel Synthesis (FM or Wave Table).
LMIC - Left Mic Input
Microphone input for the Left MIC channel, centered around VREF. Full scale can be either
1 VRMS (LMGE = 0) or 0.1 VRMS (LMGE = 1). The MIC inputs may be selected for A/D
conversion via the input multiplexer (I0).
RMIC - Right Mic Input
Microphone input for the Right MIC channel, centered around VREF. Full scale can be either
1 VRMS (RMGE = 0) or 0.1 VRMS (RMGE = 1). The MIC inputs may be selected for A/D
conversion via the input multiplexer (I1).
LAUX1 - Left Auxiliary #1 Input
Nominally 1 VRMS max analog input for the Left AUX1 channel, centered around VREF. The
AUX1 input may be selected for A/D conversion via the input multiplexer (I0). A
programmable gain block (I2) also allows routing to the output mixer. Typically used for an
external Left line-level input.
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RAUX1 - Right Auxiliary #1 Input
Nominally 1 VRMS max analog input for the Right AUX1 channel, centered around VREF.
The AUX1 input may be selected for A/D conversion via the input multiplexer (I1). A
programmable gain block (I3) also allows routing to the output mixer. Typically used for an
external Right line-level input.
LAUX2 - Left Auxiliary #2 Input
Nominally 1 VRMS max analog input for the Left AUX2 channel, centered around VREF. A
programmable gain block (I4) also allows routing of the AUX2 channels into the output mixer.
Typically used for the Left channel CDROM input.
RAUX1 - Right Auxiliary #1 Input
Nominally 1 VRMS max analog input for the Right AUX2 channel, centered around VREF. A
programmable gain block (I5) also allows routing of the AUX2 channels into the output mixer.
Typically used for the Right channel CDROM input.
MIN - Mono Input
Nominally 1 VRMS max analog input, centered around VREF, that goes through a
programmable gain stage (I26) into both channels of the mixer. This is a general purpose mono
analog input that is normally used to mix the typical "beeper" signal on most computers into the
audio system
Analog Outputs
LOUT - Left Line Level Output
Analog output from the mixer for the left channel. Nominally 1 VRMS max centered around
VREF. This pin needs a 1000 pF NPO capacitor attached and tied to analog ground.
ROUT - Right Line Level Output
Analog output from the mixer for the Right channel. Nominally 1 VRMS max centered around
VREF. This pin needs a 1000 pF NPO capacitor attached and tied to analog ground.
MOUT - Mono Output
MOUT is nominally 1 VRMS max analog output, centered around VREF. This output is a
summed analog output from both the left and right output channels of the mixer. MOUT
typically is connected to a speaker driver that drives the internal speaker in most computers.
Independently mutable via MOM in I26.
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CS4232
MIDI Interface
MIDOUT - MIDI Out Transmit Data, Output, 4mA drive
This output is used to send MIDI data serially out to a external MIDI device. Normally
connected to pin 12 of the joystick connector for use with breakout boxes.
MIDIN - MIDI In Receive Data, Input
This input is used to receive serial MIDI data from an external MIDI device. This pin should
have a 47 kΩ pullup attached and is normally connected to pin 15 of the joystick connector for
use with breakout boxes.
Synthesizer Interface
SCS - Synthesizer Chip Select, Output, 4 mA drive
This active low output is forced low when a valid address decode to the synthesizer , as defined
in the Plug and Play configuration registers, has occurred.
XCTL1/SINT - XCTL1 or Synthesizer Interrupt, Output/Input
This pin defaults to the XCTL1 output which is controlled by the XCTL1 bit in the CS4232
register I10. This pin can be changed to SINT input by connecting a 10kΩ resistor between the
XIOW pin and SGND. SINT is an active low input that should be driven by the synthesizer
interrupt output pin.
External Peripheral Port
XD<7:1> - External Data Bus bits 7 through 1, Bi-directional, 4mA drive
These pins are used to transfer data between the ISA bus and external devices such as the
synthesizer and CDROM.
SDA/XD0 - External Data Bus bit 0 and E2PROM Data Pin, Bi-directional, Open Drain,4mA
sink
This open-drain pin must have an external pullup (10kΩ) and is used to transfer data between
the ISA bus bit 0, SD0, and external devices such as the synthesizer and CDROM. SDA/XD0 is
also used in conjunction with SCL/XA0 to access an external serial E2PROM. When an
E2PROM is used, the SDA/XD0 pin should be connected to the data pin of the E2PROM
device and provides a bi-directional data port. The E2PROM is used to modify the default Plug
and Play resource data.
XCTL0/XA2 - XCTL0 or External Address SA2, Output, 4mA drive
This pin either outputs ISA bus address SA2 or XCTL0 depending on the Plug-and-Play
resource data. The default is XCTL0 which is controlled by the XCTL0 bit in the CS4232
register I10. This pin changes to address bit XA2 if the externally-loaded Plug-and-Play
resource data indicates that the synthesizer or CDROM requires more than four I/O addresses.
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CS4232
XA1 - External Address, Output, 4mA drive
This pin outputs ISA bus address SA1.
XA0/SCL - External Address, Output/Serial Clock, Output, 4mA drive
This pin outputs the ISA bus address SA0. When E2PROM access is enabled, then SCL is used
as a clock output to the E2PROM.
BRESET - Buffered Reset, Output, 4mA drive
This active low signal goes low whenever the RESDRV pin goes high.
XIOR - External Read Strobe, Output, 4mA drive (SA12-SA15/CDROM selection)
This active low signal goes low whenever (SCS or CDCS) and IOR goes low. This pin also
selects either the CDROM port or SA12 - SA15 and contains an internal pullup of
approximately 100 kΩ. The selection is made when RESDRV goes low. When XIOR is left
high (default), pins 91-94 are SA15-SA12 respectively. To enable the CDROM port, an external
10kΩ resistor must be tied between this pin and SGND.
XIOW - External Write Strobe, Output, 4mA drive (XCTL1/SINT selection)
This active low signal goes low whenever (SCS or CDCS) and IOW goes low. This pin also
selects either XCTL1 or SINT and contains an internal pullup of approximately 100 kΩ. The
selection is made when RESDRV goes low. When XIOW is left high (default), pin 16 is the
XCTL1 function. To change the pin to SINT, an external 10kΩ resistor must be tied between
this pin and SGND.
Joystick/Serial Port Interface
JACX, JACY - Joystick A Coordinates, Input
These pins and are the X/Y coordinates for Joystick A. They should have a 5.6nF capacitor to
ground and a 2.2kΩ resistor to the joystick connector pins 3 and 6, respectively.
JAB1, JAB2 - Joystick A Buttons, Input
These pins are the switch inputs for Joystick A. They should be connected to joystick connector
pins 2 and 7, respectively; as well as have a 1nF capacitor to ground, and a 4.7kΩ pullup
resistor.
JBCX/SDOUT - Joystick B Coordinate X/Serial Data Output, Input/Output
When this pin is used as a second joystick, it is the X coordinates input for Joystick B; and
should have a 5.6nF capacitor to ground and a 2.2kΩ resistor to the joystick connector pin 11.
When the serial port is enabled, SPE = 1 in I16, this pin is the serial data output. It should have
a 5.6nF capacitor to ground and a 2.2kΩ resistor to the joystick connector pin 11.
JBCY/SDIN - Joystick B Coordinate Y/Serial Data Input, Input
When this pin is used as a second joystick, it is the Y coordinates input for Joystick B; and
should have a 5.6nF capacitor to ground and a 2.2kΩ resistor to the joystick connector pin 13.
When the serial port is enabled, SPE = 1 in I16, this pin is the serial data input.
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CS4232
JBB1/FSYNC - Joystick B Button 1/Frame Sync, Input/Output
When this pin is used as a second joystick, it is the switch 1 input for Joystick B; and should be
connected to joystick connector pin 10; as well as have a 1nF capacitor to ground, and a 4.7kΩ
pullup resistor. When the serial port is enabled, SPE = 1 in I16, this pin is the serial frame sync
output.
JBB2/SCLK - Joystick B Button 2/Serial Clock, Input/Output
When this pin is used as a second joystick, it is the switch 2 input for Joystick B; and should be
connected to joystick connector pin 14; as well as have a 1nF capacitor to ground, and a 4.7kΩ
pullup resistor. When the serial port is enabled, SPE = 1 in I16, this pin is the serial clock
output.
CDROM Interface
The four CDROM pins are dual function and default to ISA upper address bits SA12-SA15. To
enable the CDROM port, an external 10kΩ resistor must be tied between XIOR and SGND.
XIOR is sampled on the falling edge of RESDRV.
CDCS - CDROM Chip Select, Output, 4mA drive
This output is goes low whenever the CS4232 decodes an address that matches the value
programmed into the CDROM base address register.
CDACK - CDROM DMA Acknowledge, Output, 4mA drive
This pin is used to output the ISA bus-generated DMA acknowledge signal to the CDROM
interface.
CDINT - CDROM Interrupt, Input
This pin is used to input an interrupt signal from the CDROM interface. The CS4232 can be
programmed, through the plug-and-play resource data, to output this signal to the appropriate
ISA bus interrupt line.
CDRQ - CDROM DMA Request, Input
This pin is used to input the DMA request signal from the CDROM interface. The CS4232 can
be programmed, through the plug-and-play resource data, to output this signal to the
appropriate ISA bus DRQ line.
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CS4232
Miscellaneous
XTAL1I - Crystal #1 Input
This pin will accept either a crystal, with the other pin attached to XTAL1O, or an external
CMOS clock. XTAL1 must have a crystal or clock source attached for proper operation. The
standard crystal frequency is 24.576 MHz although other frequencies can be used. The crystal
should be designed for fundamental mode, parallel resonance operation.
XTAL1O - Crystal #1 Output
This pin is used for a crystal placed between this pin and XTAL1I.
XTAL2I - Crystal #2 Input
This pin will accept either a crystal, with the other pin attached to XTAL2O, or an external
CMOS clock. XTAL2 must have a crystal or clock source attached for proper operation. The
standard crystal frequency is 16.9344 MHz although other frequencies can be used. The crystal
should be designed for fundamental mode, parallel resonance operation.
XTAL2O - Crystal #2 Output
This pin is used for a crystal placed between this pin and XTAL2I.
RESDRV - Reset Drive, Input
Places CS4232 in lowest power consumption mode. All sections of the CS4232, except the
digital bus interface, which reads 80h, are shut down and consuming minimal power. The
CS4232 is reset and in power down mode when this pin is logic high. The falling edge also
latches the state of XIOR and XIOW to determine the functionality of dual mode pins. This
signal is typically connected to the ISA bus signal RESDRV.
VREF - Voltage Reference, Output
All analog inputs and outputs are centered around VREF which is nominally 2.1 Volts. This
pin may be used to level shift external circuitry, although any AC loads should be buffered.
High internal-gain microphone inputs can be slightly improved by placing a 10µF capacitor on
VREF.
REFFLT - Reference Filter, Input
Voltage reference used internal to the CS4232. A 0.1 µF and a 10 µF capacitor with short fat
traces must be connected to this pin. No other connections should be made to this pin.
LFILT - Left Channel Antialias Filter Input
This pin needs a 1000 pF NPO capacitor attached and tied to analog ground.
RFILT - Right Channel Antialias Filter Input
This pin needs a 1000 pF NPO capacitor attached and tied to analog ground.
TEST - Test
This pin must be tied to ground for proper operation.
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CS4232
Power Supplies
VA - Analog Supply Voltage
Supply to the analog section of the codec.
AGND - Analog Ground
Ground reference to the analog section of the codec. Internally, this pin is connected to the
substrate as are all SGND pins; therefore, optimum layout is achieved with the AGND pin on
the same ground plane as SGND1/2/3 (see Figure 25).
VD1, VD2 - Digital Supply Voltage
Digital supply for the parallel data bus section of the codec.
DGND1, DGND2 - Digital Ground
Digital ground reference for the parallel data bus section of the codec. These pins are isolated
from the other grounds and should be connected to the digital ground section of the board (see
Figure 25).
VDF1, VDF2, VDF3 - Digital Filtered Supply Voltage
Digital supply for the internal digital section of the codec (except for the parallel data bus).
These pins should be filtered, using a ferrite bead, from VD1/VD2.
SGND1, SGND2, SGND3 - Substrate Ground
Substrate ground reference for the codec . These pins are connected to the substrate of the die
as is the AGND pin. Optimum layout is achieved by placing SGND1/2/3 on the analog ground
plane with the AGND pin as shown in Figure 25.
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CS4232
PARAMETER DEFINITIONS
Resolution
The number of bits in the input words to the DACs, and in the output words in the ADCs.
Differential Nonlinearity
The worst case deviation from the ideal code width. Units in LSB.
Total Dynamic Range
TDR is the ratio of the rms value of a full scale signal to the lowest obtainable noise floor. It is
measured by comparing a full scale signal to the lowest noise floor possible in the codec (i.e.
attenuation bits for the DACs at full attenuation). Units in dB.
Instantaneous Dynamic Range
IDR is the ratio of a full-scale rms signal to the rms noise available at any instant in time,
without changing the input gain or output attenuation settings. It is measured using S/(N+D)
with a 1 kHz, -60 dB input signal, with 60 dB added to compensate for the small input signal.
Use of a small input signal reduces the harmonic distortion components to insignificance when
compared to the noise. Units in dB.
Total Harmonic Distortion (THD)
THD is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the
test signal.
Interchannel Isolation
The amount of 1 kHz signal present on the output of the grounded input channel with 1 kHz
0 dB signal present on the other channel. Units in dB.
Interchannel Gain Mismatch
For the ADCs, the difference in input voltage that generates the full scale code for each
channel. For the DACs, the difference in output voltages for each channel with a full scale
digital input. Units in dB.
Offset Error
For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input
grounded. For the DACs, the deviation in volts of the output from VREF with mid-scale input
code.
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CS4232
PACKAGE PARAMETERS
D
100-pin TQFP - Package Code 'Q'
Symbol
Description
MIN
Lead Count
N
Overall Height
A
Stand Off
0.00
A1
Lead Width
0.14
b
Lead Thickness
0.077
c
Terminal Dimension 15.70
D
Package Body
D1
Terminal Dimension 15.70
E
Package Body
E1
Lead Pitch
0.40
e1
Foot Length
0.30
L1
Lead Angle
0.0°
T
D1
E1
1
e1
L1
b
c
T
A
A1
MAX
1.66
0.20
0.127
16.00
14.0
16.00
14.0
0.50
0.50
0.26
0.177
16.30
16.30
0.60
0.70
12.0°
Notes:
1) Dimensions in millimeters.
2) Package body dimensions do not include mold protrusion,
which is 0.25 mm.
3) Coplanarity is 0.004 in.
4) Lead frame material is AL-42 or copper, and lead finish
is solder plate.
5) Pin 1 identification may be either ink dot or dimple.
6) Package top dimensions can be smaller than bottom
dimensions by 0.20 mm.
7) The "lead width with plating" dimension does not include
a total allowable dambar protrusion of 0.08 mm (at
maximum material condition).
8) Ejector pin marks in molding are present on every package.
100
E
NOM
100
A
100-Pin PQFP (Rectangular)
Package Code 'M'
B
DIM
A
B
C
D
E
F
G
H
I
J
K
1
D
C
MILLIMETERS
MIN
NOM
MAX
16.95
17.20
17.45
14.0
22.95
23.20
23.45
20.0
0o
10 o
0.53
0.65
0.77
0.30
0.20
0.40
0.00
3.15
0.65
0.80
0.95
0.10
0.15
0.20
Plastic QUAD FLATPACK
I
E
K
H
F
80
J
G
DS145PP5
CS4232
APPENDIX A: TYPICAL E2PROM DATA
; EEPROM Validation Bytes
DB
055H, 0AAH
DB
DB
; Hardware
DB
DB
DB
DB
DB
DB
DB
000H
0F5H
; EEPROM Validation Bytes
; EEPROM data length upper byte
; lower byte, Listed Size = 245
Configuration Data (Resource Header)
000H
; 00=4/08=8 peripheral port size, XCTL0/XA2
048H
; LINE, AUX1, AUX2 mapping - RESERVED
075H
; IRQ selection A & B - B= 7, A=5
0B9H
; IRQ selection C & D - D=11, C=9
0FCH
; IRQ selection E & F - F=15, E=12
010H
; DMA selection A & B - B= 1, A=0
003H
; DMA selection C
C=3
; PnP Resource Header - Starts with Crystal PnP ID for CS4232 IC
DB
00EH, 063H, 042H, 032H, 001H,000H,000H,000H,0D3H ; CSC4232 00000001
DB
00AH, 010H, 001H
; PnP version 1.0, Vendor version 0.1
DB
082H, 007H, 000H, ’CS4232’, 000H ; ANSI ID
; LOGICAL DEVICE 0 (Windows Sound System & OPL3 & SBPro)
DB
015H, 00EH, 063H, 000H, 000H, 000H ; EISA ID: CSC0000
DB
DB
DB
DB
DB
DB
DB
DB
082H,
031H,
02AH,
02AH,
022H,
047H,
04BH,
04BH,
00BH,
000H
002H,
009H,
020H,
001H,
088H,
020H,
000H, ’WSS/OPL/SB’, 000H ; ANSI ID
; DF Best Choice
028H
; DMA: 1 - WSS & SBPro
028H
; DMA: 0,3 - WSS & SBPro capture
000H
; IRQ: 5 Interrupt Select 0
034H, 005H, 034H, 005H, 004H, 004H ; 16b WSSbase: 534
003H, 004H ; 10b SYNbase: 388
002H, 010H ; 10b SBbase: 220
DB
DB
DB
DB
DB
DB
031H,
02AH,
022H,
047H,
047H,
047H,
001H
00BH,
0A0H,
001H,
000H,
000H,
; DF Acceptable Choice 1
028H
; DMA: 0,1,3 - WSS & SBPro
09AH
; IRQ: 5,7,9,11,12,15 Interrupt Select 0
000H, 001H, 0FCH, 00FH, 004H, 004H ; 16b WSSbase: 100-FFC
000H, 001H, 0FCH, 003H, 004H, 004H ; 10b SYNbase: 100-3FC
000H, 001H, 0F0H, 003H, 010H, 010H ; 10b SBbase: 100-3F0
DB
038H
DB
DB
DB
01CH, 041H, 0D0H, 0B0H, 007H ; Compatible ID: PNPB007
01CH, 041H, 0D0H, 0B0H, 020H ; Compatible ID: PNPB020
01CH, 041H, 0D0H, 0B0H, 002H ; Compatible ID: PNPB002
DS145PP5
; End of DF for Logical Device 0
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CS4232
; LOGICAL DEVICE 1 (Game Port)
DB
015H, 00EH, 063H, 000H, 001H, 000H ; EISA ID: CSC0001
DB
DB
DB
082H, 005H, 000H, ’GAME’, 000H ; ANSI ID
031H, 000H
; DF Best Choice
04BH, 000H, 002H, 008H ; 10b GAMEbase: 200
DB
DB
031H, 001H
; DF Acceptable Choice 1
047H, 000H, 000H, 001H, 0F8H, 003H, 008H, 008H ; 10b GAMEbase: 100-3F8
DB
038H
DB
01CH, 041H, 0D0H, 0B0H, 02FH ; Compatible ID: PNPB02F
; End of DF for Logical Device 1
; LOGICAL DEVICE 2 (Control)
DB
015H, 00EH, 063H, 000H, 002H, 000H ; EISA ID: CSC0002
DB
DB
082H, 005H, 000H, ’CTRL’, 000H ; ANSI ID
047H, 001H, 000H, 001H, 0F8H, 00FH, 008H, 008H ; 16b CTRLbase: 100-FF8
; LOGICAL DEVICE 3 (MPU-401)
DB
015H, 00EH, 063H, 000H, 003H, 000H ; EISA ID: CSC0003
DB
DB
DB
DB
082H,
031H,
022H,
04BH,
004H, 000H, ’MPU’, 000H ; ANSI ID
000H
; DF Best Choice
000H, 002H
; IRQ: 9 Interrupt Select 0
030H, 003H, 002H ; 10b MPUbase: 330
DB
DB
DB
031H, 001H
; DF Acceptable Choice 1
022H, 0A0H, 09AH
; IRQ: 5,7,9,11,12,15 Interrupt Select 0
047H, 000H, 000H, 001H, 0F8H, 003H, 008H, 002H ; 10b MPUbase: 100-3F8
DB
038H
DB
01CH, 041H, 0D0H, 0B0H, 006H ; Compatible ID: PNPB006
; End of DF for Logical Device 3
; LOGICAL DEVICE 4 (CD-ROM)
DB
015H, 00EH, 063H, 000H, 004H, 000H ; EISA ID: CSC0004
82
DB
DB
082H, 003H, 000H, ’CD’, 000H ; ANSI ID
047H, 000H, 000H, 001H, 0FCH, 003H, 004H, 004H ; 10b CDbase: 100-3FC
DB
079H, 0A4H
; End of Resource Data, Checksum
DS145PP5
• Notes •
Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation
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