MAX5073 2.2MHz, Dual-Output Buck or Boost Converter with

MAX5073 2.2MHz, Dual-Output Buck or Boost Converter with
EVALUATION KIT AVAILABLE
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
PINPACKAGE
PACKAGE
CODE
MAX5073ETI -40°C to +125°C
28 Thin QFN-EP*
(5mm x 5mm)
T2855-6
MAX5073ETI+ -40°C to +125°C
28 Thin QFN-EP*
(5mm x 5mm)
T2855-6
PART
TEMP RANGE
*EP = Exposed pad.
+Denotes lead-free package.
Ordering Information continued at end of data sheet.
19-3504; Rev 3; 5/14
DRAIN1
DRAIN1
EN1
FB1
COMP1
19
18
17
16
15
PGOOD2
22
14
BYPASS
SOURCE1
23
13
VL
SOURCE1
24
12
VL
MAX5073
SGND
25
11
V+
PGND
26
10
OSC
SOURCE2
27
9
N.C.
SOURCE2
28
8
SYNC
1
2
3
4
5
6
7
FB2
Ordering Information
20
COMP2
Point-of-Load DC-DC Converters
Telecom Line Card
Networking Line Card
Power-Over-Ethernet Postregulation for PDs
21
EN2
●●
●●
●●
●●
TOP VIEW
DRAIN2
Applications
Pin Configuration
DRAIN2
The MAX5073 is available in a thermally enhanced 28-pin
thin QFN package that can dissipate 2.7W at +70°C ambient temperature. The device is rated for operation over the
-40°C to +85°C extended, or -40°C to +125°C automotive
temperature range.
●● 4.5V to 5.5V or 5.5V to 23V Input Supply
Voltage Range
●● 0.8V (Buck) to 28V (Boost) Output Voltage
●● Two Independent Output DC-DC Converters
with Internal Power MOSFETs
●● Each Output can be Configured in Buck or Boost
Mode
●● IOUT1 and IOUT2 of 2A and 1A (Respectively) in
Buck Mode
●● 180° Out-of-Phase Operation
●● Clock Output for Four Phase Operation
●● Switching Frequency Programmable from 200kHz to
2.2MHz
●● Digital Soft-Start and Sync Input
●● Individual Converter Shutdown and Power-Good
Output
●● Short-Circuit Protection (Buck)/Maximum Duty-Cycle
Limit (Boost)
●● Thermal Shutdown
●● Thermally Enhanced 28-Pin Thin QFN Package
Dissipates up to 2.7W at +70°C
PGOOD1
The MAX5073 includes an internal digital soft-start that reduces inrush current, eliminates output-voltage overshoot, and
ensures monotonic rise in output voltage during power-up.
The device includes individual shutdown and a power-good
output for each converter. Protection features include output
short-circuit protection for buck mode and maximum dutycycle limit for boost operation, as well as thermal shutdown.
Features
BST1/VDD1
The MAX5073 is a dual-output DC-DC converter with
integrated high-side n-channel power MOSFETs. Each
output can be configured either as a buck converter or a
boost converter. The device is capable of operating from
a wide 5.5V to 23V input voltage range. Each output is
programmable down to 0.8V in the buck mode and up to
28V in the boost mode with an output voltage accuracy
of ±1%. In the buck mode, converter 1 and converter 2
can deliver 2A and 1A, respectively. The output switching
frequency of each converter can be programmed from
200kHz to 2.2MHz to avoid harmonics in a radio power
supply or to reduce the size of the power supply. Each
output operates 180° out-of-phase thus reducing inputcapacitor ripple current, size, and cost. A SYNC input
facilitates external frequency synchronization. Moreover,
a CLKOUT output provides out-of-phase clock signal
with respect to converter 2, allowing four-phase operation
using two MAX5073 ICs in master-slave configuration.
CLKOUT
General Description
BST2/VDD2
MAX5073
THIN QFN
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Absolute Maximum Ratings
V+ to PGND...........................................................-0.3V to +25V
SGND to PGND.....................................................-0.3V to +0.3V
VL to SGND..................-0.3V to the lower of +6V or (V+ + 0.3V)
BST1/VDD1, BST2/VDD2, DRAIN_, PGOOD2, PGOOD1 to
SGND.................................................................-0.3V to +30V
BST1/VDD1 to SOURCE1,
BST2/VDD2 to SOURCE2 ..................................-0.3V to +6V
SOURCE_ to SGND..............................................-0.6V to +25V
EN_ to SGND............................................-0.3V to (VL to +0.3V)
CLKOUT, BYPASS, OSC, COMP1,
COMP2, SYNC, FB_ to SGND................-0.3V to (VL + 0.3V)
SOURCE1, DRAIN1 Peak Current.............................5A for 1ms
SOURCE2, DRAIN2 Peak Current.............................3A for 1ms
VL, BYPASS to SGND Short Circuit..........................Continuous
Continuous Power Dissipation (TA = +70°C)
28-Pin Thin QFN (derate 21.3mW/°C above +70°C)... 2758mW*
Package Junction-to-Case Thermal Resistance (θJC).......2°C/W
Operating Temperature Ranges:
MAX5073ETI (TMIN to TMAX).......................... -40°C to +85°C
MAX5073ATI (TMIN to TMAX)........................ -40°C to +125°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
*As per JEDEC51 standard.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22µF, CVL = 4.7µF (ceramic),
ROSC = 10kΩ (circuit of Figure 1), TA = TJ = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
Input Voltage Range
V+
Operating Supply Current
IQ
V+ Standby Supply Current
ISTBY
Efficiency
η
(Note 2)
5.5
23.0
VL = V+
4.5
5.5
VL unloaded, no switching, VFB_ = 1V,
V+ = 12V, ROSC = 60kΩ
2.2
4
0.6
1.2
EN_ = 0, PGOOD_ floating, V+ = 12V,
ROSC = 60kΩ (MAX5073ATI)
0.6
1.4
V+ = VL = 5V
82
V+ = 12V
80
V+ = 16V
78
EN_ = 0, PGOOD_ floating, V+ = 12V,
ROSC = 60kΩ (MAX5073ETI)
VOUT1 = 3.3V at 1.5A,
VOUT2 = 2.5V at 0.75A
(fSW = 1.25MHz)
V
mA
mA
%
STARTUP/VL REGULATOR
VL Undervoltage Lockout Trip
Level
UVLO
VL falling
3.95
VL Undervoltage Lockout
Hysteresis
VL Output Voltage
4.1
4.25
175
VL
V
mV
V+ = 5.5V to 23V, ISOURCE = 0 to 40mA
4.9
5.2
5.5
IBYPASS = 0, ROSC = 60kΩ (MAX5073ETI)
1.98
2.00
2.02
IBYPASS = 0, ROSC = 60kΩ (MAX5073ATI)
1.975
2.00
2.025
0
2
10
V
BYPASS OUTPUT
BYPASS Voltage
BYPASS Load Regulation
VBYPASS
∆VBYPASS
0 ≤ IBYPASS ≤ 50µA, ROSC = 60kΩ
V
mV
SOFT-START
Digital Ramp Period
Soft-Start Steps
www.maximintegrated.com
Internal 6-bit DAC
2048
fOSC
clock
cycles
64
Steps
Maxim Integrated │ 2
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Electrical Characteristics (continued)
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22µF, CVL = 4.7µF (ceramic),
ROSC = 10kΩ (circuit of Figure 1), TA = TJ = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
250
nA
VOLTAGE-ERROR AMPLIFIER
FB_ Input Bias Current
IB(EA)
FB_ Input Voltage Set Point
FB_ to COMP_
Transconductance
gM
0°C ≤ TA ≤ +70°C
0.792
0.8
0.808
-40°C ≤ TA ≤ +85°C
0.788
0.8
0.812
-40°C ≤ TJ ≤ +125°C (MAX5073ATI only)
0.788
0.8
0.812
0°C to +85°C
1.25
2
2.70
40°C to +85°C
1.2
2
2.9
-40°C to +125°C (MAX5073ATI only)
1.2
2
2.9
ISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 5.2V
(MAX5073ETI)
195
290
ISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 5.2V
(MAX5073ATI)
195
330
V
mS
INTERNAL PMOSFETS
On-Resistance Converter 1
RON1
mΩ
ISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 4.5V
(MAX5073ETI)
ISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 4.5V
(MAX5073ATI)
On-Resistance Converter 2
RON2
ISWITCH = 100mA,
VBST2/VDD2 to VSOURCE2 = 5.2V
330
630
ISWITCH = 100mA,
VBST2/VDD2 to VSOURCE2 = 4.5V
350
690
mΩ
Minimum Converter 1 Output
Current
IOUT1
VOUT1 = 3.3V, V+ = 12V (Note 3)
2
A
Minimum Converter 2 Output
Current
IOUT2
VOUT2 = 2.5V, V+ = 12V (Note 3)
1
A
Converter 1 MOSFET Leakage
Current
ILK1
EN1 = 0V, VDS = 23V
10
µA
Converter 2 MOSFET Leakage
Current
ILK2
EN2 = 0V, VDS = 23V
10
µA
INTERNAL SWITCH CURRENT LIMIT
Current-Limit Converter 1
ICL1
Current-Limit Converter 2
ICL2
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V+ = 12V (MAX5073ETI)
2.3
3
4.3
V+ = 12V (MAX5073ATI)
2.3
3
MAX5073ETI
1.38
1.8
4.6
2.10
MAX5073ATI
1.38
1.8
2.20
A
A
Maxim Integrated │ 3
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Electrical Characteristics (continued)
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22µF, CVL = 4.7µF (ceramic),
ROSC = 10kΩ (circuit of Figure 1), TA = TJ = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
SYNC = SGND, fSW = 1.25MHz
84
86
95
84
86
95
200
1125
UNITS
INTERNAL OSCILLATOR/SYNC
Maximum Duty Cycle
DMAX
Switching Frequency Range
fSW
SYNC = SGND, fSW = 2.2MHz
Each converter
Switching Frequency
fSET
ROSC = 10kΩ, each converter
Switching Frequency Accuracy
SYNC Frequency Range
SYNC High Threshold
fSYNC
VSYNCL
SYNC Input Min Pulse Width
tSYNCIN
Clock Output Phase Delay
SYNC to SOURCE1 Phase
Delay
CLKOUT
PHASE
2200
kHz
1375
kHz
5.6kΩ ≤ ROSC ≤ 56kΩ, 1% each converter
-15
+15
%
SYNC input frequency is twice the
individual converter frequency
400
4400
kHZ
VSYNCH
SYNC Low Threshold
1250
%
2.4
V
0.8
ROSC = 60kΩ, 1%, with respect to
converter 2 / SOURCE2 waveform
SYNCPHASE ROSC = 60kΩ, 1%
Clock Output High Level
VCLKOUTH
VL = 5.2V, sourcing 5mA
Clock Output Low Level
VCLKOUTL
VL = 5.2V, sinking 5mA
V
100
ns
45
degrees
45
degrees
4
V
0.4
V
EN_ INPUTS
EN_ Input High Threshold
VIH
V+ = VL = 5.2V
EN_ Input Low Threshold
VIL
V+ = VL = 5.2V
EN_ Bias Current
2.4
1.8
1.2
IB(EN)
V
0.8
V
250
nA
95
%VOUT
POWER-GOOD OUTPUT (PGOOD_)
PGOOD_ Threshold
PGOOD_ Output Voltage
PGOOD_ Output Leakage
Current
PGOODVTH_
VPGOOD_
PGOOD goes high after VOUT crosses
PGOOD_ threshold
90
92.5
ISINK = 3mA (MAX5073ETI)
0.4
ISINK = 3mA (MAX5073ATI)
0.52
V+ = VL = 5.2V, VPGOOD_ = 23V,
ILKPGOOD_
VFB_ = 1V
1
V
µA
THERMAL MANAGEMENT
Thermal Shutdown
TSHDN
Junction temperature
+150
°C
Thermal Hysteresis
THYST
Junction temperature
30
°C
Note 1: Specifications at -40°C are guaranteed by design and not production tested.
Note 2: Operating supply range (V+) is guaranteed by VL line regulation test. Connect V+ to VL for 5V operation.
Note 3: Output current may be limited by the power dissipation of the package, refer to the Power Dissipation section in the
Applications Information.
www.maximintegrated.com
Maxim Integrated │ 4
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Typical Operating Characteristics
(V+ = VL = 5.2V, TA = +25°C, unless otherwise noted.)
70
VIN = 12.0V
60
VIN = 16.0V
50
40
30
20
VIN = 12.0V
50
VIN = 16.0V
40
30
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.3
0.4
0.5
0.6
0.7
0.8
VIN = 5V
90
80
70
VIN = 3.3V
60
50
40
30
20
VOUT = 2.5V
fSW = 2.2MHz
0.2
VOUT = 12V
fSW = 2.2MHz
10
0
0.9 1.0
0.02
VL OUTPUT VOLTAGE
vs. CONVERTER SWITCHING FREQUENCY
5.50
MAX5073 toc05
2.60
BOTH CONVERTERS SWITCHING
5.45
5.40
5.35
VL (V)
2.55
5.30
VIN = 23V
5.25
5.20
2.50
5.15
5.10
0
0.5
1.0
1.5
2.45
2.0
MAX5073 toc06
OUTPUT2 VOLTAGE (BUCK CONVERTER)
vs. LOAD CURRENT
VIN = 5.5V
5.05
0
0.25
0.50
0.75
5.00
1.00
0.1
0.6
1.1
1.6
2.1
LOAD (A)
SWITCHING FREQUENCY (fSW) (MHz)
VL DROPOUT VOLTAGE vs. EACH
CONVERTER SWITCHING FREQUENCY
EACH CONVERTER SWITCHING FREQUENCY
vs. ROSC
EACH CONVERTER SWITCHING
FREQUENCY vs. TEMPERATURE
0.20
VIN = 5V
0.15
0.10
VIN = 4.5V
0.05
0
0.5
1.0
1.5
2.0
SWITCHING FREQUENCY (fSW) (MHz)
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2.5
1
0.1
0
20
40
ROSC (kΩ)
60
80
2.6
MAX5073 toc09
10
SWITCHING FREQUENCY (fSW) (MHz)
0.25
10
MAX5073 toc08
VIN = 5.5V
SWITCHING FREQUENCY (fSW) (MHz)
MAX5073 toc07
LOAD (A)
0.30
DROPOUT VOLTAGE (V)
0.20
OUTPUT1 VOLTAGE (BUCK CONVERTER)
vs. LOAD CURRENT
3.25
0
0.14
LOAD (A)
3.30
0.35
0.08
LOAD (A)
3.35
3.20
MAX5073 toc03
100
LOAD (A)
OUTPUT2 VOLTGE (V)
OUTPUT1 VOLTAGE (V)
3.40
60
10
MAX5073 toc04
0
70
20
VOUT = 3.3V
fSW = 2.2MHz
10
VIN = 5V
80
EFFICIENCY (%)
EFFICIENCY (%)
80
90
OUTPUT2 EFFICIENCY (BOOST CONVERTER)
vs. LOAD CURRENT
MAX5073 toc02
VIN = 5V
90
100
MAX5073 toc01
100
OUTPUT2 EFFICIENCY (BUCK CONVERTER)
vs. LOAD CURRENT
EFFICIENCY (%)
OUTPUT1 EFFICIENCY (BUCK CONVERTER)
vs. LOAD CURRENT
2.2MHz
1.25MHz
1
0.6MHz
0.3MHz
0.1
-50
0
50
100
150
TEMPERATURE (°C)
Maxim Integrated │ 5
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Typical Operating Characteristics (continued)
(V+ = VL = 5.2V, TA = +25°C, unless otherwise noted.)
LINE-TRANSIENT RESPONSE
(BUCK CONVERTER)
CONVERTER 1 LOAD-TRANSIENT
RESPONSE (BUCK CONVERTER)
MAX5073 toc10
MAX5073 toc11
VIN
5V/div
0V
VOUT1 = 3.3V
AC-COUPLED
200mV/div
VOUT1 = 3.3V/1.5A
AC-COUPLED
200mV/div
IOUT1
1A/div
VOUT2 = 2.5V/0.75A
AC-COUPLED
200mV/div
1ms/div
0A
100µs/div
CONVERTER 2 LOAD-TRANSIENT
RESPONSE (BUCK CONVERTER)
SOFT-START/SOFT-STOP
MAX5073 toc12
MAX5073 toc13
VOUT1 = 3.3V
AC-COUPLED
100mV/div
ENABLE
5V/div
0V
VOUT2 = 2.5V
AC-COUPLED
100mV/div
VOUT1 = 3.3V/1A
2V/div
0V
VOUT2 = 2.5V/0.5A
2V/div
IOUT2
500mA/div
0A
100µs/div
0V
2ms/div
LOAD-TRANSIENT RESPONSE
(BOOST CONVERTER)
OUT-OF-PHASE OPERATION
MAX5073 toc14
MAX5073 toc15
VOUT1 = 3.3V
AC-COUPLED
200mV/div
SOURCE2
5V/div
0V
VOUT2 = 12V
AC-COUPLED
200mV/div
SOURCE1
5V/div
0V
INPUT RIPPLE
AC-COUPLED
20mV/div
CLKOUT
5V/div
0V
IOUT2
50mA/div
0A
100µs/div
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100ns/div
Maxim Integrated │ 6
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Typical Operating Characteristics (continued)
(V+ = VL = 5.2V, TA = +25°C, unless otherwise noted.)
SYNC
5V/div
0V
1.8
SOURCE1
5V/div
0V
1.4
ROSC = 10kΩ
ISTBY (mA)
MAX5073 toc16
MAX5073 toc17
V+ STANDBY SUPPLY CURRENT (ISTBY)
vs. TEMPERATURE
EXTERNAL SYNCHRONIZATION
VOUT1 RIPPLE
AC-COUPLED
20mV/div
CLKOUT
5V/div
0V
1.0
ROSC = 60kΩ
0.6
0.2
200ns/div
-7
-40
26
59
92
125
TEMPERATURE (°C)
3.38
OUTPUT1 VOLTAGE (V)
fSW = 2.2MHz
25
fSW = 1.25MHz
20
fSW = 600kHz
15
fSW = 300kHz
10
5
OUTPUT1 VOLTAGE (BUCK CONVERTER)
vs. TEMPERATURE
MAX5073 toc19
30
ISUPPLY (mA)
3.40
MAX5073 toc18
35
V+ SWITCHING SUPPLY
CURRENT (ISUPPLY) vs. TEMPERATURE
3.36
NO LOAD
3.34
3.32
50% LOAD
3.30
3.28
3.26
3.24
3.22
-40
-7
26
59
92
3.20
125
0
-50
TEMPERATURE (°C)
50
100
150
TEMPERATURE (°C)
MAX5073 toc20
2.60
OUTPUT2 VOLTAGE (BUCK CONVERTER)
vs. TEMPERATURE
OUTPUT2 VOLTAGE (V)
50% LOAD
2.55
NO LOAD
2.50
2.45
2.40
-50
0
50
100
150
TEMPERATURE (°C)
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Maxim Integrated │ 7
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Typical Operating Characteristics (continued)
(V+ = VL = 5.2V, TA = +25°C, unless otherwise noted.)
VIN = 5.5V
fSW = 2.2MHz
2.75
2.50
MAX5073 toc22
MAX5073 toc21
3.00
OUTPUT CURRENT LIMIT (A)
FOUR-PHASE OPERATION
(SEE FIGURE 3)
OUTPUT LOAD CURRENT LIMIT
vs. TEMPERATURE
SOURCE1
(MASTER)
0V
OUTPUT1
2.25
2.00
SOURCE2
(MASTER)
0V
OUTPUT2
1.75
SOURCE1
(SLAVE)
0V
1.50
SOURCE2
(SLAVE)
1.25
1.00
-40
-5
30
65
400ns/div
100
TEMPERATURE (°C)
Pin Description
PIN
NAME
1
CLKOUT
Clock Output. CLKOUT is 45° phase-shifted with respect to converter 2 (SOURCE2, Figure 3). Connect
CLKOUT (master) to the SYNC of a second MAX5073 (slave) for a four-phase converter.
2
BST2/VDD2
Buck Converter Operation—Bootstrap Flying-Capacitor Connection for Converter 2. Connect BST2/
VDD2 to an external ceramic capacitor and diode according to the standard application circuit (Figure
1). Boost Converter Operation—Driver Bypass Capacitor Connection. Connect a low-ESR 0.1µF
ceramic capacitor from BST2/VDD2 to PGND (Figure 8).
3, 4
DRAIN2
Connection to Converter 2 Internal MOSFET Drain. Buck converter operation—use the MOSFET as a
high-side switch and connect DRAIN2 to the input supply. Boost converter operation—use the MOSFET
as a low-side switch and connect DRAIN2 to the inductor and diode junction (Figure 8).
5
EN2
Active-High Enable Input for Converter 2. Drive EN2 low to shut down converter 2, drive EN2 high for
normal operation. Use EN2 in conjunction with EN1 for supply sequencing. Connect to VL for always-on
operation.
6
FB2
Feedback Input for Converter 2. Connect FB2 to a resistive divider between converter 2’s output and
SGND to adjust the output voltage. To set the output voltage below 0.8V, connect FB2 to a resistive
voltage-divider from BYPASS to regulator 2’s output (Figure 5). See the Setting the Output Voltage
section.
7
COMP2
8
SYNC
9
N.C.
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FUNCTION
Compensation Connection for Converter 2. See the Compensation section to compensate converter
2’s control loop.
External Clock Synchronization Input. Connect SYNC to a 400kHz to 4400kHz clock to synchronize the
switching frequency with the system clock. Each converter frequency is one half the frequency applied
to SYNC. Connect SYNC to SGND when not used.
No Connection. Not internally connected.
Maxim Integrated │ 8
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Pin Description (continued)
PIN
NAME
FUNCTION
10
OSC
Oscillator Frequency Set Input. Connect a resistor from OSC to SGND (ROSC) to set the switching
frequency (see the Oscillator section). Set ROSC for equal to or lower oscillator frequency than the
SYNC input frequency when using external synchronization (0.2fSYNC < fOSC < 1.2fSYNC). ROSC is still
required when an external clock is connected to the SYNC input.
11
V+
Input Supply Voltage. V+ voltage range from 5.5V to 23V. Connect the V+ and VL together for 4.5V to
5.5V input operation. Bypass with a minimum 0.1µF ceramic capacitor to SGND.
12, 13
VL
Internal 5.2V Linear Regulator Output. Use VL to drive the high-side switch at BST1/VDD1 and
BST2/VDD2. Bypass VL with a 0.1µF capacitor to PGND and a 4.7µF ceramic capacitor to SGND.
14
BYPASS
2.0V Output. Bypass to SGND with a 0.22µF or greater ceramic capacitor.
15
COMP1
Compensation Connection for Converter 1 (See the Compensation Section)
16
FB1
Feedback Input for Converter 1. Connect FB1 to a resistive divider between converter 1’s output and
SGND to program the output voltage. To set the output voltage below 0.8V, connect FB1 to a resistive
voltage- divider from BYPASS to regulator 1’s output (Figure 5). See the Setting the Output Voltage
section.
17
EN1
Active-High Enable Input for Converter 1. Drive EN1 low to shut down converter 1, drive EN1 high for
normal operation. Use EN1 in conjunction with EN2 for supply sequencing. Connect to VL for always-on
operation.
DRAIN1
Connection to the Converter 1 Internal MOSFET Drain.
Buck converter operation—use the MOSFET as a high-side switch and connect DRAIN1 to the input
supply. Boost converter operation—use the MOSFET as a low-side switch and connect DRAIN1 to the
inductor and diode junction.
20
BST1/VDD1
Buck Converter Operation—Bootstrap Flying-Capacitor Connection for Converter 1. Connect
BST1/VDD1 to an external ceramic capacitor and diode according to the Standard Application Circuit
(Figure 1). Boost Converter Operation—Driver Bypass Capacitor Connection. Connect a low-ESR
0.1µF ceramic capacitor from BST1/VDD1 to PGND.
21
PGOOD1
Converter 1 Power-Good Output. Open-drain output goes low when converter 1’s output falls below
92.5% of its set regulation voltage. Use PGOOD1, PGOOD2, EN1, and EN2 to sequence the
converters.
22
PGOOD2
Converter 2 Power-Good Output. Open-drain output goes low when converter 2’s output falls below
92.5% of its set regulation voltage.
23, 24
SOURCE1
Connection to the Converter 1 Internal MOSFET Source.
Buck converter operation—connect SOURCE1 to the switched side of the inductor as shown in Figure 1.
Boost converter operation—connect SOURCE1 to PGND.
25
SGND
Signal Ground. Connect SGND to the exposed pad. Connect SGND and PGND together at a single
point.
26
PGND
Power Ground. Connect rectifier diode anode, input capacitor negative, output capacitor negative, and
VL bypass capacitor returns to PGND.
27, 28
SOURCE2
EP
SGND
18, 19
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Connection to the Converter 2 Internal MOSFET Source.
Buck converter operation—connect SOURCE2 to the switched side of the inductor as shown in Figure 1.
Boost converter operation—connect SOURCE2 to PGND (Figure 8).
Exposed Paddle. Connect to SGND. Solder EP to the SGND plane for better thermal performance.
Maxim Integrated │ 9
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
PGOOD2
OUTPUT2
2.5V/1A
OUTPUT1
3.3V/2A
VL
CLOCK
OUT
28 27 26 25 24 23 22
SOURCE2 PGND SGND SOURCE1PGOOD2
PGOOD1 21
1 CLKOUT
2 BST2/VDD2
INPUT
SGND
EP
4 DRAIN2
5 EN2
BST1/VDD1 20
INPUT
DRAIN1 19
3 DRAIN2
ON
OFF
VL
DRAIN1 18
MAX5073
EN1 17
FB1 16
6 FB2
COMP1 15
7 COMP2
SYNC N.C. OSC V+
8
9
10 11
ON
OFF
VL BYPASS
13 14
VL
12
SGND
SYSTEM
CLOCK
VIN = 5.5V TO 23V
PGND
SGND
*CONNECT PGND AND SGND TOGETHER AT ONE POINT NEAR THE
RETURN TERMINALS OF THE V+ AND VL BYPASS CAPACITORS.
Figure 1. MAX5073 Dual Buck Regulator Application Circuit
Detailed Description
PWM Controller
The MAX5073 converter uses a pulse-width modulation
(PWM) voltage-mode control scheme for each out-ofphase controller. It is nonsynchronous rectification and
uses an external low-forward-drop Schottky diode for
rectification. The controller generates the clock signal by
dividing down the internal oscillator or the SYNC input
when driven by an external clock, so each controller’s
switching frequency equals half the oscillator frequency
(fSW = fOSC/2). An internal transconductance error amplifier produces an integrated error voltage at the COMP pin,
providing high DC accuracy. The voltage at COMP sets
the duty cycle using a PWM comparator and a ramp generator. At each rising edge of the clock, converter 1’s highside n-channel MOSFET turns on and remains on until
either the appropriate or maximum duty cycle is reached,
or the maximum current limit for the switch is detected.
Converter 2 operates out-of-phase, so the second highside MOSFET turns on at each falling edge of the clock.
In the case of buck operation (Figure 1), during each highside MOSFET?s on-time, the associated inductor current
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ramps up. During the second half of the switching cycle,
the high-side MOSFET turns off and forward biases the
Schottky rectifier. During this time, the SOURCE voltage is clamped to 0.4V (VD) below ground. The inductor
releases the stored energy as its current ramps down,
and provides current to the output. The bootstrap capacitor is also recharged from the inductance energy when
the MOSFET turns off. The circuit goes in discontinuous
conduction mode operation at light load, when the inductor current completely discharges before the next cycle
commences. Under overload conditions, when the inductor current exceeds the peak current limit of the respective
switch, the high-side MOSFET turns off quickly and waits
until the next clock cycle.
In the case of boost operation, the MOSFET is a low-side
switch (Figure 8). During each on-time, the inductor current ramps up. During the second half of the switching
cycle, the low-side switch turns off and forward biases
the Schottky diode. During this time, the DRAIN voltage
is clamped to 0.4V (VD) above VOUT_ and the inductor
provides energy to the output as well as replenishes the
output capacitor charge.
Maxim Integrated │ 10
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Internal Oscillator/Out-of-Phase Operation
The internal oscillator generates the 180° out-of-phase
clock signal required by each regulator. The internal oscillator frequency is programmable from 400kHz to 4.4MHz
using a single 1% resistor at ROSC. Use the following
equation to calculate ROSC:
R OSC =
25 × 10 9
f OSC
where fOSC is the internal oscillator frequency in hertz
and ROSC in ohms.
The two independent regulators in the MAX5073 switch
180° out-of-phase to reduce input filtering requirements,
to reduce electromagnetic interference (EMI), and to
improve efficiency. This effectively lowers component cost
and saves board space, making the MAX5073 ideal for
cost-sensitive applications.
With dual synchronized out-of-phase operation, the
MAX5073’s high-side MOSFETs turn on 180° out-ofphase. The instantaneous input current peaks of both
regulators do not overlap, resulting in reduced RMS
ripple current and input voltage ripple. This reduces the
required input capacitor ripple current rating, allows for
fewer or less expensive capacitors, and reduces shielding
requirements for EMI. The out-of-phase waveforms in the
Typical Operating Characteristics demonstrate synchronized 180° out-of-phase operation.
Synchronization (SYNC)/
Clock Output (CLKOUT)
The main oscillator can be synchronized to the system
clock by applying an external clock (fSYNC) at SYNC.
The fSYNC frequency must be twice the required operating frequency of an individual converter. Use a TTL logic
signal for the external clock with at least a 100ns pulse
width. ROSC is still required when using external synchronization. Program the internal oscillator frequency so
0.2fSYNC < fOSC < 1.2fSYNC. The rising edge of fSYNC
synchronizes the turn-on edge of the internal MOSFET
(see Figure 3).
R OSC =
25 × 10 9
f OSC
where fOSC is the internal oscillator frequency in hertz
and ROSC in ohms, fOSC = 2 x fSW.
Two MAX5073s can be connected in the master-slave
configuration for four ripple-phase operation. The
MAX5073 provides a clock output (CLKOUT) that is 45°
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phase-shifted with respect to the internal switch turn-on
edge. Feed the CLKOUT of the master to the SYNC input
of the slave. The effective input ripple switching frequency
shall be four times the individual converter’s switching frequency. When driving the master converter using external
clock at SYNC, set the clock duty cycle to 50% for a 90°
phase-shifted operation.
Input Voltage (V+)/Internal Linear
Regulator (VL)
All internal control circuitry operates from an internally regulated nominal voltage of 5.2V (VL). At higher input voltages (V+) of 5.5V to 23V, VL is regulated to 5.2V. At 5.5V
or below, the internal linear regulator operates in dropout
mode, where VL follows V+. Depending on the load on
VL, the dropout voltage can be high enough to reduce VL
below the undervoltage lockout (UVLO) threshold.
For input voltages of less than 5.5V, connect V+ and VL
together. The load on VL is proportional to the switching frequency of converter 1 and converter 2. See the
Dropout Voltage vs. Switching Frequency graph in the
Typical Operating Characteristics. For input voltage ranges higher than 5.5V, use the internal regulator.
Bypass V+ to SGND with a low-ESR, 0.1µF or greater
ceramic capacitor placed close to the MAX5073. Current
spikes from VL may disturb internal circuitry powered by
VL. Bypass VL with a low-ESR, ceramic 0.1µF capacitor
to PGND and 4.7µF capacitor to SGND.
Undervoltage Lockout/Soft-Start
The MAX5073 includes an undervoltage lockout with
hysteresis and a power-on-reset circuit for converter turnon and monotonic rise of the output voltage. The rising
UVLO threshold is internally set to 4.3V with a 175mV
hysteresis. Hysteresis at UVLO eliminates “chattering”
during startup. When VL drops below UVLO, the internal
switches are turned off.
Digital soft-start is provided internally to reduce input
surge currents and glitches at the input during turn-on.
When UVLO is cleared and EN_ is high, digital soft-start
slowly ramps up the internal reference voltage in 64
steps. The total soft-start period is 2048 switching cycles
of the internal oscillator.
To calculate the soft-start period, use the following
equation:
2048
t SS =
f OSC
where fOSC is the internal oscillator frequency in hertz,
which is twice the switching frequency of each converter.
Maxim Integrated │ 11
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
V+
MAX5073
VL
LDO
CONVERTER 1
VL
OSCILLATOR
DEAD-TIME
CONTROL
BST1/VDD1
FREQUENCY
FOLDBACK
DRAIN1
BYPASS
Q
N
SOURCE1
Q
Q
PGOOD1
fSW / 4
VREF
EN1
VREF
DIGITAL
SOFT-START
FB1
COMP1
0.5VREF
0.92VREF
SYNC
CKO
OSC
PGOOD2
MAIN
OSCILLATOR
BST2/VDD2
VL
VDD2
OSCILLATOR
EN2
DRAIN2
SOURCE2
CONVERTER 2
FB2
COMP2
Figure 2. Functional Diagram
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Maxim Integrated │ 12
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
VIN
OUTPUT2
DUTY CYCLE = 50% CLKIN
CIN
DRAIN2
SOURCE2
SYNC
V+
DRAIN1
SOURCE1
OUTPUT1
CLKOUT
OUTPUT4
V+
DRAIN2
SOURCE2
DRAIN1
SOURCE1
OUTPUT3
SYNC
MASTER
SLAVE
SYNC
CLKOUT
(MASTER)
CLKOUT
(SLAVE)
SOURCE1
(MASTER)
SYNCPHASE
CLKOUTPHASE
SOURCE2
(MASTER)
SOURCE1
(SLAVE)
SOURCE2
(SLAVE)
CIN (RIPPLE)
Figure 3. Synchronized Controllers
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Maxim Integrated │ 13
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Enable
The MAX5073 dual converter provides separate enable
inputs EN1 and EN2 to individually control or sequence
the output voltages. These active-high enable inputs are
TTL compatible. Pulling EN_ high ramps up the reference slowly, which provides soft-start at the outputs.
Forcing the EN_ low externally disables the individual
output and generates a PGOOD_ signal. Use EN1, EN2,
and PGOOD1 for sequencing (see Figure 4). Connect
PGOOD1 to EN2 to make sure converter 1’s output is
within regulation before converter 2 starts. Add an RC network from VL to EN1 and EN2 to delay the individual converter. A larger RC time constant means a more delayed
output. Sequencing reduces input inrush current and
possible chattering. Connect the EN_ to VL for always-on
operation.
PGOOD_
Converter 1 and converter 2 includes a power-good flag,
PGOOD1 and PGOOD2, respectively. Since PGOOD is
an open-drain output and can sink 3mA while providing
the TTL logic-low signal, pull PGOOD to a logic voltage to
provide a logic-level output. PGOOD goes low when converter 1’s output drops to 92.5% of its nominal regulated
voltage. Connect PGOOD to SGND or leave unconnected
if not used.
Current Limit
The internal switch current of each converter is sensed
using an internal current mirror. Converter 1 and converter 2 have 2A and 1A internal switches. When the
peak switch current crosses the current-limit threshold
of 3A (typ) and 1.8A (typ) for converter 1 and converter
2, respectively, the on cycle is terminated immediately
and the inductor is allowed to discharge. The next cycle
resumes at the next clock pulse.
In deep overload or short-circuit conditions when the
FB voltage drops below 0.4V, the switching frequency
is reduced to 1/4 x fSW to provide sufficient time for the
inductor to discharge. During overload conditions, if the
voltage across the inductor is not high enough to allow
for the inductor current to properly discharge, current runaway may occur. Current runaway can destroy the device
in spite of internal thermal-overload protection. Reducing
the switching frequency during overload conditions prevents current runaway.
Thermal-Overload Protection
During continuous short circuit or overload at the output, the power dissipation in the IC can exceed its limit.
Internal thermal shutdown is provided to avoid irreversible damage to the device. When the die temperature or
junction temperature exceeds +150°C, an on-chip thermal
sensor shuts down the device, forcing the internal switches to turn off, allowing the IC to cool. The thermal sensor
turns the part on again after the junction temperature
cools by +30°C. During thermal shutdown, both regulators
shut down, PGOOD_ go low, and soft-start resets.
VIN
VIN
VL
VL
OUTPUT2
VL
DRAIN2
SOURCE2
V+
DRAIN1
OUTPUT1
SOURCE1
VL
DRAIN2
OUTPUT2
SOURCE2
MAX5073
VL
V+
DRAIN1
OUTPUT1
SOURCE1
MAX5073
FB2
FB1
EN2
EN1
VL
PGOOD1
SEQUENCING—OUTPUT 2 DELAYED WITH RESPECT TO OUTPUT 1.
R2
VL
FB2
FB1
EN2
EN1
C2
R1
VL
C1
R1/C1 AND R2/C2 ARE SIZED FOR REQUIRED SEQUENCING.
Figure 4. Power-Supply Sequencing Configurations
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Maxim Integrated │ 14
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Applications Information
Setting the Switching Frequency
The controller generates the clock signal by dividing down
the internal oscillator or the SYNC input signal when
driven by an external oscillator. The switching frequency
equals half the oscillator frequency (fSW = fOSC/2). The
internal oscillator frequency is set by a resistor (ROSC)
connected from OSC to SGND. The relationship between
fSW and ROSC is:
R OSC =
12.5 × 10 9
f SW
where fSW and fOSC are in hertz, and ROSC is in ohms.
For example, a 1250kHz switching frequency is set
with ROSC = 10kΩ. Higher frequencies allow designs
with lower inductor values and less output capacitance.
Consequently, peak currents and I2R losses are lower
at higher switching frequencies, but core losses, gatecharge currents, and switching losses increase.
A rising clock edge on SYNC is interpreted as a synchronization input. If the SYNC signal is lost, the internal
oscillator takes control of the switching rate, returning the
switching frequency to that set by ROSC. This maintains
output regulation even with intermittent SYNC signals.
When an external synchronization signal is used, ROSC
should be set for the oscillator frequency to be lower than
or equal to the SYNC rate (fSYNC).
Buck Converter
Effective Input Voltage Range
Although the MAX5073 converters can operate from input
supplies ranging from 5.5V to 23V, the input voltage range
can be effectively limited by the MAX5073 duty-cycle
limitations for a given output voltage. The maximum input
voltage is limited by the minimum on-time (tON(MIN)):
VOUT
VIN(MAX) ≤
t ON(MIN) × f SW
where tON(MIN) is 100ns. The minimum input voltage is
limited by the maximum duty cycle (DMAX = 88):
+ VDROP1
V
=
VIN(MIN)  OUT
 + VDROP2 − VDROP1
0.88


where VDROP1 is the total parasitic voltage drops in the
inductor discharge path, which includes the forward voltage drop (VD) of the rectifier, the series resistance of the
inductor, and the PC board resistance. VDROP2 is the
total resistance in the charging path, which includes the
on-resistance of the high-side switch, the series resistance of the inductor, and the PC board resistance.
Setting the Output Voltage
For 0.8V or greater output voltages, connect a voltagedivider from OUT_ to FB_ to SGND (Figure 5). Select
RB (FB_ to SGND resistor) to between 1kΩ and 10kΩ.
Calculate RA (OUT_ to FB_ resistor) with the following
equation:
 V
 
R A = R B  OUT  − 1
 VFB  
where VFB_ = 0.8V (see the Electrical Characteristics
table) and VOUT_ can range from VFB_ to 28V (boost
operation).
For output voltages below 0.8V, set the MAX5073 output
voltage by connecting a voltage-divider from the output
to FB_ to BYPASS (Figure 5). Select RC (FB to BYPASS
resistor) higher than a 50kΩ range. Calculate RA with the
following equation:
 VFB − VOUT 
R A =R C 

 VBYPASS − VFB 
where VFB = 0.8V, VBYPASS = 2V (see the Electrical
Characteristics table), and VOUT_ can range from 0V to
VFB_.
LX_
BYPASS
RA
RC
FB_
MAX5073
FB_
RB
MAX5073
RA
LX_
VOUT_ > 0.8V
VOUT_ < 0.8V
Figure 5. Adjustable Output Voltage
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Maxim Integrated │ 15
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX5073: inductance value (L), peak
inductor current (IL), and inductor saturation current
(ISAT). The minimum required inductance is a function
of operating frequency, input-to-output voltage differential and the peak-to-peak inductor current (∆IL). Higher
∆IL allows for a lower inductor value while a lower ∆IL
requires a higher inductor value. A lower inductor value
minimizes size and cost, improves large-signal transient
response, but reduces efficiency due to higher peak currents and higher peak-to-peak output ripple voltage for
the same output capacitor. On the other hand, higher
inductance increases efficiency by reducing the ripple current. However, resistive losses due to extra wire turns can
exceed the benefit gained from lower ripple current levels,
especially when the inductance is increased without also
allowing for larger inductor dimensions. A good compromise is to choose ∆IL equal to 30% of the full load current.
To calculate the inductance use the following equation:
L=
The input ripple waveform would be unsymmetrical due
to the difference in load current and duty cycle between
converter 1 and converter 2. The input ripple is comprised
of ∆VQ (caused by the capacitor discharge) and ∆VESR
(caused by the ESR of the capacitor). A higher load converter dictates the ESR requirement, while the capacitance requirement is a function of the loading mismatch
between the two converters. The worst-case mismatch
is when one converter is at full load while the other is at
no load or in shutdown. Use low-ESR ceramic capacitors
with high ripple-current capability at the input. Assume the
contribution from the ESR and capacitor discharge equal
to 50%. Calculate the input capacitance and ESR required
for a specified ripple using the following equations:
ESR IN =
where
(V − VOUT ) × VOUT
∆IL = IN
VIN × f SW × L
VOUT (VIN − VOUT )
VIN × f SW × ∆IL
where VIN and VOUT are typical values (so that efficiency is optimum for typical conditions). The switching
frequency is set by ROSC (see the Setting the Switching
Frequency section). The peak-to-peak inductor current,
which reflects the peak-to-peak output ripple, is worse
at the maximum input voltage. See the Output Capacitor
Selection section to verify that the worst-case output ripple is acceptable. The inductor saturating current is also
important to avoid runaway current during output overload
and continuous short circuit. Select the ISAT to be higher
than the maximum peak current limits of 4.5A and 2.2A for
converter 1 and converter 2.
Input Capacitors
The discontinuous input current waveform of the buck
converter causes large ripple currents at the input. The
switching frequency, peak inductor current, and the
allowable peak-to-peak voltage ripple dictate the input
capacitance requirement. Increasing the switching frequency or the inductor value lowers the peak to average
current ratio, yielding a lower input capacitance requirement. Note that two converters of MAX5073 run 180°
out-of-phase, thereby effectively doubling the switching
frequency at the input.
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∆VESR
∆IL 

I OUT + 2 


and
I
× D(1 − D)
C IN = OUT
∆VQ × f SW
where
D=
VOUT
VIN
where IOUT is the maximum output current from either
converter 1 or converter 2, and D is the duty cycle for that
converter. fSW is the frequency of each individual converter. For example, at VIN = 12V, VOUT = 3.3V at IOUT
= 2A, and with L = 3.3µH, the ESR and input capacitance
are calculated for a peak-to-peak input ripple of 100mV
or less, yielding an ESR and capacitance value of 20mΩ
and 6.8µF for 1.25MHz frequency. Use a 100µF capacitor
at low input voltages to avoid possible undershoot below
the undervoltage lockout threshold during power-on and
transient loading.
Maxim Integrated │ 16
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Output Capacitors
The allowable output ripple voltage and the maximum
deviation of the output voltage during step load currents
determines the output capacitance and its ESR.
The output ripple is comprised of ∆VQ (caused by the
capacitor discharge) and ∆VESR (caused by the ESR
of the capacitor). Use low-ESR ceramic or aluminum
electrolytic capacitors at the output. For aluminum
electrolytic capacitors, the entire output ripple is contributed by ∆VESR. Use the ESROUT equation to calculate the
ESR requirement and choose the capacitor accordingly.
If using ceramic capacitors, assume the contribution to
the output ripple voltage from the ESR and the capacitor
discharge are equal. Calculate the output capacitance
and ESR required for a specified ripple using the following equations:
∆VESR
ESR OUT =
∆IL
C OUT =
where
∆IL
8 × ∆VQ × f SW
∆VO_RIPPLE ≅ ∆VESR + ∆VQ
electronics being powered. When using a ceramic capacitor, assume 80% and 20% contribution from the output
capacitance discharge and the ESR drop, respectively.
Use the following equations to calculate the required ESR
and capacitance value:
ESR OUT =
I
×t
C OUT = STEP RESPONSE
∆VQ
where ISTEP is the load step and tRESPONSE is the
response time of the controller. Controller response time
depends on the control-loop bandwidth.
Boost Converter
The MAX5073 can be configured for step-up conversion
since the internal MOSFET can be used as a low-side
switch. Use the following equations to calculate the inductor (LMIN), input capacitor (CIN), and output capacitor
(COUT) when using the converter in boost operation.
Inductor
Choose the minimum inductor value so the converter
remains in continuous mode operation at minimum output
curt (IOMIN)
where ∆IL is the peak-to-peak inductor current as calculated above and fSW is the individual converter’s switching frequency.
The allowable deviation of the output voltage during fast
transient loads also determines the output capacitance
and its ESR. The output capacitor supplies the step load
current until the controller responds with a greater duty
cycle. The response time (tRESPONSE) depends on the
closed-loop bandwidth of the converter. The high switching frequency of MAX5073 allows for higher closed-loop
bandwidth, reducing tRESPONSE and the output capacitance requirement. The resistive drop across the output
capacitor ESR and the capacitor discharge causes a voltage droop during a step load. Use a combination of lowESR tantalum and ceramic capacitors for better transient
load and ripple/noise performance. Keep the maximum
output voltage deviation above the tolerable limits of the
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∆VESR
I STEP
L MIN =
V 2 IN × D × η
2 × f SW × VO × I OMIN
where
VO + VD − VIN
VO + VD − VDS
and IOMIN = 0.25 x IO
The VD is the forward voltage drop of the external
Schottky diode, D is the duty cycle, and VDS is the voltage
drop across the internal switch. Select the inductor with
low DC resistance and with a saturation current (ISAT)
rating higher than the peak switch current limit of 4.5A and
2.2A of converter 1 and converter 2, respectively.
Maxim Integrated │ 17
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Input Capacitor
The input current for the boost converter is continuous
and the RMS ripple current at the input is low. Calculate
the capacitor value and ESR of the input capacitor using
the following equations.
IN
∆I × D
4 × f SW × ∆VQ
ESR =
where
∆VESR
∆IL
(V − VDS ) × D
∆IL = IN
L × f SW
where VDS is the total voltage drop across the internal
MOSFET plus the voltage drop across the inductor ESR.
∆IL is the peak-to-peak inductor ripple current as calculated above. ∆VQ is the portion of input ripple due to the
capacitor discharge and ∆VESR is the contribution due to
ESR of the capacitor.
RMS current in the switch while the switching loss is a
function of switching frequency and input voltage. Use
the following equations to calculate the RMS current,
DC loss, and switching loss of each converter. The
MAX5073 device is available in a thermally enhanced
package and can dissipate up to 2.7W at +70°C ambient
temperature. The total power dissipation in the package must be limited so the junction temperature does
not exceed its absolute maximum rating of +150°C at
maximum ambient temperature.
For the buck converter:
=
IRMS
=
PDC I2 RMS × R DS(ON)MAX
where
Output Capacitor
For the boost converter, the output capacitor supplies the
load current when the main switch is ON. The required
output capacitance is high, especially at higher duty
cycles. Also, the output capacitor ESR needs to be low
enough to minimize the voltage drop due to the ESR while
supporting the load current. Use the following equation to
calculate the output capacitor for a specified output ripple
tolerance.
∆VESR
ESR =
IO
I × D MAX
C OUT = O
∆VQ × f SW
IO is the load current, ∆VQ is the portion of the ripple due
to the capacitor discharge and ∆VESR is the contribution
due to the ESR of the capacitor. DMAX is the maximum
duty cycle at minimum input voltage.
Power Dissipation
The MAX5073 includes a high-frequency, low RDS_ON
switching MOSFET. At +85°C, the RDS_ON of the internal
switch for converter 1 and converter 2 are 290mΩ and
630mΩ, respectively. The DC loss is a function of the
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D
(I2 DC +I2 PK +(IDC × IPK )) × MAX
3
IDC
= IO −
∆IL
2
IPK
= IO +
∆IL
2
See the Electrical Characteristics table for the RDS(ON)MAX
value.
V
×I ×(t + t )× f
PSW = INMAX O R F SW
4
For the boost converter:
=
IRMS
D
(I2 DC +I2 PK +(IDC × IPK )) × MAX
3
IIN =
VO × I O
VIN ×η
(V − VDS ) ×D
∆IL = IN
L × f SW
IDC
= IIN −
∆IL
2
IPK
= IIN +
∆IL
2
Maxim Integrated │ 18
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
=
PDC I2 RMS × R DS(ON)MAX
where VDS is the drop across the internal MOSFET. See
the Electrical Characteristics for the RDS(ON)MAX value.
PSW =
VO ×IIN ×(t R + t F )× f SW
4
where tR and tF are rise and fall times of the internal
MOSFET. The tR and tF are typically 20ns, and can be
measured in the actual application.
The supply current in the MAX5073 is dependent on
the switching frequency. See the Typical Operating
Characteristics to find the supply current of the MAX5073
at a given operating frequency. The power dissipation
(PS) in the device due to supply current (IS) is calculated
using fowing equation.
=
PS VINMAX ×I SUPPLY
The total power dissipation PT in the device is:
PT = PDC1 + PDC2 + PSW1 + PSW2 + PS
where PDC1 and PDC2 are DC losses in converter 1 and
converter 2, respectively. PSW1 and PSW2 are switching
losses in converter 1 and converter 2.
Calculate the temperature rise of the die using the
following equation:
or ceramic capacitors at the output. The high switching
frequency of MAX5073 allows use of ceramic capacitors
at the output.
Choose all the passive power components that meet
the output ripple, component size, and component cost
requirements. Choose the small-signal components for
the error amplifier to achieve the desired closed-loop
bandwidth and phase margin. Use a simple pole-zero pair
(Type II) compensation if the output capacitor ESR zero
frequency is below the unity-gain crossover frequency
(fC). Type III compensation is necessary when the ESR
zero frequency is higher than fC or when compensating
for a continuous mode boost converter that has a righthalf-plane zero.
Use the following procedure 1 to calculate the compensation network components when fZERO,ESR < fC.
Buck Converter Compensation
Procedure 1 (See Figure 6)
1) Calculate the fZERO,ESR and LC double pole:
1
f ZERO,ESR =
2π× ESR × C OUT
f LC =
1
2π × L OUT × C OUT
2) Calculate the unity-gain crossover frequency as:
f
f C = SW
20
TJ = TC + (PT x θJC)
where, θJC is the junction-to-case thermal impedance of
the package equal to +2°C/W. Solder the exposed pad of
the package to a large copper area to minimize the caseto-ambient thermal impedance. Measure the temperature
of the copper area near the device at a worst-case condition of power dissipation and use +2°C/W as θJC thermal
impedance. The case-to-ambient thermal impedance
(θC-A) is dependent on how well the heat is transferred
from the PC board to the ambient. Use a large copper
area to keep the PC board temperature low. The θC-A is
usually in the +20°C/W to +40°C/W range .
If the fZERO,ESR is lower than fC and close to fLC, use
a Type II compensation network where RFCF provides
a midband zero fmid,zero, and RFCCF provides a highfrequency pole.
3) Calculate modulator gain GM at the croser frequency.
VOUT
R1
Compensation
The MAX5073 provides an internal transconductance
amplifier with its inverting input and its output available to
the user for external frequency compensation. The flexibility of external compensation for each converter offers
wide selection of output filtering components, especially
the output capacitor. For cost-sensitive applications, use
high-ESR aluminum electrolytic capacitors; for component size-sensitive applications, use low-ESR tantalum
www.maximintegrated.com
-
COMP
gM
R2
VREF
+
RF
CF
CCF
Figure 6. Type II Compensation Network
Maxim Integrated │ 19
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
VIN
ESR
0.8
×
×
GM =
VOSC ESR + (2π× f C ×L OUT ) VOUT
VOUT
CCF
where VOSC is a peak-to-peak ramp amplitude equal to
1V.
RI
The transconductance error amplifier gain is:
CI
-
G E/A
= g m ×R F
R2
VREF
The total loop gain at fC sho be equal to 1
G M × G E/A =
1
or
CF
RF
R1
COMP
gM
+
Figure 7. Type III Compensation Network
where:
RF =
VOSC (ESR + 2π× f C ×L OUT )VOUT
CF =
0.8 × VIN × g m ×ESR
4) Place a zero at or below the LC double pole:
CF =
1
2π×R F × f LC
5) Place a high-frequency pole at fP = 0.5 x fSW.
1
2π× 0.75 ×f LC ×R F
and RF ≥ 10kΩ.
4) Calculate CI for a target unity crossoverequency, fC:
CI =
2π× f C × L OUT × C OUT × VOSC
VIN ×R F
Procedure 2 (see Figure 7)
If the output capacitor used is a low-ESR ceramic type,
the ESR frequency is usually far away from the targeted
unity crossover frequency (fC). In this case, Type III
compensation is recommended. Type III compensation
provides two-pole zero pairs. The locations of the zero
and poles should be such that the phase marginaks at fC.
f C fP
= = 5
f Z fC
The
is a good number to get about 60° phase
margin at fC. However, it is important to place the two
zeros at or below the double pole to avoid the conditional
stability issue.
5) Place a pole
(f P1 =
RI =
2) Calculate the LC double-pole frequency, fLC:
f LC =
1
2π× L OUT × C OUT
at fZERO,ESR.
1
2π× f ZERO,ESR × C I
6) Place a second zero, fZ2, at 0.2 x fC or at fLC, whichever is lower.
=
R1
1) Select a crossover frequency:
f
f C ≤ SW
20
1
)
2π×R I × C I
1
−R I
2π× f Z2 × C I
7) Placece a second pole
swiing frequency.
C CF =
(f P2 =
1
)
2π×R F × C CF
at 1/2 the
CF
(2π× 0.5 × f SW ×R F × C F ) −1
3) Place a zero
=
f
Z
1
at 0.75 × f LC
2π×R F × C F
www.maximintegrated.com
Maxim Integrated │ 20
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
OUTPUT2
PGND
PGOOD2
OUTPUT1
PGOOD1
SGND
OUTPUT1
3.3V/2A
VL
28 27 26 25 24 23 22
SOURCE2 PGND SGND SOURCE1PGOOD2
PGOOD1 21
1 CLKOUT
SGND
2 BST2/VDD2
BST1/VDD1 20
EP
CLOCK
OUT
OUTPUT2
12V/0.2A
4 DRAIN2
5 EN2
INPUT
DRAIN1 19
3 DRAIN2
ON
OFF
VL
DRAIN1 18
MAX5073
FB1 16
6 FB2
COMP1 15
7 COMP2
SYNC N.C. OSC V+
8
9
10 11
ON
OFF
EN1 17
VL BYPASS
13 14
VL
12
SYSTEM
CLOCK
INPUT
*CONNECT PGND AND SGND TOGETHER AT ONE POINT NEAR
THE RETURN TERMINALS OF THE V+ AND VL BYPASS CAPACITORS.
Figure 8. Buck-Boost Application
Boost Converter Compensation
where:
The boost converter compensation gets complicated due
to the presence of a right-half-plane zero fZERO,RHP. The
right-half-plane zero causes a drop in-phase while adding positive (+1) slope to the gain curve. It is important
to drop the gain significantly below unity before the RHP
frequency. Use the following procedure to calculate the
compensation components.
D = 1−
R (MIN) =
VOUT
I OUT(MAX)
Target the unity-gain crossovfrequency for:
1) Calculate the LC double-pole frequency, FLC, and the
right half plane zero frequency.
f LC =
VIN
VOUT
fC ≤
f ZERO,RHP
5
1− D
2π× L OUTC OUT
f ZERO,RHP =
(1− D) 2 R
(MIN)
2π×L OUT
(f Z1 =
2) Place a zero
CF =
1
2π×R F × C F
)
at 0.75 x fLC.
1
2π× 0.75 × f LC ×R F
where RF ≥ 10kΩ.
www.maximintegrated.com
Maxim Integrated │ 21
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
3) Calculate CI for a target crossoverequency, fC:
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. This is especially
true for dual converters where one channel can affect
the other. Refer to the MAX5073 EV kit data sheet for a
specific layout example. Use a multilayer board whenever
possible for better noise immunity. Follow these guidelines for good PC board layout:
2
VOSC (1 − D) + ω C 2L OC O 


CI =
ω CR F VIN
where ωC = 2π fC
4) Place a pole
(f P1 =
RI =
1
)
2π×R I × C I
2π × f ZERO,R HP × C I
5) Place the second zero
=
R1
1
)
2π×R1× C I
1
2π× f LC × C I
6) Place the second pole
swhing frequency.
C CF =
at fZERO,RHP.
1
(f Z2 =
(f P2 =
at fLC.
at 1/2 the
CF
(2π× 0.5 × f SW ×R F × C F) − 1
In applications where the MAX5073 are subject to noisy
environments, adjust the controller’s compensation to
improve the system’s noise immunity. In particular, highfrequency noise coupled into the feedback loop causes
jittery duty cycles. One solution is to lower the crossover
frequency (see the Compensation section).
www.maximintegrated.com
1) For SGND, use a large copper plane under the IC and
solder it to the exposed paddle. To effectively use this
copper area as a heat exchanger between the PC
board and ambient, expose this copper area on the
top and bottom side of the PC board. Do not make a
direct connection from the exposed pad copper plane
to SGND (pin 25) underneath the IC.
2) Isolate the power components and high-current path
from the sensitive analog circuitry.
3)Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation.
−R I
1
)
2π×R F × C CF
Improving Noise Immunity
PC Board Layout Guidelines
4) Connect SGND and PGND together close to the IC at
the ground terminals of VL and V+ bypass capacitors.
Do not connect them together anywhere else.
5)Keep the power traces and load connections short.
This practice is essential for high efficiency. Use thick
copper PC boards (2oz vs. 1oz) to enhance full-load
efficiency.
6) Ensure that the feedback connection to COUT is short
and direct.
7)Route high-speed switching nodes (BST_/VDD_,
SOURCE_) away from the sensitive analog areas
(BYPASS, COMP_, and FB_). Use the internal PC
board layer for SGND as EMI shields to keep radiated
noise away from the IC, feedback dividers, and analog
bypass capacitors.
Maxim Integrated │ 22
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Layout Procedure
1) Place the power components first, with ground terminals adjacent (inductor, CIN_, and COUT_). Make all
these connections on the top layer with wide, copperfilled areas (2oz copper recommended).
2)Group the gate-drive components (bootstrap diodes
and capacitors, and VL bypass capacitor) together
near the controller IC.
3) Make the DC-DC controller ground connections as
follows:
Ordering Information (continued)
PACKAGE
CODE
MAX5073ETI -40°C to +125°C
28 Thin QFN-EP*
(5mm x 5mm)
T2855-6
MAX5073ETI+ -40°C to +125°C
28 Thin QFN-EP*
(5mm x 5mm)
T2855-6
TEMP RANGE
b) Connect this plane to SGND and use this plane for
the ground connection for the reference (BYPASS),
enable, compensation components, feedback dividers, and OSC resistor.
c) Connect SGND and PGND together near the input
bypass capacitors and the IC (this is the only connection between SGND and PGND).
Chip Information
PINPACKAGE
PART
a) Create a small-signal ground plane underneath the
IC.
TRANSISTOR COUNT: 5994
PROCESS: BiCMOS
*EP = Exposed pad.
+Denotes lead-free package.
www.maximintegrated.com
Maxim Integrated │ 23
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
REVISION HISTORY
REVISION
NUMBER
REVISION
DATE
5
5/14
PAGES
CHANGED
DESCRIPTION
Removed automotive reference under Applications section on Page 1
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2014 Maxim Integrated Products, Inc. │ 24
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