(OTG) USB device interface. It covers the featur

(OTG) USB device interface. It covers the featur
Hello, and welcome to this presentation of the
STM32L4’s full-speed on-the-go (OTG) USB device
interface. It covers the features of this IP, which is widely
used to connect either a PC or a USB device to the
This slide explains the range of USB interfaces within the
STM32L4 product line.
As shown, this presentation describes the full-speed onthe-go (OTG) USB device interface supported in
STM32L49x/4Ax and STM32L47x/48x devices.
All devices with the FS OTG USB device interface can
operate with a low frequency crystal oscillator.
STM32L496/4A6 devices also allow a USB device to be
implemented without a crystal oscillator.
This figure shows the simplest connections between an
STM32L4 microcontroller and a USB connector in a
peripheral configuration.
The STM32L4 features a full-speed USB communication
interface allowing the microcontroller to communicate
typically with a PC or a USB storage device. The
simplest implementation is a USB peripheral device, but
the STM32L4 also supports “On-The-Go” USB functions.
The USB implementation includes low-power features
allowing the use of a low-speed crystal oscillator, OnThe-Go host or device functions, and a battery charger
detection allowing more efficient charging possibilities.
This slide summarizes the key features of this full-speed
OTG USB device interface, which is a USB specification
2.0 compliant interface operating at a bit rate of 12
Megabits per second.
In the simplest form, a full-speed USB device can be
Low frequency crystal operation is possible, and
STM32L496/4A6 devices can work crystal-less.
Its built-in support for Link Power Management adds
enhanced power modes on top of the USB 2.0
In addition, the On-The-Go or “OTG” function enables
the implementation of an OTG product or an embedded
host, both of which have the capacity to behave as a
targeted host.
The battery charger detection feature allows for
increased current up to 1.5 A to be drawn from BC1.2
compliant chargers.
In this block diagram, the full-speed OTG USB controller
core is shown in the center with its data FIFOs below.
The Physical Layer, or PHY, on its right side handles the
analog signal levels including many specific level
detections relating to OTG and battery charger detection
functions. The USB interrupt goes to the Cortex
processor to signal various USB events. The AHB
peripheral bus enables read/write access of the
controller registers and the Power & Clock control block.
Several related peripherals work in conjunction with the
USB device controller to link the USB activity to the
system power mode and software requirements.
The clock recovery system allows operation without an
external crystal oscillator, using the integrated HSI
oscillator as the main clock source.
The interrupt events are sent to the non-vectored
interrupt controller via a single line.
The system events can cause the system to wake up
from Stop mode, for example at the moment we resume
from USB Suspend mode.
At any given time, one of the two operating modes will be
in operation:
- Peripheral mode, used for a regular device or an OTG
- Targeted host mode, used for an embedded host or an
OTG device.
Interrupts from this USB block can be triggered by a large
number of events or state changes.
This slide and the following three slides show all the events
that can trigger an interrupt. As can be seen, these interrupt
sources are diverse; they range from events related to low
power management and OTG, to events related to normal
host behavior and regular USB reset and disconnect events.
Note in slide: Reset detected: In Device mode, this
interrupt is asserted when a reset is detected on the USB
in partial power-down mode when the device is in
Suspend mode.
In this second slide showing interrupts, another diverse
set of sources is described.
In this third slide describing interrupt sources, many
Suspend, OTG functions and FIFO status events are
listed as well as a general register access error.
The USB peripheral is fully active in Run mode. After a
Suspend event, Sleep mode and Stop 0 and 1 modes
are available and the contents of its registers are kept.
Stop 2 and Standby modes should not be used.
Within the USB module, dedicated bits are implemented
to provide debug functions for USB applications.
They relate to FIFO status and contents and the
scheduling of periodic queues in Host mode.
Additional details of these debug bits are listed in this
Here is an application example of a low-power device.
Power is drawn directly from the USB VBUS signal.
A single low-speed crystal oscillator at 32.768 kHz is
needed outside. A scheme is implemented inside the
microcontroller using this low-speed crystal oscillator to
trim the internal 48 MHz oscillator, thus giving the
required frequency accuracy to comply with the USB
Here is a second application example showing a batterypowered OTG solution.
The STM32L4 controls a power switch supplying VBUS
to the receptacle, and monitors for faults on the supply.
In this example, a regular crystal oscillator should be
Should dead battery support be required, VBUS should
be connected to the STM32L4 via a resistor divider.
For complete USB specification documents, please refer to
The USB2.0 document home page has a ZIP file containing
the USB2.0 and OTG2.0 specifications and an ECN for LPM
The USB device class documents page has the battery
charger specification.
Additional information can also be found in these
applications notes.
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