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Rev 0p8; 4/13/2012
MAXIM CONFIDENTIAL
Ultra Low Power Stereo Audio Codec
_____________________ FEATURES
The MAX98090 is a fully integrated audio codec
whose high performance, ultra low power
consumption and small footprint make it ideal for
portable applications.



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
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Stereo Class D speaker amplifiers provide efficient
amplification. Low radiated emissions enable
completely filterless operation.
102dB DR Stereo DAC (8kHz < Fs < 96kHz)
< 4 mW Playback Power Consumption
95dB DR Stereo ADC (8kHz < Fs < 96kHz)
< 4.5 mW Record Playback Power Consumption
Stereo Low EMI Class D Amplifier, 950mW /
Channel (8Ω , SPK_VDD = 4.2V)
Stereo Ground Referenced Class H Headphone
Amplifier
Differential Earpiece Amplifier / Stereo Line
Output
3 Stereo Single-Ended / Mono Differential Inputs
(WLP version)
FLEXSOUNDTM Technology Signal Processing
o 7-Band Parametric EQ
o ALC
I2S / LJ / RJ / TDM Digital Audio Interface
Supports Master Clock Frequencies from
256 x Fs to 60MHz
RF Immune Analog Inputs and Outputs
Extensive Click-and-Pop Reduction Circuitry
I2C Programmable Control Interface
Jack Detection
49-Bump 0.4mm WLP and 40-Pin TQFN
MAX98090
__________ GENERAL DESCRIPTION

The Class H headphone amplifiers provide a
ground referenced output eliminating the need for
large DC blocking capacitors. Class H operation
power by a 1.8V supply ensures low power
consumption and high efficiency. Also included is a
differential receiver (earpiece) amplifier that can
reconfigured as stereo line outputs.

The MAX98090 features a highly flexible input
scheme that includes six analog input pins that can
be configured as microphone inputs or single
ended line or differential inputs.


The digital audio interface can accept standard
PCM formats such as I2S, left-justified, rightjustified, and TDM as well as supporting sample
rates from 8-96 kHz.
The integrated FLEXSOUNDTM digital signal
processing includes an Automatic level control and
a seven band equalizer that can improve
loudspeaker performance by optimizing the
frequency response.







________ ORDERING INFORMATION
PART
MAX98090AEWJ+T
MAX98090AETL+T
MAX98090BEWJ+T
MAX98090BETL+T
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
49 - WLP
40 - TQFN
49 - WLP
40 - TQFN
M
__________________________________________ SIMPLIFIED BLOCK DIAGRAM
___________________________________________________ Maxim Integrated Products 1
Rev 0p8; 4/13/2012
MAXIM CONFIDENTIAL
_________________________________________________ TABLE OF CONTENTS
General Description .............................................................................................................................................. 1 Features.................................................................................................................................................................. 1 Simplified Block Diagram ..................................................................................................................................... 1 Table of Contents .................................................................................................................................................. 2 Functional Diagram ............................................................................................................................................... 4 AX P
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Absolute Maximum Ratings ................................................................................................................................. 5 MAX98090
Ordering Information ............................................................................................................................................ 1 Package Thermal Characteristics ........................................................................................................................ 5 Electrical Characteristics ..................................................................................................................................... 6 Digital Input/Output Characteristics .................................................................................................................. 14 Input Clock Characteristics ................................................................................................................................ 15 Digital Audio Interface Timing Characteristics ................................................................................................ 16 I2C Timing Characteristics .................................................................................................................................. 20 Digital Microphone Timing Characteristics ...................................................................................................... 21 Power Consumption ........................................................................................................................................... 22 Typical Operating Characteristics ..................................................................................................................... 22 Bump Configuration (WLP) ................................................................................................................................ 58 Pin Configuration (TQFN) ................................................................................................................................... 59 Pin / Bump Description ....................................................................................................................................... 60 M
Detailed Description............................................................................................................................................ 62 Device I2C Register Map ................................................................................................................................... 63 Power and Performance Management ............................................................................................................. 69 Device Performance Configuration............................................................................................................... 69 Device Enable Configuration ........................................................................................................................ 70 Analog Audio Input Configuration ..................................................................................................................... 72 Analog Microphone Inputs ............................................................................................................................ 73 Analog Microphone Bias .......................................................................................................................... 75 Digital Microphone Inputs ............................................................................................................................. 75 Analog Line Inputs ........................................................................................................................................ 77 Analog Full-Scale Direct to ADC Mixer Inputs .............................................................................................. 79 Analog Input to Analog Output Loopback ..................................................................................................... 79 Analog to Digital Converter (ADC) Configuration ............................................................................................. 80 ADC Input Mixer Configuration ..................................................................................................................... 80 ADC Output Digital Gain ............................................................................................................................... 81 ADC Output Sidetone ................................................................................................................................... 82 ADC Output Biquad Filter ............................................................................................................................. 83 Digital Audio Interface (DAI) Configuration ....................................................................................................... 84 Digital Data Path ........................................................................................................................................... 84 Digital Filtering .............................................................................................................................................. 85 DAI Clock Control ......................................................................................................................................... 86 Slave Mode .............................................................................................................................................. 87 Master Mode ............................................................................................................................................ 87 Clock Configuration .................................................................................................................................. 88 Frequency Ratio ....................................................................................................................................... 89 DAI TDM Mode ............................................................................................................................................. 91 Digital to Analog Converter (DAC) Configuration ......................................................................................... 92 DAC Input Digital Level ................................................................................................................................ 92 ___________________________________________________ Maxim Integrated Products 2
MAXIM CONFIDENTIAL
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MAX98090
Voice Gain ................................................................................................................................................ 92 Playback Level ......................................................................................................................................... 92 Automatic Level Control ............................................................................................................................... 92 DAC Input Parametric Equalizer................................................................................................................... 94 Analog Audio Output Configuration .................................................................................................................. 96 Analog Receiver (Earpiece) Output .............................................................................................................. 97 Receiver Gain Control .............................................................................................................................. 98 Receiver Output Mixer.............................................................................................................................. 98 Analog Speaker Output ................................................................................................................................ 99 Speaker Class-D Output Amplifier ......................................................................................................... 100 Speaker Gain Control ............................................................................................................................. 100 Speaker Output Mixer ............................................................................................................................ 101 Analog Headphone Output ......................................................................................................................... 102 DirectDrive Headphone Amplifier ........................................................................................................... 105 Class H Operation .................................................................................................................................. 105 Charge Pump ......................................................................................................................................... 105 Headphone Gain Control........................................................................................................................ 105 Headphone Ground Sense .................................................................................................................... 105 Headphone Output Mixer ....................................................................................................................... 105 Analog Line Outputs ................................................................................................................................... 106 Line Output Gain Control........................................................................................................................ 108 Line Output Mixer ................................................................................................................................... 108 Click-and-Pop Reduction ................................................................................................................................ 109 Jack Detection ................................................................................................................................................ 110 Jack Insertion and Removal ....................................................................................................................... 110 Accessory Button Detection ....................................................................................................................... 110 Device Status Flags ........................................................................................................................................ 112 Status Flag Masking ................................................................................................................................... 113 Quick Setup Configuration .............................................................................................................................. 114 Software Reset ............................................................................................................................................... 116 Device Revision Identification ......................................................................................................................... 117 I2C Serial Interface .......................................................................................................................................... 117 Bit Transfer ................................................................................................................................................. 117 START and STOP Conditions .................................................................................................................... 117 Early STOP Conditions ............................................................................................................................... 117 Slave Address............................................................................................................................................. 117 Acknowledge .............................................................................................................................................. 118 Write Data Format ...................................................................................................................................... 118 Read Data Format ...................................................................................................................................... 119 M
Applications Information .................................................................................................................................. 121 Typical Application Circuits ............................................................................................................................. 121 Startup / Shutdown Register Sequencing ....................................................................................................... 122 Component Selection...................................................................................................................................... 123 AC Coupling Capacitors ............................................................................................................................. 123 Charge-Pump Capacitor Selection ............................................................................................................. 124 Filterless Class D Speaker Operation............................................................................................................. 124 EMI Considerations and Optional Ferrite Bead Filter ................................................................................. 124 RF Susceptibility ............................................................................................................................................. 125 Supply Bypassing, Layout, and Grounding..................................................................................................... 125 Recommended PCB Routing .......................................................................................................................... 126 Unused Pins .................................................................................................................................................... 126 WLP Applications Information ......................................................................................................................... 126 Package Information ......................................................................................................................................... 127 Revision History ................................................................................................................................................ 130 _____________________________________________________________________ 3
MAXIM CONFIDENTIAL
37 (E2)
34 (F4)
/IRQ\
36 (D3)
SCL
SDA
28 (F6)
DVDDIO
32 (F5)
LRCLK
30 (E5)
33 (G5)
BCLK
I2C
HIZOFF
SDOEN
MICCLK
SDIN
31 (G6)
SDOUT
27 (F7)
DVDD
35 (G4)
AVDD
MCLK
26 (E7)
24 (E6)
REF
VCM
CLOCK
CONTROL
BIAS
VCM_MODE
MAX98090
23 (D6)
_______________________________________________ FUNCTIONAL DIAGRAM
MAS
MAS
BIT
CLOCK
FRAME
CLOCK
SDIEN
DATA
INPUT
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DATA
OUTPUT
LBEN
LTEN
MIXING
AVL
AVLG
JACKSNS
JACK
DETECTION
DV1G
JDETEN
JDWK
JDEB
SIDETONE
HPF
ADC_B_
ADCBQEN
MICBIAS
HPF
DVST
SINGLE
BAND EQ
AVBQ
MBEN
/EQCLP
DIGITAL FILTERING
DIGMICL
ADLEN
ADCHP
OSR128
ADREN
DACLEN
MODE
DACHP
PERFMODE
MIXADR
LINMOD
MIXRCVR
MIXRCVRGAIN
MIXSPLGAIN
MIXSPL
SPVOLL
6dB
MIX
SPKLGND
SPKRVDD
SPKRP
SPKRN
6dB
SPKRGND
SPRM
SPREN
MIXHPLGAIN
MIXHPL
MIXHPLSEL
(B3,B4)
14
16 (A4)
15 (A5)
17 (A6)
13
12 (A3)
11 (A2)
10 (A1)
HPLEN
HPLM
HPVOLL
MIX
MAX98090
9 (B1)
SPKVDD
SPKLVDD
SPKLP
SPKLN
SPLEN
SPLM
DACREN
SPVOLR
MIXSPR
MIXSPRGAIN
MIXGAIN2_4_6
IN5_6_DIFF
IN6_SE_EN EXTBUF_B
IN4_SE_EN LINE_B_EN
IN2_SE_EN LINBPGA
RCVN /
LOUTR
RCVRVOL
RCVRM
RCVREN
+14dB to -48dB
IN5
IN6
8 (C1)
+8dB to -62dB
+14dB to -48dB
MIXADL
RCVP /
LOUTL
+8dB to -62dB
ALCATK
ALCRLS
ALCCMP
ALCTHC
MIX
ADC L MIXER
MIX
IN1_SE_EN LINAPGA
IN3_SE_EN LINE_A_EN
IN5_SE_EN EXTBUF_A
IN3_4_DIFF
MIXGAIN1_3_5
MIXADL
DAC L
PGAM1
20 / 14 / 3 /
0 / -3 / -6dB
MIX
HPL
4 (E1)
MIXADR
20 / 14 / 3 /
0 / -3 / -6dB
IN4
IN3
EXTMIC
PA2EN
PGAM2
0 / 20 / 30dB
+20dB to 0dB
+3dB to -67dB
HPS
5 (D2)
+3dB to -67dB
MIX
ADC R MIXER
21 (C6)
20 (B6)
ALC
EQ3BANDEN
EQ5BANDEN
EQ7BANDEN
DIGITAL FILTERING
ADC R
EXTMIC PA1EN
ALCEN
ALCEXP
ALCTHE
ALCG
+20dB to 0dB
ADC L
IN1 / DMD1
IN2 / DMC1
DIGMICR
SEVEN
BAND
EQ
RCVLEN
RCVLM
RCVLVOL
MIX
0 / 20 / 30dB
(C4)
(D4)
MIXRCVLGAIN
MIXRCVL
DVEQ
MODE
19 (A7)
18 (B7)
DHPF
DV1
DV1M
FLEXSOUNDTM
TECHNOLOGY
MIX
22 (C7)
DSTS
AHPF
DAC R
7 (B5)
DMONO
+
AVR
AVRG
HPR
MIXHPRSEL
MIXHPR
MIXHPRGAIN
6 (D1)
HPVOLR
HPRM
HPREN
CHARGE PUMP
38 (G3)
1 (G1)
CPVSS
C1N
C1P
3 (F1)
2 (G2)
40 (F2)
39 (F3)
29 (G7)
25 (D7)
CPVDD
DGND
AGND
M
HPVDD
HPGND
_____________________________________________________________________ 4
MAXIM CONFIDENTIAL
________________________________________ ABSOLUTE MAXIMUM RATINGS
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HPSNS .................................. (HPGND - 0.3V) to (HPGND+0.3V)
HPL, HPR .............................. (HPVSS - 0.3V) to (HPVDD+0.3V)
RCVP, RCVN ................ (SPKLGND - 0.3V) to (SPKLVDD+0.3V)
SPKLP, SPKLN ............. (SPKLGND - 0.3V) to (SPKLVDD+0.3V)
SPKRP, SPKRN ........... (SPKRGND - 0.3V) to (SPKRVDD+0.3V)
JACKSNS ............................................................... -0.3V to +6.0V
Continuous Power Dissipation (TA=+70ºC)
49-Bump WLP (derate 23.8mW/ºC above +70ºC) .......... TBDW
40-Pin TQFN (derate 35.7mW/ºC above +70ºC) ............ 2.86W
Operating Temp Range ............................................ -40C to +85C
Storage Temp Range ............................................. -65C to +150C
MAX98090
(Voltages with respect to AGND)
AVDD, CPVDD, HPVDD ........................................ -0.3V to +2.2V
SPKLVDD, SPKRVDD, DVDDIO............................-0.3V to +6.0V
DGND, HPGND, SPKLGND, SPKRGND ............... -0.1V to +0.1V
CPVSS ............................... (HPGND – 2.2V) to (HPGND + 0.3V)
C1N ...................................... (HPVSS - 0.3V) to (HPGND + 0.3V)
C1P....................................... (HPGND - 0.3V) to (HPVDD + 0.3V)
MICBIAS ............................................. -0.3V to (SPKLVDD+0.3V)
REF, VCM …….………………………….…-0.3V to (AVDD+0.3V)
MCLK, SDIN, SDA, SCL, /IRQ\ .............................. -0.3V to +6.0V
LRCLK, BCLK, SDOUT .......................... -0.3V to (DVDDIO+0.3V)
IN1, IN2, IN3, IN4, IN5, IN6…………………………-0.3V to +2.2V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
________________________________ PACKAGE THERMAL CHARACTERISTICS
49-Bump WLP
Junction-to-Ambient Thermal Resistance (θJA) ............ 42ºC/W
Junction-to-Case Thermal Resistance (θJC) .................... 1ºC/W
40-Pin TQFN
Junction-to-Ambient Thermal Resistance (θJA) ............ 28ºC/W
Junction-to-Case Thermal Resistance (θJC) .................... 2ºC/W
M
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, see www.maxim-ic.com/thermal-tutorial.
_____________________________________________________________________ 5
MAXIM Confidential
MAX98090
_____________________________________ ELECTRICAL CHARACTERISTICS
(VAVDD = VHPVDD = VDVDDIO = +1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RREC) connected between RECP/LOUTL and RECN/LOUTR
(LINMOD=0). Line Output loads (RLOUT) connected between from RECP/LOUTL and RECN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or
HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RREC = ∞, RLOUT = ∞, RHP = ∞, ZSPK = ∞. CREF = 2.2μF, CVCM = CMICBIAS = 1μF, CC1N-C1P =
CCPVDD = CCPVSS = 1μF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL = AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_REC = AV_LOUT, AV_HP = AV_SPK
= 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS = 0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
Guaranteed by PSRR (Note 12)
2.8
3.7
5.5
1.65
1.8
2
VDVDD
1.08
1.2
1.98
VDVDDIO
1.65
1.8
3.6
V
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Supply Voltage Range
VSPKLVDD, VSPKRVDD
VAVDD, VHPVDD
Full Duplex 8kHz Mono,
Receiver Output
Total Supply Current (Note 2)
IVDD
DAC Playback 48kHz Stereo,
Headphone Outputs
DAC Playback 48kHz Stereo,
Speaker Outputs
Analog
1.97
3.5
Speaker
0.70
2
Digital
0.71
1.2
Analog
1.45
2
Speaker
0
0.005
Digital
0.79
1.2
Analog
0.91
2
Speaker
2.21
3
Digital
0.80
1.2
REF Voltage
1.25
VCM Voltage
Shutdown Supply Current (Note 2)
VCM from Resistive Division (VCM_MODE = 0)
0.90
VCM from Bandgap (VCM_MODE = 1)
0.78
TA = +25ºC
V
V
Analog
1
10
Speaker
1
5
2.1
20
Digital
Shutdown to Full Operation
mA
μA
10
ms
97
dB
96
dB
DIFFERENTIAL INPUT (MICROPHONE) TO ADC PATH
Dynamic Range (Note 4)
DR
Total Harmonic Distortion + Noise
Common-Mode Rejection Ratio
THD+N
CMRR
AV_MICPRE_ = 0dB , fS = 48kHz, MODE = 1 (FIR Audio),
A-weighting filter applied.
AV_MICPRE_ = 0dB, fS = 8kHz, MODE = 0 (IIR Voice),
A-weighting filter applied.
AV_MICPRE = 20dB, VIN = 90mVRMS, f = 1kHz,
-82
AV_MICPRE = 0dB, VIN = 900mVRMS, f = 1kHz
-91
AV_MICPRE = 30dB, VIN = 28.5mVRMS, f = 1kHz
-73
f = 217Hz, VIN_CM = 100mVP-P
59
VAVDD = 1.65V to 2.0V, input referred
Power Supply Rejection Ratio (Note 12)
M
Path Phase Delay
Gain Error
PSRR
90
VRIPPLE = 100mVP-P, input referred,
AV_MIC = AV_ADC = 0dB
1kHz, 0dB input,
High pass filter disabled measured from
analog input to digital output
DC Accuracy
40
dB
dB
TBD
f = 217Hz
78
f = 1kHz
78
f = 10kHz
77
MODE = 0 (IIR Voice);
8kHz
MODE = 0 (IIR Voice);
16kHz
MODE = 1 (FIR Audio)
8kHz
MODE = 1 (FIR Audio)
48kHz
-75
dB
2.2
1.1
ms
4.5
0.8
1
5
%
_____________________________________________________________________ 6
MAXIM Confidential
MAX98090
(VAVDD = VHPVDD = VDVDDIO = +1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RREC) connected between RECP/LOUTL and RECN/LOUTR
(LINMOD=0). Line Output loads (RLOUT) connected between from RECP/LOUTL and RECN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or
HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RREC = ∞, RLOUT = ∞, RHP = ∞, ZSPK = ∞. CREF = 2.2μF, CVCM = CMICBIAS = 1μF, CC1N-C1P =
CCPVDD = CCPVSS = 1μF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL = AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_REC = AV_LOUT, AV_HP = AV_SPK
= 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS = 0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIFFERENTIAL (MICROPHONE) PREAMP & PGA
Full Scale Input
AV_MICPRE_ = 0dB
1
PA_EN[1:0] = 01
AV_MICPRE_
Note 5
PA_EN[1:0] = 10
19.5
20
20.5
PA_EN[1:0] = 11
29.5
30
30.5
PGAM_[4:0] = 0x00
19.5
20
20.5
dB
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Microphone Pre-Amplifier Gain
VRMS
0
Microphone Level Adjust Gain (PGA)
MIC Input Resistance
AV_MICPGA_
RIN_MIC
Note 5
PGAM_[4:0] = 0x14
All Gain Settings, measured at IN_ (measured single-ended).
0
30
50
dB
kΩ
MICROPHONE BIAS
MICBIAS Output Voltage
VMICBIAS
ILOAD = 1mA, MBVSEL[1:0] = 00
TBD
2.2
TBD
ILOAD = 1mA, MBVSEL[1:0] = 01
TBD
2.4
TBD
ILOAD = 1mA, MBVSEL[1:0] = 10
TBD
2.57
TBD
ILOAD = 1mA, MBVSEL[1:0] = 11
TBD
2.8
TBD
0.085
0.28
mV
VSPKLVDD = 2.8V to 5.5V, MBVSEL[1:0] = 00
9.7
96
μV
f = 217Hz, VRIPPLE (SPKLVDD) = 100mVP-P
70
f = 10kHz, VRIPPLE (SPKLVDD) = 100mVP-P
75
A-weighted, f = 20Hz – 20kHz
7.4
µVRMS
f = 1kHz
52.3
nV/√Hz
fS = 48kHz, fMCLK = 12.288MHz, MODE = 1 (FIR Audio)
98
dB
VIN = 0.222VRMS, f = 1kHz
-85
AV_LINEPGA = 0dB
0.5
Load Regulation
ILOAD = 1mA to 2mA, MBVSEL[1:0] = 00
Line Regulation
Ripple Rejection
Noise Voltage
V
dB
SINGLE-ENDED (LINE) INPUT TO ADC PATH
Dynamic Range (Note 4)
DR
Total Harmonic Distortion + Noise
THD+N
-80
dB
SINGLE ENDED (LINE) INPUT PGA
Full Scale Input
VIN
Line Input Level Adjust Gain (PGA)
Line Input Amplifier Gain
Input Resistance
Feedback Resistance
AV_LINEPGA
AV_LINEAMP
RIN
RIN_FB
AV_EXTERNAL = -6dB, EXTBUF = 1
Note 5
VRMS
1
PGALIN = 0x0
19
20
21
PGALIN = 0x1
13
14
15
PGALIN = 0x2
2
3
4
PGALIN = 0x3
-1
0
1
PGALIN = 0x4
-4
-3
-2
PGALIN = 0x5, 0x6, 0x7
-7
-6
-5
Single Ended Only
6
AV_LINEPGA = 0dB
14
20
TA = +25ºC
19
20
AVL/AVR = 0xF to 0x0 (Note 5)
-12
dB
dB
kΩ
21
kΩ
3
dB
ADC LEVEL CONTROL
ADC Level Adjust Range
AV_ADCLVL
ADC Level Adjust Step Size
M
ADC Gain Adjust Range
ADC Gain Adjust Step Size
1
AV_ADCGAIN
AVLG/AVRG = 0x0 to 0x3 (Note 5)
0
dB
18
6
dB
dB
_____________________________________________________________________ 7
MAXIM Confidential
MAX98090
(VAVDD = VHPVDD = VDVDDIO = +1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RREC) connected between RECP/LOUTL and RECN/LOUTR
(LINMOD=0). Line Output loads (RLOUT) connected between from RECP/LOUTL and RECN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or
HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RREC = ∞, RLOUT = ∞, RHP = ∞, ZSPK = ∞. CREF = 2.2μF, CVCM = CMICBIAS = 1μF, CC1N-C1P =
CCPVDD = CCPVSS = 1μF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL = AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_REC = AV_LOUT, AV_HP = AV_SPK
= 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS = 0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC DIGITAL FILTERS
VOICE MODE IIR LOWPASS FILTER (MODE = 0)
0.445
x fS
0.449
x fS
Ripple Limit Cutoff
Pass band Cutoff
fPLP
Hz
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TI
AL
-3dB Cutoff
Pass band Ripple
f < fPLP
Stop band Cutoff
-0.1
fSLP
Stop band Attenuation (Note 6)
f > fSLP
0.1
dB
0.47
x fS
Hz
74
dB
PROGRAMMALE BIQUAD FILTER
Pre-Attenuator Gain Range
-15
Pre-Attenuator Step Size
0
1
High Frequency Shelving Filter
Minimum Cutoff Frequency
Low Pass Filter
Low Frequency Shelving Filter
Peak Filter
Maximum Q
dB
0.0008
x fS
0.02
x fS
0.002
x fS
0.0008
x fS
0.0008
x fS
High Pass Filter
dB
Hz
Peak Filter
10
STEREO AUDIO MODE FIR LOWPASS FILTER (MODE = 1, DHF = 0, fLRCLK < 50kHz)
0.43
x fS
0.48
x fS
0.5
x fS
Ripple Limit Cutoff
Pass band Cutoff
fPLP
-3dB Cutoff
-6.02dB Cutoff
Pass band Ripple
f < fPLP
Stop band Cutoff
Hz
-0.1
fSLP
Stop band Attenuation (Note 6)
f < fSLP
0.1
dB
0.58
x fS
Hz
60
dB
0.208
x fS
0.28
x fS
Hz
ADC STEREO AUDIO MODE FIR LOWPASS FILTER (MODE = 1, DHF = 1, fLRCLK > 50kHz)
Ripple Limit Cutoff
Pass band Cutoff
fPLP
-3dB Cutoff
Pass band Ripple
f < fPLP
Stop band Cutoff
-0.1
fSLP
Stop band Attenuation
f < fSLP
0.1
dB
0.45
x fS
Hz
60
dB
ADC DC BLOCKING HIGHPASS FILTER
DC Attenuation
AV_ADCHPF
AHPF = 1
90
dB
M
ADC TO DAC DIGITAL SIDETONE (MODE = 0)
Sidetone Level Adjust Range
AV_STLVL
DVST = 0x1F to 0x01
-60.5
Sidetone Level Adjust Step Size
Sidetone Path Phase Delay
-0.5
2
1kHz, 0dB input, High pass filter disabled
8kHz
1.8
16kHz
0.9
dB
dB
ms
_____________________________________________________________________ 8
MAXIM Confidential
MAX98090
(VAVDD = VHPVDD = VDVDDIO = +1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RREC) connected between RECP/LOUTL and RECN/LOUTR
(LINMOD=0). Line Output loads (RLOUT) connected between from RECP/LOUTL and RECN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or
HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RREC = ∞, RLOUT = ∞, RHP = ∞, ZSPK = ∞. CREF = 2.2μF, CVCM = CMICBIAS = 1μF, CC1N-C1P =
CCPVDD = CCPVSS = 1μF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL = AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_REC = AV_LOUT, AV_HP = AV_SPK
= 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS = 0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC TO DAC DIGITAL LOOP-THROUGH PATH
Dynamic Range (Note 4)
DR
Total Harmonic Distortion + Noise
fS = 48kHz, fMCLK = 12.288MHz, MODE = 1 (FIR Audio)
97
THD+N
fIN = 1kHz, fS = 48kHz, fMCLK = 12.288MHz, MODE = 1 (FIR Audio)
-83
AV_DACLVL
DV1 = 0xF to 0x0 (Note 5)
dB
-75
dB
0
dB
DAC LEVEL CONTROL
-15
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
DAC Attenuation Range
DAC Attenuation Step Size
1
DAC Gain Adjust Range
AV_DACGAIN
DV1G = 00 to 11 (Note 5)
0
DAC Gain Adjust Step Size
dB
18
6
dB
dB
DAC DIGITAL FILTERS
VOICE MODE IIR LOWPASS FILTER (MODE = 0)
Pass band Cutoff
Ripple Limit Cutoff
0.448
x fS
-3dB Cutoff
0.451
x fS
fPLP
Pass band Ripple
f < fPLP
Stop band Cutoff
Hz
-0.1
fSLP
Stop band Attenuation (Note 6)
f > fSLP
0.1
dB
0.476
x fS
Hz
75
dB
STEREO AUDIO MODE FIR LOWPASS FILTER (MODE = 1, DHF = 0, fLRCLK < 50kHz)
Ripple Limit Cutoff
Pass band Cutoff
fPLP
-3dB Cutoff
-6.02dB Cutoff
Pass band Ripple
f < fPLP
Stop band Cutoff
0.43
x fS
0.47
x fS
0.5
x fS
Hz
-0.1
fSLP
Stop band Attenuation (Note 6)
f > fSLP
0.1
dB
0.58
x fS
Hz
60
dB
Ripple Limit Cutoff
0.24
x fS
Hz
-3dB Cutoff
0.31
x fS
f < fPLP
-0.1
STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF = 1 for fLRCLK > 50kHz)
fPLP
Pass band Cutoff
Pass band Ripple
Stop band Cutoff
fSLP
Stop band Attenuation (Note 6)
f < fSLP
0.1
dB
0.477
x fS
Hz
60
dB
DAC DC BLOCKING HIGHPASS FILTER
DC Attenuation
AV_DACHPF
DHPF = 1
89
dB
AUTOMATIC LEVEL CONTROL
M
Gain Range
Compression Threshold
Verify – EC table master states -35 but description doesn’t match
Expansion Threshold
Attack Time
Release Time
Discuss – EV-kit does not match Austin - faster
0
12
dB
-31
0
dBFS
-66
-35
dBFS
0.0005
0.2
s
0.0625
8
s
_____________________________________________________________________ 9
MAXIM Confidential
MAX98090
(VAVDD = VHPVDD = VDVDDIO = +1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RREC) connected between RECP/LOUTL and RECN/LOUTR
(LINMOD=0). Line Output loads (RLOUT) connected between from RECP/LOUTL and RECN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or
HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RREC = ∞, RLOUT = ∞, RHP = ∞, ZSPK = ∞. CREF = 2.2μF, CVCM = CMICBIAS = 1μF, CC1N-C1P =
CCPVDD = CCPVSS = 1μF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL = AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_REC = AV_LOUT, AV_HP = AV_SPK
= 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS = 0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
PARAMETRIC EQUALIZER
Number of Bands
Per Band Gain Range
-12
Pre-Attenuator Gain Range
-15
TYP
MAX
UNITS
12
Bands
dB
0
dB
7
Pre-Attenuator Step Size
1
dB
0.0008
x fS
0.02
x fS
0.002
x fS
0.0008
x fS
0.0008
x fS
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
High Pass Filter
High Frequency Shelving Filter
Minimum Cutoff Frequency
Low Pass Filter
Low Frequency Shelving Filter
Peak Filter
Maximum Q
Hz
Peak Filter
10
DAC TO RECEIVER AMPLIFIER PATH
Dynamic Range (Note 4)
DR
Total Harmonic Distortion + Noise
THD+N
fS = 48kHz, fMCLK = 12.288MHz
100
f = 1kHz, POUT = 20mW, RREC = 32Ω
-68
dB
-58
dB
ANALOG INPUT TO RECEIVER AMPLIFIER PATH
Dynamic Range (Note 4)
DR
Total Harmonic Distortion + Noise
93
THD+N
SPKLVDD = 2.8V to 5.5V
Power Supply Rejection Ratio (Note 12)
PSRR
VRIPPLE = 100mVP-P
72
96
dB
-71
dB
80
f = 217Hz
77
f = 1kHz
77
f = 10kHz
69
dB
RECEIVER AMPLIFIER (Note 7)
Output Power
POUT
Full Scale Output
RREC = 32Ω, f = 1kHz, THD < 1%, VCM_MODE = 0
97
RREC = 32Ω, f = 1kHz, THD < 1%, VCM_MODE = 1
74
AV_RECPGA = 0dB (Note 8)
Receiver Volume Control (PGA)
AV_RECPGA
Volume Control Step Size (Note 13)
Note 5 and Note 13
1
Output Offset Voltage
-63
-61
-59
RCVLVOL = 0x1F
+7.5
+8
+8.5
+8dB to +6dB
0.5
+6dB to +0dB
1
0dB to -14dB
2
-14dB to -38dB
3
Click and Pop Level
M
Capacitive Drive Capability
KCP
88
No sustained oscillations
dB
97
AV_REC = -62dB, TA = 25ºC
Peak Voltage, A-weighted, 32 samples
per second, AV_REC = 0dB
dB
4
f = 1kHz
VOS
VRMS
RCVLVOL = 0x00
-38dB to -62dB
Mute Attenuation
mW
dB
±1
Into shutdown
-67
Out of shutdown
-68
RL = 32Ω
RL = ∞
500
100
mV
dBV
pF
_____________________________________________________________________ 10
MAXIM Confidential
MAX98090
(VAVDD = VHPVDD = VDVDDIO = +1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RREC) connected between RECP/LOUTL and RECN/LOUTR
(LINMOD=0). Line Output loads (RLOUT) connected between from RECP/LOUTL and RECN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or
HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RREC = ∞, RLOUT = ∞, RHP = ∞, ZSPK = ∞. CREF = 2.2μF, CVCM = CMICBIAS = 1μF, CC1N-C1P =
CCPVDD = CCPVSS = 1μF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL = AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_REC = AV_LOUT, AV_HP = AV_SPK
= 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS = 0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC TO LINEOUT AMPLIFIER PATH
Dynamic Range (Note 4)
DR
Total Harmonic Distortion + Noise
THD+N
fS = 48kHz, fMCLK = 12.288MHz
100
f = 1kHz, RLOUT = 10KΩ (0.707VRMS Output Level)
-86
dB
-70
dB
ANALOG INPUT TO LINE OUT AMPLIFIER PATH
DR
98
dB
-86
dB
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
Dynamic Range (Note 4)
Total Harmonic Distortion + Noise
THD+N
f = 1kHz, RLOUT = 10KΩ (0.707VRMS Output Level)
VSPK_VDD = 2.8V to 5.5V
Power Supply Rejection Ratio (Note 12)
PSRR
VRIPPLE = 100mVP-P
60
74
74
74
73
f = 217Hz
f = 1kHz
f = 10kHz
dB
LINE OUT AMPLIFIER (Note 7)
Full Scale Output
AV_LOUT = 0dB (Note 8)
Line Output Amplifier Gain
0.707
AV_LOUTAMP
Line Output Volume Control (PGA)
AV_LOUTPGA
Volume Control Step Size (Note 13)
VRMS
-3
Note 5 and Note 13
-63
-61
-59
RCV_VOL = 0x1F
+7.5
+8
+8.5
+8dB to +6dB
0.5
+6dB to +0dB
1
0dB to -14dB
2
-14dB to -38dB
3
-38dB to -62dB
Mute Attenuation
f = 1kHz
Capacitive Drive Capability
No sustained oscillations
dB
RCV_VOL = 0x00
dB
dB
4
88
97
RLOUT = 1kΩ
500
RLOUT = ∞
100
dB
pF
DAC TO SPEAKER AMPLIFIER PATH
Dynamic Range (Note 4)
DR
AV_SPK = 0 dB
96
dB
f = 1kHz, POUT = 200mW, ZSPK = 8Ω + 68µH, fMCLK = 12.288MHz
-73
dB
Crosstalk
SPL to SPR and SPR to SPL, POUT = 640mW, f = 1kHz
-108
Output Noise
AV_SPK = 0dB
27
µVRMS
AV_MIC = 0dB AV_SPK = 0 dB (Output referenced to 2Vrms)
94
dB
f = 1kHz, POUT = 200mW, ZSPK = 8Ω + 8µH
-73
dB
28
µVRMS
Total Harmonic Distortion + Noise
THD+N
ANALOG INPUT TO SPEAKER AMPLIFIER PATH
Dynamic Range (Note 4)
DR
Total Harmonic Distortion + Noise
THD+N
Output Noise
VSPK_VDD= 2.8V to 5.5V
PSRR
VRIPPLE = 100mVP-P
80
68
f = 1kHz
67
f = 10kHz
61
dB
M
Power Supply Rejection Ratio (Note 12)
60
f = 217Hz
_____________________________________________________________________ 11
MAXIM Confidential
MAX98090
(VAVDD = VHPVDD = VDVDDIO = +1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RREC) connected between RECP/LOUTL and RECN/LOUTR
(LINMOD=0). Line Output loads (RLOUT) connected between from RECP/LOUTL and RECN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or
HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RREC = ∞, RLOUT = ∞, RHP = ∞, ZSPK = ∞. CREF = 2.2μF, CVCM = CMICBIAS = 1μF, CC1N-C1P =
CCPVDD = CCPVSS = 1μF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL = AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_REC = AV_LOUT, AV_HP = AV_SPK
= 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS = 0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SPEAKER AMPLIFIER (Note 7)
POUT
f = 1kHz, THD < 1%, ZSPK = 8Ω + 68µH
950
730
SPK_VDD = 3.3V
580
SPK_VDD = 3.0V
400
mW
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
Output Power
SPK_VDD = 4.2V
SPK_VDD = 3.7V
Full Scale Output
Speaker Output Amplifier Gain
AV_SPK = +6dB (Note 8)
AV_SPKAMP
Speaker Volume Control (PGA)
AV_SPKPGA
Note 5 and Note 13
2
+6
SPVOL_ = 0x00
-50
-48
-46
SPVOL_ = 0x1F
+13.5
+14
+14.5
Mute Attenuation
Output Offset Voltage
VOS
Click and Pop Level
+9dB to -6dB
1
-6dB to -14dB
2
-14dB to -32dB
3
-32dB to -48dB
4
f = 1kHz
84
AV_SPKPGA = -62dB
KCP
Peak Voltage, A-weighted, 32
samples per second, AV_SPK = 0dB
DR
fS = 48kHz, fMCLK = 12.288MHz
dB
0.5
+14dB to +9dB
Volume Control Step Size (Note 13)
VRMS
dB
±0.5
Into shutdown
-65
Out of shutdown
-65
dB
dB
±3
mV
dBV
DAC TO HEADPHONE AMPLIFIER PATH
Dynamic Range (Note 4)
Total Harmonic Distortion + Noise
THD+N
Crosstalk
f = 1kHz, POUT = 10mW
Master or Slave Mode
Slave Mode
RHP = 16Ω
-88
RHP = 32Ω
-86
PSRR
-80
dB
-88
f = 1kHz, VIN = -1dBFS, RHP = 10kΩ
TBD
dB
HPL to HPR and HPR to HPL, POUT = 5mW, f = 1kHz, RHP = 32Ω
TBD
dB
VRIPPLE = 100mVP-P,
AV_HP = 0dB
70
85
f = 217Hz
79
f = 1kHz
79
f = 10kHz
74
MODE = 0 (IIR Voice); 8kHz
DAC Path Phase Delay
dB
f = 1kHz, VOUT = 1VRMS, RHP = 10kΩ
VAVDD = VHPVDD = 1.65V to 2.0V
Power Supply Rejection Ratio (Note 12)
102
96
dB
2.2
1kHz, 0dB input, High pass filter
MODE = 0 (IIR Voice); 16kHz
disabled measured from digital input
MODE = 1 (FIR Audio) 8kHz
to analog output
1.1
MODE = 1 (FIR Audio) 48kHz
0.76
ms
2.5
1
Channel Gain Mismatch
1
5
%
%
M
Gain Error
_____________________________________________________________________ 12
MAXIM Confidential
MAX98090
(VAVDD = VHPVDD = VDVDDIO = +1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RREC) connected between RECP/LOUTL and RECN/LOUTR
(LINMOD=0). Line Output loads (RLOUT) connected between from RECP/LOUTL and RECN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or
HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RREC = ∞, RLOUT = ∞, RHP = ∞, ZSPK = ∞. CREF = 2.2μF, CVCM = CMICBIAS = 1μF, CC1N-C1P =
CCPVDD = CCPVSS = 1μF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL = AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_REC = AV_LOUT, AV_HP = AV_SPK
= 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS = 0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT TO HEADPHONE AMPLIFIER PATH
Dynamic Range (Note 4)
Total Harmonic Distortion + Noise
THD+N
AV_LINE = 0dB AV_HPPGA= 0 dB
101
VIN = 250mVRMS, f =1kHz
-80
VAVDD = VHPVDD = 1.65V to 2.0V
PSRR
60
f = 217Hz
61
f = 1kHz
61
f = 10kHz
60
dB
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
Power Supply Rejection Ratio (Note 12)
40
dB
VRIPPLE = 100mVP-P,
AV_TOTAL = 0dB
HEADPHONE AMPLIFIER (Note 7)
Output Power
POUT
Total Harmonic Distortion + Noise
THD +N
Full Scale Output
f = 1kHz, THD < 1%
RL = 16Ω
20
RL = 32Ω
RHP = 16Ω, POUT = 10mW, f = 1kHz
-88
RHP = 10kΩ, VOUT = 1Vrms, f = 1kHz
-88
AV_HPPGA
Volume Control Step Size (Note 13)
1
-67
-65
HPVOL_ = 0x1F
2.5
3
3.5
+3dB to +1dB
0.5
+1dB to -5dB
1
-5dB to -19dB
2
-19dB to -43dB
3
VOS
AV_HP = -67dB
4
TA = +25ºC
Capacitive Drive Capability
No sustained oscillations
Peak Voltage, A-weighted, 32 samples
per second, AV_HP = -67dB
±0.5
TA = TMIN to TMAX
HPL to HPR and HPR to HPL, POUT = 5mW, f = 1kHz, RHP = 32Ω
KCP
dB
dB
110
Crosstalk
Click and Pop Level
dB
VRMS
-69
f = 1kHz
Output Offset Voltage
-80
HPVOL_ = 0x00
-43dB to -67dB
Mute Attenuation
mW
30
AVHP = 0dB (Note 8)
Headphone Volume Control (PGA)
40
dB
±1
±3
TBD
RHP = 32Ω
500
RHP = ∞
100
Into shutdown
-73
Out of shutdown
-73
mV
dB
pF
dBV
JACK DETECTION
JACKSNS High Threshold
MICBIAS Enabled
0.92 x
VMICBIAS
MICBIAS Disabled
0.92 x 0.95 x 0.98 x
VSPKLVDD VSPKLVDD VSPKLVDD
MICBIAS Enabled
0.06 x
VMICBIAS
MICBIAS Disabled
0.06 x 0.10 x 0.17 x
VSPKLVDD VSPKLVDD VSPKLVDD
MICBIAS Disabled
VSPKLVDD
VTH_HIGH
JACKSNS Low Threshold
VTH_LOW
JACKSNS Sense Voltage
VSENSE
0.95 x
VMICBIAS
0.10 x
VMICBIAS
0.98 x
VMICBIAS
0.17 x
VMICBIAS
V
V
V
RSPU
MICBIAS Disabled, JDWK = 0
TBD
2.3
TBD
kΩ
JACKSNS Weak Pull-up Current
IWPU
MICBIAS Disabled, JDWK = 1
2.5
5
12
μA
M
JACKSNS Strong Pull-up Resistance
JACKSNS Glitch Debounce Period
tGLITCH
JDEB = 00
25
JDEB = 11
200
ms
_____________________________________________________________________ 13
MAXIM Confidential
MAX98090
_____________________________ DIGITAL INPUT/OUTPUT CHARACTERISTICS
(VAVDD = VHPVDD = VDVDDIO = +1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RREC) connected between RECP/LOUTL and RECN/LOUTR
(LINMOD=0). Line Output loads (RLOUT) connected between from RECP/LOUTL and RECN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or
HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RREC = ∞, RLOUT = ∞, RHP = ∞, ZSPK = ∞. CREF = 2.2μF, CVCM = CMICBIAS = 1μF, CC1N-C1P =
CCPVDD = CCPVSS = 1μF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL = AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_REC = AV_LOUT, AV_HP = AV_SPK
= 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS = 0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MCLK
VIH
Input Low Voltage
VIL
1.2
V
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
Input High Voltage
Input Leakage Current
IIH, IIL
VDVDDIO = 2.0V, VIN = 0V, 5.5V, TA = +25ºC
-1
Input Capacitance
0.6
V
1
μA
10
pF
SDIN, BCLK, LRCLK - INPUT
Input High Voltage
VIH
VDVDDIO = 1.65V
Input Low Voltage
VIL
VDVDDIO = 1.65V
0.7 x
VDVDDIO
V
0.3 x
VDVDDIO
Input Hysteresis
125
Input Leakage Current
IIH, IIL
VDVDDIO = 3.6V, VIN = 0V, 3.6V, TA = +25ºC
-1
Input Capacitance
V
mV
1
10
μA
pF
BCLK, LRCLK, SDOUT - OUTPUT
Output High Voltage
VOH
VDVDDIO = 1.65V, IOH = 3mA
Output Low Voltage
VOL
VDVDDIO = 1.65V, IOL = 3mA
Input Leakage Current
IIH, IIL
VDVDDIO = 2.0V, VIN = 0V, 5.5V, TA = +25ºC, High-Z State
VDVDDIO
– 0.4
V
-1
0.4
V
1
μA
SDA, SCL - INPUT
Input High Voltage
VIH
VDVDDIO = 1.65V
Input Low Voltage
VIL
VDVDDIO = 1.65V
0.7 x
VDVDDIO
0.3 x
VDVDDIO
Input Hysteresis
Input Leakage Current
V
100
IIH, IIL
VDVDDIO = 2.0V, VIN = 0V, 5.5V, TA = +25ºC
-1
Input Capacitance
V
mV
1
10
μA
pF
SDA, /IRQ\ - OUTPUT
Output Low Voltage
VOL
VDVDDIO = 1.65V, IOH = 3mA
0.2 x
VDVDDIO
V
Output High Current
IOH
VDVDDIO = 1.65V, IOL = 3mA
1
μA
Input High Voltage
VIH
VDVDDIO = 1.65V
Input Low Voltage
VIL
VDVDDIO = 1.65V
M
DIGMICDATA - INPUT
0.65 x
VDVDDIO
0.35 x
VDVDDIO
Input Hysteresis
Input Leakage Current
Input Capacitance
V
100
IIH, IIL
VDVDDIO = 2.0V, VIN = 0V, 5.5V, TA = +25ºC
-25
V
mV
25
10
_____________________________________________________________________ 14
μA
pF
MAXIM Confidential
MAX98090
(VAVDD = VHPVDD = VDVDDIO = +1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RREC) connected between RECP/LOUTL and RECN/LOUTR
(LINMOD=0). Line Output loads (RLOUT) connected between from RECP/LOUTL and RECN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or
HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RREC = ∞, RLOUT = ∞, RHP = ∞, ZSPK = ∞. CREF = 2.2μF, CVCM = CMICBIAS = 1μF, CC1N-C1P =
CCPVDD = CCPVSS = 1μF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL = AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_REC = AV_LOUT, AV_HP = AV_SPK
= 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS = 0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGMICCLK - INPUT
Input High Voltage
VIH
VDVDDIO = 1.65V
Input Low Voltage
VIL
VDVDDIO = 1.65V
0.65 x
VDVDDIO
V
0.35 x
VDVDDIO
100
mV
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
Input Hysteresis
V
Input Capacitance
10
pF
DIGMICCLK - OUTPUT
Output High Voltage
VOH
VDVDDIO = 1.65V, IOH = 3mA
Output Low Voltage
VOL
VDVDDIO = 1.65V, IOL = 3mA
VDVDDIO
– 0.4
V
0.4
V
______________________________________ INPUT CLOCK CHARACTERISTICS
(VAVDD = VHPVDD = VDVDDIO = +1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RREC) connected between RECP/LOUTL and RECN/LOUTR
(LINMOD=0). Line Output loads (RLOUT) connected between from RECP/LOUTL and RECN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or
HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RREC = ∞, RLOUT = ∞, RHP = ∞, ZSPK = ∞. CREF = 2.2μF, CVCM = CMICBIAS = 1μF, CC1N-C1P =
CCPVDD = CCPVSS = 1μF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL = AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_REC = AV_LOUT, AV_HP = AV_SPK
= 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS = 0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
60
MHz
INPUT CLOCK CHARACTERISTICS
MCLK Input Frequency
fMCLK
MCLK Input Duty Cycle
2.048
PSCLK = 01
40
PSCLK = 10 or 11
30
DHF = 0
8
48
DHF = 1
48
96
Maximum MCLK Input Jitter
LRCLK Sample Rate (Note 9)
DAI LRCLK average frequency
error (Note 10)
PLL Lock Time
50
70
1
fLRCLK
FREQ = 0x8 to 0xF
FREQ = 0x0
%
ns
0
0
-0.025
0.025
Rapid Lock Mode
2
7
Non-Rapid Lock Mode
12
25
Maximum LRCLK input jitter
to maintain PLL lock
±100
10
M
Soft Start / Stop Time
60
_____________________________________________________________________ 15
kHz
%
ms
ns
ms
MAXIM Confidential
MAX98090
___________________ DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS
(VAVDD = VHPVDD = VDVDDIO = +1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RREC) connected between RECP/LOUTL and RECN/LOUTR
(LINMOD=0). Line Output loads (RLOUT) connected between from RECP/LOUTL and RECN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or
HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RREC = ∞, RLOUT = ∞, RHP = ∞, ZSPK = ∞. CREF = 2.2μF, CVCM = CMICBIAS = 1μF, CC1N-C1P = CCPVDD
= CCPVSS = 1μF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL = AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_REC = AV_LOUT, AV_HP = AV_SPK = 0dB.
fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS = 0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS
tBCLK
Slave Mode
80
ns
BCLK High Time
tBCLKH
Slave Mode
20
ns
BCLK Low Time
tBCLKL
Slave Mode
20
ns
BCLK or LRCLK Rise and Fall Time
tr, tf
Master Mode, CL = 15pF
SDIN to BCLK Set-Up Time
tSETUP
LRCLK to BCLK Set-Up Time
tSYNCSET
SDIN to BCLK Hold Time
tHOLD
LRCLK to BCLK Hold Time
tSYNCHOLD
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
BCLK Cycle Time
Slave Mode
Slave Mode
Minimum delay time from LSB
BCLK falling edge to Hi-Z state
tHIZOUT
Master Mode
LRCLK rising edge to
SDOUT MSB Delay
tSYNCTX
C = 30pF, TDM = 1, FSW = 1
BCLK to SDOUT Delay
tCLKTX
C = 30pF
SDOUT valid time before
opposite BCLK edge
SDOUT valid time after
opposite BCLK edge
5
ns
20
ns
20
ns
20
ns
20
20
20
20
TDM = 1, BCLK rising edge
TDM = 0
ns
TBD
ns
TBD
TBD
ns
20
tVALIDPOST
SE Mode
TDM = 1
Master Mode
TDM = 0
20
150
-15
ns
ns
15
0.8 x
tBCLK
M
tCLKSYNC
20
TDM = 1
TDM = 1, FSW = 1
TDM = 1, FSW = 0
TDM = 0, DLY = 1
tVALIDPRE
Delay Time from BCLK to LRCLK
ns
_____________________________________________________________________ 16
ns
MAX98090
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
MAXIM Confidential
M
Figure 1: I2S Audio Interface Timing Diagrams (TDM = 0)
_____________________________________________________________________ 17
MAX98090
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
MAXIM Confidential
M
Figure 2: TDM Audio Interface Short Mode Timing Diagram (TDM = 1)
_____________________________________________________________________ 18
MAX98090
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
MAXIM Confidential
M
Figure 3: TDM Long Mode Timing Diagram (TDM = 1)
_____________________________________________________________________ 19
MAXIM Confidential
MAX98090
_________________________________________ I2C TIMING CHARACTERISTICS
(VAVDD = VHPVDD = VDVDDIO = +1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RREC) connected between RECP/LOUTL and RECN/LOUTR
(LINMOD=0). Line Output loads (RLOUT) connected between from RECP/LOUTL and RECN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or
HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RREC = ∞, RLOUT = ∞, RHP = ∞, ZSPK = ∞. CREF = 2.2μF, CVCM = CMICBIAS = 1μF, CC1N-C1P = CCPVDD
= CCPVSS = 1μF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL = AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_REC = AV_LOUT, AV_HP = AV_SPK = 0dB.
fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS = 0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
I C TIMING CHARACTERISTICS
2
Serial Clock Frequency
Bus Free Time Between STOP and
START Conditions
fSCL
Guaranteed by SCL Pulse-Width Low and High
0
tBUF
1.3
µs
tHD,STA
0.6
µs
SCL Pulse-Width Low
tLOW
1.3
µs
SCL Pulse-Width High
tHIGH
0.6
µs
Setup Time for a Repeated START
Condition
tSU,STA
0.6
µs
Data Hold Time
tHD,DAT
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
Hold Time (Repeated) START Condition
RPU = 475Ω, CB = 100pF, 400pF
0
900
Transmitting
0
900
Receiving
Data Setup Time
ns
0
tSU,STA
100
SDA and SCL Receiving Rise Time
tR
Note 11
20 +
0.1xCB
300
ns
SDA and SCL Receiving Fall Time
tF
Note 11
20 +
0.1xCB
300
ns
SDA Transmitting Fall Time
tF
RPU = 475Ω, CB = 100pF to 400pF, Note 11
20 +
0.1xCB
250
ns
Setup Time for STOP Condition
tSU,STO
Bus Capacitance
CB
Pulse Width of Suppressed Spike
tSP
ns
0.6
Guaranteed by SDA Transmitting Fall Time
0
µs
400
pF
50
ns
M
Figure 4: I2C Interface Timing Diagram
_____________________________________________________________________ 20
MAXIM Confidential
MAX98090
_______________________ DIGITAL MICROPHONE TIMING CHARACTERISTICS
(VAVDD = VHPVDD = VDVDDIO = +1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RREC) connected between RECP/LOUTL and RECN/LOUTR
(LINMOD=0). Line Output loads (RLOUT) connected between from RECP/LOUTL and RECN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or
HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RREC = ∞, RLOUT = ∞, RHP = ∞, ZSPK = ∞. CREF = 2.2μF, CVCM = CMICBIAS = 1μF, CC1N-C1P = CCPVDD
= CCPVSS = 1μF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL = AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_REC = AV_LOUT, AV_HP = AV_SPK = 0dB.
fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS = 0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
DIGITAL MICROPHONE TIMING CHARACTERISTICS
fPCLK/2
MICCLK = 001
fPCLK/3
MICCLK = 010
fPCLK/4
MICCLK = 011
fPCLK/5
MICCLK = 100
fPCLK/6
MICCLK = 101
fPCLK/8
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
MICCLK = 000
DIGMICCLK Frequency
fDIGMICCLK
fMCLK = 12.288MHz
MICCLK = 110
MHz
fPCLK/10
DIGMICDATA to DIGMICCLK Set-Up Time tSU,MIC
Either clock edge
20
ns
DIGMICDATA to DIGMICCLK Hold Time
Either clock edge
0
ns
tHD,MIC
1 / fMICCLK
DIGMICCLK
tHD,MIC
tSU,MIC
tHD,MIC
tSU,MIC
DIGMICDATA
Figure 5: Digital Microphone Timing Diagram
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
M
Note 13:
The MAX98090 is 100% production tested at TA =+25ºC. Specifications over temperature limits are guaranteed by design.
Analog Supply Current = AVDD + HPVDD, Speaker Supply Current = SPKLVDD + SPKRVDD, and Digital Supply Current =
DVDD + DVDDIO
Performance measured at Headphone Outputs, unless otherwise stated.
Dynamic range measured with the EIAJ method. -60dBFS, 1kHz output signal, A-weighted and normalized to 0dBFS. f = 20Hz
– 20kHz
Gain measured relative to the 0dB setting.
Accurate for synchronous clocking modes where NI is a multiple of 0x1000.
Performance measured using DAC Inputs, unless otherwise stated.
Full scale analog output with 0dB of programmable gain, and a 0dBFS DAC input amplitude, a 1VRMS differential analog input
amplitude, or a 0.5VRMS single-ended analog input amplitude.
fLRCLK may be any rate in the indicated range. Asynchronous and non-integer fMCLK/fLRCLK ratios may exhibit some full scale
performance degradation compared to Synchronous integer ratios.
In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate.
CB is in pF.
VCM will be derived from a bandgap reference (VCM_MODE = 1) to allow the DC PSRR measurement to test the supply
voltage range.
Performance measured using an analog input to amplifier output path.
_____________________________________________________________________ 21
MAXIM Confidential
MAX98090
_______________________________________________ POWER CONSUMPTION
_______________________________ TYPICAL OPERATING CHARACTERISTICS
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (MIC TO ADC)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (MIC TO ADC)
0
0
fMCLK = 13MHz
fLRCLK = 8kHz
VIN = 707mVRMS
AV_MIC = 0dB
CIN = 10µF
THD+N RATIO (dB)
-30
-40
-50
-60
-70
-80
-90
-100
-20
-30
THD+N RATIO (dB)
-20
fMCLK = 12.288MHz
fLRCLK = 48kHz
VIN = 707mVRMS
AV_MIC = 0dB
CIN = 10µF
-10
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
-10
-40
-50
-60
-70
-80
-90
-100
10
100
1000
10000
10
100
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (MIC TO ADC)
-10
-20
THD+N RATIO (dB)
-30
-40
-50
-60
-70
-80
-90
-100
10000
100000
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (MIC TO ADC)
0
fMCLK = 13MHz
fLRCLK = 44.1kHz
VIN = 707mVRMS
AV_MIC = 0dB
CIN = 10µF
fMCLK = 12.288MHz
fLRCLK = 96kHz
VIN = 707mVRMS
AV_MIC = 0dB
CIN = 10µF
-10
-20
-30
THD+N RATIO (dB)
0
1000
FREQUENCY (Hz)
-40
-50
-60
-70
-80
-90
100
1000
FREQUENCY (Hz)
10000
100000
-100
10
100
1000
FREQUENCY (Hz)
10000
M
10
_____________________________________________________________________ 22
100000
MAXIM Confidential
MAX98090
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (MIC TO ADC)
GAIN vs FREQUENCY (MIC TO ADC)
5
0
fMCLK = 13MHz
fLRCLK = 8kHz
VIN = 70.7mVRMS
AV_MIC = +20dB
CIN = 10µF
-10
-20
3
2
NORMALIZED GAIN (dB)
-40
-50
-70
-80
-90
-100
1
0
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
THD+N RATIO (dB)
-30
-60
fMCLK = 13MHz
fLRCLK = 8kHz
VIN = 707mVRMS
AV_MIC = 0dB
CIN = 10µF
4
-1
-2
-3
-4
-5
10
100
1000
10000
10
100
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (MIC TO ADC)
-10
-20
THD+N RATIO (dB)
-30
-40
-50
-60
-70
-80
-90
-100
10000
COMMON MODE REJECTION RATIO
vs FREQUENCY (MIC TO ADC)
100
fMCLK = 13MHz
fLRCLK = 8kHz
VIN = 22.4mVRMS
AV_MIC = +30dB
CIN = 10µF
90
AV_MIC = +20dB
80
70
60
CMRR (dB)
0
1000
FREQUENCY (Hz)
50
AV_MIC = 0dB
40
AV_MIC = +30dB
30
20
fMCLK = 12.288MHz
fLRCLK = 48kHz
CIN = 10µF
10
10
100
1000
0
10
100
1000
FREQUENCY (Hz)
10000
M
FREQUENCY (Hz)
10000
____________________________________________________________________ 23
100000
MAXIM Confidential
MAX98090
POWER SUPPLY REJECTION RATIO
vs FREQUENCY (MIC to ADC)
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (MIC TO ADC)
120
20
fMCLK = 13MHz
fLRCLK = 8kHz
AV_MIC = 0dB
CIN = 10µF
0
100
OUTPUT AMPLITUDE (dBFS)
-20
60
40
20
0
-40
-60
-80
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
PSRR (dB)
80
-100
-120
fMCLK = 12.288MHz
fLRCLK = 48kHz
VRIPPLE = 100mVP-P
CIN = 10µF
-140
-160
10
100
1000
FREQUENCY (Hz)
10000
0
100000
500
1000
1500
2000
2500
FREQUENCY (Hz)
3000
3500
4000
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (MIC TO ADC)
20
fMCLK = 13MHz
fLRCLK = 8kHz
AV_MIC = 0dB
CIN = 10µF
0
OUTPUT AMPLITUDE (dBFS)
-20
-40
-60
-80
-100
-120
-140
-160
500
1000
1500
2000
2500
FREQUENCY (Hz)
M
0
____________________________________________________________________ 24
3000
3500
4000
MAXIM Confidential
MAX98090
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (MIC TO ADC)
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (MIC TO ADC)
20
20
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_MIC = 0dB
CIN = 10µF
0
OUTPUT AMPLITUDE (dBFS)
-20
-40
-60
-80
-100
-120
-140
-160
-40
-60
-80
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
OUTPUT AMPLITUDE (dBFS)
-20
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_MIC = 0dB
CIN = 10µF
0
-100
-120
-140
-160
0
5000
10000
FREQUENCY (Hz)
15000
20000
0
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (MIC TO ADC)
0
OUTPUT AMPLITUDE (dBFS)
-20
-40
-60
-80
-100
-120
-140
-160
10000
FREQUENCY (Hz)
15000
20000
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (MIC TO ADC)
20
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_MIC = 0dB
CIN = 10µF
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_MIC = 0dB
CIN = 10µF
0
-20
OUTPUT AMPLITUDE (dBFS)
20
5000
-40
-60
-80
-100
-120
-140
-160
5000
10000
FREQUENCY (Hz)
15000
20000
0
5000
10000
FREQUENCY (Hz)
M
0
____________________________________________________________________ 25
15000
20000
MAXIM Confidential
MAX98090
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (MIC TO ADC)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (LINE TO ADC)
0
20
fMCLK = 12.288MHz
fLRCLK =96kHz
AV_MIC = 0dB
CIN = 10µF
0
-20
-30
THD+N RATIO (dB)
-40
-60
-80
-100
-120
-140
-160
-40
-50
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
OUTPUT AMPLITUDE (dBFS)
-20
fMCLK = 12.288MHz
fLRCLK =48kHz
AV_LINEPGA = -6dB
VIN_SE = 0.5VRMS
VIN_DIFF = 1VRMS
CIN = 10µF
-10
-60
-70
DIFFERENTIAL
-90
-100
0
5000
10000
FREQUENCY (Hz)
15000
10
20000
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (MIC TO ADC)
0
OUTPUT AMPLITUDE (dBFS)
-20
-40
-60
-80
-100
-120
-140
-160
100
1000
FREQUENCY (Hz)
10000
100000
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (LINE TO ADC)
0
fMCLK = 12.288MHz
fLRCLK =96kHz
AV_MIC = 0dB
CIN = 10µF
fMCLK = 12.288MHz
fLRCLK =48kHz
AV_LINEPGA = 0dB
VIN_SE = 354mVRMS
VIN_DIFF = 707mVRMS
CIN = 10µF
-10
-20
-30
THD+N RATIO (dB)
20
SINGLE-ENDED
-80
-40
-50
-60
-70
DIFFERENTIAL
-80
SINGLE-ENDED
-90
-100
5000
10000
FREQUENCY (Hz)
15000
20000
10
100
1000
FREQUENCY (Hz)
M
0
____________________________________________________________________ 26
10000
100000
MAXIM Confidential
MAX98090
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (LINE TO ADC)
POWER SUPPLY REJECTION RATIO
vs FREQUENCY (LINE to ADC)
0
120
fMCLK = 12.288MHz
fLRCLK =48kHz
AV_LINEPGA = +20dB
VIN_SE = 35.4mVRMS
VIN_DIFF = 70.7mVRMS
CIN = 10µF
-10
-20
VCM_MODE = 1
80
PSRR (dB)
-40
-50
-60
-70
60
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
THD+N RATIO (dB)
-30
100
DIFFERENTIAL
SINGLE-ENDED
40
VCM_MODE = 0
-80
-90
-100
20
0
10
100
1000
FREQUENCY (Hz)
10000
100000
10
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (LINE TO ADC)
-10
-20
THD+N RATIO (dB)
-30
-40
-50
-70
-80
1000
FREQUENCY (Hz)
10000
100000
CROSSTALK vs FREQUENCY (LINE TO ADC)
fMCLK = 12.288MHz
fLRCLK =48kHz
AV_EXTERNAL = -9dB
VIN = 2VRMS
CIN = 10µF
DIFFERENTIAL
-60
100
0
fMCLK = 12.288MHz
fLRCLK =48kHz
VIN = 0.5mVRMS
AV_LINEPRE = 0dB
CIN = 10µF
-20
-40
CROSSTALK (dB)
0
fMCLK = 12.288MHz
fLRCLK = 48kHz
VIN SINGLE-ENDED
VRIPPLE = 100mVP-P
CIN = 10µF
SINGLE-ENDED
-60
DIFFERENTIAL
SINGLE-ENDED
-80
-100
-120
-90
-100
-140
100
1000
FREQUENCY (Hz)
10000
100000
10
100
1000
FREQUENCY (Hz)
M
10
____________________________________________________________________ 27
10000
100000
MAXIM Confidential
MAX98090
INBAND OUTPUT SPECTRUM vs FREQUENCY,
-3dBFS INPUT (LINE to ADC)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (INPUT DIRECT TO ADC MIXER)
0
20
fMCLK = 12.288MHz
fLRCLK =48kHz
VIN = 354mVRMS_SE
AV_PRE = 0dB
CIN = 10µF
0
-20
-30
THD+N RATIO (dB)
-40
-60
-80
-100
-120
-140
-160
-40
-50
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
OUTPUT AMPLITUDE (dBFS)
-20
-60
-70
-80
-90
-100
0
5000
10000
FREQUENCY (Hz)
15000
10
20000
INBAND OUTPUT SPECTRUM vs FREQUENCY,
-60dBFS INPUT (LINE to ADC)
20
0
-40
100
1000
FREQUENCY (Hz)
10000
100000
POWER SUPPLY REJECTION RATIO vs FREQUENCY (IN_
DIRECT TO ADC MIXER)
100
fMCLK = 12.288MHz
fLRCLK =48kHz
VIN = 0.5mVRMS_SE
AV_PRE = 0dB
CIN = 10µF
MCLK = 12.288MHz
LRCLK = 48kHz
VRIPPLE = 100mVP-P
CIN = 10µF
90
80
70
60
-60
-80
PSRR (dB)
OUTPUT AMPLITUDE (dBFS)
-20
fMCLK = 12.288MHz
fLRCLK =48kHz
VIN = 707mVRMS
CIN = 10µF
-10
TBD
50
40
-100
-120
-140
-160
30
20
10
0
5000
10000
FREQUENCY (Hz)
15000
20000
10
100
1000
FREQUENCY (Hz)
10000
M
0
____________________________________________________________________ 28
100000
MAXIM Confidential
MAX98090
INBAND OUTPUT SPECTRUM,
-60dBFS (IN_ DIRECT TO ADC MIXER)
CROSSTALK vs FREQUENCY
(INPUT DIRECT TO ADC MIXER)
20
0
fMCLK = 12.288MHz
fLRCLK =48kHz
VIN = 0.5VRMS
CIN = 10µF
-10
-20
-20
AMPLITUDE (dBFS)
-40
-40
TBD
-50
-70
-80
-90
-100
TBD
-60
-80
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
CROSSTALK (dB)
-30
-60
fMCLK = 12.288MHz
fLRCLK =48kHz
VIN = 1mVRMS
CIN = 10µF
0
-100
-120
-140
-160
10
100
1000
FREQUENCY (Hz)
10000
0
100000
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
-140
-160
15000
20000
0
fMCLK = 12.288MHz
fLRCLK =48kHz
VIN = 0.707VRMS
CIN = 10µF
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_TOTAL = 0dB
RHP = 32Ω
CIN = 10µF
-10
-20
-30
THD+N RATIO (dB)
0
10000
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE vs
FREQUENCY (LINE TO ADC TO DAC TO HEADPHONE)
INBAND OUTPUT SPECTRUM,
-3dBFS (INPUT DIRECT TO ADC MIXER)
20
5000
TBD
-40
-50
-60
POUT = 10mW
-70
POUT = 20mW
-80
-90
-100
5000
10000
FREQUENCY (Hz)
15000
20000
10
100
1000
FREQUENCY (Hz)
M
0
____________________________________________________________________ 29
10000
100000
MAXIM Confidential
MAX98090
INBAND OUTPUT SPECTRUM, -3dBFS INPUT
(LINE TO ADC TO DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE vs
FREQUENCY (LINE TO ADC TO DAC TO HEADPHONE)
20
0
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_TOTAL = 0dB
RHP = 32Ω
CIN = 10µF
-10
-20
-20
OUTPUT AMPLITUDE (dBV)
-40
-50
POUT = 10mW
-70
-80
-90
-100
-40
-60
-80
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
THD+N RATIO (dB)
-30
-60
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_TOTAL = 0dB
RHP = 32Ω
CIN = 10µF
0
POUT = 20mW
-100
-120
-140
-160
10
100
1000
FREQUENCY (Hz)
10000
0
100000
5000
10000
FREQUENCY (Hz)
15000
20000
INBAND OUTPUT SPECTRUM, -60dBFS INPUT
(LINE TO ADC TO DAC TO HEADPHONE)
20
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_TOTAL = 0dB
RHP = 32Ω
CIN = 10µF
0
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
-140
-160
5000
10000
FREQUENCY (Hz)
M
0
____________________________________________________________________ 30
15000
20000
MAXIM Confidential
MAX98090
INBAND OUTPUT SPECTRUM, -3dBFS INPUT
(LINE TO ADC TO DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (DAC TO RECEIVER)
20
0
fMCLK =12.288MHz
fLRCLK = 48kHz
AV_TOTAL = 0dB
RHP = 32Ω
CIN = 10µF
0
-20
-30
THD+N RATIO (dB)
-40
-60
-80
-100
-120
-140
-160
-40
-50
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
OUTPUT AMPLITUDE (dBV)
-20
VCM_MODE = 0
fMCLK =13MHz
fLRCLK = 8kHz
AV_REC = +8dB
RREC = 32Ω
-10
-60
-70
-80
fIN = 100Hz
-90
5000
10000
FREQUENCY (Hz)
15000
20000
0
INBAND OUTPUT SPECTRUM, -60dBFS INPUT
(LINE TO ADC TO DAC TO HEADPHONE)
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
-140
-160
0.02
0.04
0.06
0.08
OUTPUT POWER (W)
0.1
0.12
0.1
0.12
TOTAL HARMONIC DISTORTION
vs OUTPUT POWER (DAC TO RECEIVER)
0
fMCLK =12.288MHz
fLRCLK = 48kHz
AV = 0dB
RHP = 32Ω
CIN = 10µF
VCM_MODE = 1
fMCLK =13MHz
fLRCLK = 8kHz
AV_REC = +8dB
RREC = 32Ω
-10
-20
-30
THD+N RATIO (dB)
0
fIN = 3000Hz
-100
0
20
fIN = 1000Hz
-40
-50
-60
-70
-80
fIN = 100Hz
-90
5000
10000
FREQUENCY (Hz)
15000
20000
fIN = 3000Hz
-100
0
0.02
0.04
0.06
0.08
OUTPUT POWER (W)
M
0
fIN = 1000Hz
____________________________________________________________________ 31
MAXIM Confidential
MAX98090
TOTAL HARMONIC DISTORTION
vs FREQUENCY (DAC TO RECEIVER)
GAIN vs FREQUENCY (DAC TO RECEIVER)
5
0
-20
3
2
NORMALIZED GAIN (dB)
-40
-50
-70
-80
-90
-100
POUT = 25mW
1
0
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
THD+N RATIO (dB)
-30
-60
fMCLK =13MHz
fLRCLK = 8kHz
VOICE FILTER
AV_REC = 0dB
RREC = 32Ω
4
fMCLK =13MHz
fLRCLK = 8kHz
AV_REC = +8dB
RREC = 32Ω
-10
-1
-2
-3
POUT = 50mW
-4
-5
10
100
1000
10
10000
100
200
VCM_MODE = 1
100
75
50
RREC = 16Ω
160
POWER CONSUMPTION (mW)
RECEIVER OUTPUT POWER (mW)
125
10000
POWER CONSUMPTION vs
OUTPUT POWER (DAC TO RECEIVER)
OUTPUT POWER vs SPEAKER SUPPLY VOLTAGE
(DAC TO RECEIVER)
150
1000
FREQUENCY (Hz)
FREQUENCY (Hz)
120
80
VCM_MODE = 0
25
0
fMCLK =13MHz
fLRCLK = 8kHz
VCM_MODE = 1
THD+N ≤ 1%
AV_REC = +8dB
40
fMCLK =13MHz
fLRCLK = 8kHz
AV_REC = +8dB
RREC = 32Ω
RREC = 32Ω
0
3
3.5
4
4.5
SPEAKER SUPPLY VOLTAGE (V)
5
5.5
0
20
40
60
80
OUTPUT POWER (mW)
100
M
2.5
____________________________________________________________________ 32
120
140
MAXIM Confidential
MAX98090
POWER SUPPLY REJECTION RATIO vs FREQUENCY
(DAC to RECEIVER)
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO RECEIVER)
120
20
OTHER SUPPLIES
fMCLK =13MHz
fLRCLK = 8kHz
AV_REC = 0dB
RREC = 32Ω
0
100
OUTPUT AMPLITUDE (dBV)
-20
60
SPK_VDD
40
20
0
-40
-60
-80
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
PSRR (dB)
80
fMCLK = 12.288MHz
fLRCLK = 48kHz
VRIPPLE = 100mVP-P
RREC = 32Ω
-100
-120
-140
-160
10
100
1000
FREQUENCY (Hz)
10000
0
100000
5000
10000
FREQUENCY (Hz)
15000
20000
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO RECEIVER)
20
fMCLK =13MHz
fLRCLK = 8kHz
AV_REC = 0dB
RHP = 32Ω
0
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
-140
-160
5000
10000
FREQUENCY (Hz)
M
0
____________________________________________________________________ 33
15000
20000
MAXIM Confidential
MAX98090
TOTAL HARMONIC DISTORTION PLUS NOISE vs
FREQUENCY (LINE TO RECEIVER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (LINE TO RECEIVER)
0
0
DIFFERENTIAL INPUT
VCM_MODE = 0
AV_LINEPGA = 0dB
AV_REC = +8dB
RREC = 32Ω
CIN = 10µF
-10
-20
-20
THD+N RATIO (dB)
-30
-40
-50
-60
-70
-80
-90
-100
POUT = 25mW
-40
-50
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
THD+N RATIO (dB)
-30
DIFFERENTIAL INPUT
VCM_MODE = 0
AV_LINEPGA = 0dB
AV_REC = +8dB
RREC = 32Ω
CIN = 10µF
-10
-60
-70
-80
-90
fIN = 100Hz
0
0.02
fIN = 1000Hz
POUT = 80mW
fIN = 6000Hz
0.04
0.06
0.08
OUTPUT POWER (W)
-100
0.1
10
0.12
100
-20
THD+N RATIO (dB)
-30
-40
-50
-60
-70
-80
-90
-100
100000
10000
100000
5
DIFFERENTIAL INPUT
VCM_MODE = 1
AV_LINEPGA = 0dB
AV_REC = +8dB
RREC = 32Ω
CIN = 10µF
DIFFERENTIAL INPUT
AV_TOTAL = 0dB
RREC = 32Ω
CIN = 10µF
4
3
2
NORMALIZED GAIN (dB)
-10
10000
GAIN vs FREQUENCY
(LINE TO RECEIVER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (LINE TO RECEIVER)
0
1000
FREQUENCY (Hz)
1
0
-1
-2
-3
-4
fIN = 100Hz
0.02
0.04
0.06
0.08
OUTPUT POWER (W)
-5
0.1
0.12
10
100
1000
FREQUENCY (Hz)
M
0
fIN = 1000Hz
fIN = 6000Hz
____________________________________________________________________ 34
MAXIM Confidential
MAX98090
POWER SUPPLY REJECTION RATIO
vs FREQUENCY (LINE TO RECEIVER)
INBAND OUTPUT SPECTRUM,
-3dBV INPUT (LINE TO RECEIVER)
120
20
SPK_VDD
DIFFERENTIAL INPUT
AV_LINEPGA = 0dB
AV_REC = +8dB
RREC = 32Ω
CIN = 10µF
0
100
OUTPUT AMPLITUDE (dBV)
-20
60
OTHER SUPPLIES
40
20
0
-40
-60
-80
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
PSRR (dB)
80
-100
-120
DIFFERENTIAL INPUT
VRIPPLE = 100mVP-P
RREC = 32Ω
CIN = 10µF
-140
-160
10
100
1000
FREQUENCY (Hz)
10000
0
100000
5000
10000
FREQUENCY (Hz)
15000
20000
INBAND OUTPUT SPECTRUM,
-60dBV INPUT (LINE TO RECEIVER)
20
DIFFERENTIAL INPUT
AV_LINEPGA = 0dB
AV_REC = +6dB
RREC = 32Ω
CIN = 10µF
0
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
-140
-160
5000
10000
FREQUENCY (Hz)
15000
M
0
____________________________________________________________________ 35
20000
MAXIM Confidential
MAX98090
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO LINE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT LEVEL (LINE IN TO LINE OUT)
20
0
fMCLK = 13MHz
fLRCLK = 8kHz
AV_LOUT = +3dB
RLOUT = 10kΩ
0
-20
-30
THD+N RATIO (dB)
-40
-60
-80
-100
-120
-140
-160
-40
-50
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
OUTPUT AMPLITUDE (dBV)
-20
AV_LINEPGA = 0dB
AV_LOUT = +3dB
RLOUT = 10kΩ
CIN = 10µF
-10
-60
fIN = 6000Hz
-70
-90
-100
5000
10000
FREQUENCY (Hz)
15000
20000
0
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO LINE)
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
-140
-160
0.2
0.4
0.6
OUTPUT LEVEL (V)
0.8
1
TOTAL HARMONIC DISTORTION PLUS NOISE vs
FREQUENCY (LINE IN TO LINE OUT)
0
fMCLK = 13MHz
fLRCLK = 8kHz
AV_LOUT = +3dB
RLOUT = 10kΩ
AV_LINEPGA = 0dB
AV_LOUT = +3dB
RLOUT = 10kΩ
CIN = 10µF
-10
-20
-30
THD+N RATIO (dB)
0
fIN = 100Hz
-80
0
20
fIN = 1000Hz
-40
-50
-60
-70
VOUT = 300mVRMS
VOUT = 0.707mVRMS
100
1000
FREQUENCY (Hz)
-80
-90
5000
10000
FREQUENCY (Hz)
15000
20000
-100
10
M
0
____________________________________________________________________ 36
10000
100000
MAXIM Confidential
INBAND OUTPUT SPECTRUM,
-3dBV INPUT (LINE IN TO LINE OUT)
TOTAL HARMONIC DISTORTION PLUS NOISE vs
FREQUENCY (LINE IN TO LINE OUT)
0
20
VIN = 2VRMS
AV_EXTERNAL = -9dB
AV_LOUT = +3dB
RLOUT = 10kO
CIN = 10µF
-10
-20
-20
OUTPUT AMPLITUDE (dBV)
-40
SINGLE ENDED LINE INPUT
-70
-60
-80
-100
-120
DIFFERENTIAL LINE INPUT
-80
-40
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
-50
-60
AV_LINEPGA = 0dB
AV_LOUT = +3dB
RLOUT = 10kΩ
CIN = 10µF
0
-30
THD+N RATIO (dB)
MAX98090
-140
-90
-160
-100
10
100
1000
FREQUENCY (Hz)
10000
0
100000
5000
10000
FREQUENCY (Hz)
15000
20000
INBAND OUTPUT SPECTRUM,
-60dBV INPUT (LINE IN TO LINE OUT)
20
AV_LINEPGA = 0dB
AV_LOUT = +3dB
RLOUT = 10kΩ
CIN = 10µF
0
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
-140
-160
5000
10000
FREQUENCY (Hz)
M
0
____________________________________________________________________ 37
15000
20000
MAXIM Confidential
MAX98090
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (DAC TO SPEAKER)
0
0
VSPK_VDD = 5V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 8Ω + 68µH
-10
-20
-20
-30
THD+N RATIO (dB)
f = 6000Hz
-40
-50
-70
-80
-90
-50
-60
-70
-80
-90
f = 100Hz
-100
f = 6000Hz
-40
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
THD+N RATIO (dB)
-30
-60
VSPK_VDD = 3.7V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 8Ω + 68µH
-10
-100
0
0.5
1
OUTPUT POWER (W)
1.5
2
0
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (DAC TO SPEAKER)
0
-10
-20
-50
-60
-70
-80
-90
0.6
0.8
OUTPUT POWER (W)
1
1.2
VSPK_VDD = 3V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 8Ω + 68µH
-10
-20
f = 6000Hz
-30
-40
-50
-60
-70
-80
-90
f = 100Hz
-100
0.4
0
VSPK_VDD = 4.2V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 8Ω + 68µH
f = 6000Hz
-40
0.2
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (DAC TO SPEAKER)
THD+N RATIO (dB)
THD+N RATIO (dB)
-30
f = 1000Hz
f = 100Hz
f = 1000Hz
f = 100Hz
f = 1000Hz
f = 1000Hz
-100
0.2
0.4
0.6
0.8
OUTPUT POWER (W)
1
1.2
1.4
0
0.1
0.2
0.3
0.4
0.5
OUTPUT POWER (W)
M
0
____________________________________________________________________ 38
0.6
0.7
0.8
MAXIM Confidential
MAX98090
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (DAC TO SPEAKER)
0
0
VSPK_VDD = 5V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 4Ω + 33µH
-10
-20
-20
-30
THD+N RATIO (dB)
f = 6000Hz
-40
-50
-70
-80
-90
-40
-50
-60
-70
-80
-90
f = 100Hz
-100
f = 1000Hz
0.5
1
1.5
2
OUTPUT POWER (W)
2.5
3
3.5
0
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (DAC TO SPEAKER)
-10
-20
-50
-60
-70
-80
-90
0.75
1
1.25
OUTPUT POWER (W)
1.5
1.75
2
VSPK_VDD = 3V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 4Ω + 33µH
-10
-20
f = 6000Hz
-30
-40
-50
-60
-70
-80
-90
f = 100Hz
-100
0.5
0
VSPK_VDD = 4.2V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 4Ω + 33µH
f = 6000Hz
-40
0.25
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (DAC TO SPEAKER)
THD+N RATIO (dB)
THD+N RATIO (dB)
-30
f = 1000Hz
f = 100Hz
-100
0
0
f = 6000Hz
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
THD+N RATIO (dB)
-30
-60
VSPK_VDD = 3.7V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 4Ω + 33µH
-10
f = 1000Hz
f = 1000Hz
f = 100Hz
-100
0.5
1
1.5
OUTPUT POWER (W)
2
2.5
0
0.2
0.4
0.6
0.8
OUTPUT POWER (W)
M
0
____________________________________________________________________ 39
1
1.2
1.4
MAXIM Confidential
MAX98090
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (DAC TO SPEAKER)
0
0
VSPK_VDD = 5V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 8Ω + 68µH
-10
-20
-20
THD+N RATIO (dB)
-30
-40
POUT = 1.00W
-50
-70
-80
-90
POUT = 0.60W
-40
-50
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
THD+N RATIO (dB)
-30
-60
VSPK_VDD = 3.7V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 8Ω + 68µH
-10
-60
-70
-80
-90
POUT = 0.15W
POUT = 0.25W
-100
-100
10
100
1000
FREQUENCY (Hz)
10000
100000
10
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (DAC TO SPEAKER)
0
-10
-20
-50
-60
-70
-80
-90
-100
10000
100000
0
VSPK_VDD = 4.2V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 8Ω + 68µH
VSPK_VDD = 5V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 4Ω + 33µH
-10
-20
-30
POUT = 0.76W
-40
1000
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (DAC TO SPEAKER)
THD+N RATIO (dB)
THD+N RATIO (dB)
-30
100
POUT = 2.00W
-40
-50
-60
-70
-80
-90
POUT = 0.50W
POUT = 0.20W
100
1000
FREQUENCY (Hz)
10000
100000
10
100
1000
FREQUENCY (Hz)
M
10
-100
____________________________________________________________________ 40
10000
100000
MAXIM Confidential
MAX98090
OUTPUT POWER vs SUPPLY VOLTAGE
(DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (DAC TO SPEAKER)
0
2500
VSPK_VDD = 4.2V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 4Ω + 33µH
-20
POUT = 1.50W
-40
-50
-70
-80
-90
THD+N = 10%
1500
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
THD+N RATIO (dB)
-30
-60
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 8Ω + 68µH
2000
OUTPUT POWER PER CHANNEL (mW)
-10
1000
THD+N = 1%
500
POUT = 0.40W
-100
0
10
100
1000
FREQUENCY (Hz)
10000
2.5
100000
-20
THD+N RATIO (dB)
-30
-50
-60
-70
-80
-90
5
5.5
5
5.5
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 4Ω + 33µH
4000
POUT = 1.20W
-40
4
4.5
SUPPLY VOLTAGE (V)
4500
VSPK_VDD = 3.7V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
ZSPK = 4Ω + 33µH
OUTPUT POWER PER CHANNEL (mW)
-10
3.5
OUTPUT POWER vs SUPPLY VOLTAGE
(DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (DAC TO SPEAKER)
0
3
3500
THD+N = 10%
3000
2500
2000
1500
1000
THD+N = 1%
500
POUT = 0.30W
-100
0
100
1000
FREQUENCY (Hz)
10000
100000
2.5
3
3.5
4
4.5
SUPPLY VOLTAGE (V)
M
10
____________________________________________________________________ 41
MAXIM Confidential
MAX98090
GAIN vs FREQUENCY (DAC TO SPEAKER)
EFFICIENCY vs OUTPUT POWER (DAC TO SPEAKER)
5
100
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = 0dB
ZSPK = 8Ω + 68µH
4
80
70
1
60
EFFICIENCY (%)
2
0
-1
ZSPK = 8Ω + 68H
50
40
30
-2
VSPK_VDD = 4.2V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
20
-3
10
-4
0
-5
10
100
1000
FREQUENCY (Hz)
10000
0
100000
0.5
1
1.5
2
OUTPUT POWER PER CHANNEL (W)
2.5
3
EFFICIENCY vs OUTPUT POWER (DAC TO SPEAKER)
EFFICIENCY vs OUTPUT POWER (DAC TO SPEAKER)
100
100
90
90
80
80
70
70
ZSPK = 8Ω + 68H
60
ZSPK = 8Ω + 68H
ZSPK = 4Ω + 33H
EFFICIENCY (%)
EFFICIENCY (%)
ZSPK = 4Ω + 33H
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
NORMALIZED GAIN (dB)
3
90
50
40
ZSPK = 4Ω + 33H
60
50
40
30
30
10
VSPK_VDD = 3.7V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
20
VSPK_VDD = 5V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = +8dB
20
10
0
0
0.5
1
1.5
2
2.5
OUTPUT POWER PER CHANNEL (W)
3
3.5
0
0.25
0.5
0.75
1
1.25
1.5
OUTPUT POWER PER CHANNEL (W)
M
0
____________________________________________________________________ 42
1.75
2
MAXIM Confidential
MAX98090
SUPPLY CURRENT vs SUPPLY VOLTAGE
(DAC TO SPEAKERS)
CROSSTALK vs FREQUENCY (DAC TO SPEAKERS)
0
5
fMCLK = 12.288MHz
fLRCLK = 48kHz
ZSPK = 8Ω + 68µH
4.5
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = 0dB
ZSPK = 8Ω + 68µH
-20
4
CROSSTALK (dB)
-40
3
2.5
2
-60
RIGHT TO LEFT
LEFT TO RIGHT
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
SUPPLY CURRENT (mA)
3.5
-80
1.5
1
0.5
0
-100
-120
2.5
3
3.5
4
4.5
SUPPLY VOLTAGE (V)
5
5.5
10
100
1000
FREQUENCY (Hz)
POWER SUPPLY REJECTION RATIO
vs FREQUENCY (DAC to SPEAKER)
120
100
PSRR (dB)
80
60
40
fMCLK = 12.288MHz
fLRCLK = 48kHz
VRIPPLE = 100mVP-P
ZSPK = 8Ω + 68µH
OTHER SUPPLIES
SPK_VDD
20
0
100
1000
FREQUENCY (Hz)
10000
100000
M
10
____________________________________________________________________ 43
10000
100000
MAXIM Confidential
MAX98090
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO SPEAKERS)
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO SPEAKERS)
20
20
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = -6dB
ZSPK = 8Ω + 68µH
0
-20
-40
OUTPUT AMPLITUDE (dBV)
-40
-60
-80
-100
-120
-140
-160
-60
-80
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
OUTPUT AMPLITUDE (dBV)
-20
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_SPK = -6dB
ZSPK = 8Ω + 68µH
0
-100
-120
-140
-160
0
5000
10000
FREQUENCY (Hz)
15000
20000
0
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO SPEAKERS)
0
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
-140
-160
10000
FREQUENCY (Hz)
15000
20000
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO SPEAKERS)
20
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = -6dB
ZSPK = 8Ω + 68µH
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_SPK = -6dB
ZSPK = 8Ω + 68µH
0
-20
OUTPUT AMPLITUDE (dBV)
20
5000
-40
-60
-80
-100
-120
-140
-160
5000
10000
FREQUENCY (Hz)
15000
20000
0
5000
10000
FREQUENCY (Hz)
M
0
____________________________________________________________________ 44
15000
20000
MAXIM Confidential
MAX98090
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO SPEAKERS)
WIDEBAND FREQUENCY SPECTRUM
(DAC TO SPEAKERS)
0
20
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = -6dB
ZSPK = 4Ω + 33µH
0
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = 0dB
ZSPK = 8W + 68µH
-20
-40
AMPLITUDE (dBV)
-40
-60
-80
-100
-120
-60
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
OUTPUT AMPLITUDE (dBV)
-20
-80
-100
-140
-160
-120
0
5000
10000
FREQUENCY (Hz)
15000
0.1
20000
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
-140
0
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPK = -6dB
ZSPK = 4Ω + 33µH
AV_LINEPGA = 0dB
AV_SPK = +8dB
ZSPK = 8Ω + 68µH
CIN = 10µF
-10
-20
f = 6000Hz
-30
-40
-50
-60
-70
-80
-90
f = 100Hz
-160
100
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (LINE TO SPEAKER)
THD+N RATIO (dB)
0
10
FREQUENCY (MHz)
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO SPEAKERS)
20
1
f = 1000Hz
-100
5000
10000
FREQUENCY (Hz)
15000
20000
0
0.2
0.4
0.6
OUTPUT POWER (W)
M
0
____________________________________________________________________ 45
0.8
1
MAXIM Confidential
MAX98090
POWER SUPPLY REJECTION RATIO
vs FREQUENCY (LINE to SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE vs
FREQUENCY (LINE TO SPEAKER)
120
0
AV_LINEPGA = 0dB
AV_SPK = +8dB
ZSPK = 8Ω + 68µH
CIN = 10µF
-10
-20
100
-30
80
POUT = 0.60W
PSRR (dB)
-40
-50
-60
-70
-80
-90
-100
60
40
SPK_VDD
20
POUT = 0.15W
10
100
1000
FREQUENCY (Hz)
10000
0
10
100000
100
1000
FREQUENCY (Hz)
10000
100000
CROSSTALK vs FREQUENCY (LINE TO SPEAKER)
GAIN vs FREQUENCY (LINE TO SPEAKER)
0
5
AV_LINEPGA = 0dB
AV_SPK = +8dB
ZSPK = 8Ω + 68µH
CIN = 10µF
4
3
2
AV_SPK = 0dB
ZSPK = 8Ω + 68µH
CIN = 10µF
-20
-40
CROSSTALK (dB)
NORMALIZED GAIN (dB)
OTHER SUPPLIES
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
THD+N RATIO (dB)
VRIPPLE = 100mVP-P
ZSPK = 8Ω + 68µH
CIN = 10µF
1
0
-1
-60
RIGHT TO LEFT
-80
-2
-3
-100
-4
LEFT TO RIGHT
-120
-5
100
1000
FREQUENCY (Hz)
10000
100000
10
100
1000
FREQUENCY (Hz)
M
10
____________________________________________________________________ 46
10000
100000
MAXIM Confidential
MAX98090
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (DAC TO HEADPHONE)
INBAND OUTPUT SPECTRUM,
-3dBV INPUT (LINE TO SPEAKERS)
0
0
AV_LINEPGA = -6dB
AV_SPK = 0dB
ZSPK = 8O + 68µH
CIN = 10µF
-20
-40
THD+N RATIO (dB)
-30
-60
-80
-100
-40
TBD
-50
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
OUTPUT AMPLITUDE (dBV)
-20
f = 3000Hz
fMCLK = 13MHz
fLRCLK = 8kHz
AV_HP = +3dB
RHP = 32Ω
-10
-60
-70
-80
-120
-90
f = 100Hz
-140
0
5000
10000
FREQUENCY (Hz)
15000
0
20000
-40
-60
-80
-100
0.02
0.03
OUTPUT POWER (W)
0.04
0.05
0
AV_LINEPGA = -6dB
AV_SPK = 0dB
ZSPK = 8O + 68µH
CIN = 10µF
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_HP = +3dB
RHP = 32Ω
-10
-20
-30
THD+N RATIO (dB)
OUTPUT AMPLITUDE (dBV)
-20
0.01
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (DAC TO HEADPHONE)
INBAND OUTPUT SPECTRUM,
-60dBV INPUT (LINE TO SPEAKERS)
0
f = 1000Hz
-100
-40
-50
f = 1000Hz
f = 6000Hz
-60
-70
-80
-120
-140
-90
f = 100Hz
-100
5000
10000
FREQUENCY (Hz)
15000
20000
0
0.01
0.02
0.03
OUTPUT POWER (W)
M
0
____________________________________________________________________ 47
0.04
0.05
MAXIM Confidential
MAX98090
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (DAC TO HEADPHONE)
0
0
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = +3dB
RHP = 32Ω
-10
-20
-20
THD+N RATIO (dB)
-30
-40
-50
f = 1000Hz
f = 100Hz
-70
-80
-40
-50
f = 6000Hz
f = 1000Hz
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
THD+N RATIO (dB)
-30
-60
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = +3dB
RHP = 16Ω
-10
-60
-70
-80
f = 6000Hz
-90
-100
-90
f = 100Hz
-100
0
0.01
0.02
0.03
OUTPUT POWER (W)
0.04
0.05
0
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (DAC TO HEADPHONE)
-10
-20
THD+N RATIO (dB)
-30
-40
-50
-60
-80
0.03
0.04
OUTPUT POWER (W)
0.05
0.06
0.07
0.06
0.07
0
fMCLK = 12.288MHz
fLRCLK = 96kHz
AV_HP = +3dB
RHP = 32Ω
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
AV_HP = +3dB
RHP = 16Ω
-10
-20
-30
-40
f = 1000Hz
f = 6000Hz
-50
-60
f = 1000Hz
f = 100Hz
-70
0.02
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (DAC TO HEADPHONE)
THD+N RATIO (dB)
0
0.01
-70
-80
f = 6000Hz
-90
-100
-90
f = 100Hz
-100
0.01
0.02
0.03
OUTPUT POWER (W)
0.04
0.05
0
0.01
0.02
0.03
0.04
OUTPUT POWER (W)
0.05
M
0
____________________________________________________________________ 48
MAXIM Confidential
MAX98090
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (DAC TO HEADPHONE)
0
0
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
AV_HP = +3dB
RHP = 32Ω
-10
-20
-20
THD+N RATIO (dB)
-30
-40
f = 1000Hz
f = 6000Hz
-50
-70
-80
-90
-40
-50
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
THD+N RATIO (dB)
-30
-60
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_HP = +3dB
RHP = 32Ω
-10
-60
POUT = 0.01W
POUT = 0.02W
-70
-80
-90
f = 100Hz
-100
-100
0
0.01
0.02
0.03
OUTPUT POWER (W)
0.04
0.05
10
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (DAC TO HEADPHONE)
-10
-20
THD+N RATIO (dB)
-30
-40
-50
-60
-80
-90
10000
100000
0
fMCLK = 13MHz
fLRCLK = 8kHz
AV_HP = +3dB
RHP = 32Ω
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = +3dB
RHP = 32Ω
-10
-20
-30
POUT = 0.02W
-70
1000
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (DAC TO HEADPHONE)
THD+N RATIO (dB)
0
100
-40
-50
-60
POUT = 0.01W
POUT = 0.02W
100
1000
FREQUENCY (Hz)
-70
-80
-90
POUT = 0.01W
-100
-100
10
100
1000
10
M
FREQUENCY (Hz)
10000
____________________________________________________________________ 49
10000
100000
MAXIM Confidential
MAX98090
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (DAC TO HEADPHONE)
0
0
fMCLK = 12.288MHz
fLRCLK = 96kHz
AV_HP = +3dB
RHP = 32Ω
-10
-20
-20
THD+N RATIO (dB)
-30
-40
-50
POUT = 0.01W
-70
-80
-90
-100
-40
TBD
-50
POUT = 0.02W
-60
-70
-90
-100
100
1000
FREQUENCY (Hz)
10000
100000
10
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (DAC TO HEADPHONE)
-20
THD+N RATIO (dB)
-30
-40
-50
-70
-80
-90
1000
FREQUENCY (Hz)
10000
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
AV_HP = +3dB
RHP = 32Ω
-10
-20
-30
POUT = 0.025W
-40
TBD
-50
-60
-70
-80
-90
POUT = 0.01W
-100
100000
0
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = +3dB
RHP = 16Ω
POUT = 0.01W
-60
100
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (DAC TO HEADPHONE)
THD+N RATIO (dB)
-10
POUT = 0.01W
-80
10
0
POUT = 0.025W
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
THD+N RATIO (dB)
-30
-60
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
AV_HP = +3dB
RHP = 16Ω
-10
POUT = 0.02W
-100
100
1000
FREQUENCY (Hz)
10000
100000
10
100
1000
FREQUENCY (Hz)
M
10
____________________________________________________________________ 50
10000
100000
MAXIM Confidential
MAX98090
POWER CONSUMPTION vs OUTPUT POWER
(DAC TO HEADPHONE)
GAIN vs FREQUENCY (DAC TO HEADPHONE)
5
100
fMCLK = 13MHz
fLRCLK = 8kHz
AV_HP = 0dB
RHP = 32Ω
4
3
80
CURRENT CONSUMPTION (mA)
1
0
-2
70
RHP = 16Ω
60
50
40
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NORMALIZED GAIN (dB)
2
-1
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = +3dB
90
30
20
-3
RHP = 32Ω
10
-4
0
0.1
-5
10
100
1000
10000
1
10
OUTPUT POWER PER CHANNEL (mW)
100
FREQUENCY (Hz)
POWER CONSUMPTION vs OUTPUT POWER
(DAC TO HEADPHONE)
GAIN vs FREQUENCY (DAC TO HEADPHONE)
5
2
1
0
-1
80
CURRENT CONSUMPTION (mA)
3
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
AV_HP = +3dB
90
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = 0dB
RHP = 32Ω
4
NORMALIZED GAIN (dB)
100
70
RHP = 16Ω
60
50
40
30
20
-2
RHP = 32Ω
10
-3
0
-4
0.1
-5
100
1000
FREQUENCY (Hz)
10000
100000
M
10
1
10
OUTPUT POWER PER CHANNEL (mW)
____________________________________________________________________ 51
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MAXIM Confidential
MAX98090
POWER SUPPLY REJECTION RATIO
vs FREQUENCY (DAC to HEADPHONES)
CROSSTALK vs FREQUENCY (DAC TO HEADPHONE)
0
120
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = 0dB
RHP = 32Ω
SPK_VDD
-20
100
RIGHT TO LEFT
LEFT TO RIGHT
-40
CROSSTALK (dB)
60
OTHER SUPPLIES
40
20
0
TBD
-60
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PSRR (dB)
80
-80
fMCLK = 12.288MHz
fLRCLK = 48kHz
VRIPPLE = 100mVP-P
RHP = 32Ω
-100
-120
10
100
1000
FREQUENCY (Hz)
10000
100000
10
100
1000
FREQUENCY (Hz)
POWER SUPPLY REJECTION RATIO
vs FREQUENCY (DAC to HEADPHONES)
120
SPK_VDD
100
PSRR (dB)
80
60
OTHER SUPPLIES
40
20
0
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
VRIPPLE = 100mVP-P
RHP = 32Ω
100
1000
FREQUENCY (Hz)
10000
100000
M
10
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100000
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MAX98090
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO HEADPHONE)
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO HEADPHONE)
20
20
fMCLK = 13MHz
fLRCLK = 8kHz
AV_HP = 0dB
RHP = 32Ω
0
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
-140
-160
-40
-60
-80
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OUTPUT AMPLITUDE (dBV)
-20
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_HP = 0dB
RHP = 32Ω
0
-100
-120
-140
-160
0
5000
10000
FREQUENCY (Hz)
15000
20000
0
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO HEADPHONE)
0
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
-140
-160
10000
FREQUENCY (Hz)
15000
20000
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO HEADPHONE)
20
fMCLK = 13MHz
fLRCLK = 8kHz
AV_HP = 0dB
RHP = 32Ω
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_HP = 0dB
RHP = 32Ω
0
-20
OUTPUT AMPLITUDE (dBV)
20
5000
-40
-60
-80
-100
-120
-140
-160
5000
10000
FREQUENCY (Hz)
15000
20000
0
5000
10000
FREQUENCY (Hz)
M
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MAX98090
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO HEADPHONE)
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO HEADPHONE)
20
20
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = 0dB
RHP = 32Ω
0
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
-140
-160
-40
-60
-80
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OUTPUT AMPLITUDE (dBV)
-20
fMCLK = 12.288MHz
fLRCLK = 96kHz
AV_HP = 0dB
RHP = 32Ω
0
-100
-120
-140
-160
0
5000
10000
FREQUENCY (Hz)
15000
20000
0
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO HEADPHONE)
0
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
-140
-160
10000
FREQUENCY (Hz)
15000
20000
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO HEADPHONE)
20
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = 0dB
RHP = 32Ω
fMCLK = 12.288MHz
fLRCLK = 96kHz
AV_HP = 0dB
RHP = 32Ω
0
-20
OUTPUT AMPLITUDE (dBV)
20
5000
-40
-60
-80
-100
-120
-140
-160
5000
10000
FREQUENCY (Hz)
15000
20000
0
5000
10000
FREQUENCY (Hz)
M
0
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MAX98090
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO HEADPHONE)
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO HEADPHONE)
20
20
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
AV_HP = 0dB
RHP = 32Ω
0
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
-140
-160
-40
TBD
-60
-80
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OUTPUT AMPLITUDE (dBV)
-20
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = 0dB
RHP = 16Ω
0
-100
-120
-140
-160
0
5000
10000
FREQUENCY (Hz)
15000
20000
0
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO HEADPHONE)
0
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
-140
-160
10000
FREQUENCY (Hz)
15000
20000
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO HEADPHONE)
20
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
AV_HP = 0dB
RHP = 32Ω
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = 0dB
RHP = 16Ω
0
-20
OUTPUT AMPLITUDE (dBV)
20
5000
-40
-60
-80
-100
-120
-140
-160
5000
10000
FREQUENCY (Hz)
15000
20000
0
5000
10000
FREQUENCY (Hz)
M
0
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MAX98090
GAIN vs FREQUENCY (LINE TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs OUTPUT POWER (LINE TO HEADPHONE)
5
0
-20
3
2
NORMALIZED GAIN (dB)
-40
-50
-70
-80
-90
f = 6000Hz
f = 100Hz
1
0
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THD+N RATIO (dB)
-30
-60
AV_LINEPGA = 0dB
AV_HP = 0dB
RHP = 32Ω
CIN = 10µF
4
AV_LINEPGA = 0dB
AV_HP = +3dB
RHP = 32Ω
CIN = 10µF
-10
-1
-2
-3
-4
f = 1000Hz
-100
-5
0
0.01
0.02
0.03
OUTPUT POWER (W)
0.04
10
0.05
-10
-20
1000
FREQUENCY (Hz)
10000
100000
POWER SUPPLY REJECTION RATIO
vs FREQUENCY (LINE to HEADPHONES)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs FREQUENCY (LINE TO HEADPHONE)
0
100
120
AV_LINEPGA = 0dB
AV_HP = +3dB
RHP = 32Ω
CIN = 10µF
VRIPPLE = 100mVP-P
RHP = 32Ω
CIN = 10µF
100
VCM_MODE = 1
-40
-50
-60
80
PSRR (dB)
THD+N RATIO (dB)
-30
POUT = 0.01W
-70
-80
-90
-100
60
40
20
VCM_MODE = 0
POUT = 0.02W
100
1000
FREQUENCY (Hz)
0
10000
100000
10
100
1000
FREQUENCY (Hz)
10000
M
10
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MAX98090
CROSSTALK vs FREQUENCY (LINE TO HEADPHONE)
INBAND OUTPUT SPECTRUM,
-3dBV INPUT (LINE TO HEADPHONE)
0
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = 0dB
RHP = 32Ω
-20
20
RIGHT TO LEFT
LEFT TO RIGHT
-20
OUTPUT AMPLITUDE (dBV)
TBD
-80
-40
-60
-80
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CROSSTALK (dB)
-40
-60
AV_LINEPGA = -6dB
AV_HP = 0dB
RHP = 32Ω
CIN = 10µF
0
-100
-120
-100
-140
-120
-160
10
100
1000
FREQUENCY (Hz)
10000
0
100000
COMMON MODE REJECTION RATIO
vs FREQUENCY (LINE TO HEADPHONE)
80
10000
FREQUENCY (Hz)
15000
20000
INBAND OUTPUT SPECTRUM,
-60dBV INPUT (LINE TO HEADPHONE)
20
RHP = 32Ω
CIN = 10µF
70
AV_LINEPGA = -6dB
AV_HP = 0dB
RHP = 32Ω
CIN = 10µF
0
OUTPUT AMPLITUDE (dBV)
-20
60
TBD
50
CMRR (dBV)
5000
40
30
20
-40
-60
-80
-100
-120
10
-140
0
-160
100
1000
FREQUENCY (Hz)
10000
100000
0
5000
10000
FREQUENCY (Hz)
M
10
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MAX98090
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_________________________________________ BUMP CONFIGURATION (WLP)
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___________________________________________ PIN CONFIGURATION (TQFN)
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MAX98090
_____________________________________________ PIN / BUMP DESCRIPTION
BUMP
WLP
MAX98090
FUNCTION
1
G1
HPGND
2
G2
CPVSS
3
F1
CPVDD
4
E1
HPL
Headphone Ground.
Inverting Charge-Pump Output. Bypass to HPGND with a 1µF ceramic
capacitor.
Non-Inverting Charge-Pump Output. Bypass to HPGND with a 1µF ceramic
capacitor.
Left-Channel Headphone Output
Headphone Amplifier Ground Sense. Connect to the headphone jack ground
terminal or connect to ground.
Right-Channel Headphone Output
Jack detection Input. Connect to the microphone terminal of the headset jack
to detect jack activity.
Positive Earpiece Amplifier Output/Left Line Output
Negative Earpiece Amplifier Output/Right Line Output
Right Speaker Amplifier ground.
Negative Right-Channel Class D Speaker Output
Positive Right-Channel Class D Speaker Output
Right Speaker power supply. Bypass to SPKRGND with a 1µF capacitor.
Left Speaker and Microphone Bias Power Supply. Bypass to SPKLGND with a
1µF capacitor.
Negative Left-Channel Class D Speaker Output
Positive Left-Channel Class D Speaker Output
Left Speaker Amplifier Ground.
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PIN
TQFN
D2
HPSNS
6
D1
HPR
7
B5
JACKSNS
8
9
10
11
12
13
C1
B1
A1
A2
A3
-
RCVP/LOUTL
RCVN/LOUTR
SPKRGND
SPKRN
SPKRP
SPKRVDD
14
-
SPKLVDD
15
16
17
A5
A4
A6
SPKLN
SPKLP
SPKLGND
18
B7
IN2 / DMC
19
A7
IN1 / DMD
20
B6
IN3
21
C6
IN4
22
C7
MICBIAS
23
24
25
26
27
D6
E6
D7
E7
F7
REF
VCM
AGND
AVDD
DVDD
28
29
30
F6
G7
E5
DVDDIO
DGND
SDIN
31
G6
SDOUT
DVDDIO.
LRCLK
Digital Audio Left-Right Clock Input/Output. LRCLK is the audio sample rate
clock and determines whether audio data is routed to the left or right channel.
In TDM mode, LRCLK is a frame sync pulse. LRCLK is an input when the
AX49 is in slave mode and an output when in master mode.
M
5
32
F5
Positive Differential Microphone 1 Input or single-ended Line Input 2. ACcouple with a series 1μF capacitor. Can be retasked as a digital
microphone clock output.
Negative Differential Microphone 1 Input or single-ended Line Input 1. ACcouple with a series 1μF capacitor. Can be retasked as a digital
microphone data input.
Negative Differential Microphone 2 Input or single-ended Line Input 3. ACcouple with a series 1μF capacitor.
Positive Differential Microphone 2 Input or single-ended Line input 4. ACcouple with a series 1μF capacitor.
Low-Noise Bias Voltage. The bias voltage is programmable. An external
resistor in the 2.2k to 1k range should be used to set the microphone
current.
Converter Reference. Bypass to AGND with a 2.2µF capacitor.
Common Mode Reference Voltage. Bypass to AGND with a 1µF capacitor.
Analog Ground.
Analog Power Supply. Bypass to AGND with a 1µF capacitor.
Digital Power Supply. Bypass to DGND with a 1µF capacitor.
Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1µF
capacitor.
Digital Ground
Digital Audio Serial Data DAC Input
Digital Audio Serial Data ADC Output. The output voltage is referenced to
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MAX98090
Digital Audio Bit Clock Input/Output. BCLK is an input when the IC is in slave
mode and an output when in master mode. The input/output voltage is
33
G5
BCLK
F4
G4
D3
/IRQ\
MCLK
SCL
37
38
E2
G3
SDA
HPVDD
39
F3
C1P
40
C1N
-
F2
B3,
B4
SPKVDD
-
C4
IN5
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34
35
36
referenced to DVDDIO.
Active Low Hardware Interrupt Output. Connect a 10KΩ pull-up resistor to
VDD.
Master Clock Input. Acceptable input frequency range is 10MHz to 60MHz.
I2C Serial Clock Input. Connect a pull-up resistor to DVDD for full output swing.
I2C Serial Data Input/Output. Connect a pull-up resistor to DVDD for full output
swing.
Headphone Power Supply. Bypass to HPGND with a 1µF capacitor.
Charge-Pump Flying Capacitor Positive Terminal. Connect a 1µF ceramic
capacitor between C1N and C1P.
Charge-Pump Flying Capacitor Negative Terminal. Connect a 1µF ceramic
capacitor between C1N and C1P.
Speaker and Microphone Bias Power Supply. Bypass to SPK_GND with a 1µF
capacitor.
Auxiliary Negative Differential Microphone Input or single-ended line input
AC-couple with a series 1µF capacitor.
Auxiliary Positive Differential Microphone Input or single-ended line input
-
IN6
AC-couple with a series 1µF capacitor.
NC
Not internally connected.
M
-
D4
B2,
C2,
C3,
C5,
D5,
E3,
E4
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____________________________________________________________ DETAILED
MAX98090
DESCRIPTION
The MAX98090 is a fully integrated stereo audio codec with FLEXSOUND audio processing and integrated input and
output audio amplifiers.
The device features either six (WLP package) or four (TQFN package) flexible analog inputs. Each pair can be
configured as a differential analog microphone input, a single ended or differential Line input(s), or as a reduced
power, direct differential analog input to the ADC mixer. One input pair, IN1/IN2, can also be re-tasked to support two
digital microphones. As a result, any combination of two microphones (either analog or digital) can be recorded from
simultaneously. The input analog signals are amplified by up to 50dB, and then are either recorded by the stereo ADC
or routed directly to the analog output mixers for playback.
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The ADC supports sample rates between 8kHz and 96kHz, an optional dither enable, and features two performance
modes and oversampling rates. The ADC to DAI recording path features both voice (IIR) and Music (FIR) filtering,
optional DC blocking and configurable biquad filters, and up to 21dB of programmable digital gain and level control.
The digital audio interface (DAI) can simultaneously transmit and receive separate and distinct stereo audio signals in
a wide range of formats including I2S, LJ, RJ, and up to four slots in TDM. Like the ADC to DAI recording path, the DAI
to DAC playback path supports sample rates from 8kHz to 96kHz, both voice (IIR) and Music (FIR) filtering (high stop
band attenuation at fs/2), optional DC blocking filters, and up to 18dB of digital gain and level control. In addition, the
DAI playback path also features a 7 band parametric biquad equalizer, automatic level control (ALC) with up to 12dB
of compression, and a summing digital sidetone from the ADC recording path.
The MAX98090 includes three analog output drivers. The first is a differential receiver / earpiece BTL amplifier.
Alternatively, the receiver amplifier can also be configured a stereo single ended line output.
The second is an integrated, filterless, class D stereo speaker amplifier. This amplifier provides efficient amplification
for two speakers, and includes active emissions limiting to minimize the radiated emissions (EMI) traditionally
associated with class D. The right channel features a slave mode where the switching is synchronized to that of the
left channel to eliminate the beat tone that can occur with asynchronous operation. In most systems, no output filtering
is required.
M
Finally, the third is a class H, ground referenced stereo headphone amplifier featuring Maxim’s second generation
DirectDrive architecture. The class H headphone amplifiers use a charge pump to generate a ground referenced
output signal. This eliminates the need for either DC blocking capacitors or a mid-rail bias for the headphone jack
ground return. The charge pump generates both the positive and negative supply for the headphone amplifier. A
tracking circuit monitors the input signal level and automatically selects between two supply voltage levels based on
the signal level. For low signal levels the charge pump outputs HPVDD / 2 and –HPVDD / 2 for improved efficiency.
For high signal levels the charge pump outputs HPVDD and –HPVDD to maximum output power. Ground sense
reduces output noise caused by ground return current.
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MAX98090
Device I2C Register Map
Table 1 lists all of the registers, their addresses, and power-on-reset (PoR) states. Registers 0x01, 0x02 and
0xFF are read-only. Register 0x00, and all of the remaining registers, are read/write. Write zeros to all unused
bits in the register table when updating the register, unless otherwise noted.
Table 1: MAX98090 Control Register Map (Register Bits in Bold are WLP Package Only)
REGISTER DESCRIPTION
ADDR
NAME
REGISTER CONTENTS
R/W
BIT 7
POR
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
-
-
-
-
-
-
-
DS
STATE PAGE
RESET / STATUS / INTERRUPT REGISTERS
0x01
0x02
0x03
SOFTWARE RESET
W
SWRESET
0x00
116
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0x00
DEVICE STATUS
CoR
CLD
SLD
ULK
-
-
JDET
ALCACT
ALCCLP
0x00
112
JACK STATUS
R
-
-
-
-
-
LSNS
JKSNS
-
0x00
111
INTERUPT MASKS
R/W
ICLD
ISLD
IULK
-
-
IJDET
IALCACT
IALCCLP
0x04
113
SYSTEM CLOCK
W
26M
19P2M
13M
12P288M
12M
11P2896M
-
256FS
0x00
114
SAMPLE RATE
W
-
-
SR_96K
SR_32K
SR_48K
SR_44K1
SR_16K
SR_8K
0x00
114
QUICK SETUP REGISTERS
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
DAI INTERFACE
W
-
-
RJ_M
RJ_S
LJ_M
LJ_S
I2S_M
I2S_S
0x00
114
DAC PATH
W
DIG2_HP
DIG2_EAR
DIG2_SPK
DIG2_LOUT
-
-
-
-
0x00
115
MIC/DIRECT TO ADC
W
IN12_MIC1
IN34_MIC2
IN56_MIC1
IN56_MIC2
-
0x00
115
LINE TO ADC
W
IN12S_AB
IN34S_AB
IN56S_AB
IN34D_A
IN56D_B
-
-
-
0x00
115
IN12_
IN12_
IN12_
IN12_
IN34_
IN34_
IN34_
IN34_
M1HPL
M1SPKL
M1EAR
M1LOUTL
M2HPR
M2SPKR
M2EAR
M2LOUTR
0x00
116
IN12S_
IN34D_
IN34D_
IN12S_
IN34S_
IN56D_
IN56D_
IN34S_
ABHP
ASPKL
AEAR
ABLOUT
ABHP
BSPKR
BEAR
ABLOUT
0x00
116
0x00
-
0x00
78
ANALOG MIC LOOP
W
ANALOG LINE LOOP
W
IN12_DADC IN34_DADC IN56_DADC
RESERVED REGISTERS
0x0C
RESERVED
-
ANALOG INPUT CONFIGURATION REGISTERS
0x0D
0x0E
0x0F
0x10
0x11
INPUT CONFIG.
R/W
IN34DIFF
IN56DIFF
LINE INPUT LEVEL
R/W
MIXG135
MIXG246
IN1SEEN
LINE CONFIG.
R/W
EXTBUFA
EXTBUFB
MIC1 INPUT LEVEL
R/W
-
PA1EN[1:0]
MIC2 INPUT LEVEL
R/W
-
PA2EN[1:0]
IN2SEEN
IN3SEEN
IN4SEEN
LINAPGA[2:0]
-
-
IN5SEEN
IN6SEEN
LINBPGA[2:0]
-
0x1B
78
0x00
78
PGAM1[4:0]
0x11
74
PGAM2[4:0]
0x11
74
0x00
75
-
EXTMIC[1:0]
MICROPHONE CONFIGURATION REGISTERS
0x12
0x13
0x14
R/W
-
DIGITAL MIC CONFIG. R/W
MIC BIAS VOLTAGE
-
DIGITAL MIC MODE
-
-
-
MICCLK[2:0]
R/W
DMIC_COMP[3:0]
-
-
-
-
-
-
MBVSEL[1:0]
DIGMICR
DIGMICL
DMIC_FREQ[1:0]
0x00
76
0x00
76
ADC PATH AND CONFIGURATION REGISTERS
0x15
0x16
0x17
0x18
0x19
R/W
MIXADL[7:0]
0x00
80
R/W
MIXADR[7:0]
0x00
80
81
LEFT ADC LEVEL
R/W
-
AVLG[2:0]
AVL[3:0]
0x03
RIGHT ADC LEVEL
R/W
-
AVRG[2:0]
AVR[3:0]
0x03
81
ADC BIQUAD LEVEL
R/W
-
AVBQ[3:0]
0x00
83
ADC SIDETONE
R/W
0x00
82
-
DSTS[1:0]
-
-
-
DVST[4:0]
M
0x1A
LEFT ADC MIXER
RIGHT ADC MIXER
_____________________________________________________________________ 63
MAXIM Confidential
REGISTER DESCRIPTION
ADDR
NAME
MAX98090
REGISTER CONTENTS
R/W
BIT 7
BIT 6
BIT 5
BIT 4
POR
BIT 0
DS
STATE PAGE
BIT 3
BIT 2
BIT 1
-
-
-
-
0x00
88
-
-
-
USE_M1
0x00
88
CLOCK CONFIGURATION REGISTERS
0x1B
SYSTEM CLOCK
R/W
0x1C
CLOCK MODE
R/W
-
-
PSCLK[1:0]
0x1D
ANY CLOCK 1
R/W
0x00
89
0x1E
ANY CLOCK 2
R/W
NI1[7:0]
0x00
89
0x1F
ANY CLOCK 3
R/W
MI1[15:8]
0x00
90
0x20
ANY CLOCK 4
R/W
MI1[7:0]
0x00
90
0x21
MASTER MODE
R/W
0x00
86
FREQ1[3:0]
-
NI1[14:8]
-
-
-
-
BSEL[2:1]
-
-
RJ
WCI
BCI
DLY
-
-
-
-
-
-
0x00
91
-
-
LTEN
LBEN
DMONO
HIZOFF
SDOEN
SDIEN
0x00
84
R/W
MODE
AHPF
DHPF
DHF
-
-
-
-
0x80
85
DAI PLAYBACK LEVEL R/W
DV1M
-
EQ PLAYBACK LEVEL R/W
-
-
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
MAS
INTERFACE CONTROL REGISTERS
0x22
0x23
0x24
0x25
0x26
0x27
0x28
INTERFACE FORMAT R/W
TDM FORMAT 1
R/W
TDM FORMAT 2
R/W
I/O CONFIGURATION R/W
FILTER CONFIG.
SLOTL[1:0]
SLOTR[1:0]
TDM
SLOTDLY[3:0]
DV1G[1:0]
-
WS[1:0]
FSW
/EQCLP\
0x00
87
0x00
91
DV1[3:0]
0x00
92
DVEQ[3:0]
0x00
94
HEADPHONE (HP) CONTROL REGISTERS
0x29
0x2A
0x2B
0x2C
0x2D
LEFT HP MIXER
R/W
-
-
MIXHPL[5:0]
0x00
102
RIGHT HP MIXER
R/W
-
-
MIXHPR[5:0]
0x00
102
HP CONTROL
R/W
-
-
0x00
103
LEFT HP VOLUME
R/W
HPLM
-
-
HPVOLL[4:0]
0x1A
103
RIGHT HP VOLUME
R/W
HPRM
-
-
HPVOLR[4:0]
0x1A
104
100
MIXHPRSEL MIXHPLSEL
MIXHPRG[1:0]
MIXHPLG[1:0]
SPEAKER (SPK) CONFIGURATION REGISTERS
0x2E
0x2F
0x30
0x31
0x32
LEFT SPK MIXER
R/W
-
-
MIXSPL[5:0]
0x00
RIGHT SPK MIXER
R/W
-
SPK_SLAVE
MIXSPR[5:0]
0x00
100
SPK CONTROL
R/W
-
-
0x00
101
LEFT SPK VOLUME
R/W
SPLM
-
SPVOLL[5:0]
0x2C
101
RIGHT SPK VOLUME
R/W
SPRM
-
SPVOLR[5:0]
0x2C
101
0x00
92
-
MIXSPRG[1:0]
MIXSPLG[1:0]
AUTOMATIC LEVEL CONTROL (ALC) CONFIGURATION REGISTERS
0x33
0x34
0x35
0x36
ALC TIMING
R/W
ALC COMPRESSOR
R/W
ALCEN
ALCCMP[2:0]
ALCTHC[4:0]
0x00
93
ALC EXPANDER
R/W
ALCEXP[2:0]
ALCTHE[4:0]
0x00
93
ALC GAIN
R/W
ALCG[4:0]
0x00
93
-
ALCRLS[2:0]
-
-
-
ALCATK[2:0]
RECEIVER (RCV OR EARPIECE) AND LINE OUTPUT (LOUT) REGISTERS
0x37
RCV/LOUTL MIXER
R/W
0x38 RCV/LOUTL CONTROL R/W
0x39
0x3A
0x3B
-
MIXRCVL[5:0]
-
-
-
RCVLM
-
-
LINMOD
-
LOUTR MIXER
R/W
LOUTR CONTROL
R/W
-
-
-
LOUTR VOLUME
R/W
RCVRM
-
-
-
-
-
0x00 97, 106
MIXRCVLG[1:0]
RCVLVOL[4:0]
0x15 98, 107
MIXRCVR[5:0]
-
-
-
RCVRVOL[4:0]
0x00 97, 106
MIXRCVRG[1:0]
0x00
107
0x00
107
0x15
108
M
0x3C
RCV/LOUTL VOLUME R/W
-
_____________________________________________________________________ 64
MAXIM Confidential
REGISTER DESCRIPTION
ADDR
NAME
MAX98090
REGISTER CONTENTS
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
POR
BIT 2
BIT 1
BIT 0
DS
STATE PAGE
JACK DETECT AND ENABLE REGISTERS
0x3D
JACK DETECT
R/W
JDETEN
JDWK
-
-
-
-
0x3E
INPUT ENABLE
R/W
-
-
-
MBEN
LINEAEN
LINEBEN
0x3F
OUTPUT ENABLE
R/W
HPREN
HPLEN
SPREN
SPLEN
RCVLEN
0x40
LEVEL CONTROL
R/W
-
-
-
-
-
DSP FILTER ENABLE R/W
-
-
-
-
0x41
JDEB[1:0]
0x00
111
0x00
71
ADREN
ADLEN
RCVREN
DAREN
DALEN
0x00
71
/ZDEN\
/VS2EN\
/VSEN\
0x00
109
0x00
94
ADCBQEN EQ3BANDEN EQ5BANDEN EQ7BANDEN
BIAS AND POWER MODE CONFIGURATION REGISTERS
0x43
0x44
0x45
BIAS CONTROL
R/W
-
-
-
-
-
-
-
VCM_MODE
0x00
69
DAC CONTROL
R/W
-
-
-
-
-
-
PERFMODE
DACHP
0x00
69
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
0x42
ADC CONTROL
R/W
-
-
-
-
-
OSR128
ADCDITHER
ADCHP
0x06
70
DEVICE SHUTDOWN
R/W
/SHDN\
-
-
-
-
-
-
-
0x00
70
DAI PARAMETRIC EQUALIZER BAND 1: BIQUAD FILTER COEFFICIENT REGISTERS
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
EQUALIZER BAND 1
COEFFICIENT B0
EQUALIZER BAND 1
COEFFICIENT B1
EQUALIZER BAND 1
COEFFICIENT B2
EQUALIZER BAND 1
COEFFICIENT A1
EQUALIZER BAND 1
COEFFICIENT A2
R/W
B0_1[23:16]
0x00
R/W
B0_1[15:8]
0x00
R/W
B0_1[7:0]
0x00
R/W
B1_1[23:16]
0x00
R/W
B1_1[15:8]
0x00
R/W
B1_1[7:0]
0x00
R/W
B2_1[23:16]
0x00
R/W
B2_1[15:8]
0x00
R/W
B2_1[7:0]
0x00
R/W
A1_1[23:16]
0x00
R/W
A1_1[15:8]
0x00
R/W
A1_1[7:0]
0x00
R/W
A2_1[23:16]
0x00
R/W
A2_1[15:8]
0x00
R/W
A2_1[7:0]
0x00
R/W
B0_2[23:16]
0x00
R/W
B0_2[15:8]
0x00
95
DAI PARAMETRIC EQUALIZER BAND 2: BIQUAD FILTER COEFFICIENT REGISTERS
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
COEFFICIENT B0
EQUALIZER BAND 2
COEFFICIENT B1
EQUALIZER BAND 2
COEFFICIENT B2
EQUALIZER BAND 2
COEFFICIENT A1
EQUALIZER BAND 2
M
0x61
EQUALIZER BAND 2
0x62
0x63
COEFFICIENT A2
R/W
B0_2[7:0]
0x00
R/W
B1_2[23:16]
0x00
R/W
B1_2[15:8]
0x00
R/W
B1_2[7:0]
0x00
R/W
B2_2[23:16]
0x00
R/W
B2_2[15:8]
0x00
R/W
B2_2[7:0]
0x00
R/W
A1_2[23:16]
0x00
R/W
A1_2[15:8]
0x00
R/W
A1_2[7:0]
0x00
R/W
A2_2[23:16]
0x00
R/W
A2_2[15:8]
0x00
R/W
A2_2[7:0]
0x00
_____________________________________________________________________ 65
95
MAXIM Confidential
REGISTER DESCRIPTION
ADDR
NAME
MAX98090
REGISTER CONTENTS
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
POR
BIT 2
BIT 1
BIT 0
DS
STATE PAGE
DAI PARAMETRIC EQUALIZER BAND 3: BIQUAD FILTER COEFFICIENT REGISTERS
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
EQUALIZER BAND 3
COEFFICIENT B0
EQUALIZER BAND 3
COEFFICIENT B1
R/W
B0_3[23:16]
0x00
R/W
B0_3[15:8]
0x00
R/W
B0_3[7:0]
0x00
R/W
B1_3[23:16]
0x00
R/W
B1_3[15:8]
0x00
R/W
B1_3[7:0]
0x00
R/W
B2_3[23:16]
0x00
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
0x64
EQUALIZER BAND 3
COEFFICIENT B2
EQUALIZER BAND 3
COEFFICIENT A1
EQUALIZER BAND 3
COEFFICIENT A2
R/W
B2_3[15:8]
0x00
R/W
B2_3[7:0]
0x00
R/W
A1_3[23:16]
0x00
R/W
A1_3[15:8]
0x00
R/W
A1_3[7:0]
0x00
R/W
A2_3[23:16]
0x00
R/W
A2_3[15:8]
0x00
R/W
A2_3[7:0]
0x00
R/W
B0_4[23:16]
0x00
R/W
B0_4[15:8]
0x00
R/W
B0_4[7:0]
0x00
R/W
B1_4[23:16]
0x00
R/W
B1_4[15:8]
0x00
R/W
B1_4[7:0]
0x00
95
DAI PARAMETRIC EQUALIZER BAND 4: BIQUAD FILTER COEFFICIENT REGISTERS
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
COEFFICIENT B0
EQUALIZER BAND 4
COEFFICIENT B1
EQUALIZER BAND 4
COEFFICIENT B2
EQUALIZER BAND 4
COEFFICIENT A1
EQUALIZER BAND 4
COEFFICIENT A2
R/W
B2_4[23:16]
0x00
R/W
B2_4[15:8]
0x00
R/W
B2_4[7:0]
0x00
R/W
A1_4[23:16]
0x00
R/W
A1_4[15:8]
0x00
R/W
A1_4[7:0]
0x00
R/W
A2_4[23:16]
0x00
R/W
A2_4[15:8]
0x00
R/W
A2_4[7:0]
0x00
M
0x81
EQUALIZER BAND 4
_____________________________________________________________________ 66
95
MAXIM Confidential
REGISTER DESCRIPTION
ADDR
NAME
MAX98090
REGISTER CONTENTS
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
POR
BIT 2
BIT 1
BIT 0
DS
STATE PAGE
DAI PARAMETRIC EQUALIZER BAND 5: BIQUAD FILTER COEFFICIENT REGISTERS
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
EQUALIZER BAND 5
COEFFICIENT B0
EQUALIZER BAND 5
COEFFICIENT B1
R/W
B0_5[23:16]
0x00
R/W
B0_5[15:8]
0x00
R/W
B0_5[7:0]
0x00
R/W
B1_5[23:16]
0x00
R/W
B1_5[15:8]
0x00
R/W
B1_5[7:0]
0x00
R/W
B2_5[23:16]
0x00
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
0x82
EQUALIZER BAND 5
COEFFICIENT B2
EQUALIZER BAND 5
COEFFICIENT A1
EQUALIZER BAND 5
COEFFICIENT A2
R/W
B2_5[15:8]
0x00
R/W
B2_5[7:0]
0x00
R/W
A1_5[23:16]
0x00
R/W
A1_5[15:8]
0x00
R/W
A1_5[7:0]
0x00
R/W
A2_5[23:16]
0x00
R/W
A2_5[15:8]
0x00
R/W
A2_5[7:0]
0x00
R/W
B0_6[23:16]
0x00
R/W
B0_6[15:8]
0x00
R/W
B0_6[7:0]
0x00
R/W
B1_6[23:16]
0x00
R/W
B1_6[15:8]
0x00
R/W
B1_6[7:0]
0x00
95
DAI PARAMETRIC EQUALIZER BAND 6: BIQUAD FILTER COEFFICIENT REGISTERS
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
COEFFICIENT B0
EQUALIZER BAND 6
COEFFICIENT B1
EQUALIZER BAND 6
COEFFICIENT B2
EQUALIZER BAND 6
COEFFICIENT A1
EQUALIZER BAND 6
COEFFICIENT A2
R/W
B2_6[23:16]
0x00
R/W
B2_6[15:8]
0x00
R/W
B2_6[7:0]
0x00
R/W
A1_6[23:16]
0x00
R/W
A1_6[15:8]
0x00
R/W
A1_6[7:0]
0x00
R/W
A2_6[23:16]
0x00
R/W
A2_6[15:8]
0x00
R/W
A2_6[7:0]
0x00
M
0x9F
EQUALIZER BAND 6
_____________________________________________________________________ 67
95
MAXIM Confidential
REGISTER DESCRIPTION
ADDR
NAME
MAX98090
REGISTER CONTENTS
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
POR
BIT 2
BIT 1
BIT 0
DS
STATE PAGE
DAI PARAMETRIC EQUALIZER BAND 7: BIQUAD FILTER COEFFICIENT REGISTERS
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
EQUALIZER BAND 7
COEFFICIENT B0
EQUALIZER BAND 7
COEFFICIENT B1
R/W
B0_7[23:16]
0x00
R/W
B0_7[15:8]
0x00
R/W
B0_7[7:0]
0x00
R/W
B1_7[23:16]
0x00
R/W
B1_7[15:8]
0x00
R/W
B1_7[7:0]
0x00
R/W
B2_7[23:16]
0x00
R/W
B2_7[15:8]
0x00
R/W
B2_7[7:0]
0x00
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
0xA0
EQUALIZER BAND 7
COEFFICIENT B2
EQUALIZER BAND 7
COEFFICIENT A1
EQUALIZER BAND 7
COEFFICIENT A2
R/W
A1_7[23:16]
0x00
R/W
A1_7[15:8]
0x00
R/W
A1_7[7:0]
0x00
R/W
A2_7[23:16]
0x00
R/W
A2_7[15:8]
0x00
R/W
A2_7[7:0]
0x00
R/W
ADC_B0[23:16]
0x00
R/W
ADC_B0[15:8]
0x00
R/W
ADC_B0[7:0]
0x00
R/W
ADC_B1[23:16]
0x00
R/W
ADC_B1[15:8]
0x00
R/W
ADC_B1[7:0]
0x00
95
ADC BIQUAD FILTER COEFFICIENT REGISTERS
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
ADC BIQUAD
COEFFICIENT B0
ADC BIQUAD
COEFFICIENT B1
ADC BIQUAD
COEFFICIENT B2
ADC BIQUAD
COEFFICIENT A1
ADC BIQUAD
COEFFICIENT A2
R/W
ADC_B2[23:16]
0x00
R/W
ADC_B2[15:8]
0x00
R/W
ADC_B2[7:0]
0x00
R/W
ADC_A1[23:16]
0x00
R/W
ADC_A1[15:8]
0x00
R/W
ADC_A1[7:0]
0x00
R/W
ADC_A2[23:16]
0x00
R/W
ADC_A2[15:8]
0x00
R/W
ADC_A2[7:0]
0x00
R
REVID[7:0]
0x42
83
REVISION ID REGISTER
REVISION ID
M
0xFF
_____________________________________________________________________ 68
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MAXIM Confidential
MAX98090
Power and Performance Management
The device includes comprehensive power management to allow the disabling of unused blocks to minimize
supply current. In addition to this, the available power modes provide a software configurable choice between
optimized performance and reduced power consumption.
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
Device Performance Configuration
The Common Mode Bias Register (Table 2) selects the method used to derive the common mode reference
voltage. A common mode bias created by resistive division (from the AVDD supply) facilitates lower overall
power consumption (disables the bandgap reference circuit). However, this type of VCM reference has the
disadvantage of scaling with the AVDD supply voltage (and thus also has reduced PSRR). When derived from a
bandgap reference, VCM is constant regardless of the supply voltage but the additional circuitry does increase
power consumption.
The ADC, DAC, and headphone playback all have optional high performance modes (Table 3 / Table 4). In each
case, these modes trade additional power consumption for enhanced performance. The ADC also has optional
dither (recommended for the cleanest spectrum), and can be configured to two different oversampling rates (see
section TBD for additional details on ADC operation)
Table 2: Common Mode Bias Register
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x42
NAME
TYPE PoR
-
VCM_MODE
R/W
0
DESCRIPTION
-
Select source for VCM.
0 : VCM derived from resistive division selected (default)
1 : VCM created by bandgap reference selected
Table 3: Output Power and Performance Mode Register
BIT
7
6
5
4
3
2
1
PERFMODE
R/W
0
DACHP
R/W
0
M
0
ADDRESS: 0x43
NAME
TYPE PoR
-
DESCRIPTION
-
Performance Mode
Selects DAC to headphone playback performance mode.
1 : Low power playback mode.
0 : High performance playback mode.
DAC High Performance Mode
0 : DAC settings optimized for lowest power consumption
1 : DAC settings optimized for best performance
_____________________________________________________________________ 69
MAXIM Confidential
MAX98090
Table 4: Input Power and Performance Mode Register
2
1
0
DESCRIPTION
ADC Oversampling Rate
0 : ADCCLK = 64*fS
1 : ADCCLK = 128*fS (default)
ADC Quantizer Dither
0 : Dither disabled
1 : Dither enabled
ADC High Performance Mode
0 : ADC is optimized for low power operation
1 : ADC is optimized for best performance
AX P
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EN
TI
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BIT
7
6
5
4
3
ADDRESS: 0x45
NAME
TYPE PoR
OSR128
R/W
0
ADCDITHER
R/W
0
ADCHP
R/W
0
Device Enable Configuration
In addition to a device global shutdown control, the major input and output blocks can be independently enabled
(or disabled) to optimize power consumption. The device global shutdown control is detailed in Table 5. Table 6
details the available input signal path enables (with the exception of the analog microphone inputs 1/2, which
are enabled from registers 0x10 and 0x11, or Table 8 and Table 9 respectively). Table 7 details the available
output signal path enables.
When the device is in global shutdown, the major input and output blocks are all disabled to conserve power.
However, the I2C interface remains active and all device registers can be configured. Certain registers should
only be programmed while in shutdown (detailed in Table 79). Changing these registers when the device is
active could result in unexpected behavior. For optimal, minimized power consumption, only enable the stage
blocks that are part of the intended signal path configuration.
Table 5: Device Global Shutdown Register
BIT
7
6
5
4
3
2
1
/SHDN\
R/W
0
DESCRIPTION
Device Active-low Global Shutdown Control
0 : Device is in shutdown.
1 : Device is active. Certain registers should not be written to while the device is
active ().
M
0
ADDRESS: 0x45
NAME
TYPE PoR
-
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Table 6: Input Enable Register
BIT
7
6
5
3
2
1
0
MBEN
R/W
0
DESCRIPTION
Microphone Bias Enable
0 : Disable Microphone Bias
1 : Enable Microphone Bias
Enables Line A Analog Input Block
0 : Line A Input amplifier disabled
1 : Line A Input amplifier enabled
Enables Line A Analog Input Block
0 : Line B Input amplifier disabled
1 : Line B Input amplifier enabled
Right ADC Enable
0 : Right ADC disabled
1 : Right ADC enabled
Left ADC Enable
0 : Left ADC disabled
1 : Left ADC enabled
AX P
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N NA
FI
D RY
EN
TI
AL
4
ADDRESS: 0x3E
NAME
TYPE PoR
-
LINEAEN
R/W
0
LINEBEN
R/W
0
ADREN
R/W
0
ADLEN
R/W
0
Table 7: Output Enable Register
BIT
7
6
5
4
3
2
HPREN
R/W
0
HPLEN
R/W
0
SPREN
R/W
0
SPLEN
R/W
0
RCVLEN
R/W
0
RCVREN
R/W
0
DAREN
R/W
0
R/W
0
M
1
ADDRESS: 0x3F
NAME
TYPE PoR
0
DALEN
DESCRIPTION
Right Headphone Output Enable
0 : Disable Right Headphone Output
1 : Enable Right Headphone Output
Left Headphone Output Enable
0 : Disable Left Headphone Output
1 : Enable Left Headphone Output
Right Class-D Speaker Output Enable
0 : Disable Right Speaker Output
1 : Enable Right Speaker Output
Left Class-D Speaker Output Enable
0 : Disable Left Speaker Output
1 : Enable Left Speaker Output
Receiver (Earpiece) / Line Out Left Output Enable
0 : Disable Receiver / Left Line Output
1 : Enable Receiver / Left Line Output
Right Line Output Enable
0 : Disable Right Line Output
1 : Enable Right Line Output
Right DAC Digital Input Enable
0 : Disable Right DAC Input
1 : Enable Right DAC Input
Left DAC Digital Input Enable
0 : Disable Left DAC Input
1 : Enable Left DAC Input
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Analog Audio Input Configuration
The device features either six (WLP package) or four (TQFN package) flexible analog inputs. Each pair can be
configured as either an analog microphone input, a single ended or differential line input(s), or as a reduced
power, full-scale differential analog input direct to the ADC mixer. The analog microphone and line inputs can
either be routed to the stereo ADC mixer for recording or directly to any analog output mixer for playback.
MBEN
MBVSEL[1:0]
FLEXSOUND
TECHNOLOGY
DSP
MICCLK[1:0]
DIGMICL
MICBIAS
DIGITAL
MIC. CLOCK
CONTROL
DIGITAL
MIC DATA
LEFT MUX
DIGITAL
MIC DATA
RIGHT MUX
AX P
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N NA
FI
D RY
EN
TI
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MICROPHONE BIAS
GENERATOR
DIGMICR
DMDL
MIXG135
IN5
LINE A
INPUT
MIXER
DMDR
ADC
LEFT
IN1
IN3
ADCL
ADCR
LINAPGA[2:0]
-6dB / 0dB
-6dB to 20dB
ADC
RIGHT
LINE A
PGA
IN3-IN4
ADLEN
ADCHP
OSR128
ADCDITHER
ADREN
IN1-IN2
IN1SEEN
IN3SEEN
IN5SEEN
IN34DIFF
IN1 / DMD
IN3-IN4
LINEAEN
EXTBUFA
IN5-IN6
MIC 1
IN2 / DMC
MIC 2
PA1EN[1:0]
PGAM1[4:0]
EXTMIC[0]
ADC
LEFT
MIXER
LINE A
MIXADL[7:0]
LINE B
IN1-IN2
IN5-IN6
0dB to 50dB
MIC 1
INPUT
MUX
MIC 1
PGA
IN1-IN2
IN3-IN4
ZDENB
IN3
MIXADR[7:0]
IN5-IN6
IN4
MIC 1
ZDENB
IN3-IN4
IN5-IN6
MIC 2
0dB to 50dB
MIC 2
INPUT
MUX
MIC 2
PGA
ADC
RIGHT
MIXER
LINE A
LINE B
PA2EN[1:0]
PGAM2[4:0]
EXTMIC[1]
IN5
IN6
IN2SEEN
IN4SEEN
IN6SEEN
IN56DIFF
WLP ONLY
ANALOG
OUTPUT
MIXERS
LINEAEN
EXTBUFA
IN2
IN4
IN6
LINE B
INPUT
MIXER
-6dB / 0dB
-6dB to 20dB
LINE B
PGA
M
IN6-IN5
MIXG246
LINAPGA[2:0]
Figure 6: Analog Audio Input Functional Diagram
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M
AX P
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N NA
FI
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EN
TI
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Analog Microphone Inputs
The device includes three differential microphone inputs (three for the WLP package and two for the TQFN
package) and a programmable, low-noise microphone bias for powering a wide variety of external microphones
(Figure 7). By default, analog inputs IN1 and IN2 differentially (IN1 – IN2) provide the input to microphone
amplifier 1, while IN3 and IN4 differentially (IN3 – IN4) form the input to microphone amplifier 2. For the WLP
package, the additional analog input pair IN5 and IN6 can be configured as a differential input (IN5 – IN6) to
either microphone amplifier 1 or 2 (Table 15).
In the typical application, one microphone input is used for the handset microphone and the other is used as an
accessory microphone (IN1/IN2 and IN3/IN4). In systems using a background noise microphone, IN5/IN6 (WLP
only) can be retasked as another microphone input.
Analog microphone input signals are amplified by two stages of programmable gain amplifiers, and then routed
to either the ADC mixer (record) or analog outputs (playback). The first, a coarse gain stage, includes the
analog microphone enable, and offers selectable 0dB, 20dB, or 30dB gain settings. The second, a fine gain
stage, is a programmable-gain amplifier (PGA) adjustable from 0dB to 20dB in 1dB steps (Table 8 and Table 9).
Together, the two stages provide up to 50dB of signal gain for the analog microphone inputs. To maximize the
signal-to-noise ratio, use the coarse gain settings of the first stage whenever possible. Zero-crossing detection
is included on the PGA to minimize zipper noise while making gain changes.
Figure 7: Analog Microphone Input Functional Diagram
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Table 8: Microphone 1 Enable and Level Configuration Register
BIT
7
6
ADDRESS: 0x10
NAME
TYPE PoR
PA1EN[1:0]
5
R/W
3
2
1
0
-
0
Microphone 1 Input Amplifier Enable and Coarse Gain Setting
00 : Disabled
10 : 20dB
01 : 0dB
11 : 30dB
1
Microphone 1 Programmable Gain Amplifier Fine Adjust Configuration
0
0x1F : 0dB
⋮
0x14 : 0dB
0x13 : 1dB
0x12 : 2dB
0x11 : 3dB
0x10 : 4dB
0x0F : 5dB
0x0E : 6dB
0x0D : 7dB
0x0C : 8dB
0x0B : 9dB
0x0A : 10dB
0x09 : 11dB
0x08 : 12dB
0x07 : 13dB
0x06 : 14dB
0x05 : 15dB
0x04 : 16dB
0x03 : 17dB
0x02 : 18dB
0x01 : 19dB
0x00 : 20dB
AX P
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N NA
FI
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EN
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4
DESCRIPTION
0
PGAM1[4:0]
R/W
0
0
1
Table 9: Microphone 2 Enable and Level Configuration Register
BIT
7
6
5
4
3
2
1
PA2EN[1:0]
R/W
0
Microphone 2 Input Amplifier Enable and Coarse Gain Setting
00 : Disabled
10 : 20dB
01 : 0dB
11 : 30dB
1
Microphone 2 Programmable Gain Amplifier Fine Adjust Configuration
0
0
PGAM2[4:0]
R/W
DESCRIPTION
0
0
1
0x1F : 0dB
⋮
0x14 : 0dB
0x13 : 1dB
0x12 : 2dB
0x11 : 3dB
0x10 : 4dB
0x0F : 5dB
0x0E : 6dB
0x0D : 7dB
0x0C : 8dB
0x0B : 9dB
0x0A : 10dB
0x09 : 11dB
0x08 : 12dB
0x07 : 13dB
0x06 : 14dB
0x05 : 15dB
0x04 : 16dB
0x03 : 17dB
0x02 : 18dB
0x01 : 19dB
0x00 : 20dB
M
0
ADDRESS: 0x11
NAME
TYPE PoR
-
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Analog Microphone Bias
The device features a low noise microphone bias output (MICBIAS) that can be configured to power a wide
range of external microphone devices. The microphone bias can be set by the software to any one of 4 voltages
(2.2V, 2.4V, 2.55V, or 2.8V) by programming the Microphone Bias Level Configuration Register (Table 10).
Table 10: Microphone Bias Level Configuration Register
1
0
DESCRIPTION
-
AX P
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C IM
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N NA
FI
D RY
EN
TI
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BIT
7
6
5
4
3
2
ADDRESS: 0x12
NAME
TYPE PoR
-
MBVSEL[1:0]
R/W
0
0
Microphone Bias Level Configuration
00 : 2.2V
10 :
01 : 2.4V
11 :
2.55V
2.8V
Digital Microphone Inputs
One microphone input, IN1/IN2, can also be configured as a digital microphone input accepting signals from two
different digital microphones (Figure 8). Any two microphones, either analog or digital, can be recorded from
simultaneously. Digital microphone left and right are routed through the left and right record path DSP to the
DAI. The appropriate channel record path DSP is automatically switched to either of the digital microphones
when they are enabled (DIGIMICR and DIGIMICL, Error! Reference source not found.).
IN2 / DMC
DIGITAL
MIC. CLOCK
CONTROL
MICCLK[1:0]
DIGMICL
DMDL
IN1 / DMD
IN3
IN4
ADC
LEFT
MIXER
ADC
LEFT
MICBIAS
IN5
IN6
M
WLP ONLY
ADCL
DIGITAL
MIC DATA
LEFT MUX
FLEXSOUND
TECHNOLOGY
DSP
DMDR
ADC
RIGHT
MIXER
ADC
RIGHT
ADCR
LEFT
RECORD
PATH DSP
DIGITAL
MIC DATA
RIGHT MUX
DAI
RIGHT
RECORD
PATH DSP
DIGMICR
Figure 8: Digital Microphone Input Functional Diagram
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To avoid any potential clipping and minimize potential distortion, always enable the record path DC blocking
filters to remove any DC offsets (AHPF, Table 25). The record path biquad filter, and digital gain and level
control can also optionally be applied to digital microphone inputs.
The digital microphone clock rate can be configured to any one of 4 settings using MICCLK[1:0] (Error!
Reference source not found.). The digital microphone clock can be derived either from a PCLK divider or a
sample rater multiplier. If MICCLK is set to 1x and PCLK is not an integer multiple of the sample rate then the
generated clock will potentially be jittered.
Table 11: Digital Microphone 1
6
5
4
3
2
1
0
DESCRIPTION
AX P
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FI
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EN
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BIT
7
ADDRESS: 0x13
NAME
TYPE PoR
0
MICCLK[2:0]
R/W
0
0
-
-
-
DIGMICR
R/W
0
DIGMICL
R/W
0
Digital Microphone Clock Rate Configuration
000 : fDIGMICCLK = PCLK / 2
100 : fDIGMICCLK = PCLK / 6
001 : fDIGMICCLK = PCLK / 3
101 : fDIGMICCLK = PCLK / 8
010 : fDIGMICCLK = PCLK / 4
110 : fDIGMICCLK = PCLK / 10
011 : fDIGMICCLK = PCLK / 5
111 : RESERVED
Digital Microphone Right Channel Enable
0 : Right record channel uses on-chip ADC
1 : Right record channel uses digital microphone input
Digital Microphone Left Channel Enable
0 : Left record channel uses on-chip ADC
1 : Left record channel uses digital microphone input
Table 12: Digital Microphone 2
BIT
7
6
5
4
3
2
1
ADDRESS: 0x14
NAME
TYPE PoR
0
0
DMIC_COMP[3:0]
R/W
0
0
R/W
0
R/W
0
DMIC_FREQ[1:0]
Digital Microphone Compensation Filter Configuration
0000 - 1111 : TBD
If the system clock and sample rate bits in register 0x04 / 0x05 are set, then the
compensation filter configuration is automatically decoded.
Digital Microphone Frequency Range Configuration
00 : fDIGMICCLK < 3.5MHz
10 : 4.5MHz ≤ fDIGMICCLK
01 : 3.5MHz ≤ fDIGMICCLK < 4.5MHz
11 : Reserved
If any of the system clock bits in register 0x04 are set, then the frequency range
configuration is automatically decoded.
M
0
DESCRIPTION
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Analog Line Inputs
The device includes two sets of line inputs (Figure 9). The line inputs can be configured as stereo single-ended
inputs, stereo differential inputs, or multiple mixed single ended inputs. To allow the line inputs to match a wide
range of input signal levels, each line input includes a coarse programmable gain amplifier (PGA) that can
provide up to 6dB of attenuation or 20dB of signal gain. After the PGAs, the line inputs are then routed to either
the ADC mixer (record) or analog outputs (playback).
If the line input requires a custom gain level, the external gain mode provides a trimmed feedback resistor. The
line input gain is then set by using the following formula to calculate the appropriate series input resistor:
AX P
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C IM
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N NA
FI
D RY
EN
TI
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AVPGAIN = 20 x log (20kΩ/RIN)
M
In addition to custom gain levels, the external gain mode allows the line input PGAs to be reconfigured into a
variety of different amplifier topologies. It allows for the summing of multiple signals into a single input by
connecting multiple input resistors in a summing topology as shown in Figure TBD. It also allows the line inputs
to accept analog input signals larger than 1VRMS by creating a voltage divider and adjusting the ratio of the
series input resistor to the internal feedback resistor to less than 1 (20kΩ/RIN < 1).
Figure 9: Analog Line Input Functional Diagram
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Table 13: Line Input Mixer Configuration Register
DESCRIPTION
Selects IN3-IN4 Differentially as an Input to the Line A Mixer
Selects IN6-IN5 Differentially as an Input to the Line B Mixer (WLP Only)
Selects IN1 Single Ended as an Input to the Line A Mixer
Selects IN2 Single Ended as an Input to the Line B Mixer
Selects IN3 Single Ended as an Input to the Line A Mixer
Selects IN4 Single Ended as an Input to the Line B Mixer
Selects IN5 Single Ended as an Input to the Line A Mixer (WLP Only)
Selects IN6 Single Ended as an Input to the Line B Mixer (WLP Only)
AX P
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IM E
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C IM
O I
N NA
FI
D RY
EN
TI
AL
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x0D
NAME
TYPE PoR
IN34DIFF
R/W
0
IN56DIFF
R/W
0
IN1SEEN
R/W
0
IN2SEEN
R/W
0
IN3SEEN
R/W
0
IN4SEEN
R/W
0
IN5SEEN
R/W
0
IN6SEEN
R/W
0
Table 14: Line Input Level Configuration Register
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x0E
NAME
TYPE PoR
MIXG135
R/W
0
MIXG246
R/W
0
LINAPGA[2:0]
R/W
LINBPGA[2:0]
R/W
0
1
1
0
1
1
DESCRIPTION
Enable for a -6dB Reduction for Multiple Single Ended Line A Mixer Inputs
0 : Normal Line A Mixer Operation
1 : Gain is Reduced by -6dB when Multiple Single Ended Inputs are selected
Enable for a -6dB Reduction for Multiple Single Ended Line B Mixer Inputs
0 : Normal Line B Mixer Operation
1 : Gain is Reduced by -6dB when Multiple Single Ended Inputs are selected
Line Input A Programmable Internal Preamp Gain Configuration
000 : 20dB
001 : 14dB
010 : 3dB
011 : 0dB
100 : -3dB
101, 110, 111 : -6dB
Line Input B Programmable Internal Preamp Gain Configuration
000 : 20dB
001 : 14dB
010 : 3dB
011 : 0dB
100 : -3dB
101, 110, 111 : -6dB
Table 15: Line Input Mode and Source Configuration Register
BIT
7
6
5
4
3
2
1
EXTMIC[1:0]
M
0
ADDRESS: 0x0F
NAME
TYPE PoR
EXTBUFA
R/W
0
EXTBUFB
R/W
0
R/W
0
0
DESCRIPTION
Selects External Resistor Gain Mode for Line Input A
Selects External Resistor Gain Mode for Line Input B
External Microphone (IN6–IN5) Input Control Configuration (WLP Only)
00 : EXT_MIC not selected
10 : EXT_MIC selected on MIC 2
01 : EXT_MIC selected on MIC 1
11 : EXT_MIC not selected
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AX P
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FI
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EN
TI
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Analog Full-Scale Direct to ADC Mixer Inputs
The analog inputs can also be configured to accept and route differential analog signals directly to the ADC
mixers (record, Figure 10). By disabling and bypassing the analog microphone and line input gain stages, this
mode provides a reduced power configuration for full-scale (up to 1VRMS) analog input signals. Unlike the analog
microphone and line input configurations, this mode does not allow the input signals to be routed directly to the
analog output mixers (playback).
Figure 10: Analog Direct to ADC Mixer Input Functional Diagram
M
Analog Input to Analog Output Loopback
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Analog to Digital Converter (ADC) Configuration
ADC Input Mixer Configuration
Table 16: Left ADC Mixer Input Configuration Register
ADDRESS: 0x15
NAME
TYPE PoR
R/W
0
R/W
0
R/W
0
MIXADL[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
-
DESCRIPTION
Select IN1-IN2 Differential Input Direct to Left ADC Mixer
Select IN3-IN4 Differential Input Direct to Left ADC Mixer
Select IN6-IN5 Differential Input Direct to Left ADC Mixer (WLP Only)
Select Line Input A to Left ADC Mixer
Select Line Input B to Left ADC Mixer
Select Microphone Input 1 to Left ADC Mixer
Select Microphone Input 2 to Left ADC Mixer
-
AX P
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IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
BIT
7
6
5
4
3
2
1
0
Table 17: Right ADC Mixer Input Configuration Register
DESCRIPTION
Select IN1-IN2 Differential Input Direct to Right ADC Mixer
Select IN3-IN4 Differential Input Direct to Right ADC Mixer
Select IN6-IN5 Differential Input Direct to Right ADC Mixer (WLP Only)
Select Line Input A to Right ADC Mixer
Select Line Input B to Right ADC Mixer
Select Microphone Input 1 to Right ADC Mixer
Select Microphone Input 2 to Right ADC Mixer
-
M
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x16
NAME
TYPE PoR
R/W
0
R/W
0
R/W
0
MIXADR[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
-
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ADC Output Digital Gain
The IC includes separate digital level control for the left and right ADC outputs (Figure 13). To optimize dynamic
range, use analog gain to adjust the signal level and set the digital level control to 0dB whenever possible. Digital level
control is primarily used when adjusting the record level for digital microphones.
Table 18: Left ADC Digital Level Configuration Register
3
2
1
0
DESCRIPTION
-
AX P
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L
C IM
O I
N NA
FI
D RY
EN
TI
AL
BIT
7
6
5
4
ADDRESS: 0x17
NAME
TYPE PoR
0
AVLG[2:0]
R/W
0
0
0
AVL[3:0]
R/W
0
1
1
Left ADC Digital Coarse Gain Configuration
000 : 0dB
010 : +12dB
100 : +24dB
001 : +6dB
011 : +18dB
101 : +30dB
110 : +36dB
111 : +42dB
Left ADC Digital Fine Adjust Gain Configuration
0x0 : +3dB
0x1 : +2dB
0x2 : +1dB
0x3 : +0dB
0x8 : -5dB
0x9 : -6dB
0xA : -7dB
0xB : -8dB
0x4 : -1dB
0x5 : -2dB
0x6 : -3dB
0x7 : -4dB
0xC : -9dB
0xD : -10dB
0xE : -11dB
0xF : -12dB
Table 19: Right ADC Digital Level Configuration Register
BIT
7
6
5
4
3
2
1
0
AVR[3:0]
R/W
0
1
1
DESCRIPTION
-
Right ADC Digital Coarse Gain Configuration
000 : 0dB
010 : +12dB
100 : +24dB
001 : +6dB
011 : +18dB
101 : +30dB
110 : +36dB
111 : +42dB
Right ADC Digital Fine Adjust Gain Configuration
0x0 : +3dB
0x1 : +2dB
0x2 : +1dB
0x3 : +0dB
0x4 : -1dB
0x5 : -2dB
0x6 : -3dB
0x7 : -4dB
0x8 : -5dB
0x9 : -6dB
0xA : -7dB
0xB : -8dB
0xC : -9dB
0xD : -10dB
0xE : -11dB
0xF : -12dB
M
0
ADDRESS: 0x18
NAME
TYPE PoR
0
AVRG[2:0]
R/W
0
0
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ADC Output Sidetone
Enable sidetone during full-duplex operation to add a low-level copy of the recorded audio signal to the playback
audio signal (Figure 14). Sidetone is commonly used in telephony to allow the speaker to hear himself speak,
providing a more natural user experience. The IC implements sidetone digitally. Doing so helps prevent unwanted
feedback into the playback signal path and better matches the playback audio signal.
Table 20: ADC Sidetone Configuration Register
7
6
5
4
3
2
1
-
0
ADC Sidetone Digital Gain Configuration
0
-
0
DVST[4:0]
R/W
0
0
0
0x00 : OFF
0x01 : -0.5dB
0x02 : -2.5dB
0x03 : -4.5dB
0x04 : -6.5dB
0x05 : -8.5dB
0x06 : -10.5dB
0x07 : -12.5dB
0x08 : -14.5dB
0x09 : -16.5dB
0x0A : -18.5dB
0x0B : -20.5dB
0x0C : -22.5dB
0x0D : -24.5dB
0x0E : -26.5dB
0x0F : -28.5dB
0x10 : -30.5dB
0x11 : -32.5dB
0x12 : -34.5dB
0x13 : -36.5dB
0x14 : -38.5dB
0x15 : -40.5dB
0x16 : -42.5dB
0x17 : -44.5dB
0x18 : -46.5dB
0x19 : -48.5dB
0x1A : -50.5dB
0x1B : -52.5dB
0x1C : -54.5dB
0x1D : -56.5dB
0x1E : -58.5dB
0x1F : -60.5dB
M
0
-
ADC Sidetone Enable and Digital Source Configuration
00 : No sidetone selected 10 : Right ADC
01 : Left ADC
11 : Left + Right ADC
-
0
DSTS[1:0]
DESCRIPTION
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
BIT
ADDRESS: 0x1A
NAME
TYPE PoR
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ADC Output Biquad Filter
Table 21: ADC Biquad Digital Preamplifier Level Configuration Register
3
2
1
0
DESCRIPTION
-
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
BIT
7
6
5
4
ADDRESS: 0x18
NAME
TYPE PoR
-
AVBQ[3:0]
R/W
0
ADC Biquad Digital Preamplifier Gain Configuration
0
0x0 : +0dB
0x1 : -1dB
0x2 : -2dB
0x3 : -3dB
0
0
0x8 : -8dB
0x9 : -9dB
0xA : -10dB
0xB : -11dB
0x4 : -4dB
0x5 : -5dB
0x6 : -6dB
0x7 : -7dB
0xC : -12dB
0xD : -13dB
0xE : -14dB
0xF : -15dB
Table 22: DSP Biquad Filter Enable Register
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x41
NAME
TYPE PoR
-
ADCBQEN
R/W
0
EQ3BANDEN
R/W
0
EQ5BANDEN
R/W
0
EQ7BANDEN
R/W
0
DESCRIPTION
-
Enable Biquad filter in ADC path.
0 : biquad filter not used
1 : biquad filter used in ADC path
Enable 3 Band EQ in DAC path. Bands 4 through 7 are not used.
0 : 3 band EQ disabled
1 : 3 band EQ enabled. Only valid if EQ7BANDEN == 0 and EQ5BANDEN == 0.
Enable 5 Band EQ in DAC path. Bands 6 & 7 are not used.
0 : 5 band EQ disabled
1 : 5 band EQ enabled. Only valid if EQ7BANDEN == 0
Enable 7 Band EQ in DAC path.
0 : 7 band EQ disabled.
1 : 7 band EQ enabled. This makes EQ5BANDEN and EQ3BANDEN redundant.
Table 23: ADC Biquad Filter Coefficient
NAME
0xAF 0xB0 0xB1
ADC BIQUAD COEFFICIENT B0
R/W
0x00
ADC_B0[23:16]
ADC_B0[15:8]
ADC_B0[7:0]
0xB2 0xB3 0xB4
ADC BIQUAD COEFFICIENT B1
R/W
0x00
ADC_B1[23:16]
ADC_B1[15:8]
ADC_B1[7:0]
0xB5 0xB6 0xB7
ADC BIQUAD COEFFICIENT B2
R/W
0x00
ADC_B2[23:16]
ADC_B2[15:8]
ADC_B2[7:0]
0xB8 0xB9 0xBA
ADC BIQUAD COEFFICIENT A1
R/W
0x00
ADC_A1[23:16]
ADC_A1[15:8]
ADC_A1[7:0]
ADC BIQUAD COEFFICIENT A2
R/W
0x00
ADC_A2[23:16]
ADC_A2[15:8]
ADC_A2[7:0]
M
ADDRESS RANGE
0xBB 0xBC 0xBD
TYPE PoR
COEFFICIENT SEGMENT
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Digital Audio Interface (DAI) Configuration
Digital Data Path
Table 24: Digital Audio Interface (DAI) Input / Output Configuration Register
5
4
3
2
1
LTEN
R/W
0
LBEN
R/W
0
DMONO
R/W
0
HIZOFF
R/W
0
SDOEN
R/W
0
SDIEN
R/W
0
DESCRIPTION
Enables Data Loop Through from the ADC Output to the DAC Input
1 : ADC to DAC loop-through enabled.
0 : ADC to DAC loop-through disabled.
Enables Data Loop Back from the SDIEN Input to the SDOEN Output
1 : DAI SDIN used as SDOUT data source
0 : ADC used as SDOUT data source.
Enables DAC Mono Mode where SDIN L/R are Mixed and Input to DAC L/R
1 : The left and right channel SDIN input data are mixed together and input to both
the left and right DAC channel signal paths.
0 : The SDIN DAC input data is treated as left/right stereo signal data processed
separately.
When operating in mono voice mode (MODE=1) stereo data may still be input via
SDIN and optionally mixed using DMONO=1.
Disables Hi-Z Mode for SDOUT
1 : The SDOUT pin drives a valid logic level after all data bits have been
transferred out of the part.
0 : The SDOUT pin goes to a high impedance state after all 16 ADC data bits have
been transferred out of the part, allowing the SDOUT line to be shared to the
destination by other devices
Enables the Serial Data Output
1 : Serial data output enabled.
0 : Serial data output disabled.
Enables the Serial Data Input
1 : Serial data input enabled.
0 : Serial data input disabled.
M
0
ADDRESS: 0x25
NAME
TYPE PoR
-
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
BIT
7
6
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Digital Filtering
Table 25: Digital Audio Interface (DAI) Filter Configuration Register
BIT
6
5
4
R/W
1
Enables the CODEC DSP FIR Music filters (Default IIR Voice Filters)
0 : The CODEC DSP filters operate in IIR Voice mode with stop band frequencies
below the fs/2 Nyquist rate. The Voice mode filters are optimized for 8kHz or 16kHz
voice application use.
1 : The CODEC DSP filters operate in a linear phase FIR Audio mode with optional
DC blocking that may be enabled using the AHPF and DHPF I2C bits. The Audio
mode filters are optimized to maintain stereo imaging and operate at higher fs rates
while utilizing lower power.
Enables the ADC DC Blocking Filter
0 : DC blocking filter disabled
1 : DC blocking filter enabled
Enables the DAC DC Blocking Filter
0 : DC blocking filter disabled
1 : DC blocking filter enabled
Enables the DAC High Sample Rate Mode (LRCLK > 50kHz, FIR Only)
1 : LRCLK is greater than 50kHz. 4x FIR interpolation filter used.
0 : LRCLK is less than 50kHz. 8x FIR interpolation filter used.
-
AHPF
R/W
0
DHPF
R/W
0
DHF
R/W
0
-
-
-
M
3
2
1
0
MODE
DESCRIPTION
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
7
ADDRESS: 0x26
NAME
TYPE PoR
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DAI Clock Control
The digital signal paths in the IC require a master clock (MCLK) between 10MHz and 60MHz to function. The
MAX98090 requires an internal clock between 10MHz and 20MHz. A prescaler divides MCLK by 1, 2, or 4 to
create the internal clock (PCLK). PCLK is used to clock all portions of the IC. The MAX98089 includes a digital
audio signal path, capable of supporting any sample rate from 8kHz to 96kHz.
Table 26: Master Mode Clock Configuration Register
7
6
5
4
3
2
1
Master Mode Enable
1 : Master mode (LRCLK and BCLK timing signals generated internally; LRCLK and
BCLK configured as outputs).
0 : Slave mode (LRCLK and BCLK accepted from external source; LRCLK and BCLK
configured as inputs).
Bit Clock (BCLK) Rate Configuration (Master Mode Only)
000 : off
100 : PCLK / 2
001 : 32 x fS
101 : PCLK / 4
010 : 48 x fS
110 : PCLK / 8
011 : 64 x fS
111 : PCLK / 16
MAS
R/W
0
-
-
-
0
BSEL[2:0]
R/W
0
0
M
0
DESCRIPTION
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
BIT
ADDRESS: 0x21
NAME
TYPE PoR
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Table 27: Digital Audio Interface (DAI) Format Configuration Register
BIT
7
6
4
3
2
1
RJ
0
WCI
R/W
0
BCI
R/W
0
DLY
R/W
0
0
WS[1:0]
0
R/W
DESCRIPTION
Configures the DAI for Right Justified Mode (No Data Delay)
0 : left justified mode with optional data delay
1 : right justified mode. DLY register is not used.
Note: TDM has priority over RJ.
Configures the DAI for Frame Clock (LRCLK) Inversion
TDM1 = 0:
1 : Right-channel data is transmitted while LRCLK is low.
0 : Left-channel data is transmitted while LRCLK is low.
TDM1 = 1:
0 : Start of a new frame is signified by the rising edge of the LRCLK pulse.
1 : Start of a new frame is signified by the falling edge of the LRCLK pulse.
Configures the DAI for Bit Clock (BCLK) Inversion
1 : SDIN is accepted on the falling edge of BCLK.
0 : SDIN is accepted on the rising edge of BCLK.
Master Mode:
1 : LRCLK transitions occur on the rising edge of BCLK.
0 : LRCLK transitions occur on the falling edge of BCLK.
Configures the DAI for Data Delay (I2S Standard)
1 : The most significant bit of an audio word is latched at the second BCLK edge after
the LRCLK transition.
0 : The most significant bit of an audio word is latched at the first BCLK edge after
the LRCLK transition.
Set DLY1/DLY2 = 1 to conform to the I2S standard. DLY1/DLY2 are only effective
when TDM1/TDM2 = 0.
DAI Input Data Word Size
If RJ = 1:
00 : 16-bits
10 : 24-bits
01 : 20-bits
11 : Reserved
If RJ = 0:
00 : 16-bits
01, 10, 11 : 20-bits
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
5
ADDRESS: 0x22
NAME
TYPE PoR
-
R/W
0
M
Slave Mode
Master Mode
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Clock Configuration
Table 28: System Master Clock (MCLK) Prescaler Configuration Register
BIT
7
6
ADDRESS: 0x1B
NAME
TYPE PoR
-
5
0
4
3
2
1
0
R/W
Master Clock (MCLK) Prescaler Configuration
00 : Disabled
01 : MCLK / 1, 10MHz <= MCLK <= 20MHz
10 : MCLK / 2, 20MHz < MCLK <= 40MHz
11 : MCLK / 4, 40MHz < MCLK <= 60MHz
-
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
PSCLK[1:0]
DESCRIPTION
0
-
-
-
Table 29: Clock Mode Configuration Register
BIT
7
6
5
4
3
2
1
0
FREQ1[3:0]
R/W
0
0
0
-
-
-
USE_MI1
R/W
0
DESCRIPTION
Exact Integer Sampling Frequency (LRCLK) Configuration
Allows integer sampling on DAI1 for specific PCLK frequencies in 8kHz or 16kHz
voice modes. All modes 0x8 – 0xF are available in either Master or Slave modes of
operation. If the exact indicated PCLK/LRCLK ratio cannot be guaranteed by the
user, AnyClock mode (0x0) should be used. Any FREQ setting other than 0x0
overrides the PLL and NI settings.
Set the PLL to use MI1[15:0] to set a More Accurate Frequency Ratio
0 : M = 65536
1 : M is set by PLLM register.
M
0
ADDRESS: 0x1B
NAME
TYPE PoR
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Frequency Ratio
The NI and MI registers are used to set up the clock generation counter in Master Mode. They can be used
under the following conditions:
-
Master Mode (MAS = 1)
All of the System Clock Quick Setup bits (Index 0x04) are set to 0
FREQ1 bit is set to 0
To set the NI/MI values follow the following method:
Choose Over Sampling Rate (OSR). If fPCLK >= 256 x SR, then OSR = 128 (otherwise OSR = 64).
Calculate fOSR = SR x OSR
Choose MI. This is fPCLK/GCD(fPCLK, fOSR)
Choose NI. This is fOSR x MI/fPCLK
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
1.
2.
3.
4.
Table 30: Any Clock Configuration Register 1 (NI1 MSBs)
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x1D
NAME
TYPE PoR
0
0
0
NI1[14:8]
R/W
0
0
0
0
DESCRIPTION
-
Upper Half of the PLL N Value used in Master Mode Clock Generation
to Calculate the Frequency Ratio (Integer or NI Master Mode).
Table 31: Any Clock Configuration Register 2 (NI1 LSBs)
DESCRIPTION
Lower Half of the PLL N Value used in Master Mode Clock Generation
to Calculate the Frequency Ratio (Integer or NI Master Mode).
M
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x1E
NAME
TYPE PoR
0
0
0
0
NI1[7:0]
R/W
0
0
0
0
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Table 32: Any Clock Configuration Register 3 (MI1 MSBs)
ADDRESS: 0x1F
NAME
TYPE PoR
0
0
0
0
MI1[15:8]
R/W
0
0
0
0
DESCRIPTION
Upper Half of the PLL M Value used in Master Mode Clock Generation to
Calculate an Accurate Non-Integer Frequency Ratio (PLL Master Mode).
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
BIT
7
6
5
4
3
2
1
0
Table 33: Any Clock Configuration Register 4 (MI1 LSBs)
DESCRIPTION
Lower Half of the PLL M Value used in Master Mode Clock Generation to
Calculate an Accurate Non-Integer Frequency Ratio (PLL Master Mode).
M
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x20
NAME
TYPE PoR
0
0
0
0
MI1[7:0]
R/W
0
0
0
0
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DAI TDM Mode
Table 34: Digital Audio Interface (DAI) TDM Format Register 1
1
0
DESCRIPTION
Configures the DAI Frame Sync Pulse Width
1 : Frame sync pulse extended to the width of the entire data word.
(TDM1/TDM2 = 1 only)
0 : Frame sync pulse is one bit wide
Enables the DAI for Time Division Multiplex (TDM) Mode
1 : Enables time-division multiplex mode and configures the audio interface to accept
PCM data.
0 : Disables time-division multiplex mode.
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
BIT
7
6
5
4
3
2
ADDRESS: 0x23
NAME
TYPE PoR
FSW
R/W
0
TDM
R/W
0
Table 35: Digital Audio Interface (DAI) TDM Format Register 2
BIT
7
6
5
4
0
SLOTR[1:0]
SLOTDLY[3:0]
R/W
R/W
0
0
0
0
0
DESCRIPTION
Selects the Time Slot to use for Left Channel Data in TDM Mode
00 : Time Slot 1
10 : Time Slot 3
01 : Time Slot 2
11 : Time Slot 4
Selects the Time Slot to use for Right Channel Data in TDM Mode
00 : Time Slot 1
10 : Time Slot 3
01 : Time Slot 2
11 : Time Slot 4
Enables Data Delay for Slot 4 in TDM Mode
Enables Data Delay for Slot 3 in TDM Mode
Enables Data Delay for Slot 2 in TDM Mode
Enables Data Delay for Slot 1 in TDM Mode
M
3
2
1
0
ADDRESS: 0x24
NAME
TYPE PoR
0
SLOTL[1:0]
R/W
0
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Digital to Analog Converter (DAC) Configuration
DAC Input Digital Level
Voice Gain
Playback Level
Table 36: Digital Audio Interface (DAI) Playback Level Configuration Register
5
4
3
2
1
0
DESCRIPTION
Enables the DAI DAC Data Input Mute
0
DAI Digital Input Coarse Adjust Gain Configuration
00 : 0dB
10 : +12dB
01 : +6dB
11 : +18dB
0
DAI Digital Input Fine Adjust Gain Configuration
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
BIT
7
6
ADDRESS: 0x27
NAME
TYPE PoR
DV1M
R/W
0
-
DV1G[1:0]
DV1[3:0]
R/W
R/W
0
0
1
1
0x0 : 0dB
0x1 : -1dB
0x2 : -2dB
0x3 : -3dB
0xC : -12dB
0xD : -13dB
0xE : -14dB
0xF : -15dB
0x8 : -8dB
0x9 : -9dB
0xA : -10dB
0xB : -11dB
0x4 : -4dB
0x5 : -5dB
0x6 : -6dB
0x7 : -7dB
Automatic Level Control
Table 37: Automatic Level Control (ALC) Timing Register
BIT
7
ALCEN
ALCRLS[2:0]
-
ALCATK[2:0]
R/W
0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
DESCRIPTION
DAC ALC Enable
0 : ALC disabled
1 : ALC enabled
DAC ALC Release Time Configuration
0x0 : 8s
0x1 : 4s
0x2 : 2s
0x3 : 1s
0x4 : 0.5s
0x5 : 0.25s
0x6 : 0.125s
0x7 : 0.0625s
0x4 : 25ms
0x5 : 50ms
0x6 : 100ms
0x7 : 200ms
-
DAC ALC Attack Time Configuration
0x0 : 0.5ms
0x1 : 1ms
0x2 : 5ms
0x3 : 10ms
M
6
5
4
3
2
1
0
ADDRESS: 0x33
NAME
TYPE PoR
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Table 38: Automatic Level Control (ALC) Compressor Register
BIT
ADDRESS: 0x34
NAME
TYPE PoR
DESCRIPTION
5
0
DAC ALC Compression Ratio Configuration
0x0 : 1:1
0x3 : 1:4
0x1 : 1:1.5
0x4 : 1:inf
0x2 : 1:2
4
0
DAC ALC Compression Threshold Configuration
7
0
6
2
1
0
R/W
0
0x00 : 0
0x01 : -1dB
0x02 : -2dB
0x03 : -3dB
0x04 : -4dB
0x05 : -5dB
0x06 : -6dB
0x07 : -7dB
0x08 : -8dB
0x09 : -9dB
0x0A : -10dB
0x0B : -11dB
0x0C : -12dB
0x0D : -13dB
0x0E : -14dB
0x0F : -15dB
0x10 : -16dB
0x11 : -17dB
0x12 : -18dB
0x13 : -19dB
0x14 : -20dB
0x15 : -21dB
0x16 : -22dB
0x17 : -23dB
0x18 : -24dB
0x19 : -25dB
0x1A : -26dB
0x1B : -27dB
0x1C : -28dB
0x1D : -29dB
0x1E : -30dB
0x1F : -31dB
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
3
ALCCMP[2:0]
0
ALCTHC[4:0]
R/W
0
0
0
Table 39: Automatic Level Control (ALC) Expander Register
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x35
NAME
TYPE PoR
0
DAC ALC Expansion Ratio Configuration
0x0 : 1:1
0x1 : 2:1
0x2 : 3:1
0
DAC ALC Expansion Threshold Configuration
0
ALCEXP[2:0]
R/W
0
0
ALCTHC[4:0]
R/W
DESCRIPTION
0
0
0
0x00 : -35dB
0x01 : -36dB
0x02 : -37dB
0x03 : -38dB
0x04 : -39dB
0x05 : -40dB
0x06 : -41dB
0x07 : -42dB
0x08 : -43dB
0x09 : -44dB
0x0A : -45dB
0x0B : -46dB
0x0C : -47dB
0x0D : -48dB
0x0E : -49dB
0x0F : -50dB
0x10 : -51dB
0x11 : -52dB
0x12 : -53dB
0x13 : -54dB
0x14 : -55dB
0x15 : -56dB
0x16 : -57dB
0x17 : -58dB
0x18 : -59dB
0x19 : -60dB
0x1A : -61dB
0x1B : -62dB
0x1C : -63dB
0x1D : -64dB
0x1E : -65dB
0x1F : -66dB
Table 40: Automatic Level Control (ALC) Gain Configuration Register
M
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x36
NAME
TYPE PoR
0
0
ALCG[4:0]
R/W
0
0
0
DESCRIPTION
DAC ALC Make-Up Gain Configuration
0x0 : +0dB
0x1 : +1dB
0x2 : +2dB
0x3 : +3dB
0x4 : +4dB
0x5 : +5dB
0x6 : +6dB
0x7 : +7dB
0x8 : +8dB
0x9 : +9dB
0xA : +10dB
0xB : +11dB
0xC : +12dB
0xD : reserved
0xE : reserved
0xF : reserved
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DAC Input Parametric Equalizer
Table 41: DSP Biquad Filter Enable Register
3
2
1
0
DESCRIPTION
Enable Biquad filter in ADC path.
0 : biquad filter not used
1 : biquad filter used in ADC path
Enable 3 Band EQ in DAC path. Bands 4 through 7 are not used.
0 : 3 band EQ disabled
1 : 3 band EQ enabled. Only valid if EQ7BANDEN == 0 and EQ5BANDEN == 0.
Enable 5 Band EQ in DAC path. Bands 6 & 7 are not used.
0 : 5 band EQ disabled
1 : 5 band EQ enabled. Only valid if EQ7BANDEN == 0
Enable 7 Band EQ in DAC path.
0 : 7 band EQ disabled.
1 : 7 band EQ enabled. This makes EQ5BANDEN and EQ3BANDEN redundant.
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
BIT
7
6
5
4
ADDRESS: 0x41
NAME
TYPE PoR
ADCBQEN
R/W
0
EQ3BANDEN
R/W
0
EQ5BANDEN
R/W
0
EQ7BANDEN
R/W
0
Table 42: Parametric Equalizer Playback Level Configuration Register
BIT
7
6
5
4
3
2
1
/EQCLP\
DVEQ[3:0]
R/W
0
R/W
0
0
0
0
DESCRIPTION
Enables DAI Digital Input Equalizer Clipping Detection
1 : Equalizer Clip detect disabled
0 : Equalizer Clip detect enabled
DAI Digital Input Equalizer Attenuation Level Configuration
0x8 : -8dB
0x4 : -4dB
0x0 : +0dB
0x9 : -9dB
0x5 : -5dB
0x1 : -1dB
0xA : -10dB
0x6 : -6dB
0x2 : -2dB
0xB : -11dB
0x7 : -7dB
0x3 : -3dB
0xC : -12dB
0xD : -13dB
0xE : -14dB
0xF : -15dB
M
0
ADDRESS: 0x28
NAME
TYPE PoR
-
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Table 43: Parametric Equalizer Band N (1-7) Biquad Filter Coefficient Registers
ADDRESS RANGE (BY BAND)
1
2
3
4
5
6
7
0x46 0x55 0x64 0x73 0x82 0x91 0xA0
0x47 0x56 0x65 0x74 0x83 0x92 0xA1
0x48 0x57 0x66 0x75 0x84 0x93 0xA2
0x49 0x58 0x67 0x76 0x85 0x94 0xA3
EQUALIZER BAND N
COEFFICIENT B0
EQUALIZER BAND N
COEFFICIENT B1
TYPE PoR
COEFFICIENT SEGMENT
R/W 0x00
B0_N[23:16]
R/W 0x00
B0_N[15:8]
R/W 0x00
B0_N[7:0]
R/W 0x00
B1_N[23:16]
R/W 0x00
B1_N[15:8]
R/W 0x00
B1_N[7:0]
R/W 0x00
B2_N[23:16]
R/W 0x00
B2_N[15:8]
R/W 0x00
B2_N[7:0]
R/W 0x00
A1_N[23:16]
R/W 0x00
A1_N[15:8]
R/W 0x00
A1_N[7:0]
R/W 0x00
A2_N[23:16]
R/W 0x00
A2_N[15:8]
R/W 0x00
A2_N[7:0]
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
0x4A 0x59 0x68 0x77 0x86 0x95 0xA4
NAME
0x4B 0x5A 0x69 0x78 0x87 0x96 0xA5
0x4C 0x5B 0x6A 0x79 0x88 0x97 0xA6
0x4D 0x5C 0x6B 0x7A 0x89 0x98 0xA7
0x4E 0x5D 0x6C 0x7B 0x8A 0x99 0xA8
0x4F 0x5E 0x6D 0x7C 0x8B 0x9A 0xA9
0x50 0x5F 0x6E 0x7D 0x8C 0x9B 0xAA
0x51 0x60 0x6F 0x7E 0x8D 0x9C 0xAB
0x52 0x61 0x70 0x7F 0x8E 0x9D 0xAC
0x53 0x62 0x71 0x80 0x8F 0x9E 0xAD
EQUALIZER BAND N
COEFFICIENT A1
EQUALIZER BAND N
COEFFICIENT A2
M
0x54 0x63 0x72 0x81 0x90 0x9F 0xAE
EQUALIZER BAND N
COEFFICIENT B2
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MAX98090
Analog Audio Output Configuration
The device features three different integrated flexible analog audio output drivers. The receiver / line output
driver can be configured either as a differential receiver output (optimal for a 32Ω earpiece speaker) or as a
stereo single ended line output driver. The stereo speaker output drivers are filterless class D amplifiers capable
of driving both 4Ω and 8Ω speakers. The headphone output drivers utilize Maxim’s DirectDrive architecture with
an integrated charge pump, and provide configurable headphone and headset jack detection. Each analog
audio output driver has an individual programmable gain mixer and amplifier. Each output mixer accepts any
combination of signals from both the integrated DAC, and the analog microphone and line input drivers.
DACL
DACR
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
RCV /
LINE
OUT
RCVLVOL[4:0]
RCVLM
RCVLEN
MIXRCVL[5:0]
MIXRCVLG[1:0]
MIC 1
MIC 2
LINE A
FLEXSOUND
TECHNOLOGY
DSP
-12dB to 0dB
MIC 2
LINE A
RCV /
LINE
OUT
RIGHT
MIXER
LINE B
-12dB to 0dB
RCV /
LINE
OUT
MUX
MIC 1
DACREN
MIC 2
SPK
LEFT
MIXER
SPVOLL[4:0]
SPLM
SPLEN
-12dB to 0dB
SPKLGND
-48dB to 14dB
SPEAKER
LEFT PGA
LINE A
RCVN /
LOUTR
RCVRVOL[4:0]
RCVRM
RCVREN
MIXRCVR[5:0]
MIXRCVRG[1:0]
MIXSPL[5:0]
MIXSPLG[1:0]
DACR
-62dB to 8dB
LINE OUT
RIGHT PGA
DACL
DAC
RIGHT
DACHP
PERFMODE
ZDENB
VS2ENB
VSENB
LINMOD
DACL
MIC 1
DACLEN
RCVP /
LOUTL
LINE B
DACR
DAC
LEFT
-62dB to 8dB
LINE OUT
LEFT PGA
LEFT
MIXER
SPKLP
6dB
SPKLN
LINE B
-48dB to 14dB
DACR
MIC 1
MIC 2
SPK
RIGHT
MIXER
-12dB to 0dB
SPEAKER
RIGHT PGA
SPKSLAVE
DACL
MIXHPL[5:0]
MIXHPLG[1:0]
DACR
MIC 2
HP
LEFT
MIXER
SPKRN
SPKRGND
SPVOLR[4:0]
SPRM
SPREN
MIXSPL[5:0]
MIXSPLG[1:0]
LINE B
SPKRP
6dB
LINE A
MIC 1
SPK_VDD
ZDENB
VS2ENB
VSENB
DACL
HPVOLL[4:0]
HPLM
HPLEN
-12dB to 0dB
HP
LEFT
MUX
LINE A
-67dB to 3dB
HEADPHONE
LEFT PGA
HPL
LINE B
ZDENB
VS2ENB
VSENB
MIXHPLSEL
MIXHPRSEL
HPSNS
DACL
DACR
MIC 1
MIC 2
-12dB to 0dB
HP
RIGHT
MUX
LINE A
LINE B
MIXHPR[5:0]
MIXHPRG[1:0]
-67dB to 3dB
HEADPHONE
RIGHT PGA
HPVOLR[4:0]
HPRM
HPREN
HEADPHONE
DIRECT DRIVE
CHARGE PUMP
HPR
HPVDD
HPGND
C1P
C1N
CPVDD
VPVSS
M
ANALOG
INPUT
DRIVERS
HP
RIGHT
MIXER
Figure 11: Analog Audio Output Functional Diagram
_____________________________________________________________________ 96
MAXIM Confidential
MAX98090
Analog Receiver (Earpiece) Output
SPEAKER / HEADPHONES
FLEXSOUND
TECHNOLOGY
DSP
DACR
DACL
MIC 1
MIC 2
DAC
LEFT
DAC
RIGHT
LINE A
RCV /
LINE
OUT
MIXRCVL[5:0]
MIXRCVLG[1:0]
RCVLVOL[4:0]
RCVLM
RCVLEN
-12dB to 0dB
LINE OUT
LEFT PGA
LEFT
MIXER
-62dB to 8dB
RCVP /
LOUTL
LINE B
DACLEN
ZDENB
VS2ENB
VSENB
LINMOD
DACREN
DACHP
PERFMODE
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
DACR
DACL
MIC 1
MIC 2
ANALOG
INPUT
DRIVERS
LINE A
LINE B
RCV /
LINE
OUT
RIGHT
MIXER
-12dB to 0dB
RCV /
LINE
OUT
MUX
MIXRCVR[5:0]
MIXRCVRG[1:0]
LINE OUT
RIGHT PGA
-62dB to 8dB
RCVN /
LOUTR
RCVRVOL[4:0]
RCVRM
RCVREN
Figure 12: Receiver Output Functional Diagram
Table 44: Receiver and Left Line Output Mixer Source Configuration Register
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x37
NAME
TYPE PoR
0
0
0
MIXRCVL[5:0]
R/W
0
0
0
DESCRIPTION
Selects DAC Left as the Input to the Receiver / Line Out Left Mixer
Selects DAC Right as the Input to the Receiver / Line Out Left Mixer
Selects Line A as the Input to the Receiver / Line Out Left Mixer
Selects Line B as the Input to the Receiver / Line Out Left Mixer
Selects MIC 1 as the Input to the Receiver / Line Out Left Mixer
Selects MIC 2 as the Input to the Receiver / Line Out Left Mixer
Table 45: Receiver and Left Line Output Mixer Level Control Register
BIT
7
6
5
4
3
2
1
ADDRESS: 0x38
NAME
TYPE PoR
0
M
MIXRCVLG[1:0]
0
R/W
0
DESCRIPTION
Receiver / Line Output Left Mixer Gain Configuration.
00 : 0dB
10 : -9.5dB
01 : -6dB
11 : -12dB
Note: these gains are relative to the maximum output signal. In Line Output Mode this
is 1Vpk, while in receiver BTL mode it is 1Vrms differential.
_____________________________________________________________________ 97
MAXIM Confidential
MAX98090
Table 46: Receiver and Left Line Output Volume Control Register
BIT
ADDRESS: 0x39
NAME
TYPE PoR
7
RCVLM
R/W
0
6
5
-
-
-
3
2
1
0
1
Receiver / Line Output Left Mute
0 : not muted
1 : muted
Receiver / Line Output Left PGA Volume Configuration
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
4
DESCRIPTION
0
RCVLVOL[4:0]
R/W
1
0
1
0x1F : +8dB
0x1E : +7.5dB
0x1D : +7dB
0x1C : +6.5dB
0x1B : +6dB
0x1A : +5dB
0x19 : +4dB
0x18 : +3dB
0x17 : +2dB
0x16 : +1dB
0x15 : +0dB
0x14 : -2dB
0x13 : -4dB
0x12 : -6dB
0x11 : -8dB
0x10 : -10dB
0x0F : -12dB
0x0E : -14dB
0x0D : -17dB
0x0C : -20dB
0x0B : -23dB
0x0A : -26dB
0x09 : -29dB
0x08 : -32dB
0x07 : -35dB
0x06 : -38dB
0x05 : -42dB
0x04 : -46dB
0x03 : -50dB
0x02 : -54dB
0x01 : -58dB
0x00 : -62dB
Receiver Gain Control
Receiver Output Mixer
M
The IC’s receiver amplifier accepts input from the stereo DAC, the line inputs (single-ended or differential), and
the MIC inputs. Configure the mixer to mix any combination of the available sources. When more than one
signal is selected, the mixed signal can be configured to attenuate 6dB, 9.5dB, or 12dB.
_____________________________________________________________________ 98
MAXIM Confidential
MAX98090
Analog Speaker Output
The IC integrates a stereo filterless Class D amplifier that offers much higher efficiency than Class AB without
the typical disadvantages.
The high efficiency of a Class D amplifier is due to the switching operation of the output stage transistors. In a
Class D amplifier, the output transistors act as current steering switches and consume negligible additional
power. Any power loss associated with the Class D output stage is mostly due to the I2R loss of the MOSFET
on-resistance, and quiescent current overhead.
The theoretical best efficiency of a linear amplifier is 78%, however, that efficiency is only exhibited at peak
output power. Under normal operating levels (typical music reproduction levels), efficiency falls below 30%,
whereas the IC’s Class D amplifier still exhibits 80% efficiency under the same conditions.
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
Traditional Class D amplifiers require the use of external LC filters or shielding to meet EN55022B and FCC
electromagnetic-interference (EMI) regulation standards. Maxim’s patented active emissions limiting edge-rate
control circuitry reduces EMI emissions, allowing operation without any output filtering in typical applications.
RECEIVER / LINE OUT / HEADPHONES
FLEXSOUND
TECHNOLOGY
DSP
DACR
MIC 1
MIC 2
DAC
LEFT
DAC
RIGHT
SPVOLL[4:0]
SPLM
SPLEN
MIXSPL[5:0]
MIXSPLG[1:0]
DACL
SPK
LEFT
MIXER
-48dB to 14dB
-12dB to 0dB
SPEAKER
LEFT PGA
LINE A
SPKLGND
SPKLP
6dB
SPKLN
LINE B
DACLEN
DACHP
PERFMODE
ZDENB
VS2ENB
VSENB
DACREN
DACR
DACL
MIC 1
ANALOG
INPUT
DRIVERS
MIC 2
SPKSLAVE
-48dB to 14dB
SPK
RIGHT
MIXER
-12dB to 0dB
SPEAKER
RIGHT PGA
LINE A
LINE B
MIXSPL[5:0]
MIXSPLG[1:0]
SPK_VDD
SPKRP
6dB
SPVOLR[4:0]
SPRM
SPREN
SPKRN
SPKRGND
M
Figure 13: Class D Speaker Output Functional Diagram
_____________________________________________________________________ 99
MAXIM Confidential
MAX98090
Speaker Class-D Output Amplifier
Speaker Gain Control
Table 47: Left Speaker Amplifier Volume Control Register
BIT
6
5
4
3
SPLM
R/W
-
-
1
0
-
Left Speaker Output Mute Enable
1 : Left Speaker output muted.
0 : Speaker output volume set by the volume control bits.
When going into mute, the volume will slew to full attenuation, after which mute will be
asserted. When coming out of mute, the volume will slew from full attenuation to the
current SPVOLL / SPVOLR setting.
-
1
Left Speaker Output Amplifier Volume Control Configuration
0
0
1
SPVOLL[5:0]
2
DESCRIPTION
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
7
ADDRESS: 0x31
NAME
TYPE PoR
R/W
1
0
0
0x3F : +14dB
0x3E : +13.5dB
0x3D : +13dB
0x3C : +12.5dB
0x3B : +12dB
0x3A : +11.5dB
0x39 : +11dB
0x38 : +10.5dB
0x37 : +10dB
0x36 : +9.5dB
0x35 : +9dB
0x34 : +8dB
0x33 : +7dB
0x32 : +6dB
0x31 : +5dB
0x30 : +4dB
0x2F : +3dB
0x2E : +2dB
0x2D : +1dB
0x2C : +0dB
0x2B : -1dB
0x2A : -2dB
0x29 : -3dB
0x28 : -4dB
0x27 : -5dB
0x26 : -6dB
0x25 : -8dB
0x24 : -10dB
0x23 : -12dB
0x22 : -14dB
0x21 : -17dB
0x20 : -20dB
0x1F : -23dB
0x1E : -26dB
0x1D : -29dB
0x1C : -32dB
0x1B : -36dB
0x1A : -40dB
0x19 : -44dB
0x18 : -48dB
Table 48: Right Speaker Amplifier Volume Control Register
BIT
7
6
5
4
3
ADDRESS: 0x32
NAME
TYPE PoR
SPRM
R/W
0
-
-
-
Right Speaker Output Mute Enable
1 : Right Speaker output muted.
0 : Speaker output volume set by the volume control bits.
When going into mute, the volume will slew to full attenuation, after which mute will be
asserted. When coming out of mute, the volume will slew from full attenuation to the
current SPVOLL / SPVOLR setting.
-
1
Right Speaker Output Amplifier Volume Control Configuration
0
1
SPVOLR[5:0]
2
M
1
0
DESCRIPTION
R/W
1
0
0
0x3F : +14dB
0x3E : +13.5dB
0x3D : +13dB
0x3C : +12.5dB
0x3B : +12dB
0x3A : +11.5dB
0x39 : +11dB
0x38 : +10.5dB
0x37 : +10dB
0x36 : +9.5dB
0x35 : +9dB
0x34 : +8dB
0x33 : +7dB
0x32 : +6dB
0x31 : +5dB
0x30 : +4dB
0x2F : +3dB
0x2E : +2dB
0x2D : +1dB
0x2C : +0dB
0x2B : -1dB
0x2A : -2dB
0x29 : -3dB
0x28 : -4dB
0x27 : -5dB
0x26 : -6dB
0x25 : -8dB
0x24 : -10dB
0x23 : -12dB
0x22 : -14dB
0x21 : -17dB
0x20 : -20dB
0x1F : -23dB
0x1E : -26dB
0x1D : -29dB
0x1C : -32dB
0x1B : -36dB
0x1A : -40dB
0x19 : -44dB
0x18 : -48dB
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MAX98090
Speaker Output Mixer
The IC’s speaker amplifiers accept input from the stereo DAC, the line inputs (single-ended ore differential), and
the MIC inputs. Configure the mixer to mix any combination of the available sources. When more than one
signal is selected, the mixer can be configured to attenuate the signal by 6dB, 9dB or 12dB.
Table 49: Left Speaker Mixer Configuration Register
DESCRIPTION
Select Left DAC Output to Left Speaker Mixer
Select Right DAC Output to Left Speaker Mixer
Select Line Input A to Left Speaker Mixer
Select Line Input B to Left Speaker Mixer
Select Microphone Input 1 to Left Speaker Mixer
Select Microphone Input 2 to Left Speaker Mixer
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x2E
NAME
TYPE PoR
0
0
0
MIXSPL[5:0]
R/W
0
0
0
Table 50: Right Speaker Mixer Configuration Register
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x2F
NAME
TYPE PoR
-
SPK_SLAVE
MIXSPR[5:0]
-
-
R/W
0
0
0
0
0
0
DESCRIPTION
-
Speaker Slave Mode Enable
0 : right channel clock always generated independently
1 : right channel speaker uses left channel speaker clock if both speaker channels
are enabled
Select Left DAC Output to Right Speaker Mixer
Select Right DAC Output to Right Speaker Mixer
Select Line Input A to Right Speaker Mixer
Select Line Input B to Right Speaker Mixer
Select Microphone Input 1 to Right Speaker Mixer
Select Microphone Input 2 to Right Speaker Mixer
Table 51: Speaker Mixer Gain Register
BIT
7
6
5
4
3
MIXSPRG[1:0]
M
2
ADDRESS: 0x30
NAME
TYPE PoR
-
1
0
MIXSPLG[1:0]
R/W
R/W
0
0
0
0
DESCRIPTION
Right Speaker Mixer Gain Configuration
00 : +0dB
10 : -9.5dB
01 : -6dB
11 : -12dB
Left Speaker Mixer Gain Configuration
00 : +0dB
10 : -9.5dB
01 : -6dB
11 : -12dB
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MAX98090
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
Analog Headphone Output
Figure 14: DirectDrive Headphone Output Functional Diagram
Table 52: Left Headphone Mixer Configuration Register
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x29
NAME
TYPE PoR
0
0
0
MIXHPL[5:0]
R/W
0
0
0
DESCRIPTION
Select Left DAC Output to Left Headphone Mixer
Select Right DAC Output to Left Headphone Mixer
Select Line Input A to Left Headphone Mixer
Select Line Input B to Left Headphone Mixer
Select Microphone Input 1 to Left Headphone Mixer
Select Microphone Input 2 to Left Headphone Mixer
Table 53: Right Headphone Mixer Configuration Register
ADDRESS: 0x2A
NAME
TYPE PoR
0
0
0
MIXHPR[5:0]
R/W
0
0
0
M
BIT
7
6
5
4
3
2
1
0
DESCRIPTION
Select Left DAC Output to Right Headphone Mixer
Select Right DAC Output to Right Headphone Mixer
Select Line Input A to Right Headphone Mixer
Select Line Input B to Right Headphone Mixer
Select Microphone Input 1 to Right Headphone Mixer
Select Microphone Input 2 to Right Headphone Mixer
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MAX98090
Table 54: Headphone Mixer Control and Gain Register
BIT
7
6
4
3
2
1
0
MIXHPRSEL
R/W
0
DESCRIPTION
Select Headphone Mixer as Right Input Source (Default DAC Right Direct)
0 : DAC only source (best dynamic range and power consumption)
1 : Headphone mixer source
Select Headphone Mixer as Left Input Source (Default DAC Left Direct)
0 : DAC only source (best dynamic range and power consumption)
1 : Headphone mixer source
Right Headphone Mixer Gain Configuration
00 : +0dB
10 : -9.5dB
01 : -6dB
11 : -12dB
Left Headphone Mixer Gain Configuration
00 : +0dB
10 : -9.5dB
01 : -6dB
11 : -12dB
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
5
ADDRESS: 0x2B
NAME
TYPE PoR
-
MIXHPLSEL
R/W
MIXHPRG[1:0]
R/W
MIXHPLG[1:0]
R/W
0
0
0
0
0
Table 55: Left Headphone Amplifier Volume Control Register
BIT
7
6
5
4
3
2
1
DESCRIPTION
HPLM
R/W
0
-
-
-
Left Headphone Output Mute Enable
1 : Headphone output muted.
0 : Headphone output volume set by the volume control bits.
When going into mute, the volume will slew to full attenuation, after which mute will be
asserted. When coming out of mute, the volume will slew from full attenuation to the
current HPVOLL / HPVOLR setting.
-
1
Left Headphone Output Amplifier Volume Control Configuration
1
HPVOLL[4:0]
R/W
0
1
0
0x1F : +3dB
0x1E : +2.5dB
0x1D : +2dB
0x1C : +1.5dB
0x1B : +1dB
0x1A : +0dB
0x19 : -1dB
0x18 : -2dB
0x17 : -3dB
0x16 : -4dB
0x15 : -5dB
0x14 : -7dB
0x13 : -9dB
0x12 : -11dB
0x11 : -13dB
0x10 : -15d
0x0F : -17dB
0x0E : -19dB
0x0D : -22dB
0x0C : -25dB
0x0B : -28dB
0x0A : -31dB
0x09 : -34dB
0x08 : -37dB
0x07 : -40dB
0x06 : -43dB
0x06 : -47dB
0x04 : -51dB
0x03 : -55dB
0x02 : -59dB
0x01 : -63dB
0x00 : -67dB
M
0
ADDRESS: 0x2C
NAME
TYPE PoR
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MAX98090
Table 56: Right Headphone Amplifier Volume Control Register
BIT
ADDRESS: 0x2D
NAME
TYPE PoR
DESCRIPTION
HPRM
R/W
0
6
5
-
-
-
1
Right Headphone Output Amplifier Volume Control Configuration
4
3
2
1
1
HPVOLR[4:0]
R/W
0
1
0
0x1F : +3dB
0x1E : +2.5dB
0x1D : +2dB
0x1C : +1.5dB
0x1B : +1dB
0x1A : +0dB
0x19 : -1dB
0x18 : -2dB
0x17 : -3dB
0x16 : -4dB
0x15 : -5dB
0x14 : -7dB
0x13 : -9dB
0x12 : -11dB
0x11 : -13dB
0x10 : -15d
0x0F : -17dB
0x0E : -19dB
0x0D : -22dB
0x0C : -25dB
0x0B : -28dB
0x0A : -31dB
0x09 : -34dB
0x08 : -37dB
0x07 : -40dB
0x06 : -43dB
0x06 : -47dB
0x04 : -51dB
0x03 : -55dB
0x02 : -59dB
0x01 : -63dB
0x00 : -67dB
M
0
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
7
Right Headphone Output Mute Enable
1 : Headphone output muted.
0 : Headphone output volume set by the volume control bits.
When going into mute, the volume will slew to full attenuation, after which mute will be
asserted. When coming out of mute, the volume will slew from full attenuation to the
current HPVOLL / HPVOLR setting.
-
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DirectDrive Headphone Amplifier
Traditional single-supply headphone amplifiers have outputs biased at a nominal DC voltage (typically half the
supply). Large coupling capacitors are needed to block this DC bias from the headphone. Without these
capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power
dissipation and possible damage to both headphone and headphone amplifier.
Maxim’s second-generation DirectDrive architecture uses a charge pump to create an internal negative supply
voltage. This allows the headphone outputs of the ICs to be biased at GND while operating from a single supply
(Figure TBD). Without a DC component, there is no need for the large DC-blocking capacitors. Instead of two
large (220μF typ.) capacitors, the IC’s charge pump requires 3 small ceramic capacitors, conserving board
space, reducing cost, and improving the frequency response of the headphone amplifier.
AX P
R
IM E
L
C IM
O I
N NA
FI
D RY
EN
TI
AL
Class H Operation
A Class H amplifier uses a Class AB output stage with power supplies that are modulated by the output signal.
In the case of the ICs, two nominal power-supply differentials of 1.8V (+0.9V to -0.9V) and 3.6V (+1.8V to -1.8V)
are available from the charge pump. Figure TBD shows the operation of the output-voltage-dependent power
supply.
Charge Pump
The dual-mode charge pump generates both the positive and negative power supply for the headphone
amplifier. To maximize efficiency, both the charge pump’s switching frequency and output voltage change based
on signal level.
When the input signal level is less than 10% of PVDD, the switching frequency is reduced to a low rate. This
minimizes switching losses in the charge pump. When the input signal exceeds 10% of PVDD, the switching
frequency increases to support the load current.
For input signals below 25% of PVDD, the charge pump generates Q(PVDD/2) to minimize the voltage drop
across the amplifier’s power stage and thus improve efficiency. Input signals that exceed 25% of PVDD cause
the charge pump to output QPVDD. The higher output voltage allows for full output power from the headphone
amplifier.
To prevent audible glitches when transitioning from the Q(PVDD/2) output mode to the QPVDD output mode,
the charge pump transitions very quickly. This quick change draws significant current from PVDD for the
duration of the transition. The bypass capacitor on PVDD supplies the required current and prevents droop on
PVDD.
The charge pump’s dynamic switching mode can be turned off through the I2C interface. The charge pump can
then be forced to output either Q(PVDD/2) or QPVDD regardless of input signal level
Headphone Gain Control
Headphone Ground Sense
HPSNS senses the ground return for the headphone load. For optimal performance, connect HPSNS to the
ground pole of the jack through an isolated trace, as shown in Figure TBD. If HPSNS is not used, connect to the
analog ground plane.
Headphone Output Mixer
M
The headphone amplifier mixer accepts input from the stereo DAC, the line inputs (single-ended or differential),
and the MIC inputs. Configure the mixer to mix any combination of the available sources. When more than one
signal is selected, the mixer can be configured to attenuate the signal by 6dB, 9.5dB, or 12dB. The stereo DAC
can bypass the headphone mixers, and be connected directly to the headphone amplifiers to provide lower
power consumption.
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MAX98090
Analog Line Outputs
SPEAKER / HEADPHONES
FLEXSOUND
TECHNOLOGY
DSP
DACR
DACL
MIC 1
MIC 2
DAC
LEFT
DAC
RIGHT
LINE A
RCV /
LINE
OUT
MIXRCVL[5:0]
MIXRCVLG[1:0]
RCVLVOL[4:0]
RCVLM
RCVLEN
-12dB to 0dB
LINE OUT
LEFT PGA
LEFT
MIXER
-62dB to 8dB
RCVP /
LOUTL
LINE B
DACLEN
LINMOD
DACREN
ZDENB
VS2ENB
VSENB
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DACHP
PERFMODE
DACR
DACL
MIC 1
MIC 2
ANALOG
INPUT
DRIVERS
LINE A
LINE B
RCV /
LINE
OUT
RIGHT
MIXER
-12dB to 0dB
RCV /
LINE
OUT
MUX
MIXRCVR[5:0]
MIXRCVRG[1:0]
LINE OUT
RIGHT PGA
-62dB to 8dB
RCVN /
LOUTR
RCVRVOL[4:0]
RCVRM
RCVREN
Figure 15: Stereo Single-Ended Line Output Functional Diagram
Table 57: Receiver and Left Line Output Mixer Source Configuration Register
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x37
NAME
TYPE PoR
0
0
0
MIXRCVL[5:0]
R/W
0
0
0
DESCRIPTION
Selects DAC Left as the Input to the Receiver / Line Out Left Mixer
Selects DAC Right as the Input to the Receiver / Line Out Left Mixer
Selects Line A as the Input to the Receiver / Line Out Left Mixer
Selects Line B as the Input to the Receiver / Line Out Left Mixer
Selects MIC 1 as the Input to the Receiver / Line Out Left Mixer
Selects MIC 2 as the Input to the Receiver / Line Out Left Mixer
Table 58: Receiver and Left Line Output Mixer Level Control Register
BIT
7
6
5
4
3
2
0
M
1
ADDRESS: 0x38
NAME
TYPE PoR
-
MIXRCVLG[1:0]
0
R/W
0
DESCRIPTION
Receiver / Line Output Left Mixer Gain Configuration.
00 : 0dB
10 : -9.5dB
01 : -6dB
11 : -12dB
Note: these gains are relative to the maximum output signal. In Line Output Mode this is
1Vpk, while in receiver BTL mode it is 1Vrms differential.
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Table 59: Receiver and Left Line Output Volume Control Register
BIT
ADDRESS: 0x39
NAME
TYPE PoR
7
RCVLM
R/W
0
6
5
-
-
-
3
2
1
0
1
Receiver / Line Output Left Mute
0 : not muted
1 : muted
Receiver / Line Output Left PGA Volume Configuration
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4
DESCRIPTION
0
RCVLVOL[4:0]
R/W
1
0
1
0x1F : +8dB
0x1E : +7.5dB
0x1D : +7dB
0x1C : +6.5dB
0x1B : +6dB
0x1A : +5dB
0x19 : +4dB
0x18 : +3dB
0x0F : -12dB
0x0E : -14dB
0x0D : -17dB
0x0C : -20dB
0x0B : -23dB
0x0A : -26dB
0x09 : -29dB
0x08 : -32dB
0x17 : +2dB
0x16 : +1dB
0x15 : +0dB
0x14 : -2dB
0x13 : -4dB
0x12 : -6dB
0x11 : -8dB
0x10 : -10dB
0x07 : -35dB
0x06 : -38dB
0x05 : -42dB
0x04 : -46dB
0x03 : -50dB
0x02 : -54dB
0x01 : -58dB
0x00 : -62dB
Table 60: Right Line Output Mixer Source Configuration Register
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x3A
NAME
TYPE PoR
LINMOD
R/W
0
-
-
MIXRCVR[5:0]
R/W
0
0
0
0
0
0
DESCRIPTION
Selects Between Receiver BTL mode and Line Output mode
1 : LINEOUT mode. Receiver output is a stereo pair of line outputs. All control of
the Receiver output is from the left control bits.
0 : BTL mode. All control of the Receiver output is from the left control bits.
Selects DAC Left as the Input to the Line Out Right Mixer
Selects DAC Right as the Input to the Line Out Right Mixer
Selects Line A as the Input to the Line Out Right Mixer
Selects Line B as the Input to the Line Out Right Mixer
Selects MIC 1 as the Input to the Line Out Right Mixer
Selects MIC 2 as the Input to the Line Out Right Mixer
Table 61: Right Line Output Mixer Level Control Register
M
BIT
7
6
5
4
3
2
ADDRESS: 0x3B
NAME
TYPE PoR
-
1
MIXRCVRG[1:0]
R/W
0
DESCRIPTION
-
Line Output Right Mixer Gain Configuration.
00 : 0dB
10 : -9.5dB
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0
0
MAX98090
01 : -6dB
11 : -12dB
Note: these gains are relative to the maximum output signal. In Line Output Mode this is
1Vpk, while in receiver BTL mode it is 1Vrms differential.
Table 62: Right Line Output Volume Control Register
BIT
6
5
4
3
2
1
0
RCVRM
R/W
0
DESCRIPTION
Line Output Right Mute
0 : not muted
1 : muted
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7
ADDRESS: 0x3C
NAME
TYPE PoR
-
-
-
1
0
RCVRVOL[4:0]
R/W
1
0
1
-
Line Output Right PGA Volume Configuration
0x1F : +8dB
0x1E : +7.5dB
0x1D : +7dB
0x1C : +6.5dB
0x1B : +6dB
0x1A : +5dB
0x19 : +4dB
0x18 : +3dB
0x17 : +2dB
0x16 : +1dB
0x15 : +0dB
0x14 : -2dB
0x13 : -4dB
0x12 : -6dB
0x11 : -8dB
0x10 : -10dB
0x0F : -12dB
0x0E : -14dB
0x0D : -17dB
0x0C : -20dB
0x0B : -23dB
0x0A : -26dB
0x09 : -29dB
0x08 : -32dB
0x07 : -35dB
0x06 : -38dB
0x05 : -42dB
0x04 : -46dB
0x03 : -50dB
0x02 : -54dB
0x01 : -58dB
0x00 : -62dB
M
Line Output Gain Control
Line Output Mixer
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Click-and-Pop Reduction
The IC includes extensive click-and-pop reduction circuitry. The circuitry minimizes clicks and pops at turn-on,
turn-off, and during volume changes.
Zero-crossing detection is implemented on all analog PGAs and volume controls to prevent large glitches when
volume changes are made. Instead of making a volume change immediately, the change is made when the
audio signal crosses the midpoint. If no zero-crossing occurs within the timeout window, the change is forced.
AX P
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Volume slewing breaks up large volume changes into the smallest available step size and the steps through
each step between the initial and final volume setting. When enabled, volume slewing also occurs at device
turn-on and turn-off. During turn-on the volume is set to mute before the output is enabled. Once the output is
on, the volume ramps to the desired level. At turn-off the volume is ramped to mute before the outputs are
disabled.
When there is no audio signal zero-crossing detection can prevent volume slewing from occurring. Enable
enhanced volume slewing to prevent the volume controller from requesting another volume level until the
previous one has been set. Each step in the volume ramp then occurs after a zero crossing has occurred in the
audio signal or the timeout window has expired. During turn-off, enhance volume slewing is always disabled.
Table 63: Zero-Crossing Detection and Volume Smoothing Configuration Register
BIT
7
6
5
4
3
2
1
/ZDEN\
R/W
0
/VS2EN\
R/W
0
/VSEN\
R/W
0
DESCRIPTION
-
Zero-Crossing Detection
1 : Volume changes made immediately upon request.
0 : Volume changes made only at zero crossings in the audio waveform or after
approximately 100ms.
The following registers bits are affected by /ZDEN:
PGAM1, PGAM2, HPVOLL, HPVOLR, RECVOLL, RECVOLR, SPVOLL, SPVOLR
Enhanced Volume Smoothing
/VS2EN enhances the volume slew and is only used when /VSEN = 0.
1 : Enhancement disabled.
0 : Slewed volume changes wait until the previous volume step has been applied to
the output before changing to the next step.
The following register bits are affected by /VS2EN:
HPVOLL, HPVOLR, RECVOLL, RECVOLR, SPVOLL, SPVOLR
Volume Adjustment Smoothing
1 : Volume changes made by bypassing intermediate settings.
0 : Volume changes smoothed by stepping through intermediate values at a rate of
one setting every 1ms.
The following register bits are affected by /VSEN:
HPVOLL, HPVOLR, RECVOLL, RECVOLR, SPVOLL, SPVOLR
M
0
ADDRESS: 0x40
NAME
TYPE PoR
-
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Jack Detection
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The device features a software configurable jack detection block that can both sense the insertion and removal
of a jack, as well as identify the type of load inserted (headphone or headset). Figure 16 shows the typical
application circuit configuration for jack detection (and is the assumed configuration for the following sections)
Figure 16: Typical Application Circuit for Jack Detection
To detect a jack insertion/removal, the device must be powered (but may be operating in or out of shutdown
mode). Set JDETEN to enable the jack detection circuitry. When the device is in shutdown mode or the
microphone bias is disabled (MICBIAS is high impedance), an internal pull-up is enabled on JACKSNS, and is
referenced to the SPKLVDD supply. When the device is not in shutdown and the microphone bias is enabled,
the internal pull-up is disabled (JACKSNS is high impedance). In this state, successful jack detection requires
an external pull-up on JACKSNS to MICBIAS (Figure 16).
The device has both a strong and weak internal pull-up option. When JDWK is low (default, Table 64), the
strong internal pull-up is used (approximately 2.2kΩ referenced to SPKLVDD). This configuration is capable of
detecting and identifying both headphone and headset insertion. When JDWK is high, the weak internal pull-up
(approximately 5µA to SPKLVDD) is used. This minimizes the supply current however the weak internal pull-up
cannot identify headset insertion or accessory buttons.
Jack Insertion and Removal
The device detects jack insertion and removal by monitoring the voltage on JACKSNS with two internal
comparators. The output of these comparators is used to set the state of the Jack Status Register bits (LSNS
and JKSNS, Table 65). These comparators are only active when the JDETEN is set high. When the device is in
shutdown and JDETEN is low, LSNS and JKSNS will retain their previous state regardless of the jack status.
When JDETEN is set high, LSNS and JKSNS can report three possible jack states (Table TBD). When LSNS =
JKSNS = 1, jack detection is reporting that no jack is currently inserted. When LSNS = JKSNS = 0, jack
detection is reporting that a jack is inserted, but that no microphone load was detected (headset). When LSNS =
0 and JKSNS = 1, jack detection is reporting that a jack is inserted and that a microphone load is present
(Headset detection). If the weak internal pull-up is used, and the microphone bias is disabled, the jack detection
block will not be able to identify a microphone load and will report the headphone detection state even if a
headset is inserted.
When jack insertion or removal is detected (any change of state for LSNS and JKSNS), the Jack detection
change flag is set (JDET, Table 66). In addition to this, an interrupt on /IRQ\ (to alert the microcontroller of the
event) can also be triggered if IJDET is set (Table 67).
M
Accessory Button Detection
After jack insertion, the MAX98089 can detect button presses on accessories that include a microphone and a
switch that shorts the microphone signal to ground. Set JDETEN to enable jack detection circuitry. Button
presses can be detected either when MICBIAS is enabled or if it is disabled and the strong internal pull-up is
used (JDWK = 0). A button press will change the state of JKSNS from 1 to 0 until the button is released, and this
change in state will generate an event on the jack detection change flag (JDET).
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Table 64: Jack Detect Configuration Register
BIT
ADDRESS: 0x3D
NAME
TYPE PoR
JDETEN
R/W
0
6
JDWK
R/W
0
5
4
3
2
1
0
Jack Detect Enable
0 : Jack Detect Circuitry Disabled
1 : Jack Detect Circuitry Enabled
JACKSNS Pull-up Configuration
0 : 2.4kΩ resistor to SPKLVDD (allows microphone detection)
1 : 5uA to SPKLVDD (minimizes supply current)
When JDWK = 1, JACKSNS is slow to increase in voltage. Set JDWK = 0 before
setting JDETEN = 1 to prevent false detection. Valid when MBIAS = 0 or /SHDN = 0.
Jack Detect Debounce
Configures the jack detect debounce time
00 : 25ms
10 : 100ms
01 : 50ms
11 : 200ms
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7
DESCRIPTION
-
-
-
0
JDEB[1:0]
R/W
0
Table 65: Jack Status Register
BIT
7
6
5
4
3
2
LSNS
R
0
JKSNS
R
0
-
-
-
DESCRIPTION
Microphone Load Sense (Valid only if JDETEN = 1)
0 : VJACKSNS ≤ 0.95V x VSUPPLY
1 : VJACKSNS > 0.95V x VSUPPLY
VSUPPLY is determined by the state of MBEN and /SHDN\ such that:
MBEN = 0 or /SHDN\ = 0 : VSUPPLY = VSPKLVDD (Internal)
MBEN =1 and /SHDN\ = 1 : VSUPPLY = VMICBIAS (Configuration of Figure 16)
Jack Connection Sense (Valid only if JDETEN = 1)
0 : VJACKSNS < 0.1V x VSUPPLY
1 : VJACKSNS ≥ 0.1V x VSUPPLY
VSUPPLY is determined by the state of MBEN and /SHDN\ such that:
MBEN = 0 or /SHDN\ = 0 : VSUPPLY = VSPKLVDD (Internal)
MBEN =1 and /SHDN\ = 1 : VSUPPLY = VMICBIAS (Configuration of Figure 16)
-
M
1
ADDRESS: 0x02
NAME
TYPE PoR
-
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Device Status Flags
The device uses register 0x01 (Table 66) and /IRQ\ to report the status of various device functions. The status
register bits are set when their respective events occur, and cleared upon reading the register. Device status
can be determined either by poling register 0x01, or by configuring /IRQ\ to pull low when specific events occur.
/IRQ\ is an open-drain output that requires a pull-up resistor (10kΩ to TBD) for proper operation.
Table 66: Device Status Interrupt Register
7
6
5
4
3
2
1
Clipping Detect Flag
0 : No clipping has occurred.
1 : DAC or ADC clipping has occurred.
CLD reports that the DAC input data or ADC output data is clipping due to excessive
signal amplitude in the digital signal path. To resolve a clip condition in the signal path,
the DAC gain settings and analog input gain settings should be lowered. As the CLD bit
does not indicate where the overload has occurred, identify the source by lowering
gains individually.
Slew Level Detect Flag
0 : No volume slewing sequences have completed.
1 : Volume slewing complete.
SLD reports that any one of the programmable-gain arrays or volume controllers has
completed slews from a previous setting to a new programmed setting. If multiple gain
arrays or volume controllers are changed at the same time, in either the analog or
digital domain, SLD flag will be set after the last slew adjusting in each domain. SLD
also reports when the serial interface soft-start or soft-stop process has completed.
CLD
CoR
0
SLD
CoR
0
ULK
CoR
0
-
-
-
JDET
CoR
0
ALCACT
CoR
0
ALCCLP
CoR
0
Digital PLL Unlock Flag
0 : PLL is locked if enabled and operating properly.
1 : When enabled, either of the PLL is not locked.
ULK reports that the digital audio phase-locked loop for either interface became
unlocked and input digital signal data is unreliable.
Jack Configuration Change Flag
0 : No change in jack configuration.
1 : Jack configuration has changed.
JDET reports changes to any bits in the Jack Status register. Changes to the Jack
Status bits are debounced before setting JDET. The debounce period is programmable
using the JDEB bits.
ALC Compression Flag
0 : The ALC is either disabled or not in the compression region.
1 : The ALC is operating in the compression region.
ALC Clipping Flag
0 : The ALC is either disabled or no clipping has occurred.
1 : ALC clipping has occurred.
M
0
DESCRIPTION
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BIT
ADDRESS: 0x01
NAME
TYPE PoR
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Status Flag Masking
Register 0x03, the device status interrupt mask register (Table 67) determines which bits in the device status
interrupt register (Table 66) can trigger a hardware interrupt on /IRQ\ (assert low). By default, all of the device
status interrupts (except JDET) will only set the corresponding status bit and will not generate a hardware
interrupt. Set the corresponding bit high in the mask register to enable hardware interrupts.
Table 67: Device Status Interrupt Mask Register
7
6
5
4
3
2
1
R/W
0
ISLD
R/W
0
IULK
R/W
0
-
-
-
IJDET
R/W
1
IALCACT
R/W
0
IALCCLP
R/W
0
Clipping Detect Interrupt Enable
0 : Clipping detection only sets CLD (0x01[7]).
1 : Clipping detection triggers /IRQ\ and sets CLD (0x02[7]).
Slew Level Detect Interrupt Enable
0 : Slew level detection only sets SLD (0x01[6]).
1 : Slew level detection triggers /IRQ\ and sets SLD (0x02[6]).
Digital PLL Unlock Interrupt Enable
0 : PLL Unlock Condition only sets ULK (0x01[5]).
1 : PLL Unlock Condition triggers /IRQ\ and sets ULK (0x02[5]).
Jack Configuration Change Interrupt Enable
0 : Changes in headset configuration only sets JDET (0x01[2]).
1 : Changes in headset configuration triggers /IRQ\ and sets JDET (0x01[2]).
ALC Compression Interrupt Enable
0 : ALC compression only sets ALCACT (0x01[1]).
1 : ALC compression triggers /IRQ\ and sets ALCACT (0x01[1]).
ALC Clipping Interrupt Enable
0 : ALC clipping only sets ALCCLP (0x01[0]).
1 : ALC clipping triggers /IRQ\ and sets ALCCLP (0x01[0]).
M
0
ICLD
DESCRIPTION
AX P
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BIT
ADDRESS: 0x03
NAME
TYPE PoR
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Quick Setup Configuration
Table 68: System Clock Quick Setup Register
1
0
DESCRIPTION
Setup Device for Operation with a 26MHz Master Clock (MCLK)
Setup Device for Operation with a 19.2MHz Master Clock (MCLK)
Setup Device for Operation with a 13MHz Master Clock (MCLK)
Setup Device for Operation with a 12.288MHz Master Clock (MCLK)
Setup Device for Operation with a 12MHz Master Clock (MCLK)
Setup Device for Operation with a 11.2896MHz Master Clock (MCLK)
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BIT
7
6
5
4
3
2
ADDRESS: 0x04
NAME
TYPE PoR
26M
W
0
19P2M
W
0
13M
W
0
12P288M
W
0
12M
W
0
11P2896M
W
0
-
-
-
256FS
W
0
-
Setup Device for Operation with a 256 x fS MHz Master Clock (MCLK)
Table 69: Sample Rate Quick Setup Register
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x05
NAME
TYPE PoR
SR_96K
W
0
SR_32K
W
0
SR_48K
W
0
SR_44K1
W
0
SR_16K
W
0
SR_8K
W
0
DESCRIPTION
Setup Clocks and Filters for a 96kHz Sample Rate
Setup Clocks and Filters for a 32kHz Sample Rate
Setup Clocks and Filters for a 48kHz Sample Rate
Setup Clocks and Filters for a 44.1kHz Sample Rate
Setup Clocks and Filters for a 16kHz Sample Rate
Setup Clocks and Filters for an 8kHz Sample Rate
Table 70: Digital Audio Interface (DAI) Quick Setup Register
ADDRESS: 0x06
NAME
TYPE PoR
RJ_M
W
0
RJ_S
W
0
LJ_M
W
0
LJ_S
W
0
I2S_M
W
0
I2S_S
W
0
DESCRIPTION
Setup DAI for Right Justified Master Mode Operation
Setup DAI for Right Justified Slave Mode Operation
Setup DAI for Left Justified Master Mode Operation
Setup DAI for Left Justified Slave Mode Operation
Setup DAI for I2S Master Mode Operation
Setup DAI for I2S Slave Mode Operation
M
BIT
7
6
5
4
3
2
1
0
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Table 71: Digital to Analog Converter (DAC) Path Quick Setup Register
DESCRIPTION
Setup the DAC to Headphone Path
Setup the DAC to Receiver Path
Setup the DAC to Speaker Path
Setup the DAC to Line Out Path
-
AX P
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BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x07
NAME
TYPE PoR
DIG2_HP
W
0
DIG2_EAR
W
0
DIG2_SPK
W
0
DIG2_LOUT
W
0
-
Table 72: Microphone / Direct to Analog to Digital Converter (ADC) Path Quick Setup Register
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x08
NAME
TYPE PoR
IN12_MIC1
W
0
IN34_MIC2
W
0
IN56_MIC1
W
0
IN56_MIC2
W
0
IN12_DADC
W
0
IN34_DADC
W
0
IN56_DADC
W
0
-
DESCRIPTION
Setup the IN1-IN2 to Microphone 1 to ADCL Path
Setup the IN3-IN4 to Microphone 2 to ADCR Path
Setup the IN6-IN5 to Microphone 1 to ADCL Path (WLP Only)
Setup the IN6-IN5 to Microphone 2 to ADCR Path (WLP Only)
Setup the IN1-IN2 Direct to ADCL Path
Setup the IN3-IN4 Direct to ADCR Path
Setup the IN6-IN5 Direct to ADCL Path (WLP Only)
-
Table 73: Line Input to Analog to Digital Converter (ADC) Path Quick Setup Register
DESCRIPTION
Setup Stereo Single Ended Record: IN1/IN2 to Line In A/B to ADCL/R
Setup Stereo Single Ended Record: IN3/IN4 to Line In A/B to ADCL/R
Setup Stereo Single Ended Record: IN5/IN6 to Line In A/B to ADCL/R (WLP Only)
Setup Mono Differential Record: IN3-IN4 to Line In A to ADCL
Setup Mono Differential Record: IN6-IN5 to Line In B to ADCR (WLP Only)
-
M
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x09
NAME
TYPE PoR
IN12S_AB
W
0
IN34S_AB
W
0
IN56S_AB
W
0
IN34D_A
W
0
IN56D_B
W
0
-
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Table 74: Analog Microphone Input to Analog Output Loop Quick Setup Register
DESCRIPTION
Setup the IN1-IN2 Differential to Microphone 1 to Headphone Left Path
Setup the IN1-IN2 Differential to Microphone 1 to Speaker Left Path
Setup the IN1-IN2 Differential to Microphone 1 to Receiver Path
Setup the IN1-IN2 Differential to Microphone 1 to Lineout Left Path
Setup the IN3-IN4 Differential to Microphone 2 to Headphone Left Path
Setup the IN3-IN4 Differential to Microphone 2 to Speaker Left Path
Setup the IN3-IN4 Differential to Microphone 2 to Receiver Path
Setup the IN3-IN4 Differential to Microphone 2 to Lineout Left Path
AX P
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BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x0A
NAME
TYPE PoR
IN12_M1HPL
W
0
IN12_M1SPKL
W
0
IN12_M1EAR
W
0
IN12_M1LOUTL
W
0
IN34_M2HPR
W
0
IN34_M2SPKR
W
0
IN34_M2EAR
W
0
IN34_M2LOUTR
W
0
Table 75: Analog Line Input to Analog Output Loop Quick Setup Register
BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x0B
NAME
TYPE PoR
IN12S_ABHP
W
0
IN34D_ASPKL
W
0
IN34D_AEAR
W
0
IN12S_ABLOUT
W
0
IN34S_ABHP
W
0
IN56D_BSPKR
W
0
IN56D_BEAR
W
0
IN34S_ABLOUT
W
0
DESCRIPTION
Setup the IN1/IN2 Single Ended to Line In A/B to Headphone L/R Path
Setup the IN3-IN4 Differential to Line In A to Speaker Left Path
Setup the IN3-IN4 Differential to Line In A to Receiver Path
Setup the IN1/IN2 Single Ended to Line In A/B to Lineout L/R Path
Setup the IN3/IN4 Single Ended to Line In A/B to Headphone L/R Path
Setup the IN6-IN5 Differential to Line In B to Speaker Right Path (WLP Only)
Setup the IN6-IN5 Differential to Line In B to Receiver Path (WLP Only)
Setup the IN3/IN4 Single Ended to Line In A/B to Lineout L/R Path
Software Reset
The device provides a software reset (SWRESET, Table 76) that is used to return most registers to their default
(PoR) states (The ADC Biquad and DAC Equalizer coefficient registers are not reset). The software reset
register is a pushbutton, write only register. As a result, a read of this register always returns 0x00. Writing a
logic high to SWRESET triggers a software register reset, while writing a logic low to SWRESET has no effect.
Table 76: Software Reset Register
BIT
7
SWRESET
W
0
-
-
-
M
6
5
4
3
2
1
0
ADDRESS: 0x00
NAME
TYPE PoR
DESCRIPTION
Pushbutton Software Device Reset
0 : Writing a logic low to SWRESET has no effect.
1 : Reset all registers to their default PoR values. This excludes the ADC Biquad and
DAC Equalizer filter coefficients (Table 23).
-
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Device Revision Identification
The device provides a Revision ID Number register to allow the software to identify the current version of the
device. The current device revision ID value is 0x42.
Table 77: Revision ID Number Register
DESCRIPTION
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BIT
7
6
5
4
3
2
1
0
ADDRESS: 0x45
NAME
TYPE PoR
0
1
0
0
REV_ID[7:0]
R
0
0
1
0
2
Read back the revision ID of the device
I2C Serial Interface
The MAX98090 features an I C/SMBus™-compatible, 2-wire serial interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the MAX98090 and the
master at clock rates up to 400kHz. Error! Reference source not found.TBD shows the 2-wire interface timing
diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the
MAX98090 by transmitting the proper slave address followed by the register address and then the data word.
Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P)
condition. Each word transmitted to the MAX98090 is 8 bits long and is followed by an acknowledge clock pulse.
A master reading data from the MAX98090 transmits the proper slave address followed by a series of nine SCL
pulses. The MAX98090 transmits data on SDA in sync with the master-generated SCL pulses. The master
acknowledges receipt of each byte of data. Each read sequence is framed by a START (S) or REPEATED
START (Sr) condition, a not acknowledge, and a STOP (P) condition. SDA operates as both an input and an
open-drain output. A pull-up resistor, typically greater than 500Ω, is required on SDA. SCL operates only as an
input. A pull-up resistor, typically greater than 500Ω, is required on SCL if there are multiple masters on the bus,
or if the single master has an open-drain SCL output. Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX98090 from high voltage spikes on the bus lines, and
minimize crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions
section).
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START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START
condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-tohigh transition on SDA while SCL is high (Figure 17). A START condition from the master signals the beginning
of a transmission to the MAX98090. The master terminates transmission, and frees the bus, by issuing a STOP
condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition.
Early STOP Conditions
The MAX98090 recognizes a STOP condition at any point during data transmission except if the STOP
condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP
condition during the same SCL high pulse as the START condition.
Slave Address
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The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For the
MAX98090A, the seven most significant bits are 0010000. Setting the read/write bit to 1 (slave address = 0x21)
configures the MAX98090A for read mode. Setting the read/write bit to 0 (slave address = 0x20) configures the
MAX98090A for write mode. The address is the first byte of information sent to the MAX98090 after the START
condition. Similarly, for the MAX98090B, the seven most significant bits are 0010001. Setting the read/write bit
to 1 (slave address = 0x23) configures the MAX98090B for read mode. Setting the read/write bit to 0 (slave
address = 0x22) configures the MAX98090B for write mode.
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Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the MAX98090_ uses to handshake receipt each byte of
data when in write mode (Figure 18). The MAX98090_ pulls down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer, the bus master will retry communication. The master
pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the MAX98090_ is in read
mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A notacknowledge is sent when the master reads the final byte of data from the MAX98090_, followed by a STOP
condition.
-
Figure 17: START, STOP, and REPEATED START Conditions
Figure 18: Acknowledge
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Write Data Format
A write to the MAX98090_ includes transmission of a START condition, the slave address with the R//W\ bit set
to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP
condition. Figure 19 illustrates the proper frame format for writing one byte of data to the MAX98090_. Figure 20
illustrates the frame format for writing n-bytes of data to the MAX98090_.
The slave address with the R//W\ bit set to 0 indicates that the master intends to write data to the MAX98090.
The MAX98090_ acknowledges receipt of the address byte during the master-generated 9th SCL pulse.
The second byte transmitted from the master configures the MAX98090_’s internal register address pointer. The
pointer tells the MAX98090_ where to write the next byte of data. An acknowledge pulse is sent by the
MAX98090 upon receipt of the address pointer data.
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The third byte sent to the MAX98090_ contains the data that will be written to the chosen register. An
acknowledge pulse from the MAX98090_ signals receipt of the data byte. The address pointer auto increments
to the next register address after each received data byte. This auto-increment feature allows a master to write
to sequential registers within one continuous frame. The master signals the end of transmission by issuing a
STOP condition. Register addresses greater than 0xE7 are reserved. Do not write to these addresses.
ACKNOWLEDGE FROM AX36
B7
ACKNOWLEDGE FROM AX36
B6
B5
B4
B3
B2
B1
B0
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ACKNOWLEDGE FROM AX36
S
SLAVE ADDRESS
0
A
REGISTER ADDRESS
R/W
A
DAT A BYTE
A
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 19: Writing One Byte of Data to the MAX98090.
Figure 20: Writing n-Bytes of Data to the MAX98090
Read Data Format
Send the slave address with the R//W\ bit set to 1 to initiate a read operation. The MAX98090_ acknowledges
receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START command followed by
a read command resets the address pointer to register 0x00.
The first byte transmitted from the MAX98090_ will be the contents of register 0x00. Transmitted data is valid on
the rising edge of SCL. The address pointer auto-increments after each read data byte. This auto-increment
feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued
after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first
data byte to be read will be from register 0x00.
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The address pointer can be preset to a specific register before a read command is issued. The master presets
the address pointer by first sending the MAX98090’s slave address with the R//W\ bit set to 0 followed by the
register address. A REPEATED START condition is then sent followed by the slave address with the R//W\ bit
set to 1. The MAX98090_ then transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte.
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The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not
acknowledge from the master and then a STOP condition. Figure 21 illustrates the frame format for reading one
byte from the MAX98090_. Figure 22 illustrates the frame format for reading multiple bytes from the
MAX98090_.
Figure 21: Reading One Byte of Data from the MAX98090_
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Figure 22: Reading n-Bytes of Data from the MAX98090_
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_________________________________________ APPLICATIONS INFORMATION
Typical Application Circuits
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Figures are two example application circuits for the device. The external components shown are the minimum
required for the device to operate. Additional application specific components may be required.
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Figure 23: Typical Application Circuit with Analog Microphone Inputs and Receiver Output
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Figure 24: Typical Application Circuit with Digital Microphone Input and Stereo Line Outputs
Startup / Shutdown Register Sequencing
To ensure proper device initialization and minimal click-and-pop, program the devices control registers in the
correct order. To shutdown the MAX98090, simply set /SHDN\ = 0. Table 78 details an example startup
sequence for the device. To minimize click and pop on the analog output drivers (headphones, speakers,
receiver, and line outputs), the output drivers should be powered using the following sequence:
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1. Prior to powering the device (/SHDN\ = 0) and before enabling the outputs, the output driver mute(s)
should be enabled and the PGA gain(s) should be set to their lowest setting.
2. After all configuration settings are complete, power up the device (/SHDN\ = 1).
3. Enable any analog outputs that are part of the desired configuration.
4. Disable the mute on each respective analog output.
Ramp the volume up, one register step at a time, from the minimum setting until the desired volume (gain) is
reached (this sequence is part of the example in Table 78).
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Table 78: Device Startup Sequence
SEQUENCE
1
2
3
DESCRIPTION
Set /SHDN\ = 0
Configure Clocks
Configure Digital Audio Interface (DAI)
Configure Digital Signal processing (DSP)
5
6
Load Coefficients
Configure Power and Bias Mode
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4
REGISTERS
0x45 (Default PoR State)
0x1B to 0x21
0x22 to 0x25
0x17 to 0x1A, 0x26 to 0x28,
0x33 to 0x36, 0x41
0x46 to 0xBD
0x42 to 0x44
0x0D, 0x15, 0x16, 0x29, 0x2A,
0x2B, 0x2E, 0x2F, 0x37, 0x3A
0x0E to 0x11, 0x2B to 0x2D,
0x30 to 0x32, 0x38, 0x39,
0x3B, 0x3C
0x03, 0x12, 0x13, 0x14, 0x40
0x45
0x3D to 0x3F
0x2C, 0x2D, 0x31,
0x32, 0x39, 0x3C
0x30 to 0x32, 0x38, 0x39,
0x3B, 0x3C
7
Configure Analog Mixers
9
11
10
Configure Analog Gain and Volume Controls. To Minimize
Click and Pop for Analog Outputs, Enable Mute and Set the
Output PGAs to the minimum gain setting.
Configure Miscellaneous Functions
Set /SHDN\ = 1 (Power Up)
Enable Desired Functions
11
Disable Mute on Analog Output Drivers
12
For all Analog Output Drivers, Ramp the Gain up One
Volume Step per Write until the Desired Gain is Reached
8
While many configuration options and settings can be changed while the device is operating (/SHDN\ = 1), some
registers should only be adjusted with the device in shutdown (/SHDN\ = 0). Table 79 lists the registers that
should not be changed during active operation.
Table 79: Register Changes that Require /SHDN\ = 0
DESCRIPTION
Clock Control Registers
Bias Control
Digital Signal Processing
Coefficients
REGISTER
0x04, 0x05, 0x1B to 0x20
0x42 to 0x44
0x46 to 0xBD
Component Selection
AC Coupling Capacitors
An input capacitor, CIN, in conjunction with the input impedance of the MAX98090 line inputs forms a high pass
filter that removes the DC bias from an incoming analog signal. The AC coupling capacitor allows the amplifier
to automatically bias the signal to an optimum DC level. Assuming very low source impedance (comparatively),
the -3dB point of the high pass filter is given by:
f 3dB 
1
2  RIN  C IN
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Choose CIN such that f-3dB is well below the lowest frequency of interest. For best audio quality use capacitors
whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with highvoltage coefficients, such as ceramics, may result in increased distortion at low frequencies. If needed, line
output AC coupling capacitor values can be calculated in similar fashion by using the input resistance of the
output stage connected to the line output drivers.
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Charge-Pump Capacitor Selection
Use capacitors with an ESR less than 100mΩfor optimum performance. Low-ESR ceramic capacitors minimize
the output resistance of the charge pump. Most surface mount ceramic capacitors satisfy the ESR requirement.
For best performance over the extended temperature range, select capacitors with an X7R dielectric.
The value of the flying capacitor (connected between C1N and C1P) affects the output resistance of the charge
pump. A value that is too small degrades the device’s ability to provide sufficient current drive, which leads to a
loss of output voltage. Increasing the value of the flying capacitor reduces the charge-pump output resistance to
an extent. Above 1μF, the on-resistance of the internal switches and the ESR of external charge pump
capacitors dominate.
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The holding capacitor (bypassing HPVSS) value and ESR directly affect the ripple at HPVSS. Increasing the
capacitor’s value reduces output ripple. Likewise, decreasing the ESR reduces both ripple and output
resistance. Lower capacitance values can be used in systems with low maximum output power levels. See the
Output Power vs. Load Resistance graph in the Typical Operating Characteristics for more information.
Filterless Class D Speaker Operation
Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier’s output. The
filters add cost, increase the solution size of the amplifier, and can decrease efficiency and THD+N
performance. The traditional PWM scheme uses large differential output swings (2 x SPKVDD peak to peak)
and causes large ripple currents. Any parasitic resistance in the filter components results in a loss of power,
lowering the efficiency.
The IC does not require an output filter. The device relies on the inherent inductance of the speaker coil and the
natural filtering of both the speaker and the human ear to recover the audio component of the square-wave
output. Eliminating the output filter results in a smaller, less costly, and more efficient solution.
Because the frequency of the IC’s output is well beyond the bandwidth of most speakers, voice coil movement
due to the square-wave frequency is very small. Although this movement is small, a speaker not designed to
handle the additional power can be damaged. For optimum results, use a speaker with a series inductance >
10µH. Typical 8Ω speakers exhibit series inductances in the 20µH to 100µH range.
EMI Considerations and Optional Ferrite Bead Filter
Reducing trace length minimizes radiated EMI. On the PCB, route SPKLP/SPKLN and SPKRP/SPKRN as
differential pairs with the shortest trace lengths possible. This will minimize trace loop area, and thereby the
inductance of the circuit. If filter components are used on the speaker outputs, minimize the trace length from
any ground tied passive components to SPK_GND to further minimize radiated EMI.
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In applications where speaker leads exceed 20mm, additional EMI suppression can be achieved by using a filter
constructed from a ferrite bead and a capacitor to ground (Figure 25). Use a ferrite bead with low DC resistance,
high frequency (>600MHz) impedance between 100Ω and 600Ω, and rated for at least 1A. The capacitor value
varies based on the ferrite bead chosen and the actual speaker lead length. Select a capacitor less than 1nF,
with the value based upon optimizing EMI performance.
Figure 25. Optional Class D Ferrite Bead Filter
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RF Susceptibility
GSM radios transmit using time-division multiple access (TDMA) with 217Hz intervals. The result is an RF signal
with strong amplitude modulation at 217Hz and its harmonics that is easily demodulated by audio amplifiers.
The MAX98090 is designed specifically to reject RF signals; however, PCB layout has a large impact on the
susceptibility of the end product.
In RF applications, improvements to both layout and component selection decreases the MAX98090’s
susceptibility to RF noise and prevent RF signals from being demodulated into audible noise. Trace lengths
should be kept below 1/4 of the wavelength of the RF frequency of interest. Minimizing the trace lengths
prevents them from functioning as antennas and coupling RF signals into the MAX98090. The wavelength () in
meters is given by:  = c / f where c = 3 x 108 m/s, and f = the RF frequency of interest.
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Route audio signals on middle layers of the PCB to allow ground planes above and below to shield them from
RF interference. Ideally the top and bottom layers of the PCB should primarily be ground planes to create
effective shielding.
Additional RF immunity can also be obtained by relying on the self-resonant frequency of capacitors, as it
exhibits a frequency response similar to a notch filter. Depending on the manufacturer, 10pF to 20pF capacitors
typically exhibit self resonance at RF frequencies. These capacitors, when placed at the input pins, can
effectively shunt the RF noise at the inputs of the MAX98090. For these capacitors to be effective, they must
have a low-impedance, low-inductance path to the ground plane. Avoid using micro-vias to connect to the
ground plane as these vias do not conduct well at RF frequencies.
Supply Bypassing, Layout, and Grounding
Proper layout and grounding are essential for optimum performance. When designing a PCB for the
MAX98090, partition the circuitry so that the analog sections of the MAX98090 are separated from the digital
sections. This ensures that the analog audio traces are not routed near digital traces.
Use a large continuous ground plane on a dedicated layer of the PCB to minimize loop areas. Connect AGND,
DGND, and HPGND directly to the ground plane using the shortest trace length possible. Proper grounding
improves audio performance, minimizes crosstalk between channels, and prevents any digital noise from
coupling into the analog audio signals.
Ground the bypass capacitors on MICBIAS, VCM and REF directly to the ground plane with minimum trace
length. Also be sure to minimize the path length to AGND, and bypass AVDD directly to AGND. Connect all
digital I/O termination to the ground plane with minimum path length to DGND, and bypass DVDD and DVDDIO
directly to DGND.
Place the capacitor between C1P and C1N as close to the MAX98090 as possible to minimize trace length from
C1P to C1N. Inductance and resistance added between C1P and C1N reduce the output power of the
headphone amplifier. Bypass HPVDD, CPVDD and CPVSS with capacitors located close to the pin with short
trace lengths to HPGND. Close decoupling of CPVDD and CPVSS minimizes supply ripple and maximizes
output power from the headphone amplifier.
HPSNS senses ground noise on the headphone jack and adds the same noise to the output audio signal,
thereby making the output (headphone output – ground) noise free. Connect HPSNS to the headphone jack
shield to ensure accurate pickup of headphone ground noise.
Bypass SPK_VDD to SPK_GND with the shortest trace length possible and connect SPKLP, SPKLN, SPKRP,
and SPKRN to the stereo speakers using the shortest traces possible. If filter components are used on the
speaker outputs, be sure to locate them as close to the MAX98090 as possible to ensure maximum
effectiveness.
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Route microphone signals from the microphone to the MAX98090 as a differential pair, ensuring that the
positive and negative signals follow the same path as closely as possible with equal trace length. When using
single-ended microphones or other single-ended audio sources, ground the negative microphone input as near
to the audio source as possible and then treat the positive and negative traces as differential pairs.
An evaluation kit (EV Kit) is available to provide an example layout for the MAX98090. The EV Kit allows quick
setup of the MAX98090 and includes easy-to-use software allowing all internal registers to be controlled.
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Recommended PCB Routing
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The IC uses a 49-bump WLP package. Figure 26 provides an example of how to connect to all active bumps
using 3 layers of the PCB. To ensure uninterrupted ground returns, use layer 2 as a connecting layer between
layer 1 and layer 2 and flood the remaining area with ground.
Figure 26: WLP Package Suggested Routing for MAX98090
Unused Pins
Table TBD shows how to connect the IC pins when circuit blocks are unused.
WLP Applications Information
For the latest application details on WLP construction, dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability
testing results, refer to the Application Note: UCSP - A Wafer-Level Chip-Scale Package on Maxim’s website at
www.maxim-ic.com/ucsp. Figure 27 shows the dimensions of the WLP balls used on the MAX98090.
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Figure 27: MAX98090 WLP Ball Dimensions
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______________________________________________ PACKAGE INFORMATION
DOCUMENT NO.
21-0443
21-0140
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For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
49 - WLP
W493B3+2
40 - TQFN
T4055+1
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___________________________________________________ REVISION HISTORY
REVISION
NUMBER
0.1
0.5
0.6
0.7
DESCRIPTION
Initial draft release
Second draft release
Third draft release
Fourth draft release
Fifth draft release (Front Page, EC table, TOC, Register Map
and Description, Applications Information, Etc. Updates)
PAGES
CHANGED
—
Significant updates
Significant updates
Significant updates
Significant updates
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0.8
REVISION
DATE
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