Cypress Product Roadmap

Cypress Product
Roadmap
Q1 2017
Document No. 001-89435 Rev. *P
Roadmap Slide Index
Page
Topic
3
Wireless Solutions for The IoT
33
Modules
44
MCU Portfolio
72
CapSense® Controllers
84
USB Controllers
96
Asynchronous SRAM
101
Synchronous SRAM
106
Nonvolatile RAM
113
Timing Solutions
120
Specialty Memory
122
Flash Memory
145
Military Memory
156
Aerospace Memory
160
Energy Harvesting PMIC
167
Automotive Products
Document No. 001-89435 Rev. *P
2
Wireless Solutions for the IoT
Document No. 001-89435 Rev. *P
3
Integration and Performance
Bluetooth
Wi-Fi
Wi-Fi + Bluetooth Combo
Automotive
IEEE 802.11a/b/g/n/ac WLAN1 + Bluetooth
Up to 867 Mbps Wi-Fi, 1-3 Mbps Bluetooth
Dual Band (2.4/5 GHz), 2x2 MIMO2
IEEE 802.11a/b/g/n/ac WLAN + Bluetooth
Up to 867 Mbps, Dual Band (2.4/5 GHz),
2x2 MIMO, 1+1RSDB3
IEEE 802.11a/b/g/n WLAN + Bluetooth
Up to 300 Mbps Wi-Fi, 1-3 Mbps Bluetooth
Dual Band (2.4/5 GHz), 2x2 MIMO
IEEE 802.11a/b/g/n/ac WLAN + Bluetooth
Up to 433 Mbps PHY rate
Dual Band (2.4/5 GHz), 1x1
IEEE 802.11a/b/g/n WLAN + MCU
Up to 150 Mbps
ARM® Cortex®-R4/-M3 MCU
Wireless Portfolio
IEEE 802.11a/b/g/n WLAN
Up to 150 Mbps
2x2 MIMO
Bluetooth (BR4 + EDR5 + BLE6) + MCU
1-3 Mbps,
Class 1/2/37, ARM Cortex®-M4/-M3 MCU
Bluetooth (BR + EDR)
1-3 Mbps
Class 1/2/3
Bluetooth Low Energy (BLE) + MCU
1-2 Mbps,
ARM Cortex®-M3 MCU
1
4
2 Multiple-input
5 Enhanced
Wireless Local Area Network
multiple-output
3 Read simultaneous dual band
Document No. 001-89435 Rev. *P
Basic Rate
Data Rate
6 Bluetooth Low Energy
7
8
Class 1 (100 m)/2 (10 m)/3 (1 m)
Concept
Development
Sampling
Production
QQYY
QQYY
Status
Availability
4
Wireless Solutions for The IoT Roadmap
• BLE PORTFOLIO
Document No. 001-89435 Rev. *P
5
Bluetooth Low Energy (BLE) Portfolio
BLE + MCU
Q217
BCM20719
CM41, SPI, UART, I2C2,
IR TX/RX3, ADC, 6 PWM,
KB Scanner4, Mouse QD5,
Crypto6, 4 TRIAC Control,
40 GPIO, 1MB Flash,
512KB RAM, BT7 4.2,
2 Mbps support, WICED SDK8
BCM20737
CM3, SPI, UART, I2C,
IR TX/RX, ADC, 4 PWM,
LE Audio, NFC9, Crypto,
14 GPIO, 60KB RAM,
BT 4.1, WICED SDK
BCM20736
CM3, SPI, UART, I2C,
IR TX/RX, ADC, A4WP10,
4 PWM, 40 GPIO, 60KB RAM,
BT 4.1, WICED SDK
Integration and Flexibility
1
6
2
ARM® Cortex®-M0/M0+/M3/M4
Broadcom serial communications block
3 Infrared transmit and receive
4 Keyboard scanner
5 Mouse quadrature decoder
7
Document No. 001-89435 Rev. *P
Cryptographic accelerator block for security
Bluetooth Specification
8 Software development kit
9 Out-of-Band pairing with NFC
10 Alliance for Wireless Power BLE Profile
Concept
Development
Sampling
Production
QQYY
QQYY
Status
Availability
6
BCM20737
Bluetooth Low Energy Connectivity MCU with Security and Wireless Charging
Features
Industry’s Most-Widely-Deployed BLE Stack
Bluetooth Low Energy (BLE) Features
Bluetooth 4.1 compliant
Simultaneous multiple Master and Slave (1M, 3S)
Alliance for Wireless Charging (A4WP) support
Proprietary low-energy audio (LE Audio) support
Out-of-band (OOB) pairing using near-field communication (NFC)
Secure over-the-air (OTA) firmware upgrade
Security Engine
RSA, X.509, SHA, AES128
Packages
32-pin QFN (5 x 5 mm), 80-ball WLCSP (2.2 x 2.2 mm)
FCC and CE-certified 6.5 x 6.5 x 1.2-mm modules with antenna
WICED™ SMART SDK 2.1 (and later)
Collateral
Datasheet:
BCM20737
Software:
WICED SMART SDK
Quick Start Guide: WICED SMART SDK 2.x
BCM92073x_LE_TAG4
BLE Connectivity MCU
MCU Subsystem
16-bit
DelSig
ADC1
Cortex®-M3
24 MHz
SRAM
(60KB)
ROM (320KB)
Communication
Interfaces
BLE Stack
Security Engine
Profiles
A4WP
I/O Subsystem
GPIO x14
Digital Peripherals
IR RX/TX
UART x2
PWM x4
I2C/SPI
Master
NFC
LE Audio
SPI
BLE System
(Bluetooth 4.1)
JTAG Debug
Availability
Production:
1 Effective
Analog Peripheral
I/O Ring Bus
Wearables, medical, home automation, toys
Block Diagram
System Bus
Applications
Now
number of bits is 10 at 187 ksps
Document No. 001-89435 Rev. *P
7
BCM20736
Bluetooth Low Energy Connectivity MCU with Wireless Charging
Features
Industry’s Most-Widely-Deployed BLE Stack
Bluetooth Low Energy (BLE) Features
Bluetooth 4.1 compliant
Support for all standard Bluetooth 4.1 low-energy profiles including
Alliance for Wireless Charging (A4WP)
Simultaneous multiple Master and Slave (1M, 1S)
Pre-standard BLE mesh
Over-the-air (OTA) firmware upgrade
Packages
32-pin QFN (5 x 5 mm)
80-ball WLCSP (2.2 x 2.2 mm)
FCC and CE-certified 6.5 x 6.5 x 1.2-mm modules with antenna
BLE Connectivity MCU
MCU Subsystem
Analog Peripheral
16-bit
DelSig
ADC1
Cortex®-M3
24 MHz
SRAM
(60KB)
ROM (320KB)
Communication
Interfaces
BLE Stack
Profiles
A4WP
I/O Subsystem
I/O Ring Bus
Beacons, tags, toys, industrial/home automation
Block Diagram
System Bus
Applications
GPIO x40
Digital Peripherals
IR RX/TX
UART x2
PWM x4
I2C/SPI
Master
SPI
WICED™ SMART SDK 2.1 (and later)
Collateral
Datasheet:
BCM20736
Software:
WICED SMART SDK
Quick Start Guide: WICED SMART SDK 2.x
BCM92073x_LE_TAG4
BLE System
(Bluetooth 4.1)
JTAG Debug
Availability
Production:
1 Effective
Now
number of bits is 10 at 187 ksps
Document No. 001-89435 Rev. *P
8
BCM20719
Ultra Low Power Bluetooth Smart Ready Connectivity Secure MCU
Applications
Medical, home automation, wearables, POS
Block Diagram
BLE Connectivity MCU
MCU Subsystem
Analog Peripheral
I/O Subsystem
Bluetooth Low Energy (BLE) Features
Bluetooth 4.2-compliance with LE privacy 1.2, LE data length
extension, LE secure connections
Industry’s lowest-power radio
Proprietary low energy audio (LE Audio) support
2-Mbps proprietary BLE support
ARM® Cortex®-M4 CPU with Floating-Point Unit, Digital-Signal
Processing Logic and 1MB Flash
MIPI-Compliant Display Driver
Security Engine
Public key accelerator (PKA), SHA, AES, RSA, Elliptic Curve
Diffie Hellman (ECDH)
Packages
40-pin QFN (5 x 5 mm)
80-ball WLCSP (2.2 x 2.2 mm)
16-bit
DelSig
ADC1
Cortex®-M4
96 MHz
SRAM
(512KB)
Flash
(1MB)
ROM
(2MB)
BR/BLE Stack
Profiles
BR/BLE/2-Mbps
Subsystem
(Bluetooth 4.2)
JTAG Debug
32-kHz/128-kHz
On-Chip OSC
Advanced High-Performance Bus (AHB)
Industry’s Most-Widely-Deployed Bluetooth Stack
I/O Ring Bus
Features
TRIAC Control
x4
Communication
Interfaces
GPIO x40
Digital Peripherals
IR RX/TX
UART x2
PWM x6
I2C/SPI Master
Keyboard
Scanner
SPI/Dual SPI/
Quad SPI/MIPI
Quad Decoder
Security Engine
PKA
SHA
AES
WICED™ SMART Ready SDK
Collateral
Datasheet: BCM20719 (Contact Sales)
Software: WICED SMART Ready SDK (Contact Sales)
1 Effective
Availability
Sampling:
Production:
Q416
Q117
number of bits is 10 at 187 ksps
Document No. 001-89435 Rev. *P
9
Wireless Solutions for The IoT Roadmap
• Bluetooth Classic + BLE Portfolio
Document No. 001-89435 Rev. *P
10
Bluetooth Classic + BLE Portfolio
CPU Performance
BR1 +BLE
BR + EDR2 + BLE3
Q217
BCM207x9
ULP11, 48-MHz CM4, 2 SPI (Quad/Dual),
UART, I2C, IR TX/RX, ADC,
6 PWM, KB Scanner, Mouse QD,
GCI, Crypto12, 4 TRIAC Control,
40 GPIO, 1MB Flash, 512KB RAM,
BT 4.2 + BLE + 2 Mbps, C2/C3,
WICED SMART READY
BCM20735
48-MHz CM44, 2 SPI (Quad/Dual),
UART, I2C, IR TX/RX5, ADC,
6 PWM, KB Scanner6, Mouse QD7,
GCI8, 4 TRIAC Control,
40 GPIO, 384KB RAM,
BT9 4.2 + BLE + 2 Mbps, C1/C2/C310,
WICED SMART READY
BCM20707
96-MHz CM3, 2 SPI, UART, I2C,
GCI, 4 PWM, I2S/PCM,
24 GPIO, 352KB RAM,
BT 4.2 + EDR + BLE, C1/C2
WICED SMART READY
BCM20704
96-MHz CM3, UART, I2C,
USB 2.0, I2S/PCM, GCI
8 GPIO, 352KB RAM,
BT 4.2 + EDR + BLE, C1/C2
HCI-Over-UART/USB 2.0
BCM20706
96-MHz CM3 Embedded BT SoC,
2 SPI, UART, I2C, IR TX/RX,
ADC, 4 PWM, GCI, I2S/PCM, 4 TRIAC
Control, 24 GPIO, 352KB RAM,
BT 4.2 + EDR + BLE, C1/C2
WICED SMART READY
Integration
1
7
13
2 Enhanced
8
14
Basic Rate
data rate
3 Bluetooth Low Energy
4 ARM® Cortex®-M3/M4
5 Infrared transmit and receive
6 Keyboard scanner
Document No. 001-89435 Rev. *P
Mouse quadrature decoder
Global coexistence interface
9 Bluetooth Specification 3.0/4/1/4.2
10 Class 1 (100 m)/2 (10 m)/3 (1 m)
11 Ultra-low power
12 Cryptographic accelerator block for security
3D Glass shutter control
Application Development Kit
Concept
Development
Sampling
Production
QQYY
QQYY
Status
Availability
11
BCM20707
Bluetooth Connectivity MCU
Block Diagram
HCI-based Bluetooth and dongles
Bluetooth Connectivity MCU
MCU Subsystem
Analog Peripheral
Features
Bluetooth Features
Bluetooth 4.2 + high-speed stack with BR1/EDR2/BLE3
Class 1 (100 meters), Class 2 (10 meters) support
Global coexistence interface (GCI)
Wideband speech (16K) support
Up to 16 LE connections
Host controller interface (HCI) over UART
Application Specific Peripherals
Two independent half-duplex PCM/I2S interfaces
96 MHz
Bluetooth Stack
Profiles
GPIO x40
Digital Peripherals
IR RX/TX
UART x2
PWM x4
I2C/SPI
GCI
Collateral
Communication
Interfaces
ROM (848KB)
Package
49-pin FBGA (4.5 x 4.0 mm)
WICED™ SMART READY SDK
TRIAC Control
x4
SRAM
(352KB)
System Bus
Industry’s Most-Widely-Deployed Bluetooth Stack
16-bit
DelSig
ADC4
Cortex®-M3
I/O Subsystem
I/O Ring Bus
Applications
Master
SPI
Bluetooth System
(Bluetooth 4.2)
I2S/PCM
JTAG Debug
Datasheet: BCM20707
Software: WICED SMART READY SDK (Contact Sales)
Availability
Production:
1 Basic
3
2
4
Rate
Enhanced Data Rate
Document No. 001-89435 Rev. *P
Now
Bluetooth Low Energy
Effective number of bits is 10 at 187 ksps
12
BCM20704
Bluetooth Connectivity MCU
Applications
HCI-based Bluetooth and dongles
Block Diagram
Bluetooth Connectivity MCU
MCU Subsystem
I/O Subsystem
Bluetooth Features
Bluetooth 4.2 + high-speed stack with BR1/EDR2/BLE3
Class 1 (100 meters), Class 2 (10 meters) support
Global coexistence interface (GCI)
Host controller interface (HCI) over UART and USB
Cortex®-M3
96 MHz
SRAM
(352KB)
Bluetooth Stack
Package
49-pin FCBGA (4.5 x 4.0 mm)
WICED™ SMART READY SDK
Profiles
GPIO x8
Communication
Interfaces
ROM (848KB)
System Bus
Industry’s Most-Widely-Deployed Bluetooth Stack
I/O Ring Bus
Features
UART x2
I2C/SPI Master
Collateral
Datasheet: BCM20704
Software: WICED SMART READY SDK (Contact Sales)
GCI
I2S/PCM
Bluetooth System
(Bluetooth 4.2)
USB 2.0
JTAG Debug
Availability
Production:
Now
1
Basic Rate
Enhanced Data Rate
3 Bluetooth Low Energy
2
Document No. 001-89435 Rev. *P
13
BCM20706
Bluetooth Connectivity MCU
Applications
Block Diagram
Speaker/Headset, Bluetooth gateway, automation gateway
Bluetooth Connectivity MCU
MCU Subsystem
Analog Peripheral
I/O Subsystem
Industry’s Most-Widely-Deployed Bluetooth Stack
16-bit
DelSig
ADC4
Cortex®-M3
96 MHz
Package
49-pin FBGA (4.5 x 4.0 mm)
Communication
Interfaces
ROM (848KB)
Bluetooth Stack
Profiles
WICED™ SMART READY SDK
GCI
GPIO x24
Digital Peripherals
IR RX/TX
UART x2
PWM x4
I2C/SPI
Master
SPI
Collateral
Datasheet: BCM20706
Software: WICED SMART READY SDK (Contact Sales)
TRIAC Control
x4
SRAM
(352KB)
System Bus
Bluetooth Features
Hostless, complete system-on-chip
Bluetooth 4.2 stack with BR1/EDR2/BLE3
Class 1 (100 meters), Class 2 (10 meters) support
A2DP, AVRCP, SPP, GATT support
Global coexistence interface (GCI)
I/O Ring Bus
Features
Bluetooth System
(Bluetooth 4.2)
I2S/PCM
JTAG Debug
Availability
Production:
1 Basic
3
2
4
Rate
Enhanced Data Rate
Document No. 001-89435 Rev. *P
Now
Bluetooth Low Energy
Effective number of bits is 10 at 187 ksps
14
BCM20735
Bluetooth Smart and Basic Rate Connectivity MCU
Features
Industry’s Most-Widely-Deployed Bluetooth Stack
Bluetooth Features
Bluetooth 4.2 stack with basic rate and Bluetooth Low Energy (BLE)
All new Bluetooth 4.2 features: LE privacy 1.2, LE data length
extension, LE secure connections
2-Mbps proprietary BLE support
Integrated power amplifier (up to 10 dBm)
ARM®
Cortex®-M4
CPU With Floating-Point Unit (FPU) and
Digital-Signal Processing (DSP) Logic
MIPI-Compliant Display Driver
Security Engine
PKA, SHA, AES
Packages
60-pin QFN (7 x 7 mm)
111-ball FBGA (9 x 9 mm)
WICED™ SMART READY SDK
Collateral
Datasheet: BCM20735
Software: WICED SMART READY SDK (Contact Sales)
1
BLE Connectivity MCU
MCU Subsystem
Analog Peripheral
16-bit
DelSig
ADC1
Cortex®-M4
96 MHz
SRAM
(512KB)
TRIAC Control
x4
Communication
Interfaces
ROM
(2MB)
BR/BLE Stack
Profiles
BR/BLE/2-Mbps
Subsystem
(Bluetooth 4.2)
JTAG Debug
32-kHz/128-kHz
On-Chip OSC
I/O Subsystem
I/O Ring Bus
Remote controls, BR-gateways
Block Diagram
AHB Bus
Applications
GPIO x40
Digital Peripherals
IR RX/TX
UART x2
PWM x6
I2C/SPI Master
Keyboard
Scanner
SPI/Dual SPI/
Quad SPI/MIPI
Quad Decoder
Security Engine
PKA
SHA
AES
Availability
Production:
Now
Effective number of bits is 10 at 187 ksps
Document No. 001-89435 Rev. *P
15
BCM207x9
Ultra Low Power Multi-Protocol Connectivity MCU
Applications
Block Diagram
Medical, home automation, wearables, POS input devices
Multi-Protocol Connectivity MCU
MCU Subsystem
Analog Peripheral
16-bit
DelSig
ADC5
Industry’s Most-Widely-Deployed Bluetooth Stack
Cortex®-M4
SRAM
(512KB)
Cortex®-M4
CPU With Floating-Point Unit (FPU),
Digital-Signal Processing (DSP) Logic and 1MB Flash
TRIAC Control
x4
Flash
(1MB)
ROM
(2MB)
Profiles
802.15.4/BR/BLE/
2-Mbps Subsystem
(Bluetooth 4.2)
MIPI-Compliant Display Driver
Security Engine
PKA, SHA, AES, RSA, ECDH4
JTAG Debug
Packages
40-pin QFN (5 x 5 mm)
80-ball WLCSP (2.2 x 2.2 mm)
32-kHz/128-kHz
On-Chip OSC
GPIO x40
Digital Peripherals
Communication
Interfaces
BR/BLE/ZigBee/Th
read Stack
802.15.4 ZigBee and Thread Support
ARM®
96 MHz
AHB Bus
Bluetooth Features
Industry’s lowest power Bluetooth radio
Bluetooth 4.2 stack with BR1/EDR2/BLE3
All new, Bluetooth 4.2 features: LE privacy 1.2, LE data length
extension, LE secure connections
2-Mbps proprietary BLE support
LE audio
I/O Subsystem
I/O Ring Bus
Features
IR RX/TX
UART x2
PWM x6
I2C/SPI Master
Keyboard
Scanner
SPI/Dual SPI/
Quad SPI/MIPI
Quad Decoder
Security Engine
PKA
SHA
AES
WICED™ SMART READY SDK
Availability
Collateral
Datasheet: BCM207x9 (Contact Sales)
Software: WICED SMART READY SDK (Contact Sales)
1 Basic
3
2
4
Rate
Enhanced Data Rate
Document No. 001-89435 Rev. *P
Bluetooth Low Energy
Elliptic-Curve Diffie Hellman
Sampling:
Production:
5
BCM20719
Now
Q217
BCM20729
Q117
Q217
BCM20739
Q217
Q217
Effective number of bits is 10 at 187 ksps
16
Wireless Solutions for The IoT Roadmap
• Wi-Fi PORTFOLIO
Document No. 001-89435 Rev. *P
17
Wi-Fi Portfolio
IEEE 802.11a/b/g/n WLAN1
IEEE 802.11a/b/g/n WLAN + MCU
Dual Band
(2.4/5 GHz)
BCM43907
Up to 150 Mbps, 802.11a/b/g/n, SISO2, 320-MHz CR43,
GCI4 SECI5, Security6, CCX7, 6 PWMs, Ethernet (RMII/MII),
SDIO 3.0 (H/D), USB 2.0 + HSIC (H/D),
S/PDIF, 3 UART, Quad SPI, 2 SPI, 2 I2S, 2 I2C
17 GPIO, Integrated PA8 for both bands
WICED
Single Band
(2.4 GHz)
BCM43364
Up to 96 Mbps, 802.11b/g/n, SISO
GCI SECI, Security, CCX
SDIO 2.0, SPI,
5 GPIO, Integrated PA
Linux Driver, WICED
BCM43903
Up to 72 Mbps, 802.11b/g/n, SISO,
160-MHz CR4, GCI SECI, Security, CCX,
6 PWMs, 3 UART, Quad SPI, 2 SPI, 2 I2C
17 GPIO, Integrated PA
WICED
BCM43362
Up to 72 Mbps, 802.11b/g/n, SISO
SECI, Security,
SDIO 2.0, SPI,
5 GPIO, Integrated PA
Linux Driver, WICED
BCM4390
Up to 72 Mbps, 802.11b/g/n, SISO,
48-MHz CM3, GCI, Security, CCX,
6 PWMs, 4 UART, I2S, 2 SPI, I2C
24 GPIO, Integrated PA
WICED
1
5
2
6
Wireless Local Area Network
Single-input single-output
3 ARM® Cortex®-M3/R4
4 Global coexistence interface
Document No. 001-89435 Rev. *P
Data Rate
BCM43143
Up to 150 Mbps, 802.11b/g/n, SISO
GCI SECI, Security,
SDIO 2.0, USB 2.0, I2C/SPI
19 GPIO, Integrated PA
Linux Driver
Serial-enhanced coexistence interface
WPA, WAPI STA, WPA2, AES, TKIP security features
7 Cisco-compatible extensions
8 Power amplifier
Concept
Development
Sampling
Production
QQYY
QQYY
Status
Availability
18
BCM43362
Single-Chip IEEE 802.11n MAC/Baseband/Radio + SDIO Connectivity Solution
Consumer and commercial internet-of-things (IoT), sensors
and control
Block Diagram
Single-Chip Wi-Fi Connectivity Solution
I/O Subsystem
Wi-Fi Subsystem
Features
MAC
I/O Ring Bus
Applications
Industry’s Most-Widely-Deployed Wi-Fi IP
Security Engine1
WPA and WPA2
AES in hardware
Packages
69-ball WLBGA (4.52 x 2.92 mm)
WICED™ Wi-Fi SDK, Linux Driver
Collateral
Datasheet: BCM43362
Software:
WICED Wi-Fi SDK
Linux Driver
Modules:
IoT Solutions Guide
PHY
Radio
Communication
Interfaces
Security Engine
ARM®
Cortex®-M3
UART
SPI
SRAM
(240KB)
ROM
(448KB)
SDIO
SECI
JTAG Debug
Availability
Production:
1
System Bus
Wi-Fi Features
802.11b/g/n compliant
72-Mbps data rate
Single band (2.4 GHz)
SDIO 2.0 and SPI support
3-/4-wire serial enhanced coexistence interface (SECI)
GPIO x5
Now
WPA, WAPI STA, WPA2, AES, TKIP security features
Document No. 001-89435 Rev. *P
19
BCM43364
Single-Chip IEEE 802.11n MAC/Baseband/Radio
Applications
Block Diagram
Low-cost WLAN connectivity for consumer/commercial IoT
Single-Chip Wi-Fi Connectivity Solution
I/O Subsystem
Wi-Fi Subsystem
Features
I/O Ring Bus
MAC
Industry’s Most-Widely-Deployed Wi-Fi IP
Security Engine2
WPA and WPA2
AES in hardware
Cisco-compatible extensions
PHY
Communication
Interfaces
Security Engine
ARM®
Cortex®-M3
ROM
(640KB)
WICED™ Wi-Fi SDK, Linux Driver
Datasheet: BCM43364
Software:
WICED Wi-Fi SDK
Linux Driver
Modules:
IoT Solutions Guide
GCI SECI
Availability
Production:
Document No. 001-89435 Rev. *P
SDIO
JTAG Debug
Collateral
Serial-enhanced coexistence interface
UART
SPI
SRAM
(512KB)
Packages
74-ball WLBGA (4.87 x 2.87 mm)
1
GPIO x5
Radio
System Bus
Wi-Fi Features
802.11b/g/n compliant
96-Mbps data rate
Single band (2.4 GHz)
SDIO 2.0 and SPI support
2-/3-/4-wire global coexistence interface (GCI) SECI1
2 WPA,
Now
WAPI STA, WPA2, AES, TKIP security features
20
BCM43143
Single-Chip IEEE 802.11n MAC/Baseband/Radio + SDIO/USB Connectivity Solution
Applications
Block Diagram
Consumer electronics, printers
Single-Chip Wi-Fi Connectivity Solution
I/O Subsystem
Wi-Fi Subsystem
Features
I/O Ring Bus
MAC
Industry’s Most-Widely-Deployed Wi-Fi IP
Security Engine2
WPA and WPA2
AES in hardware
Cisco-compatible extensions
PHY
Communication
Interfaces
Security Engine
ARM® Cortex®-M3
USB2.0
SDIO
ROM
(448KB)
Linux Driver
Collateral
JTAG Debug
Datasheet: BCM43143
Software:
Linux Driver
Modules:
IoT Solutions Guide
Document No. 001-89435 Rev. *P
GCI SECI
I2C/SPI
Availability
Production:
Serial-enhanced coexistence interface
UART
SRAM
(256KB)
Packages
56-pin QFN (7 x 7 mm)
1
GPIO x19
Radio
System Bus
Wi-Fi Features
802.11b/g/n compliant
150-Mbps data rate
Single band (2.4 GHz)
SDIO 2.0 and USB 2.0 support
2-/3-/4-wire global coexistence interface (GCI) SECI1
2 WPA,
Now
WAPI STA, WPA2, AES, TKIP security features
21
BCM4390
IEEE 802.11n System-on-Chip with Embedded Application Processor
Applications
Block Diagram
Consumer, home automation, health, smart energy
Single-Chip Wi-Fi Connectivity Solution
Application MCU Subsystem
Wi-Fi Subsystem
Features
MAC
GPIO x24
Industry’s Most-Widely-Deployed Wi-Fi IP
Cortex®-M3
48 MHz
Wi-Fi Features
802.11b/g/n compliant
72-Mbps data rate
Single band (2.4 GHz)
2-/3-/4-wire global coexistence interface (GCI) SECI1
PHY
Security Engine2
WPA and WPA2
AES in hardware
Cisco-compatible extensions
AXI
Security Engine
PWM x6
Communication Interfaces
ROM
(448KB)
UART x4
GCISECI
SPI x2
I2C x2
JTAG Debug
Collateral
Datasheet: BCM4390
Software:
WICED Wi-Fi SDK
Modules:
IoT Solutions Guide
Availability
Production:
Document No. 001-89435 Rev. *P
JTAG Debug
Cortex®-M3
SRAM
(256KB)
WICED™ Wi-Fi SDK
Serial-enhanced coexistence interface
Digital
Peripherals
ROM
(610KB)
ARM®
Packages
286-ball WLCSP (4.87 x 5.413 mm)
1
SRAM
(448KB)
Radio
AXI
32-bit ARM Cortex-M3 Application MCU Subsystem
I/O Subsystem
2 WPA,
Now
WAPI STA, WPA2, AES, TKIP security features
22
BCM43907
IEEE 802.11n System-on-Chip with Embedded Application Processor
Applications
Block Diagram
Appliances, HID, embedded audio, health/medical
Single-Chip Wi-Fi Connectivity Solution
Wi-Fi Subsystem
Features
Application MCU Subsystem
MAC
GPIO x17
Industry’s Most-Widely-Deployed Wi-Fi IP
PHY
SRAM
(2MB)
2.4/5-GHz
Dual-Band Radio
Ethernet (RMII/MII)
Digital
Peripherals
ROM
(640KB)
Security Engine
AXI
32-bit ARM Cortex-R4 Application MCU Subsystem
Cortex®-R4
320 MHz
AXI
Wi-Fi Features
802.11a/b/g/n compliant
150-Mbps data rate
Dual band (2.4/5 GHz)
2-/3-/4-wire global coexistence interface (GCI) SECI1
I/O Subsystem
JTAG Debug
PWM x6
ARM® Cortex®-R4
(160 MHz)
Security Engine2
WPA and WPA2
AES in hardware
Cisco-compatible Extensions
Communication Interfaces
SRAM
(448KB)
Packages
316-ball WLCSP (4.58 x 5.53 mm)
WICED™ Wi-Fi SDK
UART x3
GCI SECI
Ethernet
(RMII/MII)
ROM
(576KB)
SPI x2
I2C x2
USB 2.0
HSIC
JTAG Debug
Quad SPI
SDIO 3.0
Collateral
Availability
Datasheet: BCM43907
Software:
WICED Wi-Fi SDK
Modules:
IoT Solutions Guide
1
Serial-enhanced coexistence interface
Document No. 001-89435 Rev. *P
Production:
2 WPA,
Now
WAPI STA, WPA2, AES, TKIP security features
23
BCM43903
IEEE 802.11n System-on-Chip with Embedded Application Processor
Applications
Block Diagram
Consumer/home appliances, HID
Single-Chip Wi-Fi Connectivity Solution
Wi-Fi Subsystem
Application MCU Subsystem
I/O Subsystem
Features
MAC
GPIO x17
Industry’s Most-Widely-Deployed Wi-Fi IP
Single-Band Radio
Security Engine2
WPA and WPA2
AES in hardware
Cisco-compatible extensions
Security Engine1
Collateral
Datasheet: BCM43903
Software:
WICED Wi-Fi SDK
Modules:
IoT Solutions Guide
PWM x6
UART x3
GCI SECI
ROM
(576KB)
SPI x2
I2C x2
JTAG Debug
Quad SPI
SDIO 3.0
Availability
Production:
Document No. 001-89435 Rev. *P
JTAG Debug
Communication Interfaces
SRAM
(448KB)
WICED™ Wi-Fi SDK
Serial-enhanced coexistence interface
Digital
Peripherals
ARM® Cortex®-R4
(160 MHz)
Packages
151-ball WLBGA (4.91 x 5.85 mm)
1
SRAM
(1MB)
ROM
(640KB)
AXI
32-bit ARM Cortex-R4 Application MCU Subsystem
PHY
AXI
Wi-Fi Features
802.11b/g/n compliant
72-Mbps data rate
Single band (2.4 GHz)
2-/3-/4-wire global coexistence interface (GCI) SECI1
Cortex®-R4
160 MHz
2 WPA,
Now
WAPI STA, WPA2, AES, TKIP security features
24
Wireless Solutions for The IoT Roadmap
• Wi-Fi + Bluetooth Combo Portfolio
Document No. 001-89435 Rev. *P
25
Wi-Fi + Bluetooth Combo Portfolio
IEEE 802.11a/b/g/n WLAN1 +
Bluetooth (BR2 + EDR3 + BLE4)
Dual-Band
(2.4/5 GHz)
IEEE 802.11a/b/g/n/ac WLAN +
Bluetooth (BR + EDR + BLE)
BCM43340
Up to 150 Mbps, 802.11a/b/g/n, BT54.0,
SECI6, Security7, SDIO 2.0, SPI, HSIC,
HCI-over-UART, 2 PCM/I2S, I2S/Stereo
Audio for FM, 8 GPIOs, Integrated PA8,
Linux Driver, WICED
BCM43455
Up to 433.3 Mbps, 802.11a/b/g/n/ac,
BT4.1, A4WP9, GCI10 SECI, Security,
PCIe3.0, SDIO 2.0/3.0, SPI,
HCI-over-UART, PCM/I2S, FM RX,
15 GPIOs, Integrated PA, Linux Driver
Single-Band
(2.4 GHz)
BCM4339
Up to 433.3 Mbps, 802.11a/b/g/n/ac,
BT4.1, A4WP, GCI SECI, Security,
SDIO2.0/3.0, SPI, HCI-over-UART,
PCM/I2S, FM RX, 16 GPIOs, Integrated PA,
Linux Driver
BCM43438/BCM4343W
Up to 96 Mbps, 802.11b/g/n, BT4.1,
A4WP, GCI SECI, Security, SDIO2.0,
SPI, HCI-over-UART, 2 PCM/I2S,FM RX,
PCM/Stereo Audio for FM, 5 GPIOs,
Integrated PA, Linux Driver, WICED
Data Rate
1
5
9
2
6
10
Wireless Local Area Network
Basic Rate
3 Enhanced Data Rate
4 Bluetooth Low Energy
Document No. 001-89435 Rev. *P
Bluetooth Specification
Serial-enhanced coexistence interface
7 WPA, WAPI STA, WPA2, AES, TKIP
8 Power amplifier
Alliance for Wireless Power BLE Profile
Global coexistence interface
Concept
Development
Sampling
Production
QQYY
QQYY
Status
Availability
26
BCM43438/BCM4343W
Single chip IEEE 802.11n with Integrated Bluetooth 4.1 and FM Receiver
Applications
Block Diagram
Single-Chip Wi-Fi and Bluetooth Connectivity Solution
Wi-Fi Subsystem
Features
Interfaces
MAC And PHY
Wi-Fi Features
802.11b/g/n compliant
96-Mbps data rate
SDIO 2.0 and SPI support
2-/3-/4-wire global coexistence interface (GCI) SECI1
Bluetooth Features
Bluetooth 4.0 compliant
Class 1 (100 m) and Class 2 (10 m) operation
Host controller interface (HCI)-over-UART
FM Features
FM receiver
UART
Single-Band Radio
SPI
Security Engine2
ARM® Cortex® M3
AXI
Industry’s Most-Widely-Deployed Wi-Fi IP and Bluetooth Stack
I/O Subsystem
APB
Portable consumer/commercial IoT and wearables
GPIO x5
PCM/I2S x2
SRAM (512KB)
FM Subsystem
SDIO 2.0
ROM (640KB)
FM RX
JTAG/SWD
GCI SECI
PCM/I2S
Stereo Audio
Bluetooth Subsystem
Bluetooth 4.1
Link Layer And PHY
SRAM (160KB)
AHB
ARM® Cortex® M3
Packages
63-ball WLBGA (4.87 x 2.87 mm)
74-ball WLBGA (4.87 x 2.87 mm)
153-ball WLCSP (4.87 x 2.87 mm)
ROM (576KB)
JTAG/SWD
WICED™ Wi-Fi SDK, Linux driver
Collateral
Availability
Datasheets: BCM43438, BCM4343W
Software:
WICED Wi-Fi SDK
Linux Driver
Modules:
IoT Solutions Guide
1
Serial-enhanced coexistence interface
Document No. 001-89435 Rev. *P
Production:
2 WPA,
BCM43438
Now
BCM4343W
Now
WAPI STA, WPA2, AES, TKIP security features
27
BCM43340
Single chip IEEE 802.11n with Integrated Bluetooth 4.0 and FM Receiver
Applications
Block Diagram
Portable consumer/commercial IoT applications
Single-Chip Wi-Fi and Bluetooth Connectivity Solution
Wi-Fi Subsystem
Interfaces
MAC And PHY
Industry’s Most-Widely-Deployed Wi-Fi IP and Bluetooth Stack
I/O Subsystem
UART
Dual-Band Radio
Wi-Fi Features
802.11a/b/g/n compliant
150-Mbps data rate
Dual band (2.4/5 GHz)
SDIO 2.0, SPI, HSIC support
SPI
ARM® Cortex® M3
AXI
Security Engine1
APB
Features
GPIO x8
PCM/I2S
SRAM (512KB)
FM Subsystem
SDIO 2.0
ROM (640KB)
Bluetooth Features
Bluetooth 4.0 compliant
Class 1 (100 m) and Class 2 (10 m) operation
Host controller interface (HCI)-over-UART
FM RX
JTAG/SWD
Legacy
SECI2
PCM/I2S
Stereo Audio
Bluetooth Subsystem
FM Features
FM receiver
USB/HSIC
Bluetooth 4.0
Link Layer And PHY
SRAM (195KB)
WICED™ Wi-Fi SDK, Linux Driver
AHB
ARM® Cortex® M3
Package
141-ball WLBGA (5.67 x 4.47 mm)
ROM (652KB)
JTAG/SWD
Collateral
Datasheet: BCM43340
Software:
WICED Wi-Fi SDK
Linux Driver
Modules:
IoT Solutions Guide
1
WPA, WAPI STA, WPA2, AES, TKIP security features
Document No. 001-89435 Rev. *P
Availability
Production:
2
Now
Serial-enhanced coexistence interface
28
BCM4339
Single-Chip IEEE 802.11ac with Integrated Bluetooth 4.1 and FM Receiver
Block Diagram
High-performance, space-constrained consumer IoT applications
Single-Chip Wi-Fi and Bluetooth Connectivity Solution
Wi-Fi Subsystem
Features
MAC And PHY
Dual-Band Radio
Wi-Fi Features
802.11b/g/n/ac compliant
433.3-Mbps data rate
Dual band (2.4/5 GHz)
2-/3-/4-wire global coexistence interface (GCI) SECI1
Security Engine2
Packages
160-ball FCFBGA (8 x 8 mm)
145-ball WLBGA (4.87 x 5.41 mm)
286-ball WLCSP (4.87 x 5.41 mm)
GPIO x16
PCM/I2S
SRAM (768KB)
FM Subsystem
SDIO 2.0/3.0
ROM (640KB)
FM RX
JTAG/SWD
GCI SECI
PCM/I2S
Bluetooth Subsystem
SRAM (192KB)
AHB
ARM® Cortex® M3
ROM (608KB)
Linux Driver
JTAG/SWD
Collateral
Availability
Datasheet: BCM4339
Software:
Linux Driver
Modules:
IoT Solutions Guide
Document No. 001-89435 Rev. *P
SPI
Bluetooth 4.1
Link Layer And PHY
FM Receiver
Serial-enhanced coexistence interface
ARM® Cortex® R4
I/O Subsystem
UART
AXI
Industry’s Most-Widely Deployed Wi-Fi IP and Bluetooth Stack
Bluetooth Features
Bluetooth 4.1 compliant
Class 1 (100 m) and Class 2 (10 m) operation
Host controller interface (HCI)-over-UART
1
Interfaces
APB
Applications
Production:
2 WPA,
Now
WAPI STA, WPA2, AES, TKIP security features
29
BCM43455
Single-Chip IEEE 802.11ac with Integrated Bluetooth 4.1 and FM Receiver
Block Diagram
High-performance, space-constrained consumer/commercial IoT
Single-Chip Wi-Fi and Bluetooth Connectivity Solution
Interfaces
Wi-Fi Subsystem
Features
MAC And PHY
Wi-Fi Features
802.11b/g/n/ac compliant
433.3-Mbps data rate
Dual band (2.4/5 GHz)
2-/3-/4-wire global coexistence interface (GCI) SECI1
Bluetooth Features
Bluetooth 4.1 compliant
Class 1 (100 m) and Class 2 (10 m) operation
Host controller interface (HCI)-over-UART
FM Receiver
UART
Dual-Band Radio
SPI
Security Engine2
ARM® Cortex® R4
AXI
Industry’s Most-Widely-Deployed Wi-Fi IP and Bluetooth Stack
GPIO x15
PCM/I2S
SRAM (800KB)
FM Subsystem
SDIO 2.0/3.0
ROM (704KB)
FM RX
JTAG/SWD
PCIe 3.0
PCM/I2S
Bluetooth Subsystem
GCI SECI
Bluetooth 4.1
Link Layer And PHY
Package
140-ball WLBGA (4.47x5.27 mm)
I/O Subsystem
APB
Applications
SRAM (270KB)
Linux Driver
AHB
ARM® Cortex® M3
ROM (845KB)
Collateral
JTAG/SWD
Datasheet: BCM43455
Software:
Linux Driver
Modules:
IoT Solutions Guide
Availability
Production:
1
Serial-enhanced coexistence interface
Document No. 001-89435 Rev. *P
2 WPA,
Now
WAPI STA, WPA2, AES, TKIP security features
30
Wireless Solutions for The IoT Roadmap
• Automotive Wireless Portfolio
Document No. 001-89435 Rev. *P
31
Automotive Wireless Portfolio
Performance/Integration
Bluetooth (BR1 + EDR2)
IEEE 802.11a/b/g/n/ac WLAN3 + Bluetooth
Q117
BCM89359
Up to 867 Mbps, 802.11a/b/g/n/ac,
2x2 MIMO10 w/RSDB11, BT 4.2 BR + EDR + BLE,
GCI SECI, SDIO 3.0, PCIe, UART, USB, I2C,
SPI, HCI-over-UART, PCM/I2S, Security12,
20 GPIO, C1/C2,
Linux Driver
BCM89071
24-MHz ARM7TDMI-S4, SPI, UART, I2C,
I2S/PCM, GCI5 SECI6,
HCI7-over-UART/SPI,
8 GPIO, 112KB RAM,
BT8 4.1 BR + EDR, C1/C2/C39
BCM88335/BCM89359
Up to 433.3 Mbps, 802.11a/b/g/n/ac, SISO13,
BT4.1 BR + EDR + BLE, GCI SECI,
SDIO2.0/3.0,
SPI, HCI-over-UART, PCM/I2S, Security,
9 GPIO, C1/C2,
Linux Driver
BCM20713
24-MHz ARM7TDMI-S, SPI, UART, I2C,
I2S/PCM, GCI SECI, HCI-over-UART/SPI,
8 GPIO, 16KB RAM,
BT 4.0 BR + EDR, C1/C2/C3
Concept
Development
Sampling
Production
QQYY
QQYY
Status
Availability
1
6
11
2
7
12
Basic Rate
Enhanced Data Rate
3 Wireless Local Area Network
4 ARM 7 Family CPU
5 Global coexistence interface
Document No. 001-89435 Rev. *P
Serial-enhanced coexistence interface
Host controller interface
8 Bluetooth Specification
9 Class 1 (100 m)/2 (10 m)/3 (1 m)
10 Multiple-input multiple-output
Real Simultaneous Dual Band
WPA, WAPI STA, WPA2, AES, TKIP, Cisco
Compatible Extensions security features
13 Single-input single-output
32
Modules
Document No. 001-89435 Rev. *P
33
Cypress Bluetooth Module Portfolio
Cost
New
CYBT-413034-01
EZ-BT WICED BT 4.2 Dual Mode
CM41, 1MB Flash, HomeKit
IR2, SE3
UART, SPI/I2C, PCM/I2S, GPIO
12 x 16 x 1.80 mm SMT
Features
New
CYBT-203032-11
EZ-BT WICED BT 4.2 Dual Mode
CM34, 256KB SFlash5
Ext. Antenna via RF Pad
UART, SPI/I2C, PCM/I2S, GPIO
12 x 17 x 2.00 mm SMT
New
ARM® Cortex® -M4
modulator
3 Security Engine
New
CYBLE-202007-01
EZ-BLE PRoC BT 4.2
CM0, 256 KB Flash
Ext. Antenna via u.FL, PA/LNA
2 SCB, 19 GPIO
15 x 23 x 2.05 mm SMT
CYBLE-202013-11
EZ-BLE PRoC BT 4.2
CM0, 256 KB Flash
Ext. Antenna via RF Pad, PA/LNA
2 SCB, 19 GPIO
15 x 23 x 1.55 mm SMT
4 ARM®
7 Serial
10
2 InfraRed
5 Serial
8 Alliance
11
Document No. 001-89435 Rev. *P
Communication Block
for Wireless Power
9 No Certifications
PRoC Standard Features:
CapSense, 1MSPS ADC, LCD Driver,
4 TCPWM16, DAC
PSoC Standard Features:
PRoC + 4 UDB17 + Comparator
+ Opamp + 4 PWM
WICED Standard Features:
Simultaneous Master/Slave,
ADC, PWM, UART
New
BCM20736S/36E
EZ-BLE WICED BT 4.1 (LMA)
CM3, 64 KB E2PROM
A4WP, IR
2 UART, 2 SPI, I2C, 17 GPIO
6.5 x 6.5 x 1.20 mm 48 LGA
1
Cortex® -M3
Flash
6 ARM® Cortex® -M0
CYBLE-22411x-0x
EZ-BLE PSoC BT 4.1/4.2
CM0, 256 KB Flash
Chip Antenna, PA/LNA
2 SCB, 25 GPIO
9.5 x 15.4 x 1.80 mm SMT
CYBLE-212006-01
EZ-BLE PRoC BT 4.2
CM0, 256 KB Flash
PCB Antenna, PA/LNA14
2 SCB, 19 GPIO
15 x 23 x 2.00 mm SMT
BCM20737S/37L
EZ-BLE WICED BT 4.1 (LMA 12)
CM3, 64 KB E2PROM
A4WP, IR, NFC, SE
2 UART, 2 SPI, I2C, 17 GPIO
6.5 x 6.5 x 1.20 mm 48 LGA
New
New
CYBT-413131-01
EZ-BT WICED BT 4.2 Dual Mode
CM4, 1MB Flash, HomeKit
TRIAC, IR, SE, PA/LNA
UART, SPI/I2C, PCM/I2S, GPIO
12 x 16 x 1.80 mm SMT
New
CYBT-313026-01
EZ-BT WICED BT 4.2 Dual Mode
CM3, 352KB RAM
512KB SFlash
UART, SPI/I2C, PCM/I2S, GPIO
12 x 17 x 2.00 mm SMT
CYBLE-x140xx-0x
EZ-BLE PSoC BT 4.1/4.2
CM0, 128/256KB Flash
PCB Antenna
2 SCB, 25 GPIOs
11 x 11 x 1.80 mm SMT
CYBLE-023027-00
EZ-BLE WICED BT 4.1
CM3, 128KB SFlash
A4WP, IR
UART, SPI/I2C, GPIO
10 x 10 x 1.80 mm SMT
XT15/XR
New
CYBT-313029-01
EZ-BT WICED BT 4.2 Dual Mode
CM3 , 352KB RAM
512KB SFlash, HomeKit
UART, SPI/I2C, PCM/I2S, GPIO
12 x 17 x 2.00 mm SMT
New
CYBLE-x120xx-10
EZ-BLE PRoC BT 4.1 (NC9)
CM0, 128/256KB Flash
NS10
2 SCB, 23 GPIO
14 x 19 x 2.00 mm SMT
CYBLE-013030-00
EZ-BLE WICED BT 4.1
CM3, 60KB RAM
A4WP, IR
UART, SPI/I2C, GPIO
14 x 19 x 2.00 mm SMT
New
CYBT-423028-01
EZ-BT WICED BT 4.2 Dual Mode
CM4, 1MB Flash
TRIAC11, IR, SE
UART, SPI/I2C, PCM/I2S, GPIO
9 x 9 x 1.80 mm SMT
CYBLE-x220xx-0x
EZ-BLE PRoC BT 4.1/4.2
CM0, 128/256KB Flash
2 SCB, 16 GPIOs
10 x 10 x 1.80 mm SMT
CYBLE-x120xx-0x
EZ-BLE PRoC BT 4.1/4.2
CM06, 128/256KB Flash
2 SCB7, 23 GPIO
14 x 19 x 2.00 mm SMT
CYBLE-013025-00
EZ-BLE WICED BT 4.1
CM3, 128KB SFlash
A4WP8, IR
UART, SPI/I2C, GPIO
14 x 19 x 2.00 mm SMT
XR13
Size
12
No Shield
Triode for Alternating Current
Limited Modular Approval
13
14
Extended Range
Power Amplifier /
Low-Noise Amplifier
15
Extended Temperature
Timer/Counter/PWM
17 Universal Digital Block
16
34
Cypress Standard Range BT Modules
Creator-Based Modules
(EZ-BLETM PRoCTM)
WICED Bluetooth Modules
Q317
CYBT-413034-01
EZ-BT WICED BT 4.2 Dual Mode
CM47, 1MB Flash, HomeKit
IR8, ADC, SE9, PWM
UART, SPI/I2C, PCM/I2S, GPIO
12 x 16 x 1.80 mm SMT
Q117
Q117
Q117
Features
Creator-Based Modules
(EZ-BLE PSoC®)
CYBLE-222014-01
EZ-BLE PRoC Module BLE 4.2
CM01, 256KB, 2 SCB2
16 GPIO
10 x 10 x 1.80 mm SMT
CYBLE-212020-01
EZ-BLE PRoC Module BLE 4.2
CM0, 256KB, 2 SCB
23 GPIO
14 x 19 x 2.00 mm SMT
CYBLE-214015-01
EZ-BLE PSoC Module BLE 4.2
4 Opamp, 1 CMP5, 4 UDB6
CM0, 2 SCB, 25 GPIO
11 x 11 x 1.80 mm SMT
CYBLE-222005-00
EZ-BLE PRoC Module BLE 4.1
CM0, 256KB, 2 SCB
16 GPIO
10 x 10 x 1.80 mm SMT
CYBLE-212019-00
EZ-BLE PRoC Module BLE 4.1
CM0, 256KB, 2 SCB
23 GPIO
14 x 19 x 2.00 mm SMT
CYBLE-214009-00
EZ-BLE PSoC Module BLE 4.1
4 Opamp, 1 CMP, 4 UDB
CM0, 2 SCB, 25 GPIO
11 x 11 x 1.80 mm SMT
Q217
CYBT-203032-11
EZ-BT WICED BT 4.2 Dual Mode
CM310, 256KB SFlash11
Ext. Antenna via RF Pad
UART, SPI/I2C, PCM/I2S, GPIO
12 x 17 x 2.00 mm SMT
CYBLE-022001-00
EZ-BLE PRoC Module BLE 4.1
CM0, 128KB, 2 SCB
16 GPIO
10 x 10 x 1.80 mm SMT
CYBLE-012011-00
EZ-BLE PRoC Module BLE 4.1
CM0, 128KB, 2 SCB
23 GPIO
14 x 19 x 2.00 mm SMT
CYBLE-014008-00
EZ-BLE PSoC Module BLE 4.1
4 Opamps, 1 CMP, 4 UDB
CM0, 2 SCB, 25 GPIO
11 x 11 x 1.80 mm SMT
CYBLE-013025-00
EZ-BLE WICED BT 4.1
CM3, 128KB SFlash
A4WP13, ADC, IR
UART, SPI/I2C, PWM
14 x 19 x 2.00 mm SMT
CYBLE-013027-00
EZ-BLE WICED BT 4.1
CM3, 128KB SFlash
A4WP, ADC, IR
UART, SPI/I2C, PWM
10 x 10 x 1.80 mm SMT
BCM20737S/37L
EZ-BLE WICED BT 4.1 (LMA14)
CM3, 64 KB E2PROM
A4WP, ADC, IR, NFC, SE
2 UART, 2 SPI, I2C/PWM, 17 GPIO
6.5 x 6.5 x 1.20 mm 48 LGA
CYBLE-012012-10
EZ-BLE PRoC Module BLE 4.1
CM0, 128KB, 2 SCB
23 GPIO, NS, NC
14 x 19 x 2.00 mm SMT
Q117
CYBLE-013030-00
EZ-BLE WICED BT 4.1
CM3, 60KB RAM
A4WP7, ADC, IR
UART, SPI/I2C, PWM, GPIO
14 x 19 x 2.00 mm SMT
5 Comparator
9 Security
13
2 Serial
6 Universal
10
14
Digital Block
7 ARM® Cortex® -M4
8 InfraRed modulator
Document No. 001-89435 Rev. *P
Q117
CYBLE-212023-10
EZ-BLE PRoC Module BLE 4.1
CM0, 256KB, 2 SCB
23 GPIO, NS3, NC4
14 x 19 x 2.00 mm SMT
1
ARM® Cortex® -M0
Communication Block
3 No Shield
4 No Certifications
Q217
CYBT-423028-01
EZ-BT WICED BT 4.2 Dual Mode
CM4, 1MB Flash
TRIAC12, IR, ADC, SE
UART, SPI/I2C, PCM/I2S, PWM
9 x 9 x 1.80 mm SMT
Engine
ARM® Cortex® -M0
11 Serial Flash
12 Triode for Alternating Current
Alliance for Wireless Power
Limited Modular Approval
Concept
Q217
BCM20736S/36E
EZ-BLE WICED BT 4.1 (LMA)
CM3, 64 KB E2PROM
A4WP, ADC, IR
2 UART, 2 SPI, I2C/PWM, 17 GPIO
6.5 x 6.5 x 1.20 mm 48 LGA
Development
Sampling
Production
QQYY
QQYY
Status
Availability
35
Cypress Extended Range BT Modules
Creator-Based Modules
(EZ-BLETM PRoCTM)
Creator-Based Modules
(EZ-BLE PSoC®)
WICED Bluetooth Modules
Q317
CYBT-413131-01
EZ-BT WICED BT 4.2 Dual Mode
CM44, 1MB Flash, HomeKit
TRIAC5, IR6, ADC, SE7, PA/LNA
UART, SPI/I2C, PCM/I2S, PWM, GPIO
12 x 16 x 1.80 mm SMT
Features
CYBLE-212006-01
EZ-BLE PRoC BT 4.2
CM01, 256 KB Flash
PCB Antenna, PA/LNA2
2 SCB3, 19 GPIO
15 x 23 x 2.00 mm SMT
Q117
CYBLE-224116-01
EZ-BLE PSoC BT 4.2
CM0, 256 KB Flash
Chip Antenna, PA/LNA
2 SCB, 25 GPIO
9.5 x 15.4 x 1.80 mm SMT
Q117
CYBLE-202007-01
EZ-BLE PRoC BT 4.2
CM0, 256 KB Flash
External Antenna via u.FL, PA/LNA
2 SCB, 19 GPIO
15 x 23 x 2.05 mm SMT
Q117
Q217
CYBT-313029-01
EZ-BT WICED BT 4.2 Dual Mode
CM38, 512KB SFlash9, HomeKit
UART, SPI/I2C, PCM/I2S
12 x 17 x 2.00 mm SMT
Q117
CYBLE-224110-00
EZ-BLE PSoC BT 4.1
CM0, 256 KB Flash
Chip Antenna, PA/LNA
2 SCB, 25 GPIO
9.5 x 15.4 x 1.80 mm SMT
CYBT-313026-01
EZ-BT WICED BT 4.2 Dual Mode
CM3, 512KB SFlash
UART, SPI/I2C, PCM/I2S
12 x 17 x 2.00 mm SMT
Q117
CYBLE-202013-11
EZ-BLE PRoC BT 4.2
CM0, 256 KB Flash
External Antenna via RF Pad, PA/LNA
2 SCB, 19 GPIO
15 x 23 x 1.55 mm SMT
Concept
1
ARM® Cortex® -M0
2 Power Amplifier/Low-Noise Amplifier
3 Serial Communication Block
Document No. 001-89435 Rev. *P
4 ARM®
Cortex® -M4
5 Triode for Alternating Current
6 InfraRed modulator
7 Security
Engine
8 ARM® Cortex® -M3
9 Serial Flash
Development
Sampling
Production
QQYY
QQYY
Status
Availability
36
EZ-BLE CYBLE-x220xx-0x Modules
Bluetooth Low Energy Module using PRoC BLE with 128KB and 256KB Flash
Applications
Block Diagram
Bluetooth Low Energy (BLE) connectivity, medical, industrial,
PC accessories, toys and smartphone accessories
Power /
Ground
4
EZ-BLE PRoC Module
2
SWD8 /
GPIO
32.768-kHz Crystal
Features
14
Qualification and Certification
Bluetooth SIG QDID1, FCC2, CE3, KC4, MIC5 and IC6
Small Footprint:
10 mm x 10 mm x 1.8 mm, 21/22-pad SMT with 16 GPIO
Bluetooth Smart Connectivity with BLE 4.1 and 4.2
2.4-GHz BLE radio and baseband
-91 dBm Rx sensitivity, +3-dBm Tx output power
Power Modes
1.3-µA deep-sleep, 150-nA hibernate, 60-nA stop
Highly Integrated Solution
Two crystals, chip antenna, passives, shield
128KB and 256KB Flash sizes
Preprogrammed with EZ-Serial firmware
CYBLE-x220xx-EVAL Evaluation Board Interface
Easy interface to CY8CKIT-042-BLE Pioneer Kit
Enables testing of CapSense, buttons, GPIOs, OTA7
PRoC BLE
24-MHz Crystal
XRES
Chip
Antenna
VREF10
SPI /
I2 C /
UART /
CapSense /
ADC /
PWM /
GPIO
Collateral
CYBLE-022001-00 Datasheet
CYBLE-222005-00 Datasheet
CYBLE-222014-01 (BT 4.2) Datasheet
PRoC BLE Datasheet
Getting Started Application Note
Availability
Sampling:
Production:
PSoC Creator
4.1/128KB 4.1/256KB
Now
Now
Now
Now
4.2
Now
Q1’17
PSoC Programmer
CySmart11 Windows Host Emulation Tool
CySmart iOS and Android Apps
1 Bluetooth
5 Korea
9
2 Bluetooth
6
10
Low Energy, also known as Bluetooth Smart
Special Interest Group Qualification Design ID
3 Federal Communications Commission
4 Conformité Européenne (Europe)
Document No. 001-89435 Rev. *P
Certification
Ministry of Internal Affairs and Communications (Japan)
7 Industry Canada
8 Over-the-Air
Serial wire debug communication protocol
VREF only available on 256KB module
11 A GUI-based software tool that installs on your PC to test and debug
BLE functionality; also available in iOS and Android mobile applications
37
EZ-BLE CYBLE-x140xx-0x Modules
Bluetooth Low Energy (BLE) Module using PSoC 4 BLE with up to 256KB Flash
Applications
Block Diagram
Sports and fitness monitors, medical devices, wearable
electronics, home automation solutions and game controllers
Power /
Ground
5
EZ-BLE PSoC Module
2
SWD9 /
GPIO
32.768-kHz Crystal
Features
23
Qualification and Certification
Bluetooth SIG QDID1, FCC2, CE3, KC4, MIC5 and IC6
Small Footprint: 11 mm x 11 mm x 1.8 mm, 32-SMT, 25 GPIOs
Bluetooth Smart Connectivity with Bluetooth 4.1 and 4.2
Highly Integrated Solution
Two crystals, trace antenna, passives, shield
128KB and 256KB Flash sizes, with over-the-air (OTA) firmware
upgrades
Preprogrammed with EZ-Serial firmware
Programmable Analog Blocks
Four opamps, configurable as PGAs, comparators, filters, etc.
One 12-bit, 1-Msps SAR7 ADC
Programmable Digital Blocks
Four universal digital blocks (UDBs): custom digital peripherals
Four configurable TCPWM8 blocks: 16-bit timer, counter or PWM
Two configurable serial communication blocks for I2C / SPI / UART
Power Modes:1.3-µA Deep Sleep,150-nA Hibernate,60-nA Stop
CYBLE-x140xx-EVAL Kit for fast evaluation and development
Availability
Sampling:
Production:
PSoC 4 BLE
Analog
and Digital
GPIOs
24-MHz Crystal
XRES
Trace
Antenna
VREF
Collateral
CYBLE-014008-00 Datasheet
CYBLE-214009-00 Datasheet
CYBLE-214015-01 (BT 4.2) Datasheet
PSoC 4 BLE Datasheet
Getting Started Application Note
PSoC Creator
PSoC Programmer
4.1/128KB
Now
Now
4.1/256KB 4.2
Now
Now
Now
Q1’17
CySmart10 Windows Host Emulation Tool
CySmart iOS and Android Apps
1 Bluetooth
5
9
2 Federal
6
10
Special Interest Group Qualification Design ID
Communications Commission
3 Conformité Européenne (Europe)
4 Korea Certification
Document No. 001-89435 Rev. *P
Ministry of Internal Affairs and Communications (Japan)
Industry Canada
7 Successive approximation register
8 Timer/Counter/Pulse-Width Modulator
Serial wire debug communication protocol
A GUI-based software tool that installs on your PC to test and debug
BLE functionality; also available in iOS and Android mobile applications
38
EZ-BLE CYBLE-x120xx-xx Modules
Cost Optimized Bluetooth Low Energy (BLE) EZ-BLE PRoC Modules
Applications
Block Diagram
BLE connectivity, medical, industrial, PC accessories,
toys and smartphone accessories
Power/
Ground
6
2
EZ-BLE PRoC Module
SWD9 /
GPIO
32.768-kHz Crystal
Features
21
Qualification and Certification
Bluetooth SIG QDID1 (CYBLE-012011-00 /
CYBLE-212019-00), FCC2, CE3, KC4, MIC5 and IC6
Small Footprint
14.5 mm x 19.2 mm x 2.0 mm, 31-pad SMT with 23 GPIO
Bluetooth Smart Connectivity with Bluetooth 4.1 and 4.2
2.4-GHz BLE radio and baseband
-91 dBm Rx sensitivity, +3-dBm Tx output power
Power Modes
1.3-µA Deep-Sleep, 150-nA Hibernate, 60-nA Stop
Highly Integrated Solution
Two crystals, trace antenna, passives, shield7
Preprogrammed with EZ-Serial firmware
CYBLE-x120xx-EVAL Adapter Board Interface
Easy interface to CY8CKIT-042-BLE Pioneer Kit
Enables testing of CapSense, buttons, GPIOs, OTA8
PRoC BLE
24-MHz Crystal
XRES
Trace
Antenna
VREF
SPI /
I2 C /
UART /
CapSense /
ADC /
PWM /
GPIO
Collateral
CYBLE-01200x-x0 Datasheet
CYBLE-212019-00 Datasheet
CYBLE-212020-01 (BT 4.2) Datasheet
PRoC BLE Datasheet
Getting Started Application Note
Availability
Sampling:
Production:
PSoC Creator
4.1/128KB 4.1/256KB 4.2
Now
Now
Now
Now
Now
Q1’17
PSoC Programmer
CySmart10 Windows Host Emulation Tool
CySmart iOS and Android Apps
1 Bluetooth
5
9
2 Federal
6
10
Special Interest Group Qualification Design ID
Communications Commission
3 Conformité Européenne (Europe)
4 Korea Certification
Document No. 001-89435 Rev. *P
Ministry of Internal Affairs and Communications (Japan)
Industry Canada
7 CYBLE-0120012-10 does not include metal shield
8 Over-the-Air
Serial wire debug communication protocol
A GUI-based software tool that installs on your PC to test and debug
BLE functionality; also available in iOS and Android mobile applications
39
EZ-BLE XT / XR1 Module CYBLE-22411x-0x
Long Range Bluetooth Low Energy Module Supporting Extended Temperatures
Applications
Block Diagram
Bluetooth Low Energy (BLE) connectivity, lighting, industrial
and medical
Power /
Ground
6
2
EZ-BLE PSoC XT / XR Module
SWD9 /
GPIO
32.768-kHz Crystal
Features
23
Qualification and Certification
Bluetooth SIG QDID2, FCC3, CE4, MIC5, KC6 and IC7
Small Footprint
9.5 mm x 15.4 mm x 1.8 mm, 32-pad SMT with 25 GPIOs
Bluetooth Smart Connectivity with Bluetooth 4.1 and 4.2
2.4-GHz BLE radio and baseband
Extended Industrial Temperature Range
Operating temperature range from -40ºC to +105ºC
Long Range
+9.5-dBm Tx output power, 400 meters line-of-sight range
-95 dBm Rx sensitivity
Highly Integrated Solution
2 crystals, trace antenna, power amplifier, passives, shield
Preprogrammed with EZ-Serial firmware
CYBLE-22411x-EVAL Adapter Board Interface
Easy interface to CY8CKIT-042-BLE Pioneer Kit
Enables testing of CapSense, buttons, GPIOs, OTA8
24-MHz Crystal
XRES
Chip
Antenna
VREF
Collateral
CYBLE-224110-00 Datasheet
CYBLE-224116-01 (BT 4.2) Datasheet
PSoC 4 BLE Datasheet
Getting Started Application Note
PSoC Creator
CySmart10 Windows Host Emulation Tool
4.1
Now
Now
4.2
Now
Q1’17
CySmart iOS and Android Apps
1
5
9
2
6 Korea
10
Extended temperature/extended range
Bluetooth Special Interest Group Qualification Design ID
3 Federal Communications Commission
4 Conformité Européenne (Europe)
Document No. 001-89435 Rev. *P
Power
Amplifier
SPI /
I2 C /
UART /
CapSense /
ADC /
PWM /
GPIO
PSoC Programmer
Availability
Sampling:
Production:
PSoC 4 BLE
Ministry of Internal Affairs and Communications (Japan)
Certification
7 Industry Canada
8 Over-the-Air
Serial wire debug communication protocol
A GUI-based software tool that installs on your PC to test and debug
BLE functionality; also available in iOS and Android mobile applications
40
EZ-BLE XR1 Module CYBLE-2x20xx-x1
Long Range Bluetooth Low Energy Module Supporting External Antenna
Applications
Block Diagram
Bluetooth Low Energy (BLE) connectivity, lighting, industrial
and medical
Power /
Ground
8
2
EZ-BLE PRoC XR Module
SWD9 /
GPIO
32.768-kHz Crystal
Features
Qualification and Certification
Bluetooth SIG QDID2, FCC3, CE4, MIC5, KC6 and IC7
Small Footprint
15.0 mm x 23.0 mm x 2.0 mm, 30-pad SMT with 19 GPIOs
Bluetooth Smart Connectivity with Bluetooth 4.2
2.4-GHz BLE radio and baseband
Extended Industrial Temperature Range
Operating temperature range from -40ºC to +85ºC
Long Range
+7.5-dBm Tx output power, 400 meters line-of-sight range
-93 dBm Rx sensitivity
Highly Integrated Solution
2 crystals, trace antenna (option), power amplifier, passives
Preprogrammed with EZ-Serial firmware
CYBLE-2x20xx-EVAL Adapter Board Interface
Easy interface to CY8CKIT-042-BLE Pioneer Kit
Enables testing of CapSense, buttons, GPIOs, OTA8
17
PRoC 4 BLE
24-MHz Crystal
XRES
Power
Amplifier
VREF
SPI /
I2 C /
UART /
CapSense /
ADC /
PWM /
GPIO
PCB
Antenna
Antenna
Collateral
CYBLE-2x20xx-x1 (BT 4.2) Datasheet
PSoC 4 BLE Datasheet
Getting Started Application Note
PSoC Creator
PSoC Programmer
Availability
CySmart10 Windows Host Emulation Tool
Sampling: Now
Production: Q1’17
CySmart iOS and Android Apps
1
5
9
2
6 Korea
10
Extended range
Bluetooth Special Interest Group Qualification Design ID
3 Federal Communications Commission
4 Conformité Européenne (Europe)
Document No. 001-89435 Rev. *P
Ministry of Internal Affairs and Communications (Japan)
Certification
7 Industry Canada
8 Over-the-Air
Serial wire debug communication protocol
A GUI-based software tool that installs on your PC to test and debug
BLE functionality; also available in iOS and Android mobile applications
41
BCM20737S/L
Bluetooth Low Energy WICED SiP1 Module Supporting Security Engine and NFC2
Applications
Block Diagram
Bluetooth Low Energy (BLE) connectivity, consumer
electronics, industrial and medical
23
Power /
Ground
2
BCM20707S/L Module
Features
UART
2
Qualification and Certification
FCC3, CE4 Compliant
Small Footprint
6.5 mm x 6.5 mm x 1.2 mm, 48-pin LGA5 with 17 GPIOs
Bluetooth Smart Connectivity with Bluetooth 4.1
2.4-GHz BLE radio and baseband
+4-dBm Tx output power，-93 dBm Rx sensitivity
Industrial Temperature Range
Operating temperature range from -40ºC to +85ºC
Highly Integrated Solution
1 crystal, 64 KB E2PROM, bandpass filter
Simultaneous multiple Master and Slave (1M, 3S)
Security Engine
Support A4WP6, LE7 Audio and OOB8 pairing using NFC
Secure over-the-air (OTA) firmware upgrade
I2 C
BCM20737
17
24-MHz Crystal
RESET_N
EEPROM
64 KB
Filter /
Antenna
SPI /
UART /
Infrared /
ADC /
PWM /
GPIO /
XTAL
Collateral
BCM20737S Datasheet
BCM20737L Datasheet
BCM20737 Datasheet
WICED SMART SDK（Software)
BCM20737L supports 1.2 V operation with LDO bypassed
WICED SMART SDK 2.x (Quick Start Guide)
Availability
Production:
Now
1
4 Conformité
7 Low
2
5
8
System in Package
Near Field Communication
3 Federal Communications Commission
Document No. 001-89435 Rev. *P
Européenne (Europe)
Land Grid Array
6 Alliance for Wireless Power
Energy
Out of band
42
BCM20736S/E
Bluetooth Low Energy WICED SiP1 Module Supporting Wireless Charging
Applications
Block Diagram
Bluetooth Low Energy (BLE) connectivity, consumer
electronics，beacon/tag
Power /
Ground
23
2
BCM20706S/E Module
UART
Features
2
Qualification and Certification
FCC2, CE3 Compliant
Small Footprint
6.5 mm x 6.5 mm x 1.2 mm, 48-pin LGA4 with 17 GPIOs
Bluetooth Smart Connectivity with Bluetooth 4.1
2.4-GHz BLE radio and baseband
+4-dBm Tx output power，-93 dBm Rx sensitivity
Industrial Temperature Range
Operating temperature range from -40ºC to +85ºC
Highly Integrated Solution
1 crystal, 64 KB E2PROM, bandpass filter
Simultaneous multiple Master and Slave (1M, 1S)
Support A4WP5
Secure over-the-air (OTA) firmware upgrade
I2 C
BCM20736
17
24-MHz Crystal
RESET_N
EEPROM
64 KB
Filter /
Antenna
SPI /
UART /
Infrared /
ADC /
PWM /
GPIO /
XTAL
Collateral
BCM20736S Datasheet
BCM20736E Datasheet
BCM20736 Datasheet
BCM20736E supports external antenna through RF pad
WICED SMART SDK（Software）
WICED SMART SDK 2.x (Quick Start Guide)
Availability
Production: Now
1
4
2 Federal
5
System in Package
Communications Commission
3 Conformité Européenne (Europe)
Document No. 001-89435 Rev. *P
Land Grid Array
Alliance for Wireless Power
43
MCU Portfolio
Document No. 001-89435 Rev. *P
44
MCU Portfolio
8-Bit
32-Bit ARM®
Cortex®-M0/M0+
32-Bit ARM®
Cortex®-M3
32-Bit ARM®
Cortex®-M4
32-Bit ARM®
Cortex®-M7
High Analog
Integration
Ultra-Low-Power
8-/16-Bit Replacement
Mid-Range
Performance
High Performance
Next Generation
Analog and Digital Integration
Programmable System-on-Chip (PSoC) is the world’s only programmable embedded
system-on-chip integrating an MCU core, PABs1, PDBs2, programmable interconnect
and routing, and CapSense capacitive sensing
Flexible MCU (FM) is a portfolio of high-performance ARM® Cortex®-M-based
MCUs for industrial and consumer applications
PSoC 5LP
Cortex®-M3
80 MHz, 256KB Flash
20 PAB, 30 PDB, 72 I/Os
PSoC 3
8051 CPU
67 MHz, 64KB Flash
Up to 19 PAB, 30 PDB, 72 I/Os
PSoC 1
M8C CPU
24 MHz, 32KB Flash
16 PAB, 16 PDB, 64 I/Os
8FX
8-bit RISC MCU
16 MHz, 32-50KB Flash
PSoC 4
Cortex®-M0
48 MHz, 256KB Flash
Up to 13 PAB, 20 PDB, 98 I/Os
PSoC 7
Cortex®-M7
NDA Required, Contact Sales
PSoC 6
Cortex®-M4 and Cortex®-M0+
NDA Required, Contact Sales
FM4 MCUs
Cortex®-M4
200 MHz, 2MB Flash, 190 I/Os
FM3 MCUs
Cortex®-M3
144 MHz, 1.5MB Flash, 154 I/Os
PSoC Analog Coprocessor
CY8C4Axx
48 MHz, 32KB Flash
Up to 12 PAB, 11 PDB, 38 I/Os
FM0+ MCUs
Cortex®-M0+
40 MHz, 512KB Flash, 102 I/Os
Concept
1
A programmable analog block that is configured using PSoC software to create analog front ends, signal conditioning circuits
with opamps and filters
2 A programmable digital block that is configured using PSoC software to implement custom digital peripherals and glue logic
Document No. 001-89435 Rev. *P
FM7 MCUs
Cortex®-M7
NDA Required, Contact Sales
Development
Sampling
Production
QQYY
QQYY
Status
Availability
45
FM4® MCU Portfolio
ARM® Cortex®-M4
High Performance
S6E2D-Series
160 MHz, 540 CoreMark®, 2.7-3.6 V,
2M/36K1, 512KB Video RAM,
120/176 Pins
S6E2G-Series
180 MHz, 608 CoreMark®, 2.7-5.5 V,
1M/192K1, 144/176 Pins
Flash
MB9BFx6xM/N/R-Series
160 MHz, 540 CoreMark®, 2.7-5.5 V,
1M/128K1, 32KB Work Flash2,
80/100/120 Pins
S6E2C-Series
200 MHz, 675 CoreMark®, 2.7-5.5 V,
2M/256K1, 144/176/216 Pins
S6E2H-Series
160 MHz, 540 CoreMark®, 2.7-5.5 V,
512K/64K1, 32KB Work Flash2,
80/100/120 Pins
MB9BFx6xK/L-Series
160 MHz, 540 CoreMark®, 2.7-5.5 V,
512K/64K1, 32KB Work Flash2,
48/64 Pins
CPU Speed
Concept
1
2
Flash KB/SRAM KB
Independent Flash memory available to store data or additional firmware
Document No. 001-89435 Rev. *P
Development
Sampling
Production
QQYY
QQYY
Status
Availability
46
PSoC® 5LP Portfolio
CPU Speed and Flash
ARM® Cortex®-M3 | CapSense® | DMA | LCD | RTC | Timer/Counter/PWM
Programmable Digital
PSoC 5200
Intelligent Analog
PSoC 5400
Performance Analog
PSoC 5600
Precision Analog
PSoC 5800
Analog: 1x ADC1, 1x DAC2, 2x CMP3,
0.9% VREF
Interfaces: USB, FF4 I2C
Analog: 1x ADC1, 2x DAC2, 4x CMP3,
2x Opamps, 2x SC/CT PAB5,
0.9% VREF
Interfaces: USB, FF4 I2C
Analog: 2x ADC1, 4x DAC2, 4x CMP3,
4x Opamps, DFB6, 4x SC/CT PAB5,
0.9% VREF
Interfaces: USB, FF4 I2C, CAN7
Analog: 2x/3x ADC1, 4x DAC2,
4x CMP3, 4x Opamps, DFB6,
4x SC/CT PAB5, 0.1% VREF
Interfaces: USB, FF4 I2C, CAN7
CY8C5288
80 MHz, 256K/64K/2K8
12b SAR ADC1
24x UDB9, 99-CSP10
CY8C5488
80 MHz, 256K/64K/2K8
12b SAR ADC1
24x UDB9, 99-CSP10
CY8C5688
80 MHz, 256K/64K/2K8
2x 12b SAR ADC1
24x UDB9, 99-CSP10
CY8C5888
80 MHz, 256K/64K/2K8
20b ΔƩ ADC11, 2x 12b SAR ADC1
24x UDB9, 99-CSP10
CY8C5268
67 MHz, 256K/64K/2K8
12b SAR ADC1
24x UDB9
CY8C5468
67 MHz, 256K/64K/2K8
12b SAR ADC1
24x UDB9
CY8C5668
67 MHz, 256K/64K/2K8
12b ΔƩ ADC11, 12b SAR/2x 12b SAR ADC1
24x UDB9
CY8C5868
67 MHz, 256K/64K/2K8
20b ΔƩ ADC10, 2x 12b SAR ADC1
24x UDB9
CY8C5267
67 MHz, 128K/32K/2K8
12b SAR ADC1
24x UDB9
CY8C5467
67 MHz, 128K/32K/2K8
12b SAR ADC1
24x UDB9
CY8C5667
67 MHz, 128K/32K/2K8
12b ΔƩ ADC11, 12b SAR/2x 12b SAR ADC1
24x UDB9
CY8C5867
67 MHz, 128K/32K/2K8
20b ΔƩ ADC11, 12b SAR ADC1
24x UDB9
CY8C5266
67 MHz, 64K/16K/2K9
12b SAR ADC1
20x UDB10
CY8C5466
67 MHz, 64K/16K/2K8
12b SAR ADC1
20x UDB9
CY8C5666
67 MHz, 64K/16K/2K8
12b ΔƩ ADC11, 12b SAR ADC1
20x UDB9
CY8C5866
67 MHz, 64K/16K/2K8
20b ΔƩ ADC11, 12b SAR ADC1
20x UDB9
CY8C5265
67 MHz, 32K/8K/2K8
12b SAR ADC1
20x UDB9
CY8C5465
67 MHz, 32K/8K/2K8
12b SAR ADC1
20x UDB9
1
4
2
5
Analog-to-digital converter
Digital-to-analog converter
3 Comparator
Fixed function
Switched capacitor/continuous time
programmable analog block
Document No. 001-89435 Rev. *P
6
9
7
10
Digital filter block
Controller area network
8 Flash KB/SRAM KB/EEPROM KB
Universal digital block
Status
Chip-scale package
11 Delta-Sigma ADC
Availability
Concept
Development
Sampling
Production
QQYY
QQYY
47
FM3® MCU Portfolio
ARM® Cortex®-M3
Midrange Performance
MB9BFx2xS/T-Series
60 MHz, 2.7-5.5 V,
1.5M/192K1, 64KB Work Flash2,
144/176 Pins
MB9BFx1xS/T-Series
144 MHz, 2.7-5.5 V,
1M/128K1, 144/176 Pins
MB9BFx1xN/R-Series
144 MHz, 2.7-5.5 V,
512K/64K1, 32KB Work Flash2,
100/120 Pins
MB9AFx2xK/L-Series
40 MHz, 2.7-5.5 V,
512K/32K1, 80/100 Pins
MB9AFx5xM/N/R-Series
40 MHz, 1.7-3.6 V,
512K/64K1, 32KB Work Flash2,
80/100/120 Pins
Flash
MB9AFx4xL/M/N-Series
40 MHz, 1.7-3.6 V,
256K/32K1, 32KB Work Flash2,
64/80/100 Pins
MB9AFx3xK/L-Series
20 MHz, 1.8-5.5 V,
128K/8K1, 48/64 Pins
MB9AFx1xL/M/N-Series
40 MHz, 2.7-5.5 V,
256K/32K1, 64/80/100 Pins
MB9AFxAxL/M/N-Series
20 MHz, 1.8-5.5 V,
128K/16K1, 64/80/100 Pins
MB9AFx1xK-Series
40 MHz, 2.7-5.5 V,
128K/16K1, 32KB Work Flash2,
48 Pins
MB9BFx2xK/L/M-Series
72 MHz, 2.7-5.5 V,
256K/32K1, 32KB Work Flash2,
48/64/80 Pins
MB9AFx2xK/L-Series
40 MHz, 2.7-5.5 V,
64K/4K1, 48/64 Pins
MB9BF121J-Series
72 MHz, 2.7-5.5 V,
64K/8K1, 32 Pins
CPU Speed
Concept
1
2
Flash KB/SRAM KB
Independent Flash memory available to store data or additional firmware
Document No. 001-89435 Rev. *P
Development
Sampling
Production
QQYY
QQYY
Status
Availability
48
PSoC® 4 Portfolio
ARM® Cortex®-M0/M0+ | CapSense® | Timer/Counter/PWM
PSoC MCU
PSoC 4000
Intelligent Analog
PSoC 4100
BL = BLE-Series
Programmable Digital
PSoC 4200
S = S-Series
M = M-Series
CY8C4128-BL
24-MHz M0, 256K/32K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, BLE6
CY8C4126-M
24-MHz M0, 64K/8K1,
CMP2, Opamp, ADC3,
SCB4, IDAC5
CY8C4146-S
48-MHz M0+, 64K/8K1,
CMP2, Opamp, ADC3,
SCB4, IDAC5, Smart I/O9
CY8C4246-M
48-MHz M0, 64K/8K1,
CMP2, Opamp, ADC3,
SCB4, IDAC5, UDB7
CY8C4246-L
48-MHz M0, 64K/8K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, UDB7, CAN8, USB
Flash
CY8C4247-L
48-MHz M0, 128K/16K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, UDB7, CAN8, USB
NEW
Q117
CY8C41xxPS
48-MHz M0+, 32K/4K1,
CMP2, Opamp, ADC3,
SCB4, VDAC5, Smart I/O9
CY8C4245
48-MHz M0, 32K/4K1,
2
CMP , Opamp, ADC3,
SCB4, IDAC5, UDB7
CY8C4024-S
24-MHz M0+, 16K/2K1,
CMP2, ADC3, SCB4,
IDAC5, Smart I/O9
CY8C4124
24-MHz M0, 16K/4K1,
2
CMP , Opamp, ADC3,
SCB4, IDAC5
CY8C4125-S
24-MHz M0+, 32K/4K1,
2
CMP , Opamp, ADC3, SCB4,
IDAC5, Smart I/O9
CY8C4244
48-MHz M0, 16K/4K1,
2
CMP , Opamp, ADC3,
SCB4, IDAC5, UDB7
3 Analog-to-digital
converter
CY8C4247-BL
48-MHz M0, 128K/16K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, BLE6, UDB7
CY8C4247-M
48-MHz M0, 128K/16K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, UDB7, CAN8
CY8C4125
24-MHz M0, 32K/4K1,
2
CMP , Opamp, ADC3,
SCB4, IDAC5
KB/SRAM KB
CY8C4248-BL
48-MHz M0, 256K/32K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, BLE6, UDB7
CY8C4127-BL
24-MHz M0, 128K/16K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, BLE6
CY8C4045-S
48-MHz M0+, 32K/4K1,
CMP2, ADC3, SCB4,
IDAC5, Smart I/O9
2 Comparator
CY8C4248-L
48-MHz M0, 256K/32K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, UDB7, CAN8, USB
CY8C4127-M
24-MHz M0, 128K/16K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5
CY8C4124-S
24-MHz M0+, 16K/4K1,
CMP2, Opamp, ADC3,
SCB4, IDAC5, Smart I/O9
CY8C4014
16-MHz M0, 16K/2K1,
CMP2, I2C, IDAC5
1 Flash
L = L-Series
4 Serial
7 Universal
5 Current-output
8 Controller
communication block
DAC
6 Bluetooth Low Energy
Document No. 001-89435 Rev. *P
digital block
area network
9 Embedded programmable digital logic in the I/O subsystem
Concept
Development
Sampling
Production
QQYY
QQYY
Status
Availability
49
FM0+® MCU Portfolio
ARM® Cortex®-M0+
Ultra-Low-Power 8-Bit/16-Bit Replacement
NEW
Q217
S6E1B-Series
40 MHz, 1.7-3.6 V,
512K/64K1, 32KB Work Flash2,
80/100/120 Pins, 65 µA/MHz3
Flash
S6E1x-Series
48 MHz, 2.2-5.5 V,
Concept Only, Contact Sales
NEW
S6E1C-Series
40 MHz, 1.7-3.6 V,
128K/16K1, 26/32/48/64 Pins , 40 µA/MHz3
S6E1A-Series
40 MHz, 2.7-5.5 V,
88K/6K1, 32/48 Pins, 70 µA/MHz3
CPU Speed
1
Flash KB/SRAM KB
Independent Flash memory available to store data or additional firmware
3 Active power consumption
2
Document No. 001-89435 Rev. *P
50
PSoC® 3 Portfolio
8051 CPU | CapSense® | DMA | LCD | RTC | Timer/Counter/PWM
Programmable Digital
PSoC 3200
Intelligent Analog
PSoC 3400
Performance Analog
PSoC 3600
Precision Analog
PSoC 3800
Analog: ΔƩ ADC1, 1x DAC2, 2x CMP3,
0.9% VREF
Analog: ΔƩ ADC1, 2x DAC2, 4x CMP3,
2x Opamps, 2x SC/CT PAB5,
0.9% VREF
Interfaces: FF4 I2C
Analog: ΔƩ ADC1, 2x/4x DAC2,
0x/2x/4x CMP3, 0x/2x/4x Opamps,
0x/2x/4x SC/CT PAB5, 0.1% VREF
Interfaces: USB, FF4 I2C
Analog: ΔƩ ADC1, 2x/4x DAC2,
0x/2x/4x CMP3, 0x/2x/4x Opamps,
0x/2x/4x SC/CT PAB5, 0.1% VREF
Interfaces: USB, FF4 I2C
CY8C3666
67 MHz, 64K/8K/2K6
0x/1x DFB7, 12b ADC1
20x/24x UDB8, CAN9
CY8C3866
67 MHz, 64K/8K/2K6
DFB7, 20b ADC1
20x/24x UDB8, CAN9, 72-CSP10
CY8C3665
67 MHz, 32K/4-8K/1K6
0x/1x DFB7, 12b ADC1
16x/20x UDB8, 72-CSP10
CY8C3865
67 MHz, 32K/4-8K/1K6
0x/1x DFB7, 20b ADC1
16x/20x UDB8
CPU Speed and Flash
Interfaces: FF4 I2C
CY8C3246
50 MHz, 64K/8K/2K6
12b ADC1
24x UDB8, USB, 72-CSP10
CY8C3446
50 MHz, 64K/8K/2K6
12b ADC1
24x UDB8, USB, CAN9
CY8C3245
50 MHz, 32K/4K/1K6
12b ADC1
20x UDB8, USB, 72-CSP10
CY8C3445
50 MHz, 32K/4K/1K10
12b ADC1
20x UDB8, USB
CY8C3244
50 MHz, 16K/2K/0.5K6
12b ADC1
16x UDB8
CY8C3444
50 MHz, 16K/2K/0.5K6
12b ADC1
16x UDB8
1
5
9
2
6
10
Delta-Sigma analog-to-digital converter
Digital-to-analog converter
3 Comparator
4 Fixed function
Document No. 001-89435 Rev. *P
Switched capacitor/continuous time programmable analog block
Flash KB/SRAM KB/EEPROM KB
7 Digital filter block
8 Universal digital block
Controller area network
Chip-scale package
Concept
Development
Sampling
Production
QQYY
QQYY
Status
Availability
51
PSoC® 1 Portfolio
M8C CPU | 24 MHz
PSoC MCU
Programmable Digital
Intelligent Analog
Performance Analog
CY8C29xxx
32K/2K1, 64 GPIOs2
CapSense, 16x PDB3, 4x CMP4,
1x14-bit ΔƩ5 ADC, 12x SC/CT PAB6
CY8C27xxx
32K/2K1, 44 GPIOs2
CapSense, 8x PDB3, 4x CMP4,
1x14-bit ΔƩ5 ADC, 12x SC/CT PAB6
CY8C24x93
32K/2K1, 36 GPIOs2
2x CMP4, 1x10-bit Incremental ADC
CY8C24x94
16K/1K1, 56 GPIOs2
CapSense, 4x PDB3, 2x CMP4,
2x14-bit SAR7 ADC, 6x SC/CT PAB6
CY8C28xxx
16K/1K1, 44 GPIOs2
CapSense, 12x PDB3, 4x CMP4,
4x14-bit ΔƩ5 ADC, 16x SC/CT PAB6
Flash
CY8C2xx45
16K/1K1, 38 GPIOs2
CapSense, 8x PDB3, 4x CMP4,
1x10-bit SAR7 ADC, 6x SC/CT PAB6
CY8C21x34
8K/0.5K1 , 28 GPIOs2
CapSense, 4x PDB3 , 2x CMP4,
1x10-bit Single-Slope ADC, 4x SC/CT PAB6
CY8C23x33
8K/0.25K1, 26 GPIOs2
CapSense, 4x PDB3, 1x CMP4,
1x 8-bit SAR7 ADC, 4x SC/CT PAB6
CY8C21x23
4K/0.25K1, 16 GPIOs2
4x PDB3, 2x CMP4,
1x10-bit Single-Slope ADC, 4x SC/CT PAB6
1
5
2
6
Flash KB/SRAM KB
General purpose input/output pins
3 Programmable digital block
4 Comparator
Document No. 001-89435 Rev. *P
Delta-Sigma ADC
Switched capacitor/continuous time programmable analog block
7 Successive approximation register ADC
CY8C24x23
4K/0.25K1, 24 GPIOs2
CapSense, 4x PDB3, 2x CMP4,
1x14-bit ΔƩ5 ADC, 6x SC/CT PAB6
Concept
Development
Sampling
Production
QQYY
QQYY
Status
Availability
52
8FX® MCU Portfolio
8-Bit RISC CPU
CPU Speed and Flash
8-/16-Pin
20-Pin
24-Pin
32-Pin
48-/52-Pin
MB95690K
16 MHz, 2.8-5.5 V
56/2/41
MB95650L
16 MHz, 1.8-5.5 V,
32/1/41
MB95580H
16 MHz, 2.4-5.5 V,
16/0.5/41
64-Pin
80-Pin
MB95810K
16 MHz, 2.8-5.5 V
56/2/41
MB95710M
16 MHz, 1.8-5.5 V
56/2/41
MB95770M
16 MHz, 1.8-5.5 V
56/2/41
MB95630H
16 MHz, 2.4-5.5 V
32/1/41
MB95610H
16 MHz, 2.4-5.5 V
32/1/41
MB95560H
16 MHz, 2.4-5.5 V,
16/0.5/41
MB95570H
16 MHz, 2.4-5.5 V,
16/0.5/41
Concept
Development
Sampling
Production
QQYY
QQYY
Status
1
Flash KB/SRAM KB/work Flash KB; work Flash is independent Flash memory available to store data or additional firmware
Document No. 001-89435 Rev. *P
Availability
53
PSoC® 4000 S-Series
PSoC MCU Family
Applications
Consumer devices (wearable, mobile, personal care)
Small home appliances (coffee machine, juicer)
Block Diagram
PSoC® 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
I/O Subsystem
GPIO x8
Smart
I/O
Features
32-Bit MCU Subsystem
48-MHz ARM® Cortex®-M0+ CPU
Up to 32KB Flash, 4KB SRAM
Real-time clock capability with a WCO1
Programmable Analog Blocks
One 10-bit, 46.8-ksps single-slope ADC2
Two low-power comparators (CMP)
One CapSense® block that supports low-power operation and
mutual-capacitance sensing
Two 7-bit IDACs3 configurable as a single 8-bit IDAC
Programmable Digital Blocks
Five 16-bit timer, counter, PWM (TCPWM) blocks
Two serial communication blocks (SCBs) that are configurable
as I2C, SPI or UART
Packages
25-ball WLCSP, 24-pin QFN, 32-pin QFN, 48-pin TQFP
Up to 36 GPIOs, including 16 Smart I/Os4
Collateral
Datasheet:
Flash
(16KB to 32KB)
SRAM
(2KB to 4KB)
CMP
x2
7-bit IDAC
x2
Single-Slope
ADC
CapSense
Programmable Digital
Blocks
WCO
TCPWM x5
Serial Wire Debug
SCB x2
Programmable Interconnect and Routing
48 MHz
Advanced High-Performance Bus (AHB)
Cortex®-M0+
GPIO x8
Smart
I/O
GPIOx8
GPIO x8
GPIO x4
Availability
PSoC 4000S
Production:
1 Watch
3 Current
2
4 Embedded
crystal oscillator
A simple ADC used to measure slow-moving signals
Document No. 001-89435 Rev. *P
Now
output digital-to-analog converter
programmable digital logic in the I/O subsystem
54
PSoC® 4100 S-Series
Intelligent Analog Family
Applications
Block Diagram
Home appliances (washing machine, dishwasher)
Industrial applications
PSoC® 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
I/O Subsystem
GPIO x8
Features
Collateral
48 MHz
Flash
(16KB to 64KB)
SRAM
(4KB to 8KB)
CMP
x2
7-bit IDAC5
x2
Single-Slope
ADC3
CapSense
Programmable Digital
Blocks
WCO1
TCPWM x5
Serial Wire Debug
SCB x3
Programmable Interconnect and Routing
Cortex®-M0+
GPIO x8
Smart
I/O6
GPIOx8
GPIO x8
GPIO x4
Production:
1 Watch
3A
2
4 Programmable
Document No. 001-89435 Rev. *P
Smart
I/O6
SAR2 ADC
Availability
Datasheet: PSoC 4100S
crystal oscillator
Successive approximation register
Opamp
x2
Advanced High-Performance Bus (AHB)
32-Bit MCU Subsystem
48-MHz ARM® Cortex®-M0+ CPU
Up to 64KB Flash, 8KB SRAM
Real-time clock capability with a WCO1
Programmable Analog Blocks
One 12-bit, 1-Msps SAR2 ADC
One 10-bit, 46.8-ksps single-slope ADC3
Two opamps configurable as PGAs4, comparators, etc.
Two low-power comparators (CMP)
One CapSense® block that supports low-power operation with
self- and mutual-capacitance sensing
Two 7-bit IDACs5 configurable as a single 8-bit IDAC
Programmable Digital Blocks
Five 16-bit timer, counter, PWM (TCPWM) blocks
Three serial communication blocks (SCBs) that are configurable
as I2C, SPI or UART
Packages
35-ball WLCSP, 32-pin QFN, 40-pin QFN, 48-pin TQFP
Up to 36 GPIOs, including 16 Smart I/Os6
simple ADC used to measure slow-moving signals
gain amplifier
Now
5 Current
6
output digital-to-analog converter
Embedded programmable digital logic in the I/O subsystem
55
PSoC® 4100P S-Series
Intelligent Analog Family
Block Diagram
Consumer products and industrial applications
PSoC® 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
Features
Collateral
48 MHz
Flash
(16KB to 32KB)
SRAM
(4KB)
DMA
WCO1
7-bit IDAC5
x2
CMP
x2
AMUX
x38
Smart
I/O6
SAR2 ADC
Single-Slope
ADC3
CapSense
13-bit VDAC
Programmable Digital
Blocks
GPIOx8
GPIOx8
GPIO x8
TCPWM x8
Serial Wire Debug
SCB x3
Sampling:
Production:
1 Watch
3A
2
4 Programmable
Document No. 001-89435 Rev. *P
Cortex®-M0+
GPIO x8
GPIO x6
Availability
Preliminary Datasheet: Contact Sales
crystal oscillator
Successive approximation register
Opamp
x4
Advanced High-Performance Bus (AHB)
32-Bit MCU Subsystem
48-MHz ARM® Cortex®-M0+ CPU with a DMA controller
Up to 32KB Flash, 4KB SRAM
Real-time clock capability with a WCO1
Programmable Analog Blocks
One 12-bit, 1-Msps SAR2 ADC
One 10-bit, 11.6-Ksps Single-Slope ADC3
Four opamps configurable as PGAs4, comparators, TIAs, etc.
Two low-power comparators (CMP)
One CapSense® block that supports low-power operation with
self- and mutual-capacitance sensing
One 13-bit Voltage output digital-to-analog converter (VDAC)
Two 7-bit IDACs5 configurable as a single 8-bit IDAC
Programmable Digital Blocks
Eight 16-bit Timer, Counter, PWM (TCPWM) blocks
Three serial communication blocks (SCBs) that are configurable
as I2C, SPI or UART
Packages
28-pin SSOP, 45-ball WLCSP, 48-pin QFN, 48-pin TQFP
Up to 38 GPIOs, including 8 Smart I/Os6
I/O Subsystem
Programmable Interconnect and Routing
Applications
simple ADC used to measure slow-moving signals
gain amplifier
Now
Q2 2017
5 Current
6
output digital-to-analog converter
Embedded programmable digital logic in the I/O subsystem
Product Overview
56
PSoC® 4100 BLE-Series
Intelligent Analog Family with Bluetooth Low Energy
Applications
Block Diagram
PSoC 4 BLE One-Chip Solution
MCU Subsystem
Features
Collateral
Analog front end(s)
Successive approximation register
Document No. 001-89435 Rev. *P
BLE System
Flash
(128KB to 256KB)
SRAM
(16KB to 32KB)
Serial Wire Debug
Opamp
x4
SAR
ADC
CMP
x2
CSD
Programmable Digital
Blocks
TCPWM x4
SCB x2
I/O Subsystem
GPIO x8
GPIO x8
GPIO x8
GPIO x8
Segment LCD Drive
GPIO x4
Availability
Datasheet: PSoC 4 BLE (CY8C4XX7 BLE)
2
24 MHz
Advanced High-Performance Bus (AHB)
Cortex®-M0
32-bit MCU subsystem
24-MHz ARM® Cortex®-M0 CPU
Up to 256KB Flash and 32KB SRAM
Programmable AFE1
Four opamps, configurable as PGAs, comparators, filters, etc.
One 12-bit, 1-Msps SAR2 ADC
CapSense® with SmartSense™ Auto-tuning
Industry’s No. 1 capacitive-sensing solution with one Capacitive
Sigma-Delta™ (CSD) controller with touchpad capability
Programmable digital logic
Four configurable TCPWM3 blocks: 16-bit timer, counter or PWM
Two configurable serial communication blocks (SCBs):
I2C master or slave, SPI master or slave, or UART
Packages
56-pin QFN, 68-pin CSP
Bluetooth connectivity with Bluetooth 4.1 or Bluetooth 4.24
Royalty-free stack and GUI-based Component to configure profiles
2.4-GHz BLE radio with integrated balun
1
Programmable Analog
Blocks
Programmable Interconnect and Routing
Sports and fitness monitors, wearable electronics, medical
devices, home automation solutions, game controllers, sensorbased low-power systems for the Internet of Things (IoT)
3
Production:
Now
Timer/counter/pulse-width modulation block
4.2 is only available in the 256KB Flash option device
4 Bluetooth
57
PSoC® 4200 BLE-Series
Programmable Digital Family with Bluetooth Low Energy
Applications
Block Diagram
PSoC 4 BLE One-Chip Solution
MCU Subsystem
Features
Collateral
Analog front end(s)
Successive approximation register
Document No. 001-89435 Rev. *P
BLE System
Flash
(128KB to 256KB)
SRAM
(16KB to 32KB)
Advanced High-Performance Bus (AHB)
48 MHz
CMP
x2
I/O Subsystem
GPIO x8
SAR2
ADC
CSD
Programmable Digital
Blocks
UDB x4
TCPWM4 x4
SCB x2
GPIO x8
GPIO x8
GPIO x8
Segment LCD Drive
Serial Wire Debug
GPIO x4
Availability
Datasheet: PSoC 4 BLE (CY8C4XX7 BLE)
2
Opamp
x4
Cortex®-M0
32-bit MCU subsystem
48-MHz Cortex®-M0 with up to 256KB Flash and 32KB SRAM
Programmable AFE1
Four opamps, configurable as PGAs, comparators, filters, etc.
One 12-bit, 1-Msps SAR2 ADC
CapSense® with SmartSense™ Auto-tuning
Industry’s No. 1 capacitive-sensing solution with one Capacitive
Sigma-Delta™ (CSD) controller with touchpad capability
Programmable digital logic
Four universal digital blocks (UDBs3): custom digital peripherals
Four configurable TCPWM4 blocks: 16-bit timer, counter or PWM
Two configurable serial communication blocks (SCBs):
I2C master or slave, SPI master or slave, or UART
Packages
56-pin QFN, 68-pin CSP
Bluetooth connectivity with Bluetooth 4.1 or Bluetooth 4.25
Royalty-free stack and GUI-based Component to configure profiles
2.4-GHz BLE radio with integrated balun
1
Programmable Analog
Blocks
Programmable Interconnect and Routing
Sports and fitness monitors, wearable electronics, medical
devices, home automation solutions, game controllers, sensorbased low-power systems for the Internet of Things (IoT)
3
4
Universal digital block
Timer/counter/pulse-width modulation block
Production:
5 Bluetooth
Now
4.2 is only available in the 256KB Flash option device
58
PSoC® 4100 M-Series
Intelligent Analog Family
Applications
Block Diagram
User interface and host processor for home appliances
Digital and analog sensor hub
MCU and discrete analog replacement
PSoC 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
GPIO x8
Opamp
x4
Features
32-bit MCU subsystem
24-MHz ARM® Cortex®-M0 CPU with a DMA controller and RTC
Up to 128KB Flash and 16KB SRAM
CapSense® with SmartSense™ Auto-tuning
Cypress Capacitive Sigma-Delta™ (CSD) controller
CapSense supported on up to 55 pins
Programmable Analog Blocks
Two comparators (CMP)
Four opamps, programmed as PGAs, CMPs, filters, etc.
One 12-bit, 1-Msps SAR1 ADC
Four IDACs2 (2x 8-bit, 2x 7-bit)
Programmable Digital Blocks
Eight programmable 16-bit TCPWM3 blocks
Four serial communication blocks (SCBs): I2C master or slave,
SPI master or slave, or UART
Packages: 48-pin LQFP, 64-pin TQFP (0.8-mm pitch),
64-pin TQFP (0.5-mm pitch), 68-pin QFN
GPIO x8
SRAM
(8KB to 16KB)
Serial Wire Debug
CSD
8-bit
IDAC x2
7-bit
IDAC x2
Programmable Digital
Blocks
TCPWM x8
Programmable Interconnect and Routing
Flash
(64KB to 128KB)
Advanced High-Performance Bus (AHB)
24 MHz
CMP
x2
GPIO x8
GPIO x8
GPIO x8
SCB x4
GPIO x8
Segment LCD Drive
GPIO x7
RTC
DMA
Availability
Production:
PSoC 4 M-Series (CY8C4100)
1 Successive
2
SAR
ADC
Cortex®-M0
Collateral
Datasheet:
I/O Subsystem
approximation register
Current-output digital-to-analog converter
Document No. 001-89435 Rev. *P
3
Now
Timer/counter/pulse-width modulation block
59
PSoC® 4200 M-Series
Programmable Digital Family
Applications
Block Diagram
User interface and host processor for home appliances
Digital and analog sensor hub
LED control and communication for lighting systems
PSoC 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
I/O Subsystem
GPIO x8
Opamp
x4
Features
Collateral
Datasheet:
GPIO x8
48 MHz
Flash
(64KB to 128KB)
SRAM
(8KB to 16KB)
Serial Wire Debug
CAN x2
CMP
x2
CSD
8-bit
IDAC x2
7-bit
IDAC x2
Programmable Digital
Blocks
UDB x4
TCPWM x8
Programmable Interconnect and Routing
Cortex®-M0
Advanced High-Performance Bus (AHB)
32-bit MCU subsystem
48-MHz ARM® Cortex®-M0 CPU with a DMA controller and RTC
Up to 128KB Flash and 16KB SRAM
CapSense® with SmartSense™ Auto-tuning
Cypress Capacitive Sigma-Delta™ (CSD) controller
CapSense supported on up to 55 pins
Programmable Analog Blocks
Two comparators (CMP)
Four opamps, programmed as PGAs, CMPs, filters, etc.
One 12-bit, 1-Msps SAR1 ADC
Four IDACs2 (2x 8-bit, 2x 7-bit)
Programmable Digital Blocks
Four universal digital blocks (UDBs3): custom digital peripherals
Eight programmable 16-bit TCPWM4 blocks
Four SCBs5: I2C master or slave, SPI master or slave, or UART
Two controller area network (CAN) controllers
Packages: 48-pin LQFP, 64-pin TQFP (0.8-mm pitch),
64-pin TQFP (0.5-mm pitch), 68-pin QFN
SAR
ADC
GPIO x8
GPIO x8
GPIO x8
GPIO x8
RTC
SCB x4
DMA
Segment LCD Drive
GPIO x7
Availability
Production:
PSoC 4 M-Series (CY8C4200)
1 Successive
3
2
4
approximation register
Current-output digital-to-analog converter
Document No. 001-89435 Rev. *P
Now
Universal digital block
Timer/counter/pulse-width modulation block
5 Serial
communication block programmable as I2C/SPI/UART
60
PSoC® 4200 L-Series
Programmable Digital Family
Block Diagram
Applications
User interface and host processor for home appliances
Digital and analog sensor hub
MCU and discrete analog replacement
LED control and communication for lighting systems
PSoC® 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
Features
Opamp
x4
SAR
ADC
CMP
x6
CSD
x2
8-bit
IDAC
x2
7-bit
IDAC
x2
I/O Subsystem
GPIO x8
GPIO x8
Cortex®-M0
Flash
(64KB to 256KB)
SRAM
(8KB to 32KB)
Serial Wire Debug
CAN x2
Full-Speed
USB 2.0
RTC
DMA
Collateral
Datasheet:
1 Real-time
Programmable Digital
Blocks
UDB x8
TCPWM x8
Programmable Interconnect and Routing
48 MHz
GPIO x8
Advanced High-Performance Bus (AHB)
32-bit MCU Subsystem
48-MHz ARM® Cortex®-M0 CPU with a DMA controller and RTC1
Up to 256KB Flash and 32KB SRAM
Up to 98 GPIOs supporting analog and digital interfaces
CapSense® With SmartSense™ Auto-tuning
Two Cypress Capacitive Sigma-Delta™ (CSD) controllers
Programmable Analog Blocks
Two comparators (CMPs)
Four opamps, configurable as PGAs, CMPs, filters, etc.
One 12-bit, 1-Msps SAR2 ADC
Four IDACs3 (2x 8-bit, 2x 7-bit)
Programmable Digital Blocks
Eight universal digital blocks (UDBs): custom digital peripherals
Eight configurable 16-bit TCPWM4 blocks
Four SCBs5: I2C master or slave, SPI master or slave, or UART
Full-Speed USB 2.0 Controller and Transceiver
Two Controller Area Network (CAN) Controllers
Packages: 48-pin TQFP, 64-pin TQFP, 68-pin QFN,
124-pin VFBGA
GPIO x8
GPIO x8
GPIO x8
GPIO x8
GPIO x8
GPIO x8
GPIO x8
SCB x4
GPIO x8
Segment LCD Drive
GPIO x4
Availability
Production:
PSoC 4 L-Series
clock
approximation register
2 Successive
Document No. 001-89435 Rev. *P
3
4
Current-output digital-to-analog converter
Timer/counter/pulse-width modulation block
5
Now
Serial communication block programmable as I2C/SPI/UART
61
PSoC® Analog Coprocessor
Block Diagram
Industrial sensors (photoelectric sensors, displacement sensors),
instrumentation and measurement (photometers, pH meters),
and consumer products (wearables, grooming products)
Programmable Analog Blocks
Opamp
x4
12-bit SAR
Features
Programmable Analog Blocks
One Universal Analog Block (UAB) configurable as a:
Programmable Analog Filter or
14-bit Delta-Sigma ADC or
12-bit VDAC1
Four opamps, configurable as PGAs, comparators, TIAs, etc.
One 12-bit, 1-Msps SAR2 ADC
One 10-bit single-slope3 ADC
38-channel analog multiplexer (AMUX)
One CapSense® block configurable as a:
Capacitive-sensing controller or IDACs4 (2x 7-bit) or two
low-power comparators (CMP)
38 GPIOs
Signal Processing Engine
48-MHz ARM® Cortex® -M0+ with a DMA controller and WCO5
Eight 16-bit TCPWM6 blocks
Three SCBs7: configurable as I2C, SPI or UART
Packages: 28-pin SSOP, 45-pin CSP, 48-pin QFN, 48-pin TQFP
Collateral
Preliminary Datasheet:
PSoC® Analog Coprocessor
I/O Subsystem
CMP
x2
Universal Analog Block
14-bit
DeltaSigma
10-bit
Single-Slope
ADC
AMUX
x38
12-bit
VDAC
CapSense
7-bit
IDAC
Analog
Filter
7-bit
IDAC
Signal Processing Engine
Flash
(16KB to 32KB)
Cortex®-M0+
48 MHz
SRAM
(2KB to 4KB)
DMA
TCPWM x8
WCO
SCB x3
GPIO
x8
Programmable Interconnect and Routing
Applications
GPIO
x8
GPIO
x8
GPIO
x8
GPIO
x6
Availability
CY8C4Axx datasheet
1
4
2
5 Watch
Voltage-output DAC
Successive approximation register
3 A simple ADC used to measure slow-moving signals
Document No. 001-89435 Rev. *P
Sampling:
Production:
Now
Q2 2017
Current-output DAC
crystal oscillator
6 Configurable as various timers/counters/pulse-width modulation or quadrature decoders
7 Serial
communication blocks
Product Overview
62
S6E1B-Series
FM0+ MCU Portfolio
Block Diagram
Industrial, M2M connectivity, healthcare, consumer electronics,
sensor hubs, metering and point-of-sale equipment
MCU Subsystem
Features
Cortex®-M0+
40 MHz
Ultra-Low Power MCU Subsystem
Up to 40-MHz ARM® Cortex®-M0+ CPU
65-µA/MHz active current with 1.65-V to 3.6-V operating voltage
Ultra-low-power 0.6-µA real-time clock (RTC) operating current
Up to 512KB Flash and 64KB SRAM with 32KB work Flash1
Near-zero wait-state Flash access at up to 40 MHz
Fast 540-µs startup from power-on reset and 40 µs from standby
MFT
MFS x8
PPG x3
USB
(Host + Device)
GPIO x16
GPIO x15
SRAM
(32KB to 64KB)
LVD4
DSTC5
Internal Main
Oscillator
Clock Supervisor
GPIO x9
Dual Timer
GPIO x16
RTC
I2S
Watch Counter
HDMI x2
Smart Card x2
WDT6
CRC
Pin Relocation
Flash
(304KB to 512KB)
GPIO x14
GPIO x12
GPIO x9
Crypto Assist
GPIO x5
Analog Subsystem
12-bit ADC
LCD Drive
Serial Wire
Debug
Packages: 80-pin LQFP, 100-pin LQFP, 120-pin LQFP,
96-pin BGA, 80-pin CSP (4.35 mm x 6.5 mm)
Datasheet:
I/O Subsystem
Base Timer x8
Analog and Digital Subsystems
Multi-function timer (MFT), 3 programmable pulse generators
(PPG), 8 base timers, dual timer, CRC2 and watch counter
8 channels of multi-function serial (MFS) interfaces configurable
as SPI, UART, I2C or LIN
USB, Inter-IC sound (I2S), 2 HDMI-CEC3 channels, 2 Smart Card
interface channels
12-bit, 1-Msps ADC with a 24-channel multiplexer input
LCD drive with support for up to 44 segments or 8 common outputs
Built-in cryptographic assist hardware coprocessor for encryption
Collateral
Digital Subsystem
Advanced High-Performance Bus (AHB)
Applications
GPIO x3
GPIO x3
Availability
S6E1B3-Series, S6E1B8-Series
Sampling: Now
1
4
2
5
Independent Flash memory available to store data or additional firmware
Cyclical redundancy check
3 HDMI consumer electronics control signal
Document No. 001-89435 Rev. *P
Production: Q1 2017
Low-voltage detect
Descriptor system transfer controller
6 Watchdog timer
63
S6E1C-Series
FM0+ MCU Portfolio
Applications
Block Diagram
Industrial, healthcare, sensor hubs, wearable electronics and
mobile, battery-powered devices
MCU Subsystem
Digital Subsystem
I/O Subsystem
MFS x6
Features
Datasheet:
S6E1C1-Series, S6E1C3-Series
GPIO x12
Base Timer x8
SRAM
(12KB to 16KB)
LVD3
DSTC4
Internal Main
Oscillator
Serial Wire
Debug
Dual Timer
GPIO x3
GPIO x12
RTC
I2S
Watch Counter
HDMI x2
Smart Card
WDT5
Pin Relocation
Flash
(64KB to 128KB)
Clock Supervisor
Collateral
USB
(Host + Device)
Cortex®-M0+
40 MHz
Advanced High-Performance Bus (AHB)
Ultra-Low-Power MCU Subsystem
Up to 40-MHz ARM® Cortex®-M0+ CPU
40-µA/MHz active current with 1.65-V to 3.6-V operating voltage
Low-power 1.2-µA real-time clock (RTC) operating current
Up to 128KB Flash and 16KB SRAM
Near-zero wait-state Flash access at up to 40 MHz
Fast 540-µs startup from power-on reset and 40 µs from standby
Analog and Digital Subsystems
8 base timers, dual timer, CRC1 and watch counter
6 channels of multi-function serial (MFS) interfaces configurable
as SPI, UART, I2C or LIN
USB, Inter-IC sound (I2S), 2 HDMI-CEC2 channels, 2 Smart Card
interface channels
12-bit, 1-Msps ADC with a 24-channel multiplexer input
Packages: 32-pin LQFP, 48-pin LQFP, 64-pin LQFP, 32-pin QFN,
48-pin QFN, 26-pin CSP (2.35mm x 2.72mm)
GPIO x8
GPIO x9
GPIO x4
CRC
GPIO x2
Analog Subsystem
12-bit ADC
GPIO x2
GPIO x2
Availability
Production: Now
1
4
2
5
Cyclical redundancy check
HDMI consumer electronics control signal
3 Low-voltage detect
Document No. 001-89435 Rev. *P
Descriptor system transfer controller
Watchdog timer
64
S6E2C-Series
FM4 MCU Portfolio
Block Diagram
Features
High-Performance MCU Subsystem
675 CoreMark®, 200-MHz ARM® Cortex®-M4 CPU
365-µA/MHz active current with 2.7-V to 5.5-V operating voltage
Ultra-low-power 1.0-µA real-time clock (RTC) operating current
Up to 2MB Flash and 256KB SRAM with 16KB Flash accelerator
Error-correcting code (ECC) support, hardware WDT1, low-voltage
detect and clock supervisor blocks for safety-critical applications
Analog and Digital Subsystems
3 multi-function timers (MFT), 9 programmable pulse generators
(PPG), 16 base timers, 4 quadrature position/revolution
counters (QPRC), a dual timer, CRC2 and watch counter
16 channels of multi-function serial (MFS) interfaces configurable
as SPI, UART, I2C or LIN
Two USB, two CAN3, CAN-FD4, IEEE 1588 Ethernet5, HighSpeed Quad-SPI (HS-QSPI), I2S6 and external bus interfaces
Three 12-bit, 2-Msps ADCs with a 32-channel multiplexer input
Two 12-bit digital-to-analog converters (DACs)
Built-in Cryptographic Assist hardware coprocessor for encryption
Packages: 144-pin LQFP, 176-pin LQFP, 216-pin LQFP,
192-pin BGA
Collateral
Datasheet:
MCU Subsystem
Digital Subsystem
Cortex®-M4
200 MHz
Flash
(1MB to 2MB)
SRAM
(128KB to 256KB)
MPU7
LVD
DMA8
DSTC9
Internal Main
Oscillator
Clock Supervisor
I/O Subsystem
MFT x3
MFS x16
GPIO x8
PPG x9
USB x2
(Host + Device)
GPIO x16
Base Timer x16
CAN x2
Dual Timer
CAN-FD
QPRC x4
IEEE 1588
Ethernet
RTC
SD Card
Watch Counter
HS-QSPI
GPIO x11
I2S
WDT
CRC
GPIO x15
GPIO x16
GPIO x15
GPIO x15
GPIO x4
GPIO x8
External Bus
Interface
GPIO x16
Crypto Assist
GPIO x16
Analog Subsystem
12-bit ADC x3
GPIO x15
Pin Relocation
Motor control, factory automation, industrial, IoT
Building management systems and automation
Advanced High-Performance Bus (AHB)
Applications
GPIO x16
12-bit DAC x2
GPIO x3
GPIO x3
Serial Wire/
JTAG Debug
GPIO x13
Availability
S6E2CC-Series
Production: Now
1
4
7
2
5
8
Watchdog timer
Cyclical redundancy check
3 Controller area network
Document No. 001-89435 Rev. *P
Controller area network with flexible data-rate
Ethernet communications solution that supports the Precision Time Protocol (PTP) standard
6 Inter-IC sound
Memory protection unit
Direct memory access
9 Descriptor System Transfer Controller
65
S6E2G-Series
FM4 MCU Portfolio
Block Diagram
Motor control, factory automation, industrial, Internet of Things (IoT),
and building management systems and automation
MCU Subsystem
Digital Subsystem
Features
Flash
(512KB to 1MB)
SRAM
(128KB to 192KB)
MPU6
LVD
DMA7
DSTC8
Internal Main
Oscillator
Clock Supervisor
MFT x2
MFS x10
GPIO x8
PPG x9
USB x2
(Host + Device)
GPIO x16
Base Timer x16
CAN
GPIO x11
Advanced High-Performance Bus (AHB)
High-Performance MCU Subsystem
608 CoreMark®, 180-MHz ARM® Cortex®-M4 CPU
244-µA/MHz active current with 2.7-V to 5.5-V operating voltage
Up to 1MB Flash and 192KB SRAM with 16KB Flash accelerator
Error-correcting code (ECC) support, hardware WDT1, low-voltage
detect and clock supervisor blocks for safety-critical applications
Analog and Digital Subsystems
2 multi-function timers (MFT), 9 programmable pulse generators
(PPG), 16 base timers, 2 quadrature position/revolution
counters (QPRC), a dual timer, CRC2 and watch counter
10 channels of multi-function serial (MFS) interfaces configurable
as SPI, UART, I2C or LIN
Two USB, CAN3, IEEE 1588 Ethernet4, I2S5, 2 Smart Card
interfaces and an external bus interfaces
Three 12-bit, 2-Msps ADCs with a 32-channel multiplexer input
Built-in Cryptographic Assist hardware coprocessor for encryption
Packages
144-pin LQFP, 176-pin LQFP
Cortex®-M4
180 MHz
I/O Subsystem
GPIO x15
Dual Timer
GPIO x15
QPRC x2
IEEE 1588
Ethernet
RTC
SD Card
Watch Counter
Smart Card x2
I2S
WDT
CRC
Analog Subsystem
12-bit ADC x3
GPIO x6
Pin Relocation
Applications
GPIO x7
GPIO x11
GPIO x4
GPIO x6
External Bus
Interface
GPIO x16
Crypto Assist
GPIO x8
GPIO x16
GPIO x3
GPIO x3
Serial Wire/
JTAG Debug
GPIO x8
Collateral
Datasheet:
S6E2G-Series
Availability
Production: Now
1
Watchdog timer
2 Cyclical redundancy check
3 Controller area network
Document No. 001-89435 Rev. *P
4
Ethernet communications solution that supports the Precision Time Protocol (PTP) standard
5 Inter-IC sound
6 Memory protection unit
7
8
Direct memory access
Descriptor system transfer controller
66
S6E2H-Series
FM4 MCU Portfolio
Block Diagram
Motor control, factory automation, industrial, IoT
DSLR lens MCU and home appliance
MCU Subsystem
Digital Subsystem
MFT x3
High-Performance MCU Subsystem
540 CoreMark®, 160-MHz ARM® Cortex®-M4 CPU
188-µA/MHz active current with 2.7-V to 5.5-V operating voltage
Ultra-low power 1.3-µA real-time clock (RTC) operating current
Up to 512KB Flash and 64KB SRAM with 16KB Flash accelerator
Error-correcting code (ECC) support, hardware WDT1, low-voltage
detect and clock supervisor blocks for safety-critical applications
Analog and Digital Subsystems
3 multi-function timers (MFT), 9 programmable pulse generators
(PPG), 8 base timers, 3 quadrature position/revolution
counters (QPRC), a dual timer, CRC2 and watch counter
8 channels of multi-function serial (MFS) interfaces configurable
as SPI, UART, I2C or LIN
Two CAN3, SD Card and External Bus Interfaces
Three 12-bit, 2-Msps ADCs with a 24-channel multiplexer input
Two 12-bit digital-to-analog converters (DACs)
Packages
80-pin LQFP, 100-pin LQFP, 120-pin LQFP, 121-pin BGA
SRAM
(32KB to 64KB)
MPU4
LVD
DMA5
DSTC6
Internal Main
Oscillator
Clock Supervisor
Serial Wire/
JTAG Debug
GPIO x15
GPIO x16
Base Timer x8
Flash
(256KB to 512KB)
MFS x8
PPG x9
Cortex®-M4
160 MHz
Advanced High-Performance Bus (AHB)
Features
I/O Subsystem
CAN x2
GPIO x8
Dual Timer
QPRC x3
RTC
GPIO x16
SD Card
Watch Counter
WDT
CRC
External Bus
Interface
Pin Relocation
Applications
GPIO x14
GPIO x12
GPIO x9
GPIO x5
Analog Subsystem
12-bit ADC x3
12-bit DAC x2
GPIO x2
GPIO x3
Collateral
Datasheet:
S6E2H-Series
Availability
Production: Now
1
4
2
5
Watchdog timer
Cyclical redundancy check
3 Controller area network
Document No. 001-89435 Rev. *P
Memory protection unit
Direct memory access
6 Descriptor System Transfer Controller
67
Low-Cost PSoC® Development Kits
PSoC Prototyping Kits
Bluetooth Low Energy (BLE)
Pioneer Development Kit
PSoC 5LP Development Kit
by SparkFun1
Kit Number
CY8CKIT-049 or CY8CKIT-059
CY8CKIT-042-BLE
DEV-13229
Key Features
Ultra-low-cost prototyping
Breadboard-compatible
Serial wire debug (SWD) or
bootload for program/debug
Arduino form factor-compatible
Access to all PSoC 4 BLE I/Os
Full SWD program and debug
Arduino form factor-compatible
Access to all PSoC 5LP I/Os
Full SWD program and debug
Price
$4-$10
$49
$50
Learn more or buy a kit today at www.cypress.com/kits
1 SparkFun
is an online retail store that specializes in supporting the hobbyist market with kits and tools to develop small electronics products
Document No. 001-89435 Rev. *P
68
Low-Cost FM® Development Kits
FM0+ S6E1B-Series Pioneer Kit FM4 S6E2C-Series Pioneer Kit
FM4 S6E2H-Series Pioneer Kit
Kit Number
FM0-100L-S6E1B8
FM4-176L-S6E2CC-ETH
FM4-176L-S6E2H
Key Features
Arduino form factor-compatible
Full SWD program and debug
Arduino form factor-compatible
Full SWD program and debug
Arduino form factor-compatible
Full SWD program and debug
Price
$49
$49
$25
Learn more or buy a kit today at www.cypress.com/kits
Document No. 001-89435 Rev. *P
69
MCU Packages
Package
LQFP
Pins
48
PSoC 1
PDIP
QFN
8
20
28
16
24
32






40
SOIC
48
56
68
8
16
20
28











68
72

PSoC 3

PSoC 4







PSoC 5LP

CapSense
Package



SSOP
TQFP
Pins
8
16
20
24
28
32
48
44
PSoC 1








48
WLCSP
64

PSoC 4
100
30
32



PSoC 3







PSoC 5LP

CapSense
Package

WLCSP M-WLCSP1
Pins
99
PSoC 1

104


µBGA
116
124
PSoC 3

PSoC 4
PSoC 5LP

PSoC 6


CapSense
1 Multi-die
WLCSP
Document No. 001-89435 Rev. *P
70
Additional MCU Packages
Package
SSOP
TSSOP
SDIP
QFN
Pins
8
16
20
24
16
20
24
32
32
8FX










FM0+
FM3
48
Pins
80
8FX

FM0+
100
120



FM3





FM4





Document No. 001-89435 Rev. *P
144
176
216
QFP
TQFP
100
120
32
48
52
64
















LQFP
64

FM4
Package
LQFP


BGA
96
112
121
WLCSP
161
192





26
80









71
CapSense Controllers
Document No. 001-89435 Rev. *P
72
CapSense Express™
CapSense Plus™
PSoC®
Configurable Controllers1
Programmable Controllers2
Programmable System-on-Chip2
CY8CMBR3106S
11 Buttons, 2 Sliders
Proximity, Liquid Tolerance
SmartSense_EMCplus™3
CY8CMBR3116
16 Buttons, 8 LEDs
Proximity, Liquid Tolerance
SmartSense_EMCplus
CY8CMBR3108
8 Buttons, 4 LEDs
Proximity, Liquid Tolerance
SmartSense_EMCplus
CY8CMBR3110
10 Buttons, 5 LEDs
Proximity, Liquid Tolerance
SmartSense_EMCplus
Performance
CY8C56xx/58xx
62 Buttons, 12 Sliders
64, 128, 256KB Flash
Proximity, Liquid Tolerance
SmartSense_EMCplus
CY8C20xx7
31 Buttons, 6 Sliders
16, 32KB Flash
Proximity, Liquid Tolerance
SmartSense™ Auto-tuning
CY8C52xx/54xx
62 Buttons, 12 Sliders
32, 64, 128, 256KB Flash
Proximity, Liquid Tolerance
SmartSense_EMCplus
CY8C36xx/38xx
62 Buttons, 12 Sliders
32, 64KB Flash
Proximity, Liquid Tolerance
SmartSense_EMCplus
CY8C20xx6A/S
33 Buttons, 6 Sliders
16, 32KB Flash, 2KB SRAM
SmartSense Auto-tuning
CY8C4xx8-BL
36 Buttons, 7 Sliders
256KB Flash, BLE4
Proximity, Liquid Tolerance
SmartSense_EMCplus
CY8CMBR2110
10 Buttons, 10 LEDs
SmartSense Auto-tuning
Portfolio
CY8C32xx/34xx
62 Buttons, 12 Sliders
16, 32, 64KB Flash
Proximity, Liquid Tolerance
SmartSense_EMCplus
CY8CMBR2016
16 Buttons
SmartSense Auto-tuning
CY8C20xx6H
25 Buttons, 5 Sliders
8, 16KB Flash
SmartSense Auto-tuning
Haptics
CY8C21x34/B
24 Buttons, 4 Sliders
8KB Flash
Proximity, Liquid Tolerance
SmartSense Auto-tuning
CY8C41xx/42xx
36 Buttons, 7 Sliders
16, 32KB Flash
Proximity, Liquid Tolerance
SmartSense_EMCplus
CY8C41xxS
36 Buttons, 7 Sliders
64KB Flash, 4th Gen
Proximity, Liquid Tolerance
SmartSense_EMCplus
CY8C20x36A
33 Buttons, 6 Sliders
8KB Flash
SmartSense Auto-tuning
CY8C28xx
44 Buttons, 8 Sliders
16KB Flash
Proximity, Liquid Tolerance
SmartSense Auto-tuning
NEW
CY8C40xx
16 Buttons, 3 Sliders
8, 16KB Flash
Proximity, Liquid Tolerance
SmartSense_EMCplus
CY8C40xxS
36 Buttons, 7 Sliders
32KB Flash, 4th Gen
Proximity, Liquid Tolerance
SmartSense_EMCplus
CapSense®
CY8CMBR3102
2 Buttons, Proximity
SmartSense_EMCplus
CY8C4246/7
96 Buttons, 19 Sliders
64, 128KB Flash
Proximity, Liquid Tolerance
SmartSense_EMCplus
CY8CMBR2044
4 Buttons, 4 LEDs
SmartSense Auto-tuning
CY8CMBR2010
10 Buttons, 10 LEDs
SmartSense Auto-tuning
CY8CMBR3002
2 Buttons, 2 LEDs
SmartSense_EMCplus
CY8C201xx
10 Buttons, 5 LEDs
2 Sliders
CY8C20x34
25 Buttons, 6 Sliders
8KB Flash
CY8C41xxPS Q117
38 Buttons, 7 Sliders
32KB Flash, 4th Gen
Proximity, Liquid Tolerance
SmartSense_EMCplus
Integration
1 Standard
products that are configured for target applications with a graphical user interface
2 Microcontroller-based products that can be freely programmed to implement additional functions
3 SmartSense Electromagnetic Compatible = SmartSense Auto-tuning + high noise immunity
Document No. 001-89435 Rev. *P
4
Production Sampling Development Concept
Bluetooth Low Energy
Status
Availability
QQYY
QQYY
73
PSoC® 4000 S-Series
PSoC MCU Family
Applications
Consumer devices (wearable, mobile, personal care)
Small home appliances (coffee machine, juicer)
Block Diagram
PSoC® 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
I/O Subsystem
GPIO x8
Smart
I/O4
Features
32-Bit MCU Subsystem
48-MHz ARM® Cortex®-M0+ CPU
Up to 32KB Flash, 4KB SRAM
Real-time clock capability with a WCO1
Programmable Analog Blocks
One 10-bit, 46.8-ksps Single-Slope ADC2
Two low-power comparators (CMP)
One CapSense® block that supports low-power operation and
mutual-capacitance sensing
Two 7-bit IDACs3 configurable as a single 8-bit IDAC
Programmable Digital Blocks
Five 16-bit timer, counter, PWM (TCPWM) blocks
Two serial communication blocks (SCBs) that are configurable
as I2C, SPI or UART
Packages
25-ball WLCSP, 24-pin QFN, 32-pin QFN, 48-pin TQFP
Up to 36 GPIOs, including 16 Smart I/Os4
Collateral
Datasheet:
Flash
(16KB to 32KB)
SRAM
(2KB to 4KB)
CMP
x2
7-bit IDAC3
x2
Single-Slope
ADC2
CapSense
Programmable Digital
Blocks
WCO1
TCPWM x5
Serial Wire Debug
SCB x2
Programmable Interconnect and Routing
48 MHz
Advanced High-Performance Bus (AHB)
Cortex®-M0+
GPIO x8
Smart
I/O
GPIOx8
GPIO x8
GPIO x4
Availability
PSoC 4000S
Production:
1 Watch
3 Current
2
4 Embedded
crystal oscillator
A simple ADC used to measure slow-moving signals
Document No. 001-89435 Rev. *P
Now
output digital-to-analog converter
programmable digital logic in the I/O subsystem
74
PSoC® 4100 S-Series
Intelligent Analog Family
Applications
Block Diagram
Home appliances (washing machine, dishwasher)
Industrial applications
PSoC® 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
I/O Subsystem
GPIO x8
Features
Collateral
48 MHz
Flash
(16KB to 64KB)
SRAM
(4KB to 8KB)
CMP
x2
7-bit IDAC5
x2
Single-Slope
ADC3
CapSense
Programmable Digital
Blocks
WCO1
TCPWM x5
Serial Wire Debug
SCB x3
Programmable Interconnect and Routing
Cortex®-M0+
GPIO x8
Smart
I/O6
GPIOx8
GPIO x8
GPIO x4
Production:
1 Watch
3A
2
4 Programmable
Document No. 001-89435 Rev. *P
Smart
I/O6
SAR2 ADC
Availability
Datasheet: PSoC 4100S
crystal oscillator
Successive approximation register
Opamp
x2
Advanced High-Performance Bus (AHB)
32-Bit MCU Subsystem
48-MHz ARM® Cortex®-M0+ CPU
Up to 64KB Flash, 8KB SRAM
Real-time clock capability with a WCO1
Programmable Analog Blocks
One 12-bit, 1-Msps SAR2 ADC
One 10-bit, 46.8-ksps Single-Slope ADC3
Two opamps configurable as PGAs4, comparators, etc.
Two low-power comparators (CMP)
One CapSense® block that supports low-power operation with
self- and mutual-capacitance sensing
Two 7-bit IDACs5 configurable as a single 8-bit IDAC
Programmable Digital Blocks
Five 16-bit timer, counter, PWM (TCPWM) blocks
Three serial communication blocks (SCBs) that are configurable
as I2C, SPI or UART
Packages
35-ball WLCSP, 32-pin QFN, 40-pin QFN, 48-pin TQFP
Up to 36 GPIOs, including 16 Smart I/Os6
simple ADC used to measure slow-moving signals
gain amplifier
Now
5 Current
6
output digital-to-analog converter
Embedded programmable digital logic in the I/O subsystem
75
PSoC® 4100P S-Series
Intelligent Analog Family
Applications
Block Diagram
Consumer products
Industrial applications
PSoC® 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
I/O Subsystem
GPIO x8
Features
Collateral
Flash
(16KB to 32KB)
SRAM
(4KB)
DMA
WCO1
7-bit IDAC5
x2
CMP
x2
AMUX
x38
Single-Slope
ADC3
CapSense
13-bit VDAC
Programmable Digital
Blocks
Programmable Interconnect and Routing
48 MHz
GPIOx8
GPIOx8
GPIO x8
TCPWM x8
Serial Wire Debug
SCB x3
Sampling:
Production:
1 Watch
3A
2
4 Programmable
Document No. 001-89435 Rev. *P
Cortex®-M0+
Smart
I/O6
SAR2 ADC
GPIO x6
Availability
Preliminary Datasheet: Contact Sales
crystal oscillator
Successive approximation register
Opamp
x4
Advanced High-Performance Bus (AHB)
32-Bit MCU Subsystem
48-MHz ARM® Cortex®-M0+ CPU with a DMA controller
Up to 32KB flash, 4KB SRAM
Real-time clock capability with a WCO1
Programmable Analog Blocks
One 12-bit, 1-Msps SAR2 ADC
One 10-bit, 11.6-Ksps Single-Slope ADC3
Four opamps configurable as PGAs4, comparators, TIAs, etc.
Two low-power comparators (CMP)
One CapSense® block that supports low-power operation with
self- and mutual-capacitance sensing
One 13-bit Voltage output digital-to-analog converter (VDAC)
Two 7-bit IDACs5 configurable as a single 8-bit IDAC
Programmable Digital Blocks
Eight 16-bit Timer, Counter, PWM (TCPWM) blocks
Three serial communication blocks (SCBs) that are configurable
as I2C, SPI or UART
Packages
28-pin SSOP, 45-ball WLCSP, 48-pin QFN, 48-pin TQFP
Up to 38 GPIOs, including 8 Smart I/Os6
simple ADC used to measure slow-moving signals
gain amplifier
Now
Q2 2017
5 Current
6
output digital-to-analog converter
Embedded programmable digital logic in the I/O subsystem
Product Overview
76
PSoC® 4100 BLE-Series
Intelligent Analog Family with Bluetooth Low Energy
Applications
Block Diagram
PSoC 4 BLE One-Chip Solution
MCU Subsystem
Features
Collateral
Analog front end(s)
Successive approximation register
Document No. 001-89435 Rev. *P
BLE System
Flash
(128KB to 256KB)
SRAM
(16KB to 32KB)
Advanced High-Performance Bus (AHB)
24 MHz
Serial Wire Debug
CMP
x2
I/O Subsystem
GPIO x8
SAR2
ADC
CSD
Programmable Digital
Blocks
TCPWM3 x4
SCB4 x2
GPIO x8
GPIO x8
GPIO x8
Segment LCD Drive
GPIO x4
Availability
Datasheet: PSoC 4 BLE (CY8C4XX7 BLE)
2
Opamp
x4
Cortex®-M0
32-bit MCU subsystem
24-MHz ARM® Cortex®-M0 CPU
Up to 256KB Flash and 32KB SRAM
Programmable AFE1
Four opamps, configurable as PGAs, comparators, filters, etc.
One 12-bit, 1-Msps SAR2 ADC
CapSense® with SmartSense™ Auto-tuning
Industry’s No. 1 capacitive-sensing solution with one Capacitive
Sigma-Delta™ (CSD) controller with touchpad capability
Programmable digital logic
Four configurable TCPWM3 blocks: 16-bit timer, counter or PWM
Two configurable serial communication blocks (SCBs4):
I2C master or slave, SPI master or slave, or UART
Packages
56-pin QFN, 68-pin CSP
Bluetooth connectivity with Bluetooth 4.1 or Bluetooth 4.25
Royalty-free stack and GUI-based Component to configure profiles
2.4-GHz BLE radio with integrated balun
1
Programmable Analog
Blocks
Programmable Interconnect and Routing
Sports and fitness monitors, wearable electronics, medical
devices, home automation solutions, game controllers, sensorbased low-power systems for the Internet of Things (IoT)
3 Timer,
4 Serial
Production:
counter, PWM block
communication block programmable as I2C/SPI/UART
Now
5 Bluetooth
4.2 is only available in the 256KB flash option device
77
PSoC® 4200 BLE-Series
Programmable Digital Family with Bluetooth Low Energy
Applications
Block Diagram
Features
Collateral
Analog front end(s)
Successive approximation register
Document No. 001-89435 Rev. *P
Programmable Analog
Blocks
Opamp
x4
BLE System
Flash
(128KB to 256KB)
SRAM
(16KB to 32KB)
Advanced High-Performance Bus (AHB)
48 MHz
CMP
x2
I/O Subsystem
GPIO x8
SAR2
ADC
CSD
Programmable Digital
Blocks
UDB3 x4
TCPWM4 x4
SCB5 x2
GPIO x8
GPIO x8
GPIO x8
Segment LCD Drive
Serial Wire Debug
GPIO x4
Availability
Datasheet: PSoC 4 BLE (CY8C4XX7 BLE)
2
MCU Subsystem
Cortex®-M0
32-bit MCU subsystem
48-MHz Cortex®-M0 with up to 256KB flash and 32KB SRAM
Programmable AFE1
Four opamps, configurable as PGAs, comparators, filters, etc.
One 12-bit, 1-Msps SAR2 ADC
CapSense® with SmartSense™ Auto-tuning
Industry’s No. 1 capacitive-sensing solution with one Capacitive
Sigma-Delta™ (CSD) controller with touchpad capability
Programmable digital logic
Four universal digital blocks (UDBs3): custom digital peripherals
Four configurable TCPWM4 blocks: 16-bit timer, counter or PWM
Two configurable serial communication blocks (SCBs5):
I2C master or slave, SPI master or slave, or UART
Packages
56-pin QFN, 68-pin CSP
Bluetooth connectivity with Bluetooth 4.1 or Bluetooth 4.26
Royalty-free stack and GUI-based Component to configure profiles
2.4-GHz BLE radio with integrated balun
1
PSoC 4 BLE One-Chip Solution
Programmable Interconnect and Routing
Sports and fitness monitors, wearable electronics, medical
devices, home automation solutions, game controllers, sensorbased low-power systems for the Internet of Things (IoT)
3
4
Universal digital block
Timer/counter/PWM
Production:
5
6
Now
Serial communication block programmable as I2C/SPI/UART
Bluetooth 4.2 is only available in the 256KB flash option device
78
PSoC® 4100 M-Series
Intelligent Analog Family
Applications
Block Diagram
User interface and host processor for home appliances
Digital and analog sensor hub
MCU and discrete analog replacement
PSoC 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
GPIO x8
SAR1
ADC
Opamp
x4
Features
32-bit MCU subsystem
24-MHz ARM® Cortex®-M0 CPU with a DMA controller and RTC
Up to 128KB Flash and 16KB SRAM
CapSense® with SmartSense™ Auto-tuning
Cypress Capacitive Sigma-Delta™ (CSD) controller
CapSense supported on up to 55 pins
Programmable Analog Blocks
Two comparators (CMP)
Four opamps, programmed as PGAs, CMPs, filters, etc.
One 12-bit, 1-Msps SAR1 ADC
Four IDACs2 (2x 8-bit, 2x 7-bit)
Programmable Digital Blocks
Eight programmable 16-bit TCPWM3 blocks
Four SCBs4: I2C master or slave, SPI master or slave, or UART
Packages: 48-pin LQFP, 64-pin TQFP (0.8-mm pitch),
64-pin TQFP (0.5-mm pitch), 68-pin QFN
GPIO x8
Flash
(64KB to 128KB)
SRAM
(8KB to 16KB)
Serial Wire Debug
CMP
x2
CSD
8-bit
IDAC2
x2
7-bit
IDAC2
x2
Programmable Digital
Blocks
TCPWM3 x8
Programmable Interconnect and Routing
24 MHz
Advanced High-Performance Bus (AHB)
Cortex®-M0
GPIO x8
GPIO x8
GPIO x8
SCB4 x4
GPIO x8
Segment LCD Drive
GPIO x7
RTC
DMA
Collateral
Datasheet:
I/O Subsystem
Availability
PSoC 4 M-Series (CY8C4100)
Production:
1 Successive
3
2
4
approximation register
Current-output digital-to-analog converter
Document No. 001-89435 Rev. *P
Now
Timer/counter/PWM
Serial communication block programmable as I2C/SPI/UART
79
PSoC® 4200 M-Series
Programmable Digital Family
Applications
Block Diagram
User interface and host processor for home appliances
Digital and analog sensor hub
LED control and communication for lighting systems
PSoC 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
I/O Subsystem
GPIO x8
Features
Collateral
GPIO x8
48 MHz
Flash
(64KB to 128KB)
SRAM
(8KB to 16KB)
Serial Wire Debug
CAN x2
CMP
x2
CSD
8-bit
IDAC2
x2
7-bit
IDAC2
x2
Programmable Digital
Blocks
UDB3 x4
TCPWM4 x8
Programmable Interconnect and Routing
Cortex®-M0
Advanced High-Performance Bus (AHB)
32-bit MCU subsystem
48-MHz ARM® Cortex®-M0 CPU with a DMA controller and RTC
Up to 128KB Flash and 16KB SRAM
CapSense® with SmartSense™ Auto-tuning
Cypress Capacitive Sigma-Delta™ (CSD) controller
CapSense supported on up to 55 pins
Programmable Analog Blocks
Two comparators (CMP)
Four opamps, programmed as PGAs, CMPs, filters, etc.
One 12-bit, 1-Msps SAR1 ADC
Four IDACs2 (2x 8-bit, 2x 7-bit)
Programmable Digital Blocks
Four universal digital blocks (UDBs3): custom digital peripherals
Eight programmable 16-bit TCPWM4 blocks
Four SCBs5: I2C master or slave, SPI master or slave, or UART
Two controller area network (CAN) controllers
Packages: 48-pin LQFP, 64-pin TQFP (0.8-mm pitch),
64-pin TQFP (0.5-mm pitch), 68-pin QFN
Datasheet:
SAR1
ADC
Opamp
x4
GPIO x8
GPIO x8
GPIO x8
GPIO x8
RTC
SCB5 x4
DMA
Segment LCD Drive
GPIO x7
Availability
Production:
PSoC 4 M-Series (CY8C4200)
1 Successive
3
2
4
approximation register
Current-output digital-to-analog converter
Document No. 001-89435 Rev. *P
Universal digital block
Timer/counter/PWM
Now
5 Serial
communication block programmable as I2C/SPI/UART
80
PSoC® 4200 L-Series
Programmable Digital Family
Block Diagram
Applications
User interface and host processor for home appliances
Digital and analog sensor hub
MCU and discrete analog replacement
LED control and communication for lighting systems
PSoC® 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
Opamp
x4
SAR2
CMP
x6
CSD
x2
8-bit
IDAC3
x2
7-bit
IDAC3
x2
I/O Subsystem
GPIO x8
GPIO x8
ADC
Features
Cortex®-M0
Flash
(64KB to 256KB)
SRAM
(8KB to 32KB)
Serial Wire Debug
CAN x2
Full-Speed
USB 2.0
RTC1
DMA
Collateral
Datasheet:
1 Real-time
Programmable Digital
Blocks
UDB x8
TCPWM4 x8
Programmable Interconnect and Routing
48 MHz
GPIO x8
Advanced High-Performance Bus (AHB)
32-bit MCU Subsystem
48-MHz ARM® Cortex®-M0 CPU with a DMA controller and RTC1
Up to 256KB flash and 32KB SRAM
Up to 98 GPIOs supporting analog and digital interfaces
CapSense® With SmartSense™ Auto-tuning
Two Cypress Capacitive Sigma-Delta™ (CSD) controllers
Programmable Analog Blocks
Two comparators (CMPs)
Four opamps, configurable as PGAs, CMPs, filters, etc.
One 12-bit, 1-Msps SAR2 ADC
Four IDACs3 (2x 8-bit, 2x 7-bit)
Programmable Digital Blocks
Eight universal digital blocks (UDBs): custom digital peripherals
Eight configurable 16-bit TCPWM4 blocks
Four SCBs5: I2C master or slave, SPI master or slave, or UART
Full-Speed USB 2.0 Controller and Transceiver
Two Controller Area Network (CAN) Controllers
Packages: 48-pin TQFP,64-pin TQFP,68-pin QFN,124-pin
VFBGA
GPIO x8
GPIO x8
GPIO x8
GPIO x8
GPIO x8
GPIO x8
GPIO x8
SCB5
x4
GPIO x8
Segment LCD Drive
GPIO x4
Availability
Production:
PSoC 4 L-Series
clock
approximation register
2 Successive
Document No. 001-89435 Rev. *P
3
4
Current-output digital-to-analog converter
Timer/counter/PWM
5
Now
Serial communication block programmable as I2C/SPI/UART
81
Low-Cost PSoC® Development Kits
PSoC Prototyping Kits
Bluetooth Low Energy (BLE)
Pioneer Development Kit
PSoC 5LP Development Kit
by SparkFun1
Kit Number
CY8CKIT-049 or CY8CKIT-059
CY8CKIT-042-BLE
DEV-13229
Key Features
Ultra-low-cost prototyping
Breadboard-compatible
Serial wire debug (SWD) or
bootload for program/debug
Arduino form factor-compatible
Access to all PSoC 4 BLE I/Os
Full SWD program and debug
Arduino form factor-compatible
Access to all PSoC 5LP I/Os
Full SWD program and debug
Price
$4–$10
$49
$50
Learn more or buy a kit today at www.cypress.com/kits
1 SparkFun
is an online retail store that specializes in supporting the hobbyist market with kits and tools to develop small electronics products
Document No. 001-89435 Rev. *P
82
PSoC Packages
Package
Pins
LQFP
48
PSoC 1
PDIP
QFN
8
20
28
16
24
32






40
48
56
68
8
16
20
28











68
72

PSoC 3
PSoC 4
SOIC








PSoC 5LP

CapSense
Package



SSOP
TQFP
Pins
8
16
20
24
28
32
48
44
PSoC 1








48
WLCSP
64

PSoC 4
100
30
32



PSoC 3







PSoC 5LP

CapSense
Package

WLCSP
µBGA
Pins
99
124
PSoC 1



PSoC 3
PSoC 4

PSoC 5LP
CapSense
Document No. 001-89435 Rev. *P
83
USB Controllers
Document No. 001-89435 Rev. *P
84
USB 3.1
USB Portfolio
Device
Hub
Bridge
CYUSB301x
FX3
CYUSB33xx
HX3
32-Bit Bus to USB 3.1 Gen 1
ARM9, 512KB RAM
USB 3.1 Gen 1, Shared Link™1
BC 1.22, Ghost Charge™3
FX3PD
NEW
USB 3.1 Gen 2 Type-C
Peripheral Controller with PD
Contact Sales
CYUSB333x
HX3C
Storage
Type-C
CYUSB306x
CX3
CYUSB303x
FX3S
CYPD1xxx
CCG1
CSI-24 to USB 3.1 Gen 1
4 CSI-24 Lanes, 1 Gbps/Lane
16-Bit Bus to USB 3.1 Gen 1
RAID5, Dual SDXC6/eMMC7
USB Type-C Port Controller
1 PD Port, 5 Profiles, 100 W
CYUSB361x
GX3
CYUSB302x
SD3
CYPD2xxx
CCG2
USB 3.1 Gen 1 to GigE
Energy Efficient Ethernet
USB 3.1 Gen 1 SD Reader
SDXC6/eMMC7, RAID5
USB Type-C Cable Controller
1 PD Port, Termination, ESD
Q117
4 Ports: 1 Type-C, 3 Type-A
USB PD, Billboard, BC1.22
HX3PD
USB 2.0
USB 3.1 Gen 2 Type-C
Hub with PD
Contact Sales
NEW
DX3
DSI8
USB 3.1 Gen 1 to
Contact Sales
TX
Q117
CYPD3xxx
CCG3
USB Type-C Port Controller
20-V, Crypto, Billboard
CY7C6801x/53
FX2LP
CY7C656x4
HX2VL
CYWB016xBB
Bay™
CYWB0x2xABS
Arroyo™, Astoria™
NEW
16-Bit Bus to USB 2.0
8051, 16KB RAM
4 Ports
4 Transaction Translators
HS USB OTG
Dual SDXC6/eMMC7
16-Bit Bus to USB 2.0
8051, Dual SD/eMMC7
USB Type-C Port Controller
2 PD Ports,128KB Flash, Mux
CY7C68003
TX2UL
CY7C656x1
HX2LP
CY7C6803x
NX2LP
ULPI9 PHY
13, 19.2, 24, 26 MHz
4 Ports, Industrial Grade
1 Transaction Translator
NAND Flash to USB 2.0
8051, 15KB RAM
CCG3PA
32-Bit Bus to USB 2.0
ARM9 512KB RAM
Parallel ATA to USB 2.0
8051
UART/SPI/I2C
M8C MCU, 20 GPIOs
SPI, 8KB Flash
to USB
2 Channels, CapSense®
CY7C64215
enCoRe III
CY7C65213
USB-to-UART (Gen 2)
M8C MCU, 50 GPIOs, ADC
I2C/SPI, 16KB Flash
CY7C65210/7
USB Billboard
CY7C67200
EZ-OTG™
M8C MCU, 36 GPIOs, ADC
I2C/SPI, 32KB Flash
ARM Cortex M0
1 or 2 UART/SPI/I2C channels
2 Ports, FS USB OTG
25 GPIOs
Document No. 001-89435 Rev. *P
USB charging without
host connection
4 Camera Serial Interface v2.0
5 Redundant
array of
independent disks
6 SD extended capacity
Q217
USB Type-C Port Controller
Contact Sales
Type-C products
apply to any
USB speed
CY7C67300
EZ-Host
CY7C643xx
enCoRe V
3 Enables
CCG5
SL811HS
4 Ports, FS USB OTG
32 GPIOs
USB 2.0 and
SuperSpeed traffic on the same port
2 Battery Charging specification v1.2
Q217
FS USB Host/Device
256Byte RAM
3 Mbps, 8 GPIOs
1 Simultaneous
Q117
USB Type-C Port Controller
Contact Sales
NEW
CY7C683xx
AT2LP
CY7C6521x
USB-Serial
CYPD4xxx
CCG4/CCG4M
NEW
CYUSB201x
FX2G2
CY7C638xx
enCoRe™ II
USB 1.1
Host
Concept
7 Embedded
Multimedia Card
Serial Interface
9 UTMI low-pin interface
8 Display
Development
Sampling
Production
QQYY
QQYY
Status
Availability
85
CCG1
USB Type-C and PD Port Controller
Block Diagram
Notebooks, tablets, monitors, docking stations, power adapters,
Type-C EMCAs1 and dongles
CCG1: USB Type-C Port Controller with PD
MCU Subsystem
Programmable Analog
Blocks
Features
IDAC
32-bit MCU Subsystem
48-MHz ARM® Cortex®-M0 CPU with 32KB flash and 4KB SRAM
Integrated Analog Blocks
12-bit, 1-Msps ADC for VBUS voltage and current monitoring
Dynamic overcurrent and overvoltage protection
Integrated Digital Blocks
Two configurable 16-bit TCPWM2 blocks
One SCB3: I2C master or slave, SPI master or slave, or UART
Up to eight GPIOs
Type-C Support
Integrated Type-C transceiver, supporting two Type-C ports
Controls routing of all protocols to an external MUX
PD Support
Supports provider4 and consumer5 roles and all power profiles
Low-Power Operation
1.71-5.5 V operation
Sleep: 1.3 mA, Deep Sleep: 1.3 µA
Packages
40-pin QFN (36 mm x 36 mm), 35-ball CSP (6.8 mm x 6.8 mm),
16-pin SOIC (60 mm x 60 mm)
Collateral
2
Electronically Marked Cable Assembly
Timer/Counter/Pulse-Width Modulation
Document No. 001-89435 Rev. *P
ADC
CORTEX®-M0
48 MHZ
Flash
(32KB)
SRAM
(4KB)
Advanced High-Performance Bus (AHB)
Type-C
Port 1
Comparators
Programmable Digital
Blocks
TCPWM
SCB
(I2C, SPI, UART)
Profiles and
Configurations
Baseband MAC
Type-C
Port 2
GPIO
Port
Serial Wire Debug
Baseband PHY
Availability
Datasheet:
CCG1 Datasheet
Reference Design Kit: CCG1 RDK
1
I/O Subsystem
Programmable Interconnect and Routing
Applications
3
Serial communication block
Type-C port that sources power over VBUS
Production:
5A
Now
Type-C port that sinks power from VBUS
4A
86
CCG2
USB Type-C and PD Port Controller
Applications
Block Diagram
USB Type-C Electronically Marked Cabled Assembly (EMCA) and
powered accessories
CCG2: USB Type-C Port Controller With PD
MCU Subsystem
Integrated Digital Blocks
I/O Subsystem
Features
CC7
Flash
(32KB)
SRAM
(4KB)
VCONN2
SCB1
(I2C, SPI, UART)
Profiles and
Configurations
Baseband MAC
Baseband PHY
Programmable I/O Matrix
48 MHz
VDDIO
GPIO5
Port
Integrated RP, RD, RA
Serial Wire Debug
Production:
CCG2 Datasheet
CCG2 RDK
1 Serial
3
2
communication block configurable as UART, SPI or I2C
Termination resistor read as a Down Facing Port (DFP)
4 Termination
Document No. 001-89435 Rev. *P
CORTEX-M0
VCONN1
SCB1
SPI, UART)
Availability
Collateral
Datasheet:
Reference Design Kit:
(I2C,
Advanced High-Performance Bus (AHB)
32-bit MCU Subsystem
48-MHz ARM® Cortex® -M0 CPU with 32KB flash and 4KB SRAM
Integrated Digital Blocks
Integrated timer/counter/pulse-width modulators (TCPWMs)
Two SCBs1 configurable to I2C, SPI or UART modes
Type-C Support
Integrated transceiver, supporting one Type-C port
Integrated DFP (RP2), UFP (RD3), EMCA (RA4) termination resistors
Power Delivery (PD) Support
Standard power profiles
Low-Power Operation
Two independent VCONN rails with integrated isolation
Independent supply voltage pin for GPIO5
2.7-5.5-V operation
Sleep: 2.0 mA; Deep Sleep: 2.5 µA
System-Level ESD on CC6 and VDD Pins
±8-kV contact, ±15-kV Air Gap IEC61000-4-2 level 4C
Packages
20-ball CSP (3.3 mm x 3.3 mm) with 0.4-mm ball pitch,
14-pin DFN (2.5 mm x 3.5 mm)with 0.6-mm pin pitch,
24-pin QFN (4 mm x 4 mm) with 0.55-mm pin pitch
TCPWM6
Now
Termination resistor read as a Up Facing Port (UFP)
resistor read as an EMCA
5 General-purpose
6
input/output
Configuration Channel
87
CCG3
USB Type-C and PD Port Controller
Block Diagram
Applications
Accessories and power adapters
CCG3: USB Type-C Cable Controller
MCU Subsystem
Collateral
Datasheet:
Cortex®-M0
48 MHz
Flash
(64KB)
Flash
(64KB)
4x TCPWM9
4x SCB4
(I2C, SPI, UART)
Crypto Engine
I/O Subsystem
Programmable
I/O Matrix
Type-C Support
Integrated transceiver, supporting one Type-C port
Alternate modes1, Crypto Engine2 for USB authentication3
Power Delivery (PD) Support for Standard Power Profiles
Integrated Digital Blocks for VBUS Power and MUX Interface
Four TCPWMs, 24x GPIOs
Four SCBs4 for configurable master/slave I2C, SPI or UART
USB Billboard Controller5 with Billboard Device Class6 support
Integrated Analog Blocks for OVP/OCP7
20-V OVP/OCP; 4:2 cross-bar switch
32-bit ARM® Cortex®-M0 CPU with MCU Subsystem
2x64KB Flash for fail-safe updates over CC, I2C or USB interfaces
Low-Power Operation
2x VBUS Gate Drivers8, for consumer and provider power paths
2x high-voltage (5-20 V, 25 V maximum) VBUS voltage inputs
Sleep: 2.0 mA; Deep Sleep: 2.5 µA with wake-on-I2C or wake-on-CC
System-Level ESD on CC/VCONN, VBUS, and SBU Pins
±8-kV contact, ±15-kV Air Gap IEC61000-4-2 Level 4C
Packages
42-ball (8.5 mm2) CSP and 40-pin (36 mm2) QFN
Integrated Digital Blocks
Advanced High-Performance Bus (AHB)
Features
CC
24x GPIO
Ports
USB PD Subsystem
Baseband MAC
Baseband PHY
20-V Regulator
2x VCONN FETs
Overcurrent
Protection
2x 20V VBUS FET
Gate Drivers8
System Resources
Overvoltage
Protection
Integrated Resistors
(RP, RD, RA)10
Full-Speed USB
Billboard Controller
4:2 Analog
Cross-Bar Switch
8-bit SAR ADC
SRAM
(8KB)
Availability
Samples:
CCG3 Datasheet
1
6
2
7
Mode of operation in which the data lines are repurposed to transmit non-USB data
The encryption hardware and software required to implement USB Authentication
3 A USB-IF specification that defines the authentication protocol for Type-C accessories
4 Serial communication block configurable as UART, SPI or I2C
5 A USB Device controller that informs the USB Host of the supported Alternate Modes
Document No. 001-89435 Rev. *P
Now
Production:
Q1 2017
A specification that defines the method for a USB Device to communicate the supported Alternate Modes
Overvoltage protection, overcurrent protection
8 Circuits to control the gates of external power Field-Effect Transistors (FETs) on V
BUS (5-20 V)
9 Timer/counter/pulse-width modulator block
10 Termination resistors: R read as a DFP, R as a UFP, R as an EMCA
P
D
P
88
CCG4/4M
USB Type-C and PD Port Controller
Applications
Block Diagram
Notebooks, tablets, monitors, docking stations, power adapters
CCG4/4M: Two-Port Type-C Controller with Power Delivery
Features
ARM
Cortex®-M0
48 MHz
Flash
(128KB)
SRAM
(8KB)
16
4x SCB1
32
32
Type-C
Baseband
Transceiver
Type-C
Baseband
Transceiver
CC
CC
2x VCONN
FETs
4
4x
TCPWM
4
24
GPIOs
2x VCONN
FETs
2
4x 8-bit
SAR ADC
Programmable I/O Matrix
Integrated USB Type-C Transceivers Support Two Type-C Ports
Integrated 2x 1-W VCONN FETs and 2x FET control signals, per
port programmable RP1 and removable RP, and RD2 terminations
Supports dead battery mode operation
Integrated SuperSpeed USB/DisplayPort (DP) Mux (CCG4M)
Increased Flash Enables Fail-Safe Bootup
Integrates 128KB flash to store dual FW images for Fail-Safe Boot
Integrated Digital Blocks for Inter-Chip Communications
Four SCBs3 master or slave configurable to I2C, SPI or UART
SCBs interconnect CCG4 with embedded controller,
two alternate muxes and Thunderbolt4 controller (optional)
Integrated Blocks for OVP5 and OCP6
Four 8-bit SAR ADCs configurable for OVP and OCP
Low-Power Operation
2.7-V to 5.5-V operation and independent supply voltage for general
purpose input/output (GPIO) Sleep: 2.0 mA; Deep Sleep: 2.5 µA
with wake-on-I2C or wake-on-configuration channel (CC)
System-Level ESD on CC Pins
±8-kV contact, ±15-kV Air Gap IEC61000-4-2 level 4C
32-bit ARM® Cortex® -M0 CPU with MCU Subsystem
128KB Flash, upgradable over CC lines or I2C interface
Packages
40-pin QFN, 96-ball BGA (CCG4M)
To
EC7
24
SS_
USB
+
DP
USB/DP
Mux
(CCG4M)
2
8
2
12
Type-C
Port 2
Type-C
Port 1
SS_USB
+ DP
2
AUX
SBU
Availability
Samples: Now
Production: Q1 2017
Collateral
Datasheet: CCG4 Datasheet
1 Termination
3
2
4 An
resistor read as a DFP
Termination resistor read as a UFP
Document No. 001-89435 Rev. *P
Serial communication block configurable as UART, SPI or I2C
interface jointly defined by intel and Apple that connects peripherals to a computer
5
6
Overvoltage protection
Overcurrent protection
7
Embedded controller in a PC
89
FX3
USB 3.1 Gen 1 Peripheral Controller
Block Diagram
Industrial
Medical and machine vision cameras
3-D and 1080p full HD and 4K Ultra HD (UHD) cameras
Document and fingerprint scanners
Videoconferencing and data acquisition systems
Video capture cards and HDMI converters
Protocol and logic analyzers
USB test tools and software-designed radios (SDRs)
5
FX3 Controller
JTAG
512KB
RAM
Image
Sensor,
FPGA or
ASIC
Features
USB 3.1 Gen 1-compliant peripheral controller
USB-IF certified (TID:340800007)
Fully accessible 32-bit, 200-MHz ARM926EJ core
512KB of embedded SRAM for code space and buffers
Up to 32-bit, 100-MHz, flexible GPIF II interface
Other peripheral interfaces such as I2C, I2S, UART, SPI and
12 GPIOs
Unused I/O pins can be used as GPIOs
Up to 32 USB endpoints
Flexible clock options:
19.2-MHz crystal
19.2-MHz, 26-MHz, 38.4-MHz and 52-MHz clock input
121-ball BGA (10 x 10 mm), 131-ball WLCSP (4.7 x 5.1 mm)
32
32
32
USB 3.1 Gen 1
ARM9
GPIF-II
Applications
32
32
32
UART
4
I2C
I2S
2
4
SPI
4
6
USB 3.1
Gen1
Host
GPIO
12
Availability
Production:
Now
Collateral
Datasheet:
Development Kit:
Software Development Kit:
Document No. 001-89435 Rev. *P
CYUSB301X/CYUSB201X
FX3 SuperSpeed Explorer Kit
EZ-USB FX3 SDK
90
FX3S
USB 3.1 Gen 1 RAID1-on-Chip
Applications
Block Diagram
Servers
Routers
Mobile storage
USB flash drives
POS terminals
Automatic teller machines (ATM)
SDIO expanders and data logging devices
5
16
GPIF II
ASIC,
FPGA,
SoC
USB 3.1 Gen 1-compliant Peripheral Controller
USB-IF certified (TID:340800007)
Fully accessible 32-bit, 200-MHz ARM926EJ core
512KB of embedded SRAM for code space and buffers
Up to 16-bit, 100-MHz, flexible GPIF II interface
Peripheral interfaces such as I2C, UART, SPI and GPIOs
Supports two SDXC2, eMMC3 4.4, or SDIO 3.0 interfaces
Support RAID0 or RAID1 configurations
Flexible clock options:
19.2-MHz crystal
19.2-MHz, 26-MHz, 38.4-MHz and 52-MHz clock input
121-ball BGA (10 x 10 mm)
131-ball WLCSP (4.7 x 5.1 mm)
32
32
32
32
SDXC2/eMMC3S
DIO
4
SD Card,
eMMC3 NAND,
SDIO Device
6
USB 3.1
Gen 1
Host
SDXC2/eMMC3S
DIO
4
SD Card,
eMMC3 NAND,
SDIO Device
Availability
Collateral
1 Redundant
512KB
RAM
(RAID1
Firmware)
ARM9
Features
Datasheet:
Kit:
Software:
App Notes:
JTAG
USB 3.1 Gen 1
FX3S
RAID1-on-Chip
EZ-USB® FX3S™
FX3S RAID1-on-Chip Boot Disk Kit
FX3 Software Development Kit (SDK)
FX3S Hardware Design Guidelines (AN70707)
USB RAID 1 Disk Design Using FX3S (AN89661)
array of independent disks
Document No. 001-89435 Rev. *P
2 SD
extended capacity
3 Embedded
Production:
Now
Multimedia Card
91
CX3
MIPI1 CSI-2 to USB 3.1 Gen 1 Bridge
Block Diagram
Features
USB 3.1 Gen 1-compliant video-class controller
Four-lane MIPI1 Camera Serial Interface v2.0 (CSI-2) input
Camera Control Interface (CCI) for image sensor configuration
Supports industry-standard video data formats:
RAW8/10/12/142, YUV422/4443, RGB888/666/5654
Supports uncompressed streaming video:
4K UHD at 15 fps, 1080p at 30 fps, 720p at 60 fps
On-chip ARM9 with 512KB RAM for data processing
Supports I2C, I2S, SPI, UART and 12 GPIOs
121-BGA (10 x 10 x 1.7 mm)
Collateral
Datasheet:
Reference Design Kit:
Software Development Kit:
5
CX3 Bridge
JTAG
512KB
RAM
ARM9
Image
Sensor or
Image
Signal
Processor
4
32
32
32
32
UART
4
I2C
SPI
2
4
USB 3.1 Gen 1
Industrial
Medical and machine vision cameras
1080p full HD and 4K Ultra HD (UHD) cameras
Document scanners
Fingerprint scanners
Game consoles
Videoconferencing systems
Notebook PCs
Tablets and image acquisition systems
MIPI1 CSI-2
Applications
6
USB 3.1
Gen 1
Host
GPIO
12
Availability
Production:
Now
CYUSB306X
CX3™ Reference Design
EZ-USB SDK
1
Mobile Industry Processor Interface
format for raw video data
3 Video format for luminance and chrominance components
4 Video format for red, green and blue pixel components
2 Video
Document No. 001-89435 Rev. *P
92
HX3
USB 3.1 Gen 1 Hub
Applications
Block Diagram
Docking stations for notebook PCs and tablets,
PC motherboards, servers, digital TV, monitors, retail hub
boxes, printers, scanners, set-top boxes, home
gateways, routers and game consoles
Upstream Port
EEPROM
2
2
4
HX3 Hub
SS3 PHY
USB 2.0 PHY
8
MCU
USB 3.1 Gen 1 PHY
I2C
32
Features
16
32
USB 3.1 Gen 1-compliant four-port Hub Controller
USB-IF certified (Test ID: 330000047)
WHQL certified for Windows 7, Window 8, Windows 8.1
Shared Link™ supports simultaneous USB 2.0 and
USB SuperSpeed (SS) devices on the same port
Ghost Charge™ enables USB charging while the hub is
disconnected from a USB Host
Charging Standard support:
USB-IF Battery Charging v1.2
Apple Charging Standard
Charging an OTG Host in an ACA-Dock
Programming of external EEPROM via USB
Configurable USB SS and USB 2.0 PHY that drives 11ʺ trace
68-QFN (8 x 8 x 1.0 mm), 88-QFN (10 x 10 x 1.0 mm),
100-BGA (6 x 6 x 1.0 mm)
SuperSpeed Hub
Controller
USB 2.0 Hub Controller
16
32
Buffers
4x TT1
Repeater
16
32
Routing Logic
Routing Logic
32
16
USB 3.1 Gen 1 PHY
USB 3.1 Gen 1 PHY
SS3
PHY
USB 2.0 PHY
USB 3.1 Gen 1 PHY
SS3
PHY
SS3 PHY
USB 2.0 PHY
USB 3.1 Gen 1 PHY
SS3 PHY
USB 2.0 PHY
USB 2.0 PHY
2
4
4
Downstream Port 1
2
4
Downstream Port 2
2
Downstream Port 3
4
2
Downstream Port 4
Collateral
Datasheet:
Application Note:
Kits:
Configuration Utility:
1
HX3 Datasheet
HX3 Hardware Design Guide
CY4609, CY4603, CY4613
Blaster Plus2
Transaction translator
Document No. 001-89435 Rev. *P
2
Availability
Production:
Now
A Cypress GUI-based PC application for setting HX3 configuration parameters
3
SuperSpeed
93
GX3
USB 3.1 Gen 1 to GigE1 Bridge
Block Diagram
USB dongles, docking stations and port replicators
Network printers and security cameras
Ultrabooks and home gateways
Game consoles and portable media players
DVRs, IP set-top boxes and IP TVs
Other embedded systems
GX3 Bridge
Data SRAM
Program
ROM
DMA
Engine
RISC SOC
GigE MAC
Controller
USB
Controller
One-chip USB 3.1 Gen 1 to 10/100/1000M GigE bridge
Integrates USB 3.1 Gen 1 PHY and GigE PHY
Integrates USB 3.1 Gen 1 Controller and GigE MAC2
Needs only a 25-MHz crystal to drive both USB & GigE1 PHY
IEEE 802.3az3 support for low-power idle state
Supports dynamic cable length and power adjustment
Offers multiple power management wake-on-LAN4 features
Supports optional EEPROM to store USB descriptors
Integrates on-chip POR5 circuitry
68-QFN (8 x 8 x 0.85 mm)
8
GigE1 PHY
Features
I2C
GPIO
2
Clock
USB 3.1 Gen 1 PHY
Applications
6
USB 3.1
Gen 1
Host
Reset
8
Collateral
Datasheet:
GX3 Datasheet
Reference Design Kit: GX3 RDK
Software Drivers:
GX3 Drivers
Availability
Production:
Now
1 Gigabit
Ethernet
Media access controller that provides the address to an Ethernet node
3 A new-energy efficient Ethernet standard
4 An Ethernet standard that allows a computer to be turned on by a network message
5 Power-on-reset
2
Document No. 001-89435 Rev. *P
94
HX3C
USB 3.0 Type-C PD Hub1
Block Diagram
Applications
USB Type-C charging hubs1, adapters and accessories
Docking stations for notebook PCs and tablets
Televisions and monitors
PC motherboards and servers
Set-top boxes, home gateways and routers
EEPROM
USB Type-C (US Port)
2
4
2
HX3C Hub
SS6 PHY
MCU
Features
2
USB 2.0 PHY CC5
16
32
2
Directs data traffic between a USB Host and multiple USB Devices
A USB Device controller that is used to implement the USB Billboard Device Class
Informs the USB Host of the supported Alternate Modes as well as any failures
Document No. 001-89435 Rev. *P
USB 2.0 Hub1 Controller
SS6 Hub1 Controller
2
16
32
Buffers
4x TT7
Repeater
16
32
Routing Logic
USB
Billboard
Controller2
Routing Logic
16
32
USB 3.1 Gen 1 PHY
SS6 PHY
2
USB Type-A (DS Port)
2
USB 3.1 Gen 1 PHY
USB 2.0 PHY SS6 PHY
4
Collateral
1
PD
Controller
32
USB 3.1 Gen 1-compliant Hub1 controller
Upstream (US): Type-C
Downstream (DS): 1 Type-C and 2 Type-A ports
Integrated Type-C transceivers, supporting two ports
Integrated DFP (RP) and UFP (RD) termination resistors
Integrated USB Billboard Controller2
Charging Support: USB PD, BC v1.23, Apple Charging
Standard4
PD policy engine configures power profiles dynamically
Ghost Charge™: Charging DS without US connection
Firmware upgradable over USB
System-Level ESD on CC5 Pins: 8 kV contact, 15 kV airconfigurable USB SS6 and USB 2.0 PHY (drives 11ʺ trace)
121-ball BGA (10 mm x 100 mm, 0.8 mm ball-pitch)
Datasheet:
CYUSB3333/CYUSB3343
Product Overview: EZ-USB® HX3C: USB 3.0 Type-C Hub
with Power Delivery
2
USB 3.1 Gen 1 PHY
4
2
USB Type-A (DS Port)
2
USB 3.1 Gen 1 PHY
USB 2.0 PHY SS6 PHY
4
USB 2.0 PHY CC5
2
PD
Controller
2
USB Type-C (DS Port)
Availability
Samples:
Production:
3A
Now
Q1 2017
specification published by the USB Implementers Forum
(USB-IF) for charging portable USB Devices
4 An Apple-specified battery charging standard for the iPhone,
iPod and iPad
5
Configuration Channel
USB SuperSpeed
7 Transaction Translator
6
95
Asynchronous SRAMs
Document No. 001-89435 Rev. *P
96
Asynchronous SRAM Portfolio
High Density | Wide Voltage Range | Automotive A1, E2 | On-Chip ECC3
Low-Power SRAM (MoBL®4)
Fast SRAM
32Mb-128Mb
Non-ECC
ECC
CY7C107x
32Mb; 3.3 V
12 ns; x8, x16
Ind
64Kb-1Mb
2Mb-16Mb
CY7C106x
16Mb; 1.8, 3.3 V
10 ns; x8, x16, x32
Ind
1
ECC
CY6218x
64Mb; 1.8, 3.0 V
55 ns; x16
Ind
NDA Required
Contact Sales
CY7C106x
16Mb; 1.8-5.0 V
10 ns; x8, x16, x32
Ind, Auto E
CY6216x
16Mb;1.8, 3.0, 5.0 V
45 ns; x8, x16
Ind, Auto A
CY6216x
16Mb; 1.8-5.0 V
45 ns; x8, x16, x32
Ind, Auto E
CY7C1012
12Mb; 3.3 V
10 ns; x24
Ind
CY7C105x
8Mb; 3.3, 5.0 V
10 ns; x8, x16
Ind, Auto E
CY6215x
8Mb; 1.8, 3.0, 2.5-5V
45 ns; x8, x16
Ind, Auto A, E
CY6216x
8Mb; 3.3, 5.0 V
45 ns; x8, x16, x32
Ind, Auto E
CY7C104x
4Mb; 3.3, 5.0 V
10 ns; x4, x8, x16
Ind, Auto A, E
CY7C1034
6Mb; 3.3 V
10 ns; x24
Ind
CY7C104x
4Mb; 1.8-5.0 V
10 ns; x8, x16
Ind, Auto E
CY6214x
4Mb; 1.8, 3.0, 2.5-5V
45 ns; x8, x16
Ind, Auto A, E
CY6214x
4Mb; 1.8-5.0 V
45 ns; x8, x16
Ind, Auto E
CY7C1010/11
2Mb; 3.3 V
10 ns; x8, x16
Ind, Auto A, E
CY7C1024
3Mb; 3.3 V
10 ns; x24
Ind
CY6213x
2Mb; 1.8, 2.5-5.0 V
45 ns; x8, x16
Ind, Auto A, E
CY7C1020
512Kb; 2.6, 3.3, 5.0 V
10 ns; x16
Ind, Auto E
CY7C1019/21/100x
1Mb; 2.6, 3.3, 5.0 V
10 ns; x4, x8, x16
Ind, Auto A, E
CY6212x
1Mb; 2.5-5.0 V
45 ns; x8, x16
Ind, Auto A, E
CY7C19x/1399
256Kb; 3.3, 5.0 V
10 ns; x4, x8
Ind, Auto A
CY62256
256Kb; 1.8, 3.0, 5V
55 ns, 70 ns; x8
Ind, Auto A, E
5
A Fast SRAM with a deep-sleep mode in addition to a
conventional standby mode. For example, the
12-ns 16Mb offering has a deep-sleep current of
≤1.37 µA/Mb and a standby current of ≤1.87 mA/Mb
Document No. 001-89435 Rev. *P
ECC
Serial SRAM (with ECC)
Quad-SPI
HyperBus™6
NDA Required
Contact Sales
NDA Required
Contact Sales
CY6217x
32Mb; 1.8-5.0 V
55 ns; x16
Ind
CY7C105x
8Mb; 3.3 V
10 ns; x8, x16
Ind
AEC-Q100 -40°C to +85°C
AEC-Q100 -40°C to +125°C
3 Error correcting code
4 More Battery Life
2
Non-ECC
PowerSnooze™5
6
CY7S106x
16Mb; 1.8-5.0 V
10 ns; x8, x16, x32
Ind, Auto E
CY7S104x
4Mb; 1.8-5.0 V
10 ns; x8, x16
Ind, Auto E
A high-bandwidth,12-signal interface that
transfers information over 8 I/O signals at
Status
Double Data Rate (DDR), delivering up to
Availability
400 MBps
Concept
Development
Sampling
Production
QQYY
QQYY
Roadmap
97
Fast SRAM Family with ECC1
Applications
Family Table
Switches and routers
IP phones
Test equipment
Automotive
Computation servers
Military and aerospace systems
Features
Access time: 10 ns
Bus-width configurations: x8, x16 and x32
Wide operating voltage range: 1.65-5.5 V
Industrial and automotive temperature grades
Industry-standard, RoHS-compliant packages
ECC to detect/correct single-bit errors
Bit-interleaving to avoid multi-bit errors
Error indication (ERR) pin to indicate single-bit errors
Density
MPN
Access Time
4Mb
8Mb
16Mb
CY7C104x
CY7C105X
CY7C106x
10 ns
10 ns
10 ns
Operating Current
(Maximum at 85ºC)
45 mA
110 mA
110 mA
Block Diagram
Fast SRAM with ECC
SRAM Array
ECC
Encoder
Input
Buffer
18-23
Address
Address
Decoder
Collateral
8, 16, 32
Data
ERR
I/O Mux
SRAM Array
Sense
Amps
ECC
Decoder
Datasheet: Async SRAM with ECC datasheets
Control Logic
CE
OE
WE
BHE2
BLE3
Availability
1
Error-correcting code
Byte high enable
3 Byte low enable
2
Document No. 001-89435 Rev. *P
Sampling:
Production:
Now
Now
Product Overview
98
MoBL®1 SRAM Family With ECC2
Applications
Family Table
Programmable logic controllers
Handheld devices
Multifunction printers
Automotive
Implantable medical devices
Computation servers
Features
Access time: 45 ns
Standby current: 8.7 µA for 4Mb
Bus-width configurations: x8, x16 and x32
Wide operating voltage range: 1.65-5.5 V
Industrial and automotive temperature grades
Industry-standard, RoHS-compliant packages
ECC to detect/correct single-bit errors
Bit-interleaving to avoid multi-bit errors
Error indication (ERR) pin to indicate single-bit errors
Density
MPN
4Mb
8Mb
16Mb
CY6214x
CY6215x
CY6216x
Standby Current
(Maximum at 85ºC)
8.7 µA
16.0 µA
16.0 µA
Standby Current
(Typical at 25ºC)
3.5 µA
5.5 µA
5.5 µA
Block Diagram
MoBL® SRAM with ECC
SRAM Array
ECC
Encoder
Input
Buffer
18-23
Address
Address
Decoder
I/O Mux
SRAM Array
Collateral
8, 16, 32
Data
ERR
Datasheet: Async SRAM with ECC datasheets
Sense
Amps
ECC
Decoder
Control Logic
CE
OE
WE
BHE3
BLE4
Availability
1
More Battery Life
Error-correcting code
3 Byte high enable
4 Byte low enable
2
Document No. 001-89435 Rev. *P
Sampling:
Production:
Now
Now
Product Overview
99
Fast SRAM Family with PowerSnooze™1
Applications
Family Table
Programmable logic controllers
Handheld devices
Multifunction printers
Automotive
Computation servers
Features
Access time: 10 ns
PowerSnooze: Additional power-saving (deep-sleep) mode
Deep-sleep current: 15 µA for 4Mb (see Family Table)
Bus-width configurations: x8, x16 and x32
Wide operating voltage range: 1.65-5.5 V
Industrial and automotive temperature grades
Industry-standard, RoHS-compliant packages
Error-Correcting Code (ECC) to detect/correct single-bit errors
Bit-interleaving to avoid multi-bit errors
Density
MPN
Access Time
4Mb
16Mb
CY7S104x
CY7S106x
10 ns
10 ns
Deep Sleep Current
(Maximum at 85ºC)
15 µA
22 µA
Block Diagram
Fast SRAM with PowerSnooze
ECC
Encoder
20
Address
Address
Decoder
Collateral
Datasheet: Async SRAM with ECC datasheets
DS2
8, 16, 32
Data
ERR
I/O Mux
SRAM Array
Power
Management
Block
(Enables
PowerSnooze)
Input
Buffer
Sense
Amps
ECC
Decoder
Control Logic
CE
OE
WE BHE3 BLE4
Availability
1
A Fast SRAM with a deep-sleep mode in addition to a conventional standby mode.
For example, the 12-ns 16Mb offering has a deep-sleep current of ≤1.37 µA/Mb and a
standby current of ≤1.87 mA/Mb
2 Deep-sleep
3 Byte high enable
4 Byte low enable
Document No. 001-89435 Rev. *P
Sampling:
Production:
Now
Now
Product Overview 100
Synchronous SRAMs
Document No. 001-89435 Rev. *P
101
Synchronous SRAM Portfolio
High Random Transaction Rate (RTR)1 | Low Latency | High Bandwidth
Standard Sync
and NoBL®
Standard Sync
and NoBL with
ECC2
QDR® -II/
DDR-II
QDR-II+/
DDR-II+
QDR-II+X/
DDR-II+X
QDR-IV
RTR: 250 MT/s (max.)
BW: 18 Gbps (max.)
Latency: 1 Cycle
Pipeline and
Flow-Through Modes
RTR: 250 MT/s (max.)
BW: 18 Gbps (max.)
Latency: 1 Cycle
Pipeline and
Flow-Through Modes
RTR: 666 MT/s (max.)
BW: 47.9 Gbps (max.)
Latency: 1.5 Cycles
CIO4 and SIO5
RTR: 666 MT/s (max.)
BW: 79.2 Gbps (max.)
Latency: 2 or 2.5 Cycles
CIO and SIO, ODT6
RTR: 900 MT/s (max.)
BW: 91.1 Gbps (max.)
Latency: 2.5 Cycles
SIO, ODT
RTR: 2.1 GT/s (max.)
BW: 153.5 Gbps (max.)
Latency: 5 or 8 Cycles
Dual-Port Bidirectional
ODT
CY7C161/2xKV18
144Mb; 250-333 MHz
1.8 V; x9, x18, x36
Burst 2, 4
CY7Cx4/5/6/7xKV18
144Mb; 300-550 MHz
1.8 V; x18, x36
Burst 2, 4
CY7C151/2xKV18
72Mb; 250-333 MHz
1.8 V; x9, x18, x36
Burst 2, 4
CY7Cx54/5/6/7KV18
72Mb; 250-550 MHz
1.8 V; x18, x36
RH7; Burst 2, 4
CY7C156/7xXV18
72Mb; 366-633 MHz
1.8 V; x18, x36
Burst 2, 4
CY7C126/7x
36Mb; 366-633 MHz
1.8 V; x18, x36
Burst 2, 4
Density
CY7C147/8xB
72Mb; 133-250 MHz
2.5, 3.3 V; x18, x36
CY7C144/6xK
36Mb; 133-250 MHz
2.5, 3.3 V; x36, x72
CY7C144/6xKVE
36Mb; 133-250 MHz
2.5, 3.3 V; x18, x36
CY7C141/2xKV18
36Mb; 250-333 MHz
1.8 V; x8, x9, x18, x36
Burst 2, 4
CY7Cx24/5/6/7xKV18
36Mb; 400-550 MHz
1.8 V; x18, x36
Burst 2, 4
CY7C137/8xD/K
18Mb; 100-250 MHz
3.3 V; x18, x32, x36
CY7C137/8xKVE
18Mb; 100-250 MHz
2.5, 3.3 V; x18, x36
CY7C131/2/9xKV18
18Mb; 250-333 MHz
1.8 V; x8, x18, x36
Burst 2, 4
CY7Cx14/5/6/7xKV18
18Mb; 400-550 MHz
1.8 V; x18, x36
Burst 2, 4
CY7C135/6xC
9Mb; 100-250 MHz
3.3 V; x18, x32, x36
Auto E8
CY7C41xKV13
144Mb; 667-1066 MHz
1.3 V; x18, x36
Burst 2
CY7C40xKV13
72Mb; 667-1066 MHz
1.3 V; x18, x36
Burst 2
CY7C1911xKV18
18Mb; 250-333 MHz
1.8 V; x9
Burst 2, 4
CY7C134/2xG
2-4Mb; 100-250 MHz
3.3 V; x18, x32, x36
Random Transaction Rate
1 Rate
of truly random accesses to memory, expressed in
transactions per second (MT/s, GT/s)
2 Error-correcting code
Document No. 001-89435 Rev. *P
3 Acceleration
6
4
7
data engine
Common I/O
5 Separate I/O
On-die termination
Radiation hardened, military grade
8 AEC-Q100: -40°C to +125°C
Concept
Development
Sampling
Production
QQYY
QQYY
Status
Availability
2102
QDR®-IV
Applications
Switches and routers
High-performance computing
Military and aerospace systems
Test and measurement
Family Table
Option
Density
MPN
Maximum Frequency
RTR
QDR-IV HP
72Mb
144Mb
CY7C40x1KV13
CY7C41x1KV13
667 MHz
1,334 MT/s
QDR-IV XP
72Mb
144Mb
CY7C40x2KV13
CY7C41x2KV13
1,066 MHz
2,132 MT/s
Features
Datasheets: CY7C4122KV13 / CY7C4142KV13
CY7C4121KV13 / CY7C4141KV13
CY7C4022KV13 / CY7C4042KV13
CY7C4021KV13, CY7C4041KV13
1 Double
Data Rate: Two data transfers per clock cycle
code: Data encoded with extra parity bits to detect and correct bit errors,
including unavoidable errors due to background radiation
3 Failures in Time per Megabit
4 An iterative algorithm for assessing and eliminating the skew (differences in arrival times)
between multiple data signals
5 Pseudo open drain: Signaling interface that uses strong pull-down and weak pull-up
drive strength
6 Flip-Chip Ball Grid Array
2 Error-correcting
Document No. 001-89435 Rev. *P
Address/Control
Clock
QDR-IV
Bus
Inversion
x21,
x22
Address Address Parity
Port
Error
Parity
Address Interface
x2
x2
ECC
Data Clocks x2
x2
Data Valid
x18, x36
Data Port A
x2
Data Port B
(HSTL / SSTL or POD)
Collateral
Block Diagram
Data Port A
(HSTL / SSTL or POD)
Available in two options: QDR-IV HP (RTR 1,334 MT/s) and
QDR®-IV XP (RTR 2,132 MT/s)
Two independent, bidirectional DDR1 data ports
ECC2 to reduce soft error rate to less than 0.01 FIT/Mb3
Bus inversion to reduce simultaneous switching I/O noise
On-die termination (ODT) to reduce board complexity
De-skew training4 to improve signal-capture timing
I/O levels: 1.2-1.25 V (HSTL/SSTL), 1.1-1.2 V (POD5)
Package: 361-pin FCBGA6
Bus widths: x18, x360.13
SRAM Array
x2
x2
Impedance Matching
Control
Logic
Control
x4
Data Valid
x18, x36
Data Port B
x2
Bus Inversion
ODT
Data Clocks
Bus Inversion
Test
Engine
JTAG Interface
Availability
Sampling:
Production:
Now
Now
Product Overview 103
Standard Synchronous SRAM
With On-Chip ECC1
Applications
Switches and routers
Radar and signal processing
Test equipment
Automotive
Military and aerospace systems
Family Table
RTR
FIT/Mb5
Option
Density
MPN
Standard Sync with
On-Chip ECC Pipeline
18Mb
36Mb
CY7C1370/2K
CY7C1440/2K
250 MT/s
<0.01
Standard Sync with
On-Chip ECC
Flow-Through
18Mb
36Mb
CY7C1371/3K
CY7C1441/3K
133 MT/s
<0.01
Features
Block Diagram
Datasheet: 36M Sync SRAM, 18M Sync SRAM
Output
Enable
x18, x36
Data Port
Control
Logic
Output
Register
(Pipeline)
SRAM
Array
Address
Interface
Chip Enable
ECC
Encoder
x19-x21
Address
Bus
Test
Engine
Byte Write
Clock
Collateral
Input
Register
x2
Control
Data Port and Control
(2.5 / 3.3V)
Available in two modes2: Pipeline and Flow-Through
SCD and DCD deselect options3
Bus-width configurations: x18, x36
Two voltage options: 2.5 V and 3.3 V
Industrial and commercial temperature grades
ECC to detect and correct single-bit errors
Packages: 165-ball BGA and 100-pin TQFP
Industry-standard, RoHS4-compliant packages
JTAG
Interface
ECC
Decoder
1 Error-correcting
code: Data encoded with extra parity bits to detect and correct bit errors,
including unavoidable errors due to background radiation
2 Modes of synchronous SRAM operation that optimize either read latency (Flow-Through)
or operating frequency (Pipeline)
3 Modes of operation in Pipeline mode where the output driver is tri-stated after either a
single cycle (SCD) or dual cycle (DCD) of issuing the deselect command
4 Restriction of Hazardous Substances: A European Union directive intended to eliminate
the use of environmentally hazardous material in electronic components
5 The projected failure rate of a device; one FIT/Mb equals one failure per billion device
hours per megabit of data
Document No. 001-89435 Rev. *P
Availability
Sampling:
Production:
Now
Now
Product Overview 104
NoBL® SRAM With On-Chip ECC1
Applications
Switches and routers
Radar and signal processing
Test equipment
Automotive
Military and aerospace systems
Family Table
RTR
FIT/Mb4
Option
Density
MPN
NoBL with On-Chip ECC
Pipeline
18Mb
36Mb
CY7C1380/2K
CY7C1460/2K
250 MT/s
<0.01
NoBL with On-Chip ECC
Flow-Through
18Mb
36Mb
CY7C1381/3K
CY7C1461/3K
133 MT/s
<0.01
Features
Block Diagram
Datasheet: 36M NoBL SRAM, 18M NoBL SRAM
1 Error-correcting
code: Data encoded with extra parity bits to detect and correct bit errors,
including unavoidable errors due to background radiation
2 Modes of synchronous SRAM operation that optimize either read latency (Flow-Through)
or operating frequency (Pipeline)
3 Restriction of Hazardous Substances: A European Union directive intended to eliminate
the use of environmentally hazardous material in electronic components
4 The projected failure rate of a device; one FIT/Mb equals one failure per billion device
hours per megabit of data
Document No. 001-89435 Rev. *P
Output
Enable
x18, x36
Data Port
NoBL
Logic
SRAM
Array
Address
Interface
Chip Enable
ECC
Encoder
Test
Engine
Byte Write
Clock
Collateral
Input
Register
x2
Control
Data Port and Control
(2.5 V / 3.3 V)
Available in two modes2: Pipeline and Flow-Through
No Bus Latency® (NoBL®) architecture for balanced read and write
Bus-width configurations: x18, x36
Two voltage options: 2.5 V and 3.3 V
Industrial and commercial temperature grades
ECC to detect and correct single-bit errors
Packages: 165-ball BGA and 100-pin TQFP
Industry-standard, RoHS3-compliant packages
Output
Register
(Pipeline)
x19-x21
Address
Bus
JTAG
Interface
ECC
Decoder
Availability
Sampling:
Production:
Now
Now
Product Overview 105
Nonvolatile RAM
Document No. 001-89435 Rev. *P
106
nvSRAM Portfolio
High Density | High Speed
LPC6 nvSRAM
CY14B116R/S
16Mb; 3.0 V
25, 45 ns; x32; Ind1
RTC2
CY14B116K/L
16Mb; 3.0 V
25, 45 ns; x8; Ind
RTC
CY14V116F/G
16Mb; 3.0, 1.8 V I/O
30 ns; ONFI3 1.0
x8, x16; Ind
Higher Densities
nvSRAM
NDA Required
Contact Sales
CY14B104NA
4Mb; 3.0 V
25, 45 ns; x16
Auto E4; RTC
CY14B108K/L
8Mb; 3.0 V
25, 45 ns; x8; Ind
RTC
CY14B108M/N
8Mb; 3.0 V
25, 45 ns; x16; Ind
RTC
CY14B116M/N
16Mb; 3.0 V
25, 45 ns; x16; Ind
RTC
CY14B104K/LA
4Mb; 3.0 V
25, 45 ns; x8; Ind
RTC
CY14V104LA
4Mb; 3.0, 1.8 V I/O
25, 45 ns; x8; Ind
CY14B104M/NA
4Mb; 3.0 V
25, 45 ns; x16; Ind
RTC
CY14V104NA
4Mb; 3.0, 1.8 V I/O
25, 45 ns; x16; Ind
CY14V101PS
1Mb; 3.0, 1.8 V I/O
108-MHz QSPI7; Ind
Ext. Ind8; RTC
CY14V101QS
1Mb; 3.0, 1.8 V I/O
108-MHz QSPI; Ind
Ext. Ind
CY14B101I
1Mb; 3.0 V
3.4-MHz I2C; Ind
RTC
CY14B101KA/LA
1Mb; 3.0 V
25, 45 ns; x8; Ind
RTC
CY14V101LA
1Mb; 3.0, 1.8 V I/O
25, 45 ns; x8; Ind
CY14B101MA/NA
1Mb; 3.0 V
25, 45 ns; x16; Ind
RTC
CY14V101NA
1Mb; 3.0, 1.8 V I/O
25, 45 ns; x16; Ind
CY14B101P
1Mb; 3.0 V
40-MHz SPI; Ind
RTC
CY14B512P
512Kb; 3.0 V
40-MHz SPI; Ind
RTC
CY14B512I
512Kb; 3.0 V
3.4-MHz I2C; Ind
RTC
CY14B256KA/LA
256Kb; 3.0 V
25, 45 ns; x8; Ind
RTC
CY14V/U256LA
256Kb; 3.0, 1.8V I/O
35 ns; x8; Ind
CY14E256LA
256Kb; 5.0 V
25, 45 ns; x8; Ind
STK14C88-5
256Kb; 5.0 V
35, 45 ns; x8; Mil5
CY14B256P
256Kb; 3.0 V
40-MHz SPI; Ind
RTC
CY14B256I
256Kb; 3.0 V
3.4-MHz I2C; Ind
RTC
STK11C68-5
64Kb; 5.0 V
35, 55 ns; x8; Mil5
STK12C68-5
64Kb; 5.0 V
35, 55 ns; x8; Mil
CY14B064P
64Kb; 3.0 V
40-MHz SPI; Ind
RTC
CY14B064I
64Kb; 3.0 V
3.4-MHz I2C; Ind
RTC
64Kb-256Kb
512Kb-16Mb
Parallel nvSRAM
1 Industrial
4 AEC-Q100
7
2 Real-time
5
8
grade -40°C to +85°C
clock
3 Open NAND flash interface
Document No. 001-89435 Rev. *P
-40°C to +125°C
Military grade -55°C to +125°C
6 Low-pin-count
Higher Densities
nvSRAM
NDA Required
Contact Sales
Quad serial peripheral interface
Extended Industrial grade -40°C to +105°C
Concept
Development
Sampling
Production
QQYY
QQYY
Status
Availability
107
F-RAM Portfolio
Low Power | High Endurance
4Kb-256Kb
512Kb-8Mb
LPC1
Processor
Companion
F-RAM
Wireless
Memory
Parallel F-RAM
FM25V20A
2Mb; 2.0-3.6 V
40-MHz SPI; Ind2
CY15B104Q
4Mb; 2.0-3.6 V
40-MHz SPI; Ind
Higher Densities
F-RAM
NDA Required
Contact Sales
FM22L16/LD16
4Mb; 2.7-3.6 V
55 ns; x8; Ind
CY15B102Q
2Mb; 2.0-3.6 V
25-MHz SPI; Auto E3
FM25V10/VN10
1Mb; 2.0-3.6 V
40-MHz SPI; Ind, Auto A
FM24V10/VN10
1Mb; 2.0-3.6 V
3.4-MHz I2C; Ind, Auto A
FM28V102A
1Mb; 2.0-3.6 V
60 ns; x16; Ind
FM28V202A
2Mb; 2.0-3.6 V
60 ns; x16; Ind
FM25V05
512Kb; 2.0-3.6 V
40-MHz SPI; Ind, Auto A
FM24V05
512Kb; 2.0-3.6 V
3.4-MHz I2C; Ind, Auto A
CY15B101N
1Mb; 2.0-3.6 V
60 ns; x16; Auto A
CY15B102N
2Mb; 2.0-3.6 V
60 ns; x16; Auto A
FM25V02A/W256
256Kb; V02A: 2.0-3.6 V
W256: 2.7-5.5 V
40-MHz SPI; Ind, Auto A
FM24V02A/W256
256Kb; V02A: 2.0-3.6 V
W256: 2.7-5.5 V
3.4-MHz I2C; Ind, Auto A
FM33256
256Kb; 3.3V; 16-MHz SPI
Ind; RTC5; Power Fail
Watchdog; Counter
FM28V020
256Kb; 2.0-3.6 V
70 ns; x8; Ind
FM18W08
256Kb; 2.7-5.5 V
70 ns; x8; Ind
FM25V01A
128Kb; 2.0-3.6 V
40-MHz SPI; Ind, Auto A
FM24V01A
128Kb; 2.0-3.6 V
3.4-MHz I2C; Ind, Auto A
FM31256/31(L)278
256Kb; 3.3, 5.0V; 1-MHz
I2C; Ind; RTC; Power
Fail; Watchdog; Counter
FM1808B
256Kb; 5.0 V
70 ns; x8; Ind
FM16W08
64Kb; 2.7-5.5 V
70 ns; x8; Ind
FM25640/CL64
64Kb; 3.3, 5.0 V
20-MHz SPI; Ind, Auto E4
FM24C64/CL64
64Kb; 3.3, 5.0 V
1-MHz I2C; Ind, Auto E
FM3164/31(L)276
64Kb; 3.3, 5.0 V; 1-MHz
I2C; Ind; RTC; Power
Fail; Watchdog; Counter
FM25C160/L16
16Kb; 3.3, 5.0 V
20-MHz SPI; Ind, Auto E
FM24C16/CL16
16Kb; 3.3, 5.0 V
1-MHz I2C; Ind, Auto A
FM25040/L04
4Kb; 3.3, 5.0 V
20-MHz SPI; Ind, Auto E
FM24C04/CL04
4Kb; 3.3, 5.0 V
1-MHz I2C; Ind, Auto A
1
4 AEC-Q100
2
5 Real-time
Low-pin-count
Industrial grade -40°C to +85°C
3 AEC-Q100 -40°C to +85°C
Document No. 001-89435 Rev. *P
-40°C to +125°C
clock
Wireless Memory
NDA Required
Contact Sales
Concept
Development
Sampling
Production
QQYY
QQYY
Status
Availability
108
nvSRAM Packages
Family
44-pin
TSOP
II
48-ball
FBGA








4Mb



8Mb



16Mb

28-pin
SOIC
28-pin
CDIP
64Kb



256Kb



Density
8-pin
SOIC
8-pin
DFN
16-pin
SOIC
1Mb
Parallel
64Kb

256Kb

512Kb

1Mb

64Kb

LPC












Document No. 001-89435 Rev. *P
Wafer

512Kb

165ball
FBGA


1Mb
48-pin 48-pin 54-pin 60-ball
SSOP TSOP I TSOPII FBGA

256Kb
I2C
28-pad 32-pin
LCC
SOIC

109
F-RAM Packages
Family
LPC
I2C
8-pin
SOIC
8-pin
DFN
4Kb


16Kb


64Kb


128Kb

256Kb

512Kb

1Mb

Density
14-pin
SOIC
28-pin
SOIC
28-pin
TSOP I
32-pin
TSOP I


44-pin
TSOP II
48-ball
FBGA
Wafer

2Mb


4Mb


4Kb

16Kb


64Kb


128Kb

256Kb

512Kb

1Mb

64Kb
Processor
Companion 256Kb
Parallel
8-pin
EIAJ


64Kb

256Kb



2Mb


4Mb

1Mb
Document No. 001-89435 Rev. *P



110
4Mb SPI Serial F-RAM
Applications
Block Diagram
Multifunction printers
Industrial controls and automation
Medical wearables
Test and measurement equipment
Smart meters
4Mb SPI Serial F-RAM
Control
4
Instruction
Register
Features
40-MHz SPI interface
100-trillion read/write cycle endurance
Operating voltage range: 2.0-3.6 V
Low (8-µA) sleep current
100-year data retention
Industrial temperature operation
Packages: 8-pin TDFN, 8-pin SOIC
Document No. 001-89435 Rev. *P
F-RAM
Array
Address
Register
Serial
Input
Data I/O
Register
Serial
Output
Status
Register
Availability
Collateral
Preliminary Datasheet:
Control
Logic
Contact Sales
Sampling:
Production:
Now
Now
111
1Mb Quad SPI nvSRAM
Applications
Block Diagram
Computing and networking
Industrial automation
RAID storage
VCAP2
1Mb Quad SPI
nvSRAM
Store
Control
2
Control
Logic
Features
QSPI I/Os
Quad SPI interface: 108 MHz
Unlimited write endurance
One million store cycles on power fail
Data retention of 20 years at 85°C
Operating voltages: 3.0 V, 1.8-V I/O
Low standby (280-µA) and sleep (10-µA) currents
Industrial temperature range: -40°C to +85°C
Extended Industrial temperature range: -40°C to +105°C
Integrated, high-accuracy real-time clock (RTC)
Package: 16-SOIC
Store/Recall
Control
SRAM Array
4
I/O
Control
Recall
Software
Command
Detect
XIN1
XOUT1
RTC
VRTC
HSB3
Availability
Collateral
Sampling:
Production:
Final Datasheet: CY14V101QS
1
2
Document No. 001-89435 Rev. *P
Power
Control
SONOS Array
Now
Now
Crystal connections
External capacitor connection
3 Hardware
store busy
112
Timing Solutions
Document No. 001-89435 Rev. *P
113
Standard Performance
High Performance
Clock Synthesizer Roadmap
1
Product
Family
Features
CY37xx
Frequency: 3.5 GHz
12 Outputs; 4 PLL;
0.09-ps RMS Jitter1
(Q2’18)
CY34xx
Frequency: 2.1 GHz
12 Outputs; 1-4 PLL;
0.09-ps RMS Jitter
(Q4’17)
CY294x
Frequency: 2.1 GHz
1 Output; 1 PLL;
0.11-ps RMS Jitter
CY27410
Frequency: 700 MHz
12 Outputs; 4 PLL;
0.7-ps RMS Jitter
CY2xx
(FleXO™)
Frequency: 690 MHz
1 Output; 1 PLL;
0.6-ps RMS Jitter
CY254x /
CY251x
Frequency: 166 MHz
3-9 Outputs; 1-4 PLL;
100-ps CCJ2
CY22800 /
CY22801 /
CY2429x
Frequency: 200 MHz
2-4 Outputs; 1 PLL;
250-ps CCJ
CY2239x /
CY229x /
CY2238x
Frequency: 200 MHz
3-6 Outputs; 3-4 PLL;
400-ps CCJ
CY22050 /
CY22150
Frequency: 200 MHz
3-6 Outputs; 1 PLL;
250-ps CCJ
Integrated phase noise across 12-kHz to 20-MHz offset
jitter
2 Cycle-to-cycle
Document No. 001-89435 Rev. *P
(Prod)
[EOL]
2016
Q1 Q2
Q3
2017
Q4
Q1
Q2
Q3
2018
Q4
Q1
Q2
Q3
2019
Q4
Q1
Q2
Q3
2020
Q4
Q1
Q2
Q3
Q4
[Q3’20]
[Q4’20]
Concept
Samples
Production
EOL
114
Clock Buffer Roadmap (NDA)
Product
Family
Features
CY2DLx /
DMx/DPx/CPx
Frequency: 1.5 GHz
2-10 Outputs;
0.05-ps RMS Jitter1;
(Prod)
[EOL]
2016
Q1
Q2
Q3
2017
Q4
Q1
Q2
Q3
2018
Q4
Q1
Q2
Q3
2019
Q4
Q1 Q2
Q3
2020
Q4
Q1
Q2
Q3
Q4
Frequency: 220 MHz
CY230x / EP0x 5-9 Outputs;
22-ps CCJ4;
CY230xNZ
Frequency: 133 MHz
4-18 Outputs;
250-ps CCJ;
CY23S02/05/0
8/09/FP12
Frequency: 200 MHz
2-12 Outputs; 200-ps
CCJ4;
[Q3’19]
CY7B99x
(RoboClock™)
Frequency: 200 MHz
8-18 Outputs; 50-ps
CCJ;
[Q3’19]
1
Integrated phase noise across 12-kHz to 20-MHz offset
jitter
2 Cycle-to-cycle
Document No. 001-89435 Rev. *P
Concept
Samples
Production
EOL
115
Timing Solutions Portfolio (NDA)
Programmable | High-Performance | EMI Reduction | Automotive
Clock Generators
Clock Buffers
Standard Performance
High Performance
Programmable Clocks
CY274x
Maximum Frequency: 700 MHz
12 Outputs; PCIe 3.0; 4 PLL
0.7-ps RMS Jitter1; Ind2; Auto A3
Q320
CY2Xx (FleXO™)
Maximum Frequency: 690 MHz
1 Output; Frequency Margining
0.6-ps RMS Jitter; Ind
NEW
Q117
CY294x/ CY5107
Maximum Frequency: 2.1 GHz
1 Output; 40/100 GbE; 1 PLL
0.11-ps RMS Jitter; Ind
NEW
PLL ICs
Zero/Non-Zero Delay Buffer
MB15F63UL
Maximum Input Frequency: 2 GHz
Sigma-Delta and Integer PLL;
-88.5 dBc/Hz CNR4; Ind
CY2DLx/DMx/DPx/CPx
Maximum Frequency: 1.5 GHz
2-10 Outputs; LVDS, LVPECL, CML
0.05-ps RMS Jitter; Ind
Q217
CY34xx
Maximum Frequency: 2.1 GHz
0.1-ps RMS Jitter
Contact Sales
CY37xx
Maximum Frequency: 3.5 GHz
12 Outputs; 4 PLL; JESD204B
0.09-ps RMS Jitter; Ind
CY254x/CY251x
Maximum Frequency: 166 MHz
3-9 Outputs; 1-4 PLL; I2C
100-ps CCJ6; Ind
CY2239x/CY229x/CY2238x Q420
Maximum Frequency: 200 MHz
3-6 Outputs; 3-4 PLL; I2C
400-ps CCJ; Ind; Auto E7
CY22800/801/2429x
Maximum Frequency: 200 MHz
2-4 Outputs; 1 PLL; PCIe 1.1
250-ps CCJ; Ind; Auto A
MB88151Ax/2Ax/3Ax/4Ax
Maximum Frequency: 134 MHz
1 Output; 1 PLL;
< 200-ps CCJ; Ind
MB15E07SL/05SL/03SL
Maximum Input Frequency: 2.5GHz
1 PLL; < 4mA PSC8; Ind
CY230x/EP0x
Maximum Frequency: 220 MHz
5-9 Outputs; LVCMOS
22-ps CCJ; Ind; Auto A
CY22050/150
Maximum Frequency: 200 MHz
3-6 Outputs; 1 PLL
250-ps CCJ; Ind
MB15E07SR/06SR/05SR
Maximum Input Frequency: 3GHz
1 PLL; -86 dBc/Hz CNR; Ind
CY230xNZ
Maximum Frequency: 133 MHz
4-18 Outputs; LVCMOS
250-ps CCJ; Ind
MB88155x
Maximum Frequency: 80 MHz
1 Output; 1 PLL;
< 200-ps CCJ; Ind
MB15F78UL/73UL/72UL
Maximum Input Frequency: 2.6 GHz
2 PLL; < 2.8 mA PSC; Ind
CY23S02/05/08/09/FP12 Q319
Maximum Frequency: 200 MHz
2-12 Outputs; Spread Aware
200-ps CCJ; Ind
MB15F07SL
Maximum Input Frequency: 1.1 GHz
2 PLL; < 5 mA PSC; Ind
CY7B99x (RoboClock™) Q319
Maximum Frequency: 200 MHz
8-18 Outputs; Configurable Skew
50-ps CCJ; Ind2
Concept Development Sampling
1
Integrated phase noise across 12-kHz to 20-MHz offset
2 Industrial grade: -40°C to +85°C
3 AEC-Q100: -40°C to +85°C
4 Carrier-to-noise ratio
Document No. 001-89435 Rev. *P
5
Automatic clock switching on failure of a clock source
6 Cycle-to-cycle jitter
7 AEC-Q100: -40°C to +125°C
8 Power supply current
Status
Availability
EOL (Last-Time-Ship)
QQYY
Production
QQYY
QQYY
116
CY274x: High-Performance 4-PLL
Clock Generator (NDA)
Applications
Block Diagram
Multifunction printers
Digital TVs
Blu-ray recorders
Home gateways
Femtocells
Routers and switches
PLL 1 Block
High frequency: 700-MHz differential, 250-MHz single-ended
Pin select and I2C programming
Twelve outputs:
Eight configurable (differential or single-ended)
Four single-ended
Reference clock support for PCIe 3.0, SATA 2.0 and 10 GbE
RMS phase jitter <0.7 ps (typical)
Additional features:
Configurable as zero or non-zero delay buffer
Glitch-free frequency switching
Frequency select
Early / late clocks
PLL cascading
Voltage-controlled frequency synthesis (VCFS)
Collateral
OUT1
Divider
OUT2
Divider
OUT3P
Divider
OUT3N
PLL
Divider
XIN1
Features
XOUT2
IN1P3
IN1N3
IN2P3
IN2N3
Output
Bank 1
OUT4P
OUT4N
OUT5P
Input
Block
OUT5N
PLL 2 Block
OUT6P
OUT6N
OUT7P
SCLK4
SDAT4
VIN5
FS26
FS16
FS06
OUT7N
Memory
and
Control
Logic
OUT8P
PLL 3 Block
Output
Bank 2
OUT8N
OUT9P
OUT9N
OUT10P
PLL 4 Block
OUT10N
OUT11
OUT12
Availability
Datasheet: 4-PLL High Performance Clock Generator (CY274X)
1
4 Serial
2
5 Voltage
Crystal input
Crystal output
3 Reference clock inputs
Four-PLL Spread-Spectrum Clock Generator
Sampling:
Production:
Now
Now
port
input pin for VCFS
6 Frequency select inputs
Document No. 001-89435 Rev. *P
117
CY294x: High-Performance 1-PLL
Programmable Oscillator
Applications
Block Diagram
Routers
Switches
Base stations
Storage area networks
Network backplanes
Wireless infrastructure
Military/Aerospace
Test and measurement
Video
High-Performance Programmable Oscillator
Crystal
Oscillator
PLL
Features
High frequency: 2,100-MHz differential, 250-MHz single-ended
LVPECL1, LVDS2, HCSL3 and CML4 outputs
RMS phase jitter5 ~110 fs (typical) at all output frequencies
Frequency select to choose from four preprogrammed
configurations
Voltage-controlled frequency synthesis (VCFS) with tunable
pull range of 50 ppm to 275 ppm
Pin select and I2C programming
VDD support: 1.8 V, 2.5 V and 3.3 V
Operating temperature range from -40°C to +85°C
Available in a 5 mm x 7 mm, 5 mm x 3.2 mm LCC package
Collateral
SCLK6
SDAT6
VIN7
FS18
FS08
OUT1P
OUT1N
Memory
and
Control
Logic
Sampling:
Production:
Now
Q1 2017
1
4
7
2
5
8 Frequency
Document No. 001-89435 Rev. *P
Output
Bank
Availability
Preliminary Datasheet: Contact Sales
Low-voltage positive emitter coupled logic
Low-voltage differential signaling
3 High-speed current steering logic
Divider
Current mode logic
The uncertainty of the clock rising and falling edge timing
6 I2C input
Voltage input pin for VCFS
select inputs
118
CY3441: High-Performance Quad-PLL
Clock Synthesizers
Block Diagram
XIN10
XOUT11
Applications
Routers
Switches
Base stations
Storage area networks
Network backplanes
Wireless infrastructure
CY3441
PLL 1
Features
IN0
IN1
IN2
Input
Clock
Dividers
and Mux
Four inputs supporting frequencies of 8 kHz to 750 MHz
Twelve outputs supporting frequencies of 8 kHz to 2,100 MHz
LVPECL1, LVDS2, HCSL3, CML4 and LVCMOS5 outputs
Four independently configurable PLLs
Fully programmable loop bandwidth of 1 mHz to 4 kHz
Pin select and I2C programming
RMS phase jitter6 ~110 fs (typical)
Operating temperature range from -40°C to +85°C
64-QFN Package
Additional features:
Completely flexible input to output frequency translation
Jitter attenuation
Hitless switching7
Clock monitoring with fully programmable thresholds
SCLK8
SDAT8
RST9
OE9
Collateral
Availability
Preliminary Datasheet: Contact Sales
Contact Sales
IN3
PLL 2
Output
Bank
Memory
and
Control
Logic
PLL 3
PLL 4
1
4 Current
7
10
2
5
8 I2C
11
Low-voltage positive emitter coupled logic
Low-voltage differential signaling
3 High-speed current steering logic
Document No. 001-89435 Rev. *P
mode logic
Low-voltage CMOS
6 The uncertainty of the clock rising and falling edge timing
Automatic clock switching on failure of a clock source
input
9 Reset and output enable
OUT0P
OUT0N
OUT1P
OUT1N
OUT2P
OUT2N
OUT3P
OUT3N
OUT4P
OUT4N
OUT5P
OUT5N
OUT6P
OUT6N
OUT7P
OUT7N
OUT8P
OUT8N
OUT9P
OUT9N
OUT10P
OUT10N
Crystal input
Crystal output
119
Specialty Memory
Document No. 001-89435 Rev. *P
120
Specialty Memory Portfolio
Intelligent Memory | High Density | High Throughput
Dual-Port SRAM
Asynchronous
FIFO
Synchronous
Synchronous
2 Mb-72 Mb
CYFB0072V4
72Mb; 1.8, 3.3 V
133 MHz
x36; Ind1
CYD02/9/18/36SxxV18
2Mb, 9Mb, 18Mb, 36Mb; 1.8 V
167 MHz, 200 MHz
x18, x36, x72; Ind1
CYFX18V/36V/72V
18Mb, 36Mb, 72Mb; 1.8, 3.3 V
100 MHz, 133 MHz
x9 to x36 Prog3; Ind1
2 Kb-64 Kb
128 Kb-1 Mb
CY7C083x/5x
2Mb, 4Mb, 9Mb, 18Mb; 3.3 V
100 MHz, 133 MHz, 167 MHz
x18, x36, x72; Ind1
CY7C02x/3x/5x
512Kb, 1Mb; 3.3, 5.0 V
12 ns, 15 ns, 20 ns, 25 ns
x8, x16, x18, x36; Ind1
CY7C09279/289/389/579
512Kb, 1Mb; 3.3 V
7, 9, 12 ns; 83 MHz, 100 MHz
x8, x16, x18, x36; Ind1
CY7C4275/81/85/91
512Kb, 1Mb; 3.3 V
67 MHz, 100 MHz
x9, x18; Ind1
CY7C006/025/026
128Kb, 256Kb; 3.3, 5.0 V
15 ns, 20 ns, 25 ns, 55 ns
x8, x16, x18; Ind1
CY7C09269/369
256Kb; 3.3 V
9 ns, 12 ns
x16, x18; Ind1
CY7C4255/61/65/71
128Kb, 256Kb; 3.3, 5.0 V
67 MHz, 100 MHz
x9, x18; Ind1
CY7C024/144
64Kb; 3.3, 5.0 V
15 ns, 20 ns, 25 ns, 55 ns
x8, x16, x18; Ind1
CY7C09159/349
64Kb; 3.3 V
9 ns, 12 ns
x9, x18; Comm2
CY7C13x
8Kb, 16Kb, 32Kb; 5.0 V
15 ns, 25 ns, 55 ns
x8; Ind1
1
Industrial grade: -40°C to +85°C
Commercial grade: 0°C to +70°C
3 Programmable bus width
2
Document No. 001-89435 Rev. *P
CY7C4201/11
2Kb, 4Kb; 3.3 V
67 MHz
x9; Ind1
4
Production Sampling Development Concept
CYFB denotes Video Frame Buffer products
Status
Availability
QQYY
QQYY
121
Flash Memory
Document No. 001-89435 Rev. *P
122
NOR Flash Memory Family Decoder
S 29 G L 128 S
Document No. 001-89435 Rev. *P
Technology: J = 110-nm Floating Gate (FG)
K = 90-nm FG
L = 65-nm FG
M = 50-nm FG
N = 110-nm MirrorBit® (MB) 1 = 63-nm DRAM
P = 90-nm MB
R, S = 65-nm MB
T = 45-nm MB
Density:
008 = 8Mb 064 = 64Mb
016 = 16Mb 128 = 128Mb
032 = 32Mb 256 = 256Mb
512 = 512Mb
01G = 1Gb
02G = 2Gb
Voltage:
D = 2.5 V
S = 1.8 V
Family:
A = Standard ADP (Address-Data Parallel)
C = Burst Mode ADP (Address-Data Parallel)
F = Serial
G = Page Mode
J = Simultaneous Read/Write ADP (Address-Data Parallel)
K = HyperBus™
N = Burst Mode Simultaneous Read/Write ADM (Address-Data Multiplexed)
P = Page Mode Simultaneous Read/Write ADP (Address-Data Parallel)
V = Burst Mode Simultaneous Read/Write ADM (Address-Data Multiplexed)
W = Burst Mode Simultaneous Read/Write ADP (Address-Data Parallel)
X = Burst Mode Simultaneous Read/Write AADM (Address-Address-Data
Multiplexed)
Series:
25 = SPI
26 = HyperFlash™
29 = Parallel 70 = Stacked Die
Prefix:
S
L = 3.0 V
04G = 4Gb
27 = HyperRAM™
79 = Dual Quad SPI
Product Selector Guide 123
Parallel NOR Flash Memory Roadmap
Product Family
Density
S29GL-T
45-nm MB
3.0 V
2Gb1
1Gb
512Mb
S29GL-S
65-nm MB
3.0 V
2Gb1
1Gb
512Mb
256Mb
128Mb
64Mb
S29GL-P
90-nm MB
3.0 V
2Gb1
1Gb
512Mb
S29GL-P
90-nm MB
3.0 V
256Mb
128Mb
S29GL-N
110-nm MB
3.0 V
64Mb
32Mb
S29AS-J / S29AL-J
110-nm FG
1.8 V / 3.0 V
16Mb
8Mb
S29JL-J
110-nm FG
3.0 V
64Mb
32Mb
S29PL-J
110-nm FG
3.0 V
128Mb
64Mb
32Mb
1
S70 Series
Document No. 001-89435 Rev. *P
(Prod)
[EOL]
2017
Q1
Q2
Q3
2018
Q4
Q1
Q2
Q3
2019
Q4
Q1
Q2
2020
Q3
Q4
Q1
Q2
Q3
2021
Q4
Q1
Q2
Q3
Q4
[Q3’17]
[Q3’17]
[Q3’17]
All parts supported by Longevity Program unless noted
Concept
Samples
Production
EOL
124
Parallel NOR Flash Memory Portfolio
S29PL-J1, 2
S29GL-N2
S29GL-P2
S29GL-S2
S29GL-T2
S29AS-J
S29AL-J
S29JL-J1
110-nm FG, 1.8 V 110-nm FG, 3.0 V 110-nm FG, 3.0 V 110-nm FG, 3.0 V 110-nm MB, 3.0 V 90-nm MB, 3.0 V 65-nm MB, 3.0 V 45-nm MB, 3.0 V
≥256Mb
Density
Initial/Page Access
* Temp Range
All parts supported by
Longevity Program
unless noted
≤32Mb
64–128Mb
128Mb
60 ns / 20 ns
* I, A
16Mb
70 ns / -* I, A
16Mb
55 ns / -* I, A, N, M
8Mb
70 ns / -* I, A
8Mb
55 ns / -* I, A, N, M
64Mb
55 ns / -* I, A
64Mb
55 ns / 20 ns
* I, A
64Mb
90 ns / 25 ns
* I, A
32Mb
60 ns / -* I, A
32Mb
55 ns / 20 ns
* I, A
32Mb
90 ns / 25 ns
* I, A
* I = Industrial: -40°C to +85°C
A = Automotive, AEC-Q100 Grade 3: -40°C to +85°C
V = Industrial-plus: -40°C to +105°C
B = Automotive, AEC-Q100 Grade 2: -40°C to +105°C
N = Extended: -40°C to +125°C
M = Automotive, AEC-Q100 Grade 1: -40°C to +125°C
Document No. 001-89435 Rev. *P
2Gb3 Q317
110 ns / 25 ns
*I
2Gb3
110 ns / 20 ns
* I, A, V, B
2Gb3
110 ns / 20 ns
* I, A, V, B, N
Q317
1Gb
110 ns / 25 ns
*I
1Gb
100 ns / 15 ns
* I, A, V, B
1Gb
100 ns / 15 ns
* I, A, V, B, N
512Mb Q317
100 ns / 25 ns
*I
512Mb
100 ns / 15 ns
* I, A, V, B
512Mb
100 ns / 15 ns
* I, A, V, B, N
256Mb
90 ns / 25 ns
*I
256Mb
90 ns / 15 ns
* I, A, V, B
128Mb
90 ns / 25 ns
*I
128Mb
90 ns / 15 ns
* I, A, V, B
64Mb
70 ns / 15 ns
* I, A, B
1
Supports Simultaneous Read/Write Operation
Supports Page Mode
3 S70 series (stacked die)
2
Concept Development Sampling
Status
Availability
EOL (Last-Time-Ship)
QQYY
Production
QQYY
QQYY
125
Burst NOR Flash Memory Roadmap
Product Family
Density
S29WS-P
90-nm MB
1.8 V
512Mb
256Mb
128Mb
S29NS-P
90-nm MB
1.8 V
512Mb
S29VS-R
65-nm MB
1.8 V
256Mb
128Mb
64Mb
S29XS-R
65-nm MB
1.8 V
256Mb
128Mb
64Mb
S29CD-J / S29CL-J
110-nm MB
2.5 V / 3.0 V
32Mb
16Mb
(Prod)
[EOL]
2017
Q1
Q2
Q3
2018
Q4
Q1
Q2
Q3
2019
Q4
Q1
All parts supported by Longevity Program unless noted
Document No. 001-89435 Rev. *P
Q2
2020
Q3
Q4
Concept
Q1
Q2
Q3
Samples
2021
Q4
Q1
Q2
Production
Q3
Q4
EOL
126
S29WS-P1
90-nm MB, 1.8 V
S29NS-P2
90-nm MB, 1.8 V
S29VS-R2
65-nm MB, 1.8 V
S29XS-R3
65-nm MB, 1.8 V
Density
Initial Access/SDR Clock
* Temp Range
All parts supported by
Longevity Program
unless noted
512Mb
80 ns / 104 MHz
*W
512Mb
80 ns / 83 MHz
*W
256Mb
80 ns / 104 MHz
*W
256Mb
80 ns / 108 MHz
* W, I
256Mb
80 ns / 108 MHz
* W, I
128Mb
80 ns / 104 MHz
*W
128Mb
80 ns / 108 MHz
* W, I
128Mb
80 ns / 108 MHz
* W, I
64Mb
80 ns / 108 MHz
* W, I
64Mb
80 ns / 108 MHz
* W, I
≤32Mb
64–128Mb
≥256Mb
Burst NOR Flash Memory Portfolio
* W = Wireless: -25°C to +85°C
I = Industrial: -40°C to +85°C
A = Automotive, AEC-Q100 Grade 3: -40°C to +85°C
N = Extended: -40°C to +125°C
M = Automotive, AEC-Q100 Grade 1: -40°C to +125°C
Document No. 001-89435 Rev. *P
S29CD-J1
110-nm FG, 2.5 V
S29CL-J1
110-nm FG, 3.0 V
32Mb
54 ns / 75 MHz
* I, A, N, M, H, T
32Mb
54 ns / 75 MHz
* I, A, N, M, H, T
16Mb
54 ns / 66 MHz
* I, A, N, M, H, T
16Mb
54 ns / 66 MHz
* I, A, N, M, H, T
1 ADP
(Address Data Parallel) Burst
(Address Data Multiplex) Burst
3 AADM (Address high, Address low, Data Multiplex) Burst
2 ADM
Concept Development Sampling
Status
Availability
EOL (Last-Time-Ship)
QQYY
Production
QQYY
QQYY
127
Serial NOR Flash Memory Roadmap
Product Family
Density
(Prod)
[EOL]
S25FS-S / S25FL-S
65-nm MB1
1.8 V / 3.0 V
1Gb3
512Mb
256Mb
128Mb
64Mb4
S79FL-S
65-nm MB1
3.0 V
1Gb5
512Mb5
256Mb5
S25FL-P
90-nm MB1
3.0 V
256Mb3
128Mb
64Mb
32Mb
[Q4’17]
[Q2’18]
[Q1’18]
[Q1’18]
S25FL-L
65-nm FG2
3.0 V
256Mb
128Mb
64Mb
(Q2’17)
(Q1’17)
S25FL1-K
90-nm FG2
3.0 V
64Mb
32Mb
16Mb
[Q1’18]
[Q1’18]
[Q1’18]
S25FL2-K
90-nm FG2
3.0 V
8Mb
[Q1’17]
2017
Q1
Q2
Q3
2018
Q4
Q1
Q2
Q3
2019
Q4
Q1
Q2
2020
Q3
Q4
Q1
Q2
Q3
2021
Q4
Q1
Q2
Q3
Q4
All parts supported by Longevity Program unless noted
1 >4KB
Sector
2 4KB
Sector
3 S70
Document No. 001-89435 Rev. *P
Series
4 1.8V
Only
5 S79
Dual Quad SPI
Concept
Samples
Production
EOL
128
SPI NOR Flash Memory Portfolio
S25FL2-K1
90-nm FG, 3.0 V
4KB2
S25FL1-K
90-nm FG, 3.0 V
4KB2
S25FL-L
65-nm FG, 3.0 V
4KB2
S25FL-P
90-nm MB, 3.0 V
>4KB2
All parts supported by
Longevity Program
unless noted
64–128Mb
≥256Mb
Density
SDR Clock/DDR Clock
* Temp Range
64Mb Q118
108 MHz / -* I, A, V, B, N4, M4
S79FL-S3
65-nm MB, 3.0 V
>4KB2
S25FS-S
65-nm MB, 1.8 V
>4KB2
1Gb5
133 MHz / 80 MHz
* I, A, V, B, N, M
1Gb
133 MHz / 80 MHz
* I, A, V, B
1Gb5
133 MHz / 80 MHz
* I, A, V, B, N, M
512Mb
133 MHz / 80 MHz
* I, A, V, B, N ,M
512Mb
133 MHz / 80 MHz
* I, A, V, B
512Mb
133 MHz / 80 MHz
* I, A, V, B, N, M
256Mb
133 MHz / 80 MHz
* I, A, V, B
256Mb
133 MHz / 80 MHz
* I, A, V, B, M
256Mb
133 MHz / 66 MHz
* I, A, V, B, N, M
256Mb5 Q417
104 MHz / -* I, A
256Mb
133 MHz / 80 MHz
* I, A, V, B, N, M
128Mb Q217
133 MHz / 66 MHz
* I, A, V, B, N, M
128Mb6 Q218
104 MHz / -* I, A, V, B
128Mb8
133 MHz / 80 MHz
* I, A, V, B, N, M
128Mb7 Q218
104 MHz / -* I, A, V, B
128Mb9
108 MHz / -* I, A, V, B
64Mb Q117
108 MHz / 54 MHz
* I, A, V, B, N, M
32Mb Q118
108 MHz / -* I, A, V, B, N4, M4
≤32Mb
S25FL-S
65-nm MB, 3.0 V
>4KB2
Q118
64Mb
104 MHz / -* I, A, V, B
128Mb
133 MHz / 80 MHz
* I, A, V, B, M
64Mb
133 MHz / 80 MHz
* I, A, V, B, N, M
Q118
32Mb
104 MHz / -* I, A, V, B
16Mb Q118
108 MHz / -* I, A, V, B, N4, M4
8Mb
76 MHz / -*I
Q117
* I = Industrial: -40ºC to +85ºC
A = Automotive, AEC-Q100 Grade 3: -40ºC to +85ºC
V = Industrial-plus: -40ºC to +105ºC
B = Automotive, AEC-Q100 Grade 2: -40ºC to +105ºC
N = Extended: -40ºC to +125ºC
M = Automotive, AEC-Q100 Grade 1: -40ºC to +125ºC
Document No. 001-89435 Rev. *P
1
6
2
7
S25FL2-K Dual SPI
Logical sector size
3 S79 series, Dual Quad SPI
(stacked die)
4 Contact Sales
5 S70 series (stacked die)
S25FL129P Quad SPI
S25FL128P Dual SPI
8 S25FL128S 133-MHz SDR/
80-MHz DDR
9 S25FL127S 108-MHz SDR
Concept Development Sampling
Status
Availability
EOL (Last-Time-Ship)
QQYY
Production
QQYY
QQYY
129
HyperFlash™ and HyperRAM™ NOR
Flash Memory Roadmap
Product Family
Density
(Prod)
[EOL]
S26KS-S / S26KL-S
65-nm MB1
1.8 V / 3.0 V
1Gb2
512Mb
256Mb
128Mb
(TBD)
S27KS-1 / S27KL-1
63-nm DRAM
1.8 V / 3.0 V
256Mb2
128Mb2
64Mb
(TBD)
(Q4’16)
1
>4KB Sector
2
S70 Series
Document No. 001-89435 Rev. *P
2017
Q1
Q2
Q3
2018
Q4
Q1
Q2
Q3
2019
Q4
Q1
All parts supported by Longevity Program unless noted
Q2
2020
Q3
Q4
Concept
Q1
Q2
Q3
Samples
2021
Q4
Q1
Q2
Production
Q3
Q4
EOL
130
HyperFlash™ and HyperRAM™
Portfolio
HyperFlash
S26KS-S1
65-nm MB, 1.8 V
HyperFlash
S26KL-S1
65-nm MB, 3.0 V
HyperRAM
S27KS-12
63-nm DRAM, 1.8 V
HyperRAM
S27KL-12
63-nm DRAM, 3.0 V
256Mb3
Contact Sales
Density
Initial Access/DDR Clock
* Temp Range
64–128Mb
≥256Mb
All parts supported by
Longevity Program
unless noted
1Gb3
96 ns / 166 MHz
* I, A, V, B, N, M
1Gb3
96 ns / 100 MHz
* I, A, V, B, N, M
512Mb
96 ns / 166 MHz
* I, A, V, B, N4, M4
512Mb
96 ns / 100 MHz
* I, A, V, B, N4, M4
256Mb
96 ns / 166 MHz
* I, A, V, B, N4, M4
256Mb
96 ns / 100 MHz
* I, A, V, B, N4, M4
256Mb3
Contact Sales
128Mb
96 ns / 166 MHz
* I, A, V, B, N4, M4
128Mb
96 ns / 100 MHz
* I, A, V, B, N4, M4
128Mb3
Contact Sales
Q117
Q117
64Mb
36 ns / 166 MHz
* I, A, V, B
* I = Industrial: -40°C to +85°C
A = Automotive, AEC-Q100 Grade 3: -40°C to +85°C
V = Industrial-plus: -40°C to +105°C
B = Automotive, AEC-Q100 Grade 2: -40°C to +105°C
N = Extended: -40°C to +125°C
M = Automotive, AEC-Q100 Grade 1: -40°C to +125°C
Document No. 001-89435 Rev. *P
Q217
128Mb3
Contact Sales
64Mb
36 ns / 100 MHz
* I, A, V, B
1 S26
= HyperFlash
= HyperRAM
3 S70 series (stacked die)
4 Contact sales
2 S27
Concept Development Sampling
Status
Availability
EOL (Last-Time-Ship)
QQYY
Production
QQYY
QQYY
131
NAND Family Decoder
NAND
S 34 M L 08G 2
1 Multi-level
Technology: 1 = 4x-nm
2 = 32-nm
3 = 16-nm
Density:
01G = 1Gb
02G = 2Gb
04G = 4Gb
08G = 8Gb
16G = 16Gb
Voltage:
L = 3.0 V
S = 1.8 V
Family:
M = NAND (Address-Data Multiplexed)
S = SecureNAND (Address-Data Multiplexed)
Series:
34 = NAND
Prefix:
S
cell
Document No. 001-89435 Rev. *P
Product Selector Guide
132
NAND Flash Memory Roadmap
Product Family
Density
(Prod)
[EOL]
S34MS-1 / S34ML-1
4x-nm SLC, ONFI 1.0
1.8 V / 3.0 V
8Gb1
4Gb
2Gb
1Gb
S34MS-2 / S34ML-2
32-nm SLC, ONFI 1.0
1.8 V / 3.0 V
16Gb
8Gb
4Gb
2Gb
1Gb
S34SL-2
32-nm SLC, ONFI 1.0
3.0 V
4Gb
2Gb
1Gb
S34ML-3
16-nm SLC, ONFI 1.0
3.0 V
16Gb
8Gb
4Gb
2Gb
1Gb
(TBD)
(TBD)
(Q2’18)
(TBD)
(TBD)
S34MS-3
16-nm SLC, ONFI 1.0
1.8 V
16Gb
8Gb
4Gb
2Gb
1Gb
(TBD)
(TBD)
(Q4’18)
(TBD)
(TBD)
1
3.0V only
Document No. 001-89435 Rev. *P
2017
Q1
Q2
Q3
2018
Q4
Q1
Q2
Q3
2019
Q4
Q1
Q2
2020
Q3
Q4
Q1
Q2
Q3
2021
Q4
Q1
Q2
Q3
Q4
[Q2’18]
[Q2’18]
[Q2’18]
[Q2’18]
All parts supported by Longevity Program unless noted
Concept
Samples
Production
EOL
133
SLC NAND Portfolio
S34ML-11
4x-nm, 3.0 V
SLC, ONFI 1.02
S34MS-11
4x-nm, 1.8 V
SLC, ONFI 1.02
S34ML-23
32-nm, 3.0 V
SLC, ONFI 1.02
S34MS-23
32-nm, 1.8 V
SLC, ONFI 1.02
16Gb; x8
40 MBps
* I, A5, V5, B5
S34SL-23, 4
32-nm, 3.0 V
SLC, ONFI 1.02
S34ML-31
16-nm, 3.0 V
SLC, ONFI 1.02
S34MS-31
16-nm, 1.8 V
SLC, ONFI 1.02
16Gb; x8
40 MBps
* I, A5, V5, B5
16Gb; x8
40 MBps
* I, A, V, B
16Gb; x8
40 MBps
* I, A, V, B
8Gb; x8
40 MBps
* I, A, V, B
8Gb; x8
40 MBps
* I, A, V, B
8Gb; x8
40 MBps
* I, A, V, B
8Gb; x8
40 MBps
* I, A, V, B
1–4Gb
8–16Gb
Density; Bus Width
Interface Bandwidth
* Temp Range
All parts supported by
Longevity Program
unless noted
8Gb; x8
40 MBps
* I, A, V5, B
Q218
4Gb; x8/16
40 MBps
* I, A, V , B
Q218
4Gb; x8
40 MBps
* I, A5, V, B
Q218
4Gb; x8/16
40 MBps
* I, A, V, B
4Gb; x8/16
40 MBps
* I, A, V, B
4Gb; x8
40 MBps
* I, V
4Gb; x8
40 MBps
* I, A, V, B
2Gb; x8/16
40 MBps
* I, A, V, B
Q218
2Gb; x8/16
40 MBps
* I, A5, V, B
Q218
2Gb; x8/16
40 MBps
* I, A5, V5, B5
2Gb; x8/16
40 MBps
* I, A5, V5, B5
2Gb; x8
40 MBps
* I, V5
2Gb; x8
40 MBps
* I, A, V, B
2Gb; x8
40 MBps
* I, A, V, B
1Gb; x8
40 MBps
* I, A, V, B
Q218
1Gb; x8/16
40 MBps
* I, A5, V, B
Q218
1Gb; x8/16
40 MBps
* I, A, V, B
1Gb; x8/16
40 MBps
* I, A, V, B
1Gb; x8
40 MBps
* I, V
1Gb; x8
40 MBps
* I, A, V, B
1Gb; x8
40 MBps
* I, A, V, B
* I = Industrial: -40°C to +85°C
A = Automotive, AEC-Q100 Grade 3: -40°C to +85°C
V = Industrial-plus: -40°C to +105°C
B = Automotive, AEC-Q100 Grade 2: -40°C to +105°C
Document No. 001-89435 Rev. *P
Q118
4Gb; x8
40 MBps
* I, A, V, B
1 1-bit
Error-Correcting Code (ECC)
NAND Flash Interface
3 4-bit Error-Correcting Code (ECC)
Status
4 SecureNAND™: Cypress’s SLC NAND Flash Memory with
Availability
full-capacity volatile and nonvolatile block protection
5 Contact Sales
EOL (Last-Time-Ship)
2 Open
Concept Development Sampling
QQYY
Production
QQYY
QQYY
134
Flash and RAM MCP Decoder
S 71 N S 512 R D
RAM Density:
A = 16Mb
B = 32Mb
C = 64Mb
D = 128Mb
E = 256Mb
Flash Technology:
N = 110-nm MirrorBit (MB)
P = 90-nm MB R, S = 65-nm MB
Flash Density:
032 = 32Mb
064 = 64Mb
128 = 128Mb
256 = 256Mb
512 = 512Mb
01G = 1Gb
Voltage:
L = 3.0 V
S = 1.8 V
Family:
G = Page Mode
K = HyperFlash
N = Burst Mode Simultaneous Read/Write ADM (Address-Data Multiplexed)
V = Burst Mode Simultaneous Read/Write ADM (Address-Data Multiplexed)
W = Burst Mode Simultaneous Read/Write ADP (Address-Data Parallel)
X = Burst Mode Simultaneous Read/Write AADM (Address-Address-Data Multiplexed)
Series:
71, 98 = NOR Flash + pSRAM 72 = NOR Flash + DRAM
Prefix:
S
Memory Type:
2 = NAND SLC, x16 NAND, x16 LPDDR1, 200 MHz DDR, 1.8 V
RAM Density:
9 = 512Mb
Flash Density:
A = 1Gb
Voltage:
L = 3.0 V
Family:
M = NAND
Series:
76 = NAND Flash + DRAM
Prefix:
S
S 76 M S A 9 2
Document No. 001-89435 Rev. *P
S = 1.8 V
Product Selector Guide
135
Flash and RAM MCP Flash Memory
Roadmap
Product Family
Flash / RAM
Flash / RAM (Prod)
Density
[EOL]
S71WS-P
90-nm MB / pSRAM
1.8 V
256Mb / 64Mb
S71NS-P
90-nm MB / pSRAM
1.8 V
512Mb / 128Mb
S71VS-R
65-nm MB / pSRAM
1.8 V
256Mb / 128Mb
256Mb / 64Mb
128Mb / 64Mb
128Mb / 32Mb
64Mb / 32Mb
S72VS-R
65-nm MB / DRAM
1.8 V
256Mb / 256Mb
S72XS-P
65-nm MB / DRAM
1.8 V
256Mb / 256Mb
2017
Q1
Q2
Q3
2018
Q4
Q1
Q2
Q3
2019
Q4
Q1
Q2
2020
Q3
Q4
Q1
Q2
Q3
2021
Q4
Q1
Q2
Q3
Q4
S98GL-N
110-nm MB / pSRAM 64Mb / 32Mb
3.0 V
S76MS
NAND / DRAM
1.8 V
1Gb / 512Mb
S71KL-S
HyperFlash /
HyperRAM
3.0 V
512Mb / 64Mb
256Mb / 64Mb (Q217)
128Mb / 64Mb (TBD)
S71KS-S
HyperFlash /
HyperRAM
1.8 V
512Mb / 64Mb (Q2’17)
256Mb / 64Mb (TBD)
128Mb / 64Mb (TBD)
All parts supported by Longevity Program unless noted
Document No. 001-89435 Rev. *P
Concept
Samples
Production
EOL
136
Flash and RAM MCP Memory Portfolio
S71WS-P1
90-nm MB,
1.8 V
S71NS-P2
90-nm MB,
1.8 V
Flash Density
RAM Density
* Temp Range
All parts supported
by Longevity
Program unless
noted
S71VS-R2
65-nm MB,
1.8 V
S72VS-R3
65-nm MB,
1.8 V
S72XS-R3
65-nm MB,
1.8 V
S98GL-N4
110-nm MB,
3.0 V
S76MS5
32-nm MB,
1.8 V
S71KS-S6
65-nm MB,
1.8 V
S71KL-S6
65-nm MB,
3.0 V
≥256Mb
1Gb
512Mb
*I
512Mb Q117
64Mb9
* I, A, V, B
512Mb
64Mb9
* I, A, V, B
256Mb
64Mb
*W
256Mb
64Mb9
* I, A, V, B
256Mb Q117
64Mb9
* I, A, V, B
128Mb
64Mb
*W
128Mb
64Mb9
* I, A, V, B
128Mb
64Mb9
* I, A, V, B
512Mb
128Mb
*W
256Mb
256Mb7
*I
256Mb
128Mb
*W
64–128Mb
256Mb
64Mb
*W
256Mb
256Mb
*W
256Mb
256Mb8
* W, I
128Mb
32Mb
*W
64Mb
32Mb
*W
* W = Wireless: -25°C to +85°C
I = Industrial: -40°C to +85°C
A = Automotive, AEC-Q100 Grade 3: -40°C to +85°C
V = Industrial-plus: -40°C to +105°C
B = Automotive, AEC-Q100 Grade 2: -40°C to +105°C
Document No. 001-89435 Rev. *P
64Mb
32Mb
*I
1 ADP
8 DRAM
2 ADM
9 HyperRAM
(Address Data Parallel) Burst
(Address Data Multiplex) Burst
3 AADM (Address High, Address Low,
Data Multiplex) Burst
4 Parallel, Page Mode
5 NAND
6 HyperFlash
7 DRAM Version 2
Version 1
Concept Development Sampling
Status
Availability
EOL (Last-Time-Ship)
QQYY
Production
QQYY
QQYY
137
Parallel NOR Flash Memory Packages
Family
AS-J
AL-J
JL-J
PL-J
GL-N
GL-P
GL-S
GL-T
Density
Device
48-Ball
FBGA
48-Ball
FBGA
56-Ball
BGA
64-Ball
BGA
64-Ball
Fortified BGA
(0.8-mm pitch)
(0.5-mm pitch)
(0.8-mm pitch)
(0.8-mm pitch)
(1.0-mm pitch)
S29AS008J

16Mb
S29AS016J

8Mb
S29AL008J

16Mb
S29AL016J

32Mb
S29JL032J

8Mb


48-Pin
TSOP
56-Pin
TSOP
KGD









64Mb
S29JL064J

32Mb
S29PL032J



64Mb
S29PL064J


128Mb
S29PL127J
32Mb
S29GL032N


64Mb
S29GL064N


128Mb
S29GL128P
256Mb













S29GL256P



512Mb
S29GL512P


1Gb
S29GL01GP


2Gb
S70GL02GP

64Mb
S29GL064S
128Mb
S29GL128S

256Mb
S29GL256S
512Mb
S29GL512S
1Gb













S29GL01GS



2Gb
S70GL02GS

512Mb
S29GL512T



1Gb
S29GL01GT



2Gb
S70GL02GT
Document No. 001-89435 Rev. *P




138
Burst NOR Flash Memory Packages
Family
WS-P
NS-P
VS-R
XS-R
44-Ball
FBGA
(0.5-mm pitch)
64-Ball
BGA
(0.5-mm pitch)
84-Ball
Fortified BGA
(0.8-mm pitch)
80-Ball
FBGA
(1.0-mm pitch)
80-Pin
PQFP
KGD
S29CD016J



32Mb
S29CD032J


16Mb
S29CL016J


32Mb
S29CL032J


Density
Device
128Mb
S29WS128P

256Mb
S29WS256P

512Mb
S29WS512P

512Mb
S29NS512P
64Mb
S29VS064R

128Mb
S29VS128R

256Mb
S29VS256R

64Mb
S29XS064R

128Mb
S29XS128R

256Mb
S29XS256R

16Mb
CD-J
CL-J
Document No. 001-89435 Rev. *P

139
SPI NOR Flash Memory Packages
Family
Density
Device
FL2-K
8Mb
16Mb
32Mb
64Mb
64Mb
128Mb
256Mb
32Mb
64Mb
128Mb
128Mb
256Mb
128Mb
128Mb
256Mb
512Mb
1Gb
256Mb
512Mb
1Gb
64Mb
128Mb
256Mb
512Mb
1Gb
S25FL208K
S25FL116K
S25FL132K
S25FL164K
S25FL064L
S25FL128L
S25FL256L
S25FL032P
S25FL064P
S25FL128P
S25FL129P
S70FL256P
S25FL127S
S25FL128S
S25FL256S
S25FL512S
S70FL01GS
S79FL256S
S79FL512S
S79FL01GS
S25FS064S
S25FS128S
S25FS256S
S25FS512S
S70FS01GS
FL1-K
FL-L
FL-P
FL-S
FL-S
Dual
Quad
FS-S
SOIC-8
150 mil
SOIC-8
208 mil







UD
UD




SOIC-16
300 mil

UD
UD













CF



USON
4 x 3 mm
WSON
4 x 4 mm
WSON
6 x 5 mm
CF
CF




UD
UD
WSON
8 x 6 mm
VSOP8
208 mil
UD









LGA (CF)
LGA (CF)

CF


BGA24
8 x 6 mm
5 x 5 Ball
BGA24
8 x 6 mm
4 x 6 Ball
KGD



UD
UD






UD
UD






CF
CF
CF

























CF

CF
CF = Contact Factory
UD = Under Development
Document No. 001-89435 Rev. *P
140
HyperFlash and HyperRAM Packages
Family
KS-S
KL-S
KS-1
KL-1
BGA24
8 x 6 mm
5 x 5 Ball
KGD
S26KS128S

CF
256Mb
S26KS256S

CF
512Mb
S26KS512S

CF
1Gb
S70KS01GS

128Mb
S26KL128S

CF
256Mb
S26KL256S

CF
512Mb
S26KL512S

CF
1Gb
S70KL01GS

64Mb
S26KS0641

128Mb
S70KS1281

256Mb
S70KS2561

64Mb
S26KL0641

128Mb
S70KL1281

256Mb
S70KL2561

Density
Device
128Mb
CF
CF
CF = Contact Factory
Document No. 001-89435 Rev. *P
141
SLC NAND Packages
Family
ML-1
ML-2
ML-3
MS-1
MS-2
MS-3
Density
Device
1Gb
2Gb
4Gb
8Gb
1Gb
2Gb
4Gb
8Gb
16Gb
1Gb
2Gb
4Gb
8Gb
16Gb
1Gb
2Gb
4Gb
1Gb
2Gb
4Gb
8Gb
16Gb
1Gb
2Gb
4Gb
8Gb
16Gb
S34ML01G1
S34ML02G1
S34ML04G1
S34ML08G1
S34ML01G2
S34ML02G2
S34ML04G2
S34ML08G2
S34ML16G2
S34ML01G3
S34ML02G3
S34ML04G3
S34ML08G3
S34ML16G3
S34MS01G1
S34MS02G1
S34MS04G1
S34MS01G2
S34MS02G2
S34MS04G2
S34MS08G2
S34MS16G2
S34MS01G3
S34MS02G3
S34MS04G3
S34MS08G3
S34MS16G3
Document No. 001-89435 Rev. *P
63-Ball
BGA
(0.8-mm pitch)



























67-Ball
BGA
(0.8-mm pitch)




48-Pin
TSOP



















142
SecureNAND Packages
Family
SL-2
63-Ball
BGA
(0.8-mm pitch)
Density
Device
1Gb
S34SL01G2

2Gb
S34SL02G2

4Gb
S34SL04G2

Document No. 001-89435 Rev. *P
153-Ball
FBGA
(0.5-mm pitch)
100-Ball
LBGA
(1.0-mm pitch)
143
Flash and RAM MCP Memory Packages
BGA24
8 x 6 mm
5 x 5 Ball
56-Ball
Very Thin FBGA
(0.5-mm pitch)
56-Ball
FBGA
(0.8-mm pitch)
84-Ball
FBGA
(0.8-mm pitch)
130-Ball
BGA
(0.65-mm pitch)
133-Ball
FBGA
(0.5-mm pitch)
Family
Flash
Density
RAM
Density
S71WS-P
256Mb
64Mb
S71NS-P
512Mb
128Mb

256Mb
128Mb

256Mb
64Mb

128Mb
64Mb

128Mb
32Mb

64Mb
32Mb

S72VS-R
256Mb
256Mb

S72XS-R
256Mb
256Mb

S98GL-N
64Mb
32Mb
1Gb
512Mb
128Mb
64Mb

256Mb
64Mb

512Mb
64Mb

128Mb
64Mb

256Mb
64Mb

512Mb
64Mb

S71VS-R
S76MS
S71KS-S
S71KL-S
Document No. 001-89435 Rev. *P



144
Military Memory
Document No. 001-89435 Rev. *P
145
Military Memory Portfolio
Military Temperature | Single Event Latch-up Immune
Fast Async SRAM
Sync SRAM
NoBL®2, ECC
ECC1
F-RAM™
NOR Flash
Serial/Parallel I/O
Serial/Parallel I/O, ECC
Serial/Parallel I/O, ECC
Q217
S29GL-S
128Mb-1Gb; 100 ns/15 ns,
3.0 V, x16,
Auto E5, M
64Mb-1Gb
CY7C41xKV13
144Mb; 667-1066 MHz,
1.3 V, x18/x36,
Burst 2, M4
CY7S106x
16Mb, 1.8-5.0 V,
10 ns, x8/x16/x32,
Auto E, M
CY7C144/6xK
36Mb, 133-250 MHz,
2.5 V/3.3 V, x18/x36,
M
CY7S105x
8Mb, 1.8-5.0 V,
10 ns, x8/x16/x32,
Auto E, M
CY7C137/8xK
18Mb, 100-250 MHz,
2.5 V/3.3 V, x18/x36,
M
CY7S104x
4Mb, 1.8-5.0 V,
12 ns, x8/x16,
Auto E, M
CY7C136xK
9Mb, 100-250 MHz,
2.5 V/3.3 V, x18/x36,
M
64Kb-256Kb
1Mb-36Mb
QDR®3II+/IV
Nonvolatile SRAM
CYPT154xAV18
72Mb, 1.8 V, 250 MHz,
x18/x36; Burst 2/4, M
S25FS-S
128Mb-512Mb; 1.8 V,
133-MHz QSPI,
Auto E, M
CY14B116x
16Mb; 1.8-3.0 V,
25 ns/45 ns, x8/x16/x32,
M, RTC6
CY14B104x
4Mb, 1.8-3.0 V,
25 ns/45 ns, x8/x16,
Auto E, M
CY14B101x
1Mb, 1.8-3.0 V,
25 ns/45 ns, x8/x16, SPI
Auto E, M, RTC
Q317
CY15B102N
2Mb, 2.0-3.6 V,
60 ns, x16, Auto E, M
CY15B102Q
2Mb, 2.0-3.6 V,
40-MHz SPI, Auto E, M
FM25V10
1Mb; 2.0-3.6 V,
40-MHz SPI, Auto E, M
STK12C68-5
64Kb; 5.0 V,
35 ns/55 ns, x8; QML-Q
5 AEC-Q100
2
6 Real-time
Document No. 001-89435 Rev. *P
S25FL-S
128Mb-512Mb; 3.0 V,
133-MHz/80 MHz,
Auto E, M
STK14C88-5
256Kb; 5.0 V,
35 ns/45 ns, x8; QML-Q7
1
Error-correcting code
No Bus Latency
3 Quad Data Rate
4 Military Temperature: −55°C to +125°C
CYRS26xKV18
144Mb, 1.8 V, 450 MHz,
x18/x36, Burst 2/4, M
-40°C to +125°C
clock
7 Qualified Manufacturers List Level Q, per MIL-PRF-38535
Concept
Development
Sampling
Production
QQYY
QQYY
Status
Availability
146
256Kb Military nvSRAM
Applications
Block Diagram
Military communication
Military real-time controls
Avionics real-time controls
High-reliability data logging
VCAP1
256kb Parallel nvSRAM
Features
Fast access time (35 ns, 45 ns, or 55 ns)
Available in parallel interface for 64Kb and 256Kb densities
Unlimited read/write endurance
One million store cycles on power fail
100 years data retention at +85°C
Qualified Manufacturers List Level Q (QML-Q certified)
per MIL-PRF-38535
Military temperature grade: -55°C to +125°C
Packages: Ceramic 32-pin DIP, ceramic 32-pin LCC, 28-pin SOIC
and 32-pin SOIC
SONOS Array
STORE
Control
3
Control
Logic
Data
Store/Recall
Control
SRAM Array
x8
Power
Control
HSB2
RECALL
I/O Control
Address
Decoder
Software
Command
Detect
x14
Collateral
Address
Datasheets: STK12C68
STK14C88
Availability
Sampling: Now
Production: Now
1
2
External capacitor connection
Hardware STORE busy
Document No. 001-89435 Rev. *P
147
SRAM
Applications
Block Diagram
Military communication
Military real-time control
Avionics real-time control
Address
Port
x21, x22
QDR-II+
Data Clocks
Maximum frequency of operation/throughput: 250 MHz/36 Gbps
Burst sizes: 2 or 4
Bus-width configurations: x18 or x36
Military temperature grade: -55°C to +125°C
Two independent unidirectional data ports for read and write
enable concurrent transactions
Maximum throughput with double data rate (DDR) data ports
Output impedance matching input (ZQ): Matches the device
outputs to system data bus impedance
Bit-interleaving to eliminate multi-bit errors
I/O signaling standards: 1.5-1.8 V (HSTL)
Controllers available for Altera/Xilinx/Microsemi FPGAs
Package: 165-pin CCGA2
Collateral
Datasheets: CYPT1542AV18/CYPT1544AV18
CYPT1543AV18/CYPT1545AV18
1
2
CQ
K
CQ
Write Data Port
x18, x36
Write Data Port
(HSTL)
Features
Address Interface
K
SRAM Array
ZQ
Output Impedance Matching
Control
Logic
7
Control
Read Data Port
(HSTL)
72Mb
1
®
QDR -II+
Echo Clocks
QVLD Data Valid
Read Data Port
x18, x36
Boundary
Scan
JTAG Interface
Availability
Sampling: Now
Production: Now
Quad Data Rate: Four data transfers per clock cycle
Ceramic column grid array package
Document No. 001-89435 Rev. *P
148
SRAM
High-performance computing
Military and aerospace systems
Test and measurement
Features
Available in two options: QDR-IV HP (RTR 1,334 MT/s)
and QDR-IV XP (RTR 2,132 MT/s)
Two independent, bidirectional DDR2 data ports
Embedded error-correcting code (ECC) to reduce soft error rate
to <0.01 failure-in-time (FIT) per megabit
Bus inversion to reduce simultaneous switching I/O noise
On-die termination (ODT) to reduce board complexity
De-skew training to improve signal-capture timing
I/O levels: 1.2-1.25 V (HSTL/SSTL), 1.1-1.2 V (POD3)
Military temperature grade: -55°C to +125°C
Package: 361-ball FCBGA4
Bus widths: x18 or x36
Family Table
Option
Density
MPN
Max. Frequency
RTR
QDR-IV HP
72Mb
144Mb
CY7C40x1KV13
CY7C41x1KV13
667 MHz
1,334 MT/s
QDR-IV XP
72Mb
144Mb
CY7C40x2KV13
CY7C41x2KV13
1,066 MHz
2,132 MT/s
Block Diagram
Address
Address/Control Bus
Clock
Inversion Port
Address Parity
Parity Error
x21,x22
QDR-IV
Address Interface
2
2
Data Clocks
2
2
Data Valid
x18, x36
Data Port A
Collateral
Bus Inversion
2
ECC
Data Port B
(HSTL/SSTL or POD)
Applications
Data Port A
(HSTL/SSTL or POD)
1
®
QDR -IV
SRAM Array
Data Clocks
2
2
Data Valid
x18, x36
Data Port B
2
Bus Inversion
Datasheet: CY7C4021KV13/CY7C4041KV13
ODT
Impedance Matching
1
Quad Data Rate: Four data transfers per clock cycle
Double Data Rate: Two data transfers per clock cycle
3 Pseudo Open Drain: Signaling interface that uses strong pull-down and weak
pull-up drive strength
4 Flip-chip ball grid array
Control
Logic
Control
4
Test
Engine
JTAG Interface
Availability
2
Document No. 001-89435 Rev. *P
Sampling: Now
Production: Contact Sales
149
Sync SRAM With On-Chip ECC
Available in flow-through and pipeline modes1
Single-cycle (SCD)2 and double-cycle (DCD)2 deselect options
Bus-width configurations: x18 or x36
Two voltage options: 2.5 V and 3.3 V
Military temperature grade: -55°C to +125°C
Error-correcting code (ECC) to detect and correct
single-bit errors
Packages: 165-ball BGA and 100-pin TQFP
Industry-standard, RoHS3-compliant packages
MPN
Standard Sync with
On-Chip ECC Pipeline
9Mb
18Mb
36Mb
CY7C1360/2K
CY7C1370/2K
CY7C1440/2K
250 MT/s
<0.01
Standard Sync with
On-Chip ECC Flow-Through
9Mb
18Mb
36Mb
CY7C1361/3K
CY7C1371/3K
CY7C1441/3K
133 MT/s
<0.01
Block Diagram
Datasheets: CY7C135XKV33/CY7C136XKV33
CY7C137XKV33/CY7C138XKV33
CY7C144XKV33/CY7C146XKV33
1 Modes
of synchronous SRAM operation that optimize either read latency (Flow-Through)
or operating frequency (Pipeline)
2 Modes of operation in Pipeline mode where the output driver is tri-stated after either a
single cycle (SCD) or dual cycle (DCD) of issuing the deselect command
3 Restriction of Hazardous Substances: A European Union directive intended to eliminate
the use of environmentally hazardous material in electronic components
4 Failures-in-Time (FIT) per Megabit of Data (FIT/Mb): The projected failure rate of a device
where one FIT/Mb equals one failure per billion device hours per megabit of data
Document No. 001-89435 Rev. *P
Input
Register
2
Control
Byte Write
Chip Enable
Clock
Collateral
RTR
FIT/Mb4
Density
Output
Enable
x18, x36
Data Port
Control
Logic
ECC
Encoder
SRAM
Array
Address
Interface
Features
Option
Test
Engine
Avionics engine controls
Radar and signal processing
Test equipment
Military and aerospace systems
Family Table
Data Port and Control
(2.5/3.3V)
Applications
Output
Register
(Pipeline)
x19-x21
Address
Bus
JTAG
Interface
ECC
Decoder
Availability
Sampling: Now
Production: Now
150
Fast SRAM With PowerSnooze™
Applications
1
Family Table
Avionics engine controls
Military helicopter controls
Military/commercial aircraft flight controls
Density
MPN
4Mb
8Mb
16Mb
CY7S104x
CY7S105x
CY7S106x
Deep Sleep Current
(Max at 85°C)
15 µA
22 µA
22 µA
Access Time
(85°C/125°C)
10/12 ns
10/12 ns
10/12 ns
Features
Access time: 10 ns or 12 ns (see Family Table)
PowerSnooze™: Additional power-savings (deep-sleep) mode
Deep-sleep current: 22 µA for 16Mb (see Family Table)
Multiple bus-width configurations: x8, x16 and x32
Wide I/O operating voltage range: 1.8-5.0 V
Military temperature grade: -55°C to +125°C
Industry-standard, RoHS2-compliant and leaded BGA packages
Error-correcting code (ECC) to detect/correct single-bit errors
Bit-interleaving to avoid multi-bit errors
Block Diagram
Fast SRAM with PowerSnooze™
ECC
Encoder
Input
Buffer
Data
Address
20
x8, x16, x32
Address
Decoder
SRAM Array
ERR
Power
Management
Block
(Enables
PowerSnooze)
Collateral
Datasheets: CY7S1049G/CY7C1049G
CY7S1059H/CY7C1059H
CY7S1069G/CY7C1069G
I/O Mux
DS3
Sense
Amps
ECC
Decoder
Control Logic
CE
OE WE BHE4 BLE4
Availability
1
A Fast SRAM with a deep-sleep mode in addition to a conventional standby mode.
For example, the 12-ns 16Mb offering has a deep-sleep current of ≤1.37 µA/Mb and a
standby current of ≤1.87 mA/Mb
2 Restriction of Hazardous Substances: A European Union directive intended to eliminate
the use of environmentally hazardous material in electronic components
3 Deep sleep power mode
4 Byte high enable (BHE)/Byte low enable (BLE)
Document No. 001-89435 Rev. *P
Sampling:
Now
Production: Contact Sales
151
16Mb Parallel nvSRAM
Block Diagram
Applications
Industrial automation
Programmable logic controllers
Gaming machines
Industrial data logging
Networking and storage
Telecom equipment
VCAP4
16Mb Parallel nvSRAM
STORE
Control
Features
Control
Logic
Data
XIN1
XOUT2
INT3
Store/Recall
Control
SRAM Array
HSB5
RECALL
I/O Control
RTC
Power
Control
Address
Decoder
Software
Command
Detect
x21
Address
Availability
Collateral
Datasheet: CY14X116L/CY14X116N/CY14X116S
1
4
2
5
Document No. 001-89435 Rev. *P
3
x32
Fast access time (25 ns)
Available in parallel and Open NAND Flash Interface (ONFI)
version 1.0 interfaces
Unlimited read/write endurance
One million store cycles on power fail
20 years data retention at +85°C
Optional real-time clock (RTC) functionality
Military temperature grade: -55°C to +125°C
Packages: 44-pin TSOP-II, 48-pin TSOP-I, 54- pin TSOP-II,
165-ball FBGA
Crystal connection input
Crystal connection output
3 Interrupt output/calibration/square wave
SONOS Array
Sampling: Now
Production: Contact Sales
External capacitor connection
Hardware STORE busy
152
2Mb SPI Serial F-RAM
Applications
Multifunction printers
Industrial controls and automation
Medical wearables
Test and measurement equipment
Smart meters
Aerospace and defense applications
Missiles and launchers
Block Diagram
2Mb SPI Serial F-RAM
Control
4
Features
40-MHz SPI interface
100-trillion read/write cycle endurance
Operating voltage range: 2.0-3.6 V
Low (20-µA) sleep current at +125°C
100 years data retention at +85°C
Military temperature grade: -55°C to +125°C
Packages: 8-pin TDFN and 8-pin SOIC
Control
Logic
Instruction
Register
F-RAM
Array
Address
Register
Serial
Input
Data I/O
Register
Serial
Output
Status
Register
Collateral
Datasheet: CY15B102Q
Availability
Sampling: Now
Production: Contact Sales
Document No. 001-89435 Rev. *P
153
128Mb/256Mb/512Mb/1Gb Parallel
NOR Flash Memory
Applications
Block Diagram
Military systems boot memory
Avionics boot memory
1Gb Parallel Page Mode NOR Flash Memory
D0 – D15 16
Features
Operating voltage range: 2.7 V to 3.6 V
100 program1/sector erase2 endurance cycles3 at +125°C
>10 years data retention at +125°C
Initial access time: 100 ns
Page access time: 15 ns
Program time (512B): 0.34 ms (typical)
Sector erase time (128KB): 275 ms (typical)
Military temperature grade: -55°C to +125°C
Packages: 56-pin TSOP (14 x 20 mm), 64-ball fortified4 BGA (9
x 9 and 13 x 11 mm)
Embedded
Voltage
Control
A0 – A25 26
X Decoder
Array
RESET
CE
OE
I/O
Y Decoder
Control
Logic
26
WE
WP5
RY/BY6
Data Path
16
Collateral
Datasheet: S29GLXXXS (128M/256M/512M/1G)
Availability
Sampling: Now
Production: Contact Sales
1
4
2
5
The operation required to change a NOR Flash memory cell state from “1” to “0”
The operation in which all the bytes in a sector of NOR Flash memory are erased
simultaneously prior to programming
3 The number of times a NOR Flash memory sector can be programmed or erased before
it wears out
Document No. 001-89435 Rev. *P
Fortified BGA supports a 1-mm ball pitch
Write protect input
6 Ready/busy output
154
128Mb/256Mb/512Mb SPI NOR Flash
Memory
Applications
Block Diagram
Military systems boot memory
Avionics boot memory
512Mb Quad SPI NOR Flash Memory
CS7
SRAM
Features
SCK7
Operating voltage range: 2.7-3.6 V
100 program1/sector erase2 endurance cycles3 at +125°C
>10 years data retention at +125°C
SDR4 clock rate: 104-MHz QIO5
DDR6 clock rate: 80-MHz QIO
Program time (512B): 0.340 ms (typical)
Sector erase time (256KB): 520 ms (typical)
Military temperature grade: -55°C to +125°C
Packages: 16-pin SOIC 300 mil and 24-ball BGA (6x8 mm)
I/O07
Array
Left
X/Y
Decoder
Array
Right
I/O17
I/O
I/O27
Control
Logic
I/O37
RD9
Data Path
RESET8
Collateral
Datasheet: S25FL512S (512Mb)
S25FL128/256S (128Mb/256Mb)
Availability
Sampling: Now
Production: Contact Sales
1
The operation required to change a NOR Flash memory cell state from “1” to “0”
The operation in which all the bytes in a sector of NOR flash memory are erased
simultaneously prior to programming
3 The number of times a NOR Flash memory sector can be programmed/erased before
it wears out
4 Single Data Rate: A mode of data transfer in which data is transferred once per clock
cycle
2
Document No. 001-89435 Rev. *P
5
Quad Input/Output (QIO): An interface that transfers addresses or data on four I/O’s
simultaneously
6 Double Data Rate: A mode of data transfer in which data is transferred twice per clock cycle
7 Signals used for standard Quad (x4) SPI interface. Refer to the S25FL512S datasheet for signal
definitions in the x1 and x2 mode.
8 RESET# is an optional signal available on 16-pin-SOIC and BGA packages.
9 Read data buffer
155
Aerospace Memory
Document No. 001-89435 Rev. *P
156
Aerospace Memory Portfolio
Radiation Hardened | Latch-up Immune | QML-V1 Certified
Fast Async SRAM
Non-ECC2
ECC
Sync SRAM
Nonvolatile NOR
QDR®-II+/IV
Serial I/O
128Mb-256Mb
Q217
16Mb-72Mb
CYRS4141x
144Mb; 1.2 V; 667 MHz
x18, x36; Burst 2
CYRS109x
128Mb; 1.8-5.0 V
12 ns; x8, x16, x32
CYRS264x
144Mb; 1.8 V; 450 MHz
x18, x36; Burst 2,4
CYRS108x
64Mb Serial; 1.8-5.0 V
SPI, QSPI, 106MHz
CYRS154x
72Mb; 1.8 V; 250 MHz
x18, x36; Burst 2,4
FRAM
Serial I/O
Parallel I/O
Q218
CYRS16x256
256Mb; 3.0 V
DDR QSPI; 133MHz
CYRS108x
64Mb; 1.8-5.0 V
12 ns; x8, x16, x32
Q317
Q118
2Mb-4Mb
CYRS106x
16Mb; 1.8-5.0 V
10 ns; x8, x16, x32
CYRS104x
4Mb; 3.3 V
12 ns; x8
Q117
Q317
CYRS104x
4Mb; 1.8-5.0 V
12 ns; x8, x16, x32
Q217
CYRS15x102
2Mb; 2.0-3.6 V
40 MHz; SPI
Concept
Q417
Q217
Development
CYRS15x102
2Mb; 2.0-3.6 V
60 ns; x16
Q417
Sampling
Production
QQYY
QQYY
Status
1
2
Qualified Manufacturers List Level V, per military specification MIL-PRF-38535
Error-correcting code
Document No. 001-89435 Rev. *P
Availability
157
SRAM with RadStop™
Block Diagram
Applications
Payload processing
Reconfigurable computing platforms
Address
Port
x21,x22
Features
QDR-II+
Data Clocks
K
CQ
x18, x36
SRAM Array
ZQ
Output Impedance Matching
Control
Logic
7
Control
Echo Clocks
QVLD
Data Valid
Read Data Port
x18, x36
Boundary
Scan
JTAG Interface
Availability
Cypress Datasheets: 72-Mbit SRAMs w/ RadStop™
DLAM Datasheets: 72-Mbit SRAMs w/ RadStop™
Request FPGA controller IP via email: [email protected]
Non-space-qualified prototypes (CYPT154x): Now
QML-V5 space-qualified devices (CYRS154x): Now
1 Cypress’s
4
2
5
Document No. 001-89435 Rev. *P
CQ
Write Data Port
Collateral
Address Interface
K
Write Data Port
(HSTL)
Maximum frequency of operation/throughput: 250 MHz / 36 Gbps
Burst sizes: 2, 4
Bus-width configurations: x18, x36
Military temperature grade: −55°C to +125°C
Two independent unidirectional data ports for read and write
enable concurrent transactions
Maximum throughput with double data rate (DDR) data ports
Output impedance matching input (ZQ): Matches the device
outputs to system data bus impedance
Bit-interleaving to eliminate multi-bit errors
I/O signaling standards: 1.5−1.8 V (HSTL)
Controller available for Xilinx and Microsemi FPGAs
Total ionizing dose: 300 Krad
Heavy-ION SEL2: 120 LET3 MeV-cm sq/mg
Heavy-ION SEU4: 1.34E-07 (geosynchronous) error/bit-day
QML-V5 qualified (DLAM6 part number: 5962F11201/02VXA)
proprietary design and process technology that increases radiation-resistance
Single-event latch-up
3 Linear energy transfer
1
Read Data Port
(HSTL)
72Mb
QDR®-II+
Single-event upset
Qualified Manufacturers List Level V, per military specification MIL-PRF-38535
6 Defense Logistics Agency Land and Maritime, Columbus, OH
158
4Mb Fast SRAM with RadStop™
1
Block Diagram
Applications
Payload processing
Sensors and switches
Fast SRAM
Features
Access time: 10 ns (85°C), 12 ns (125°C)
Bus-width configuration: x8
Operating voltage: 3.3 V
Military temperature grade: −55°C to +125°C
Bit-interleaving to eliminate multi-bit errors
Package: 36-pin ceramic flat pack (CFP)
Total ionizing dose: 300 Krad
Heavy-ION SEL2: 120 LET3 MeV-cm sq/mg
Heavy-ION SEU4: 5.0E-08 (geosynchronous) error/bit-day
QML-V5 qualified (DLAM6 part number: 5962F11235VXA)
Address Port
x18
CE
Sense
Amps
I/O
MUX
Data Port
x8
OE
WE
Availability
Cypress Datasheet: 4-Mbit SRAM w/ RadStop™
DLAM Datasheet:
4-Mbit SRAM w/ RadStop™
Non-space-qualified prototypes (CYPT1049):
QML-V5 space-qualified devices (CYRS1049):
1 Proprietary
4
2
5
Document No. 001-89435 Rev. *P
SRAM
Array
Control Logic
Collateral
Cypress design and process technology that increases radiation-resistance
Single-event latch-up
3 Linear energy transfer
Address
Decoder
Now
Now
Single-event upset
Qualified Manufacturers List Level V, per military specification MIL-PRF-38535
6 Defense Logistics Agency Land and Maritime, Columbus, OH
159
Energy Harvesting PMIC
Document No. 001-89435 Rev. *P
160
Series Solar Cell by
Panasonic (AM-1801)
Wearable
Activity Monitor
Building
WSNs for HVAC, Level of
Light Emitted,
Temperature, Humidity,
Motion, BLE4 Beacon5
Indoor/Outdoor
Single Solar Cell by
Ningbo Hebe Solar (HSC125155)
NEW
Light
Piezoelectric Device by
Thrive (K7520BS3)
Residential
WSNs2 for HVAC3, Level
of Light Emitted,
Temperature, Humidity,
Motion
S6AE101A
Linear, Power Gating6,
Multiplexer7,
10-pin QFN
Series
Solar Cell
Industrial
WSNs for Infrastructure, Agriculture,
Transportation, Factory Automation, Animal
Monitoring
Indoor
NEW
NEW
NEW
MB39C811
Buck DC/DC, Dual-Bridge
Rectifier, Power Good,
40-pin QFN
MB39C811
Buck DC/DC, Dual-Bridge
Rectifier, Power Good,
40-pin QFN
MB39C811
Buck DC/DC, Dual-Bridge
Rectifier, Power Good,
40-pin QFN
S6AE101A
Linear, Power Gating,
Multiplexer,
10-pin QFN
S6AE102A
Linear, Power Gating,
Multiplexer, LDO8,
Comparator, 20-pin QFN
S6AE103A
Linear, PowerGating,
Multiplexer, LDO, Timer,
Comparator, 24-pin QFN
Energy Harvesting PMIC1 Portfolio
Electromagnetic Device by
Perpetuum (PMG-FSH)
Light
Single
Solar Cell
MB39C811
Buck DC/DC, Dual-Bridge
Rectifier, Power Good,
40-pin QFN
Vibration
TEG by Micropelt
(TGP-651)
Piezoelectric,
Electromagnetic
MB39C831
Boost DC/DC, MPPT,
Li-ion Protection,
40-pin QFN
Thermoelectric
Generator (TEG)
Management IC
2 Wireless Sensor Nodes
3 Heating, ventilation, air conditioning
4 Bluetooth Low Energy
5 A wireless device that transmits data (e.g., signal strength and ID)
over a periodic radio signal from a known location
Document No. 001-89435 Rev. *P
MB39C831
Boost DC/DC, MPPT9,
Li-ion Protection,
40-pin QFN
MB39C811
Buck DC/DC, Dual-Bridge
Rectifier, Power Good,
40-pin QFN
Heat
1 Power
Outdoor
6 Output
Market Segment
power control circuit that controls power provided
to the system load
7 Power source switch circuit for primary battery or Energy
Harvesting Device
8 Low dropout regulator
9 Maximum Power Point Tracking
Concept
Development
Sampling
Production
QQYY
QQYY
Status
Availability
Roadmap 161
Energy Harvesting PMIC1 (S6AE101A)
Applications
Block Diagram
Series solar cell energy harvesting2 and wireless sensor nodes3
Primary
Battery
(Optional)
Features
Ultra-low power: Enables 1 cm2 minimum solar cell size for
startup operation4
Input voltage range:
Series solar cell: 2.0-5.5 V
Primary battery: 2.0-5.5 V
Output voltage range: 1.1-5.2 V
Quiescent current5: 250 nA
Startup power: 1.2 µW
Power gating6 switch circuit
Storage control circuit
Multiplexer7 circuit (battery vs. solar cell)
Overvoltage protection
Packages: 10-pin SON (3.0 x 3.0 mm)
S6AE101A
System
Load
Power Gating6
Switch
+
Multiplexer7
Storage
Control
Series
Solar Cell
Overvoltage
Protection
Vref8
Control Block
Collateral
Datasheet:
S6AE101A Datasheet
Development Kits: Solar-Powered IoT Device Kit
S6AE10xA Evaluation Board
Software:
Easy DesignSim™ Software
Availability
Sampling:
Production:
1 Power
4
2 The
5
Management IC
process of capturing and converting tiny amounts of energy
(e.g., from light, vibration or heat) into electricity
3 A sensor-based device that monitors conditions such as temperature, humidity and
pressure and wirelessly transmits that data to a control unit, such as a PC or a mobile
device
Document No. 001-89435 Rev. *P
Now
Now
Estimate based on solar cell power = 2 µW/cm2 at 100 lx
Current consumed at no load condition
6 Output power control circuit that controls power provided to the system load
7 Power source switch circuit for primary battery and Energy Harvesting Device
8 Voltage reference circuit for internal block
Product Overview 162
Energy Harvesting PMIC1 (S6AE102A)
Applications
Block Diagram
Series solar cell energy harvesting2 and wireless sensor nodes3
Primary Battery
(Optional)
Features
S6AE102A
Power Gating
Switch
+
Ultra-low power: Enables 1 cm2 minimum solar cell size for
startup operation4
Input voltage range:
Series solar cell: 2.0-5.5 V
Primary battery: 2.0-5.5 V
Output voltage range: 1.1-5.2 V
Quiescent current5: 280 nA
Startup power: 1.2 µW
Low quiescent current low dropout regulator (LDO): 400 nA
Dual-channel power gating6 switch circuit with IRQ7 control
Signal output circuit of power gating switch control
Multiplexer8 circuit (battery vs. solar cell)
Hybrid storage control circuit9 and overvoltage protection
Packages: 20-pin QFN (4.0 x 4.0 mm)
Multiplexer
Hybrid Storage
Control
Series
Solar
Cell
Overvoltage
Protection
VIN_LDO
LDO
+
Control Block
ENA_LDO
STBY_LDO
IRQ for Power
Gating
Switch Control
INT
Vref10
Datasheet:
S6AE102A Datasheet
Development Kits: S6AE10xA Evaluation Board
Software:
Easy DesignSim™ Software
Availability
Sampling:
Production:
1 Power
5
2 The
6
Document No. 001-89435 Rev. *P
System
Load2
SW_CONT
VOUT_LDO
Collateral
Management IC
process of capturing and converting tiny amounts of energy
(e.g., from light, vibration or heat) into electricity
3 A sensor-based device that monitors conditions such as temperature, humidity and
pressure and wirelessly transmits that data to a control unit, such as a PC or a mobile device
4 Estimate based on solar cell power = 2 µW/cm2 at 100 lx
Power Gating
Switch
System
Load1
Now
Now
Current consumed at no load condition
Output power control circuit that controls power provided to the system load
7 Interrupt request control function for power management
8 Power source switch circuit for primary battery or series solar cell
9 Uses a small and large capacitor to automatically store excess power for backup
10 Voltage reference circuit for internal block
Product Overview 163
Energy Harvesting PMIC1 (S6AE103A)
Applications
Block Diagram
Series solar cell energy harvesting2 and wireless sensor nodes3
Primary Battery
(Optional)
Features
Ultra-low power: Enables 1 cm2 minimum solar cell size for
startup operation4
Input voltage range:
Series solar cell: 2.0-5.5 V
Primary battery: 2.0-5.5 V
Output voltage range: 1.1-5.2 V
Quiescent current5: 280 nA
Startup power: 1.2 µW
Low quiescent current low drop out regulator (LDO): 400 nA
Low consumption current CR timer6: 30 nA
General-purpose low consumption current comparator: 20 nA
Dual channel power gating7 switch circuit with CR timer and
IRQ6 control
Signal output circuit of power gating switch control
Multiplexer8 circuit (battery vs. solar cell)
Hybrid storage control circuit9 and overvoltage protection
Packages: 24-pin QFN (4.0 x 4.0 mm)
S6AE103A
Power Gating
Switch
+
Multiplexer
Power Gating
Switch
Hybrid Storage
Control
Series
Solar Cell
VIN_LDO
System
Load1
System
Load2
+
Overvoltage
Protection
SW_CONT/
COMPOUT
LDO
ENA_COMP
ENA_LDO
STBY_LDO
VOUT_LDO
Control Block
Vref10
COMPP
Comparator
COMPM
CR Timer & IRQ
for Power Gating
Switch Control
INT
Collateral
Datasheet:
S6AE103A Datasheet
Development Kits: S6AE10xA Evaluation Board
Software:
Easy DesignSim™ Software
Availability
Sampling:
Production:
1 Power
5
2 The
6
Management IC
process of capturing and converting tiny amounts of energy
(e.g., from light, vibration or heat) into electricity
3 A sensor-based device that monitors conditions such as temperature, humidity and pressure
and wirelessly transmits that data to a control unit, such as a PC or a mobile device
4 Estimate based on solar cell power = 2 µW/cm2 at 100 lx
Document No. 001-89435 Rev. *P
Now
Now
Current consumed at no load condition
Time (or IRQ: Interrupt request) control function for power management
7 Output power control circuit that controls power provided to the system load
8 Power source switch circuit for primary battery or series solar cell
9 Uses a small and large capacitor to automatically store excess power for backup
10 Voltage reference circuit for internal block
Product Overview 164
Energy Harvesting PMIC1 (MB39C811)
Applications
Block Diagram
Series solar cell energy harvesting2, Piezoelectric3 energy
harvesting and wireless sensor nodes (WSN)4
MB39C811
Features
Ultralow-power buck DC/DC converter dual-bridge rectifiers
Quiescent current5: 1.5 µA
Input voltage range: 2.6 V-23 V
Output voltage: 1.5 V, 1.8 V, 2.5 V, 3.3 V, 3.6 V, 4.1 V,
4.5 V and 5.0 V
Output current: 100 mAmax
Overcurrent protection
Low-loss full-wave bridge rectifier: VF6 = 0.28 V (IF = 10 µA),
IR7 = 20 nAmax (Vreverse = 18 V)
Shunt for input protection: VIN ≥21 V, up to 100-mA pulldown
Input and output power good monitoring
Package: 40-pin QFN (6.0 x 6.0 mm)
VIN
Series
Solar cell
Shunt
Bridge
Rectifier
Piezoelectric
VOUT
Bridge
Rectifier
VB Reg8
S2
S1
S0
VOUT
Setting
Buck DC/DC
Converter
BGR9
ERR
CMP10
Collateral
Datasheet:
MB39C811 Datasheet
Development Kits: Energy Harvesting Starter Kit
MB39C811 Evaluation Board
Software:
Easy DesignSim™ Software
Availability
Sampling:
Production:
1 Power
5
2 The
6
Management IC
process of capturing and converting tiny amounts of energy
(e.g., from light, vibration or heat) into electricity
3 Power generation device using vibration
4 A sensor-based device that monitors conditions such as temperature, humidity and
pressure and wirelessly transmits that data to a control unit, such as a PC or a mobile device
Document No. 001-89435 Rev. *P
Power Good
VIN
Power
Good
VOUT
Power
Good
Now
Now
Current consumed at no load condition
Bridge rectifier reverse breakdown voltage
7 Bridge rectifier reverse bias leak current
8 Regulator for internal block
9 Band Gap Reference
10 Error Comparator
Product Overview 165
Energy Harvesting PMIC1 (MB39C831)
Applications
Single solar cell energy harvesting2, thermoelectric generator3
energy harvesting and wireless sensor nodes4
Block Diagram
VIN
MB39C831
Features
Ultralow-voltage startup boost DC/DC converter
Input voltage range: 0.3 V-4.75 V
Startup voltage: 0.35 V
Output voltage: 3.0 V, 3.3 V, 3.6 V, 4.1 V, 4.5 V, 5.0 V
(Constant voltage mode only)
Quiescent current5: 32 µA
Output current: 8 mA (VDD = 0.6 V, VOUT = 3.3 V) and
80 mA (VDD = 3.0 V, VOUT = 3.3 V)
Input peak current limit: 200 mA
Built-in Maximum Power Point Tracking (MPPT)6 function
Built-in Li-ion charge function
Input and output power good monitoring
Package: 40-pin QFN (6.0 x 6.0 mm)
VDD Voltage
Detector
(UVLO7)
Startup
VCC Voltage
Detector
VOUT Voltage
Detector
MPPT6
Enable
Enable
S2
S1
S0
VOUT-VDD
Voltage
Inversion
Detector
BGR8
VOUT
Boost DC/DC
Converter
Energy
Storage
Device
MPPT6
Controller
Collateral
Datasheet:
MB39C831 Datasheet
Development Kits: MB39C831 Evaluation Board
Software:
Easy DesignSim™ Software
VIN & VOUT
Power Good
Availability
Sampling:
Production:
1 Power
5 Current
2 The
6 Maximum
Management IC
process of capturing and converting tiny amounts of energy
(e.g., from light, vibration or heat) into electricity
3 Power Generation Device using heat
4 A sensor-based device that monitors conditions such as temperature, humidity and pressure
and wirelessly transmits that data to a control unit, such as a PC or a mobile device
Document No. 001-89435 Rev. *P
Now
Now
consumed at no load condition
Power Point Tracking maximizes the Energy Harvest by adjusting
current drawn from a solar panel
7 Undervoltage lockout
8 Band Gap Reference
Product Overview 166
Automotive Products
Document No. 001-89435 Rev. *P
167
Table of Contents
Page
Topic
169
Automotive TrueTouch®
176
Automotive CapSense®
182
Automotive PSoC®
190
Automotive USB
197
Automotive Traveo Instrument Cluster
206
Automotive Traveo Body Control MCU Family
212
Automotive Traveo MPN Selector Guide
217
Automotive Flash Memory
237
Automotive Power Management IC
242
Automotive Wireless Portfolio
Document No. 001-89435 Rev. *P
168
Automotive TrueTouch® Roadmap
Document No. 001-89435 Rev. *P
169
Automotive Portfolio: TrueTouch
Gen4
Gen6
Gen7
10 Finger, AutoArmor™1, DualSense™2, H2O3, Glove Touch4
In-Cell7 or SLIM8, Gestures, AMS
Thick Glove or Thick/Curved Overlay
Next Generation
CYAT8168X-88
88 I/O, 100-Hz RR9
Grades: A10 and S11
CYAT8X68X-88
88 I/O, 100-Hz RR
Grades: A and S
CYAT8X7XX
NDA Required, Contact Sales
CY8CTMA1036
65 I/O, 80-Hz RR
Gestures, Thin Glove12
Grades: A and S
CYAT8168X-77/71
77/71 I/O, 120-Hz RR
Grades: A and S
CYAT8X68X-77/71
77/71 I/O, 120-Hz RR
Grades: A and S
CY8CTMA768
56 I/O, 80-Hz RR
Gestures, Thin Glove
Grades: A and S
CYAT8168X-61
61 I/O, 120-Hz RR
Grades: A and S
CYAT8X68X-61
61 I/O, 120-Hz RR
Grades: A and S
CYTMA461
48/43 I/O13, 80-Hz RR
AMS, Thick Overlay, Thick Glove
Grades: A and S
CYAT8165X-48
48 I/O, 100-Hz RR
Grades: A and S
CYAT8X65X-48
48 I/O, 100-Hz RR
Grades: A and S
CY8CTMA460
48/43 I/O15, 100-Hz RR
Gestures, Thin Glove
Grades: A and S
CYAT816XX-36
36 I/O, 120-Hz RR
Grades: A and S
CYAT8X6XX-36
36 I/O, 100-Hz RR
Grades: A and S
3″–8″
7″–12″
Active Touch Area
> 12″
Gestures, AMS5
Thick Glove6 or Thick Overlay
1 Enables
compliance with chip-level emission,
immunity and system-level specifications
2 Self-Capacitance + Mutual-Capacitance
3 Waterproofing and wet-finger tracking
4 A feature that allows the detection of gloved fingers
on a touch sensor
5 Automatic Mode Switching
6 1-mm to 5-mm glove thickness (ski gloves)
Document No. 001-89435 Rev. *P
CYAT8X7XX
NDA Required, Contact Sales
Q117
7
A type of sensor stack-up in which the RX sensor is
inside the LCD module under the color-filter glass
8 Single-Layer Independent Multi-Touch
9 Refresh rate
10 AEC-Q100: -40°C to +85°C
11 AEC-Q100: -40°C to +105°C
12 Less than 1-mm glove thickness (normal leather gloves)
13 Number of available I/Os depends on package selection
Concept Development Sampling Production
Industrial
Automotive
Availability
QQYY
QQYY
170
Automotive Portfolio:
TrueTouch® Software1
PSoC Designer™
TrueTouch® Host
Emulator2
TrueTouch Driver for
Android3
Manufacturing Test
Kit4
5.4 SP1
3.3.25
3.5
1.8.10
CY8CTMA616
Production
Production
CY8CTMA884
Production
TTDA 2.5.1
Production
CY8CTMA460
Production
CY8CTMA768
Production
CY8CTMA1036
Production
CY8CTMA461
Production
Production
CYAT8168X-61
Production
Production
CYAT8168X-71
Production
Production
CYAT8168X-77
Production
CYAT8168X-88
Production
CYAT8165X-48
Sampling
Software
MPN
Current Version
Gen 1
Gen 3
Gen 4
Gen 6
®
CY8CTMA120
Production
CY8CTMG120
Production
Production
Production
TTDA 2.5
Production
Contact Sales
Production
Production
Production
Production
Contact sales for the latest TrueTouch software, drivers and tools
1 PSoC
Designer, TTHE and MTK releases are backward compatible. The latest version is recommended for new designs.
Host Emulator (TTHE) is a front-end tool used to configure, tune, debug and demonstrate TrueTouch devices
3 TrueTouch Driver for Android (TTDA) is the driver for Android that translates touch information into Linux/Android events
4 TrueTouch Manufacturing Test Kit (MTK) enables customers and ITO partners to test touch panels that use Cypress TrueTouch controllers through the manufacturing flow
2 TrueTouch
Document No. 001-89435 Rev. *P
171
CY8CTMA460/768/1036
Automotive TrueTouch® Gen4 Family
Applications
Block Diagram
Host Processor
Touchscreens and trackpads
Features
Advanced User Interface
Waterproofing1: Works with water droplets, condensation, sweat
and wet-finger tracking
Tracking with up to 1-mm-thick gloves
Proprietary Analog Front End2 with AutoArmor™3
True 10-V TX-Boost™ with multiphase TX4
DualSense™: Self5- and mutual6-capacitance analog front end
(U.S. patents 8,358,142; 8,319,505; and 8,067,948)
System Solutions
Supports thin ITO7 stackups and metal mesh sensors
AutoArmor enables compliance with chip-level emission
(IEC 61967), immunity (IEC 62132) and system-level
(CISPR 25) specifications
Android driver support
Manufacturing test kits for production testing
Packages
100-pin TQFP, 56-pin QFN (TMA460 only)
1 - I2 C
2 - Serial Peripheral Interface (SPI)
INT8
CY8CTMA
460/768/1036
I2C/SPI
32
32
Flash
ARM® Cortex®
CPU
32
SRAM
32
10-V TX
Pump
Touch
Sequencer
RX
Channels
Programmable Analog Multiplexer
65
Touchscreen Sensor I/O: XY00–XY64
Touchscreen Sensor
Collateral
Availability
Datasheet:
CY8CTMA1036/768/460
Evaluation Kit: CY3290-TMA1036A
Sampling:
Production:
56-pin QFN: Now
100-pin TQFP: Now; 56-pin QFN: Q1 2017
1 The
5 The
2 Analog
6 The
ability of a touchscreen sensor to work properly in the presence of water droplets, condensation or sweat
circuit in the touchscreen controller used to measure self- and mutual-capacitance
3 Cypress proprietary technology used to reduce emissions and improve EMI immunity to meet automotive EMC
requirements
4 A scanning method used to drive multiple TX lines simultaneously
Document No. 001-89435 Rev. *P
capacitance of a row or column line in a touchscreen sensor
capacitance between a row and a column in a touchscreen sensor
7 Indium tin oxide
8 Interrupt
172
CY8CTMA461
Automotive TrueTouch® Gen4 Family
Applications
Block Diagram
Host Processor
Touchscreens and trackpads
Features
Advanced User Interface
Waterproofing1: Works with water droplets, condensation, sweat
and wet-finger tracking
Tracking with up to 5-mm-thick gloves or thick overlay
Proprietary Analog Front End2 with AutoArmor™3
True 10-V TX-Boost™ with multiphase TX4
DualSense™: Self5- and mutual6-capacitance analog front end
(U.S. patents 8,358,142; 8,319,505; and 8,067,948)
System Solutions
Supports thin ITO7 stackups and metal mesh sensors
AutoArmor enables compliance with chip-level emission
(IEC 61967), immunity (IEC 62132) and system-level
(CISPR 25) specifications
Android driver support
Manufacturing test kits for production testing
Packages
100-pin TQFP, 56-pin QFN
1 - I2 C
2 - Serial Peripheral Interface (SPI)
INT8
CY8CTMA461
I2C/SPI
32
32
Flash
ARM® Cortex®
CPU
32
SRAM
32
10-V TX
Pump
Touch
Sequencer
Rx
Channels
Programmable Analog Multiplexer
48
Touchscreen Sensor I/O: XY00–XY47
Touchscreen Sensor
Collateral
Datasheets and Design Guides:
Contact Sales or [email protected]
Availability
Sampling:
Production:
56-pin QFN: Now
100-pin TQFP: Now; 56-pin QFN: Q1 2017
1 The
5 The
2 Analog
6 The
ability of a touchscreen sensor to work properly in the presence of water droplets, condensation or sweat
circuit in the touchscreen controller used to measure self- and mutual-capacitance
3 Cypress proprietary technology used to reduce emissions and improve EMI immunity to meet automotive EMC
requirements
4 A scanning method used to drive multiple TX lines simultaneously
Document No. 001-89435 Rev. *P
capacitance of a row or column line in a touchscreen sensor
capacitance between a row and a column in a touchscreen sensor
7 Indium tin oxide
8 Interrupt
173
CYAT8168X
Automotive TrueTouch® Gen6 Family
Applications
Block Diagram
Host Processor
Large touchscreen human machine interface (HMI) systems
1 - I2C
2 - Serial Peripheral Interface (SPI)
INT7
Features
CYAT8168X
I2C/SPI
Advanced User Interface
Waterproofing1: Works with water droplets, condensation, sweat
and wet-finger tracking
Tracking with up to 5-mm thick gloves or thick overlay
Proprietary Analog Front End2 with AutoArmor™3
True 5-V TX-Boost™ with Multi-Phase TX4
54 Receive Channels to support ≥100 Hz refresh rates
DualSense™: Self5- and mutual6-capacitance analog front end
(U.S. Patents 8,773,146; 8,358,142; 8,319,505; and 8,067,948)
AutoArmor enables compliance with chip-level emissions
(IEC 61967), immunity (IEC 62132) and system-level
(CISPR 25) specifications
System Solutions
Manufacturing test kits for production testing
Package
128-pin TQFP, 100-pin TQFP
32
32
Flash
ARM® Cortex®
CPU
32
SRAM
32
Channel
Engine
Touch
Sequencer
5-V TX
Pump
RX
Channels
Programmable Analog Multiplexer
88
Touchscreen Sensor I/O: XY00–XY87
Touchscreen Sensor
Collateral
Datasheets and Design Guides:
Contact Sales or [email protected]
Availability
Production:
Now
1 The
5 The
2 Analog
6 The
ability of a touchscreen sensor to work properly in the presence of water droplets, condensation or sweat
circuit in the touchscreen controller used to measure self- and mutual-capacitance
3 Cypress proprietary technology used to reduce emissions and improve EMI immunity to meet automotive EMC
requirements
4 A scanning method used to drive multiple TX lines simultaneously
Document No. 001-89435 Rev. *P
capacitance of a row or column line in a touchscreen sensor
capacitance between a row and a column in a touchscreen sensor
7 Interrupt
174
Automotive TrueTouch Packages
Package
Pins
Body Size (mm)
QFN
56
100
128
8x8
14 x 14
14 x 20
0.5
0.5
0.5
Family
Pitch (mm)
Gen 1
CY8CTMA120
, 1
CY8CTMG120

Gen 3
Gen 4
CY8CTMA616

CY8CTMA884

CY8CTMA460
1

CY8CTMA768

CY8CTMA1036

CY8CTMA461
Gen 6
TQFP
1

CYAT8168X-61

CYAT8168X-71

CYAT8168X-77


CYAT8168X-88
CYAT8165X-48
1

Wettable flanks package to allow automated optical inspection (AOI)
Document No. 001-89435 Rev. *P
175
Automotive CapSense® Roadmap
Document No. 001-89435 Rev. *P
176
CapSense Express™
CapSense Plus™
PSoC®
Configurable Controllers1
Programmable Controllers2
Programmable System-on-Chip
CY8CMBR3106S Q217
11 Buttons, 2 Sliders
SmartSense_EMCplus™3
Proximity
Grades: A4 and S5
CY8CMBR3116 Q217
16 Buttons, 8 LEDs
SmartSense_EMCplus
Proximity, Water Tolerance
Grades: A and S
CY8CMBR3108
8 Buttons, 4 LEDs
Proximity, Water Tolerance
SmartSense_EMCplus
CY8CMBR3110 Q217
10 Buttons, 5 LEDs
SmartSense_EMCplus
Proximity, Water Tolerance
Grades: A and S
CY8CMBR3102
2 Buttons, Proximity
SmartSense_EMCplus
CY8CMBR2110
10 Buttons, 10 LEDs
SmartSense Auto-tuning
Entry
Value
Performance
Automotive Portfolio: CapSense®
CY8CMBR2016
16 Buttons
SmartSense Auto-tuning
CY8C20xx7/S
31 Buttons, 6 Sliders
16, 32KB Flash; 2KB SRAM
Proximity, Water Tolerance
Glove, Stylus Support
CY8C20236A
10 Buttons, 2 Sliders
8KB Flash, 1KB SRAM
SmartSense Auto-tuning
Grade: A
CY8C21x34
20 Buttons, 4 Sliders
8KB Flash, 512B SRAM
Proximity, Water Tolerance
Grades: A and E6
CY8C20xx6H
25 Buttons, 5 Sliders
8,16KB Flash; 1,2KB SRAM
SmartSense Auto-tuning
Haptics
CY8CMBR2044
4 Buttons, 4 LEDs
SmartSense Auto-tuning
CY8CMBR2010
10 Buttons, 10 LEDs
SmartSense Auto-tuning
CY8C24x94
43 Buttons, 8 Sliders
16KB Flash, 1KB SRAM
Grade: A
CY8CMBR3002
2 Buttons, 2 LEDs
SmartSense_EMCplus
CY8C201xx
10 Buttons, 5 LEDs
2 Sliders
CY8C20234
10 Buttons, 2 Sliders
8KB Flash, 512B SRAM
Grade: A
CY8C4246/7-M Q117
51 Buttons, 10 Sliders
64, 128KB Flash
Proximity, Water Tolerance
Grades: A and S
CY8C4246/7-L
96 Buttons, 19 Sliders
128, 256KB Flash
Proximity, Water Tolerance
Contact Sales
CY8C41xx-S Q117
34 Buttons, 5 Sliders
16–64KB Flash
Proximity, Water Tolerance
Grades: A and S
CY8C36xx/38xx
62 Buttons, 12 Sliders
32, 64KB Flash
Proximity, Water Tolerance
CY8C41xx/42xx
24 Buttons, 4 Sliders
16, 32KB Flash
Proximity, Water Tolerance
Grades: A and S
CY8C32xx/34xx
62 Buttons, 12 Sliders
16-64KB Flash
Proximity, Water Tolerance
CY8C21x12
20 Buttons, 4 Sliders
8KB Flash, 512B SRAM
Proximity, Water Tolerance
Grades: A and E
CY8C40xx-S Q217
24 Buttons, 5 Sliders
16, 32KB Flash
Proximity, Water Tolerance
Grades: A and S
CY8C2xx45
36 Buttons, 7 Sliders
16KB Flash, 1KB SRAM
Grades: A and E
CY8C40xx
16 Buttons, 3 Sliders
16KB Flash, 2KB SRAM
Proximity, Water Tolerance
Grades: A and S
Integration
1 Standard
products are configured for target applications with a graphical user interface
2 Microcontroller-based products can be freely programmed to implement additional functions
3 SmartSense Electromagnetic Compatible = SmartSense Auto-tuning + high noise immunity
Document No. 001-89435 Rev. *P
4 AEC-Q100:
-40°C to +85°C
5 AEC-Q100: -40°C to +105°C
6 AEC-Q100: -40°C to +125°C
Concept Development Sampling Production
Industrial
Automotive
Availability
QQYY
QQYY
177
Automotive Portfolio:
CapSense® Software1
Software
Current Version
3
5
PSoC® Creator™2
PSoC Designer™
PSoC Programmer4
EZ-Click™
4.0
5.4 SP1
3.25
2.0 SP2
Production
Production
PSoC 1
PSoC 3
Production
Production
PSoC 4
Production
Production
CapSense Plus™
CapSense Express™
Production
Production
Download the latest PSoC software version here
1 All
software and tool releases are backward compatible. The latest versions are recommended for new designs
Creator is an Integrated Design Environment (IDE) that allows concurrent hardware and firmware design of PSoC 3 and PSoC 4 systems
3 PSoC Designer is an IDE that enables firmware design using a library of precharacterized peripherals for PSoC 1 systems
4 PSoC Programmer can be used with PSoC Designer and PSoC Creator to program and debug any design onto a PSoC device
5 EZ-Click is a Windows® GUI-based tool that enables development of CapSense MBR solutions. It allows you to set up sensor configuration, apply global system properties, monitor real-time
sensor output, and run production-line system diagnostics
2 PSoC
Document No. 001-89435 Rev. *P
178
Automotive PSoC® 4100-Series
Intelligent Analog Family
MCU and discrete analog replacement, digital and analog onechip sensor hub, user interface for heating, ventilation and
air conditioning
Block Diagram
PSoC® 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
32-bit MCU Subsystem
24-MHz ARM® Cortex®-M0 CPU
Up to 32KB Flash and 4KB SRAM
Programmable Analog Blocks
Two comparators (CMP)
One opamp, configurable as PGA1, CMP, filter, etc.
One 12-bit, 806-ksps SAR2 ADC
CapSense® with SmartSense™ Auto-tuning
One Cypress Capacitive Sigma-Delta™ (CSD) controller
Capacitive sensing supported on up to 24 pins
Programmable Digital Blocks
Four configurable 16-bit TCPWM3 blocks
Two configurable serial communication blocks (SCBs): I2C master
or slave, SPI master or slave, UART or LIN slave
Packages
28-pin SSOP
Collateral
Datasheet:
Cortex®-M0
24 MHz
Flash
(16KB to 32KB)
SRAM
(4KB)
Advanced High-Performance Bus (AHB)
Features
Opamp
x1
SAR
ADC
CMP
x2
CSD
Programmable Digital
Blocks
TCPWM x4
SCB x2
Segment LCD Drive
I/O Subsystem
GPIO x6
Programmable Interconnect and Routing
Applications
GPIO x4
GPIO x6
GPIO x4
Serial Wire Debug
GPIO x4
Availability
Automotive PSoC 4100 Datasheet
Sampling:
Production:
Now
Now
1 Programmable
gain amplifier
approximation register
3 Timer/counter/pulse-width modulator
2 Successive
Document No. 001-89435 Rev. *P
179
Automotive PSoC® 4200-Series
Programmable Digital Family
MCU and discrete analog replacement, digital and analog onechip sensor hub, user interface for heating, ventilation and
air conditioning
Block Diagram
PSoC® 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
32-bit MCU Subsystem
48-MHz ARM® Cortex®-M0 CPU
Up to 32KB Flash and 4KB SRAM
Programmable Analog Blocks
Two comparators (CMP)
One opamp, configurable as PGA1, CMP, filter, etc.
One 12-bit, 1-Msps SAR2 ADC
CapSense® with SmartSense™ Auto-tuning
One Cypress Capacitive Sigma-Delta™ (CSD) controller
Capacitive sensing supported on up to 24 pins
Programmable Digital Blocks
Four universal digital blocks (UDBs): custom digital peripherals
Four configurable 16-bit TCPWM3 blocks
Two configurable serial communication blocks (SCBs): I2C master
or slave, SPI master or slave, UART or LIN slave
Packages
28-pin SSOP
Collateral
Datasheet:
Cortex®-M0
48 MHz
Flash
(16KB to 32KB)
SRAM
(4KB)
Serial Wire Debug
Advanced High-Performance Bus (AHB)
Features
Opamp
x1
SAR
ADC
CMP
x2
CSD
Programmable Digital
Blocks
UDB x4
TCPWM x4
SCB x2
Segment LCD Drive
I/O Subsystem
GPIO x6
Programmable Interconnect and Routing
Applications
GPIO x4
GPIO x6
GPIO x4
GPIO x4
Availability
Automotive PSoC 4200 Datasheet
Sampling:
Production:
Now
Now
1 Programmable
gain amplifier
approximation register
3 Timer/counter/pulse-width modulator
2 Successive
Document No. 001-89435 Rev. *P
180
Automotive CapSense Packages
Package
Pins
Body Size (mm)
Family
Pitch (mm)
PSoC 1
2XX45
QFN
SOIC
24
56
16
20
28
48
4x4
8x8
3.8 x 9.9
5.3 x 7.3
5.3 x 10.3
7.5 x 15.8
0.5
0.5
1.27
0.65
0.65
0.635


21X34


24X23



24894

29X66
PSoC 4
4000

41/42XX
1
SSOP



Wettable flanks package to allow automated optical inspection (AOI)
Document No. 001-89435 Rev. *P
181
Automotive PSoC® Roadmap
Document No. 001-89435 Rev. *P
182
Automotive PSoC and MCU Portfolio
8-Bit
32-Bit ARM®
Cortex®-M0/M0+
32-Bit ARM®
Cortex®-M3
32-Bit ARM®
Cortex®-M4
32-Bit ARM®
Cortex®-M7
High Analog
Integration
Ultra-Low-Power
8-/16-Bit Replacement
Mid-Range
Performance
High Performance
Next Generation
Analog and Digital Integration
Programmable System-on-Chip (PSoC) is the world’s only programmable embedded
system-on-chip integrating an MCU core, PABs1, PDBs2, programmable interconnect
and routing, and CapSense capacitive sensing
Flexible MCU (FM) is a portfolio of high-performance ARM® Cortex®-M-based
MCUs for industrial and consumer applications
PSoC 5LP
Cortex®-M3
80 MHz, 256KB Flash
20 PAB, 30 PDB, 72 I/Os
PSoC 4
Cortex®-M0
48 MHz, 128KB Flash
Up to 13 PAB, 16 PDB, 51 I/Os
PSoC 3
8051 CPU
67 MHz, 64KB Flash
Up to 19 PAB, 30 PDB, 72 I/Os
PSoC 1
M8C CPU
24 MHz, 32KB Flash
16 PAB, 16 PDB, 56 I/Os
PSoC 7
Cortex®-M7
NDA Required, Contact Sales
PSoC 6
Cortex®-M4 and Cortex®-M0+
NDA Required, Contact Sales
FM7 MCUs
Cortex®-M7
NDA Required, Contact Sales
FM4 MCUs
Cortex®-M4
200 MHz, 2MB Flash, 190 I/Os
FM3 MCUs
Cortex®-M3
144 MHz, 1.5MB Flash, 154 I/Os
PSoC Analog Coprocessor
CY8C4Axx
48 MHz, 32KB Flash
Up to 12 PAB, 11 PDB, 38 I/Os
FM0+ MCUs
Cortex®-M0+
40 MHz, 512KB Flash, 102 I/Os
Concept Development Sampling Production
1
A programmable analog block that is configured using PSoC software to create analog front ends, signal conditioning circuits
with opamps and filters
2 A programmable digital block that is configured using PSoC software to implement custom digital peripherals and glue logic
Document No. 001-89435 Rev. *P
Industrial
Automotive
Availability
QQYY
QQYY
183
Automotive Portfolio: PSoC® 1
M8C Core | 24 MHz
PSoC MCU
Programmable Digital
Intelligent Analog
Performance Analog
Analog: 2x CMP1
Analog: 1x/2x CMP,
4xSC/CT PAB2
Interfaces: I2C, SPI, UART
Analog: 2x/4x CMP,
6xSC/CT PAB, PGA3
Interfaces: I2C, SPI, UART
Analog: 4x CMP,
12x/16x SC/CT PAB, PGA
Interfaces: I2C, SPI, UART
Interfaces: I2C, SPI
CY8C29x66
32K/2K4, 44 GPIOs5
1x14-bit ΔƩ ADC6
Grades: A7 and E8
CY8C27x43
32K/2K, 44 GPIOs
CapSense®, 1x14-bit ΔƩ ADC
CY8C24894
16K/1K, 56 GPIOs
CapSense, 2x14-bit SAR ADC
Grade: A
CY8C28xxx
16K/1K, 44 GPIOs
CapSense, 4x14-bit ΔƩ ADC
Performance
CY8C2xx45
16K/1K, 38 GPIOs
CapSense, 1x10-bit SAR ADC
Grades: A and E
CY8C21x34
8K/0.5K, 28 GPIOs
CapSense, 1x10-bit ADC
Grades: A and E
CY8C24x23
4K/0.25K, 24 GPIOs
CapSense, 1x14-bit ΔƩ ADC
Grades: A and E
CY8C23x33
8K/0.25K, 26 GPIOs
CapSense, 1x 8-bit SAR ADC
CY8C24x93
32K/2K, 36 GPIOs
1x10-bit ADC
CY8C21x23
4K/0.25K, 16 GPIOs
1x10-bit ADC
Integration
1 Comparator
2 Switched
capacitor/continuous time programmable analog block
3 Programmable gain amplifier
4 Flash KB/SRAM KB
5 General-purpose input/output pins
Document No. 001-89435 Rev. *P
6 Analog-to-digital
converter: Includes incremental, successive
approximation register (SAR) or Delta-Sigma (ΔƩ) ADCs
7 AEC-Q100: -40°C to +85°C
8 AEC-Q100: -40°C to +125°C
Concept Development Sampling Production
Industrial
Automotive
Availability
QQYY
QQYY
184
Automotive Portfolio: PSoC® 4
ARM® Cortex®-M0/M0+ | CapSense® | Timer/Counter/PWM
PSoC MCU
PSoC 4000
Intelligent Analog
PSoC 4100
BL = BLE-Series
Programmable Digital
PSoC 4200
S = S-Series
M = M-Series
L = L-Series
CY8C4248-L
48-MHz M0, 256K/32K
CMP, Opamp, ADC
SCB, IDAC, UDB7, CAN8
USB
CY8C4248-BL
48-MHz M0, 256K/32K
CMP, Opamp, ADC
SCB, IDAC, BLE, UDB
CY8C4247-M Q117
48-MHz M0, 128K/16K
CMP, Opamp, ADC
SCB, IDAC, UDB, CAN
Grades: A and S
CY8C4247-L
48-MHz M0, 128K/16K
CMP, Opamp, ADC
SCB, IDAC, UDB, CAN,
USB
CY8C4247-BL
48-MHz M0, 128K/16K
CMP, Opamp, ADC
SCB, IDAC, BLE, UDB
CY8C4246-M Q117
48-MHz M0, 64K/8K
CMP, Opamp, ADC
SCB, IDAC, UDB
Grades: A and S
CY8C4246-L
48-MHz M0, 64K/8K
CMP, Opamp, ADC
SCB, IDAC, UDB, CAN
USB
Flash
CY8C4128-BL
24-MHz M0, 256K/32K1
CMP2, Opamp, ADC3
SCB4, IDAC5, BLE6
Q217
CY8C4045-S
48-MHz M0+, 32K/4K
NDA Contact Sales
Q217
CY8C4024-S
24-MHz M0+, 16K/2K
NDA Contact Sales
CY8C4127-M Q117
24-MHz M0, 128K/16K
CMP, Opamp, ADC
SCB, IDAC
Grades: A9 and S10
CY8C4127-BL
24-MHz M0, 128K/16K
CMP, Opamp, ADC
SCB, IDAC, BLE
CY8C4126-M Q117
24-MHz M0, 64K/8K
CMP, Opamp, ADC
SCB, IDAC
Grades: A and S
CY8C4146-S
48-MHz M0+, 64K/8K
NDA Contact Sales
CY8C4125
24-MHz M0, 32K/4K
CMP, Opamp, ADC
SCB, IDAC
Grades: A and S
CY8C4125-S
24-MHz M0+, 32K/4K
NDA Contact Sales
CY8C4124
24-MHz M0, 16K/4K
CMP, Opamp, ADC
SCB, IDAC
Grades: A and S
CY8C4124-S
24-MHz M0+, 16K/2K
NDA Contact Sales
Q117
Q117
CY8C4245
48-MHz M0, 32K/4K
CMP, Opamp, ADC
SCB, IDAC, UDB
Grades: A and S
Q117
CY8C4244
48-MHz M0, 16K/4K
CMP, Opamp, ADC
SCB, IDAC, UDB
Grades: A and S
CY8C4014
16-MHz M0, 16K/2K
CMP, I2C, IDAC
Grades: A and S
Concept Development Sampling Production
1 Flash
KB/SRAM KB
2 Comparator
3 Analog-to-digital converter
4 Serial
communication block
5 Current-output DAC
6 Bluetooth Low Energy
Document No. 001-89435 Rev. *P
7 Universal
digital block
8 Controller area network
9
AEC-Q100: -40°C to +85°C
10 AEC-Q100: -40°C to +105°C
Industrial
Automotive
Availability
QQYY
QQYY
185
Automotive Portfolio:
PSoC® Software1
Software
Current Version
5
PSoC Designer™
PSoC Programmer4
EZ-Click™
4.0
5.4 SP1
3.25
2.0 SP2
Production
Production
PSoC 1
PSoC 4
3
PSoC Creator™2
Production
Production
Download the latest PSoC software version here
1 All
software and tool releases are backward compatible. The latest versions are recommended for new designs
Creator is an Integrated Design Environment (IDE) that allows concurrent hardware and firmware design of PSoC 3 and PSoC 4 systems
3 PSoC Designer is an IDE that enables firmware design using a library of precharacterized peripherals for PSoC 1 systems
4 PSoC Programmer can be used with PSoC Designer and PSoC Creator to program and debug any design onto a PSoC device
5 EZ-Click is a Windows® GUI-based tool that enables development of CapSense MBR solutions. It allows you to set up sensor configuration, apply global system properties, monitor real-time
sensor output, and run production-line system diagnostics
2 PSoC
Document No. 001-89435 Rev. *P
186
Automotive PSoC® 4100-Series
Intelligent Analog Family
MCU and discrete analog replacement
Digital and analog one-chip sensor hub
User interface for heating, ventilation, air conditioning
Block Diagram
PSoC® 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
32-bit MCU Subsystem
24-MHz ARM® Cortex®-M0 CPU
Up to 32KB Flash and 4KB SRAM
Programmable Analog Blocks
Two comparators (CMP)
One opamp, configurable as PGA1, CMP, filter, etc.
One 12-bit, 806-ksps SAR2 ADC
CapSense® with SmartSense™ Auto-tuning
One Cypress Capacitive Sigma-Delta™ (CSD) controller
Capacitive sensing supported on up to 24 pins
Programmable Digital Blocks
Four configurable 16-bit TCPWM3 blocks
Two configurable serial communication blocks (SCBs): I2C master
or slave, SPI master or slave, UART or LIN slave
Packages
28-pin SSOP
Collateral
Datasheet:
Cortex®-M0
24 MHz
Flash
(16KB to 32KB)
SRAM
(4KB)
Advanced High-Performance Bus (AHB)
Features
Opamp
x1
SAR
ADC
CMP
x2
CSD
Programmable Digital
Blocks
TCPWM x4
SCB x2
Segment LCD Drive
I/O Subsystem
GPIO x6
Programmable Interconnect and Routing
Applications
GPIO x4
GPIO x6
GPIO x4
Serial Wire Debug
GPIO x4
Availability
Automotive PSoC 4100 Datasheet
Sampling:
Production:
Now
Now
1 Programmable
gain amplifier
approximation register
3 Timer/counter/pulse-width modulator
2 Successive
Document No. 001-89435 Rev. *P
187
Automotive PSoC® 4200-Series
Programmable Digital Family
MCU and discrete analog replacement
Digital and analog one-chip sensor hub
User interface for heating, ventilation, air conditioning
Block Diagram
PSoC® 4 One-Chip Solution
MCU Subsystem
Programmable Analog
Blocks
32-bit MCU Subsystem
48-MHz ARM® Cortex®-M0 CPU
Up to 32KB Flash and 4KB SRAM
Programmable Analog Blocks
Two comparators (CMP)
One opamp, configurable as PGA1, CMP, filter, etc.
One 12-bit, 1-Msps SAR2 ADC
CapSense® with SmartSense™ Auto-tuning
One Cypress Capacitive Sigma-Delta™ (CSD) controller
Capacitive sensing supported on up to 24 pins
Programmable Digital Blocks
Four universal digital blocks (UDBs): custom digital peripherals
Four configurable 16-bit TCPWM3 blocks
Two configurable serial communication blocks (SCBs): I2C master
or slave, SPI master or slave, UART or LIN slave
Packages
28-pin SSOP
Collateral
Datasheet:
Cortex®-M0
48 MHz
Flash
(16KB to 32KB)
SRAM
(4KB)
Serial Wire Debug
Advanced High-Performance Bus (AHB)
Features
Opamp
x1
SAR
ADC
CMP
x2
CSD
Programmable Digital
Blocks
UDB x4
TCPWM x4
SCB x2
Segment LCD Drive
I/O Subsystem
GPIO x6
Programmable Interconnect and Routing
Applications
GPIO x4
GPIO x6
GPIO x4
GPIO x4
Availability
Automotive PSoC 4200 Datasheet
Sampling:
Production:
Now
Now
1 Programmable
gain amplifier
approximation register
3 Timer/counter/pulse-width modulator
2 Successive
Document No. 001-89435 Rev. *P
188
Automotive PSoC Packages
Package
Pins
Body Size (mm)
Family
Pitch (mm)
PSoC 1
2XX45
QFN
SOIC
24
56
16
20
28
48
4x4
8x8
3.8 x 9.9
5.3 x 7.3
5.3 x 10.3
7.5 x 15.8
0.5
0.5
1.27
0.65
0.65
0.635


21X34


24X23



24894

29X66
PSoC 4
4000

41/42XX
1
SSOP



Wettable flanks package to allow automated optical inspection (AOI)
Document No. 001-89435 Rev. *P
189
Automotive USB
Document No. 001-89435 Rev. *P
190
Automotive Portfolio: USB
Device
Hub
FX3: CYUSB301x
USB 3.1 Gen 1, Shared Link™1
BC 1.22, Ghost Charge™3
Grade: A4, S5
USB 3.1
32-Bit Bus to USB 3.1 Gen 1
ARM9, 512KB RAM
NEW
CYUSB401x
FX3PD
USB 3.1 Gen 2 Type-C
USB PD, LVDS, 10 Gbps
HX3: CYUSB33xx
Bridge
Q117
USB 2.0
Storage
Type-C
CX3: CYUSB306x
FX3S: CYUSB303x
CCG1: CYPD1xxx
CSI-26 to USB 3.1 Gen 1
4 CSI-26 Lanes, 1 Gbps/Lane
16-Bit Bus to USB 3.1 Gen 1
RAID7, Dual SDXC8/eMMC9
USB Type-C Port Controller
1 PD Port, 5 Profiles, 100 W
HX3C: CYUSB333x
GX3: CYUSB361x
SD3: CYUSB302x
4 Ports: 1 Type-C, 3 Type-A
USB PD, Billboard, BC1.22
USB 3.1 Gen 1 to GigE
Energy Efficient Ethernet
USB 3.1 Gen 1 SD Reader
SDXC8/eMMC9, RAID7
HX3PD: CYUSB434x
DX3: CYUSB307x
CCG2: CYPD2xxx
USB Type-C Cable Controller
1 PD Port, Termination, ESD
Grade: A4, S5
CCG3: CYPD3xxx
USB Type-C Port Controller
20-V, Crypto, Billboard
Grade: A4, S5
DSI10
USB 3.1 Gen 2 Type-C Hub
USB PD, Billboard, 10 Gbps
USB 1.1
Host
USB 3.1 Gen 1 to
TX
4 DSI Lanes, 1 Gbps/Lane
FX2LP: CY7C6801x/53
HX2VL: CY7C656x4
Bay™: CYWB016xBB
16-Bit Bus to USB 2.0
8051, 16KB RAM
4 Ports
4 Transaction Translators
HS USB OTG
Dual SDXC8/eMMC9
Arroyo™, Astoria™:
CYWB0x2xABS
16-Bit Bus to USB 2.0
8051, Dual SD/eMMC9
CCG4: CYPD4xxx
USB Type-C Port Controller
2 PD Ports,128KB Flash, Mux
Grade: A4, S5
TX2UL: CY7C68003
HX2LP: CY7C656x1
NX2LP: CY7C6803x
CCG3PA: CYPD3xxx
ULPI11 PHY
13, 19.2, 24, 26 MHz
4 Ports, Industrial Grade
1 Transaction Translator
NAND Flash to USB 2.0
8051, 15KB RAM
USB Type-C Port Controller
30V, Direct Charge, 64KB Flash
FX2G2: CYUSB201x
AT2LP: CY7C683xx
CCG5: CYPS5xxx
32-Bit Bus to USB 2.0
ARM9 512KB RAM
Parallel ATA to USB 2.0
8051
USB Type-C Port Controller
2 PD Ports
enCoRe™ II: CY7C638xx
USB-Serial: CY7C6521x
SL811HS
M8C MCU, 20 GPIOs
SPI, 8KB Flash
UART/SPI/I2C to USB
2 Channels, CapSense®
FS USB Host/Device
256Byte RAM
enCoRe III: CY7C64215
USB-to-UART (Gen 2):
CY7C65213
M8C MCU, 50 GPIOs, ADC
I2C/SPI, 16KB Flash
3 Mbps, 8 GPIOs
USB Billboard:
CY7C65210/7
enCoRe V: CY7C643xx
M8C MCU, 36 GPIOs, ADC
I2C/SPI, 32KB Flash
ARM Cortex M0
1 or 2 UART/SPI/I2C channels
4 AEC-Q100: -40°C to +85°C
USB 2.0 and
SuperSpeed traffic on the same port 5 AEC-Q100: -40°C to +105°C
6 Camera Serial Interface v2.0
2 Battery Charging specification v1.2
3 Enables USB charging without host connection
1 Simultaneous
Document No. 001-89435 Rev. *P
Type-C products
apply to any
USB speed
EZ-Host : CY7C67300
4 Ports, FS USB OTG
32 GPIOs
Grade: A4
EZ-OTG™ : CY7C67200
2 Ports, FS USB OTG
25 GPIOs
10 Display Serial Interface
array of
11 UTMI low-pin interface
independent disks
8 SD extended capacity
9 Embedded Multimedia Card
Concept Development Sampling Production
7 Redundant
Industrial
Automotive
Availability
QQYY
QQYY
191
Automotive HX3
USB 3.1 Gen 1 Hub
Applications
Block Diagram
Upstream Port
Automotive infotainment
2
4
Features
HX3 Hub
SS PHY
1
2
8
MCU
I2C
16
32
SuperSpeed Hub
Controller
USB 2.0 Hub Controller
16
32
Buffers
Repeater
4x TT2
16
32
Routing Logic
Routing Logic
32
16
SS PHY
USB 2.0 PHY
4
HX3 Datasheet
HX3 Hardware Design Guidelines
and Schematic Checklist (AN91378)
Kits:
CY4609, CY4603, CY4613
Configuration Utility: Blaster Plus1
USB 2.0 PHY
32
USB 3.1 Gen 1 PHY
Datasheet:
Application Note:
2
USB 3.1 Gen 1 PHY
USB 3.1 Gen 1-compliant four-port Hub Controller
USB-IF certified (Test ID: 330000047)
WHQL certified for Windows 7, Window 8, Windows 8.1
Shared Link™: Supports simultaneous USB 2.0 and
USB SuperSpeed (SS) devices on the same port
Ghost Charge™: Enables USB charging while the Hub is
disconnected from a USB Host
Charging Standard support:
USB-IF Battery Charging v1.2
Apple Charging Standard
Charging an OTG Host in an ACA-Dock
Programming of external EEPROM via USB
Configurable USB SS and USB 2.0 PHY. Drives 11ʺ trace
100-BGA (6 x 6 x 1.0 mm)
Collateral
EEPROM
2
Downstream Port 1
USB 3.1 Gen 1 PHY
SS PHY
4
USB 2.0 PHY
2
Downstream Port 2
USB 3.1 Gen 1 PHY
SS PHY
4
USB 2.0 PHY
2
Downstream Port 3
USB 3.1 Gen 1 PHY
SS PHY
4
USB 2.0 PHY
2
Downstream Port 4
Availability
Sampling:
Production:
Industrial (Now), Automotive: Q1 2017
Industrial (Now), Automotive: Q1 2017
Transaction translator
A Cypress GUI-based PC application for setting HX3 configuration parameters
Document No. 001-89435 Rev. *P
192
Automotive CCG2
USB Type-C and PD Port Controller
Applications
Block Diagram
Automotive infotainment
CCG2: USB Type-C Port Controller With PD
MCU Subsystem
Features
Collateral
TCPWM6
Flash
(32KB)
SRAM
(4KB)
VCONN1
SCB
SPI, UART)
VCONN2
SCB
(I2C, SPI, UART)
Profiles and
Configurations
Baseband MAC
Baseband PHY
Programmable I/O Matrix
48 MHz
Advanced High-Performance Bus (AHB)
CORTEX-M0
(I2C,
VDDIO
GPIO5
Port
Integrated RP, RD, RA
Serial Wire Debug
Availability
CCG2 Datasheet
CCG2 RDK
communication block configurable as UART, SPI or I2C
Termination resistor read as a DFP
3 Termination resistor read as a UFP
4 Termination resistor read as an EMCA
Samples: Industrial (Now)
1 Serial
5 General-purpose
2
6
Document No. 001-89435 Rev. *P
I/O Subsystem
CC7
32-bit MCU Subsystem
48-MHz ARM® Cortex® -M0 CPU with 32KB flash and 4KB SRAM
Integrated Digital Blocks
Integrated timers, counters and pulse-width modulators
Two SCBs1 configurable to I2C, SPI or UART modes
Type-C Support
Integrated transceiver, supporting one Type-C port
Integrated DFP (RP2), UFP (RD3), EMCA (RA4) termination resistors
Power Delivery (PD) Support
Standard power profiles
Low-Power Operation
Two independent VCONN rails with integrated isolation
Independent supply voltage pin for GPIO5
2.7-V to 5.5-V operation
Sleep: 2.0 mA; Deep Sleep: 2.5 µA
System-Level ESD on CC6 and VDD Pins
±8-kV contact, ±15-kV Air Gap IEC61000-4-2 level 4C
Package
24-pin QFN
Datasheet:
Reference Design Kit:
Integrated Digital Blocks
Production: Industrial (Now)
input/output
Timer/counter/pulse-width modulation block
7 Configuration Channel
193
Automotive CCG3
USB Type-C and PD Port Controller
Applications
Block Diagram
Automotive infotainment
CCG3: USB Type-C Cable Controller
Collateral
Datasheet:
Cortex®-M0
48 MHz
Flash
(64KB)
Flash
(64KB)
Advanced High-Performance Bus (AHB)
Type-C Support
Integrated transceiver, supporting one Type-C port
Alternate modes1, Crypto engine2 for USB Authentication3
Power Delivery (PD) Support for Standard Power Profiles
Integrated Digital Blocks for VBUS Power and MUX Interface
Four timers, counters and pulse-width modulators, 24x GPIOs
Four SCBs4 for configurable master/slave I2C, SPI or UART
USB Billboard Controller5 with Billboard Device Class6 support
Integrated Analog Blocks for OVP, OCP7
20-V OVP7 and OCP7; 4:2 cross-bar switch
32-bit ARM® Cortex®-M0 CPU with MCU Subsystem
2x64KB Flash for fail-safe updates over CC, I2C or USB interfaces
Low-Power Operation
2x VBUS gate drivers8, for consumer and provider power paths
2x high-voltage (5–20 V, 25 V maximum) VBUS voltage inputs
Sleep: 2.0 mA; deep sleep: 2.5 µA with wake-on-I2C or wake-on-CC
System-Level ESD on CC/VCONN, VBUS, and SBU Pins
±8-kV contact, ±15-kV Air Gap IEC61000-4-2 level 4C
Package
40-pin QFN
Integrated Digital Blocks
4x TCPWM9
4x SCB
(I2C, SPI, UART)
Crypto Engine
I/O Subsystem
Programmable
I/O Matrix
MCU Subsystem
Features
CC
24x GPIO
Ports
USB PD Subsystem
Baseband MAC
Baseband PHY
20-V Regulator
2x VCONN FETs
Overcurrent
Protection
2x 20V VBUS FET
Gate Drivers
System Resources
Overvoltage
Protection
Integrated Resistors
(RP, RD, RA)10
Full-Speed USB
Billboard Controller
4:2 Analog
Cross-Bar Switch
8-bit SAR ADC
SRAM
(8KB)
Availability
CCG3 Datasheet
Samples: Industrial (Now)
1
6
2
7
Mode of operation in which the data lines are repurposed to transmit non-USB data
The encryption hardware and software required to implement USB Authentication
3 A USB-IF specification that defines the authentication protocol for Type-C accessories
4 Serial communication block configurable as UART, SPI or I2C
5 A USB Device controller that informs the USB Host of the supported alternate modes
Document No. 001-89435 Rev. *P
Production: Industrial (Now)
A specification that defines the method for a USB device to communicate the supported alternate modes
Overvoltage protection, overcurrent protection
8 Circuits to control the gates of external power field-effect transistors (FETs) on V
BUS (5–20 V)
9 Timer/counter/pulse-width modulator block
10 Termination resistors: R read as a DFP, R as a UFP, R as an EMCA
P
D
P
194
Automotive CCG4
USB Type-C and PD Port Controller
Applications
Block Diagram
Automotive infotainment
Features
CCG4/4M: Two-Port Type-C Controller with Power Delivery
SRAM
(8KB)
16
4x SCB3
32
32
Type-C
Baseband
Transceiver
Type-C
Baseband
Transceiver
CC
CC
2x VCONN
FETs
2
4x 8-bit
SAR ADC
4
4x
TCPWM
4
24
GPIOs
2x VCONN
FETs
To
EC7
24
SS_
USB
+
DP
USB/DP
Mux
(CCG4M)
2
8
2
12
Type-C
Port 2
Type-C
Port 1
Samples: Industrial (Now)
Datasheet: CCG4 Datasheet
1 Termination
3
2
4 An
Document No. 001-89435 Rev. *P
Flash
(128KB)
SS_USB
+ DP
2
AUX
SBU
Availability
Collateral
resistor read as a DFP
Termination resistor read as a UFP
Cortex®-M0
48 MHz
Programmable I/O Matrix
Integrated USB Type-C Transceivers Support Two Type-C Ports
Integrated 2x 1-W VCONN FETs and 2x FET control signals, per
port programmable RP1 and removable RP, and RD2 terminations
Supports dead battery mode operation
Integrated SuperSpeed USB/DisplayPort (DP) Mux (CCG4M)
Increased Flash Enables Fail-Safe Bootup
Integrates 128KB flash to store dual FW images for Fail-Safe Boot
Integrated Digital Blocks for Inter-Chip Communications
Four SCBs3 master or slave configurable to I2C, SPI or UART
SCBs interconnect CCG4 with embedded controller,
two alternate muxes and Thunderbolt4 controller (optional)
Integrated Blocks for OVP5 and OCP6
Four 8-bit SAR ADCs configurable for OVP and OCP
Low-Power Operation
2.7–5.5-V operation and independent supply voltage for general
purpose input/output (GPIO) Sleep: 2.0 mA; Deep Sleep: 2.5 µA
with wake-on-I2C or wake-on-configuration channel (CC)
System-Level ESD on CC Pins
±8-kV contact, ±15-kV Air Gap IEC61000-4-2 level 4C
32-bit ARM® Cortex®-M0 CPU with MCU Subsystem
128KB Flash, upgradable over CC lines or I2C interface
Packages
40-pin QFN
I2C
Serial communication block configurable as UART, SPI or
interface jointly defined by intel and Apple that connects peripherals to a computer
5
6
Production: Industrial (Now)
Overvoltage protection
Overcurrent protection
7
Embedded controller in a PC
195
Automotive USB Packages
Package
Pins
Body Size
TQFP
BGA
QFN
100
100
24
40
14 x 14 mm
6 x 6 mm
4 x 4 mm
6 x 6 mm
0.5 mm
0.5 mm
0.5 mm
0.5 mm
Functionality
Family
Pitch
Hub
HX3
CYUSB33XX
Host
EZ-Host
CY7C67300
Type-C
CCG2
CYPD219X
CCG3
CYPD319X

CCG4
CYPD429X

Document No. 001-89435 Rev. *P



196
Traveo Instrument Cluster MCU Family Roadmap
Document No. 001-89435 Rev. *P
197
Feature Overview
Traveo Instrument Cluster MCU Family
QPRC1
I/O Timer2
Source Clock
Timer
External NMI /
External IRQ5
IRQ
DMA6
Standard I/O
Relocation
Watchdog
CSV7
Oscillators
PLLs
SSCG PLL8
Power Mgmt.
Temp. Sensor9
Flash
D-Cache
Work-Flash
I-Cache
RAM
PPU13
TPU14
Reload Timer
Boot ROM
RTC3
OCD (JTAG)
Trace10
Cortex® R5F
FPU, Safety, Security
Sound Gen
LVD11
CRC12
eSHE
Wave Gen x5
Mixer
SMC + ZPD4
TCON15
3D Engine
Base Timer
VRAM
12-bit ADC
Command
Sequence
Video In
Dithering
Gamma16
Vector
Drawing
2D Engine
Signature
Unit
Video Out /
LCD Bus
HyperBus™
3-Pin MLB17
4-bit
DDR HSSPI18
APIX AIC19
Multifunctional
Serial
CAN FD
Ethernet AVB20
PCM/PWM21
Audio-DAC
I2S22
4COM x 32SEG
LCDC
EBI23
1
8
15
2
9
16
Quad position and revolution counter
Input/output timer
3 Real-time clock
4 Stepper motor control + zero point detection
5 Nonmaskable interrupt/interrupt request
6 Direct memory access
7 Clock supervisor
Document No. 001-89435 Rev. *P
Spread-spectrum clock generator/phase-locked loop
Power management, temperature sensor
10 On-chip debug (Joint Test Action Group)
11 Low-voltage detection
12 Cyclic redundancy check
13 Peripheral protection units
14 Timing protection unit
Timing controller
Dithering and gamma correction
17 Media local bus
18 Double-data-rate high-speed serial peripheral
interface
19 Automotive pixel link/automatic interconnect
20 Audio/video bridging
21
Pulse-code modulation/pulse-width
modulation
22 Inter-IC sound bus
23 External bus interface
198
S6J3120 Series
Traveo Instrument Cluster MCU Family: Virgo
Applications
Block Diagram1
Instrument clusters
2-ch QPRC
Features
32-bit MCU Core Systems
128-MHz ARM® Cortex®-R5, up to 1MB Flash and
88KB RAM with backup RAM
Supply Voltage
5.0 V
Interfaces
3-ch CAN FD, DDR HSSPI, 10-ch multifunctional serial
Cluster Features
4COM x 32SEG LCDC and 3-ch sound generator
Package
144-pin TEQFP
12-ch
I/O Timer
10-ch Reload
Timer
3-ch Source
Clock Timer
External NMI /
16 External IRQ
IRQ
16-ch DMA
Standard I/O
Relocation
Watchdog
CSV
Oscillators
PLLs
SSCG PLL
Power
Management
Flash
D-Cache
Work-Flash
I-Cache
RAM
PPU
TPU
Boot ROM
RTC
OCD (JTAG)
Trace
Sound Gen
LVD
Datasheet:
S6J3120 Series
Hardware Manual: S6J3120 Series
1
CRC
eSHE
Wave Gen
Mixer
4-ch SMC ZPD
TCON
3D Engine
30-ch Base
Timer
VRAM
28-ch + 22-ch
12-bit ADC
Command
Sequencer
Video In
Dithering
Gamma
2D Engine
Vector
Drawing
Signature Unit
Video Out
HyperBus™
3-Pin MLB
1-ch 4-bit
DDR HSSPI
APIX AIC
10-ch Multifunctional
Serial
3-ch CAN FD
Ethernet AVB
PCM/PWM
Audio-DAC
I2S
4COM x 32SEG
LCDC
EBI
Collateral
Cortex® R5, 128 MHz
Safety, Security
Availability
Sampling:
Production:
Now
Q1 2017
Blue boxes highlighted in block diagram indicate features available on the device shown. Gray boxes indicate omitted features
Document No. 001-89435 Rev. *P
199
S6J3200 Series
Traveo Instrument Cluster MCU Family: Amber-I (S6J323/4/7x)
Applications
Block Diagram7
Instrument clusters, head-up displays (HUDs), HVACs
2-ch QPRC
Features
32-bit MCU Core Systems
Up to 240-MHz ARM® Cortex®-R5F, 2MB Flash,
272KB RAM with backup RAM and 2MB VRAM
Supply Voltages
1.2 V, 3.3 V and 5.0 V
Interfaces
4-ch CAN FD, 1-ch DDR HSSPI, 2-ch HyperBus™1,
12-ch multifunctional serial, MLB2, Ethernet AVB3
Cluster Features
2D engine, 2-ch (maximum) video-out/1-ch (maximum)
video-in, audio-DAC, PCM/PWM4 and I2S5
Packages
208-pin TEQFP, 216-pin TEQFP and 256-pin TEQFP6
Collateral
Datasheet:
S6J3200 Series
Hardware Manual: S6J3200 Series
1 Cypress’s high-bandwidth, 12-signal interface that transfers data over 8 I/O
signals at double data rate (DDR), delivering 333 MBps
2 Media local bus
3 Audio/video bridging
4 Pulse-code modulation/pulse-width modulation
5 Inter-IC sound bus
6 Contact Sales for 256-pin TEQFP availability
7 Blue boxes highlighted in the block diagram indicate features available on the
device shown. Gray boxes indicate omitted features.
Document No. 001-89435 Rev. *P
24-ch
I/O Timer
14-ch Reload
Timer
4-ch Source
Clock Timer
External NMI /
16 External IRQ
IRQ
16-ch DMA
Standard I/O
Relocation
Watchdog
CSV
Oscillators
PLLs
SSCG PLL
Power
Management
Flash
2MB
D-Cache
16KB
Work-Flash
112KB
I-Cache
16KB
RAM
272KB
PPU
TPU
TCON
1-ch
1-ch Video In
Boot ROM
RTC
OCD (JTAG)
Trace
Cortex® R5, 240 MHz
FPU, Safety, Security
Sound Gen
LVD
CRC
eSHE
Wave Gen x5
Mixer*
6-ch SMC ZPD
3D Engine
24-ch Base
Timer
VRAM
2MB
50-ch 12-bit
ADC
Command
Sequencer
Dithering
Gamma
2D Engine
Vector
Drawing
Signature Unit
Display Ctrl
RSDS/RGB
2-ch (MUXed)
2-ch HyperBus™*
1-ch 3-Pin MLB
1-ch 4-bit x2
DDR HSSPI
APIX AIC
12-ch Multifunctional
Serial
4-ch CAN FD
1-ch Ethernet AVB
1-ch PCM/PWM*
Audio-DAC*
2-ch I2S*
4COM x 32SEG
LCDC
EBI
*optional for some devices
Availability
Sampling:
Production:
Now
Q2 2017
200
S6J3200 Series
Traveo Instrument Cluster MCU Family: Amber-P (S6J325/6/8x)
Applications
Block Diagram7
Instrument clusters, head-up displays (HUDs), HVACs
2-ch QPRC
Features
32-bit MCU Core Systems
Up to 240-MHz ARM® Cortex®-R5F, 2MB Flash,
272KB RAM with backup RAM and 2MB VRAM
Supply Voltages
1.2 V, 3.3 V and 5.0 V
Interfaces
4-ch CAN FD, 1-ch DDR HSSPI, 2-ch HyperBus™1,
12-ch multifunctional serial, MLB2, Ethernet AVB3
Cluster Features
3D OpenGL ES1.1 on-the-fly, 2D engine,
2-ch (maximum) video-out/1-ch (maximum) video-in,
audio-DAC, PCM/PWM4 and I2S5
Packages
208-pin TEQFP, 216-pin TEQFP and 256-pin TEQFP6
Collateral
Datasheet:
S6J3200 Series
Hardware Manual: S6J3200 Series
1 Cypress’s high-bandwidth, 12-signal interface that transfers data over 8 I/O
signals at double data rate (DDR), delivering 333 MBps
2 Media local bus
3 Audio/video bridging
4 Pulse-code modulation/pulse-width modulation
5 Inter-IC sound bus
6 Contact Sales for 256-pin TEQFP availability
7 Blue boxes highlighted in the block diagram indicate features available on the
device shown. Gray boxes indicate omitted features.
Document No. 001-89435 Rev. *P
24-ch
I/O Timer
14-ch Reload
Timer
4-ch Source
Clock Timer
External NMI /
16 External IRQ
IRQ
16-ch DMA
Standard I/O
Relocation
Watchdog
CSV
Oscillators
PLLs
SSCG PLL
Power
Management
Flash
2MB
D-Cache
16KB
Work-Flash
112KB
I-Cache
16KB
RAM
272KB
PPU
TPU
TCON
1-ch
1-ch Video In
Boot ROM
RTC
OCD (JTAG)
Trace
Cortex® R5, 240 MHz
FPU, Safety, Security
Sound Gen
LVD
CRC
eSHE
Wave Gen x5
Mixer*
6-ch SMC ZPD
3D Engine
24-ch Base
Timer
VRAM
2MB
50-ch 12-bit
ADC
Command
Sequencer
Dithering
Gamma
2D Engine
Vector
Drawing
Signature Unit
Display Ctrl
LVDS*/RSDS/RGB
2-ch (MUXed)
2-ch HyperBus™*
1-ch 3-Pin MLB
1-ch 4-bit x2
DDR HSSPI
APIX AIC
12-ch Multifunctional
Serial
4-ch CAN FD
1-ch Ethernet AVB
1-ch PCM/PWM*
Audio-DAC*
2-ch I2S*
4COM x 32SEG
LCDC
EBI
*optional for some devices
Availability
Sampling:
Production:
Now
Q2 2017
201
S6J3200 Series
Traveo Instrument Cluster MCU Family: Amethyst-I (S6J32A/Bx)
Applications
Block Diagram4
Instrument clusters, head-up displays (HUDs), HVACs
2-ch QPRC
Features
32-bit MCU Core Systems
Up to 160-MHz ARM® Cortex®-R5F, 1MB Flash,
208KB RAM with backup RAM and 1MB VRAM
Supply Voltages
1.2 V, 3.3 V and 5.0 V
Interfaces
4-ch CAN FD, 1-ch DDR HSSPI, 1-ch HyperBus™1,
12-ch multifunctional serial
Cluster Features
2D engine, 1-ch video-out, audio-DAC,
PCM/PWM2 and I2S3
Packages
208-pin TEQFP and 216-pin TEQFP
Collateral
Datasheet:
S6J3200 Series
Hardware Manual: S6J3200 Series
24-ch
I/O Timer
14-ch Reload
Timer
4-ch Source
Clock Timer
External NMI /
16 External IRQ
IRQ
16-ch DMA
Standard I/O
Relocation
Watchdog
CSV
Oscillators
PLLs
SSCG PLL
Power
Management
Flash
1MB
D-Cache
16KB
Work-Flash
112KB
I-Cache
16KB
RAM
208KB
PPU
TPU
TCON
1-ch
Video In
Boot ROM
RTC
OCD (JTAG)
Trace
Cortex® R5, 160 MHz
FPU, Safety, Security
Sound Gen
LVD
CRC
eSHE
Wave Gen x5
Mixer*
6-ch SMC ZPD
3D Engine
24-ch Base
Timer
VRAM
1MB
50-ch 12-bit
ADC
Command
Sequencer
Dithering
Gamma
2D Engine
Vector
Drawing
Signature Unit
Display Ctrl
RSDS/RGB
1-ch (MUXed)
1-ch HyperBus™
3-Pin MLB
1-ch 4-bit x2
DDR HSSPI
APIX AIC
12-ch Multifunctional
Serial
4-ch CAN FD
Ethernet AVB
1-ch PCM/PWM*
16-bit Audio-DAC*
2-ch I2S*
4COM x 32SEG
LCDC
EBI
*optional for some devices
Availability
1 Cypress’s high-bandwidth, 12-signal interface that transfers data over 8 I/O
signals at double data rate (DDR), delivering 333 MBps
2 Pulse-code modulation/pulse-width modulation
3 Inter-IC sound bus
4 Blue boxes highlighted in the block diagram indicate features available on the
device shown. Gray boxes indicate omitted features.
Document No. 001-89435 Rev. *P
Sampling:
Production:
Now
Q4 2017
202
S6J3200 Series
Traveo Instrument Cluster MCU Family: Amethyst-P (S6J32C/Dx)
Applications
Block Diagram4
Instrument clusters, head-up displays (HUDs), HVACs
2-ch QPRC
Features
32-bit MCU Core Systems
Up to 160-MHz ARM® Cortex®-R5F, 1MB Flash,
208KB RAM with backup RAM and 1MB VRAM
Supply Voltages
1.2 V, 3.3 V and 5.0 V
Interfaces
4-ch CAN FD, 1-ch DDR HSSPI, 1-ch HyperBus™1,
12-ch multifunctional serial
Cluster Features
3D OpenGL ES1.1 on-the-fly, 2D engine,
1-ch video-out, audio-DAC, PCM/PWM2 and I2S3
Packages
208-pin TEQFP and 216-pin TEQFP
Collateral
Datasheet:
S6J3200 Series
Hardware Manual: S6J3200 Series
24-ch
I/O Timer
14-ch Reload
Timer
4-ch Source
Clock Timer
External NMI /
16 External IRQ
IRQ
16-ch DMA
Standard I/O
Relocation
Watchdog
CSV
Oscillators
PLLs
SSCG PLL
Power
Management
Flash
1MB
D-Cache
16KB
Work-Flash
112KB
I-Cache
16KB
RAM
208KB
PPU
TPU
TCON
1-ch
Video In
Boot ROM
RTC
OCD (JTAG)
Trace
Cortex® R5, 160 MHz
FPU, Safety, Security
Sound Gen
LVD
CRC
eSHE
Wave Gen x5
Mixer*
6-ch SMC ZPD
3D Engine
24-ch Base
Timer
VRAM
1MB
50-ch 12-bit
ADC
Command
Sequencer
Dithering
Gamma
2D Engine
Vector
Drawing
Signature Unit
Display Ctrl
RSDS/RGB
1-ch (MUXed)
1-ch HyperBus™
3-Pin MLB
1-ch 4-bit x2
DDR HSSPI
APIX AIC
12-ch Multifunctional
Serial
4-ch CAN FD
Ethernet AVB
1-ch PCM/PWM*
16-bit Audio-DAC*
2-ch I2S*
4COM x 32SEG
LCDC
EBI
*optional for some devices
Availability
1 Cypress’s high-bandwidth, 12-signal interface that transfers data over 8 I/O
signals at double data rate (DDR), delivering 333 MBps
2 Pulse-code modulation/pulse-width modulation
3 Inter-IC sound bus
4 Blue boxes highlighted in the block diagram indicate features available on the
device shown. Gray boxes indicate omitted features.
Document No. 001-89435 Rev. *P
Sampling:
Production:
Now
Q4 2017
203
S6J3200 Series
Traveo Instrument Cluster MCU Family: Amber-I4L (S6J32E/F/Gx)
Applications
Block Diagram7
Instrument clusters, head-up displays (HUDs)
2-ch QPRC
Features
32-bit MCU Core Systems
240-MHz ARM® Cortex®-R5F, 4MB Flash, 512KB RAM,
16KB backup RAM and 2MB VRAM
Supply Voltages
1.2 V, 3.3 V and 5 V
Interfaces
4-ch CAN FD, 2-ch DDR HSSPI, 2-ch HyperBus™1,
MLB2, 12-ch multifunctional serial and Ethernet AVB3
Cluster Features
2D engine, audio-DAC, PCM/PWM4, I2S5 and
2-ch (maximum) video-out/1-ch (maximum)
video-in (including 1-ch LVDS input)
Packages
208-pin TEQFP, 216-pin TEQFP and 256-pin TEQFP6
Collateral
Datasheet:
S6J3200 Series
Hardware Manual: S6J3200 Series
1 Cypress’s high-bandwidth, 12-signal interface that transfers data over 8 I/O
signals at double data rate (DDR), delivering 333 MBps
2 Media local bus
3 Audio/video bridging
4 Pulse-code modulation/pulse-width modulation
5 Inter-IC sound bus
6 Contact Sales for 256-pin TEQFP availability
7 Blue boxes highlighted in the block diagram indicate features available on the
device shown. Gray boxes indicate omitted features.
Document No. 001-89435 Rev. *P
24-ch
I/O Timer
10-ch Reload
Timer
4-ch Source
Clock Timer
External NMI /
24 External IRQ
IRQ
16-ch DMA
Standard I/O
Relocation
Watchdog
CSV
Oscillators
PLLs
SSCG PLL
Power
Management
Flash
4MB
D-Cache
16KB
Work-Flash
112KB
I-Cache
16KB
RAM
528KB
PPU
TPU
Boot ROM
RTC
OCD (JTAG)
Trace
Cortex® R5, 240 MHz
FPU, Safety, Security
Sound Gen
LVD
CRC
eSHE
Wave Gen x5
Mixer*
6-ch SMC ZPD
TCON
3D Engine
24-ch Base
Timer
VRAM
2MB
50-ch 12-bit
ADC
Command
Sequencer
1-ch Video In
Dithering
Gamma
2D Engine
Vector
Drawing
Signature Unit
Display Ctrl
LVDS/RSDS/RGB
2-ch (MUXed)
2-ch HyperBus™*
1-ch 3-Pin MLB
2-ch 4-bit x2
DDR HSSPI
APIX AIC
12-ch Multifunctional
Serial
4-ch CAN FD
1-ch Ethernet AVB
1-ch PCM/PWM*
Audio-DAC*
2-ch I2S*
4COM x 32SEG
LCDC
EBI
*optional for some devices
Availability
Sampling:
Production:
Now
Now
204
S6J3300 Series
Traveo Instrument Cluster MCU Family: Juno (4MB)/Artemis (2MB) (S6J331/2/3/4x)
Applications
Block Diagram8
Instrument clusters, vehicle controllers
Features
32-bit MCU Core Systems
240-MHz ARM® Cortex®-R5F, up to 4MB Flash and
544KB RAM with backup RAM
Supply Voltages
1.15V, 3.3V or 5.0V
Interfaces
6-ch CAN FD, 1-ch DDR HSSPI, 1-ch HyperBus™1, MLB2,
12-ch multifunctional serial, EBI3, APIX AIC4 and
Ethernet AVB4
Cluster Features
Simple video out and LCD-bus interface, audio-DAC,
PCM/PWM6 and I2S7
Packages
144-pin TEQFP, 176-pin TEQFP, 208-pin TEQFP
2-ch QPRC
12-ch
I/O Timer
6-ch Reload
Timer
4-ch Source
Clock Timer
External NMI /
24 External IRQ
IRQ
16-ch DMA
Standard I/O
Relocation
Watchdog
CSV
Oscillators
PLLs
SSCG PLL
Power
Management
Flash
D-Cache
16KB
Work-Flash
112KB
I-Cache
16KB
RAM
544KB
PPU
TPU
Boot ROM
RTC
Cortex® R5, 240 MHz
FPU, Safety, Security
OCD (JTAG)
Trace
Sound Gen
LVD
CRC
eSHE
Wave Gen x5
Mixer*
6-ch SMC ZPD
TCON
3D Engine
32-ch Base
Timer
VRAM
32 + 16-ch
12-bit ADC
Command
Sequencer
Video In
Dithering
Gamma
2D Engine
Vector
Drawing
Signature Unit
LCD Bus
Video-Out
1-ch HyperBus™
1-ch 3-Pin MLB*
1-ch 4-bit x2
DDR HSSPI
APIX AIC*
12-ch Multifunctional
Serial
6-ch CAN FD
1-ch Ethernet
AVB*
1-ch PCM/PWM*
Audio-DAC
2-ch I2S*
Collateral
Datasheet:
S6J331x Series
Hardware Manual: S6J3300 Series
4COM x 32SEG
LCDC
EBI
*optional for some devices
1
Cypress’s high-bandwidth, 12-signal interface that transfers data over 8 I/O
signals at double data rate (DDR), delivering 333 MBps
2 Media local bus
3 External bus interface
4 Automotive pixel link/automatic interconnect
5 Audio/video bridging
6 Pulse-code modulation/pulse-width modulation
7 Inter-IC sound bus
8 Blue boxes highlighted in the block diagram indicate features available on the
device shown. Gray boxes indicate omitted features.
Document No. 001-89435 Rev. *P
Availability
Juno
Artemis
Sampling:
Production:
Sampling:
Production:
Now
Q2 2017
Now
Q2 2017
205
Traveo Body Control MCUs Family
Document No. 001-89435 Rev. *P
206
Feature Overview
Traveo Body Control MCU Family
QPRC1
I/O Timer2
Source Clock
Timer
External NMI /
External IRQ4
Partial
Wakeup
DMA5
Standard I/O
Relocation
Watchdog
CSV6
Oscillators
PLLs
SSCG PLL7
Power
Management
Flash
D-Cache
Work-Flash
I-Cache
RAM
PPU11
TPU12
Reload Timer
Boot ROM
RTC3
OCD (JTAG)
Trace8
LVD9
Cortex® R5F
FPU, Safety, Security
CRC10
eSHE
4-bit x2 DDR
HSSPI13
HyperBus™
Base Timer
CAN FD
Ethernet AVB14
12-bit ADC
EBI15
FlexRay
1
6
11
2
7
12
Quad position and revolution counter
Input/output timer
3 Real-time clock
4 Nonmaskable interrupt/Interrupt request
5 Direct memory access
Document No. 001-89435 Rev. *P
Clock supervisor
Spread-spectrum clock generator/phase-locked loop
8 On-chip debug (Joint Test Action Group)
9 Low-voltage detection
10 Cyclic redundancy check
13
14
15
Multifunctional
Serial
Peripheral protection units
Timing protection unit
Double-data-rate high-speed serial peripheral interface
Audio/video bridging
External bus interface
207
S6J3110 Series
Traveo Body Control MCU Family: Leo (4MB) (S6J311B/C/D/Ex)
Applications
Body control modules (BCM), HVACs, gateways, lighting,
infotainment
Features
32-bit MCU Core System
144-MHz ARM® Cortex®-R5, up to 4MB Flash
and 384KB RAM with backup RAM
Supply Voltage
5.0 V
Interfaces
Up to 2-ch CAN FD and 22-ch multifunctional serial
AD Converter
Up to 64-ch (2 units)
Timers
Up to 12-ch I/O timer1 and 30-ch base timer
Packages
144-pin TEQFP and 176-pin TEQFP
Collateral
Datasheets:
S6J311B to S6J311E Series (Leo)
Hardware Manuals: S6J3110 Series
1
2
Block Diagram2
3-ch Source
Clock Timer
External NMI /
16 External IRQ
Partial
Wakeup
16-ch DMA
Standard I/O
Relocation
12-ch I/O Timer
Watchdog
CSV
Oscillators
PLLs
SSCG PLL
Power
Management
Flash
Reload Timer
Boot ROM
D-Cache
16KB
Work-Flash
112KB
1-ch RTC
OCD (JTAG)
Trace
I-Cache
16KB
RAM
PPU
TPU
QPRC
LVD
Cortex® R5, 144 MHz
Safety, Security
CRC
eSHE
HyperBus™
DDR HSSPI
30-ch Base
Timer
2-ch 192-msg
CAN FD
Ethernet AVB
32-ch x2
12-bit ADC
EBI
FlexRay
22-ch Multifunctional
Serial
Availability
Sampling:
Production:
Now
Q1 2017
Input/output timer
Blue boxes highlighted in block diagram indicate features available on the device shown. Gray boxes indicate omitted features
Document No. 001-89435 Rev. *P
208
S6J3110 Series
Traveo Body Control MCU Family: Aries (1MB) (S6J3118/9/Ax)
Applications
Body control modules (BCM), HVACs, gateways, lighting,
infotainment
Features
32-bit MCU Core System
96-MHz ARM® Cortex®-R5, up to 1MB Flash
and 88KB RAM with backup RAM
Supply Voltage
5.0 V
Interfaces
1-ch CAN FD and 4-ch multifunctional serial
AD Converter
56-ch (2 units)
Timers
Up to 12-ch I/O timer1 and 30-ch base timer
Packages
144-pin TEQFP
Collateral
Datasheets:
S6J3118 to S6J311A Series (Aries)
Hardware Manuals: S6J3110 Series
1
2
Block Diagram2
3-ch Source
Clock Timer
External NMI/
16 External IRQ
Partial
Wakeup
16-ch DMA
Standard I/O
Relocation
12-ch I/O Timer
Watchdog
CSV
Oscillators
PLLs
SSCG PLL
Power
Management
Flash
Reload Timer
Boot ROM
D-Cache
16KB
Work-Flash
48KB
1-ch RTC
OCD (JTAG)
Trace
I-Cache
16KB
RAM
PPU
TPU
QPRC
LVD
Cortex® R5, 96MHz
Safety, Security
CRC
eSHE
HyperBus™
DDR HSSPI
30-ch Base
Timer
1-ch 192-msg
CAN FD
Ethernet AVB
31-ch+25-ch
12-bit ADC
EBI
FlexRay
4-ch Multifunctional
Serial
Availability
Sampling:
Production:
Now
Q1 2017
Input/output timer
Blue boxes highlighted in block diagram indicate features available on the device shown. Gray boxes indicate omitted features
Document No. 001-89435 Rev. *P
209
S6J3350 Series
Traveo Body Control MCU Family: Neptune (S6J335B/C/D/Ex)
Block Diagram5
Applications
Body control modules (BCM), gateways
2-ch QPRC
Features
12-ch I/O Timer
32-bit MCU Core Systems
240-MHz ARM® Cortex®-R5F, up to 4MB Flash and
544KB RAM with backup RAM
Supply Voltages
1.15 V, 3.3 V, or 5.0 V
Interfaces
Up to 8-ch CAN FD, up to 12-ch multifunctional serial,
Ethernet AVB1, HyperBus™2, 1-ch DDR HSSPI, EBI3
AD Converter
Up to 64-ch (2 units)
Timers
Up to 12-ch I/O timer4 and 64-ch base timer
Packages
144-pin TEQFP, 176-pin TEQFP and 208-pin TEQFP
External NMI /
24 External IRQ
Partial
Wakeup
16-ch DMA
Standard I/O
Relocation
Watchdog
CSV
Oscillators
PLLs
SSCG PLL
Power
Management
Flash
D-Cache
16KB
Work-Flash
112KB
I-Cache
16KB
RAM
PPU
TPU
6-ch Reload
Timer
GPIO
1-ch RTC
OCD (JTAG)
Trace
LVD
Cortex® R5, 240 MHz
FPU, Safety, Security
CRC
eSHE
1-ch
HyperBus™
1-ch 4-bit x2
DDR HSSPI
64-ch Base
Timer
8-ch 192-msg
CAN FD
1-ch
Ethernet AVB
32-ch x2
12-bit ADC
EBI
FlexRay
12-ch Multifunctional
Serial
Availability
Collateral
Datasheet:
Hardware Manual:
4-ch Source
Clock Timer
S6J3350 Series
S6J3350 Series
Sampling:
Production:
1
4
2
5
Audio/video bridging
Cypress’s high-bandwidth, 12-signal interface that transfers data over 8 I/O
signals at double data rate (DDR), delivering 333 MBps
3 External bus interface
Document No. 001-89435 Rev. *P
Now
Q2 2017
Input/output timer
Blue boxes highlighted in block diagram indicate features available on the device shown.
Gray boxes indicate omitted features
210
S6J3400 Series
Traveo Body Control MCU Family: Athena (S6J3428/9/Ax)
Block Diagram2
Applications
Body control modules (BCM), HVACs, gateways, lighting,
infotainment
Features
12-ch I/O Timer
32-bit MCU Core Systems
132-MHz ARM® Cortex®-R5F, up to 1MB Flash and
128KB RAM with backup RAM
Supply Voltages
3.3 V or 5.0 V
Interfaces
Up to 6-ch CAN FD and 14-ch multifunctional serial
AD Converter
Up to 64-ch (2 units)
Timers
Up to 12-ch I/O timer1 and 64-ch base timer
Packages
100-pin TEQFP/LQFP, 120-pin TEQFP/LQFP,
144-pin TEQFP/LQFP and 176-pin TEQFP/LQFP
1
2
4-ch Source
Clock Timer
External NMI /
32 External IRQ
Partial
Wakeup
16-ch DMA
Standard I/O
Relocation
Watchdog
CSV
Oscillators
PLLs
SSCG PLL
Power
Management
Flash
D-Cache
16KB
Work-Flash
112KB
I-Cache
16KB
RAM
PPU
TPU
6-ch Reload
Timer
GPIO
1-ch RTC
OCD (JTAG)
Trace
LVD
Cortex® R5, 132 MHz
FPU, Safety, Security
CRC
eSHE
HyperBus™
DDR HSSPI
64-ch Base
Timer
6-ch 128-msg
CAN FD
Ethernet AVB
32-ch x2
12-bit ADC
EBI
FlexRay
14-ch Multifunctional
Serial
Availability
Collateral
Datasheets:
Hardware Manual:
2-ch QPRC
S6J3400 Series
S6J3400 Series
Sampling:
Production:
Now
Q2 2017
Input/output timer
Blue boxes highlighted in block diagram indicate features available on the device shown. Gray boxes indicate omitted features
Document No. 001-89435 Rev. *P
211
Traveo MPN Selector Guides
Document No. 001-89435 Rev. *P
212
Product Selector Guide
S6J3110 Series (Leo/Aries), S6J3120 Series (Virgo)
Part Number
S6J311
S6J311
S6J312
Flash
1.5/2/3/4MB
512/768KB,1MB
512/768KB,1MB
RAM
128/192/256/320KB
48/64/80KB
48/64/80KB
SHE1
On/Off
On/Off
On/Off
Chip Erase
Controllable
Controllable
Controllable
Package
TEQFP-144/176
TEQFP-144
TEQFP-144
S6J310 Part Numbering Decoder
S6J 3 1 X X X X X X XX X XXX
Reserved
Packing:
0 = Tray
Packages: E2 = TQEFP 0.5-mm Pitch
Reliability:
S = GS Grade, E = ES Grade
Revision:
C
Option:
A = SHE On + Chip Erase (Controllable)2
B = SHE Off + Chip Erase (Controllable)
Pins:
H = 144, J = 176
Flash Size: 8 = 512KB, 9 = 768KB, A = 1MB, B = 1.5MB
C = 2MB, D = 3MB, E = 4MB
Function:
1 = Body, 2 = Cluster
Product ID: 1 = S6J310 Series
Core:
3 = R5
ID:
S6J = Cypress Automotive MCU
1 Secure
2
hardware extension
Chip erase can be constantly disabled via the chip erase enable register
Document No. 001-89435 Rev. *P
213
Product Selector Guide
S6J3350 Series (Neptune)
Part Number
S6J335
Flash
1.5/2/3/4MB
RAM
192/256/384/512KB
ETH1
Yes
SHE2
On/Off
Chip Erase
Enabled/Controllable
VCC / DVCC
5/5 V, 3/5 V, 3/3 V
Package
TEQFP-144/176/208
S6J3350 Part Numbering Decoder
S6J 3 3 5 X X X X X XX X XXX
Reserved
Packing:
0 = Tray
Packages:
C2 = TEQFP 0.4-mm Pitch, E2 = TEQFP 0.5-mm Pitch
Reliability:
S = GS Grade, E = ES Grade
Revision:
C
Option:
S = SHE On + Chip Erase (Enabled)
T = SHE On + Chip Erase (Controllable)3
U = SHE Off + Chip Erase (Enabled)
V = SHE Off + Chip Erase (Controllable)
S/U/T/V = VCC/DVCC: 5/5 V, A/C/E/G = VCC/DVCC: 3/5 V
B/D/F/H = VCC/DVCC: 3/3 V
Pins:
H = 144, J = 176, K = 208
Flash Size: B = 1.5MB, C = 2MB, D = 3MB, E = 4MB
Function:
5 = ETH
Product ID: 3 = S6J330 Series
1 Ethernet
2
audio/video bridging
Secure hardware extension
Document No. 001-89435 Rev. *P
3
Core:
3 = R5
ID:
S6J = Cypress Automotive MCU
Chip erase can be constantly disabled via the chip erase
enable register
214
Product Selector Guide
S6J3200 Series (Amber/Amethyst)
Part Number
S6J323
S6J324
S6J325
S6J326
S6J327
S6J328
S6J32A
S6J32B
S6J32C
S6J32D
Flash
2MB
2MB
2MB
2MB
2MB
2MB
1MB
1MB
1MB
1MB
RAM
256KB
256KB
256KB
256KB
256KB
256KB
192KB
192KB
192KB
192KB
VRAM
2MB
2MB
2MB
2MB
2MB
2MB
1MB
1MB
1MB
1MB
2D
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SS1
No
Yes
No
Yes
Yes
Yes
No
Yes
No
Yes
3D
No
No
Yes
Yes
No
Yes
No
No
Yes
Yes
LVDS2
No
No
No
Yes
No
Yes
No
No
No
No
2HB3
No
No
No
No
Yes
Yes
No
No
No
No
SHE4
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
Package
TEQFP-208/216/2565
TEQFP-208/216/2565
TEQFP-208/216/2565
TEQFP-208/216/2565
TEQFP-208/216/2565
TEQFP-208/216/2565
TEQFP-208/216
TEQFP-208/216
TEQFP-208/216
TEQFP-208/216
S6J3200 Part Numbering Decoder
S6J 3 2 X X X X X X XX X XXX
Reserved
Packing:
0 = Tray
Packages:
C2 = TEQFP 0.4-mm Pitch, E2 = TEQFP 0.5-mm Pitch
Reliability:
S = GS Grade, E = ES Grade
Revision:
H
Option:
S = SHE On, U = SHE Off
Pins:
K = 208, L = 216, M = 256
Flash Size: A = 1MB, C = 2MB
Function:
3 = 2D, 4 = 2D + SS, 5 = 2D + 3D, 6 = 2D + 3D + SS + LVDS,
7 = 2D + SS + 2HB, 8 = 2D + 3D + SS + LVDS + 2HB, A = 2D,
B = 2D + SS, B = 2D + SS, C = 2D, D = 2D + 3D + SS
Product ID: 2 = S6J320 Series
1 Sound
system
2 Low-voltage differential
signaling interface
3
Second HyperBus interface
4 Secure hardware extension
Document No. 001-89435 Rev. *P
5
Core:
3 = R5
ID:
S6J = Cypress Automotive MCU
Contact Sales for 256-pin
TEQFP availability
215
Product Selector Guide
S6J3200 Series (Amber-I4L)
Part Number
S6J32E
S6J32F
S6J32G
Flash
4MB
4MB
4MB
RAM
512KB
512KB
512KB
VRAM
2MB
2MB
2MB
2D
Yes
Yes
Yes
3D
No
No
No
SS1
No
Yes
Yes
LVDS2
Yes
Yes
Yes
2HB3
No
No
Yes
SHE4
On/Off
On/Off
On/Off
Chip Erase
Enabled/Controllable
Enabled/Controllable
Enabled/Controllable
Package
TEQFP-208/216/2565
TEQFP-208/216/2565
TEQFP-208/216/2565
S6J3200 Part Numbering Decoder
S6J 3 2 X X X X X X XX X XXX
Reserved
Packing:
0 = Tray
Packages:
C2 = TEQFP 0.4-mm Pitch, E2 = TEQFP 0.5-mm Pitch
Reliability:
S = GS Grade, E = ES Grade
Revision:
H
Option:
S = SHE On + Chip Erase (Enabled)
T = SHE On + Chip Erase (Controllable)6
U = SHE Off + Chip Erase (Enabled)
V = SHE Off + Chip Erase (Controllable)
K = 208, L = 216, M = 256
Pins:
Flash Size: E = 4MB
Function:
E = 2D + LVDS
F = 2D + SS + LVDS,
G = 2D + SS + LVDS + 2HB
Product ID: 2 = S6J320 Series
Core:
3 = R5
ID:
S6J = Cypress Automotive MCU
1 Sound
system
2 Low voltage differential signaling interface
3 Second HyperBus interface
4 Secure hardware extension
5 Contact Sales for 256-pin TEQFP availability
6 Chip erase can be constantly disabled via the chip erase enable register
Document No. 001-89435 Rev. *P
216
Automotive Flash Memory
Document No. 001-89435 Rev. *P
217
NOR Flash Memory Automotive Family
Decoder
S 29 G L 128 S
Document No. 001-89435 Rev. *P
Technology:
J = 110-nm Floating Gate (FG)
K = 90-nm FG
L = 65-nm FG
L = 65-nm FG
N = 110-nm MirrorBit ® (MB) 1 = 63-nm DRAM
P = 90-nm MB
S = 65-nm MB
T = 45-nm MB
Density:
008 = 8Mb
016 = 16Mb
032 = 32Mb
064 = 64Mb
128 = 128Mb
256 = 256Mb
512 = 512Mb 04G = 4Gb
01G = 1Gb
02G = 2Gb
Voltage:
D = 2.5 V
L = 3.0 V
S = 1.8 V
Family:
A = Standard ADP (Address-Data Parallel)
C = Burst Mode ADP (Address-Data Parallel)
F = Serial
G = Page Mode
J = Simultaneous Read/Write ADP (Address-Data Parallel)
K = HyperBus™
P = Page Mode Simultaneous Read/Write ADP (Address-Data Parallel)
Series:
25 = SPI
26 = HyperFlash™ 27 = HyperRAM™
29 = Parallel 70 = Stacked Die 79 = Dual Quad SPI
Prefix:
S
Product Selector Guide 218
Parallel NOR Flash Memory
Automotive Roadmap
Product Family
Density
S29GL-T
45-nm MB
3.0 V
2Gb1
1Gb
512Mb
S29GL-S
65-nm MB
3.0 V
2Gb1
1Gb
512Mb
256Mb
128Mb
64Mb
S29GL-N
110-nm MB
3.0 V
64Mb
32Mb
S29AS-J / S29AL-J
110-nm FG
1.8 V / 3.0 V
16Mb
8Mb
S29JL-J
110-nm FG
3.0 V
64Mb
32Mb
S29PL-J
110-nm FG
3.0 V
128Mb
64Mb
32Mb
1
S70 Series
Document No. 001-89435 Rev. *P
(Prod)
[EOL]
2017
Q1
Q2
Q3
2018
Q4
Q1
Q2
2019
Q3
Q4
Q1
Q2
Q3
2020
Q4
Q1
Q2
Q3
All parts supported by Longevity Program unless noted
Production
Concept
Samples
(STD)
2021
Q4
Q1
Q2
Production
(Auto)
Q3
Q4
EOL
219
Automotive Portfolio: Parallel NOR
S29GL-S2
65 nm, 3.0 V
S29GL-T2
45 nm, 3.0 V
Density
Initial / Page Access
* Temp Range
2Gb3
110 ns / 20 ns
* A and B
2Gb3
110 ns / 20 ns
* A and B
All parts supported by
Longevity Program
unless noted
1Gb
100 ns / 15 ns
* A and B
1Gb
100 ns / 15 ns
* A , B and M
512Mb
100 ns / 15 ns
* A and B
512Mb
100 ns / 15 ns
* A , B and M
≥256Mb
S29AS-J
110 nm, 1.8 V
S29AL-J
110 nm, 3.0 V
S29JL-J1
110 nm, 3.0 V
S29PL-J1,2
110 nm, 3.0 V
S29GL-N2
110 nm, 3.0 V
256Mb
90 ns / 15 ns
* A and B
≤32Mb
64–128Mb
128Mb
60 ns / 20 ns
* A
16Mb
70 ns / -* A
16Mb
55 ns / -* A and M
8Mb
70 ns / -* A
8Mb
55 ns / -* A and M
* A = Automotive, AEC-Q100 Grade 3: -40°C to +85°C
B = Automotive, AEC-Q100 Grade 2: -40°C to +105°C
M = Automotive, AEC-Q100 Grade 1: -40°C to +125°C
128Mb
90 ns / 15 ns
* A and B
64Mb
55 ns / -* A
64Mb
55 ns / 20 ns
* A
64Mb
90 ns / 25 ns
* A
32Mb
60 ns / -* A
32Mb
55 ns / 20 ns
* A
32Mb
90 ns / 25 ns
* A
1
Supports Simultaneous Read/Write Operation
Supports Page Mode
3 S70 series (stacked die)
2
Concept
Development
Sampling
Production
QQYY
QQYY
Industrial
Automotive
Availability
EOL (Last-Time-Ship)
Document No. 001-89435 Rev. *P
64Mb
70 ns / 15 ns
* A and B
QQYY
220
HyperFlash™ and HyperRAM™ NOR
Flash Memory Roadmap
Product Family
(Prod)
[EOL]
Density
S26KS-S / S26KL-S
65-nm MB1
1.8 V / 3.0 V
1Gb3
512Mb
256Mb
128Mb
(TBD)
S27KS-1
63-nm DRAM
1.8 V
256Mb3
128Mb3
64Mb
(TBD)
(Q1’17)
(Q1’17)
S27KL-1
63-nm DRAM
3.0 V
256Mb3
128Mb3
64Mb
(TBD)
(Q1’17)
1
>4KB Sector
2
4KB Sector
Document No. 001-89435 Rev. *P
3
S70 Series
2017
Q1
Q2
Q3
2018
Q4
Q1
Q2
2019
Q3
Q4
Q1
Q2
Q3
2020
Q4
Q1
Q2
Q3
All parts supported by Longevity Program unless noted
Production
Concept
Samples
(STD)
2021
Q4
Q1
Q2
Production
(Auto)
Q3
Q4
EOL
221
HyperFlash
S26KS-S1
65 nm 1.8 V
HyperFlash
S26KL-S1
65 nm 3.0 V
Density (Name)
SDR Clock / DDR Clock
* Temp Range
All parts supported by
Longevity Program
unless noted
1Gb4
96 ns / 166 MHz
Contact Sales
1Gb4
96 ns / 100 MHz
Contact Sales
512Mb
96 ns / 166 MHz
* A , B and M
512Mb
96 ns / 100 MHz
* A , B and M
256Mb
96 ns / 166 MHz
* A , B and M
128Mb
96 ns / 166 MHz
* A , B and M
HyperRAM
S27KS-12
63 nm, 1.8 V
HyperRAM
S27KL-12
63 nm, 3.0 V
256Mb
96 ns / 100 MHz
* A , B and M
256Mb4
36 ns / 166 MHz
Contact Sales
256Mb4
36 ns / 100 MHz
Contact Sales
128Mb
96 ns / 100 MHz
* A , B and M
128Mb4
36 ns / 166 MHz
Contact Sales
Q117
128Mb4
36 ns / 100 MHz
Contact Sales
Q117
64Mb
36 ns / 166 MHz
* A and B
64Mb
36 ns / 100 MHz
* A and B
≤32Mb
64–128Mb
≥256Mb
Automotive Portfolio: HyperFlash™,
HyperRAM™, & Burst Parallel NOR
* A = Automotive, AEC-Q100 Grade 3: -40°C to +85°C
B = Automotive, AEC-Q100 Grade 2: -40°C to +105°C
M = Automotive, AEC-Q100 Grade 1: -40°C to +125°C
T = Automotive, AEC-Q100 Grade 0: -40°C to +145°C
S29CD-J3
110 nm, 2.5 V
S29CL-J3
110 nm, 3.0 V
32Mb
54 ns / 75 MHz
* A , M and T
32Mb
54 ns / 75 MHz
* A , M and T
16Mb
54 ns / 66 MHz
* A , M and T
16Mb
54 ns / 66 MHz
* A , M and T
Q117
1 S26
= HyperFlash
= HyperRAM
3 ADP (Address Data Parallel) Burst
4 S70 series (stacked die)
2 S27
Concept
Availability
EOL (Last-Time-Ship)
Document No. 001-89435 Rev. *P
Development
Sampling
Production
QQYY
QQYY
Industrial
Automotive
QQYY
222
Serial NOR Flash Memory Automotive
Roadmap
Product Family
Density
S25FS-S / S25FL-S
65-nm MB1
1.8 V / 3.0 V
1Gb3
512Mb
256Mb
128Mb
64Mb4
S79FL-S
65-nm MB1
3.0 V
1Gb5
512Mb5
256Mb5
S25FL-P
90-nm MB1
3.0 V
256Mb3
128Mb
S25FL-P
90-nm MB1
3.0 V
64Mb
32Mb
S25FL-L
65-nm FG2
3.0 V
256Mb
128Mb
64Mb
S25FL1-K
90-nm FG2
3.0 V
64Mb
32Mb
16Mb
1 >4KB
Sector
2 4KB
Sector
3 S70
(Prod)
[EOL]
2017
Q1
Q2
Q3
2018
Q4
Q1
Q2
2019
Q3
Q4
Q1
Q2
Q3
2020
Q4
Q1
Q2
Q3
2021
Q4
Q1
Q2
Q3
Q4
[Q2’18]
[Q2’18]
(Q1’17)
(Q3’17)
(Q2’17)
Series
Document No. 001-89435 Rev. *P
4 1.8V
Only
5 S79
Dual Quad SPI
All parts supported by Longevity Program unless noted
Production
Concept
Samples
(STD)
Production
(Auto)
EOL
223
SPI NOR Flash Memory Automotive
Portfolio
S25FL1-K
90 nm, 3.0 V
Uniform Sector¹
S25FL-L
65 nm, 3.0 V
Uniform Sector¹
S25FL-P
90 nm, 3.0 V
Hybrid Sector¹
S25FL-S
65 nm, 3.0 V
Hybrid Sector¹
S79FL-S2
65 nm, 3.0 V
Hybrid Sector¹
S25FS-S
65 nm, 1.8 V
Hybrid Sector¹
1Gb3
133 MHz / 80 MHz
* A, B and M
1Gb
133 MHz / 80 MHz
* A and B
1Gb3
133 MHz / 80 MHz
* A, B and M
512Mb
133 MHz / 80 MHz
* A, B and M
512Mb
133 MHz / 80 MHz
* A and B
512Mb
133 MHz / 80 MHz
* A, B and M
256Mb
133 MHz / 80 MHz
* A and B
256Mb
133 MHz / 80 MHz
* A and B
Density (Name)
SDR Clock / DDR Clock
* Temp Range
≥256Mb
All parts supported by
Longevity Program
unless noted
Q317
128Mb
133 MHz / 66 MHz
* A, B and M
256Mb3
104 MHz / -*A
Q218
256Mb
133 MHz / 80 MHz
* A, B and M
Q217
64Mb
108 MHz / 54 MHz
* A, B and M
128Mb4
104 MHz / -* A and B
Q218
128Mb6
133 MHz / 80 MHz
* A, B and M
32Mb
108 MHz / -* A and B
128Mb5
104 MHz / -* A and B
Q218
128Mb7
108 MHz / -* A and B
16Mb
108 MHz / -* A and B
64Mb
104 MHz / -* A and B
64Mb
108 MHz / -* A and B
≤32Mb
64–128Mb
Q117
256Mb
133 MHz / 66 MHz
* A, B and M
128Mb
133 MHz / 80 MHz
* A and B
64Mb
133 MHz / 80 MHz
* A, B and M
32Mb
104 MHz / -* A and B
Concept
1
* A = Automotive, AEC-Q100 Grade 3: -40°C to +85°C
B = Automotive, AEC-Q100 Grade 2: -40°C to
+105°C
M = Automotive, AEC-Q100 Grade 1: -40°C to +125°C
Document No. 001-89435 Rev. *P
Logical sector size
S79 series, Dual Quad SPI (stacked die)
3 S70 series (stacked die)
4 S25FL129P Quad SPI
5 S25FL128P Dual SPI
6 S25FL128S 133-MHz SDR / 80-MHz DDR
7 S25FL127S 108-MHz SDR
2
Development
Sampling
Production
QQYY
QQYY
Industrial
Automotive
Availability
EOL (Last-Time-Ship)
QQYY
224
NAND Automotive Family Decoder
NAND
S 34 M L 08G 2
1 Multi-level
Technology: 1 = 4x-nm
2 = 32-nm
3 = 16-nm
Density:
01G = 1Gb
02G = 2Gb
04G = 4Gb
08G = 8Gb
16G = 16Gb
Voltage:
L = 3.0 V
S = 1.8 V
Family:
M = NAND (Address-Data Multiplexed)
Series:
34 = NAND
Prefix:
S
cell
Document No. 001-89435 Rev. *P
Product Selector Guide
225
SLC NAND Flash Memory Automotive
Roadmap
Product Family
Density
(Prod)
[EOL]
S34MS-1 / S34ML-1
4x-nm SLC, ONFI 1.0
1.8 V / 3.0 V
8Gb1
4Gb
2Gb
1Gb
S34MS-2 / S34ML-2
32-nm SLC, ONFI 1.0
1.8 V / 3.0 V
16Gb
8Gb
4Gb
2Gb
1Gb
S34SL-2
32-nm SLC, ONFI 1.0
3.0 V
4Gb
2Gb
1Gb
S34ML-3
16-nm SLC, ONFI 1.0
3.0 V
16Gb
8Gb
4Gb
2Gb
1Gb
(TBD)
(TBD)
(Q3’18)
(TBD)
(TBD)
S34MS-3
16-nm SLC, ONFI 1.0
1.8 V
16Gb
8Gb
4Gb
2Gb
1Gb
(TBD)
(TBD)
(Q1’19)
(TBD)
(TBD)
1
3.0V only
Document No. 001-89435 Rev. *P
2017
Q1
Q2
Q3
2018
Q4
Q1
Q2
2019
Q3
Q4
Q1
Q2
Q3
2020
Q4
Q1
Q2
Q3
2021
Q4
Q1
Q2
Q3
Q4
[Q4’18]
[Q4’18]
[Q4’18]
[Q4’18]
All parts supported by Longevity Program unless noted
Production
Concept
Samples
(STD)
Production
(Auto)
EOL
226
SLC NAND Automotive Portfolio
S34ML-11
4x nm, 3.0 V
SLC, ONFI 1.02
S34MS-11
4x nm, 1.8 V
SLC, ONFI 1.02
S34ML-23
32 nm, 3.0 V
SLC, ONFI 1.02
S34MS-23
32 nm, 1.8 V
SLC, ONFI 1.02
16Gb; x8
40 MBps
* I and V5
S34SL-23, 4
32 nm, 3.0 V
SLC, ONFI 1.02
S34ML-31
16 nm, 3.0 V
SLC, ONFI 1.02
S34MS-31
16 nm, 1.8 V
SLC, ONFI 1.02
16Gb; x8
40 MBps
* I and V5
16Gb; x8
40 MBps
* A and B
16Gb; x8
40 MBps
* A and B
8Gb; x8
40 MBps
* A and B
8Gb; x8
40 MBps
* A and B
8Gb; x8
40 MBps
* A and B
8Gb; x8
40 MBps
* A and B
8–16Gb
Density; Bus Width
Interface Bandwidth
* Temp Range
All parts supported by
Longevity Program
unless noted
1–4Gb
8Gb; x8
40 MBps
* A and B
4Gb; x8/16
40 MBps
* A and B
Q418
4Gb; x8
40 MBps
* A and B
Q418
4Gb; x8/16
40 MBps
* A and B
4Gb; x8/16
40 MBps
* A and B
4Gb; x8
40 MBps
* I, V
4Gb; x8
40 MBps
* A and B
2Gb; x8/16
40 MBps
* A and B
Q418
2Gb; x8/16
40 MBps
* A and B
Q418
2Gb; x8/16
40 MBps
* A and B
2Gb; x8/16
40 MBps
* I and V5
2Gb; x8
40 MBps
* I, V5
2Gb; x8
40 MBps
* A and B
2Gb; x8
40 MBps
* A and B
1Gb; x8
40 MBps
* A and B
Q418
1Gb; x8/16
40 MBps
* A and B
Q418
1Gb; x8/16
40 MBps
* A and B
1Gb; x8/16
40 MBps
* A and B
1Gb; x8
40 MBps
* I, V
1Gb; x8
40 MBps
* A and B
1Gb; x8
40 MBps
* A and B
* I = Industrial: -40°C to +85°C
A = Automotive, AEC-Q100 Grade 3: -40°C to +85°C
V = Industrial-plus: -40°C to +105°C
B = Automotive, AEC-Q100 Grade 2: -40°C to +105°C
Document No. 001-89435 Rev. *P
1 1-bit
Error-Correcting Code (ECC)
NAND Flash Interface
Industrial
3 4-bit Error-Correcting Code (ECC)
Automotive
4 SecureNAND™: Cypress’s SLC NAND Flash Memory with
Availability
full-capacity volatile and nonvolatile block protection
5 Contact Sales
EOL (Last-Time-Ship)
Concept
Q118
Development
4Gb; x8
40 MBps
* A and B
Sampling
Production
QQYY
QQYY
2 Open
QQYY
227
Flash and RAM Automotive MCP
Decoder
S 71 K S 512 R D
RAM Density:
A = 16Mb
Flash Technology:
S = 65-nm MirrorBit
Flash Density:
128 = 128Mb
256 = 256Mb
Voltage:
L = 3.0 V
S = 1.8 V
Family:
K = HyperFlash
Series:
71 = NOR Flash + pSRAM
Prefix:
S
Document No. 001-89435 Rev. *P
B = 32Mb
C = 64Mb
D = 128Mb
512 = 512Mb
01G = 1Gb
E = 256Mb
228
Flash and RAM MCP Flash Memory
Automotive Roadmap
Product Family
Flash / RAM
Flash / RAM (Prod)
Density
[EOL]
S71KS-S / S71KL-S
HyperFlash /
HyperRAM
1.8 V / 3.0 V
512Mb/64Mb (Q4’16)
256Mb/64Mb (TBD)
128Mb/64Mb (TBD)
2017
Q1
Q2
Q3
2018
Q4
Q1
Q2
2019
Q3
Q4
Q1
Q2
Q3
2020
Q4
Q1
Q2
Q3
All parts supported by Longevity Program unless noted
Production
Concept
Samples
(STD)
Document No. 001-89435 Rev. *P
2021
Q4
Q1
Q2
Production
(Auto)
Q3
Q4
EOL
229
Flash and RAM MCP Memory
Automotive Portfolio
S71KS-S¹
65nm, 1.8V
64–128Mb
≥256Mb
Flash Density
RAM Density
* Temp Range
S71KL-S¹
65nm, 3.0V
All parts supported by
Longevity Program
unless noted
512Mb
64Mb2
* A and B
512Mb
64Mb2
* A and B
Q416
256Mb
64Mb²
* A and B
256Mb
64Mb²
* A and B
Q217
128Mb
64Mb2
* A and B
128Mb
64Mb2
* A and B
* A = Automotive, AEC-Q100 Grade 3: -40°C to +85°C
B = Automotive, AEC-Q100 Grade 2: -40°C to
+105°C
1 HyperFlash
2 HyperRAM
Concept
Development
Sampling
Production
QQYY
QQYY
Industrial
Automotive
Availability
EOL (Last-Time-Ship)
Document No. 001-89435 Rev. *P
QQYY
230
Parallel NOR Flash Memory Packages
48-ball
FBGA
48-ball
FBGA
56-ball
BGA
64-ball
BGA
64-ball
Fortified BGA
(0.8-mm pitch)
(0.5-mm pitch)
(0.8-mm pitch)
(0.8-mm pitch)
(1.0-mm pitch)
48-pin
TSOP
56-pin
TSOP
Family
Density
Device
AS-J
8Mb
S29AS008J

16Mb
S29AS016J

8Mb
S29AL008J

16Mb
S29AL016J

32Mb
S29JL032J


64Mb
S29JL064J


32Mb
S29PL032J


64Mb
S29PL064J


128Mb
S29PL127J
32Mb
S29GL032N




64Mb
S29GL064N




64Mb
S29GL064S




128Mb
S29GL128S



256Mb
S29GL256S



512Mb
S29GL512S



1Gb
S29GL01GS


2Gb
S70GL02GS

512Mb
S29GL512T



1Gb
S29GL01GT



2Gb
S70GL02GT
AL-J
JL-J
PL-J
GL-N
GL-S
GL-T
Document No. 001-89435 Rev. *P









231
HyperFlash, HyperRAM, & Burst
Parallel NOR Packages
BGA24
8 x 6 mm
5 x 5 ball
80-ball
FBGA
(1.0-mm pitch)
80-pin
PQFP
KGD
Family
Density
Device
KS-S
128Mb
S26KS128S

CF
256Mb
S26KS256S

CF
512Mb
S26KS512S

CF
1Gb
S70KS01GS

128Mb
S26KL128S

CF
256Mb
S26KL256S

CF
512Mb
S26KL512S

CF
1Gb
S70KL01GS

64Mb
S26KS0641

128Mb
S26KS1281

256Mb
S70KS2561

64Mb
S26KL0641

128Mb
S26KL1281

256Mb
S70KL2561

16Mb
S29CD016J


32Mb
S29CD032J


16Mb
S29CL016J


32Mb
S29CL032J


KL-S
KS-1
KL-1
CD-J
CL-J
CF
CF

CF = Contact Factory
Document No. 001-89435 Rev. *P
232
SPI NOR Flash Memory Packages
Family
FL1-K
FL-L
FL-P
FL-S
FL-S
Dual
Quad
FS-S
Density
Device
16Mb
32Mb
64Mb
64Mb
128Mb
256Mb
32Mb
64Mb
128Mb
128Mb
256Mb
128Mb
128Mb
256Mb
512Mb
1Gb
256Mb
512Mb
1Gb
64Mb
128Mb
256Mb
512Mb
1Gb
S25FL116K
S25FL132K
S25FL164K
S25FL064L
S25FL128L
S25FL256L
S25FL032P
S25FL064P
S25FL128P
S25FL129P
S70FL256P
S25FL127S
S25FL128S
S25FL256S
S25FL512S
S70FL01GS
S79FL256S
S79FL512S
S79FL01GS
S25FS064S
S25FS128S
S25FS256S
S25FS512S
S70FS01GS
SOIC-8
150 mil
SOIC-8
208 mil





UD
UD




SOIC-16
300 mil

UD
UD













CF



USON
4 x 3 mm
WSON
4 x 4 mm
WSON
6 x 5 mm
CF
CF




UD
UD
WSON
8 x 6 mm
VSOP8
208 mil
UD









LGA (CF)
LGA (CF)

CF


BGA24
8 x 6 mm
5 x 5 Ball



UD
UD



BGA24
8 x 6 mm
4 x 6 Ball



UD
UD

















KGD



CF
CF
CF











CF

CF
CF = Contact Factory
UD = Under Development
Document No. 001-89435 Rev. *P
233
SLC NAND Packages
Family
ML-1
ML-2
ML-3
MS-1
MS-2
MS-3
Density
Device
1Gb
2Gb
4Gb
8Gb
1Gb
2Gb
4Gb
8Gb
16Gb
1Gb
2Gb
4Gb
8Gb
16Gb
1Gb
2Gb
4Gb
1Gb
2Gb
4Gb
8Gb
16Gb
1Gb
2Gb
4Gb
8Gb
16Gb
S34ML01G1
S34ML02G1
S34ML04G1
S34ML08G1
S34ML01G2
S34ML02G2
S34ML04G2
S34ML08G2
S34ML16G2
S34ML01G3
S34ML02G3
S34ML04G3
S34ML08G3
S34ML16G3
S34MS01G1
S34MS02G1
S34MS04G1
S34MS01G2
S34MS02G2
S34MS04G2
S34MS08G2
S34MS16G2
S34MS01G3
S34MS02G3
S34MS04G3
S34MS08G3
S34MS16G3
Document No. 001-89435 Rev. *P
63-Ball
BGA
(0.8-mm pitch)



























67-Ball
BGA
(0.8-mm pitch)




48-Pin
TSOP



















234
SecureNAND Packages
Family
SL-2
63-Ball
BGA
(0.8-mm pitch)
Density
Device
1Gb
S34SL01G2

2Gb
S34SL02G2

4Gb
S34SL04G2

Document No. 001-89435 Rev. *P
235
Flash and RAM MCP Memory Packages
Family
S71KS-S
S71KL-S
Flash
Density
RAM
Density
24-ball
FBGA
(1.0-mm pitch)
128Mb
64Mb

256Mb
64Mb

512Mb
64Mb

128Mb
64Mb

256Mb
64Mb

512Mb
64Mb

Document No. 001-89435 Rev. *P
236
Automotive Power Management IC
Document No. 001-89435 Rev. *P
237
Automotive PMIC Family Portfolio
Advanced Driver
Assistance Systems (ADAS)
Mid-Range
High-End
Instrument Cluster
CYBP221A
1xBuck Cnv1, DVS2, PG3
3.0-V to 5.5-V Input
6-A Output
NEW
Q417
S6BP211A
Pre-Boost+Buck Cnv
12-V VBAT4
3.3-V to 6.0-V/4 A Output
20-Pin TSSOP
CYBP221A
1xBuck Cnv, DVS, PG
3.0-V to 5.5-V Input
6-A Output
CYBP511A
Multi-SMPS5
3.0-V to 5.5-V Input
High Output Current
32-Pin Side-Wettable6 QFN
Q217
S6BP502A
3xSMPS
SSCG, PG
12-V VBAT, 2.0-A Output
32-Pin Side-Wettable QFN
S6BP202A
1xBuck-Boost Cnv, PG
12-V VBAT, 5-V/2.4-A Output
16-Pin TSSOP
Low-End
NEW
Q417
S6BP211A
Pre-Boost+Buck Cnv
12-V VBAT
3.3-V to 6.0-V/4-A Output
20-Pin TSSOP
S6BP202A
1xBuck-Boost Cnv, PG
12-V VBAT, 5-V/2.4-A Output
16-Pin TSSOP
S6BP203A
1xBuck-Boost Cnv, PG
12-V VBAT, 3.3-V/2.4-A Output
16-Pin TSSOP
CYBP411A
Multiple Power Supplies
WDT, I2C
3.3-V Input, High Output Current
48-Pin Side-Wettable QFN
S6BP201A
1xBuck-Boost Cnv3, PG
12-V VBAT, 5-V/1-A Output
16-Pin TSSOP
S6BP202A
1xBuck-Boost Cnv, PG
12-V VBAT, 5-V/2.4-A Output
16-Pin TSSOP
S6BP401A
4xSMPS, 2xLDO
WDT, PG
5-V Input, 3.0-A Output
40-Pin QFN
S6BP201A
1xBuck-Boost Cnv, PG
12-V VBAT, 5-V/1-A Output
16-Pin TSSOP
S6BP401A
4xSMPS, 2xLDO
WDT, PG
5-V Input, 3.0-A Output
40-Pin QFN
NEW
S6BP201A
1xBuck-Boost Cnv, PG
12-V VBAT, 5-V/1-A Output
16-Pin TSSOP
Q217
S6BP501A
3xSMPS
SSCG, PG
12-V VBAT, 1.4-A Output
32-Pin Side-Wettable QFN
NEW
CYBP411A
Multiple Power Supplies
WDT7, I2C
3.3-V Input, High Output Current
48-Pin Side-Wettable QFN
NEW
S6BP203A
1xBuck-Boost Cnv, PG
12-V VBAT, 3.3-V/2.4-A Output
16-Pin TSSOP
Body Control Module
Q217
S6BP502A
3xSMPS
SSCG8, PG
12-V VBAT, 2.0-A Output
32-Pin Side-Wettable QFN
NEW
Q217
S6BP501A
3xSMPS
SSCG, PG
12-V VBAT, 1.4-A Output
32-Pin Side-Wettable QFN
S6BP201A
1xBuck-Boost Cnv3, PG
12-V VBAT, 5-V/1-A Output
16-Pin TSSOP
Market Segment
1 Converter:
A general-purpose regulator IC that integrates power MOSFETs
2 Dynamic voltage scaling
3 Power good: An output signal that PMICs provide to signify that the supplied power by PMICs is proper and ready
4 Battery voltage
5 Switch-mode power supply: A general-purpose regulator IC that uses a switching circuit to up-convert and/or down-convert
a voltage source to a different voltage for powering other ICs
6 A package whose flanks are processed to improve soldering adherence and to simplify the optical inspection,
which follows soldering
7 Watchdog timer
8 Spread-spectrum clock generator
Document No. 001-89435 Rev. *P
Concept
Development
Sampling
Production
QQYY
QQYY
Industrial
Automotive
Availability
238
One-Channel Automotive PMIC
Automotive PMIC Family | S6BP20x
Applications
Instrument clusters, body control and ADAS
Features
1-Channel PMIC: Synchronous buck-boost converter
Wide Input Voltage Range: 2.5-42 V
Low Quiescent Current: 20 µA
Programmable Switching Frequency: 0.2-2.1 MHz
Synchronization with external clock from 200 kHz to 400 kHz
Autonomous PFM/PWM1 switching
BOM Integration: Built-in switching transistors
System Safety Function2 Support:
Undervoltage protection (UVP), overvoltage protection (OVP),
undervoltage locked-out (UVLO), thermal shutdown (TSD) and
overcurrent protection (OCP)
Voltage supervisor with independent power good (PG)3 pins
Operating Temperature Range: -40°C to +125°C
Package: 16-pin thermally enhanced TSSOP
Qualification: AEC-Q100 Grade-1
Collateral
Family Table
Output Voltage4
Max. Output Current
MPN
UVP/OVP Threshold
5.0-5.2 V
1.0 A
S6BP201A
±4.5%
5.0-5.2 V
2.4 A
S6BP202A
±4.5%, ±8.0%
3.3 V
2.4 A
S6BP203A
±8.0%
Block Diagram
Battery
2.5-42 V
Enable
5.0 V
S6BP20xA
5.0-V LDO,
Enable
Buck-Boost
DC/DC
Converter
2.1 MHz
PFM/PWM Switch
External Clock for
Synchronization
5.0 V or 3.3 V
Oscillator,
External
Sync
Frequency
Setting
Datasheets:
S6BP201A, S6BP202A and S6BP203A
Evaluation Kits: S6BP201A, S6BP202A and S6BP203A
Tool:
Easy DesignSim™
Protection
Function
PG Function
PG
GND
1
Pulse-frequency modulation/pulse-width modulation
A set of system functions that protect ECUs from damage and/or from generating erroneous
results during abnormal power supply conditions
3 An output signal that PMICs provide to signify that the supplied power by PMICs
is proper and ready
4 S6BP201A and S6BP202A have factory-selectable options of output voltage, power-on-reset
time, UVP/OVP threshold, and SYNC Function
2
Document No. 001-89435 Rev. *P
Availability
Samples: Now
Production: Now
239
Three-Channel Instrument Cluster Automotive PMIC
Automotive PMIC Family | S6BP50x
Applications
Low-end to mid-range hybrid automotive cluster systems
Family Table
Buck Converter
Output Specification4
Features
3-Channels:
Buck controller, boost converter, buck converter
Wide Range Input: 2.5-42 V
Low Quiescent Current: 15 µA
High Switching Frequency:
Boost converter and buck converter: 2.1 MHz
Built-in spread-spectrum clock generator (SSCG)
Synchronization with external clock from 1.8 to 2.4 MHz
System Safety Function1 Support:
Undervoltage protection (UVP), overvoltage protection (OVP),
undervoltage lock-out (UVLO), thermal shutdown (TSD) and
overcurrent protection (OCP)
Voltage supervisor with independent power good (PG)2 pins
Temperature supervisor with thermal warning feature
Operating Temperature Range: -40°C to +105°C
Package: 32-pin thermally enhanced side-wettable3 QFN
Qualification: AEC-Q100 Grade-2
MPN
Buck Controller
Output Specification
Boost Converter
Output Specification
1.15 V, 1.4 A
S6BP501A
3.3 V, 1.6 A
5.0 V, 1.3 A
1.2 V, 2.0 A
S6BP502A
3.3 V, 1.9 A
5.0 V, 1.3 A
Block Diagram
2.5-42 V
S6BP50x
Battery
Power
Sources
5.0 V
Boost
Converter
2.1 MHz
3.3 V
Enable SSCG
External Clock for
Synchronization
Enable
SSCG,
External
Sync
Enable,
LDO
Collateral
Preliminary Datasheet: S6BP501A/S6BP502A
Evaluation Kit:
Contact Sales
1
A set of system functions that protect ECUs from damage and/or from generating
erroneous results during abnormal power supply conditions
2 An output signal that PMICs provide to signify that the supplied power by PMICs is proper
and ready
3 A package whose flanks are processed to improve soldering adherence and to simplify the
optical inspection, which follows soldering
4 Output voltages are finely adjustable with external resistive dividers
Document No. 001-89435 Rev. *P
Buck
Controller
0.42 MHz
GND
Protection
Function
Bypass Switch
Buck
Converter
2.1 MHz
PG and
Thermal
Warning
1.2 V or 1.15 V
Thermal
Warning
PG
Availability
Samples: Now
Production: Q2 2017
240
Six-Channel ADAS Automotive PMIC
Automotive PMIC Family | S6BP401A
Block Diagram
Applications
2.5-42 V
Automotive advanced driver assistance systems (ADAS)
and security camera systems
S6BP202A
Automotive PMIC
Battery
5.0 V
Features
6-Channel PMIC: 4-channel buck converters, 2-channel LDOs
Input Voltage Range: 4.5-5.5 V
High Switching Frequency: 2.1 MHz
Synchronization with external clock from 1.8 to 2.4 MHz
BOM Integration:
Built-in switching transistors, LDO output transistors, voltage
setting resistors and compensation circuitry and discharge
resistors
System Safety Function1 Support:
Built-in windowed watchdog timer (WDT)
Voltage supervisor with independent power good (PG)2 pins
Independent enable pins
Overcurrent protection (OCP), overvoltage protection (OVP),
undervoltage locked-out (UVLO) and thermal shutdown (TSD)
Operating Temperature Range: -40°C to +125°C
Package: 40-pin thermally enhanced QFN
Qualification: AEC-Q100 Grade-1
S6BP401A
Enable for
6-Channel
6
1.8 V
External Clock for
Synchronization
Trigger
Input
Reset
Output
(Combined with
PG for LDO1)
GND
1.8V LDO,
Enable
Oscillator,
External
Sync
Windowed
Watchdog
Timer
Power Sources
Buck Converter
2.1 MHz (DC/DC 1)
1.200-1.575 V3
2.0 A
(MCU Core)
Buck Converter
2.1 MHz (DC/DC 2)
1.000-1.275 V3
3.0 A
(ISP Core)
Buck Converter
2.1 MHz (DC/DC 3)
1.200-2.575 V3
2.0 A
(DDR)
Buck Converter
2.1 MHz (DC/DC 4)
3.300-3.400 V3
1.0 A
(Flash Memory)
3.300-3.400 V3
0.2 A
(MCU I/O)
LDO 1
1.200-2.875 V3
0.5 A
(Camera Module)
LDO 2
Protection
Function
PG
5
PG for 5-Channel
(Except LDO1)
Collateral
Availability
Datasheet:
S6BP401A
Evaluation Kit: S6SBP401AM2SA1001
1A
set of system functions that protect ECUs from damage and/or from generating
erroneous results during abnormal power supply conditions
Document No. 001-89435 Rev. *P
Samples: Now
Production: Now
2 An
output signal that PMICs provide to signify that the supplied power by PMICs is
proper and ready
3 S6BP401A has factory-selectable options of output voltage for each channel
241
Automotive Wireless Portfolio
Document No. 001-89435 Rev. *P
242
Automotive Wireless Portfolio
Performance/Integration
Bluetooth (BR1 + EDR2)
IEEE 802.11a/b/g/n/ac WLAN3 + Bluetooth
Q117
BCM89359
Up to 867 Mbps, 802.11a/b/g/n/ac,
2x2 MIMO10 w/RSDB11, BT 4.2 BR + EDR + BLE,
GCI SECI, SDIO 3.0, PCIe, UART, USB, I2C,
SPI, HCI-over-UART, PCM/I2S, Security12,
20 GPIO, C1/C2,
Linux Driver
BCM89071
24-MHz ARM7TDMI-S4, SPI, UART, I2C,
I2S/PCM, GCI5 SECI6,
HCI7-over-UART/SPI,
8 GPIO, 112KB RAM,
BT8 4.1 BR + EDR, C1/C2/C39
BCM88335/BCM89359
Up to 433.3 Mbps, 802.11a/b/g/n/ac, SISO13,
BT4.1 BR + EDR + BLE, GCI SECI,
SDIO2.0/3.0,
SPI, HCI-over-UART, PCM/I2S, Security,
9 GPIO, C1/C2,
Linux Driver
BCM20713
24-MHz ARM7TDMI-S, SPI, UART, I2C,
I2S/PCM, GCI SECI, HCI-over-UART/SPI,
8 GPIO, 16KB RAM,
BT 4.0 BR + EDR, C1/C2/C3
Concept
Development
Sampling
Production
QQYY
QQYY
Status
Availability
1
6
11
2
7
12
Basic Rate
Enhanced Data Rate
3 Wireless Local Area Network
4 ARM 7 Family CPU
5 Global coexistence interface
Document No. 001-89435 Rev. *P
Serial-enhanced coexistence interface
Host controller interface
8 Bluetooth Specification
9 Class 1 (100 m)/2 (10 m)/3 (1 m)
10 Multiple-input multiple-output
Real Simultaneous Dual Band
WPA, WAPI STA, WPA2, AES, TKIP, Cisco
Compatible Extensions security features
13 Single-input single-output
243