Single Hot-Swap Power Controllers with Circuit

Single Hot-Swap Power Controllers with Circuit
TPS2330
TPS2331
www.ti.com
SLVS277G – MARCH 2000 – REVISED JULY 2013
SINGLE HOT-SWAP POWER CONTROLLERS WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
Check for Samples: TPS2330, TPS2331
FEATURES
1
•
•
•
•
•
•
•
•
•
•
Single-Channel High-Side MOSFET Driver
Input Voltage: 3 V to 13 V
Output dV/dt Control Limits Inrush Current
Circuit-Breaker With Programmable
Overcurrent Threshold and Transient Timer
Power-Good Reporting With Transient Filter
CMOS- and TTL-Compatible Enable Input
Low 5-μA Standby Supply Current (Max)
Available in 14-Pin SOIC and TSSOP Package
–40°C to 85°C Ambient Temperature Range
Electrostatic Discharge Protection
D OR PW PACKAGE
(TOP VIEW)
typical application
VO
+
VIN
3 V–13 V
ISET
ISENSE
DISCH
GATE
VSENSE
VREG
APPLICATIONS
Hot-Swap/Plug/Dock Power Management
Hot-Plug PCI, Device Bay
Electronic Circuit Breaker
DISCH
ENABLE
PWRGD
FAULT
ISET
AGND
IN
NOTE: Terminal 13 is active-high on TPS2331.
IN
•
•
•
14
13
12
11
10
9
8
1
2
3
4
5
6
7
GATE
DGND
TIMER
VREG
VSENSE
AGND
ISENSE
AGND
PWRGD
TPS2330
DGND
FAULT
TIMER
ENABLE
DESCRIPTION
The TPS2330 and TPS2331 are single-channel hot-swap controllers that use external N-channel MOSFETs as
high-side switches in power applications. Features of these devices, such as overcurrent protection (OCP),
inrush-current control, output-power status reporting, and the ability to discriminate between load transients and
faults, are critical requirements for hot-swap applications.
The TPS2330/31 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure the
device is off at start-up and confirm the status of the output voltage rails during operation. An internal charge
pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the N-channel
MOSFETs. The charge pump controls both the rise times and fall times (dV/dt) of the MOSFETs, reducing power
transients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrent
conditions with a timer function; this allows designs such as DSPs, that may have high peak currents during
power-state transitions, to disregard transients for a programmable period.
Table 1. AVAILABLE OPTIONS
TA
–40°C to 85°C
(1)
HOT-SWAP CONTROLLER DESCRIPTION
PIN COUNT
PACKAGES (1)
ENABLE
ENABLE
Dual-channel with independent OCP and adjustable PG
20
TPS2300IPW
TPS2301IPW
Dual-channel with interdependent OCP and adjustable PG
20
TPS2310IPW
TPS2311IPW
Dual-channel with independent OCP
16
TPS2320ID
TPS2320IPW
TPS2321ID
TPS2321IPW
Single-channel with OCP and adjustable PG
14
TPS2330ID
TPS2330IPW
TPS2331ID
TPS2331IPW
The packages are available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TPS2331IPWR).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
TPS2330
TPS2331
SLVS277G – MARCH 2000 – REVISED JULY 2013
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
IN
VREG
ISET
ISENSE
GATE
PREREG
DISCH
Clamp
dv/dt Rate
Protection
Charge
Pump
Circuit
Breaker
50 µA
Pulldown FET
Circuit Breaker
UVLO and
Power Up
AGND
75 µA
VSENSE
PWRGD
Deglitcher
DGND
ENABLE
FAULT
Logic
Deglitcher
TIMER
Table 2. Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
6, 9
I
Analog ground, connects to DGND as close as possible
DGND
2
I
Digital ground
DISCH
14
O
Discharge transistor
ENABLE/ENABLE
13
I
Active-low (TPS2330) or active-high enable (TPS2331)
FAULT
11
O
Overcurrent fault, open-drain output
GATE
1
O
Connects to gate of high-side MOSFET
IN
8
I
Input voltage
ISENSE
7
I
Current-sense input
ISET
10
I
Adjusts circuit-breaker threshold with resistor connected to IN
PWRGD
12
O
Open-drain output, asserted low when VSENSE voltage is less than reference.
TIMER
3
O
Adjusts circuit-breaker deglitch time
VREG
4
O
Connects to bypass capacitor, for stable operation
VSENSE
5
I
Power-good sense input
2
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SLVS277G – MARCH 2000 – REVISED JULY 2013
DETAILED DESCRIPTION
DISCH – DISCH should be connected to the source of the external N-channel MOSFET transistor connected to
GATE. This pin discharges the load when the MOSFET transistor is disabled. They also serve as referencevoltage connection for internal gate-voltage-clamp circuitry.
ENABLE or ENABLE – ENABLE for TPS2330 is active-low. ENABLE for TPS2331 is active-high. When the
controller is enabled, GATE voltage powers up to turn on the external MOSFETs. When the ENABLE pin is
pulled high for TPS2330 or the ENABLE pin is pulled low for TPS2331 for more than 50 μs, the gate of the
MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the
output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when
enabled and shuts down PREREG when disabled so that total supply current is much less than 5 μA.
FAULT – FAULT is an open-drain overcurrent flag output. When an overcurrent condition is sustained long
enough to charge TIMER to 0.5 V, the device latches off and pulls FAULT low. In order to turn the device back
on, either the enable pin must be toggled or the input power must be cycled.
GATE – GATE connects to the gate of the external N-channel MOSFET transistor. When the device is enabled,
internal charge-pump circuitry pulls this pin up by sourcing approximately 15 μA. The turnon slew rates depend
on the capacitance present at the GATE terminal. If desired, the turnon slew rates can be further reduced by
connecting capacitors between this pin and ground. These capacitors also reduce inrush current and protect the
device from false overcurrent triggering during power up. The charge-pump circuitry generates gate-to-source
voltages of 9 V–12 V across the external MOSFET transistor.
IN – IN should be connected to the power source driving the external N-channel MOSFET transistor connected
to GATE. The TPS2330/31 draws its operating current from IN, and remains disabled until the IN power supply
has been established. The device has been constructed to support 3-V, 5-V, or 12-V operation.
ISENSE, ISET – ISENSE in combination with ISET implements overcurrent sensing for GATE. ISET sets the
magnitude of the current that generates an overcurrent fault, through an external resistor connected to ISET. An
internal current source draws 50 μA from ISET. With a sense resistor from IN to ISENSE, which is also
connected to the drain of the external MOSFET, the voltage on the sense resistor reflects the load current. An
overcurrent condition is assumed to exist if ISENSE is pulled below ISET. To ensure proper circuit breaker
operation, VI(ISENSE) and VI(ISET) should never exceed VI(IN).
PWRGD – PWRGD signals the presence of undervoltage conditions on VSENSE. The pin is an open-drain
output and is pulled low during an undervoltage condition. To minimize erroneous PWRGD responses from
transients on the voltage rail, the voltage sense circuit incorporates a 20-μs deglitch filter. When VSENSE is
lower than the reference voltage (about 1.23 V), PWRGD is active-low to indicate an undervoltage condition on
the power-rail voltage. PWRGD may not correctly report power conditions when the device is disabled because
there is no gate drive power for the PWRGD output transistor in the disable mode, or, in other words, PWRGD is
floating. Therefore, PWRGD is pulled up to its pullup power supply rail in disable mode.
TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning
off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which
charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker
latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to
restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly
recommended from TIMER to ground, to prevent any false triggering.
VREG – VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator is
used to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1-μF ceramic capacitor should
be connected between VREG and ground to aid in noise rejection. In this configuration, on disabling the device,
the internal low-dropout regulator also is disabled, which removes power from the internal circuitry and allows the
device to be placed in low-quiescent-current mode. In applications where IN1 is less than 5.5 V, VREG and IN1
may be connected together. However, under these conditions, disabling the device may not place the device in
low-quiescent-current mode, because the internal low-dropout voltage regulator is being bypassed, thereby
keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1-μF ceramic capacitor
between VREG and ground is not needed if IN1 already has a bypass capacitor of 1 μF to 10 μF.
VSENSE – VSENSE can be used to detect undervoltage conditions on external circuitry. If VSENSE senses a
voltage below approximately 1.23 V, PWRGD is pulled low.
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TPS2330
TPS2331
SLVS277G – MARCH 2000 – REVISED JULY 2013
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VALUE
UNIT
VI(IN1), VI(ISENSE), VI(VSENSE), VI(ISET), VI(ENABLE)
–0.3 to 15
V
VI(VREG)
–0.3 to 7
V
VO(GATE)
–0.3 to 30
V
VO(DISCH), VO(PWRGD), VO( FAULT ), VO(TIMER)
–0.3 to 15
V
I(GATE), I(DISCH)
0 to 100
mA
I(PWRGD), I(TIMER), I( FAULT )
0 to 10
mA
Operating virtual junction temperature range, TJ
–40 to 100
°C
Storage temperature range, Tstg
–55 to 150
°C
260
°C
Input voltage range
Output voltage range
Sink current range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to DGND.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PW-14
755 mW
10.07 mW/°C
302 mW
151 mW
D-14
613 mW
8.18 mW/°C
245 mW
123 mW
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
3
13
VI(VREG)
3
5.5
VI
Input voltage
TJ
Operating virtual junction temperature
VI(ISENSE), VI(ISET), VI(VSENSE)
4
NOM
VI(IN), VI(ISENSE), VI(VSENSE), VI(ISET)
V
VI(IN)
–40
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UNIT
100
°C
Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: TPS2330 TPS2331
TPS2330
TPS2331
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SLVS277G – MARCH 2000 – REVISED JULY 2013
ELECTRICAL CHARACTERISTICS
over recommended operating temperature range (–40°C < TA < 85°C), 3V ≤ VI(IN1) ≤13 V, 3 V ≤ VI(IN2) ≤ 5.5 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.5
1
mA
5
μA
GENERAL
II(IN)
Input current, IN
VI(ENABLE) = 5 V (TPS2331),
VI( ENABLE ) = 0 V (TPS2330)
II(stby)
Standby current (sum of currents into
IN, ISENSE, and ISET)
VI(ENABLE) = 0 V (TPS2331),
VI( ENABLE ) = 5 V (TPS2330)
Gate voltage
II(GATE) = 500 nA, DISCH open
GATE
VG(GATE_3V)
VG(GATE_4.5V)
VI(IN) = 3 V
VG(GATE_10.8V)
VC(GATE)
IS(GATE)
tr(GATE)
9
11.5
VI(IN) = 4.5 V
10.5
14.5
VI(IN) = 10.8 V
16.8
21
Clamping voltage, GATE to DISCH
9
10
12
V
Source current, GATE
3 V ≤ VI(IN) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
VI(GATE) = VI(IN) + 6 V
10
14
20
μA
Sink current, GATE
3 V ≤ VI(IN) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
VI(GATE) = VI(IN)
50
75
100
μA
Rise time, GATE
Cg to GND = 1 nF (1)
VI(IN) = 3 V
0.5
VI(IN) = 4.5 V
0.6
VI(IN) = 10.8 V
Cg to GND = 1 nF (1)
Fall time, GATE
ms
1
VI(IN) = 3 V
tf(GATE)
V
0.1
VI(IN) = 4.5 V
0.12
VI(IN) = 10.8 V
0.2
ms
TIMER
V(TO_TIMER)
Threshold voltage, TIMER
0.4
0.5
0.6
V
Charge current, TIMER
VI(TIMER) = 0 V
35
50
65
μA
Discharge current, TIMER
VI(TIMER) = 1 V
1
2.5
RISET = 1 kΩ
40
50
60
RISET = 400 Ω, TA = 25°C
14
19
24
RISET = 1 kΩ, TA = 25°C
44
50
53
RISET = 1.5 kΩ, TA = 25°C
68
73
78
0.1
5
mA
CIRCUIT BREAKER
VIT(CB)
Threshold voltage, circuit breaker
I(IB_ISENSE)
Input bias current, ISENSE
Discharge current, GATE
tpd(CB)
Propagation (delay) time, comparator
inputs to gate output
VO(GATE) = 4 V
400
800
VO(GATE) = 1 V
25
150
Cg = 50 pF,
(50% to 10%),
10-mV overdrive,
CTIMER = 50 pF
mV
μA
mA
μs
1.3
ENABLE, ACTIVE LOW (TPS2330)
VIH( ENABLE )
High-level input voltage, ENABLE
VIL( ENABLE )
Low-level input voltage, ENABLE
2
RI( ENABLE )
Input pullup resistance, ENABLE
See
td(off_ ENABLE )
Turnoff delay time, ENABLE
VI( ENABLE ) increasing above stop threshold;
100 ns rise time, 20 mV overdrive (1)
60
μs
td(on_ ENABLE )
Turnon delay time, ENABLE
VI( ENABLE ) decreasing below start threshold;
100 ns fall time, 20 mV overdrive (1)
125
μs
(2)
100
(1)
Specified, but not production tested.
(2)
Test IO of ENABLE at VI( ENABLE ) = 1 V and 0 V, then RI( ENABLE ) = I
O_ 0V * I O_ 1V
V
200
0.8
V
300
kΩ
1V
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SLVS277G – MARCH 2000 – REVISED JULY 2013
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ELECTRICAL CHARACTERISTICS (Continued)
over recommended operating temperature range (–40°C < TA < 85°C), 3 V ≤VI(IN1) ≤13 V, 3 V ≤ VI(IN2) ≤ 5.5 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
ENABLE, ACTIVE HIGH (TPS2331)
VIH(ENABLE)
High-level input voltage, ENABLE
VIL(ENABLE)
Low-level input voltage, ENABLE
2
RI(ENABLE)
Input pulldown resistance, ENABLE
td(on_ENABLE)
Turnon delay time, ENABLE
VI(ENABLE) increasing above start threshold;
100-ns rise time, 20-mV overdrive (1)
85
μs
td(off_ENABLE)
Turnoff delay time, ENABLE
VI(ENABLE) decreasing below stop threshold;
100-ns fall time, 20-mV overdrive (1)
100
μs
V(VREG)
PREREG output voltage
4.5 ≤ VI(IN) ≤ 13 V
V(drop_PREREG)
PREREG dropout voltage
VI(IN) = 3 V
100
V
150
0.7
V
300
kΩ
PREREG
3.5
4.1
5.5
V
0.1
V
2.95
V
VREG UVLO
V(TO_UVLOstart)
Output threshold voltage, start
2.75
2.85
V(TO_UVLOstop)
Output threshold voltage, stop
2.65
2.78
Vhys(UVLO)
Hysteresis
50
75
UVLO sink current, GATE
V
mV
VI(GATE) = 2 V
10
mA
VI(VSENSE) decreasing
1.2
1.22
5
1.25
20
30
40
mV
0.2
0.4
V
PWRGD1 and PWRGD2
VIT(ISENSE)
Trip threshold, VSENSE
Vhys
Hysteresis voltage, power-good
comparator
VO(sat_PWRGD)
Output saturation voltage, PWRGD
IO = 2 mA
VO(VREG_min)
Minimum VO(VREG) for valid powergood
IO = 100 μA, VO(PWRGD) = 1 V
1
V
Input bias current, power-good
comparator
VI(VSENSE) = 5.5 V
1
μA
Leakage current, PWRGD
VO(PWRGD) = 13 V
1
μA
tdr
Delay time, rising edge, PWRGD
VI(VSENSE) increasing, overdrive = 20 mV,
tr = 100 ns (1)
tdf
Delay time, falling edge, PWRGDx
VI(VSENSEx) decreasing, overdrive = 20 mV,
tr = 100 ns (1)
Ilkg(PWRGD)
V
25
μs
2
μs
FAULT OUTPUT
VO(sat_ FAULT )
Output saturation voltage, FAULT
IO = 2 mA
Ilkg( FAULT )
Leakage current, FAULT
VO( FAULT ) = 13 V
I(DISCH)
Discharge current, DISCH
VI(DISCH) = 1.5 V, VI(VIN) = 5 V
VIH(DISCH)
Discharge on high-level input voltage
VIL(DISCH)
Discharge on low-level input voltage
0.4
V
1
μA
DISCH
(1)
6
5
10
mA
2
V
1
V
Specified, but not production tested.
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SLVS277G – MARCH 2000 – REVISED JULY 2013
PARAMETER MEASUREMENT INFORMATION
Load 12 W
VI(ENABLE)
5 V/div
Load 12 W
VI(ENABLE)
5 V/div
VO(GATE)
10 V/div
VO(DISCH)
5 V/div
VO(GATE)
10 V/div
VO(DISCH)
5 V/div
t – Time – 10 ms/div
t – Time – 10 ms/div
Figure 1. Turnon Voltage Transition
VI(ENABLE)
5 V/div
No Capacitor on Timer
Figure 2. Turnoff Voltage Transition
VI(ENABLE)
5 V/div
VO(GATE)
10 V/div
No Capacitor on Timer
VO(GATE)
10 V/div
VO(FAULT)
10 V/div
VO(FAULT)
10 V/div
IO(OUT)
2 A/div
IO(OUT)
2 A/div
t – Time – 1 ms/div
t – Time – 5 ms/div
Figure 3. Overcurrent Response:
Enabled Into Overcurrent Load
Figure 4. Overcurrent Response: an Overcurrent
Load Plugged Into the Enabled Board
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PARAMETER MEASUREMENT INFORMATION (continued)
VI(ENABLE)
5 V/div
No Capacitor on Timer
No Capacitor on Timer
VI(IN)
10 V/div
VO(GATE)
10 V/div
VO(GATE)
10 V/div
VO(FAULT)
10 V/div
VO(OUT)
10 V/div
IO(OUT)
1 A/div
II(IN)
2 A/div
t – Time – 1 ms/div
t – Time – 5 ms/div
Figure 5. Enabled Into Short Circuit
VI(IN)
10 V/div
VO(GATE)
10 V/div
Figure 6. Hot Plug
No Capacitor on Timer
VO(OUT)
10 V/div
IO(OUT)
1 A/div
t – Time – 1 ms/div
Figure 7. Hot Removal
8
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SLVS277G – MARCH 2000 – REVISED JULY 2013
TYPICAL CHARACTERISTICS
INPUT CURRENT (ENABLED)
vs
INPUT VOLTAGE
INPUT CURRENT (DISABLED)
vs
INPUT VOLTAGE
15
52
IN = 5 V to 13 V
TA = 85°C
14
TA = 25°C
13
TA = 25°C
49
II – Input Current – nA
II – Input Current – mA
50
48
47
TA = 0°C
46
TA = –40°C
TA = –40°C
12
TA = 0°C
11
10
9
45
8
44
43
4
5
6
7
8
9
10
11
12
13
7
14
4
5
6
7
8
9
10
11
12
13 14
VI – Input Voltage – V
Figure 9.
VI – Input Voltage – V
Figure 8.
GATE OUTPUT VOLTAGE
vs
INPUT VOLTAGE
GATE VOLTAGE RISE TIME
vs
GATE LOAD CAPACITANCE
22
18
CL(GATE) = 1000 pF
20
IN = 12 V
TA = 25°C
TA = 85°C
TA = 25°C
TA = 0°C
18
TA = –40°C
16
14
12
10
2
3
4
5
6
7
8
9
VI – Input Voltage – V
10
11
12
tr – GATE Voltage Rise Time – ms
VO – GATE Output Voltage – V
TA = 85°C
IN = 5 V to 13 V
51
15
12
9
6
3
0
0
3
6
9
12
CL(GATE) – GATE Load Capacitance – nF
Figure 10.
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
GATE VOLTAGE FALL TIME
vs
GATE LOAD CAPACITANCE
GATE OUTPUT CURRENT
vs
GATE VOLTAGE
4
15
14.5
IO – GATE Output Current – mA
t f – GATE Voltage Fall Time – ms
IN = 12 V
TA = 25°C
3
2
1
14
TA = –40°C
TA = 85°C
13.5
TA = 25°C
13
TA = 0°C
12.5
12
11.5
IN = 13 V
0
11
0
3
6
9
12
14 15
16
19
20
21
22
Figure 13.
CIRCUIT-BREAKER RESPONSE TIME
vs
TIMER CAPACITANCE
LOAD VOLTAGE DISCHARGE TIME
vs
LOAD CAPACITANCE
23
24
320
IN = 12 V
TA = 25°C
t – Load Voltage Discharge Time – ms
t(res) – Circuit-Breaker Response Time – ms
18
Figure 12.
12
9
6
3
0
IN = 12 V
IO = 0 A
TA = 25°C
280
240
200
160
120
80
40
0
0
10
17
V – GATE Voltage – V
CL(GATE) – GATE Load Capacitance – nF
0.2
0.4
0.6
0.8
CTIMER – TIMER Capacitance – nF
Figure 14.
1
0
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100
200
300
400
CL – Load Capacitance – mF
Figure 15.
500
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SLVS277G – MARCH 2000 – REVISED JULY 2013
TYPICAL CHARACTERISTICS (continued)
UVLO START AND STOP THRESHOLDS
vs
TEMPERATURE
PWRGD INPUT THRESHOLD
vs
TEMPERATURE
1.27
2.88
VIT – PWRGD Input Threshold – V
Vref – UVLO Start and Stop Thresholds – V
2.9
2.86
Start
2.84
2.82
2.8
2.78
Stop
2.76
2.74
1.26
Up
1.25
1.24
1.23
Down
1.22
1.21
2.72
2.7
–45–35 –25–15 –5 5 15 25 35 45 55 65 75 85 95
TA – Temperature – °C
Figure 16.
1.20
–45–35 –25–15 –5 5 15 25 35 45 55 65 75 85 95
TA – Temperature – °C
Figure 17.
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APPLICATION INFORMATION
This diagram shows a typical dual hot-swap application. The pullup resistors at PWRGD and FAULT should be
relatively large (e.g. 100 kΩ) to reduce power loss unless they are required to drive a large load.
System
Board
RSENSE
3 V ∼ 13 V IN
1 µF ∼ 10 µF
+
RVSENSE_TOP
VO
RISET
RVSENSE_BOTTOM
0.1 µF
VREG IN ISET
ENABLE
ENABLE
DGND
AGND
ISENSE GATE DISCH VSENSE
TPS2331
FAULT
PWRGD
FAULT
PWRGD
TIMER
Figure 18. Typical Hot-Swap Application
INPUT CAPACITOR
A 0.1-μF ceramic capacitor in parallel with a 1-μF ceramic capacitor should be placed on the input power
terminals near the connector on the hot-plug board to help stabilize the voltage rails on the cards. There is no
need to mount the TPS2330/31 near the connector or these input capacitors. For applications with more severe
power environments, a 2.2-μF or higher ceramic capacitor is recommended near the input terminals of the hotplug board. A bypass capacitor for IN should be placed close to the device.
OUTPUT CAPACITOR
A 0.1-μF ceramic capacitor is recommended per load on the TPS2330/31; these capacitors should be placed
close to the external FETs and to TPS2330/31. A larger bulk capacitor on the load is also recommended. The
value of the bulk capacitor should be selected based on the power requirements and the transients generated by
the application.
EXTERNAL FET
To deliver power from the input sources to the loads, the controller needs an external N-channel MOSFET. A few
widely used MOSFETs are shown in Table 3. But many other MOSFETs on the market can also be used with
the TPS23xx in hot-swap systems.
12
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Table 3. Some Available N-Channel MOSFETs
CURRENT RANGE
(A)
0 to 2
2 to 5
5 to 10
PART NUMBER
DESCRIPTION
MANUFACTURER
IRF7601
N-channel, rDS(on) = 0.035 Ω, 4.6 A, Micro-8
International Rectifier
MTSF3N03HDR2
N-channel, rDS(on) = 0.040 Ω, 4.6 A, Micro-8
ON Semiconductor
IRF7101
Dual N-channel, rDS(on) = 0.1 Ω, 2.3 A, SO-8
International Rectifier
MMSF5N02HDR2
Dual N-channel, rDS(on) = 0.04 Ω, 5 A, SO-8
ON Semiconductor
IRF7401
N-channel, rDS(on) = 0.022 Ω, 7 A, SO-8
International Rectifier
MMSF5N02HDR2
N-channel, rDS(on) = 0.025 Ω, 5 A, SO-8
ON Semiconductor
IRF7313
Dual N-channel, rDS(on) = 0.029 Ω, 5.2 A, SO-8
International Rectifier
SI4410
N-channel, rDS(on) = 0.020 Ω, 8 A, SO-8
Vishay Dale
IRLR3103
N-channel, rDS(on) = 0.019 Ω, 29 A, d-Pak
International Rectifier
IRLR2703
N-channel, rDS(on) = 0.045 Ω, 14 A, d-Pak
International Rectifier
TIMER
For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. This
capacitor should be connected between TIMER and ground. The presence of an overcurrent condition on of the
TPS2330/31 causes a 50-μA current source to begin charging this capacitor. If the overcurrent condition persists
until the capacitor has been charged to approximately 0.5 V, the TPS2330/31 latches off the transistor and pulls
the FAULT pin low. The timer capacitor can be made as large as desired to provide additional time delay before
registering a fault condition. The time delay is approximately:
dt(sec) = C(TIMER)(F) × 10,000(Ω)
OUTPUT-VOLTAGE SLEW-RATE CONTROL
When enabled, the TPS2330/TPS2331 controllers supply the gate of an external MOSFET transistor with a
current of approximately 15 μA. The slew rate of the MOSFET source voltage is thus limited by the gate-to-drain
capacitance Cgd of the external MOSFET capacitor to a value approximating:
dV s
15 mA
+
C gd
dt
(1)
If a slower slew rate is desired, an additional capacitance can be connected between the gate of the external
MOSFET and ground.
VREG CAPACITOR
The internal voltage regulator connected to VREG requires an external capacitor to ensure stability. A 0.1-μF or
0.22-μF ceramic capacitor is recommended.
GATE DRIVE CIRCUITRY
The TPS2330/TPS2331 includes four separate features associated with each gate-drive terminal:
• A charging current of approximately 15 μA is applied to enable the external MOSFET transistor. This current
is generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH) of
9 V–12 V. DISCH must be connected to the external MOSFET source terminal to ensure proper operation of
this circuitry.
• A discharge current of approximately 75 μA is applied to disable the external MOSFET transistor. Once the
transistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLO
discharge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode while
ensuring that the gate of the external MOSFET transistor remains at a low voltage.
• During a UVLO condition, the gate of the MOSFET transistor is pulled down by an internal PMOS transistor.
This transistor continues to operate even if the voltage at IN is 0 V. This circuitry also helps hold the external
MOSFET transistor off when power is suddenly applied to the system.
• During an overcurrent fault condition, the external MOSFET transistor that exhibited an overcurrent condition
is rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at 4 V) from the
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pin. Once the gate has been pulled below approximately 1.5 V, this driver is disengaged and the UVLO driver
is enabled instead.
SETTING THE CURRENT-LIMIT CIRCUIT-BREAKER THRESHOLD
The current sensing resistor RISENSE and the current limit setting resistor RISET determine the current limit of the
channel, and can be calculated by the following equation:
R
50 10 –6
I LMT + ISET
R ISENSE
(2)
Typically RISENSE is usually very small (0.001 Ω to 0.1 Ω). If the trace and solder-junction resistances between the
junction of RISENSE and ISENSE and the junction of RISENSE and RISET are greater than 10% of the RISENSE value,
then these resistance values should be added to the RISENSE value used in the foregoing calculation.
Table 4 shows some of the current-sense resistors available in the market.
Table 4. Some Current-Sense Resistors
CURRENT RANGE
(A)
PART NUMBER
DESCRIPTION
0 to 1
WSL-1206, 0.05 1%
0.05 Ω, 0.25 W, 1% resistor
1 to 2
WSL-1206, 0.025 1%
0.025 Ω, 0.25 W, 1% resistor
2 to 4
WSL-1206, 0.015 1%
0.015 Ω, 0.25 W, 1% resistor
4 to 6
WSL-2010, 0.010 1%
0.010 Ω, 0.5 W, 1% resistor
6 to 8
WSL-2010, 0.007 1%
0.007 Ω, 0.5 W, 1% resistor
8 to 10
WSR-2, 0.005 1%
0.005 Ω, 0.5 W, 1% resistor
MANUFACTURER
Vishay Dale
SETTING THE POWER-GOOD THRESHOLD VOLTAGE
The two feedback resistors RVSENSE_TOP and RVSENSE_BOT connected between VO and ground form a resistor
divider, setting the voltage at the VSENSE pins. VSENSE voltage equals:
VI(SENSE) = VO × RVSENSE_BOT/(RVSENSE_TOP + RVSENSE_BOT)
This voltage is compared to an internal voltage reference (1.225 V ±2%) to determine whether the output voltage
level is within a specified tolerance. For example, given a nominal output voltage at VO, and defining VO_min as
the minimum required output voltage, then the feedback resistors are defined by:
VO_min * 1.225
R VSENSE_TOP +
R VSENSE_BOT
1.225
(3)
Start the process by selecting a large standard resistor value for RVSENSE_BOT to reduce power loss. Then
RVSENSE_TOP can be calculated by inserting all of the known values into the preceding equation. When VO is lower
than VO_min, PWRGD is low as long as the controller is enabled.
UNDERVOLTAGE LOCKOUT (UVLO)
The TPS2330/TPS2331 includes an undervoltage lockout (UVLO) feature that monitors the voltage present on
the VREG pin. This feature disables the external MOSFET if the voltage on VREG drops below 2.78 V (nominal)
and re-enables normal operation when it rises above 2.85 V (nominal). Because VREG is fed from IN through a
low-dropout voltage regulator, the voltage on VREG tracks the voltage on IN within 50 mV. While the
undervoltage lockout is engaged, GATE is held low by an internal PMOS pulldown transistor, ensuring that the
external MOSFET transistor remain off at the times, even if the power supply has fallen to 0 V.
POWER-UP CONTROL
The TPS2330/TPS2331 includes a 500-μs (nominal) start-up delay that ensures that internal circuitry has
sufficient time to start before the device begins turning on the external MOSFETs. This delay is triggered only on
the rapid application of power to the circuit. If the power supply ramps up slowly, the undervoltage lockout
circuitry provides adequate protection against undervoltage operation.
14
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SLVS277G – MARCH 2000 – REVISED JULY 2013
THREE-CHANNEL HOT-SWAP APPLICATION
Some applications require hot-swap control of up to three voltage rails, but may not explicitly require the sensing
of the status of the output power on all three of the voltage rails. One such application is a device bay, where
dV/dt control of 3.3 V, 5 V, and 12 V is required. By using TPS2330/TPS2331 to drive all three power rails, as is
shown in Figure 19, TPS2330/31 can deliver three different voltages to three loads while monitoring the status of
one of the loads.
System
Board
3.3 V IN2
VO2
1 µF ∼ 10 µF
+
Rg2
Rg3
5 V IN3
VO3
1 µF ∼ 10 µF
+
RSENSE
12 V IN1
1 µF ∼ 10 µF
+
RVSENSE_TOP
VO1
RISET
RVSENSE_BOTTOM
Rg1
0.1 µF
VREG IN ISET
ENABLE
DGND
AGND
ENABLE
ISENSE GATE
DISCH VSENSE
TPS2331
FAULT
PWRGD
FAULT
PWRGD
TIMER
Figure 19. Three-Channel Application
Figure 20 shows ramp-up waveforms of the three output voltages.
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TPS2330
TPS2331
SLVS277G – MARCH 2000 – REVISED JULY 2013
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VO – Output Voltage – 2 V/div
VO1
VO3
VO2
t – Time – 2.5 ms/div
Figure 20.
16
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TPS2331
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SLVS277G – MARCH 2000 – REVISED JULY 2013
REVISION HISTORY
Note: Revision history for previous versions is not available. Page numbers of previous versions may differ.
Changes from Revision F (November 2006) to Revision G
Page
•
Added text to ISENSE, ISET pin description paragraph for clarification. ............................................................................. 3
•
Added additional VI specs to ROC table for clarification ...................................................................................................... 4
•
Added minus sign to 40°C MIN TJ temperature ................................................................................................................... 4
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17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS2330ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS2330I
TPS2330IDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS2330I
TPS2330IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS2330I
TPS2330IDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS2330I
TPS2330IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD2330I
TPS2330IPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD2330I
TPS2330IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD2330I
TPS2330IPWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD2330I
TPS2331ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS2331I
TPS2331IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS2331I
TPS2331IDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS2331I
TPS2331IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD2331I
TPS2331IPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD2331I
TPS2331IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD2331I
TPS2331IPWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD2331I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS2330IDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TPS2330IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TPS2331IDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TPS2331IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS2330IDR
SOIC
D
14
2500
367.0
367.0
38.0
TPS2330IPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
TPS2331IDR
SOIC
D
14
2500
367.0
367.0
38.0
TPS2331IPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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