DLP7000UV 0.7XGA 2xLVDS UV Type A DMD (Rev. C)

DLP7000UV 0.7XGA 2xLVDS UV Type A DMD (Rev. C)
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DLP7000UV
DLPS061C – MAY 2015 – REVISED SEPTEMBER 2015
DLP7000UV DLP® 0.7 UV XGA 2x LVDS Type A DMD
1 Features
3 Description
•
DLP7000UV is a digitally controlled MEMS (microelectromechanical system) spatial light modulator
(SLM). When coupled to an appropriate optical
system, the DLP7000UV can be used to modulate
the amplitude, direction, and/or phase of incoming
light.
1
•
•
•
•
•
0.7-Inch Diagonal Micromirror Array
– 1024 × 768 Array of Aluminum, MicrometerSized Mirrors
– 13.68-µm Micromirror Pitch
– ±12° Micromirror Tilt Angle (Relative to Flat
State)
– Designed for Corner Illumination
Designed for Use With UV Light (363 to 420 nm):
– Window Transmission 98% (Single Pass,
Through Two Window Surfaces)
– Micromirror Reflectivity 88%
– Array Diffraction Efficiency 85%
– Array Fill Factor 92% (Nominal)
Two 16-Bit, Low-Voltage Differential Signaling
(LVDS) Double Data Rate (DDR) Input Data
Buses
Up to 400 MHz Input Data Clock Rate
40.64-mm by 31.75-mm by 6.0-mm Package
Footprint
Hermetic Package
2 Applications
•
•
Industrial
– Direct Imaging Lithography
– Laser Marking and Repair Systems
– Computer-to-Plate Printers
– Rapid Prototyping Machines
– 3D Printers
Medical
– Ophthalmology
– Photo Therapy
– Hyper-Spectral Imaging
The DLP7000UV DMD is an addition to the DLP
Discovery 4100 platform, which enables very fast
pattern rates combined with high performance spatial
light modulation operating beyond the visible
spectrum into the UVA spectrum (363 nm to 420 nm).
The DLP7000UV digital micromirror device (DMD) is
designed with a special window that is optimized for
UV transmission. The DLP Discovery 4100 platform
also provides the highest level of individual
micromirror control with the option for random row
addressing. Combined with a hermetic package, the
unique capability and value offered by DLP7000UV
makes it well suited to support a wide variety of
industrial,
medical,
and
advanced
display
applications.
The DLP7000UV DMD with a hermetic package is
sold with a dedicated DLPC410 controller for high
speed pattern rates of >32000 Hz (1-bit binary) and
>1900 Hz (8-bit gray), one DLPR410 (DLP Discovery
4100 Configuration PROM), and one DLPA200 (DMD
micromirror driver).
Device Information
PART NUMBER
DLP7000UV
PACKAGE
LCCC (203)
(1)
BODY SIZE (NOM)
40.64 mm × 31.75 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
Illumination
Driver
DLPC410
DLP7000UV
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP7000UV
DLPS061C – MAY 2015 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Description (continued)......................................... 3
Pin Configuration and Functions ......................... 3
Specifications....................................................... 10
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
8
Absolute Maximum Ratings .................................... 10
Storage Conditions.................................................. 10
ESD Ratings............................................................ 10
Recommended Operating Conditions..................... 11
Thermal Information ................................................ 11
Electrical Characteristics......................................... 12
LVDS Timing Requirements ................................... 13
LVDS Waveform Requirements.............................. 14
Serial Control Bus Timing Requirements................ 15
Systems Mounting Interface Loads....................... 16
Micromirror Array Physical Characteristics ........... 17
Micromirror Array Optical Characteristics ............. 18
Window Characteristics......................................... 19
Chipset Component Usage Specification ............. 19
Detailed Description ............................................ 20
8.1 Overview ................................................................. 20
8.2
8.3
8.4
8.5
8.6
8.7
9
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Window Characteristics and Optics .......................
Micromirror Array Temperature Calculation............
Micromirror Landed-On/Landed-Off Duty Cycle .....
21
21
29
31
32
34
Application and Implementation ........................ 36
9.1 Application Information............................................ 36
9.2 Typical Application .................................................. 37
10 Power Supply Recommendations ..................... 40
10.1 Power-Up Sequence (Handled by the DLPC410)
................................................................................. 40
11 Layout................................................................... 40
11.1 Layout Guidelines ................................................. 40
11.2 Layout Example .................................................... 42
12 Device and Documentation Support ................. 43
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
43
43
44
44
44
44
13 Mechanical, Packaging, and Orderable
Information ........................................................... 44
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2015) to Revision C
Page
•
Changed device status from Product Preview to Production Data ........................................................................................ 1
•
Added 3.7-W maximum value to illumination power density (from 363 nm to 420 nm) in Recommended Operating
Conditions ............................................................................................................................................................................ 11
•
Updated Figure 18 ............................................................................................................................................................... 36
Changes from Revision A (June 2015) to Revision B
Page
•
Released full data sheet ......................................................................................................................................................... 1
•
Corrected minimum value of UVA spectrum from 365 nm to 363 nm in Description ............................................................ 1
Changes from Original (May 2015) to Revision A
•
2
Page
Corrected device part number ............................................................................................................................................... 1
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Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: DLP7000UV
DLP7000UV
www.ti.com
DLPS061C – MAY 2015 – REVISED SEPTEMBER 2015
5 Description (continued)
Reliable function and operation of the DLP7000UV requires that it be used in conjunction with the other
components of the chipset. A dedicated chipset provides developers easier access to the DMD as well as high
speed, independent micromirror control.
Electrically, the DLP7000UV consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid
of 1024 memory cell columns by 768 memory cell rows. The CMOS memory array is addressed on a row-by-row
basis, over two 16-bit low voltage differential signaling (LVDS) double data rate (DDR) buses. Addressing is
handled via a serial control bus. The specific CMOS memory access protocol is handled by the DLPC410 digital
controller.
6 Pin Configuration and Functions
FLP Package
203-Pin LCCC
Bottom View
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
30
28
29
26
27
24
25
22
23
20
21
18
19
16
17
14
15
12
13
10
11
8
9
6
7
4
5
2
3
1
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3
DLP7000UV
DLPS061C – MAY 2015 – REVISED SEPTEMBER 2015
www.ti.com
Pin Functions
PIN
(1)
NO.
TYPE
(I/O/P)
INTERNAL
TERM (3)
CLOCK
D_AN(0)
B10
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
368.72
D_AN(1)
A13
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
424.61
D_AN(2)
D16
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
433.87
D_AN(3)
C17
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
391.39
D_AN(4)
B18
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
438.57
D_AN(5)
A17
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
391.13
D_AN(6)
A25
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
563.26
D_AN(7)
D22
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
411.62
D_AN(8)
C29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
D_AN(9)
D28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
543.07
D_AN(10)
E27
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
455.98
D_AN(11)
F26
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
359.5
D_AN(12)
G29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
542.67
D_AN(13)
H28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
551.51
D_AN(14)
J27
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
528.04
D_AN(15)
K26
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
484.38
D_AP(0)
B12
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
366.99
D_AP(1)
A11
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
417.47
NAME
SIGNAL
DATA
RATE (2)
DESCRIPTION
TRACE (MILS)
DATA INPUT
(1)
(2)
(3)
4
Input data bus A
(2x LVDS)
595.11
The following power supplies are required to operate the DMD: VCC, VCC1, VCC2. VSS must also be connected.
DDR = Double Data Rate. SDR = Single Data Rate. Refer to the LVDS Timing Requirements for specifications and relationships.
Refer to Electrical Characteristics for differential termination specification.
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Product Folder Links: DLP7000UV
DLP7000UV
www.ti.com
DLPS061C – MAY 2015 – REVISED SEPTEMBER 2015
Pin Functions (continued)
PIN
(1)
NO.
TYPE
(I/O/P)
INTERNAL
TERM (3)
CLOCK
D_AP(2)
D14
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
434.89
D_AP(3)
C15
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
394.67
D_AP(4)
B16
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
437.3
D_AP(5)
A19
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
389.01
D_AP(6)
A23
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
562.92
D_AP(7)
D20
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
410.34
D_AP(8)
A29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
594.61
D_AP(9)
B28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
539.88
D_AP(10)
C27
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
456.78
D_AP(11)
D26
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
360.68
D_AP(12)
F30
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
D_AP(13)
H30
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
570.85
D_AP(14)
J29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
527.18
D_AP(15)
K28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
481.02
D_BN(0)
AB10
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
368.72
D_BN(1)
AC13
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
424.61
D_BN(2)
Y16
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
433.87
D_BN(3)
AA17
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
391.39
D_BN(4)
AB18
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
438.57
NAME
SIGNAL
DATA
RATE (2)
DESCRIPTION
Input data bus A
(2x LVDS)
TRACE (MILS)
543.97
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5
DLP7000UV
DLPS061C – MAY 2015 – REVISED SEPTEMBER 2015
www.ti.com
Pin Functions (continued)
PIN
(1)
NO.
TYPE
(I/O/P)
INTERNAL
TERM (3)
CLOCK
D_BN(5)
AC17
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
391.13
D_BN(6)
AC25
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
563.26
D_BN(7)
Y22
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
411.62
D_BN(8)
AA29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
595.11
D_BN(9)
Y28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
543.07
D_BN(10)
W27
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
455.98
D_BN(11)
V26
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
360.94
D_BN(12)
T30
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
575.85
D_BN(13)
R29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
519.37
D_BN(14)
R27
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
532.59
D_BN(15)
N27
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
441.14
D_BP(0)
AB12
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
366.99
D_BP(1)
AC11
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
417.47
D_BP(2)
Y14
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
434.89
D_BP(3)
AA15
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
394.67
D_BP(4)
AB16
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
437.3
D_BP(5)
AC19
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
389.01
DCLK_B
DCLK_B
NAME
SIGNAL
DATA
RATE (2)
D_BP(6)
AC23
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
D_BP(7)
Y20
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
6
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DESCRIPTION
Input data bus B
(2x LVDS) Input
data bus B (2x
LVDS)
TRACE (MILS)
562.92
410.34
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: DLP7000UV
DLP7000UV
www.ti.com
DLPS061C – MAY 2015 – REVISED SEPTEMBER 2015
Pin Functions (continued)
PIN
(1)
NO.
TYPE
(I/O/P)
INTERNAL
TERM (3)
CLOCK
D_BP(8)
AC29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
594.61
D_BP(9)
AB28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
539.88
D_BP(10)
AA27
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
456.78
D_BP(11)
Y26
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
360.68
D_BP(12)
U29
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
578.46
D_BP(13)
T28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
509.74
D_BP(14)
P28
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
D_BP(15)
P26
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
440
DCLK_AN
B22
Input
LVCMOS
–
Differential
Terminated 100 Ω
–
477.10
DCLK_AP
B24
Input
LVCMOS
–
Differential
Terminated 100 Ω
–
477.11
DCLK_BN
AB22
Input
LVCMOS
–
Differential
Terminated 100 Ω
–
477.10
DCLK_BP
AB24
Input
LVCMOS
–
Differential
Terminated 100 Ω
–
477.11
NAME
DATA
RATE (2)
SIGNAL
DESCRIPTION
Input data bus B
(2x LVDS)
TRACE (MILS)
534.59
DATA CLOCK
DATA CONTROL INPUTS
SCTRL_AN
C21
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
SCTRL_AP
C23
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_A
SCTRL_BN
AA21
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
SCTRL_BP
AA23
Input
LVCMOS
DDR
Differential
Terminated 100 Ω
DCLK_B
Serial control for
data bus A (2x
LVDS)
477.07
477.14
Serial control for
data bus B (2x
LVDS)
477.07
477.14
SERIAL COMMUNICATION AND CONFIGURATION
SCPCLK
E3
Input
LVCMOS
–
Pull-down
–
Serial port clock
379.29
SCPDO
B2
Output
LVCMOS
–
SCPDI
F4
Input
LVCMOS
–
–
SCPCLK
Serial port output
480.91
Pull-down
SCPCLK
Serial port input
SCPENZ
D4
Input
LVCMOS
323.56
–
Pull-down
SCPCLK
Serial port enable
326.99
PWRDNZ
C3
Input
LVCMOS
–
Pull-down
–
Device Reset
406.28
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DLP7000UV
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Pin Functions (continued)
PIN
(1)
NAME
NO.
TYPE
(I/O/P)
MODE_A
D8
Input
LVCMOS
–
Pull-down
–
MODE_B
C11
Input
LVCMOS
–
Pull-down
–
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
CLOCK
DESCRIPTION
Data bandwidth
mode select
TRACE (MILS)
396.05
208.86
MICROMIRROR BIAS CLOCKING PULSE
MBRST(0)
P2
Input
Analog
–
–
–
MBRST(1)
AB4
Input
Analog
–
–
–
MBRST(2)
AA7
Input
Analog
–
–
–
MBRST(3)
N3
Input
Analog
–
–
–
MBRST(4)
M4
Input
Analog
–
–
–
MBRST(5)
AB6
Input
Analog
–
–
–
MBRST(6)
AA5
Input
Analog
–
–
–
Micromirror Bias
Clocking Pulse
MBRST signals
clock micromirrors
into state of
LVCMOS memory
cell associated
with each mirror.
MBRST(7)
L3
Input
Analog
–
–
–
MBRST(8)
Y6
Input
Analog
–
–
–
MBRST(9)
K4
Input
Analog
–
–
–
MBRST(10)
L5
Input
Analog
–
–
–
MBRST(11)
AC5
Input
Analog
–
–
–
MBRST(12)
Y8
Input
Analog
–
–
–
MBRST(13)
J5
Input
Analog
–
–
–
MBRST(14)
K6
Input
Analog
–
–
–
MBRST(15)
AC7
Input
Analog
–
–
–
VCC
A7,A15,C1,
E1,U1,W1,A
B2,AC9,AC
15
Power
Analog
–
–
–
Power for
LVCMOS Logic
–
VCC1
A21,A27,D3
0,M30,Y30,
AC21,AC27
Power
Analog
–
–
–
Power supply for
LVDS Interface
–
VCC2
G1,J1,L1,N
1,R1
Power
Analog
–
–
–
Power for High
Voltage CMOS
Logic
–
POWER
8
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DLP7000UV
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DLPS061C – MAY 2015 – REVISED SEPTEMBER 2015
Pin Functions (continued)
PIN
NAME
(1)
NO.
TYPE
(I/O/P)
DATA
RATE (2)
SIGNAL
INTERNAL
TERM (3)
CLOCK
DESCRIPTION
TRACE (MILS)
A1,A3,A5,A
9,B4,B8,B1
4,B20,B26,
B30,C7,
C13,C19,C2
5,D6,D12,D
18,D24,E29,
F2,F28,
G3,G27,H2,
H4,H26,J3,J
25,K2,K30,L
25,
VSS
L27,L29,M2,
M6,M26,M2
8,N5,N25,N
29,P4,
Power
Analog
–
–
–
Common return
for all power
inputs
–
P30,R3,R5,
R25,T2,T26,
U27,V28,V3
0,W5,
W29,Y4,Y1
2,Y18,Y24,
AA3,AA9,A
A13,AA19,
AA25,AB8,A
B14,AB20,A
B26,AB30
RESERVED SIGNALS (NOT FOR USE IN SYSTEM)
RESERVED
_AA1
AA1
Input
LVCMOS
–
Pull-down
–
Pins should be
connected to VSS
–
RESERVED
_B6
B6
Input
LVCMOS
–
Pull-down
–
–
–
RESERVED
_T4
T4
Input
LVCMOS
–
Pull-down
–
–
–
RESERVED
_U5
U5
Input
LVCMOS
–
Pull-down
–
–
–
AA11,AC3,
C5,C9,D10,
D2,E5,G5,H
6,P6,T6,
–
–
–
–
–
DO NOT
CONNECT
–
NO_CONN
ECT
U3,V2,V4,W
3,Y10,Y2
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
ELECTRICAL
VCC
Voltage applied to VCC
(2) (3)
–0.5
4
V
VCCI
Voltage applied to VCCI
(2) (3)
–0.5
4
V
VCC2
Voltage applied to VVCC2
–0.5
8
V
VMBRST
Micromirror clocking pulse waveform voltage applied to MBRST[15:0]
Input Pins (supplied by DLPA200)
-28
28
V
0.3
V
|VCC – VCCI|
(2) (3) (4)
Supply voltage delta (absolute value)
(4)
Voltage applied to all other input pins
(2)
VCC + 0.3
V
|VID|
Maximum differential voltage, damage can occur to internal termination
resistor if exceeded, see Figure 2
–0.5
700
mV
IOH
Current required from a high-level output
VOH = 2.4 V
–20
mA
IOL
Current required from a low-level output
VOL = 0.4 V
15
mA
20
30
°C
-40
80
°C
ENVIRONMENTAL
Case temperature – operational
TC
(5)
Case temperature – non-operational
TGRADIENT
(5)
Device temperature gradient – operational
(6)
Relative humidity (non-condensing)
(1)
(2)
(3)
(4)
(5)
(6)
5
°C
95
%RH
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS (ground).
Voltages VCC, VCCI, and VCC2 are required for proper DMD operation.
Exceeding the recommended allowable absolute voltage difference between VCC and VCCI may result in excess current draw. The
difference between VCC and VCCI, | VCC – VCCI|, should be less than the specified limit.
DMD Temperature is the worst-case of any test point shown in Case Temperature , or the active array as calculated by the Micromirror
Array Temperature Calculation .
As measured between any two points on the exterior of the package, or as predicted between any two points inside the micromirror
array cavity. Refer to Case Temperature and Micromirror Array Temperature Calculation .
7.2 Storage Conditions
are applicable before the DMD is installed in the final product.
Tstg
Storage temperature
Relative humidity (non-condensing)
MIN
MAX
-40
80
UNIT
°C
95
%RH
7.3 ESD Ratings
VALUE
V(ESD)
(1)
10
Electrostatic
discharge
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
All pins except MBRST[0:15]
±2000
MBRST[0:15] pins
<250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible if necessary precautions are taken.
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7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
NOM
MAX
UNIT
3.0
3.3
3.6
V
3.0
3.3
3.6
V
7.25
7.5
7.75
V
26.5
V
0.3
V
ELECTRICAL
VCC
Supply voltage for LVCMOS core logic
(2) (3)
(2) (3)
VCCI
Supply voltage for LVDS receivers
VCC2
Mirror electrode and HVCMOS supply voltage
VMBRST
Clocking pulse waveform voltage applied to MBRST[15:0] input pins (supplied by DLPA200)
|VCC – VCCI|
Supply voltage delta (absolute value)
(2) (3)
–27
(3)
ENVIRONMENTAL - For Illumination Source between 363 and 420 nm
< 363 nm
Illumination power density
(4) (5)
(6)
363 to 420 nm
2
mW/cm2
2.5
(7)
W/cm2
3.7
> 420 nm
(8) (9)
TC
Case/array temperature
TGRADIENT
Device temperature gradient – operational
20
30
(11)
Relative humidity (non-condensing)
Operating landed duty cycle
(12)
W
(7)
W/cm2
(10)
°C
Thermally limited
5
°C
95
%RH
25%
(1)
The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by
the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the
Recommended Operating Conditions limits.
(2) All voltages referenced to VSS (ground).
(3) Voltages VCC, VCCI, and VCC2, are required for proper DMD operation.
(4) Various application parameters can affect optimal, long-term performance of the DMD, including illumination spectrum, illumination
power density, micromirror landed duty cycle, ambient temperature (both storage and operating), case temperature, and power-on or
power-off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle.
(5) Total integrated illumination power density, above or below the indicated wavelength threshold.
(6) The maximum operating conditions for operating temperature and illumination power density for wavelengths < 363 nm should not be
implemented simultaneously.
(7) Also limited by the resulting micromirror array temperature. Refer to Micromirror Array Temperature Calculation for information related to
calculating the micromirror array temperature.
(8) In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. Refer to Micromirror
Array Temperature Calculation for further details.
(9) Temperature is the highest measured value of any test point shown in Figure 17 or the active array as calculated by the Micromirror
Array Temperature Calculation.
(10) Refer to Micromirror Array Temperature Calculation for thermal test point locations, package thermal resistance, and device
temperature calculation.
(11) As measured between any two points on the exterior of the package, or as predicted between any two points inside the micromirror
array cavity. Refer to Case Temperature and Micromirror Array Temperature Calculation.
(12) Landed duty cycle refers to the percentage of time an individual micromirror spends landed in one state (12° or –12°) versus the other
state (–12° or 12°).
7.5 Thermal Information
DLP7000UV
THERMAL METRIC
(1) (2)
FLP (LCCC)
UNIT
203 PINS
Active micromirror array resistance to TP1
(1)
(2)
0.9
°C/W
The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate
heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the
Recommended Operating Conditions . The total heat load on the DMD is largely driven by the incident light absorbed by the active area;
although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical
systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in
this area can significantly degrade the reliability of the device.
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.6 Electrical Characteristics
over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted)
PARAMETERS
TEST CONDITIONS
High-level output voltage
See Figure 10
(1)
VOL
Low-level output voltage
See Figure 10
(1)
VMBRST
Clocking Pulse Waveform applied to
MBRST[29:0] Input Pins (supplied
by DLPA200)
IOZ
High impedance output current
IOH
High-level output current
(1)
Low-level output current
(1)
VOH
IOL
,
,
(1)
VCC = 3.0 V,
IOH = –20 mA
VCC = 3.6 V,
IOH = 15 mA
MIN
TYP
MAX
UNIT
2.4
V
-27
VCC = 3.6 V
0.4
V
26.5
V
10
µA
VOH = 2.4 V, VCC ≥ 3 V
–20
VOH = 1.7 V, VCC ≥ 2.25 V
–15
VOL = 0.4 V, VCC ≥ 3 V
15
VOL = 0.4 V, VCC ≥ 2.25 V
14
mA
mA
High-level input voltage
(1)
1.7
VCC + .3
V
Low-level input voltage
(1)
–0.3
0.7
V
IIL
Low-level input current
(1)
µA
IIH
High-level input current
ICC
Current into VCC pin
ICCI
Current into VCCI pin
ICC2
Current into VCC2 pin
PD
Power dissipation
ZIN
Internal differential impedance
95
ZLINE
Line differential impedance (PWB,
Trace)
90
VIH
VIL
(1)
(2)
(1)
Input capacitance
CO
Output capacitance
CIM
Input capacitance for MBRST[0:15]
pins
12
VI = 0 V
–60
VCC = 3.6 V,
VI = VCC
200
µA
VCC = 3.6 V,
1475
mA
VCCI = 3.6 V
450
mA
25
mA
VCC2 = 8.75 V
2.0
CI
(1)
(2)
VCC = 3.6 V,
(1)
W
105
Ω
110
Ω
f = 1 MHz
10
pF
f = 1 MHz
10
pF
270
pF
f = 1 MHz
220
100
Applies to LVCMOS pins only.
Exceeding the maximum allowable absolute voltage difference between VCC and VCCI may result in excess current draw. See the
Absolute Maximum Ratings for details.
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7.7 LVDS Timing Requirements
over operating free-air temperature range (unless otherwise noted); see Figure 1
MIN
fDCLK_*
DCLK_* clock frequency {where * = [A, or B]}
200
tc
Clock cycle - DLCK_*
2.5
tw
Pulse width - DLCK_*
ts
Setup time - D_*[15:0] and SCTRL_* before DCLK_*
th
Hold time, D_*[15:0] and SCTRL_* after DCLK_*
tskew
Skew between bus A and B
NOM
MAX
UNIT
400
MHz
ns
1.25
ns
.35
ns
.35
ns
–1.25
1.25
ns
tw
DCLK_AN
DCLK_AP
th
tw
tc
ts
ts
th
SCTRL_AN
SCTRL_AP
tskew
D_AN(15:0)
D_AP(15:0)
DCLK_BN
DCLK_BP
th
tw
tw
tc
th
ts
ts
SCTRL_BN
SCTRL_BP
D_BN(15:0)
D_BP(15:0)
Figure 1. LVDS Timing Waveforms
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7.8 LVDS Waveform Requirements
over operating free-air temperature range (unless otherwise noted); see Figure 2
MIN
|VID|
Input differential voltage (absolute difference)
VCM
Common mode voltage
VLVDS
LVDS voltage
tr
tr
100
NOM
MAX
UNIT
400
600
mV
1200
mV
0
2000
mV
Rise time (20% to 80%)
100
400
ps
Fall time (80% to 20%)
100
400
ps
VLVDS
(v)
VLVDSmax = VCM + |½VID|
VLVDSmax
Tf (20% - 80%)
VLVDS = V CM +/- | 1/2 V ID |
VID
VCM
T r (20% - 80%)
VLVDS min
VLVDS min = 0
Time
Figure 2. LVDS Waveform Requirements
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7.9 Serial Control Bus Timing Requirements
over operating free-air temperature range (unless otherwise noted); see Figure 3 and Figure 4
MIN
NOM
MAX
UNIT
50
500
kHz
–300
300
ns
960
ns
fSCP_CLK
SCP clock frequency
tSCP_SKEW
Time between valid SCP_DI and rising edge of SCP_CLK
tSCP_DELAY
Time between valid SCP_DO and rising edge of SCP_CLK
t SCP_EN
Time between falling edge of SCP_EN and the first rising edge of
SCP_CLK
t_SCP
Rise time for SCP signals
200
ns
tf_SCP
Fall time for SCP signals
200
ns
30
tc
SCPCLK
ns
fclock = 1 / tc
50%
50%
tSCP_SKEW
SCPDI
50%
tSCP_DELAY
SCPD0
50%
Figure 3. Serial Communications Bus Timing Parameters
tr_SCP
tf_SCP
Input Controller VCC
SCP_CLK,
SCP_DI,
SCP_EN
VCC/2
0v
Figure 4. Serial Communications Bus Waveform Requirements
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7.10 Systems Mounting Interface Loads
PARAMETER
Maximum system mounting interface
load to be applied to the:
MAX
UNIT
Thermal interface area (see Figure 5)
111
N
Electrical interface area
423
N
400
N
Datum A Interface area (see Figure 5 )
(1)
MIN
(1)
NOM
Combined loads of the thermal and electrical interface areas in excess of Datum A load shall be evenly distributed outside the Datum A
area (423+ 111 – Datum A).
Figure 5. System Interface Loads
16
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7.11 Micromirror Array Physical Characteristics
M
Number of active columns
N
Number of active rows
P
Micromirror (pixel) pitch
Micromirror active array width
M×P
Micromirror active array height
N×P
Micromirror active border
Pond of micromirror (POM)
(1)
VALUE
UNIT
1024
micromirrors
768
micromirrors
13.68
µm
14.008
mm
10.506
mm
10
micromirrors/side
M±4
M±3
M±2
M±1
The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
0
1
2
3
(1)
See Figure 6
0
1
2
3
DMD Active Array
NxP
M x N Micromirrors
N±4
N±3
N±2
N±1
MxP
P
Pond of micromirrors (POM) omitted for clarity.
Details omitted for clarity.
P
Not to scale.
P
P
Refer to Micromirror Array Physical Characteristics for M, N, and P specifications.
Figure 6. Micromirror Array Physical Characteristics
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7.12 Micromirror Array Optical Characteristics
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
PARAMETER
a
β
TEST CONDITIONS
Micromirror tilt angle
Micromirror tilt angle tolerance
MIN
DMD parked state (1) (2) (3), See
Figure 12
See Figure 12
degrees
–1
16
(12)
Micromirror array optical efficiency
(13) (14)
degrees
µs
µs
10
Adjacent micromirrors
Orientation of the micromirror axis-of-rotation
1
22
43
Non-adjacent micromirrors
Non operating micromirrors (11)
See Figure 11
363 to 420 nm, with all micromirrors
in the ON state
UNIT
12
Micromirror crossover time (9)
Micromirror switching time at 400 MHz with
global reset (10)
MAX
0
DMD landed state (1) (4) (5)
See Figure 12
(1) (4) (6) (7) (8)
NOM
0
44
45
46
micromirrors
degrees
66%
(1) Measured relative to the plane formed by the overall micromirror array.
(2) Parking the micromirror array returns all of the micromirrors to an essentially flat (0˚) state (as measured relative to the plane formed by
the overall micromirror array).
(3) When the micromirror array is parked, the tilt angle of each individual micromirror is uncontrolled.
(4) Additional variation exists between the micromirror array and the package datums, as shown in the Mechanical, Packaging, and
Orderable Information .
(5) When the micromirror array is landed, the tilt angle of each individual micromirror is dictated by the binary contents of the CMOS
memory cell associated with each individual micromirror. A binary value of 1 will result in a micromirror landing in an nominal angular
position of +12°. A binary value of 0 results in a micromirror landing in an nominal angular position of –12°.
(6) Represents the landed tilt angle variation relative to the Nominal landed tilt angle.
(7) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(8) For some applications, it is critical to account for the micromirror tilt angle variation in the overall System Optical Design. With some
System Optical Designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some System Optical Designs, the micromirror tilt angle variation between devices may result
in colorimetry variations and/or system contrast variations.
(9) Micromirror Cross Over time is primarily a function of the natural response time of the micromirrors.
(10) Micromirror switching is controlled and coordinated by the DLPC410 (DLPS024) and DLPA200 (DLPS015). Nominal Switching time
depends on the system implementation and represents the time for the entire micromirror array to be refreshed.
(11) Non-operating micromirror is defined as a micromirror that is unable to transition nominally from the –12° position to +12° or vice versa.
(12) Measured relative to the package datums B and C, shown in the Mechanical, Packaging, and Orderable Information
(13) The minimum or maximum DMD optical efficiency observed depends on numerous application-specific design variables, such as:
– Illumination wavelength, bandwidth/line-width, degree of coherence
– Illumination angle, plus angle tolerance
– Illumination and projection aperture size, and location in the system optical path
– IIlumination overfill of the DMD micromirror array
– Aberrations present in the illumination source and/or path
– Aberrations present in the projection path
The specified nominal DMD optical efficiency is based on the following use conditions:
– Visible illumination (363 to 420 nm)
– Input illumination optical axis oriented at 24° relative to the window normal
– Projection optical axis oriented at 0° relative to the window normal
– f / 3.0 illumination aperture
– f / 2.4 projection aperture
Based on these use conditions, the nominal DMD optical efficiency results from the following four components:
– Micromirror array fill factor: nominally 92%
– Micromirror array diffraction efficiency: nominally 85%
– Micromirror surface reflectivity: nominally 88%
18
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–
Window transmission: nominally 98% for wavelengths 363nm to 420nm, applies to all angles 0° to 30° AOI (Angle of Incidence)
(single pass, through two surface transitions)
(14) Does not account for the effect of micromirror switching duty cycle, which is application dependent. Micromirror switching duty cycle
represents the percentage of time that the micromirror is actually reflecting light from the optical illumination path to the optical projection
path. This duty cycle depends on the illumination aperture size, the projection aperture size, and the micromirror array update rate.
7.13 Window Characteristics
PARAMETER
(1)
CONDITIONS
Window material designation
Corning 7056
Window refractive index
At wavelength 589 nm
Window flatness
(2)
MIN
4
(3)
Within the Window Aperture
Window aperture
See
Illumination overfill
Refer to Illumination Overfill
Window transmittance, single–pass
through both surfaces and glass (5)
Within the wavelength range 363nm to 420nm. Applies to all
angles 0 to 30 AOI
(5)
MAX
UNIT
1.487
Per 25 mm
Window artifact size
(1)
(2)
(3)
(4)
TYP
400
fringes
µm
(4)
98%
See Window Characteristics and Optics for more information.
At a wavelength of 632.8 nm.
See the section at the end of this document for details regarding the size and location of the window aperture.
For details regarding the size and location of the window aperture, see the package mechanical characteristics listed in the Mechanical
ICD in the Mechanical, Packaging, and Orderable Information section.
See the TI application report Wavelength Transmittance Considerations for DMD Window, DLPA031.
7.14 Chipset Component Usage Specification
The DLP7000UV is a component of one or more DLP® chipsets. Reliable function and operation of the
DLP7000UV requires that it be used in conjunction with the other components of the applicable DLP® chipset,
including those components that contain or implement TI DMD control technology. TI DMD control technology is
the TI technology and devices for operating or controlling a DLP® DMD.
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8 Detailed Description
8.1 Overview
Optically, the DLP7000UV consists of 786,432 highly reflective, digitally switchable, micrometer-sized mirrors
(micromirrors), organized in a two-dimensional array of 1024 micromirror columns by 768 micromirror rows (
Figure 11). Each aluminum micromirror is approximately 13.68 microns in size (see the Micromirror Pitch in
Figure 11), and is switchable between two discrete angular positions: –12° and +12°. The angular positions are
measured relative to a 0° flat state, which is parallel to the array plane (see Figure 12). The tilt direction is
perpendicular to the hinge-axis which is positioned diagonally relative to the overall array. The On State landed
position is directed towards Row 0, Column 0 (upper left) corner of the device package (see the Micromirror
Hinge-Axis Orientation in Figure 11). In the field of visual displays, the 1024 by 768 pixel resolution is referred to
as XGA.
Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a
specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell
contents, after the micromirror clocking pulse is applied. The angular position (–12° or +12°) of the individual
micromirrors changes synchronously with a micromirror clocking pulse, rather than being synchronous with the
CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a micromirror
clocking pulse will result in the corresponding micromirror switching to a +12° position. Writing a logic 0 into a
memory cell followed by a micromirror clocking pulse will result in the corresponding micromirror switching to a
–12° position.
Updating the angular position of the micromirror array consists of two steps. First, updating the contents of the
CMOS memory. Second, application of a Micromirror Clocking Pulse to all or a portion of the micromirror array
(depending upon the configuration of the system). Micromirror Clocking Pulses are generated externally by a
DLPA200, with application of the pulses being coordinated by the DLPC410 controller.
Around the perimeter of the 1024 by 768 array of micromirrors is a uniform band of active border micromirrors.
The pond of micromirror (POM) is not user-addressable. The border micromirrors land in the –12° position once
power has been applied to the device. There are 10 border micromirrors on each side of the 1024 by 768 active
array.
Figure 7 shows a DLPC410 and DLP7000UV Chipset Block Diagram. The DLPC410 and DLPA200 control and
coordinate the data loading and micromirror switching for reliable DLP7000UV operation. The DLPR410 is the
programmed PROM required to properly configure the DLPC410 controller. For more information on the chipset
components, see Application and Implementation . For a typical system application using the DLP Discovery
4100 chipset including the DLP7000UV, see Figure 19.
20
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8.2 Functional Block Diagram
PWRDN
DLP7000UV
Figure 7. DLPC410 and DLP7000UV Chipset Block Diagram
8.3 Feature Description
Table 1. DLPC410 DMD Types Overview
DMD
ARRAY
DLP7000UV - 0.7” XGA
1024 × 768
(1)
PATTERNS/s
32552
DATA RATE (Gbs)
MIRROR PITCH
25.6
13.6 μm
(1)
This is for single block mode resets.
Figure 7 is a simplified system block diagram showing the use of the following components:
•
DLPC410
– Xilinx [XC5VLX30] FPGA configured to provide high-speed DMD data and control,
and DLPA200 timing and control
•
DLPR410
– [XCF16PFSG48C] serial flash PROM contains startup configuration information
(EEPROM)
•
DLPA200
– DMD micromirror driver for the DLP7000UV DMD
•
DLP7000UV
– Spatial Light Modulator (DMD)
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8.3.1 DLPC410 Controller
The DLP7000UV chipset includes the DLPC410 controller which provides a high-speed LVDS data and control
interface for DMD control. This interface is also connected to a second FPGA used to drive applications (not
included in the chipset). The DLPC410 generates DMD and DLPA200 initialization and control signals in
response to the inputs on the control interface.
For more information, see the DLPC410 data sheet (DLPS024).
8.3.2 DLPA200 DMD Micromirror Driver
DLPA200 micromirror driver provides the micromirror clocking pulse driver functions for the DMD. One DLPA200
is required for DLP7000UV.
For more information on the DLPA200, see the DLPA200 data sheet (DLPS015).
8.3.3 Flash Configuration PROM
The DLPC410 is configured at startup from the serial flash PROM. The contents of this PROM can not be
altered. For more information, see the DLPC410 data sheet (DLPS024) and DLPR410 data sheet (DLPS027).
8.3.4 DMD
8.3.4.1 DLP7000UV Chipset Interfaces
This section will describe the interface between the different components included in the chipset. For more
information on component interfacing, see Application and Implementation .
8.3.4.1.1 DLPC410 Interface Description
8.3.4.1.1.1 DLPC410 IO
Table 2 describes the inputs and outputs of the DLPC410 to the user. For more details on these signals, see the
DLPC410 data sheet.
Table 2. Input/Output Description
PIN NAME
DESCRIPTION
I/O
ARST
Asynchronous active low reset
I
CLKIN_R
Reference clock, 50 MHz
I
DIN_[A,B,C,D](15:0)
LVDS DDR input for data bus A,B,C,D (15:0)
I
DCLKIN[A,B,C,D]
LVDS inputs for data clock (200 - 400 MHz) on bus A, B, C, and D
I
DVALID[A,B,C,D]
LVDS input used to start write sequence for bus A, B, C, and D
I
ROWMD(1:0)
DMD row address and row counter control
I
ROWAD(10:0)
DMD row address pointer
I
BLK_AD(3:0)
DMD mirror block address pointer
I
BLK_MD(1:0)
DMD mirror block reset and clear command modes
I
PWR_FLOAT
Used to float DMD mirrors before complete loss of power
I
DMD_TYPE(3:0)
DMD type in use
O
RST_ACTIVE
Indicates DMD mirror reset in progress
O
INIT_ACTIVE
Initialization in progress.
O
VLED0
System heartbeat signal
O
VLED1
Denotes initialization complete
O
8.3.4.1.1.2 Initialization
The INIT_ACTIVE ( Table 2) signal indicates that the DLP7000UV, DLPA200, and DLPC410 are in an
initialization state after power is applied. During this initialization period, the DLPC410 is initializing the
DLP7000UV and DLPA200 by setting all internal registers to their correct states. When this signal goes low, the
system has completed initialization. System initialization takes approximately 220 ms to complete. Data and
command write cycles should not be asserted during the initialization.
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During initialization the user must send a training pattern to the DLPC410 on all data and DVALID lines to
correctly align the data inputs to the data clock. For more information, see the DLPC410 data sheet – Interface
Training Pattern.
8.3.4.1.1.3 DMD Device Detection
The DLPC410 automatically detects the DMD type and device ID. DMD_TYPE ( Table 2) is an output from the
DLPC410 that contains the DMD information. Only DMDs sold with the chipset or kit are recognized by the
automatic detection function. All other DMDs do not operate with the DLPC410.
8.3.4.1.1.4 Power Down
To ensure long term reliability of the DLP7000UV, a shutdown procedure must be executed. Prior to power
removal, assert the PWR_FLOAT ( Table 2) signal and allow approximately 300 µs for the procedure to
complete. This procedure assures the mirrors are in a flat state.
8.3.4.2 DLPC410 to DMD Interface
8.3.4.2.1 DLPC410 to DMD IO Description
Table 3 lists the available controls and status pin names and their corresponding signal type, along with a brief
functional description.
Table 3. DLPC410 to DMD I/O Pin Descriptions
PIN NAME
DESCRIPTION
I/O
DDC_DOUT_[A,B,C,D](15:0)
LVDS DDR output to DMD data bus A,B,C,D (15:0)
O
DDC_DCLKOUT_[A,B,C,D]
LVDS output to DMD data clock A,B,C,D
O
DDC_SCTRL_[A,B,C,D]
LVDS DDR output to DMD data control A,B,C,D
O
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8.3.4.2.2 Data Flow
Figure 8 shows the data traffic through the DLPC410. Special considerations are necessary when laying out the
DLPC410 to allow best signal flow.
LVDS BUS A
sDIN_A(15:0)
sDCLK_A
sDVALID_A
LVDS BUS B
sDIN_B(15:0)
sDCLK_B
sDVALID_B
LVDS BUS D
LVDS BUS C
sDIN_D(15:0)
sDCLK_D
sDVALID_D
sDIN_C(15:0)
sDCLK_C
sDVALID_C
DLPC410
LVDS BUS D
LVDS BUS A
sDOUT_D(15:0)
sDCLKOUT_D
sSCTRL_D
sDOUT_A(15:0)
sDCLKOUT_A
sSCTRL_A
LVDS BUS C
sDOUT_C(15:0)
sDCLKOUT_C
sSCTRL_C
LVDS BUS B
sDIN_B(15:0)
sDCLK_B
sDVALID_B
Figure 8. DLPC410 Data Flow
Two LVDS buses transfer the data from the user to the DLPC410. Each bus has its data clock that is input edge
aligned with the data (DCLK). Each bus also has its own validation signal that qualifies the data input to the
DLPC410 (DVALID).
Output LVDS buses transfer data from the DLPC410 to the DLP7000UV. Output buses LVDS A and LVDS B are
used as highlighted in Figure 8.
8.3.4.3 DLPC410 to DLPA200 Interface
8.3.4.3.1 DLPA200 Operation
The DLPA200 DMD Micromirror Driver is a mixed-signal Application Specific Integrated Circuit (ASIC) that
combines the necessary high-voltage power supply generation and Micromirror Clocking Pulse functions for a
family of DMDs. The DLPA200 is programmable and controllable to meet all current and anticipated DMD
requirements.
The DLPA200 operates from a +12 volt power supply input. For more detailed information on the DLPA200, see
the DLPA200 data sheet.
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8.3.4.3.2 DLPC410 to DLPA200 IO Description
The Serial Communications Port (SCP) is a full duplex, synchronous, character-oriented (byte) port that allows
exchange of commands from the DLPC410 to the DLPA200. One SCP bus is used for the DLP7000UV.
DLPA200
SCP bus
DLPC410
SCP bus
DLPA200
(Only with 1080p DMD)
Figure 9. Serial Port System Configuration
There are five signal lines associated with the SCP bus: SCPEN, SCPCK, SCPDI, SCPDO, and IRQ .
Table 4 lists the available controls and status pin names and their corresponding signal type, along with a brief
functional description.
Table 4. DLPC410 to DLPA200 I/O Pin Descriptions
PIN NAME
DESCRIPTION
I/O
A_SCPEN
Active low chip select for DLPA200 serial bus
O
A_STROBE
DLPA200 control signal strobe
O
A_MODE(1:0)
DLPA200 mode control
O
A_SEL(1:0)
DLPA200 select control
O
A_ADDR(3:0)
DLPA200 address control
O
B_SCPEN
Active low chip select for DLPA200 serial bus (2)
O
B_STROBE
DLPA200 control signal strobe (2)
O
B_MODE(1:0)
DLPA200 mode control
O
B_SEL(1:0)
DLPA200 select control
O
B_ADDR(3:0)
DLPA200 address control
O
The DLPA200 provides a variety of output options to the DMD by selecting logic control inputs: MODE[1:0],
SEL[1:0] and reset group address A[3:0] ( Table 4). The MODE[1:0] input determines whether a single output,
two outputs, four outputs, or all outputs, will be selected. Output levels (VBIAS, VOFFSET, or VRESET) are
selected by SEL[1:0] pins. Selected outputs are tri-stated on the rising edge of the STROBE signal and latched
to the selected voltage level after a break-before-make delay. Outputs will remain latched at the last Micromirror
Clocking Pulse waveform level until the next Micromirror Clocking Pulse waveform cycle.
8.3.4.4 DLPA200 to DLP7000UV Interface Overview
The DLPA200 generates three voltages: VBIAS, VRESET, and VOFFSET that are supplied to the DMD MBRST
lines in various sequences through the Micromirror Clocking Pulse driver function. VOFFSET is also supplied
directly to the DMD as DMDVCC2. A fourth DMD power supply, DMDVCC, is supplied directly to the DMD by
regulators.
The function of the Micromirror Clocking Pulse driver is to switch selected outputs in patterns between the three
voltage levels (VBIAS, VRESET and VOFFSET) to generate one of several Micromirror Clocking Pulse
waveforms. The order of these Micromirror Clocking Pulse waveform events is controlled externally by the logic
control inputs and timed by the STROBE signal. DLPC410 automatically detects the DMD type and then uses the
DMD type to determine the appropriate Micromirror Clocking Pulse waveform.
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A direct Micromirror Clocking Pulse operation causes a mirror to transition directly from one latched state to the
next. The address must already be set up on the mirror electrodes when the Micromirror Clocking Pulse is
initiated. Where the desired mirror display period does not allow for time to set up the address, a Micromirror
Clocking Pulse with release can be performed. This operation allows the mirror to go to a relaxed state
regardless of the address while a new address is set up, after which the mirror can be driven to a new latched
state.
A mirror in the relaxed state typically reflects light into a system collection aperture and can be thought of as off
although the light is likely to be more than a mirror latched in the off state. System designers should carefully
evaluate the impact of relaxed mirror conditions on optical performance.
8.3.5 Measurement Conditions
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. Figure 10 shows an equivalent test load circuit for the
output under test. The load capacitance value stated is only for characterization and measurement of AC timing
signals. This load capacitance value does not indicate the maximum load the device is capable of driving. All rise
and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH
MIN for output clocks.
LOAD CIRCUIT
RL
From Output
Under Test
Tester
Channel
CL = 50 pF
CL = 5 pF for Disable Time
Figure 10. Test Load Circuit for AC Timing Measurements
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Incident
Illumination
Package Pin
A1 Corner
Details Omitted For Clarity.
Not To Scale.
DMD
Micromirror
Array
0
(Border micromirrors eliminated for clarity)
M±1
Active Micromirror Array
0
N±1
Micromirror Hinge-Axis Orientation
Micromirror Pitch
P (um)
45°
P (um)
P (um)
³2Q-6WDWH´
Tilt Direction
³2II-6WDWH´
Tilt Direction
P (um)
Figure 11. DMD Micromirror Array, Pitch, and Hinge-Axis Orientation
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Ill Inc
um id
in en
at t
io
n
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Package Pin
A1 Corner
Ill Inc
um id
in en
at t
io
n
DLP7000UV
Two
“On-State”
Micromirrors
For Reference
h
Pat
nt
ide ht
Inc n-Lig
atio
m in
Illu
h
t
nt t Pa
ide gh
Inc on-Li
ati
m in
Illu
Projected-Light
Path
Two
“Off-State”
Micromirrors
ht
ig
-L
te h
a
St at
ff- P
Flat-State
( “parked” )
Micromirror Position
O
a±b
-a ± b
Silicon Substrate
“On-State”
Micromirror
Silicon Substrate
“Off-State”
Micromirror
Figure 12. Micromirror Landed Positions and Light Paths
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8.4 Device Functional Modes
8.4.1 DMD Operation
The DLP7000UV has only one functional mode, it is set to be highly optimized for low latency and high speed in
generating mirror clocking pulses and timings.
When operated with the DLPC410 controller in conjunction with the DLPA200 driver, the DLP7000UV can be
operated in several display modes. The DLP7000UV is loaded as 16 blocks of 48 rows each. Figure 13,
Figure 14, Figure 15, and Figure 16 show how the image is loaded by the different Micromirror Clocking Pulse
modes.
There are four Micromirror Clocking Pulse modes that determine which blocks are reset when a Micromirror
Clocking Pulse command is issued:
• Single block mode
• Dual block mode
• Quad block mode
• Global mode
8.4.1.1 Single Block Mode
In single block mode, a single block can be loaded and reset in any order. After a block is loaded, it can be reset
to transfer the information to the mechanical state of the mirrors.
Data Loaded
Reset
1 6 Re se t Line s
(0 – 15 )
Figure 13. Single Block Mode
8.4.1.2 Dual Block Mode
In dual block mode, reset blocks are paired together as follows (0-1), (2-3), (4-5) . . . (14-15). These pairs can be
reset in any order. After data is loaded a pair can be reset to transfer the information to the mechanical state of
the mirrors.
Data Loaded
Reset
1 6 Re se t Line s
(0 – 15 )
Figure 14. Dual Block Mode
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Device Functional Modes (continued)
8.4.1.3 Quad Block Mode
In quad block mode, reset blocks are grouped together in fours as follows (0-3), (4-7), (8-11) and (12-15). Each
quad group can be randomly addressed and reset. After a quad group is loaded, it can be reset to transfer the
information to the mechanical state of the mirrors.
1 6 Re se t Line s
(0 – 15 )
Data Loaded
Reset
Figure 15. Quad Block Mode
8.4.1.4 Global Mode
In global mode, all reset blocks are grouped into a single group and reset together. The entire DMD must be
loaded with the desired data before issuing a Global Reset to transfer the information to the mechanical state of
the mirrors.
1 6 Re se t Line s
(0 – 15 )
Data Loaded
Reset
Figure 16. Global Mode
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8.5 Window Characteristics and Optics
NOTE
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical
system operating conditions exceeding limits described previously.
8.5.1 Optical Interface and System Image Quality
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
8.5.2 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the
projection lens. The mirror tilt angle defines DMD capability to separate the ON optical path from any other light
path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other
system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt
angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination
numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.
8.5.3 Pupil Match
TI recommends the exit pupil of the illumination is nominally centered within 2° (two degrees) of the entrance
pupil of the projection optics. Misalignment of pupils can create objectionable artifacts in the display’s border
and/or active area, which may require additional system apertures to control, especially if the numerical aperture
of the system exceeds the pixel tilt angle.
8.5.4 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical
operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the
window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical
system should be designed to limit light flux incident anywhere on the window aperture from exceeding
approximately 10% of the average flux level in the active area. Depending on the particular system’s optical
architecture, overfill light may have to be further reduced below the suggested 10% level in order to be
acceptable.
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8.6 Micromirror Array Temperature Calculation
Achieving optimal DMD performance requires proper management of the maximum DMD case temperature, the
maximum temperature of any individual micromirror in the active array, the maximum temperature of the window
aperture, and the temperature gradient between case temperature and the predicted micromirror array
temperature. (See Figure 17).
See the Recommended Operating Conditions for applicable temperature limits.
8.6.1 Package Thermal Resistance
The DMD is designed to conduct absorbed and dissipated heat to the back of the Type A package where it can
be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the
package within the specified operational temperatures, refer to Figure 17. The total heat load on the DMD is
typically driven by the incident light absorbed by the active area; although other contributions include light energy
absorbed by the window aperture and electrical power dissipation of the array.
8.6.2 Case Temperature
The temperature of the DMD case can be measured directly. For consistency, Thermal Test Point locations 1, 2,
and 3 are defined, as shown in Figure 17.
INCIDENT
LIGHT
A
A
1
2
1
ARRAY
3X (15.88 [.625])
2
3
1
2
3
(10.16 [.400])
Figure 17. Thermal Test Point Location
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Micromirror Array Temperature Calculation (continued)
8.6.3 Micromirror Array Temperature Calculation
Active array temperature cannot be measured directly; therefore, it must be computed analytically from
measurement points on the outside of the package, package thermal resistance, electrical power, and
illumination heat load. The relationship between array temperature and the reference ceramic temperature (test
point number 3 in Figure 17) is provided by the following equations:
TArray = Measured Ceramic temperature at location (test point number 3) + (Temperature increase due to power incident
to the array × array-to-ceramic resistance)
(1)
TArray = TCeramic+ (QArray × RArray-To-Ceramic)
where
•
•
•
•
TCeramic = Measured ceramic temperature (°C) at location (test point number 3)
RArray-To-Ceramic = DMD package thermal resistance from array to outside ceramic (°C/W)
QArray = Total DMD array power, which is both electrical plus absorbed on the DMD active array (W)
QArray = QElectrical + (QIllumination × DMD absorption constant (0.42))
where
•
•
•
QElectrical = Approximate nominal electrical internal power dissipation (W)
QIllumination = [Illumination power density × illumination area on DMD] (W)
DMD absorption constant = 0.42
(2)
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating
frequencies. The nominal electrical power dissipation of the DMD is variable and depends on the operating state
of mirrors and the intensity of the light source. The DMD absorption constant of 0.42 assumes nominal operation
with an illumination distribution of 83.7% on the active array, 11.9% on the array border, and 4.4% on the window
aperture. A system aperture may be required to limit power incident on the package aperture since this area
absorbs much more efficiently than the array.
Sample Calculation:
• Illumination power density = 2 W/cm2
• Illumination area = (1.4008 cm × 1.0506 cm) / 83.7% = 1.76 cm2 (assumes 83.7% on the active array and
16.3% overfill)
• QIllumination= 2 W/cm2 × 1.76 cm 2= 3.52 W
• QElectrical= 2.0 W
• RArray-To-Ceramic = 0.9 °C/W
• TCeramic= 20°C (measured on ceramic)
• QArray = 2.0 W + (3.52 W × 0.42) = 3.48 W
• TArray = 20°C + (3.48 W × 0.9°C/W) =23.1°C
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8.7 Micromirror Landed-On/Landed-Off Duty Cycle
8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the On–state versus the amount of time the same
micromirror is landed in the Off–state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On-state 100% of the
time (and in the Off-state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off-state 100% of
the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages)
always add to 100.
8.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD’s usable life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
8.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this
interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s
usable life.
In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at
for a give long-term average Landed Duty Cycle.
8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the
pixel will experience a 0/100 Landed Duty Cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in Table 5.
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Table 5. Grayscale Value and Landed Duty Cycle
GRAYSCALE VALUE
LANDED DUTY CYCLE
0%
0/100
10%
10/90
20%
20/80
30%
30/70
40%
40/60
50%
50/50
60%
60/40
70%
70/30
80%
80/20
90%
90/10
100%
100/0
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DLP7000UV devices require they be coupled with the DLPC410 controller to provide a reliable solution for
many different applications. The DMDs are spatial light modulators which reflect incoming light from an
illumination source to one of two directions, with the primary direction being into a projection collection optic.
Each application is derived primarily from the optical architecture of the system and the format of the data
coming into the DLPC410. Applications of interest include lithography, 3D Printing, medical systems, and
compressive sensing.
9.1.1 DMD Reflectivity Characteristics
TI assumes no responsibility for end-equipment reflectivity performance. Achieving the desired end-equipment
reflectivity performance involves making trade-offs between numerous component and system design
parameters. DMD reflectivity characteristics over UV exposure times are represented in Figure 18.
100
90
Relative Reflectivity (%)
80
70
60
50
40
30
20
20qC
25qC
30qC
10
0
0
10000
20000
30000
Exposure Hours
40000
50000
D001
2.3 W/cm2, 363 to 400 nm
Figure 18. Nominal DMD Relative Reflectivity Percentage and Exposure Hours
DMD reflectivity includes micromirror surface reflectivity and window transmission. The DMD was characterized
for DMD reflectivity using a broadband light source (200-W metal-halide lamp). Data is based off of a 2.3-W/cm2
UV exposure at the DMD surface (363-nm peak output) using a 363-nm high-pass filter between the light source
and the DMD. (Contact your local Texas Instruments representative for additional information about power
density measurements and UV filter details.)
9.1.2 Design Considerations Influencing DMD Reflectivity
Optimal, long-term performance of the digital micromirror device (DMD) can be affected by various application
parameters. Below is a list of some of these application parameters and includes high level design
recommendations that may help extend relative reflectivity from time zero:
• Illumination spectrum – using longer wavelengths for operation while preventing shorter wavelengths from
striking the DMD
• Illumination power density – using lower power density
• DMD case temperature – operating the DMD with the case temperature at the low end of its specification
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Application Information (continued)
•
•
Cumulative incident illumination – limiting the total hours of UV illumination exposure when the DMD is not
actively steering UV light in the application. For example, a design might include a shutter to block the
illumination or LED illumination where the LEDs can be strobed off during periods not requiring UV exposure.
Micromirror landed duty cycle – applying a 50/50 duty cycle pattern during periods where operational patterns
are not required.
9.2 Typical Application
OPTICAL
SENSOR
LED
DRIVERS
(CAMERA)
LEDS
OPTICS
LED
SENSORS
USER
INTERFACE
LVDS BUS (A,B)
LVDS BUS (A,B)
DDC_DCLK, DVALID, DDC_DIN(15:0)
DDC_DCLKOUT, DDCSCTRL, DDC_DOUT(15:0)
SCP BUS
ROW and BLOCK SIGNALS
SCPCLK, SCPDO, SCPDI, DMD_SCPENZ, A_SCPENZ
ROWMD(1:0), ROWAD(10:0), BLKMD(1:0), BLKAD(3:0), RST2BLKZ
CONTROL SIGNALS
COMP_DATA, NS_FLIP, WDT_ENBLZ, PWR_FLOAT
CONNECTIVITY
USER - MAIN
PROCESSOR / FPGA
(USB, ETHERNET, ETC.)
DLPA200 CONTROL
A_MODE(1:0), A_SEL(1:0),
A_ADDR(3:0), OEZ, INIT
DLPC410 INFO SIGNALS
RST_ACTIVE, INIT_ACTIVE, ECP2_FINISHED,
DMD_TYPE(3:0), DDC_VERSION(2:0)
MBRST1_(15:0)
DLP7000UV
DLPA200
A
DLPC410
PGM SIGNALS
VOLATILE
and
NON-VOLATILE
STORAGE
DLPR410
PROM_CCK_DDC, PROGB_DDC,
PROM_DO_DDC, DONE_DDC, INTB_DDC
JTAG
ARSTZ
CLKIN_R
OSC
50 MHz
~
VLED0
VLED1
DMD_RESET
POWER MANAGMENT
Figure 19. DLPC410 and DLP7000UV Embedded Example Block Diagram
9.2.1 Design Requirements
All applications using the DLP7000UV chipset require both the controller and the DMD components for operation.
The system also requires an external parallel flash memory device loaded with the DLPC410 Configuration and
Support Firmware. The chipset has several system interfaces and requires some support circuitry. The following
interfaces and support circuitry are required:
• DLPC410 system interfaces:
– Control interface
– Trigger interface
– Input data interface
– Illumination interface
– Reference clock
• DLP7000UV interfaces:
– DLPC410 to DLP7000UV digital data
– DLPC410 to DLP7000UV control interface
– DLPC410 to DLP7000UV micromirror reset control interface
– DLPC410 to DLPA200 micromirror driver
– DLPA200 to DLP7000UV micromirror reset
Device Description:
The DLP7000UV XGA chipset offers developers a convenient way to design a wide variety of industrial, medical,
telecom and advanced display applications by delivering maximum flexibility in formatting data, sequencing data,
and light patterns.
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Typical Application (continued)
The DLP7000UV XGA chipset includes the following four components: DMD Digital Controller (DLPC410),
EEPROM (DLPR410), DMD Micromirror Driver (DLPA200), and a DMD (DLP7000UV).
DLPC410 DMD Digital Controller
• Provides high speed LVDS data and control interface to the DLP7000UV.
• Drives mirror clocking pulse and timing information to the DLPA200.
• Supports random row addressing.
DLPR410 EEPROM
• Contains startup configuration information for the DLPC410.
DLPA200 DMD Micromirror Driver
• Generates Micromirror Clocking Pulse control (sometimes referred to as a Reset) of DMD mirrors.
DLP7000UV: DMD
• Steers light in two digital positions (+12° and –12°) using 1024 × 768 micromirror array of aluminum mirrors.
Table 6. DLP Discovery 4100 Chipset Configurations: 0.7 XGA Chipset
QTY
TI PART
1
DLP7000UV
DESCRIPTION
1
DLPC410
DLP Discovery 4100 DMD controller
1
DLPR410
DLP Discovery 4100 configuration PROM
1
DLPA200
DMD micromirror driver
0.7 UV XGA Type A DMD
Reliable function and operation of DLP7000UV XGA chipsets require the components be used in conjunction
with each other. This document describes the proper integration and use of the DLP7000UV XGA chipset
components.
The DLP7000UV XGA chipset can be combined with a user programmable Application FPGA (not included) to
create high performance systems.
9.2.2 Detailed Design Procedure
The DLP7000UV DMD is designed with a window which allows transmission of Ultra-Violet (UV) light. This
makes it well suited for UV applications requiring fast, spatially programmable light patterns using the micromirror
array. UV wavelengths can affect the DMD differently than visible wavelengths. There are system level
considerations which should be leveraged when designing systems using this DMD.
38
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9.2.3 Application Curve
100
90
80
o
UV AOI = 0
Transmittance (%)
70
60
50
40
30
20
10
0
300
320
340
360
380
400
420
440
460
480
500
Wavelength (nm)
Type A UVA on 7056 glass (3-mm thick)
Figure 20. Corning 7056 Nominal UV Window Transmittance (Maximum Transmission Region)
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10 Power Supply Recommendations
10.1 Power-Up Sequence (Handled by the DLPC410)
The sequence of events for DMD system power-up is:
1. Apply logic supply voltages to the DLPA200 and to the DMD according to DMD specifications.
2. Place DLPA200 drivers into high impedance states.
3. Turn on DLPA200 bias, offset, or reset supplies according to driver specifications.
4. After all supply voltages are assured to be within the limits specified and with all micromirror clocking pulse
operations logically suspended, enable all drivers to either VOFFSET or VBIAS level.
5. Begin micromirror clocking pulse operations.
Repeated failure to adhere to the prescribed power-up and power-down procedures may affect device reliability.
The DLP7000UV power-up and power-down procedures are defined by the DLPC410 data sheet (DLPS024).
These procedures must be followed to ensure reliable operation of the device.
11 Layout
11.1 Layout Guidelines
The DLP7000UV is part of a chipset that is controlled by the DLPC410 in conjunction with the DLPA200. These
guidelines are targeted at designing a PCB board with these components.
11.1.1 Impedance Requirements
Signals should be routed to have a matched impedance of 50 Ω ±10% except for LVDS differential pairs
(DMD_DAT_Xnn, DMD_DCKL_Xn, and DMD_SCTRL_Xn), which should be matched to 100 Ω ±10% across
each pair.
11.1.2 PCB Signal Routing
When designing a PCB board for the DLP7000UV controlled by the DLPC410 in conjunction with the DLPA200,
the following are recommended:
Signal trace corners should be no sharper than 45°. Adjacent signal layers should have the predominate traces
routed orthogonal to each other. TI recommends that critical signals be hand routed in the following order: DDR2
Memory, DMD (LVDS signals), then DLPA200 signals.
TI does not recommend signal routing on power or ground planes.
TI does not recommend ground plane slots.
High speed signal traces should not crossover slots in adjacent power and/or ground planes.
Table 7. Important Signal Trace Constraints
SIGNAL
CONSTRAINTS
LVDS (DMD_DAT_xnn,
DMD_DCKL_xn, and
DMD_SCTRL_xn)
P-to-N data, clock, and SCTRL: <10 mils (0.25 mm); Pair-to-pair <10 mils (0.25 mm); Bundle-to-bundle
<2000 mils (50 mm, for example DMD_DAT_Ann to DMD_DAT_Bnn)
Trace width: 4 mil (0.1 mm)
Trace spacing: In ball field – 4 mil (0.11 mm); PCB etch – 14 mil (0.36 mm)
Maximum recommended trace length <6 inches (150 mm)
Table 8. Power Trace Widths and Spacing
SIGNAL NAME
40
MINIMUM TRACE
WIDTH
MINIMUM TRACE
SPACING
GND
Maximize
5 mil (0.13 mm)
VCC, VCC2
20 mil (0.51 mm)
10 mil (0.25 mm)
MBRST[15:0]
10 mil (0.25 mm)
10 mil (0.25 mm)
LAYOUT REQUIREMENTS
Maximize trace width to connecting pin as a minimum
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11.1.3 Fiducials
Fiducials for automatic component insertion should be 0.05-inch copper with a 0.1-inch cutout (antipad). Fiducials
for optical auto insertion are placed on three corners of both sides of the PCB.
11.1.4 PCB Layout Guidelines
A target impedance of 50 Ω for single ended signals and 100 Ω between LVDS signals is specified for all signal
layers.
11.1.4.1 DMD Interface
The digital interface from the DLPC410 to the DMD are LVDS signals that run at clock rates up to 400 MHz. Data
is clocked into the DMD on both the rising and falling edge of the clock, so the data rate is 800 MHz. The LVDS
signals should have 100-Ω differential impedance. The differential signals should be matched but kept as short
as possible. Parallel termination at the LVDS receiver is in the DMD; therefore, on board termination is not
necessary.
11.1.4.1.1 Trace Length Matching
The DLPC410 DMD data signals require precise length matching. Differential signals should have impedance of
100Ω (with 5% tolerance). It is important that the propagation delays are matched. The maximum differential pair
uncoupled length is 100 mils with a relative propagation delay of ±25 mil between the p and n. Matching all
signals exactly will maximize the channel margin. The signal path through all boards, flex cables and internal
DMD routing must be considered in this calculation.
11.1.4.2 DLP7000UV Decoupling
General decoupling capacitors for the DLP7000UV should be distributed around the PCB and placed to minimize
the distance from IC voltage and ground pads. Each decoupling capacitor (0.1 µF recommended) should have
vias directly to the ground and power planes. Via sharing between components (discreet or integrated) is
discouraged. The power and ground pads of the DLP7000UV should be tied to the voltage and ground planes
with their own vias.
11.1.4.2.1 Decoupling Capacitors
Decoupling capacitors should be placed to minimize the distance from the decoupling capacitor to the supply and
ground pin of the component. It is recommended that the placement of and routing for the decoupling capacitors
meet the following guidelines:
• The supply voltage pin of the capacitor should be located close to the device supply voltage pin(s). The
decoupling capacitor should have vias to ground and voltage planes. The device can be connected directly to
the decoupling capacitor (no via) if the trace length is less than 0.1 inch. Otherwise, the component should be
tied to the voltage or ground plane through separate vias.
• The trace lengths of the voltage and ground connections for decoupling capacitors and components should
be less than 0.1 inch to minimize inductance.
• The trace width of the power and ground connection to decoupling capacitors and components should be as
wide as possible to minimize inductance.
• Connecting decoupling capacitors to ground and power planes through multiple vias can reduce inductance
and improve noise performance.
• Decoupling performance can be improved by utilizing low ESR and low ESL capacitors.
11.1.4.3 VCC and VCC2
The VCC pins of the DMD should be connected directly to the DMD VCC plane. Decoupling for the VCC should
be distributed around the DMD and placed to minimize the distance from the voltage and ground pads. Each
decoupling capacitor should have vias directly connected to the ground and power planes. The VCC and GND
pads of the DMD should be tied to the VCC and ground planes with their own vias.
The VCC2 voltage can be routed to the DMD as a trace. Decoupling capacitors should be placed to minimize the
distance from the VCC2 and ground pads of the DMD. Using wide etch from the decoupling capacitors to the
DMD connection will reduce inductance and improve decoupling performance.
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11.1.4.4 DMD Layout
See the respective sections in this data sheet for package dimensions, timing and pin out information.
11.1.4.5 DLPA200
The DLPA200 generates the micromirror clocking pulses for the DMD. The DMD-drive outputs from the
DLPA200 (MBRST[15:0]) should be routed with minimum trace width of 11 mil and a minimum spacing of 15 mil.
The VCC and VCC2 traces from the output capacitors to the DLPA200 should also be routed with a minimum
trace width and spacing of 11 mil and 15 mil, respectively. See the DLPA200 customer data sheet (DLPS015) for
mechanical package and layout information.
11.2 Layout Example
For LVDS (and other differential signal) pairs and groups, it is important to match trace lengths. In the area of the
dashed lines, Figure 21 shows correct matching of signal pair lengths with serpentine sections to maintain the
correct impedance.
Figure 21. Mitering LVDS Traces to Match Lengths
42
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
Figure 22 provides a legend of reading the complete device name for any DLP device.
Figure 22. Device Nomenclature
12.1.1.1 Device Marking
The device marking consists of the fields shown in Figure 23.
TI Internal Numbering
DMD Part Number
2-Dimensional Matrix Code
(DMD Part Number and
Serial Number)
YYYYYYY
DLP7000UVFLP
GHXXXXX LLLLLLM
LLLLLL
Part 1 of Serial Number
Part 2 of Serial Number
(7 characters)
(7 characters)
TI Internal Numbering
Figure 23. Device Marking
12.2 Documentation Support
12.2.1 Related Documentation
The following documents contain additional information related to the use of the DLP7000UV device:
Table 9. Related Documentation
DOCUMENT TITLE
DOCUMENT LINK
DLPC410 Digital Controller data sheet
DLPS024
DLPA200 DMD Micromirror Driver data sheet
DLPS015
DLPR410 EEPROM data sheet
DLPS027
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12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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16-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
DLP7000UVFLP
ACTIVE
Package Type Package Pins Package
Drawing
Qty
LCCC
FLP
203
1
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
W NIPDAU
N / A for Pkg Type
Op Temp (°C)
Device Marking
(4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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16-Oct-2015
Addendum-Page 2
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