1Gb: x8, x16 Automotive DDR3L SDRAM Addendum

1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Description
Addendum Automotive DDR3L SDRAM
MT41K128M8 – 16 Meg x 8 x 8 banks
MT41K64M16 – 8 Meg x 16 x 8 banks
Description
•
•
•
•
•
•
This addendum provides information to add Automotive Ultra-high Temperature (AUT) option for the data
sheet. This addendum does not provide detailed information about the device. Refer to the data sheet (1Gb:
x8, x16 Automotive DDR3L SDRAM, Rev. B 2/15 EN)
for a complete description of device functionality, operating modes, and specifications for the same Micron
part number products. The 1.35V DDR3L SDRAM device is a low-voltage version of the 1.5V DDR3 SDRAM
device. Refer to the DDR3 (1.5V) SDRAM data sheet
specifications when running in 1.5V compatible
mode.
Options1
•
•
•
•
•
•
•
•
•
Marking
• Configuration
– 128 Meg x 8
– 64 Meg x 16
• FBGA package (Pb-free) – x8
– 78-ball FBGA (8mm x 10.5mm)
• FBGA package (Pb-free) – x16
– 96-ball FBGA (8mm x 14mm)
• Timing – cycle time
– 1.07ns @ CL = 13 (DDR3-1866)
• Product certification
– Automotive
• Operating temperature
– Industrial (–40°C ≤ T C ≤ +95°C)
– Automotive (–40°C ≤ T C ≤ +105°C)
– Ultra-high (–40°C ≤ T C ≤ +125°C)3
• Revision
Features
•
•
•
•
•
•
•
Write leveling
Multipurpose register
Output driver calibration
AEC-Q100
PPAP submission
8D response time
VDD = V DDQ = 1.35V (1.283V to 1.45V)
Backward compatible to V DD = V DDQ = 1.5V ±0.075V
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
Programmable CAS (READ) latency (CL)
Programmable CAS additive latency (AL)
Programmable CAS (WRITE) latency (CWL)
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
TC of –40°C to 125°C
– 64ms, 8192-cycle refresh at –40°C to 85°C
– 32ms at 85°C to 105°C
– 16ms at 105°C to 115°C
– 8ms at 115°C to 125°C
Self refresh temperature (SRT)
Automatic self refresh (ASR)
Notes:
128M8
64M16
DA
TW
-107
A
IT
AT
UT
:J
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
2. The datasheet does not support ×4 mode
even though ×4 mode description exists in
the following sections.
3. The UT option use based on automotive usage model. Contact Micron sales representative for further information.
Table 1: Key Timing Parameters
Speed Grade
Data Rate (MT/s)
Target tRCD-tRP-CL
-107
1866
13-13-13
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tRCD
(ns)
13.91
tRP
(ns)
13.91
CL (ns)
13.91
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Description
Table 2: Addressing
Parameter
128 Meg x 8
64 Meg x 16
Configuration
16 Meg x 8 x 8 banks
8 Meg x 16 x 8 banks
Refresh count
8K
8K
16K A[13:0]
8K A[12:0]
Row address
Bank address
8 BA[2:0]
8 BA[2:0]
Column address
1K A[9:0]
1K A[9:0]
1KB
2KB
Page Size
Figure 1: DDR3L Part Numbers
Example Part Number: MT41K64M16DA-107AAT:J
Configuration
Package
Speed
Revision
{
MT41K
:
:J
Configuration
Mark
128 Meg x 8
128M8
64 Meg x 16
64M16
Package
Temperature
Mark
78-ball FBGA, 8mm x 10.5mm
DA
96-ball FBGA, 8mm x 14mm
TW
Speed Grade
tCK = 1.07ns, CL = 13
Note:
Revision
Mark
Industrial temperature
IT
Automotive temperature
AT
Ultra-high temperature
UT
Mark
Certification
Mark
107
Automotive
A
1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com for available offerings.
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Functional Description
Functional Description
DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write
operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clockcycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK
going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select
the bank and the starting column location for the burst access.
The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM
allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
Industrial Temperature
The industrial temperature (IT) device requires that the case temperature not exceed
–40°C or 95°C. JEDEC specifications require the refresh rate to double when T C exceeds
85°C; this also requires use of the high-temperature self refresh option. Additionally,
ODT resistance and the input/output impedance must be derated when T C is <0°C or
>85°C.
Automotive Temperature
The automotive temperature (AT) device requires that the case temperature not exceed
–40°C or 105°C. JEDEC specifications require the refresh rate to double when T C exceeds
85°C; this also requires use of the high-temperature self refresh option. Additionally,
ODT resistance and the input/output impedance must be derated when T C is <0°C or
>85°C.
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Functional Description
Utra-high Temperature
The Utra-high temperature (UT) device requires that the case temperature not exceed
–40°C or 125°C. JEDEC specifications require the refresh rate to double when T C exceeds
85°C; this also requires use of the high-temperature auto refresh option. When T C >
+85°C, the refresh rate must be increased to 2X, when T C > +105°C, the refresh rate must
be increased to 4X and when T C > +115°C, the refresh rate must be increased to 8X. Selfrefresh mode is not available for T C > +105°C. Additionally, ODT resistance and the input/output impedance must be derated when T C is <0°C or >85°C.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL enable mode of operation (normal operation).
• Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ is to be
interpreted as any and all DQ collectively, unless specifically stated otherwise.
• The terms “DQS” and “CK” found throughout this data sheet are to be interpreted as
DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.
• Complete functionality may be described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements.
• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated is considered undefined, illegal, and not supported, and can result in unknown operation.
• Row addressing is denoted as A[n:0]. For example, 1Gb: n = 12 (x16); 1Gb: n = 13 (x4,
x8); 2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and 4Gb: n = 15 (x4,
x8).
• Dynamic ODT has a special use case: when DDR3 devices are architected for use in a
single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer
to the Dynamic ODT Special Use Case section.
• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be
used, use the lower byte for data transfers and terminate the upper byte as noted:
–
–
–
–
Connect UDQS to ground via 1kΩ* resistor.
Connect UDQS# to V DD via 1kΩ* resistor.
Connect UDM to V DD via 1kΩ* resistor.
Connect DQ[15:8] individually to either V SS, V DD, or V REF via 1kΩ resistors,* or float
DQ[15:8].
*If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT.
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Electrical Specifications
Electrical Specifications
Absolute Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 3: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
1
VDD
VDD supply voltage relative to VSS
–0.4
1.975
V
VDDQ
VDD supply voltage relative to VSSQ
–0.4
1.975
V
VIN, VOUT
Voltage on any pin relative to VSS
–0.4
1.975
V
0
95
°C
2, 3
Operating case temperature – Industrial
–40
95
°C
2, 3
Operating case temperature – Automotive
–40
105
°C
2, 3
Operating case temperature – Ultra-high
–40
125
°C
2, 3
Storage temperature
–55
150
°C
TC
TSTG
Operating case temperature – Commercial
Notes:
1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be
greater than 0.6 × VDDQ. When VDD and VDDQ are <500mV, VREF can be ≤300mV.
2. MAX operating case temperature. TC is measured in the center of the package.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation.
4. Ultra-high temperature use based on automotive usage model. Please contact Micron
sales representative if you have questions.
Input/Output Capacitance
Table 4: DDR3L Input/Output Capacitance
Note 1 applies to the entire table;
Capacitance
Parameters
DDR3L-1866
Symbol
Min
Max
Unit
CK and CK#
CCK
0.8
1.3
pF
ΔC: CK to CK#
Notes
CDCK
0.0
0.15
pF
Single-end I/O: DQ, DM
CIO
1.4
2.1
pF
2
Differential I/O: DQS, DQS#, TDQS, TDQS#
CIO
1.4
2.1
pF
3
CDDQS
0.0
0.15
pF
3
CDIO
–0.5
0.3
pF
4
CI
0.75
1.2
pF
5
CDI_CTRL
–0.4
0.2
pF
6
CDI_CMD_ADDR
–0.4
0.4
pF
7
ΔC: DQS to DQS#, TDQS, TDQS#
ΔC: DQ to DQS
Inputs (CTRL, CMD, ADDR)
ΔC: CTRL to CK
ΔC: CMD_ADDR to CK
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Thermal Characteristics
Table 4: DDR3L Input/Output Capacitance (Continued)
Note 1 applies to the entire table;
DDR3L-1866
Capacitance
Parameters
Symbol
Min
Max
Unit
ZQ pin capacitance
CZQ
–
3.0
pF
Reset pin capacitance
CRE
–
3.0
pF
Notes:
Notes
1. VDD = 1.35V (1.283–1.45V), VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25°C. VOUT(DC) = 0.5
× VDDQ, VOUT = 0.1V (peak-to-peak).
2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. CDDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately.
4. CDIO = CIO(DQ) - 0.5 × (CIO(DQS) + CIO(DQS#)).
5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =
A[n:0], BA[2:0].
6. CDI_CTRL = CI(CTRL) - 0.5 × (CCK(CK) + CCK(CK#)).
7. CDI_CMD_ADDR = CI(CMD_ADDR) - 0.5 × (CCK(CK) + CCK(CK#)).
Thermal Characteristics
Table 5: Thermal Characteristics
Parameter/Condition
Value
Units
Symbol
Notes
Operating case temperature –
Commercial
0 to +85
°C
TC
1, 2, 3
Operating case temperature –
Industrial
–40 to +95
°C
TC
1, 2, 3, 4
Operating case temperature –
Automotive
–40 to +105
°C
TC
1, 2, 3, 4
Operating case temperature –
Ultra-high
–40 to +125
°C
TC
1, 2, 3, 4, 6
78-ball “DA”
10.1
°C/W
ΘJC
5
96-ball “TW”
9.4
Junction-to-case (TOP)
Notes:
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1. MAX operating case temperature. TC is measured in the center of the package.
2. A thermal solution must be designed to ensure the DRAM device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9µs
interval refresh rate. The use of SRT or ASR must be enabled.
5. The thermal resistance data is based off of a number of samples from multiple lots and
should be viewed as a typical number.
6. Ultra-high temperature use based on automotive usage model. Please contact Micron
sales representative if you have questions.
6
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Thermal Characteristics
Figure 2: Thermal Measurement Point
(L/2)
Tc test point
L
(W/2)
W
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Electrical Characteristics – IDD Specifications
Electrical Characteristics – IDD Specifications
Table 6: IDD Maximum Limits
Symbol
Width
DDR3L
-1866
Units
Notes
Operating current 0: One bank ACTIVATE-to-PRECHARGE
IDD0
x8
36
mA
1, 2
Operating current 1: One bank ACTIVATE-toREAD-to-PRECHARGE
IDD1
Parameter
x16
46
mA
1, 2
x8
47
mA
1, 2
x16
63
mA
1, 2
Precharge power-down current: Slow exit
IDD2P0 (slow)
All
12
mA
1, 2, 6
Precharge power-down current: Fast exit
IDD2P1 (fast)
All
12
mA
1, 2, 6
Precharge quiet standby
IDD2Q
All
15
mA
1, 2, 6
Precharge standby current
IDD2N
All
17
mA
1, 2, 6
Precharge standby ODT current
IDD2NT
x8
27
mA
1, 2, 6
x16
28
mA
1, 2, 6
Active power-down current
IDD3P
All
14
mA
1, 2, 6
Active standby current
IDD3N
x8
26
mA
1, 2, 6
x16
28
mA
1, 2, 6
Burst read operating current
IDD4R
Burst write operating current
IDD4W
x8
95
mA
1, 2
x16
135
mA
1, 2
x8
99
mA
1, 2
x16
149
mA
1, 2
Burst refresh current
IDD5B
All
165
mA
1, 2
Room temperature self refresh
IDD6
All
12
mA
1, 2, 3, 7
Extended temperature self refresh
IDD6ET
All
14
mA
1, 4, 7
All banks interleaved read current
IDD7
x8
162
mA
1, 2
x16
219
mA
1, 2
Reset current
IDD8
All
14
mA
1, 2
Notes:
1.
2.
3.
4.
5.
TC = 85°C; SRT and ASR are disabled.
Enabling ASR could increase IDDx by up to an additional 2mA.
Restricted to TC (MAX) = 85°C.
TC = 85°C; ASR and ODT are disabled; SRT is enabled.
The IDD values must be derated (increased) on IT-option and AT-option devices when operated outside of the range 0°C ≤ TC ≤ +85°C:
5a. When TC < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD4W must
be derated by 2%; and IDD6 and IDD7 must be derated by 7%.
5b. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B
must be derated by 2%; IDD2Px must be derated by 30%.
6. The IDD values must be derated (increased) on UT-option. When TC > +105°C: IDD2p0,
IDD2p1, IDD2N, IDD2NT, IDD2Q, IDD3P, and IDD3N must be derated by 60% from the 85°C specs.
7. When TC >105°C, self refresh mode is not available.
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Electrical Characteristics and AC Operating Conditions
Electrical Characteristics and AC Operating Conditions
Table 7: Electrical Characteristics and AC Operating Conditions for Speed Extensions
Notes 1–8 apply to the entire table
DDR3L-1866
Parameter
Symbol
Min
Max
Unit
Notes
8
7800
ns
9, 42
85°C < TC ≤ 95°C
8
3900
ns
42
95°C < TC ≤ 105°C
8
3900
ns
42
105°C < TC ≤ 125°C
8
3900
ns
42
ns
10, 11
Clock Timing
Clock period average: DLL
disable mode
–40°C ≤ TC ≤ 85°C
tCK
(DLL_DIS)
Clock period average: DLL enable mode
tCK
(AVG)
High pulse width average
tCH
(AVG)
0.47
0.53
CK
12
Low pulse width average
tCL
(AVG)
Clock period jitter
See Speed Bin Tables for
tCK range allowed
0.47
0.53
CK
12
DLL locked
tJITper
–60
60
ps
13
DLL locking
tJITper,lck
–50
50
ps
13
Clock absolute period
tCK
(ABS)
Clock absolute high pulse width
tCH
(ABS)
0.43
–
tCK
(AVG)
14
Clock absolute low pulse width
tCL
(ABS)
0.43
–
tCK
(AVG)
15
Cycle-to-cycle jitter
Cumulative error across
tCK
MIN =
(AVG) MIN
+tJITper MIN;
MAX = tCK (AVG) MAX +
tJITper MAX
ps
DLL locked
tJITcc
120
ps
16
DLL locking
tJITcc,lck
100
ps
16
2 cycles
tERR2per
–88
88
ps
17
3 cycles
tERR3per
–105
105
ps
17
4 cycles
tERR4per
–117
117
ps
17
5 cycles
tERR5per
–126
126
ps
17
6 cycles
tERR6per
–133
133
ps
17
7 cycles
tERR7per
–139
139
ps
17
8 cycles
tERR8per
–145
145
ps
17
9 cycles
tERR9per
–150
150
ps
17
10 cycles
tERR10per
–154
154
ps
17
11 cycles
tERR11per
–158
158
ps
17
12 cycles
tERR12per
–161
161
ps
17
ps
17
n = 13, 14 . . . 49, 50
cycles
tERRnper
tERRnper
MIN = (1 +
0.68ln[n]) × tJITper MIN
tERRnper MAX = (1 +
0.68ln[n]) × tJITper MAX
DQ Input Timing
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Electrical Characteristics and AC Operating Conditions
Table 7: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
DDR3L-1866
Parameter
Data setup time to DQS,
DQS#
Base (specification) @
2 V/ns
Symbol
Min
Max
Unit
Notes
tDS
70
–
ps
18, 19
(AC130)
VREF @ 2 V/ns
Data hold time from DQS,
DQS#
Base (specification) @
2 V/ns
tDH
–
ps
19, 20
75
–
ps
18, 19
(DC90)
VREF @ 2 V/ns
Minimum data pulse width
135
110
–
ps
19, 20
tDIPW
320
–
ps
41
tDQSQ
–
85
DQ Output Timing
DQS, DQS# to DQ skew, per access
ps
tQH
0.38
–
DQ Low-Z time from CK, CK#
tLZDQ
–390
195
ps
22, 23
DQ High-Z time from CK, CK#
tHZDQ
–
195
ps
22, 23
DQS, DQS# rising to CK, CK# rising
tDQSS
–0.27
0.27
CK
25
DQS, DQS# differential input low pulse width
tDQSL
0.45
0.55
CK
DQS, DQS# differential input high pulse width
tDQSH
0.45
0.55
CK
DQS, DQS# falling setup to CK, CK# rising
tDSS
0.18
–
CK
25
DQS, DQS# falling hold from CK, CK# rising
tDSH
0.18
–
CK
25
DQS, DQS# differential WRITE preamble
tWPRE
0.9
–
CK
DQS, DQS# differential WRITE postamble
tWPST
0.3
–
CK
DQS, DQS# rising to/from rising CK, CK#
tDQSCK
–195
195
ps
23
DQS, DQS# rising to/from rising CK, CK# when
DLL is disabled
tDQSCK
1
10
ns
26
DQ output hold time from DQS, DQS#
tCK
(AVG)
21
DQ Strobe Input Timing
DQ Strobe Output Timing
(DLL_DIS)
DQS, DQS# differential output high time
tQSH
0.40
–
CK
21
DQS, DQS# differential output low time
tQSL
0.40
–
CK
21
DQS, DQS# Low-Z time (RL - 1)
tLZDQS
–390
195
ps
22, 23
DQS, DQS# High-Z time (RL + BL/2)
tHZDQS
–
195
ps
22, 23
DQS, DQS# differential READ preamble
tRPRE
0.9
Note 24
CK
23, 24
DQS, DQS# differential READ postamble
tRPST
0.3
Note 27
CK
23, 27
tDLLK
Command and Address Timing
DLL locking time
CTRL, CMD, ADDR
setup to CK,CK#
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
VREF @ 1 V/ns
Base (specification)
VREF @ 1 V/ns
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512
–
CK
28
tIS
65
–
ps
29, 30, 44
(AC135)
200
–
ps
20, 30
tIS
150
–
ps
29, 30, 44
(AC125)
275
–
ps
20, 30
10
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Electrical Characteristics and AC Operating Conditions
Table 7: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
DDR3L-1866
Parameter
Symbol
Min
Max
Unit
Notes
tIH
110
–
ps
29, 30
(DC90)
200
–
ps
20, 30
Minimum CTRL, CMD, ADDR pulse width
tIPW
535
–
ps
41
ACTIVATE to internal READ or WRITE delay
tRCD
See Speed Bin Tables for
tRCD
ns
31
tRP
See Speed Bin Tables for
tRP
ns
31
tRAS
See Speed Bin Tables for
tRAS
ns
31, 32
tRC
See Speed Bin Tables for
tRC
ns
31, 43
tRRD
MIN = greater of 4CK or
5ns
CK
31
MIN = greater of 4CK or
6ns
CK
31
CTRL, CMD, ADDR hold
from CK,CK#
Base (specification)
VREF @ 1 V/ns
PRECHARGE command period
ACTIVATE-to-PRECHARGE command period
ACTIVATE-to-ACTIVATE command period
ACTIVATE-to-ACTIVATE
1KB page size
minimum command period
2KB page size
Four ACTIVATE
windows
1KB page size
tFAW
2KB page size
27
–
ns
31
35
–
ns
31
tWR
MIN = 15ns; MAX = N/A
ns
31, 32, 33
tWTR
MIN = greater of 4CK or
7.5ns; MAX = N/A
CK
31, 34
tRTP
MIN = greater of 4CK or
7.5ns; MAX = N/A
CK
31, 32
CAS#-to-CAS# command delay
tCCD
MIN = 4CK; MAX = N/A
CK
Auto precharge write recovery + precharge time
tDAL
MIN = WR +
(AVG);
MAX = N/A
CK
MODE REGISTER SET command cycle time
tMRD
MIN = 4CK; MAX = N/A
CK
MODE REGISTER SET command update delay
tMOD
MIN = greater of 12CK or
15ns; MAX = N/A
CK
MULTIPURPOSE REGISTER READ burst end to
mode register set for multipurpose register exit
tMPRR
MIN = 1CK; MAX = N/A
CK
tZQinit
MAX = N/A
MIN = MAX(512nCK,
640ns)
CK
tZQoper
MAX = N/A
MIN = MAX(256nCK,
320ns)
CK
Write recovery time
Delay from start of internal WRITE transaction to
internal READ command
READ-to-PRECHARGE time
tRP/tCK
Calibration Timing
ZQCL command: Long cali- POWER-UP and REbration time
SET operation
Normal operation
ZQCS command: Short calibration time
MAX = N/A
MIN = MAX(64nCK, 80ns) tZQCS
CK
Initialization and Reset Timing
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Electrical Characteristics and AC Operating Conditions
Table 7: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
DDR3L-1866
Parameter
Symbol
Min
Max
Unit
tXPR
MIN = greater of 5CK or
tRFC + 10ns; MAX = N/A
CK
tVDDPR
MIN = N/A; MAX = 200
ms
RESET# LOW to power supplies stable
tRPS
MIN = 0; MAX = 200
ms
RESET# LOW to I/O and RTT High-Z
tIOZ
MIN = N/A; MAX = 20
ns
Exit reset from CKE HIGH to a valid command
Begin power supply ramp to power supplies stable
Notes
35
Refresh Timing
REFRESH-to-ACTIVATE or REFRESH
command period
Maximum refresh
period
tRFC
– 1Gb
MIN = 110; MAX = 70,200
ns
tRFC
– 2Gb
MIN = 160; MAX = 70,200
ns
tRFC
– 4Gb
MIN = 260; MAX = 70,200
ns
tRFC
– 8Gb
MIN = 350; MAX = 70,200
ns
TC ≤ 85°C
64 (1X)
ms
36
TC > 85°C
–
32 (2X)
ms
36
TC > 105°C
16 (4X)
ms
36
8 (8X)
ms
36
TC > 115°C
Maximum average
periodic refresh
TC ≤ 85°C
tREFI
7.8 (64ms/8192)
µs
36
TC > 85°C
3.9 (32ms/8192)
µs
36
TC >105°C
1.95 (16ms/8192)
µs
36
TC >115°C
0.977 (8ms/8192)
µs
36
tXS
MIN = greater of 5CK or
tRFC + 10ns; MAX = N/A
CK
Exit self refresh to commands requiring a
locked DLL
tXSDLL
MIN = tDLLK (MIN);
MAX = N/A
CK
Minimum CKE low pulse width for self refresh
entry to self refresh exit timing
tCKESR
MIN = tCKE (MIN) + CK;
MAX = N/A
CK
Valid clocks after self refresh entry or powerdown entry
tCKSRE
MIN = greater of 5CK or
10ns; MAX = N/A
CK
Valid clocks before self refresh exit,
power-down exit, or reset exit
tCKSRX
MIN = greater of 5CK or
10ns; MAX = N/A
CK
Self Refresh
Timing45
Exit self refresh to commands not requiring a
locked DLL
28
Power-Down Timing
CKE MIN pulse width
Command pass disable delay
Power-down entry to power-down exit timing
Begin power-down period prior to CKE
registered HIGH
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tCKE
Greater of 3CK or 5ns
CK
tCPDED
(MIN)
MIN = 2;
MAX = N/A
CK
tPD
MIN = tCKE (MIN);
MAX = 9 × tREFI
CK
tANPD
WL - 1CK
CK
12
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Electrical Characteristics and AC Operating Conditions
Table 7: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
DDR3L-1866
Parameter
Symbol
Power-down entry period: ODT either
synchronous or asynchronous
PDE
Power-down exit period: ODT either
synchronous or asynchronous
PDX
Min
Max
tANPD
tRFC
Greater of
or
REFRESH command to CKE
LOW time
tANPD
+ tXPDLL
Unit
Notes
CK
CK
Power-Down Entry Minimum Timing
ACTIVATE command to power-down entry
tACTPDEN
MIN = 2
CK
PRECHARGE/PRECHARGE ALL command to
power-down entry
tPRPDEN
MIN = 2
CK
REFRESH command to power-down entry
tREFPDEN
MIN = 2
CK
MRS command to power-down entry
tMRSPDEN
MIN = tMOD (MIN)
CK
READ/READ with auto precharge command to
power-down entry
tRDPDEN
MIN = RL + 4 + 1
CK
WRITE command to power-down entry
BL8 (OTF, MRS)
BC4OTF
tWRPDEN
MIN = WL + 4 +
tWR/tCK (AVG)
CK
BC4MRS
tWRPDEN
MIN = WL + 2 +
tWR/tCK (AVG)
CK
BL8 (OTF, MRS)
BC4OTF
tWRAPDEN
MIN = WL + 4 + WR + 1
CK
BC4MRS
tWRAPDEN
MIN = WL + 2 + WR + 1
CK
tXP
MIN = greater of 3CK or
6ns;
MAX = N/A
CK
tXPDLL
MIN = greater of 10CK or
24ns; MAX = N/A
CK
28
RTT synchronous turn-on delay
ODTL on
CWL + AL - 2CK
CK
38
RTT synchronous turn-off delay
ODTL off
CWL + AL - 2CK
WRITE with auto precharge command to power-down entry
37
Power-Down Exit Timing
DLL on, any valid command, or DLL off to
commands not requiring locked DLL
Precharge power-down with DLL off to
commands requiring a locked DLL
ODT Timing
CK
40
RTT turn-on from ODTL on reference
tAON
–195
195
ps
23, 38
RTT turn-off from ODTL off reference
tAOF
0.3
0.7
CK
39, 40
Asynchronous RTT turn-on delay
(power-down with DLL off)
tAONPD
MIN = 2; MAX = 8.5
ns
38
Asynchronous RTT turn-off delay
(power-down with DLL off)
tAOFPD
MIN = 2; MAX = 8.5
ns
40
ODT HIGH time with WRITE command and BL8
ODTH8
MIN = 6; MAX = N/A
CK
ODT HIGH time without WRITE command or with
WRITE command and BC4
ODTH4
MIN = 4; MAX = N/A
CK
Dynamic ODT Timing
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Electrical Characteristics and AC Operating Conditions
Table 7: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
DDR3L-1866
Parameter
Symbol
Min
Max
Unit
RTT,nom-to-RTT(WR) change skew
ODTLcnw
WL - 2CK
RTT(WR)-to-RTT,nom change skew - BC4
ODTLcwn4
4CK + ODTLoff
CK
RTT(WR)-to-RTT,nom change skew - BL8
ODTLcwn8
6CK + ODTLoff
CK
CK
tADC
0.3
0.7
CK
tWLMRD
40
–
CK
tWLDQSEN
25
–
CK
Write leveling setup from rising CK, CK#
crossing to rising DQS, DQS# crossing
tWLS
140
–
ps
Write leveling hold from rising DQS, DQS#
crossing to rising CK, CK# crossing
tWLH
140
–
ps
Write leveling output delay
tWLO
0
7.5
ns
Write leveling output error
tWLOE
0
2
ns
RTT dynamic change skew
Notes
39
Write Leveling Timing
First DQS, DQS# rising edge
DQS, DQS# delay
1.
2.
3.
4.
Notes:
5.
6.
7.
8.
9.
10.
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AC timing parameters are valid from specified TC MIN to TC MAX values.
All voltages are referenced to VSS.
Output timings are only valid for RON34 output buffer selection.
The unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation.
The unit CK represents one clock cycle of the input clock, counting the actual clock
edges.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test environment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the
AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum
slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs
(DQs are at 2V/ns for DDR3-1866 and DDR3-2133) and 2 V/ns for differential inputs in
the range between VIL(AC) and VIH(AC).
All timings that use time-based values (ns, µs, ms) should use tCK (AVG) to determine the
correct number of clocks (Table 7 (page 9) uses CK or tCK [AVG] interchangeably). In the
case of noninteger results, all minimum limits are to be rounded up to the nearest
whole integer, and all maximum limits are to be rounded down to the nearest whole
integer.
Strobe or DQSdiff refers to the DQS and DQS# differential crossing point when DQS is
the rising edge. Clock or CK refers to the CK and CK# differential crossing point when
CK is the rising edge.
This output load is used for all AC timing (except ODT reference timing) and slew rates.
The actual test load may be different. The output signal voltage reference point is
VDDQ/2 for single-ended signals and the crossing point for differential signals (see Figure
25: Differential Output Signal in the data sheet).
When operating in DLL disable mode, Micron does not warrant compliance with normal
mode timings or functionality.
The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG)
MIN is the smallest clock rate allowed, with the exception of a deviation due to clock
jitter. Input clock jitter is allowed provided it does not exceed values specified and must
be of a random Gaussian distribution in nature.
14
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Electrical Characteristics and AC Operating Conditions
11. Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread
spectrum may not use a clock rate below tCK (AVG) MIN.
12. The clock’s tCH (AVG) and tCL (AVG) are the average half clock period over any 200 consecutive clocks and is the smallest clock half period allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values
specified and must be of a random Gaussian distribution in nature.
13. The period jitter (tJITper) is the maximum deviation in the clock period from the average
or nominal clock. It is allowed in either the positive or negative direction.
14. tCH (ABS) is the absolute instantaneous clock high pulse width as measured from one
rising edge to the following falling edge.
t
15. CL (ABS) is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge.
16. The cycle-to-cycle jitter tJITcc is the amount the clock period can deviate from one cycle
to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.
17. The cumulative jitter error tERRnper, where n is the number of clocks between 2 and 50,
is the amount of clock time allowed to accumulate consecutively away from the average
clock over n number of clock cycles.
18. tDS (base) and tDH (base) values are for a single-ended 1 V/ns slew rate DQs (DQs are at
2V/ns for DDR3-1866 and DDR3-2133) and 2 V/ns slew rate differential DQS, DQS#; when
DQ single-ended slew rate is 2V/ns, the DQS differential slew rate is 4V/ns.
19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transition edge to its respective data strobe signal (DQS, DQS#) crossing.
20. The setup and hold times are listed converting the base specification values (to which
derating tables apply) to VREF when the slew rate is 1 V/ns (DQs are at 2V/ns for
DDR3-1866 and DDR3-2133). These values, with a slew rate of 1 V/ns (DQs are at 2V/ns
for DDR3-1866 and DDR3-2133), are for reference only.
21. When the device is operated with input clock jitter, this parameter needs to be derated
by the actual tJITper (larger of tJITper (MIN) or tJITper (MAX) of the input clock (output
deratings are relative to the SDRAM input clock).
22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by the actual jitter error when input clock jitter is present,
even when within specification. This results in each parameter becoming larger. The following parameters are required to be derated by subtracting tERR10per (MAX): tDQSCK
(MIN), tLZDQS (MIN), tLZDQ (MIN), and tAON (MIN). The following parameters are required to be derated by subtracting tERR10per (MIN): tDQSCK (MAX), tHZ (MAX), tLZDQS
(MAX), tLZDQ (MAX), and tAON (MAX). The parameter tRPRE (MIN) is derated by subtracting tJITper (MAX), while tRPRE (MAX) is derated by subtracting tJITper (MIN).
24. The maximum preamble is bound by tLZDQS (MAX).
25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its respective clock signal (CK, CK#) crossing. The specification values are not affected by the
amount of clock jitter applied, as these are relative to the clock signal crossing. These
parameters should be met whether clock jitter is present.
26. The tDQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.
27. The maximum postamble is bound by tHZDQS (MAX).
28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT commands. In addition, after any change of latency tXPDLL, timing must be met.
29. tIS (base) and tIH (base) values are for a single-ended 1 V/ns control/command/address
slew rate and 2 V/ns CK, CK# differential slew rate.
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Electrical Characteristics and AC Operating Conditions
30. These parameters are measured from a command/address signal transition edge to its
respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether clock jitter is present.
31. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU(tPARAM
[ns]/tCK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP (nCK) = RU(tRP/tCK[AVG]) if all input clock jitter specifications are met. This means that for DDR3-800 6-6-6, of which tRP = 5ns, the device will
support tnRP = RU(tRP/tCK[AVG]) = 6 as long as the input clock jitter specifications are
met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are
valid even if six clocks are less than 15ns due to input clock jitter.
32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the internal PRECHARGE command until tRAS (MIN) has been satisfied.
33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR.
34. The start of the write recovery time is defined as follows:
35.
36.
37.
38.
39.
40.
41.
42.
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• For BL8 (fixed by MRS or OTF): Rising clock edge four clock cycles after WL
• For BC4 (OTF): Rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL
RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in
High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in excessive current, depending on bus activity.
The refresh period is 64ms when TC is less than or equal to 85°C. This equates to an average refresh rate of 7.8125µs. However, nine REFRESH commands should be asserted at
least once every 70.3µs. When TC is greater than 85°C, the refresh period is 32ms. When
TC is greater than 105°C, the refresh period is 16ms. When TC is greater than 115°C, the
refresh period is 8ms.
Although CKE is allowed to be registered LOW after a REFRESH command when
tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN)
is required.
ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to
turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT
reference load is shown in Figure 19: ODT Timing Reference Load in the data sheet. Designs that were created prior to JEDEC tightening the maximum limit from 9ns to 8.5ns
will be allowed to have a 9ns maximum.
Half-clock output parameters must be derated by the actual tERR10per and tJITdty when
input clock jitter is present. This results in each parameter becoming larger. The parameters tADC (MIN) and tAOF (MIN) are each required to be derated by subtracting both
tERR10per (MAX) and tJITdty (MAX). The parameters tADC (MAX) and tAOF (MAX) are
required to be derated by subtracting both tERR10per (MAX) and tJITdty (MAX).
ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT
turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is
shown in Figure 19: ODT Timing Reference Load in the data sheet. This output load is
used for ODT timings (Figure 26: Reference Output Load for AC Timing and Output Slew
Rate in the data sheet).
Pulse width of a input signal is defined as the width between the first crossing of
VREF(DC) and the consecutive crossing of VREF(DC).
Should the clock rate be larger than tRFC (MIN), an AUTO REFRESH command should
have at least one NOP command between it and another AUTO REFRESH command. Additionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should
be followed by a PRECHARGE ALL command.
16
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Extended Temperature Usage
43. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in a reduction of REFRESH characteristics or
product lifetime.
44. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific
speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may
be used for data inputs.
For example, for DDR3-800, two input AC levels are defined: VIH(AC175),min and
VIH(AC150),min (corresponding VIL(AC175),min and VIL(AC150),min). For DDR3-800, the address/
command inputs must use either VIH(AC175),min with tIS(AC175) of 200ps or VIH(AC150),min
with tIS(AC150) of 350ps; independently, the data inputs must use either VIH(AC175),min
with tDS(AC175) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps.
45. Self refresh is not available when TC > 105°C.
Extended Temperature Usage
Micron’s DDR3 SDRAM support the optional extended case temperature (TC) range of
0°C to 125°C. Thus, the SRT and ASR options must be used at a minimum.
The extended temperature range DRAM must be refreshed externally at 2x (double refresh) anytime the case temperature is above 85°C (and does not exceed 105°C), 4x anytime the case temperature is above 105°C (and does not exceed 115°C) and 8x anytime
the case temperature is above 115°C (and does not exceed 125°C). However, self refresh
mode requires either ASR or SRT to support the extended temperatures between 85°C
and 105°C and is not supported for temperatures above 105°C.
Table 8: Self Refresh Temperature and Auto Self Refresh Description
Field
MR2 Bits
Description
Self Refresh Temperature (SRT)
SRT
7
If ASR is disabled (MR2[6] = 0), SRT must be programmed to indicate TOPER during self refresh:
*MR2[7] = 0: Normal operating temperature range (–40°C to 85°C)
*MR2[7] = 1: Extended operating temperature range (–40°C to 105°C)
If ASR is enabled (MR2[7] = 1), SRT must be set to 0, even if the extended temperature range is
supported
*MR2[7] = 0: SRT is disabled
Auto Self Refresh (ASR)
ASR
6
When ASR is enabled, the DRAM automatically provides SELF REFRESH power management functions, (refresh rate for all supported operating temperature values)
* MR2[6] = 1: ASR is enabled (M7 must = 0)
When ASR is not enabled, the SRT bit must be programmed to indicate TOPER during SELF REFRESH
operation
* MR2[6] = 0: ASR is disabled; must use manual self refresh temperature (SRT)
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Extended Temperature Usage
Table 9: Self Refresh Mode Summary
MR2[6] MR2[7]
(ASR)
(SRT) SELF REFRESH Operation
Permitted Operating Temperature
Range for Self Refresh Mode
0
0
Self refresh mode is supported in the normal temperature
range
0
1
Self refresh mode is supported in normal and extended temper- Normal and extended (–40°C to
ature ranges; When SRT is enabled, it increases self refresh
105°C)
power consumption
1
0
Self refresh mode is supported in normal and extended temper- Normal and extended (–40°C to
ature ranges; Self refresh power consumption may be tempera- 105°C)
ture-dependent
1
1
Illegal
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18
Normal (–40°C to 85°C)
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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Revision History
Revision History
Rev. C – 2/17
• Typo correction in Calibration Timing in Electrical Characteristics and AC Operating
Conditions for Speed Extensions table
Rev. B – 4/16
• Updated refresh rate specification through the data sheet: 16ms at 105°C to 115°C,
and 8ms at 115°C to 125°C
• Updated the description of Utra-high Temperature in Functional Description section
• Updated Electrical Characteristics and AC Operating Conditions for Speed Extensions
table in Electrical Characteristics and AC Operating Conditions: Updated Refresh
Timing and note
• Updated Self Refresh Temperature and Auto Self Refresh Description table and Self
Refresh Mode Summary table in Extended Temperature Usage section
Rev. A – 9/15
• Initial release
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www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
09005aef86775d6d
1gb_aut_DDR3L_1_35v_addendum.pdf - Rev. C 2/17 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
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