LTM9005 - IF Sampling Receiver Subsystem

LTM9005 - IF Sampling Receiver Subsystem
Electrical Specifications Subject to Change
LTM9005
IF Sampling Receiver
Subsystem
Features
Description
Fully Integrated “RF-to-Bits” IF-Sampling Receiver
Subsystem
n Wide RF Frequency Range: 400MHz to 3.8GHz
n 140MHz Center Frequency Internal SAW Filter
n Low Power ADC with Up to 14-Bit Resolution,
125Msps Sample Rate
n 16dB Cascaded NF, 17.7dBm Two-Tone IIP3
n 1.2W Total Power Consumption
n 50Ω Single-Ended RF and LO Ports
n Continuous 20dB Attenuation Range
n Internal Bypass Capacitance, No External
Components Required
n ADC Clock Duty Cycle Stabilizer
n Digital Output Supply Range: 0.5V to 3.6V
n15mm × 22mm LGA package
The LTM®9005 is an IF Sampling Receiver Subsystem for
wireless base stations and communications test equipment. Utilizing an integrated System in a Package (SiP)
technology, it includes a downconverting mixer, 140MHz
SAW filter, two gain stages, a variable attenuator and
analog-to-digital converter (ADC). The system is tuned for
an Intermediate Frequency (IF) of 140MHz and a signal
bandwidth of up to 60MHz; contact Linear Technology
regarding customization. The high integration and small
package allow for a very compact receiver.
n
Applications
The high signal level downconverting mixer is optimized
for high linearity, wide dynamic range IF sampling applications. It includes a high speed differential LO buffer
amplifier driving a double-balanced mixer. Broadband,
integrated transformers on the RF and LO inputs provide
single ended 50Ω interfaces. The RF and LO inputs are
internally matched to 50Ω from 1.6GHz to 2.3GHz.
Versions are available with ADCs up to 14-bit resolution
and 125Msps. A separate output supply allows the parallel
output bus to drive 0.5V to 3.6V logic. A single-ended CLK
input controls converter operation. An optional clock duty
cycle stabilizer allows high performance at full speed for
a wide range of clock duty cycles.
Base Station Receivers
Remote Radio Heads
n Communications Test Equipment
n
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
IF Frequency Response, 64k Point FFT,
RF = 1.95GHz, LO = 1.81GHz
Simplified IF-Sampling Receiver
0
3.3V
–10
OVDD
0.5V to 3.6V
–20
(dB)
–30
–40
–50
LNA
SAW
LTM9005
LO
GAIN
GND
OGND
–60
–70
CLK
DAC
9005 TA01
–80
80
100
120 140 160 180
IF FREQUENCY (MHz)
200
220
9005 TA01b
9005p
1
LTM9005
Absolute Maximum Ratings
Pin Configuration
(Notes 1, 2)
(See Pin Functions, Pin Configuration Table)
Supply Voltage (VCC2, VCC3)...................... –0.3V to 3.6V
Supply Voltage (VCC1, VDD, OVDD).............. –0.3V to 4.0V
Digital Output Ground Voltage (OGND)......... –0.3V to 1V
LO Input Power (380MHz to 4.2GHz)....................10dBm
LO Input DC Voltage.............................. –1V to VCC1 + 1V
RF Input Power (400MHz to 3.8GHz)....................12dBm
RF Input DC Voltage................................................ ±0.1V
EN Voltage......................................–0.3V to VCC1 + 0.3V
AMP1SHDN Voltage........................–0.3V to VCC2 + 0.3V
AMP2SHDN Voltage........................–0.3V to VCC3 + 0.3V
GAIN Voltage..................................–0.3V to VCC1 + 0.3V
GAIN Current...........................................................20mA
Digital Input Voltage..................... –0.3V to (VDD + 0.3V)
Digital Output Voltage................. –0.3V to (OVDD + 0.3V)
Operating Ambient Temperature Range
LTM9005C................................................ 0°C to 70°C
LTM9005I.............................................–40°C to 85°C
Storage Temperature Range................... –45°C to 125°C
Maximum Junction Temperature........................... 125°C
TOP VIEW
A
B
C
D
E
F
G
H
J
K
L
M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CAUTION: Pins A8, A9, B8, B9, L8, L9, M8 and M9
and the RF and LO inputs are sensitive to electro-static
discharge (ESD). It is very important that proper ESD
precautions be observed when handling the LTM9005.
Avoid ultrasonic exposure, the LTM9005 contains a
hermetic cavity filter.
17
LGA PACKAGE
204-LEAD (15mm × 22mm × 4.3mm)
TJMAX = 125°C, θJA = TDB°C/W
Order Information
LEAD FREE FINISH
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTM9005CV-AA#PBF
LTM9005V AA
204-Lead (15mm × 22mm × 4.3mm) LGA
0°C to 70°C
LTM9005IV-AA#PBF
LTM9005V AA
204-Lead (15mm × 22mm × 4.3mm) LGA
–40°C to 85°C
LTM9005CV-AB#PBF
LTM9005V AB
204-Lead (15mm × 22mm × 4.3mm) LGA
0°C to 70°C
LTM9005IV-AB#PBF
LTM9005V AB
204-Lead (15mm × 22mm × 4.3mm) LGA
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
9005p
2
LTM9005
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3). All specifications apply at maximum gain setting.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
RF Input Frequency Range
No External Matching (Midband)
With External Matching (Low Band or High Band)
400
LO Input Frequency Range
No External Matching
With External Matching
380
RF Input Return Loss
ZO = 50Ω, 1600MHz to 2300MHz (No External Matching)
>12
dB
LO Input Return Loss
ZO = 50Ω, 1000MHz to 5000MHz (No External Matching)
>10
dB
RF Input Power for –1dBFS
LTM9005-AA
RF = 900MHz, LO = 760MHz
RF = 1950MHz, LO = 1810MHz
LTM9005-AB
RF = 900MHz, LO = 760MHz
RF = 1950MHz, LO = 1810MHz
1600 to 2300
1000 to 4200
MAX
UNITS
3800
MHz
MHz
5000
MHz
MHz
TBD
TBD
TBD
–18.8
TBD
TBD
dBm
dBm
TBD
TBD
TBD
–17.8
TBD
TBD
dBm
dBm
–8
–5
–3
0
2
5
dBm
dBm
LO Input Power
1200MHz to 4200MHz
380MHz to 1200MHz
LO to RF Leakage
fLO = 380MHz to 1600MHz
fLO = 1600MHz to 4000MHz
<–50
<–45
dBm
dBm
RF to LO Isolation
fRF = 400MHz to 1700MHz
fRF = 1700MHz to 3800MHz
>50
>42
dB
dB
2Rf-2LO Output Spurious Product
(fRF = fLO + fIF/2)
900MHz: fRF = 830MHz at TBD
1950MHz: fRF = 1880MHz at –19dBm
TBD
–71
dBc
dBc
3Rf-3LO Output Spurious Product
(fRF = fLO + fIF/3)
900MHz: fRF = 807MHz at TBD
1950MHz: fRF = 1857MHz at –19dBm
TBD
–96
dBc
dBc
Filter
Characteristics
The
l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Center Frequency
LTM9005-AA
LTM9005-AB
140
140
MHz
MHz
Lower 1dB Bandedge
LTM9005-AA
LTM9005-AB
132
130.8
MHz
MHz
Upper 1dB Bandedge
LTM9005-AA
LTM9005-AB
148
149.2
MHz
MHz
Lower 3dB Bandedge
LTM9005-AA
LTM9005-AB
131.5
130
MHz
MHz
Upper 3dB Bandedge
LTM9005-AA
LTM9005-AB
148.5
150
MHz
MHz
Lower 35dB Stopband
LTM9005-AA
LTM9005-AB
129
126.8
MHz
MHz
Upper 35dB Stopband
LTM9005-AA
LTM9005-AB
151
153.2
MHz
MHz
Passband Flatness
133.6MHz – 146.4MHz, LTM9005-AA
130.8MHz – 149.2MHz, LTM9005-AB
0.6
0.8
dB
dB
Phase Linearity
133.6MHz – 146.4MHz, LTM9005-AA
130.8MHz – 149.2MHz, LTM9005-AB
10
TBD
deg
deg
Group Delay
133.6MHz – 146.4MHz, LTM9005-AA
130.8MHz – 149.2MHz, LTM9005-AB
60
115
ns
ns
Absolute Delay
LTM9005-AA
LTM9005-AB
1
1
µs
µs
9005p
3
LTM9005
Converter
Characteristics l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
14
Bits
Resolution (No Missing Codes)
LTM9005-Ax
Integral Linearity Error (Note 4)
IF = 140MHz, LTM9005-Ax
±TBD
LSB
Differential Linearity Error
IF = 140MHz, LTM9005-Ax
±TBD
LSB
l
Gain
Control
The
l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. VCC1 = 3.3V, RF Input = –1dBFS.
SYMBOL PARAMETER
CONDITIONS
MIN
Gain Adjustment Range
TYP
MAX
UNITS
20
Forward Current Range
0
l
dB
10
mA
Response Time
10% to 90% Gain Current Step
TBD
µs
Input Impedance
XX MHz, 0.1 < IGAIN < 10mA
50
Ω
Isolation to Output
RF Input = TBD dBm (Note 5)
TBD
dB
Control Voltage
Maximum Gain
Gain –20dB
3.3
2.55
V
V
Dynamic
Accuracy
The
l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3). All specifications apply at maximum gain setting.
SYMBOL PARAMETER
CONDITIONS
SNR
LTM9005-AA
RF = 1950MHz, LO = 1810MHz
LTM9005-AB
RF = 1950MHz, LO = 1810MHz
SFDR
Signal-to-Noise Ratio at –1dBFS, within the RF
Passband
Spurious Free Dynamic Range at –1dBFS
2nd or 3rd Harmonic
LTM9005-AA
RF = 1950MHz, LO = 1810MHz
LTM9005-AB
RF = 1950MHz, LO = 1810MHz
SFDR
Spurious Free Dynamic Range at –1dBFS
4th or Higher
LTM9005-AA
RF = 1950MHz, LO = 1810MHz
LTM9005-AB
RF = 1950MHz, LO = 1810MHz
S/(N+D)
Signal-to-Noise Plus Distortion Ratio at –1dBFS
LTM9005-AA
RF = 1950MHz, LO = 1810MHz
LTM9005-AB
RF = 1950MHz, LO = 1810MHz
IMD3
Intermodulation Distortion at –7dBFS per Tone
LTM9005-AA
RF = 1950MHz, LO = 1810MHz
LTM9005-AB
RF = 1950MHz, LO = 1810MHz
MIN
TYP
MAX
UNITS
TBD
67.2
TBD
dB
TBD
67
TBD
dB
TBD
75
TBD
dB
TBD
75
TBD
dB
TBD
93.5
TBD
dB
TBD
93.5
TBD
dB
TBD
60.5
TBD
dB
TBD
62
TBD
dB
TBD
72.5
TBD
dB
TBD
72.5
TBD
dB
9005p
4
LTM9005
Digital
Inputs and Outputs
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logic Inputs (CLK, OE, ADCSHDN)
VIH
High Level Input Voltage
VDD = 3V
l
VIL
Low Level Input Voltage
VDD = 3V
l
IIN
Input Current
VIN = 0V to VDD
l
CIN
Input Capacitance
(Note 6)
2
V
–10
0.8
V
10
µA
3
pF
Amplifier Shutdown (AMP1SHDN, AMP2SHDN)
VIH
High Level Input Voltage
VCC2 = VCC3 = 3V
l
2.4
V
VIL
Low Level Input Voltage
VCC2 = VCC3 = 3V
l
IIH
Input High Current
VCC2 = VCC3 = 3V, VIN = 2V
1.3
µA
IIL
Input Low Current
VCC2 = VCC3 = 3V, VIN = 0.8V
0.1
µA
0.8
V
Mixer Enable (EN)
VIH
High Level Input Voltage
VCC1 = 3.3V
l
VIL
Low Level Input Voltage
VCC1 = 3.3V
l
IIN
Input Current
VIN = 0V to VCC1
l
2.7
V
53
0.3
V
90
µA
Turn-ON Time
2.8
µs
Turn-OFF Time
2.9
µs
Analog Inputs (Mode, SENSE)
IMODE
MODE Input Leakage
ISENSE
SENSE Input Leakage
0V < SENSE < 1V
l
–3
3
µA
l
–3
3
µA
Logic Outputs
OVDD = 3V
COZ
Hi-Z Output Capacitance
OE = 3V (Note 6)
3
pF
ISOURCE
Output Source Current
VOUT = 0V
50
mA
ISINK
Output Sink Current
VOUT = 3V
50
mA
VOH
High Level Output Voltage
IO = –10µA
IO = –200µA
l
IO = 10µA
IO = 1.6mA
l
VOL
Low Level Output Voltage
2.7
2.995
2.99
0.005
0.09
V
V
0.4
V
V
OVDD = 2.5V
VOH
High Level Output Voltage
IO = –200µA
2.49
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
OVDD = 1.8V
VOH
High Level Output Voltage
IO = –200µA
1.79
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
9005p
5
LTM9005
Power
Requirements
The
l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
MIN
TYP
MAX
VCC1
Mixer Supply Range
l
2.9
3.3
3.6
V
VCC2
First Amplifier Supply Range
l
2.85
3.3
3.465
V
VCC3
Second Amplifier Supply Range
l
2.85
3.3
3.465
V
VDD
ADC Analog Supply Voltage
l
2.85
3.3
3.465
V
OVDD
ADC Digital Output Supply Voltage
l
0.5
3.3
3.6
V
ICC1
Mixer Supply Current
EN = 3V
l
82
92
mA
ICC1(SHDN) Mixer Shutdown Supply Current
EN = 0V
l
100
µA
First Amplifier Supply Current
AMP1SHDN = 0V
l
ICC2(SHDN) First Amplifier Shutdown Supply Current
AMP1SHDN = 3V
l
AMP2SHDN = 0V
l
ICC3(SHDN) Second Amplifier Shutdown Supply Current AMP2SHDN = 3V
l
ICC2
ICC3
Second Amplifier Supply Current
CONDITIONS
90
90
132
UNITS
105
mA
3
mA
105
mA
3
mA
156
mA
IDD
ADC Supply Current
ADCSHDN = 0V
PD(SHDN)
Power Dissipation in Shutdown
EN = 0V, AMP1SHDN = AMP2SHDN =
ADCSHDN = 3V, OE = 3V, No RF, No LO, No CLK
TBD
mW
PD(NAP)
ADC Nap Mode Power
EN = 0V, AMP1SHDN = AMP2SHDN =
ADCSHDN = 3V, OE = 0V, No RF, No LO, No CLK
15
mW
PD(TOTAL)
Total Power Dissipation
EN = 3V, AMP1SHDN = AMP2SHDN =
ADCSHDN = 0V, OE = 0V, fSAMPLE = MAX
1200
mW
l
Timing Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
fs
Sampling Frequency
tL
CLK Low Time
tH
CONDITIONS
MIN
l
1
Duty Cycle Stabilizer Off (Note 6)
Duty Cycle Stabilizer On (Note 6)
l
l
3.8
3
CLK High Time
Duty Cycle Stabilizer Off (Note 6)
Duty Cycle Stabilizer On (Note 6)
l
l
3.8
3
tAP
Sample-and-Hold Aperture Delay
Figure 1 (Note 6, Note 7)
tJITTER
Sample-and-Hold Acquisition Delay Time Jitter
(Note 6, Note 7)
tD
CLK to DATA delay
CL = 5pF (Note 6)
l
DATA Access Time After OE↓
CL = 5pF (Note 6)
BUS Relinquish Time
(Note 6)
Pipeline Latency
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: VCC1 = 3.3V, VCC2 = VCC3 = VDD = 3V, AMP1SHDN = AMP2SHDN =
ADCSHDN = 0V, EN = 3.3V, fSAMPLE = 125MHz, RF input power = –10dBm.
TYP
MAX
UNITS
125
MHz
4
4
500
500
ns
ns
4
4
500
500
ns
ns
0
ns
0.2
1.4
psRMS
2.7
5.4
ns
l
4.3
10
ns
l
3.3
8.5
5
ns
Cycles
Note 4: Integral nonlinearity is defined as the deviation of a code from
a “best fit straight line” to the transfer curve. The deviation is measured
from the center of the quantization band.
Note 5: Noise level superimposed on the GAIN pin at 140MHz required to
generate spur above the noise floor.
Note 6: Guaranteed by design, not subject to test.
Note 7: Analog input measured at L8-L9 pads.
9005p
6
LTM9005
Timing Diagram
tAP
ANALOG
INPUT
N+4
N+2
N
N+1
tH
N+5
N+3
tL
CLK
tD
D0-D13, OF
N–5
N–4
N–3
N–2
N–1
N
9005 TD01
Figure 1. Digital Output Bus Timing
9005p
7
LTM9005
Typical Performance Characteristics
LTM9005-AA: 64K Point
2-Tone FFT
–20
0
fIN = 1949MHz and 1951MHz
–7dBFS Per Tone
SENSE = VDD
–10
–20
–40
–50
–60
–70
–80
–20
–30
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
–20
LTM9005: 64K Point FFT,
Minimum Gain
0
fIN = 1950MHz
–1dBFS
SENSE = VDD
–10
–20
–50
–60
–70
–80
fIN = 1950MHz
–1dBFS
SENSE = VDD
–10
–20
–40
–60
–70
–90
–100
–110
–110
–120
–40
–50
–80
–90
0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
–30
–50
–100
–120
LTM9005: IF Frequency Response
0
–30
AMPLITUDE (dBFS)
–30
–40
0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
9005 G03
?? (dB)
–10
–120
0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
9005 G02
LTM9005: 64K Point FFT,
Maximum Gain
0
fIN = 900MHz
–1dBFS
SENSE = VDD
–10
–40
9005 G01
AMPLITUDE (dBFS)
0
fIN = 900MHz
–1dBFS
SENSE = VDD
–30
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–30
LTM9005: 64K Point FFT,
Minimum Gain
AMPLITUDE (dBFS)
0
–10
LTM9005: 64K Point FFT,
Maximum Gain
–60
–70
0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
9005 G04
–80
40 60 80 100 120 140 160 180 200 220 240
IF FREQUENCY (MHz)
9005 G06
9005 G05
LTM9005: LO Port Return Loss
vs Frequency
LTM9005: LO Port Impedance
0
RETURN LOSS (dB)
–5
–10
–15
–20
–25
–30
100
NO MATCHING ELEMENTS
1.81GHz MATCH (3.3nH + 1.5pF)
840MHz MATCH (1.5pF)
1000
FREQUENCY (MHz)
10000
9005 G08
9005p
8
LTM9005
Typical Performance Characteristics
LTM9005: RF Port Return Loss
vs Frequency
LTM9005: RF Port Impedance
0
RETURN LOSS (dB)
–5
–10
–15
–20
–25
–30
100
1000
FREQUENCY (MHz)
NO MATCHING ELEMENTS
1.95GHz MATCH (5.6nH)
700MHz MATCH (4.7pF)
900MHz MATCH (2.7pF)
10000
9005 G10
Pin Functions
RF (Pin M3): Single-Ended Input for the RF Signal. This
pin is internally connected to the primary side of the RF
input transformer, which has low DC resistance to ground.
If the RF source is not DC blocked, then a series blocking
capacitor must be used. The RF input is internally matched
from 1.6GHz to 2.3GHz. Operation down to 400MHz or up
to 3.8GHz is possible with simple external matching.
AMP1SHDN (Pin D4), AMP2SHDN (Pin L16): Amplifier Enable Pins. Connecting AMPSHDN to GND results in normal
operation. Connecting AMP1SHDN to VCC2 disables the
amplifier preceding the SAW filter and connecting AMP2SHDN to VCC3 disables the amplifier following the SAW
filter. It is recommended to tie AMP1SHDN, AMP2SHDN
and ADCSHDN together and control with 3V logic.
LO (Pin M6): Single-Ended Input for the Local Oscillator
Signal. This pin is internally connected to the primary side
of the LO transformer, which is internally DC blocked. An
external blocking capacitor is not required. The LO input
is internally matched from 1GHz to 5GHz. Operation down
to 380MHz is possible with simple external matching.
CLK (Pin A11): ADC Clock Input. The input sample starts
on the positive edge.
GAIN (Pin F1): Cathode of PIN Diode. Sinking current
from GAIN attenuates the signal. The forward voltage is
approximately 1V and the output impedance is 50Ω.
EN (Pin H1): Mixer Enable Pin. Connecting EN to VCC1
results in normal operation. Connecting EN to GND disables
the mixer. The EN pin should not be left floating.
ADCSHDN (Pin C13): ADC Shutdown Mode Selection Pin.
Connecting ADCSHDN to GND and OE to GND results in
normal operation with the ADC outputs enabled. Connecting ADCSHDN to GND and OE to VDD results in normal
operation with the outputs at high impedance. Connecting
ADCSHDN to VDD and OE to GND results in nap mode with
the outputs at high impedance. Connecting ADCSHDN to
VDD and OE to VDD results in sleep mode with the outputs
at high impedance.
OE (Pin C12): Output Enable Pin. Refer to ADCSHDN pin
function.
9005p
9
LTM9005
Pin Functions
D0 – D13 (See Table for Pin Locations): Digital Outputs.
D13 is the MSB.
OF (Pin G15): Over/Under Flow Output. High when an
over or under flow has occurred.
MODE (Pin F15): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
offset binary output format and turns the clock duty cycle
stabilizer off. 1/3 VDD selects offset binary output format
and turns the clock duty cycle stabilizer on. 2/3 VDD selects
2’s complement output format and turns the clock duty
cycle stabilizer on. VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE (Pin H12): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and the
default input range. Connecting SENSE to 1.5V selects the
internal reference and a 3dB lower input range. An external
reference greater than 0.5V and less than 1V applied to
SENSE selects the external reference. A 1V external reference sets the input range equal to the default input range,
a 0.5V external reference sets the input range 3dB lower
and an external value between 0.5V and 1V sets the input
range proportionally.
A8 (Pin A8): Test Pin Used During Manufacturing Only.
Connect directly to B8. Keep this connection free from
noise.
A9 (Pin A9): Test Pin Used During Manufacturing Only.
Connect directly to B9. Keep this connection free from
noise.
B8 (Pin B8): Test Pin Used During Manufacturing Only.
Connect directly to A8. Keep this connection free from
noise.
L8 (Pin L8): Test Pin Used During Manufacturing Only.
Connect directly to M8. Keep this connection free from
noise.
L9 (Pin L9): Test Pin Used During Manufacturing Only.
Connect directly to M9. Keep this connection free from
noise.
M8 (Pin M8): Test Pin Used During Manufacturing Only.
Connect directly to L8. Keep this connection free from
noise.
M9 (Pin M9): Test Pin Used During Manufacturing Only.
Connect directly to L9. Keep this connection free from
noise.
OGND (Pins A16, A17, B17, C16 and C17): Output Driver
Ground.
OVDD (Pins D16 and D17): Positive Supply for the Output
Drivers. This supply is internally bypassed to GND. OVDD
can be 0.5V to 3.6V.
VCC1 (Pins K1 and K2): 3.3V Supply Voltage for Mixer.
VCC1 is internally bypassed to GND.
VCC2 (Pins B1 and C1): 3.3V Supply Voltage for First
Amplifier. VCC2 is internally bypassed to GND. Can operate
at 3V if desired.
VCC3 (Pins M14 and M15): 3.3V Supply Voltage for Second
Amplifier. VCC3 is internally bypassed to GND. Can operate
at 3V if desired.
VDD (Pins A13 and B13): 3.3V Supply Voltage for ADC.
VDD is internally bypassed to GND. Can operate at 3V if
desired.
GND (See Table for Pin Locations): Module Ground.
B9 (Pin B9): Test Pin Used During Manufacturing Only.
Connect directly to A9. Keep this connection free from
noise.
9005p
10
LTM9005
Pin Functions
Pin Configuration
A
B
C
D
E
F
1
GND
VCC2
VCC2
2
GND
GND
GND
3
GND
GND
GND
GND
G
H
J
K
L
M
GND
GND
GAIN
GND
EN
GND
GND
GND
GND
GND
GND
VCC1
GND
GND
GND
VCC1
GND
GND
GND
GND
GND
GND
GND
GND
GND
RF
4
GND
GND
GND
AMP1 SHDN
GND
GND
GND
GND
GND
GND
GND
GND
5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
LO
7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
8
A8
B8
GND
GND
GND
GND
GND
GND
GND
GND
L8
M8
9
A9
B9
GND
GND
GND
GND
GND
GND
GND
GND
L9
M9
10
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
11
CLK
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
12
GND
GND
OE
GND
GND
GND
GND
SENSE
GND
GND
GND
GND
13
V DD
VDD
ADC SHDN
GND
GND
GND
GND
GND
GND
GND
GND
GND
14
D0
D2
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC3
15
D1
D3
GND
GND
D5
MODE
OF
GND
GND
GND
GND
VCC3
16
OGND
D4
OGND
OVDD
D6
D9
D11
D13
GND
GND
AMP2 SHDN
GND
17
OGND
OGND
OGND
OVDD
D7
D8
D10
D12
GND
GND
GND
GND
Top View of LGA Package (Looking Through Component)
Block Diagram
VCC1
VCC2
VCC3
VDD
OVDD
RF
2ND
AMPLIFIER
1ST
AMPLIFIER
14-BIT
ADC
SAW
OUTPUT
DRIVERS
OF
D13
…
D0
BPF
OGND
50Ω
1.5V
REFERENCE
RANGE
SELECT
REFERENCE
BUFFER
0.1µF
EN
LO
GAIN
AMP1 SHDN
AMP2 SHDN
50Ω
SENSE
CLK
MODE
ADC SHDN
OE
9005 BD01
Simplified Block Diagram
9005p
11
LTM9005
Operation
Description
• RF Input Port
The LTM9005 is an integrated System in a Package (SiP)
that includes a high-speed 14-bit A/D converter, two lowdistortion fixed-gain amplifiers, a SAW filter, a continuously
variable attenuator and an active mixer. The LTM9005 is
designed for very compact IF sampling applications with
RF input frequencies up to 3.8GHz. Typical applications
include wireless base stations, remote radio heads and
communications test instrumentation.
• LO Input Port
All of the supply bypassing and passive filtering has been
included inside the LTM9005 making the total solution size
extremely small. Furthermore, the tight coupling makes
the performance more consistent and less dependent on
board layout. Great care has been taken to protect sensitive signals from noise within the µModule package and
isolate the RF section from the digital section.
The overall gain is optimized for the dynamic range of the
ADC relative to the RF input level allowed by the mixer. The
equivalent cascaded noise figure is 16dB. The RF input
level for –1dBFs is typically –19dBm.
The following sections describe the operation of each
functional element. The SiP technology allows the
LTM9005 to be customized and this is described in the
Semi-Custom Options section. The outline of the remaining
sections follows the basic functional elements as shown
in Figure 2.
VCC1
VCC2
VCC3
VDD
OVDD
ATTENUATOR
RF
MIXER
1ST
AMPLIFIER
SAW
2ND
AMPLIFIER
BPF
ADC
LTM9005
GND
LO GAIN CONTROL
OGND
9005 F02
ADC CLK
Figure 2. Basic Functional Elements
The Applications section describes the design considerations and recommendations for interfacing to the key
ports and functions as well as board layout in the following order:
• ADC Clock Input Port
• GAIN Control Input
• SENSE and Reference Input
• Digital Outputs
• Shutdown Control
• Power Supplies
• Layout
Semi-Custom Options
The µModule construction affords a new level of flexibility
in application-specific standard products. Standard mixedsignal, IF and RF components can be integrated regardless
of their process technology and matched with passive
components to a particular application. The LTM9005‑AA,
as the first example, is configured with a 14-bit ADC
sampling at rates up to 125Msps. The total system gain
is 22dB of which 20dB is variable. The IF is fixed by the
SAW filter at 140MHz with 16MHz bandwidth. The RF range
is matched for 1.6GHz to 2.3GHz with external matching
required to achieve 400MHz to 3.8GHz.
However, other options are possible through Linear
Technology’s semi-custom development program. Linear
Technology has in place a program to deliver other speed,
resolution, RF/IF range, gain and filter configurations for
nearly any specified application. ADC resolution and speed
options range from 14-bits and 125Msps to 10-bits and
10Msps. The IF can be set from 70MHz to about 270MHz
with bandwidths from a few MHz to about 60MHz. These
semi-custom designs are based on existing ADCs, amplifiers, filters and mixers with appropriately modified
matching networks. The final subsystem is then tested
to the exact parameters defined for the application. The
final result is a fully integrated, accurately tested and
optimized solution in the same package. For more details
on the semi-custom receiver subsystem program, contact
Linear Technology.
9005p
12
LTM9005
Operation
Down-Converting Mixer
Analog to Digital Converter
The mixer stage consists of a high linearity double-balanced mixer, RF buffer amplifier, high speed limiting LO
buffer amplifier and bias/enable circuits. The RF and LO
inputs are both single ended. Low side or high side LO
injection can be used.
The analog-to-digital converter (ADC) is a CMOS pipelined
multistep converter. The converter has six pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later (see Digital Output Bus Timing). The
CLK input is single-ended. The ADC has two phases of
operation, determined by the state of the CLK input pin.
The RF input consists of an integrated transformer and a
high linearity differential amplifier. The primary terminals of
the transformer are connected to the RF input and ground.
The secondary side of the transformer is internally connected to the amplifier’s differential inputs.
The LO input consists of an integrated transformer and
high speed limiting differential amplifiers. The amplifiers
are designed to precisely drive the mixer for the highest
linearity and the lowest noise figure.
Attenuator
A dual PIN diode with common-cathode connection is
used for continuously variable attenuation. The anodes
are connected to the outputs of the mixer and pulled up
to VCC1 through 100nH inductors. The cathode includes a
series 50Ω resistor to GAIN. See the GAIN Control Input
section for applications information.
First and Second Amplifiers
The amplifiers used in the LTM9005 are low noise and
low distortion fully differential ADC drivers. The amplifiers are fully differential amplifiers with on chip feedback
resistors.
SAW Filter
A high selectivity, surface acoustic wave (SAW) filter is
integrated in the LTM9005.
(Applications to provide additional text)
Each pipelined stage contains an ADC, a reconstruction
DAC and an interstage residue amplifier. In operation, the
ADC quantizes the input to the stage and the quantized
value is subtracted from the input by the DAC to produce a
residue. The residue is amplified and output by the residue
amplifier. Successive stages operate out of phase so that
when the odd stages are outputting their residue, the even
stages are acquiring that residue and visa versa.
When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors.
At the instant that CLK transitions from low to high, the
sampled input is held. While CLK is high, the held input
voltage is buffered by the S/H amplifier which drives the
first pipelined ADC stage. The first stage acquires the
output of the S/H during this high phase of CLK. When
CLK goes back low, the first stage produces its residue
which is acquired by the second stage. At the same time,
the input S/H goes back to acquiring the analog input.
When CLK goes back high, the second stage produces its
residue which is acquired by the third stage. An identical
process is repeated for the third, fourth and fifth stages,
resulting in a fifth stage residue that is sent to the sixth
stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
Band-Pass Filter
An L-C bandpass filter follows the second amplifier to
prevent aliasing and to minimize the noise contribution
of the second amplifier.
(Applications to provide additional text)
9005p
13
LTM9005
Applications Information
RF Input Port
The RF input is shown in Figure 3 and is internally matched
from 1.6GHz to 2.3GHz, requiring no external components
over this frequency range. The input return loss, shown
in Figure 4, is typically 12dB at the band edges. The input
match at the lower band edge can be optimized with a
series 3.9pF capacitor at Pin M3, which improves the
1.6GHz return loss to greater than 25dB. Likewise, the
2.3GHz match can be improved to greater than 25dB with
a series 1.5nH inductor. A series 2.7nH/2.2pF network will
simultaneously optimize the lower and upper band edges
and expand the RF input bandwidth to 1.2GHz to 2.5GHz.
Measured RF input return losses for these three cases are
also plotted in Figure 4.
LOW-PASS MATCH
FOR 450MHz, 900MHz
and 3.6GHz RF
TO
MIXER
ZO = 50Ω
L = L (mm)
RFIN
3
RF
C5
9005 F03
C5
HIGH-PASS MATCH
FOR 2.6GHz RF
AND WIDEBAND RF
L5
0
Figure 3. RF Input Schematic
RF PORT RETURN LOSS (dB)
0
NO EXT MATCH
–5
Input return losses for the 450MHz, 900MHz, 2.6GHz and
3.6GHz applications are plotted in Figure 5. The input return
loss with no external matching is repeated in Figure 5 for
comparison. The 2.6GHz RF input match uses the high-pass
matching network shown in Figure 3 with C5 = 3.9pF and
L5 = 3.6nH. The high-pass input matching network is also
used to create a wideband or dual-band input match. For
example, with C5 = 3.3pF and L5 = 10nH, the RF input is
matched from 800MHz to 2.2GHz, with optimum matching
in the 800MHz to 1.1GHz and 1.6GHz to 2.2GHz bands,
simultaneously.
RF PORT RETURN LOSS (dB)
RFIN
Alternatively, the input match can be shifted as low as
400MHz or up to 3800MHz by adding a shunt capacitor
(C5) to the RF input. A 450MHz input match is realizedwith
C5 = 12pF, located 6.5mm away from Pin M3 on a 50Ω
input transmission line. A 900MHz input match requires
C5 = 3.9pF, located at 1.7mm. A 3.6GHz input match is
realized with C5 = 1pF, located at 2.9mm. This series
transmission line/shunt capacitor matching topology
allows the LTM9005 to be used for multiple frequency
standards without circuit board layout modifications. The
series transmission line can also be replaced with a series
chip inductor for a more compact layout.
–5
–10
–15
450MHz
L = 6.5mm
C5 = 12pF
900MHz
L = 1.7mm
C5 = 3.9pF
–20
–25
–10
–30
0.2
–15
–20
–25
SERIES 2.7nH
AND 2.2pF
SERIES 3.9pF
–30
0.2
0.7
1.2
0.7
1.2
3.6GHz
L = 2.9mm
C5 = 1pF
NO EXT
MATCH
1.7 2.2 2.7 3.2
FREQUENCY (GHz)
3.7
2.6GHz
SERIES 3.9pF
SHUNT 3.6nH
4.2
9005 F05
Figure 5. RF Input Return Loss with and Without Matching
SERIES 1.5nH
1.7 2.2 2.7 3.2
FREQUENCY (GHz)
3.7
4.2
9005 F04
Figure 4. Series Reactance Matching
9005p
14
LTM9005
Applications Information
RF input impedance and S11 versus frequency (with no
external matching) are listed in Table 1 and referenced
to Pin M3. The S11 data can be used with a microwave
circuit simulator to design custom matching networks and
simulate board-level interfacing to the RF input filter.
EXTERNAL
MATCHING
FOR LO < 1GHz
LOIN
TO
MIXER
L4
15
LO
C4
LIMITER
Table 1 RF Input Impedance vs Frequency
FREQUENCY
(MHz)
INPUT
IMPEDANCE
S11
MAG
ANGLE
50
4.6 + j2.3
0.832
174.7
300
9.1 + j11.2
0.706
153.8
450
12.0 + j14.5
0.639
145.8
REGULATOR
VCC1
14.7 + j17.4
0.588
138.7
20.5 + j23.3
0.506
123.4
1300
34.4 + j30.3
0.380
97.5
1700
59.6 + j23.8
0.299
55.8
1950
69.2 + j2.8
0.163
6.9
2200
59.2 – j18.1
0.184
–53.5
2450
41.5 – j24.5
0.274
–94.2
2700
28.3 – j21.3
0.374
–120.3
3000
19.0 – j13.5
0.481
–145.5
3300
13.9 – j5.1
0.568
–167.3
3600
10.8 + j3.4
0.645
171.9
3900
9.4 + j12.3
0.700
151.4
RF Input Overload
In the event of an overload condition at the RF input, (Applications to provide additional text following
characterization).
LO Input Port
The LO input, shown in Figure 6, is internally matched from
1GHz to 5GHz. The input match can be shifted down, as
low as 750MHz, with a single shunt capacitor (C4) on Pin
M6. One example is plotted in Figure 7 where C4 = 2.7pF
produces a 50MHz to 1GHz match.
9005 F06
Figure 6. LO Input Schematic
0
LO PORT RETURN LOSS (dB)
600
900
VREF
–10
NO EXT
MATCH
–20
–30
L4 = 10nH
C4 = 8.2pF
L4 = 2.7nH
C4 = 3.9pF
0.3
L4 = 0
C4 = 2.7pF
1
LO FREQUENCY (GHz)
5
9005 F07
Figure 7. LO Input Return Loss
LO input matching below 750MHz requires the series
inductor (L4)/shunt capacitor (C4) network shown in
Figure 6. Two examples are plotted in Figure 7 where
L4 = 2.7nH/C4 = 3.9pF produces a 650MHz to 830MHz
match and L4 = 10nH/C4 = 8.2pF produces a 460MHz to
560MHz match.
The optimum LO drive is –3dBm for LO frequencies above
1.2GHz, although the amplifiers are designed to accommodate several dB of LO input power variation without
significant mixer performance variation. Below 1.2GHz,
0dBm LO drive is recommended for optimum noise figure,
although –3dBm will still deliver good conversion gain
and linearity.
9005p
15
LTM9005
Applications Information
Custom matching networks can be designed using the port
impedance data listed in Table 2. This data is referenced
to the LO pin with no external matching.
Table 2 LO Input Impedance vs Frequency
FREQUENCY
(MHz)
INPUT
IMPEDANCE
MAG
S11
ANGLE
50
10.0 – j326
0.991
–17.4
300
80.5 – j41.9
0.820
–99.2
500
11.8 – j10.1
0.632
–155.9
to SENSE. It is not recommended to drive the SENSE pin
with a logic device. The SENSE pin should be tied to the
appropriate level as close to the converter as possible. If
the SENSE pin is driven externally, note that this pin is
filtered internally with a 50Ω series resistor and a 0.1µF
capacitor to ground.
ADC Clock Input
The CLK input can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with a
low-jitter squaring circuit before the CLK pin (Figure 8).
700
18.8 + j10.9
0.474
151.8
900
35.0 + j27.4
0.350
100.8
1200
72.9 + j19.3
0.241
31.3
1500
70.0 – j12.6
0.196
–26.1
1800
55.0 – j17.0
0.167
–64.3
2200
47.8 – j9.7
0.102
–97.2
FERRITE
BEAD
2600
53.6 – j1.9
0.039
–26.8
0.1µF
3000
66.7 + j0.7
0.143
2.1
3500
82.1 – j13.9
0.263
–17.4
4000
69.0 – j30.1
0.290
–43.5
4500
43.7 – j13.2
0.154
–107.5
5000
36.4 + j19.8
0.271
111.6
LO Input Overload
Text to come.
Reference Operation
The LTM9005 includes an internal voltage reference that
is internally bypassed. An external reference can be used
or the internal reference can be configured for two pin
selectable input ranges. Tying the SENSE pin to VDD selects
the default range; tying the SENSE pin to 1.5V selects a
3dB lower range.
Other voltage ranges in-between the pin selectable ranges
can be programmed. An external reference can be used by
applying its output directly or through a resistive divider
CLEAN
SUPPLY
4.7µF
SINUSOIDAL
CLOCK
INPUT
1k
0.1µF
50Ω
1k
CLK
LTM9005
NC7SVU04
9005 F08
Figure 8. Sinusoidal Single-Ended CLK Driver
The noise performance of the ADC can depend on the
clock signal quality as much as on the analog input. Any
noise present on the CLK signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
In applications where jitter is critical, use as large an
amplitude as possible. Also, if the ADC is clocked with a
sinusoidal signal, filter the CLK signal to reduce wideband
noise and distortion products generated by the source.
Figure 9 and Figure 10 show alternatives for converting a
differential clock to the single-ended CLK input. The use
of a transformer provides no incremental contribution
9005p
16
LTM9005
Applications Information
depending on transmission line length may require a 10Ω
to 20Ω series resistor to act as both a lowpass filter for
high frequency noise that may be induced into the clock
line by neighboring digital signals, as well as a damping
mechanism for reflections.
CLEAN
SUPPLY
4.7µF
FERRITE
BEAD
0.1µF
CLK
Maximum and Minimum Conversion Rates
LTM9005
100Ω
9005 F09
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
Figure 9. CLK Driver Using an LVDS or PECL to CMOS Converter
ETC1-1T
CLK
Clock Duty Cycle Stabilizer
LTM9005
5pF-30pF
DIFFERENTIAL
CLOCK
INPUT
9005 F10
0.1µF
The maximum conversion rate for the ADC is 125Msps.
The lower limit of the sample rate is determined by the
droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency
for the LTM9005 is 1Msps.
FERRITE
BEAD
VCM
Figure 10. LVDS or PECL CLK Drive Using a Transformer
to phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz will
degrade the SNR compared to the transformer solution.
The nature of the received signals also has a large bearing
on how much SNR degradation will be experienced. For
high crest factor signals such as WCDMA or OFDM, the
use of these translators will have a lesser impact.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may
be desirable in cases where lower voltage differential
signals are considered. The center tap may be bypassed
to ground through a capacitor close to the ADC if the
differential signals originate on a different plane. The
use of a capacitor at the input may result in peaking, and
An optional clock duty cycle stabilizer circuit ensures high
performance even if the input clock has a non 50% duty
cycle. Using the clock duty cycle stabilizer is recommended
for most applications. To use the clock duty cycle stabilizer,
the MODE pin should be connected to 1/3VDD or 2/3VDD
using external resistors.
This circuit uses the rising edge of the CLK pin to sample
the analog input. The falling edge of CLK is ignored and
the internal falling edge is generated by a phase-locked
loop. The input clock duty cycle can vary from 40% to
60% and the clock duty cycle stabilizer will maintain a
constant 50% internal duty cycle. If the clock is turned off
for a long period of time, the duty cycle stabilizer circuit
will require a hundred clock cycles for the PLL to lock
onto the input clock.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50% (±5%) duty cycle.
GAIN Control Input
The total receiver gain is continuously adjustable using a
PIN diode. Maximum gain is set by forcing GAIN to VCC1.
9005p
17
LTM9005
Applications Information
Minimum gain is achieved by sinking approximately 10mA
from the GAIN pin. If the gain is to be adjusted as part of
an active control loop then the circuit in Figure 11 can be
used. See the Typical Performance Characteristics for the
transfer function.
VCC1
LTM9005
Digital Output Modes
Figure 12 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated
from the ADC power and ground. The additional N-channel
transistor in the output driver allows operation down to
low voltages. The internal resistor in series with the output
makes the output appear as 50Ω to external circuitry and
may eliminate the need for external damping resistors.
LTM9005
VDD
OVDD 0.5V
TO 3.6V
VDD
OVDD
49.9Ω
GAIN
DATA
FROM
LATCH
TBDΩ
PREDRIVER
LOGIC
43Ω
OE
9005 F11
TYPICAL
DATA
OUTPUT
OGND
Figure 11. Automatic Gain Control Circuit
The DAC used to control GAIN will contribute a non-negligible amount of voltage noise. (Text to come—discuss
further and provide noise analysis.)
In some applications it may be sufficient to permanently
set the gain to a fixed level. This simplifies the circuitry as
a fixed resistor to ground can be implemented.
Digital Outputs
Table 3 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
Table 3. Output Codes vs Input Voltage, LTM9005-AA
INPUT
(SENSE = VDD)
Overvoltage
Maximum
Minimum
Undervoltage
OF
D13 – D0
(OFFSET BINARY)
D13 – D0
(2’S COMPLEMENT)
1
0
0
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
0
0
0
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
0
0
1
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
9005 F12
Figure 12. Digital Output Buffer
As with all high speed/high resolution converters the digital
output loading can affect the performance. The digital
outputs of the ADC should drive a minimal capacitive load
to avoid possible interaction between the digital outputs
and sensitive input circuitry. For full speed operation, the
capacitive load should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the ADC parallel digital output can
be selected for offset binary or 2’s complement format.
Connecting MODE to GND or 1/3VDD selects straight binary
output format. Connecting MODE to 2/3VDD or VDD selects
2’s complement output format. An external resistive divider
can be used to set the 1/3VDD or 2/3VDD logic values.
Table 5 shows the logic states for the MODE pin.
9005p
18
LTM9005
Applications Information
Table 4. MODE Pin Function
MODE PIN
OUTPUT FORMAT
CLOCK DUTY CYCLE
STABILIZER
0
Straight Binary
Off
1/3VDD
Straight Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overflow Bit
When OF outputs a logic high the converter is either overranged or underranged.
Output Clock
The ADC has a delayed version of the CLK input available
as a digital output, CLKOUT. The falling edge of the CLKOUT
pin can be used to latch the digital output data.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same supply that powers the logic being driven.
For example, if the converter drives a DSP powered by a
1.8V supply, then OVDD should be tied to that same 1.8V
supply.
OVDD can be powered with any voltage from 500mV up
to the VDD of the part. OGND can be powered with any
voltage from GND up to 1V and must be less than OVDD.
The logic outputs will swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The
data access and bus relinquish times are too slow to allow
the outputs to be enabled and disabled during full speed
operation. The output Hi-Z state is intended for use during
long periods of inactivity.
Shutdown Modes
The LTM9005 provides several levels of shutdown. The
mixer, both amplifiers and the ADC can all be shut down
independently. Furthermore, the ADC may be placed in
shutdown or nap modes to conserve power. Connecting
ADCSHDN to GND results in normal operation. Connecting
ADCSHDN to VDD and OE to VDD results in sleep mode,
which powers down all circuitry including the reference
and the ADC typically dissipates 1mW. When exiting
sleep mode, it will take milliseconds for the output data
to become valid because the reference capacitors have to
recharge and stabilize. Connecting ADCSHDN to VDD and
OE to GND results in nap mode and the ADC typically dissipates 30mW. In nap mode, the on-chip reference circuit
is kept on, so that recovery from nap mode is faster than
that from sleep mode, typically taking 100 clock cycles. In
both sleep and nap modes, all digital outputs are disabled
and enter the Hi-Z state.
Amplifier Shutdown
When the ADC is in sleep or nap mode, it is recommended
to shut down both the first and second amplifiers using
their respective shutdown pins, AMP1SHDN and AMP2SHDN. Connecting AMPSHDN to GND results in normal
operation. Connecting AMP1SHDN to VCC2 disables the
amplifier preceding the SAW filter and connecting AMP2SHDN to VCC3 disables the amplifier following the SAW
filter. It is recommended to tie AMP1SHDN, AMP2SHDN
and ADCSHDN together and control with 3V logic.
Mixer Enable Interface
The mixer is enabled and shut down differently than the
other functions in the LTM9005. The voltage necessary to
turn on the mixer is 2.7V. To disable the mixer, the enable
voltage must be less than 0.3V. If the EN pin is allowed
to float, the mixer will tend to remain in its last operating
state. Thus it is not recommended that the enable function
be used in this manner. If the shutdown function is not
required, then the EN pin should be connected directly
to VCC1.
Supply Sequencing
The VCC pins provide the supplies to the mixer and both
amplifiers. The VDD pin provides the supply to the ADC.
Each VCC pin is brought out separately and internally
bypassed. The mixer, both amplifiers and the ADC are
separate integrated circuits within the LTM9005; however,
there are no supply sequencing considerations beyond
9005p
19
LTM9005
Applications Information
standard practice. It is recommended that all supply
inputs use the same low noise, 3.3V supply, but the ADC
and the amplifiers may be operated from a lower voltage
level if desired. All three rails can operate from the same
3.3V linear regulator but place a ferrite bead between
the supply pins. Separate linear regulators can be used
without additional supply sequencing circuitry if they have
common input supplies.
Grounding and Bypassing
The LTM9005 requires a printed circuit board with a clean
unbroken ground plane; a multilayer board with an internal
ground plane is recommended. The pinout of the LTM9005
has been optimized for a flow-through layout so that the
interaction between inputs and digital outputs is minimized.
The placement of critical pads allows for those signals to
be routed on the top layer.
The ground planes within the LTM9005 are broken in to
three areas: RF ground, IF ground and digital ground.
The mixer (VCC1) and first amplifier (VCC2) return to RF
ground. In Figure ?, this area is to the left of the line starting between pads M6 and M7 and ending between pads
A10 and A11. The RF ground plane is bridged to the IF
ground plane by the SAW filter. All GND pins can connect
to the same ground plane. It is not necessary to break
these ground planes on the circuit board but the pads are
separated and available for use.
The second amplifier (VCC3) and the analog portion of the
ADC (VDD) return to IF ground. All GND pads to the right
of line described above are IF ground. The IF ground plane
is bridged to the digital ground plane by the ADC die. The
digital ground plane uses the OGND pads and extends
under all of the digital output pads.
The LTM9005 is internally bypassed with the mixer (VCC1),
first amplifier (VCC2), second amplifier (VCC3) and ADC
(VDD) supplies returning to ground (GND). The digital
output supply (OVDD) is returned to OGND. Additional
bypass capacitance is optional and may be required if
power supply noise is significant.
Heat Transfer
Most of the heat generated by the LTM9005 is transferred
through the bottom-side ground pads. For good electrical
and thermal performance, it is critical that all ground pins
are connected to a ground plane of sufficient area with as
many vias as possible.
IF GND
RF GND
DIGITAL GND
A1
9005 F13
Figure 13
9005p
20
LTM9005
Applications Information
Recommended Layout
The high integration of the LTM9005 makes the PCB board
layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations
are still necessary.
• Use large PCB copper areas for ground. This helps to
dissipate heat in the package through the board and
also helps to shield sensitive on-board analog signals.
Common ground (GND) and output ground (OGND)
are electrically isolated on the LTM9005, but can be
connected on the PCB underneath the part to provide
a common return path.
• Use multiple ground vias. Using as many vias as possible
helps to improve the thermal performance of the board
and creates necessary barriers sepa-rating analog and
digital traces on the board at high frequencies.
• Separate analog and digital traces as much as possible, using vias to create high-frequency barriers.
This will reduce digital feedback that can reduce the
signal-to-noise ratio (SNR) and dynamic range of the
LTM9005.
• Connect pad A8 to B8 on the top layer with no other
connections. These pads should not be connected to
any other circuitry or ground. Keep these two pads free
from noise. Connect A9 to B9, L8 to M8 and L9 to M9
in the same manner.
Figure # through ## give a good example of the recommended layout.
The quality of the paste print is an important factor in
producing high yield assemblies. It is recommended to
use a type 3 or 4 printing no-clean solder paste. The solder
stencil design should follow the guidelines outlined in Application Note 100. Avoid ultrasonic cleaning.
The LTM9005 employs gold-finished pads for use with
Pb-based or tin-based solder paste. It is inherently Pb-free
and complies with the JEDEC (e4) standard. The materials declaration is available online at http://www.linear.
com/leadfree/mat_dec.jsp.
9005p
21
LTM9005
Applications Information
DC1391B.zip
Layer: top.cmp
Layer 1
DC1391B.zip
Layer: inner1.lyr
DC1391B.zip
Layer: inner4.lyr
DC1391B.zip
Layer: bottom.sol
Layer 2
Layer 3
Layer 4
26 Jan 2009,08:23 AM
26 Jan 2009,08:23 AM
9005p
22
LTM9005
Package Description
LGA Package
204-Lead (22mm × 15mm × 4.32mm)
(Reference LTC DWG # 05-08-1841 Rev Ø)
aaa Z
15
BSC
X
4.22 – 4.42
Y
M
L
K
J
H
G
F
E
D
C
B
Ø(0.635)
PAD 1
A
1
0.12 – 0.28
2
PAD 1
CORNER
3
4
4
5
6
7
8
22
BSC
20.32
BSC
9
10
MOLD
CAP
SUBSTRATE
11
12
0.27 – 0.37
3.95 – 4.05
13
1.27
BSC
Z
bbb Z
DETAIL B
14
15
16
17
aaa Z
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
PACKAGE TOP VIEW
PADS
SEE NOTES
13.97
BSC
3
PACKAGE BOTTOM VIEW
DETAIL B
0.635 ±0.025 SQ. 204x
DETAIL A
eee S X Y
10.1600
8.8900
7.6200
DETAIL A
6.3500
5.0800
3.8100
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2.5400
2. ALL DIMENSIONS ARE IN MILLIMETERS
1.2700
0.0000
1.2700
3
LAND DESIGNATION PER JESD MO-222
4
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
2.5400
5. PRIMARY DATUM -Z- IS SEATING PLANE
3.8100
6. THE TOTAL NUMBER OF PADS: 204
5.0800
LTMXXXXXX
µModule
COMPONENT
PIN “A1”
TRAY PIN 1
BEVEL
SYMBOL TOLERANCE
aaa
0.15
bbb
0.10
eee
0.05
6.3500
7.6200
PACKAGE IN TRAY LOADING ORIENTATION
LGA 204 0209 REV Ø
8.8900
10.1600
SUGGESTED PCB LAYOUT
TOP VIEW
9005p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTM9005
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
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LTC2226
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LTC2227
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LTC2228
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LTC2229
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LTC2245
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LTC2246
14-Bit, 25Msps ADC
75mW, 74dB SNR, 5mm × 5mm QFN
LTC2247
14-Bit, 40Msps ADC
125mW, 74dB SNR, 5mm × 5mm QFN
LTC2248
14-Bit, 65Msps ADC
210mW, 74dB SNR, 5mm × 5mm QFN
LTC2249
14-Bit, 80Msps ADC
230mW, 73dB SNR, 5mm × 5mm QFN
LTC2252
12-Bit, 105Msps, 3V ADC, Lowest Power
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LTC2253
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LTC2254
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320mW, 72.4dB SNR, 88dB SFDR, 32-Pin QFN Package
LTC2255
14-Bit, 125Msps ADC, 3V ADC, Lowest Power
395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN Package
LT5527
400MHz to 3.7GHz, 5V High Signal Level
Downconverting Mixer
23.5dBm IIP3 at 1.9GHz, NF = 12.5dB, Single-Ended RF and
LO Ports
LT5557
800MHz to 2.7GHz High Linearity Direct Conversion
Quadrature Demodulator
24.7dBm IIP3 at 1.9GHz, NF = 11.7dB, Single-Ended RF and LO
Ports, 3.3V Supply
LTC6400-8/LTC6400-14/
LTC6400-20/LTC6400-26
Low Noise, Low Distortion Differential Amplifier for 300MHz
IF, Fixed Gain of 8dB, 14dB, 20dB or 26dB
3V, 90mA, 39.5dBm OIP3 at 300MHz, 6dB NF
LTC6401-8/LTC6401-14/
LTC6401-20/LTC6401-26
Low Noise, Low Distortion Differential Amplifier for 140MHz
IF, Fixed Gain of 8dB, 14dB, 20dB or 26dB
3V, 45mA, 45.5dBm OIP3 at 140MHz, 6dB NF
LTM9001
16-Bit, High-Speed Receiver Subsystem
µModule Receiver with ADC, Fixed Gain Amplifier and
Anti-Alias Filter in 11.25mm × 11.25mm LGA
LTM9002
14-Bit, High-Speed Dual Receiver Subsystem
µModule Receiver with Dual ADC, Dual Amplifiers, Anti-Alias
Filters and a Dual Trim DAC in 15mm × 11.25mm LGA
9005p
24 Linear Technology Corporation
LT 1010 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2010
Electrical Specifications Subject to Change
LTM9004
14-Bit Direct Conversion
Receiver Subsystem
FEATURES
DESCRIPTION
n
The LTM®9004 is a 14-bit direct conversion receiver
subsystem. Utilizing an integrated system in a package
(SiP) technology, the LTM9004 is a μModule® receiver that
includes a dual high speed 14-bit A/D converter, lowpass
filter, differential gain stages and a quadrature demodulator.
Contact Linear Technology regarding customization.
n
n
n
n
n
n
n
n
n
n
n
n
Integrated Dual 14-Bit, High-Speed ADC, Lowpass
Filter, Differential Gain Stages and I/Q Demodulator
Lowpass Filter for Each ADC Channel
1.92MHz (LTM9004-AA)
4.42MHz (LTM9004-AB)
9.42MHz (LTM9004-AC)
20MHz (LTM9004-AD)
RF Input Frequency Range: 0.8GHz to 2.7GHz
50Ω Single-Ended RF and LO Ports
I/Q Gain Mismatch: 0.2dB Typical
I/Q Phase Mismatch: 1.5 Deg Typical
Voltage-Adjustable Demodulator DC Offsets
76dB/1.92MHz SNR (LTM9004-AA)
63.5dB SFDR (LTM9004-AA)
Clock Duty Cycle Stabilizer
Low Power: 1.83W
Shutdown and Nap Modes
15mm × 22mm LGA Package
APPLICATIONS
n
n
n
Telecommunications
Direct Conversion Receivers
Cellular Basestations
The LTM9004 is perfect for zero-IF communications
applications, with AC performance that includes 76dB
SNR and 63.5dB spurious free dynamic range (SFDR).
The entire chain is DC-coupled and provides access for
DC offset adjustment. The integrated on-chip broadband
transformers provide 50Ω single-ended interfaces at the
RF and LO inputs.
A 5V supply powers the mixer and first amplifier for
minimal distortion while a 3V supply allows low power
ADC operation. A separate supply allows the outputs to
drive 0.5V to 3.3V logic. An optional multiplexer allows
both channels to share a digital output bus. An optional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. μModule is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
VCC1 = 5V
LTM9004-AA: 64k Point FFT
fIN = 1950.5MHz, –1dBFS
SENSE = VDD
VCC3 = 3V
VDD
VCC2
0VDD
0.5V TO
3.6V
0
–10
–20
ADC
0°
CLKOUT
LNA
ADC CLK
MUX
OF
90°
ADC
AMPLITUDE (dBFS)
I
–30
–40
–50
HD2
–60
HD3
–70
–80
–90
–100
Q
–110
OFFSET ADJUST
OGND
LTM9004-AD
DC OFFSET
CONTROL
LO
–120
0
4
8
12
16
20
FREQUENCY (MHz)
GND
9004 TA01b
DAC
9004 TA01
9004p
1
LTM9004
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage (VCC1, VCC2)...................... –0.3V to 5.5V
Supply Voltage (VCC3, LTM9004-AA,
LTM9004-AB) ............................................ –0.3V to 5.5V
Supply Voltage (VCC3, LTM9004-AC,
LTM9004-AD)............................................ –0.3V to 3.5V
Supply Voltage (VDD, OVDD)...................... –0.3V to 4.0V
Digital Output Ground Voltage (OGND) ........ –0.3V to 1V
LO Input Power ....................................................10dBm
RF Input Power ....................................................20dBm
RF Input DC Voltage ...............................................±0.1V
LO Input DC Voltage ..............................................±0.1V
x_ADJ Input Voltage ........................–0.3V to VCC1, VCC2
SENSE Input Voltage .................................. –0.3V to VDD
Digital Input Voltage
(MIXENABLE)...............................–0.3V to (VCC1 + 0.3V)
Digital Input Voltage
(AMP1ENABLE) ...........................–0.3V to (VCC2 + 0.3V)
Digital Input Voltage
(AMP2ENABLE) ...........................–0.3V to (VCC2 + 0.3V)
Digital Input Voltage (except MIXENABLE and
AMPxENABLE) ..............................–0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation ................................................TBD W
Operating Temperature Range
LTM9004C................................................ 0°C to 70°C
LTM9004I............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
θJA
LGA
TJMAX = 125°C, θJA = 15°C/W, θJC = 6°C/W
Derived from TBDmm × TBDmm PCB with 4 Layers Weight = TBD g
CAUTION: This part is sensitive to electrostatic discharge
(ESD). It is very important that proper ESD precautions
be observed when handling the RF and LO inputs of the
LTM9004.
ORDER INFORMATION
LEAD FREE FINISH
TRAY
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTM9004CV-AA#PBF
LTM9004CV-AA#PBF
LTM9004V AA
204-Lead (15mm × 22mm × 2.8mm) LGA
0°C to 70°C
LTM9004IV-AA#PBF
LTM9004IV-AA#PBF
LTM9004V AA
204-Lead (15mm × 22mm × 2.8mm) LGA
–40°C to 85°C
LTM9004CV-AB#PBF
LTM9004CV-AB#PBF
LTM9004V AB
204-Lead (15mm × 22mm × 2.8mm) LGA
0°C to 70°C
LTM9004IV-AB#PBF
LTM9004IV-AB#PBF
LTM9004V AB
204-Lead (15mm × 22mm × 2.8mm) LGA
–40°C to 85°C
LTM9004CV-AC#PBF
LTM9004CV-AC#PBF
LTM9004V AC
204-Lead (15mm × 22mm × 2.8mm) LGA
0°C to 70°C
LTM9004IV-AC#PBF
LTM9004IV-AC#PBF
LTM9004V AC
204-Lead (15mm × 22mm × 2.8mm) LGA
–40°C to 85°C
LTM9004CV-AD#PBF
LTM9004CV-AD#PBF
LTM9004V AD
204-Lead (15mm × 22mm × 2.8mm) LGA
0°C to 70°C
LTM9004IV-AD#PBF
LTM9004IV-AD#PBF
LTM9004V AD
204-Lead (15mm × 22mm × 2.8mm) LGA
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
9004p
2
LTM9004
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC1 = VCC2 = 5V, VDD = OVDD = 3V, VCC3 = 3V
(LTM9004-AC, LTM9004-AD), VCC3 = 5V (LTM9004-AA, LTM9004-AB), PLO = 0dBm. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
RF Input Frequency Range
No External Matching (High Band)
With External Matching (Low Band, Mid Band)
1.5 to 2.7
0.8 to 1.5
GHz
GHz
LO Input Frequency Range
No External Matching (High Band)
With External Matching (Low Band, Mid Band)
1.5 to 2.7
0.8 to 1.5
GHz
GHz
Baseband Frequency Range
LTM9004-AA
LTM9004-AB
LTM9004-AC
LTM9004-AD
DC to 1.92
DC to 4.42
DC to 9.42
DC to 20
MHz
MHz
MHz
MHz
TYP
MAX
UNITS
RF Input Return Loss
Z0 = 50Ω, 1.5GHz to 2.7GHz, Internally Matched
>10
dB
LO Input Return Loss
Z0 = 50Ω, 1.5GHz to 2.7GHz, Internally Matched
>10
dB
RF Input Power for –1dBFS
RF = 1950MHz
–7.3
dBm
–13 to 5
dBm
LO Input Power
I/Q Gain Mismatch
0.2
I/Q Phase Mismatch
fLPF
MIN
dB
1.5
Deg
LO to RF Leakage
RF = 900MHz
RF = 1900MHz
–60.8
–64.6
dBm
dBm
RF to LO Isolation
RF = 900MHz
RF = 1900MHz
59.7
57.1
dB
dB
Maximum DC Offset Voltage, No RF
(Note 5)
35
mV
DC Offset Variation
–40°C to 85°C
210
μV/°C
Gain Flatness
DC to 1.92MHz (LTM9004-AA)
DC to 4.42MHz (LTM9004-AB)
DC to 9.42MHz (LTM9004-AC)
DC to 20MHz (LTM9004-AD)
0.2
0.2
0.2
0.3
dB
dB
dB
dB
Group Delay Flatness
DC to 1.92MHz (LTM9004-AA)
DC to 4.42MHz (LTM9004-AB)
DC to 9.42MHz (LTM9004-AC)
DC to 20MHz (LTM9004-AD)
15
15
15
5
nsec
nsec
nsec
nsec
Rejection
LTM9004-AA
5MHz
10MHz
5.3
33.5
dB
dB
LTM9004-AB
7.5MHz
12.5MHz
1
11
dB
dB
LTM9004-AC
12.5MHz
17.5MHz
0.5
1
dB
dB
LTM9004-AD
30MHz
40MHz
1.5
5.5
dB
dB
1dB Point (LTM9004-AA)
1dB Point (LTM9004-AB)
1dB Point (LTM9004-AC)
1dB Point (LTM9004-AD)
4
6.3
15
28
MHz
MHz
MHz
MHz
Lowpass Filter Cutoff Frequency
9004p
3
LTM9004
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC1 = VCC2 = 5V, VDD = OVDD = 3V, VCC3 = 3V (LTM9004-AC,
LTM9004-AD), VCC3 = 5V (LTM9004-AA, LTM9004-AB), PLO = 0dBm.
SYMBOL
PARAMETER
IIP3
Input 3rd-Order Intercept, 1 Tone
22
dBm
IIP2
Input 2nd-Order Intercept, 1 Tone
58
dBm
SNR
Signal-to-Noise Ratio at –1dBFS
1.92MHz (LTM9004-AA)
4.42MHz (LTM9004-AB)
9.42MHz (LTM9004-AC)
20MHz (LTM9004-AD)
SFDR
Spurious Free Dynamic Range 2nd or
3rd Harmonic at –1dBFS
LTM9004-AA
RF = 1950.5MHz, LO =1950MHz
SFDR
S/(N+D)
HD2
HD3
Spurious Free Dynamic Range 4th or
Higher at –1dBFS
Signal-to-Noise Plus Distortion Ratio
at –1dBFS
2nd Order Harmonic Distortion Ratio
at –1dBFS
3rd Order Harmonic Distortion Ratio
at –1dBFS
CONDITIONS
MIN
l
l
l
l
70.6
69.7
70.3
66.3
TYP
MAX
UNITS
76.1
75.2
72
68.9
dB/1.92MHz
dB/4.42MHz
dB/9.42MHz
dB/20MHz
63.5
dB
LTM9004-AB
RF = 1951MHz, LO =1950MHz
65
dB
LTM9004-AC
RF = 1952.5MHz, LO =1950MHz
66
dB
LTM9004-AD
RF = 1955MHz, LO =1950MHz
64
dB
LTM9004-AA
RF = 1950.5MHz, LO =1950MHz
88
dB
LTM9004-AB
RF = 1951MHz, LO =1950MHz
91
dB
LTM9004-AC
RF = 1952.5MHz, LO =1950MHz
89
dB
LTM9004-AD
RF = 1955MHz, LO =1950MHz
89
dB
58.5
dB
LTM9004-AB
RF = 1951MHz, LO =1950MHz
60
dB
LTM9004-AC
RF = 1952.5MHz, LO =1950MHz
61
dB
LTM9004-AD
RF = 1955MHz, LO =1950MHz
60
dB
LTM9004-AA
RF = 1950.5MHz, LO =1950MHz
64
dB
LTM9004-AB
RF = 1951MHz, LO =1950MHz
66
dB
LTM9004-AC
RF = 1952.5MHz, LO =1950MHz
66
dB
LTM9004-AD
RF = 1955MHz, LO =1950MHz
64
dB
LTM9004-AA
RF = 1950.5MHz, LO =1950MHz
69
dB
LTM9004-AB
RF = 1951MHz, LO =1950MHz
66
dB
LTM9004-AC
RF = 1952.5MHz, LO =1950MHz
67
dB
LTM9004-AD
RF = 1955MHz, LO =1950MHz
67
dB
LTM9004-AA
RF = 1950.5MHz, LO =1950MHz
9004p
4
LTM9004
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC1 = VCC2 = 5V, VDD = OVDD = 3V. VCC3 = 3V
(LTM9004-AC, LTM9004-AD), VCC3 = 5V (LTM9004-AA, LTM9004-AB)
SYMBOL PARAMETER
CONDITIONS
MIN
l
Resolution (No Missing Codes)
TYP
MAX
14
UNITS
Bits
Integral Linearity Error (Note 4)
Differential Analog Input
±1.5
LSB
Differential Linearity Error
Differential Analog Input
±1
LSB
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC1 = VCC2 = 5V, VDD = OVDD = 3V. VCC3 = 3V
(LTM9004-AC, LTM9004-AD), VCC3 = 5V (LTM9004-AA, LTM9004-AB)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Mixer Logic Input (MIXENABLE)
VIH
High Level Input Voltage
VCC1 = 5V
l
VIL
Low Level Input Voltage
VCC1 = 5V
l
IIN
Input Current
VIN = VCC1
2
V
1
V
120
μA
Turn On Time
120
ns
Turn Off Time
750
ns
2
V
First Amplifier Logic Input (AMP1ENABLE)
VIH
High Level Input Voltage
VCC2 = 5V
l
VIL
Low Level Input Voltage
VCC2 = 5V
l
RIN
Input Pull-Up Resistance
VCC2 = 5V, VAMP1ENABLE = 0V to 0.5V
2.55
1.8
25
1.25
70
V
kΩ
Turn On Time
200
ns
Turn Off Time
50
ns
Second Amplifier Logic Input (AMP2ENABLE, LTM9004-AA, LTM9004-AB)
VIH
High Level Input Voltage
VCC3 = 5V
l
VIL
Low Level Input Voltage
VCC3 = 5V
l
RIN
Input Pull-Up Resistance
VCC3 = 5V, VAMP2ENABLE = 2.9V to 0V
VCC3 – 0.6
V
VCC3
– 2.1
40
66
90
V
kΩ
Turn On Time
4
μs
Turn Off Time
350
ns
2.55
2.25
V
0.7
0.4
V
60
100
140
kΩ
Second Amplifier Logic Input (AMP2ENABLE, LTM9004-AC, LTM9004-AD)
VIH
High Level Input Voltage
VCC3 = 3V
l
VIL
Low Level Input Voltage
VCC3 = 3V
l
RIN
Input Pull-Up Resistance
VCC3 = 3V, VAMP2ENABLE = 0V to 0.5V
Turn On Time
200
ns
Turn Off Time
50
ns
ADC Logic Inputs (CLK, OE, ADCSHDN, MODE, MUX)
VIH
High Level Input Voltage
VDD = 3V
l
2
V
VIL
Low Level Input Voltage
VDD = 3V
l
IIN
Input Current
VIN = 0V to VDD
l
CIN
Input Capacitance
(Note 6)
ISENSE
SENSE Input Leakage
0V < SENSE < 1V
l
–3
3
μA
IMODE
MODE Input Leakage
0V < MODE < VDD
l
–3
3
μA
–10
0.8
V
10
μA
3
pF
9004p
5
LTM9004
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC1 = VCC2 = 5V, VDD = OVDD = 3V. VCC3 = 3V
(LTM9004-AC, LTM9004-AD), VCC3 = 5V (LTM9004-AA, LTM9004-AB)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logic Outputs
OVDD = 3V
COZ
Hi-Z Output Capacitance
OE = 3V (Note 6)
3
pF
ISOURCE
Output Source Current
VOUT = 0V
50
mA
ISINK
Output Sink Current
VOUT = 3V
50
mA
VOH
High Level Output Voltage
IO = –10μA
IO = –200μA
l
IO = 10μA
IO = 1.6mA
l
VOL
Low Level Output Voltage
2.7
2.995
2.99
0.005
0.09
V
V
0.4
V
V
OVDD = 2.5V
VOH
High Level Output Voltage
IO = –200μA
2.49
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
OVDD = 1.8V
VOH
High Level Output Voltage
IO = –200μA
1.79
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC1 = VCC2 = 5V, VDD = OVDD = 3V. VCC3 = 3V (LTM9004-AC,
LTM9004-AD), VCC3 = 5V (LTM9004-AA, LTM9004-AB) (Note 3)
SYMBOL
PARAMETER
VCC1
Mixer Supply Voltage
l
VCC2
First Amplifier Supply Voltage
Second Amplifier Supply Voltage
VCC3
CONDITIONS
LTM9004-AA, LTM9004-AB
LTM9004-AC, LTM9004-AD
MIN
TYP
MAX
UNITS
4.5
5.25
V
l
4.5
5.25
V
l
l
4.5
2.7
3
5.25
3.5
V
V
VDD
ADC Analog Supply Voltage
l
2.7
3
3.6
V
OVDD
ADC Digital Output Supply Voltage
l
0.5
3
3.6
V
ICC1
Mixer Supply Current
l
129
180
mA
l
10
11
mA
l
52
63
mA
ICC1(SHDN) Mixer Shutdown Current
ICC2
First Amplifier Supply Current
l
7.5
9
mA
LTM9004-AA, LTM9004-AB
l
21
24
mA
LTM9004-AA, LTM9004-AB
l
0.8
4
mA
LTM9004-AC, LTM9004-AD
l
36
44
mA
LTM9004-AC, LTM9004-AD
l
0.6
4
mA
l
273
306
ICC2(SHDN) First Amplifier Shutdown Current
ICC3
Second Amplifier Supply Current
ICC3(SHDN) Second Amplifier Shutdown Current
ICC3
Second Amplifier Supply Current
ICC3(SHDN) Second Amplifier Shutdown Current
IDD
ADC Supply Current
PD(SLEEP)
Sleep Power
MIXENABLE = AMPxENABLE = 0V, ADCSHDN
= 3V, OE = 3V, No CLK
7
mW
mA
PD(NAP)
Nap Mode Power
MIXENABLE = AMPxENABLE = 0V, ADCSHDN
= 3V, OE = 0V, No CLK
33
mW
9004p
6
LTM9004
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC1 = VCC2 = 5V, VDD = OVDD = 3V. VCC3 = 3V (LTM9004-AC,
LTM9004-AD), VCC3 = 5V (LTM9004-AA, LTM9004-AB) (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PD(TOTAL)
Total Power Dissipation
LTM9004-AA, LTM9004_AB,
MIXENABLE = AMP1ENABLE =
AMP2ENABLE = 5V, ADCSHDN = 0V, fSAMPLE
= MAX
1.83
W
LTM9004-AC, LTM9004-AD
MIXENABLE = AMP1ENABLE = 5V,
AMP2ENABLE = 3V, ADCSHDN = 0V, fSAMPLE
= MAX
1.83
W
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC1 = VCC2 = 5V, VDD = OVDD = 3V. VCC3 = 3V (LTM9004-AC,
LTM9004-AD), VCC3 = 5V (LTM9004-AA, LTM9004-AB)
SYMBOL
PARAMETER
fS
Sampling Frequency
tL
CLK Low Time
tH
CLK High Time
tJITTER
Sample-and-Hold Acquisition Delay Time Jitter
tAP
Sample-and-Hold Aperture Delay
CONDITIONS
MIN
l
1
Duty Cycle Stabilizer Off (Note 6)
Duty Cycle Stabilizer Off (Note 6)
l
l
3.8
3
Duty Cycle Stabilizer Off (Note 6)
Duty Cycle Stabilizer Off (Note 6)
l
l
3.8
3
tC
MAX
UNITS
125
MHz
4
4
500
500
ns
ns
4
4
500
500
ns
ns
psRMS
0.2
0
tAPA - tAPB Aperture Delay Skew
tD
TYP
ns
TBD
CLK to DATA delay
CL = 5pF (Note 6)
l
1.4
2.7
5.4
ns
DATA to CLKOUT Skew
(tD - tC) (Note 6)
l
–0.6
0
0.6
ns
1.4
MUX to DATA Delay
CL = 5pF (Note 6)
l
2.7
5.4
ns
DATA Access Time After OE↓
CL = 5pF (Note 6)
l
4.3
10
ns
BUS Relinquish Time
(Note 6)
l
3.3
8.5
ns
Pipeline Latency
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: fSAMPLE = 125MHz, CLKI = CLKQ unless otherwise noted.
5
Cycles
Note 4: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 5: DC offset voltage is defined as the DC voltage corresponding to
the output code with LO signal applied, but no RF signal.
Note 6: Guaranteed by design, not subject to test.
9004p
7
LTM9004
TIMING DIAGRAMS
Dual Digital Output Bus Timing
tAP
ANALOG
INPUT
N+2
N
N+4
N+1
tH
N+3
N+5
tL
CLKI = CLKQ
tD
N–5
D0-D13, OF
N–4
N–3
N–2
N–1
N
tC
CLKOUT
9004 TD01
Multiplexed Digital Output Bus Timing
tIPI
DEMODULATOR
ANALOG
OUTPUT I
I
DEMODULATOR
ANALOG
OUTPUT Q
Q
I+2
I+4
I+1
tIPQ
I+3
Q+2
Q+4
Q+1
Q+3
tL
tH
CLKI = CLKQ = MUX
DI0-DI13
I–5
Q–5
I–4
Q–5
I–3
Q–3
I–2
Q–2
I–1
Q–3
I–3
Q–2
I–2
Q–1
tMD
tD
DQ0-DQ13
Q–4
I–5
Q–4
I–4
tC
CLKOUT
9004 TD02
9004p
8
LTM9004
TYPICAL PERFORMANCE CHARACTERISTICS
LTM9004-AA: 64k Point FFT
fIN = 1950.5MHz, –1dBFS
SENSE = VDD
LTM9004-AA, Baseband
Frequency Response
0
–10
0
–5
–20
–20
–10
–30
–30
–15
–40
–20
–50
–25
–40
–50
–60
–70
–80
–90
(dB)
0
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTM9004-AA: 64k Point FFT
fIN = 700.5MHz, –1dBFS
SENSE = VDD
–60
–35
–80
–90
–40
–45
–100
–100
–50
–110
–110
–55
–120
–120
0
8
4
12
16
20
0
8
4
12
16
–20
–20
–10
–30
–30
–15
–40
–20
–50
–25
–50
–60
(dB)
0
–5
AMPLITUDE (dBFS)
0
–10
–40
–60
–30
–70
–35
–80
–90
–40
–45
–100
–100
–50
–110
–110
–55
–120
–120
–70
–80
–90
16
24
32
40
–60
0
16
8
24
32
40
LTM9004-AC, Baseband
Frequency Response
–20
–20
–10
–30
–30
–15
–40
–20
–50
–25
–60
–70
–80
–90
(dB)
0
–5
AMPLITUDE (dBFS)
0
–10
–50
–60
–30
–70
–35
–80
–90
–40
–45
–100
–100
–50
–110
–110
–55
–120
–120
20
30
40
FREQUENCY (MHz)
50
60
9004 G05
8 12 16 20 24 28 32 36 40
BASEBAND FREQUENCY (MHz)
9004 G04a
LTM9004-AC: 64k Point FFT
fIN = 1952.5MHz, –1dBFS
SENSE = VDD
0
–10
10
4
9004 G04
9004 G03
LTM9004-AC: 64k Point FFT
fIN = 702.5MHz, –1dBFS
SENSE = VDD
0
0
FREQUENCY (MHz)
FREQUENCY (MHz)
–40
4 6 8 10 12 14 16 18 20
BASEBAND FREQUENCY (MHz)
LTM9004-AB, Baseband
Frequency Response
0
–10
8
2
9004 G02a
LTM9004-AB: 64k Point FFT
fIN = 1951.0MHz, –1dBFS
SENSE = VDD
LTM9004-AB: 64k Point FFT
fIN = 701.0MHz, –1dBFS
SENSE = VDD
0
0
9004 G02
9004 G01
AMPLITUDE (dBFS)
–60
20
FREQUENCY (MHz)
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–30
–70
0
10
20
30
40
FREQUENCY (MHz)
–60
50
60
9004 G06
0
8
16 24 32 40 48 56 64 72 80
BASEBAND FREQUENCY (MHz)
9004 G06a
9004p
9
LTM9004
TYPICAL PERFORMANCE CHARACTERISTICS
LTM9004-AD: 64k Point FFT
fIN = 1955.0MHz, –1dBFS
SENSE = VDD
LTM9004-AD, Baseband
Frequency Response
0
–10
0
–5
–20
–20
–10
–30
–30
–15
–40
–50
–60
–70
–80
–90
AMPLITUDE (dB)
0
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTM9004-AD: 64k Point FFT
fIN = 705.0MHz, –1dBFS
SENSE = VDD
–40
–50
–60
–70
–80
–90
–20
–25
–30
–35
–40
–45
–100
–100
–50
–110
–110
–55
–120
–120
0
10
20
30
40
FREQUENCY (MHz)
50
60
9004 G07
–60
0
10
20
30
40
FREQUENCY (MHz)
50
60
9004 G08
0
16 32 48 64 80 96 112 128 144 160
IF FREQUENCY (MHz)
9004 G09
9004p
10
LTM9004
PIN FUNCTIONS
Supply Pins
VCC1 (Pins G5, H2), VCC2 (Pins C5, C8, K5, K8): Analog
5V Supply for Mixer and First Amplifiers. The specified
operating range is 4.5V to 5.25V. The voltage on this pin
provides power for the mixer and amplifier stages only
and is internally bypassed to GND.
VCC3 (Pins C9, C12, K9, K12), VDD (Pins D14, F13,
G13, J14): Analog 3V Supply for Second Amplifiers and
ADC. The specified operating range is 2.7V to 3.6V. VDD
is internally bypassed to GND.
OVDD (Pins D17, J17): Positive Supply for the Digital
Output Drivers. The specified operating range is 0.5V to
3.6V. OVDD is internally bypassed to OGND.
GND (See Table for Pin Locations): Analog Ground.
OGND (Pins C17, K17): Digital Output Driver Ground.
Analog Inputs
RF (Pin E2): RF Input Pin. This is a single-ended 50Ω
terminated input. No external matching network is required
for the high frequency band. An external series capacitor
(and/or shunt capacitor) may be required for impedance
transformation to 50Ω in the low frequency band from
800MHz to 1.5GHz (see Figure 4). If the RF source is not
DC blocked, a series blocking capacitor should be used.
Otherwise, damage to the IC may result.
LO (Pin H3): Local Oscillator Input Pin. This is a singleended 50Ω terminated input. No external matching network
is required in the high frequency band. An external shunt
capacitor (and/or series capacitor) may be required for
impedance transformation to 50Ω for the low frequency
band from 800MHz to 1.5GHz (see Figure 6). If the LO
source is not DC blocked, a series blocking capacitor must
be used. Otherwise, damage to the IC may result.
CLKQ (Pin G14): Q-Channel ADC Clock Input. The input
sample starts on the positive edge.
CLKI (Pin F14): I-Channel ADC Clock Input. The input
sample starts on the positive edge.
I+_ADJ (Pin B1): DC Offset Adjust Pin for I-Channel, + Line.
Source or sink current through this pin to trim DC offset.
I–_ADJ (Pin C1): DC Offset Adjust Pin for I-Channel, – Line.
Source or sink current through this pin to trim DC offset.
Q+_ADJ (Pin K1): DC Offset Adjust Pin for Q-Channel, + Line.
Source or sink current through this pin to trim DC offset.
Q–_ADJ (Pin L1): DC Offset Adjust Pin for Q-Channel, – Line.
Source or sink current through this pin to trim DC offset.
Control Pins
MIXENABLE (Pin E4): Mixer Enable Pin. If MIXENABLE =
high (the input voltage is higher than 2.0V), the mixer is
enabled. If MIXENABLE = low (the input voltage is less than
1.0V), it is disabled. If the enable function is not needed,
then this pin should be tied to VCC.
AMP1ENABLE (Pins D5, L5): First Amplifier Enable Pin.
AMP1ENABLE = high or floating results in normal (active)
operating mode for the first amplifier in each channel.
AMP1ENABLE = low (a minimum of 2.1V below VCC), results
in the first amplifiers being disabled. If the enable function
is not needed, then this pin should be tied to VCC.
AMP2ENABLE (Pins C10, L10): Second Amplifier Enable
Pin. AMP2ENABLE = high or floating results in normal
(active) operating mode for the second amplifier in each
channel. AMP2ENABLE = low (a minimum of 0.45V below
VDD), results in the second amplifiers being disabled. If
the enable function is not needed, then this pin should
be tied to VDD.
ADCSHDNQ (Pin J12): Q-Channel ADC Shutdown Mode
Selection Pin. Connecting ADCSHDNQ to GND and OEQ to
GND results in normal operation with the outputs enabled.
Connecting ADCSHDNQ to GND and OEQ to VDD results
in normal operation with the outputs at high impedance.
Connecting ADCSHDNQ to VDD and OEQ to GND results in
nap mode with the outputs at high impedance. Connecting
ADCSHDNQ to VDD and OEQ to VDD results in sleep mode
with the outputs at high impedance.
ADCSHDNI (Pin D12): I-Channel ADC Shutdown Mode
Selection Pin. Connecting ADCSHDNI to GND and OEI to
GND results in normal operation with the outputs enabled.
Connecting ADCSHDNI to GND and OEI to VDD results in
normal operation with the outputs at high impedance.
Connecting ADCSHDNI to VDD and OEI to GND results in
nap mode with the outputs at high impedance. Connecting
ADCSHDNI to VDD and OEI to VDD results in sleep mode
with the outputs at high impedance.
9004p
11
LTM9004
PIN FUNCTIONS
OEQ (Pin K13): Q-Channel Output Enable Pin. Refer to
ADCSHDNQ pin function.
SENSEQ (Pin H13), SENSEI (Pin E13): ADC Reference Programming Pin. Tie to VDD for normal operation. An external
reference can be used, see ADC Reference section.
OEI (Pin C13): I-Channel Output Enable Pin. Refer to
ADCSHDNI pin function.
MODE (Pin J13): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects straight binary
output format and turns the clock duty cycle stabilizer off.
1/3 VDD selects straight binary output format and turns
the clock duty cycle stabilizer on. 2/3 VDD selects 2’s
complement output format and turns the clock duty cycle
stabilizer on. VDD selects 2’s complement output format
and turns the clock duty cycle stabilizer off.
Digital Outputs
CLKOUT (Pin E12): ADC Data Ready Clock Output. Latch
data on the falling edge of CLKOUT. CLKOUT is derived from
CLKI. Tie CLKQ to CLKI for simultaneous operation.
DI0 - DI13 (See Table for Pin Locations): I-Channel
(In-Phase) ADC Digital Outputs. DI13 is the MSB.
DQ0 - DQ13 (See Table for Pin Locations): Q-Channel
(Quadrature) ADC Digital Outputs. DQ13 is the MSB.
MUX (Pin D13): Digital Output Multiplexer Control. If MUX
= high, Q-channel comes out on DQ0 to DQ13; I-channel
comes out on DI0 to DI13. If MUX = low, the output busses
are swapped and Q-channel comes out on DI0 to DI13;
I-channel comes out on DQ0 to DQ13. To multiplex both
channels onto a single output bus, connect MUX, CLKQ
and CLKI together.
OF (Pin H12): Overflow/Underflow Output. High when an
overflow or underflow has occurred on either I-channel or
Q-channel.
Pin Configuration
A
B
C
I–_ADJ
D
E
F
G
H
J
K
L
M
Q–_ADJ
GND
GND
GND
1
GND
I+_ADJ
GND
GND
GND
GND
GND
GND
Q+_ADJ
2
GND
GND
GND
GND
RF
GND
GND
VCC1
GND
GND
3
GND
GND
GND
GND
GND
GND
GND
LO
GND
GND
GND
GND
4
GND
GND
GND
GND
MIX_EN
GND
GND
GND
GND
GND
GND
GND
5
GND
GND
VCC2
AMP1A_
EN
GND
GND
VCC1
GND
GND
VCC2
AMP1B_
EN
GND
6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
8
GND
GND
VCC2
GND
GND
GND
GND
GND
GND
VCC2
GND
GND
9
GND
GND
VCC3
GND
GND
GND
GND
GND
GND
VCC3
GND
GND
10
GND
GND
AMP2A_
EN
GND
GND
GND
GND
GND
GND
GND
AMP2B_
EN
GND
11
GND
GND
GND
GND
GND
12
GND
GND
VCC3
13
DI3
DI0
OEI
14
DI8
DI4
DI1
15
DI7
DI6
DI2
16
GND
DI9
DI5
DI10
17
GND
GND
OGND
OVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
OF
SHDNQ
VCC3
GND
GND
SENSEI
VDD
VDD
SENSEQ MODE
OEQ
DQ13
DQ10
VDD
GND
CLKI
CLKQ
GND
VDD
DQ12
DQ8
DQ6
GND
GND
GND
GND
GND
GND
DQ11
DQ4
DQ5
DI11
GND
GND
DQ1
DQ3
DQ9
DQ7
GND
DI12
DI13
DQ0
DQ2
OVDD
OGND
GND
GND
SHDNI CLKOUT
MUX
Top View of LGA Package (Looking Through Component)
9004p
12
LTM9004
BLOCK DIAGRAM
MIX
ENABLE
VCC1
VCC2
AMP1
ENABLE
VCC3
AMP2
ENABLE
CLK
MODE
ADC
OE
SHDN
VDD
OVDD
OF
RF
LPF
1ST
AMP
LPF
2ND
AMP
LPF
REFH
1.5V
REFERENCE
D13
...
OUTPUT
DRIVERS
ADC
REFL
D0
CLKOUT
GND
RANGE
SELECT
DIFF
REF
AMP
LO
ADJ
ADJ
SENSE
REF
BUFFER
9004 BD
Figure 1. Functional Block Diagram (Only One Channel is Shown)
9004p
13
LTM9004
OPERATION
DESCRIPTION
The LTM9004 is a direct conversion receiver targeting
high linearity receiver applications, such as wireless infrastructure with RF input frequencies up to 2.7GHz. It
is an integrated μModule receiver utilizing system in a
package (SiP) technology to combine a dual, high speed
14-bit A/D converter, lowpass filters, two low noise differential amplifiers per channel with fixed gain, and an I/Q
demodulator with DC offset adjustment.
The direct conversion receiver architecture offers several
advantages over the traditional superheterodyne. It eases
the requirements for RF front-end bandpass filtering, as it
is not susceptible to signals at the image frequency. The
RF bandpass filters need only attenuate strong out-of-band
signals to prevent them from overloading the front end.
Also, direct conversion eliminates the need for IF amplifiers and bandpass filters. Instead, the RF input signal is
directly converted to baseband.
Direct conversion does, however, come with its own set of
implementation issues. Since the receive LO signal is at the
same frequency as the RF signal, it can easily radiate from
the receive antenna and violate regulatory standards.
Unwanted baseband signals can also be generated by
2nd order nonlinearity of the receiver. A tone at any frequency entering the receiver will give rise to a DC offset
in the baseband circuits. The 2nd order nonlinearity of the
receiver also allows a modulated signal, even the desired
signal, to generate a pseudo-random block of energy
centered about DC.
For this reason, the LTM9004 provides for DC offset correction immediately following the I/Q demodulator stage.
Once generated, straightforward elimination of DC offset
becomes very problematic. Necessary gain in the baseband
amplifiers increases the offset because their frequency
response extends to DC.
The following sections describe in further detail the operation of each section. The μModule technology allows
the LTM9004 to be customized and this is described in the
first section. The outline of the remaining sections follows
the basic functional elements as shown in Figure 2.
VCC1
VCC2
VCC3
VDD
0VDD
1ST
AMP
RF
2ND
AMP
LPF
ADC
MIXER
DGND
LO
OFFSET ADJ
GND
9004 F02
ADC
CLK
Figure 2. Basic Functional Elements (Only Half Shown)
SEMI-CUSTOM OPTIONS
The μModule construction affords a new level of flexibility
in application-specific standard products. Standard ADC,
amplifier and RF components can be integrated regardless
of their process technology and matched with passive
components to a particular application. The LTM9004-AA,
as the first example, is configured with a dual 14-bit ADC
sampling at rates up to 125Msps. The amplifiers provide a
total voltage gain of 14dB (including the gain of the mixer).
The lowpass filter limits the bandwidth to 1.92MHz. The
RF and LO inputs of the I/Q demodulator have integrated
transformers and present 50Ω single-ended inputs. An
external DAC can be used for DC offset cancellation.
However, other options are possible through Linear
Technology’s semi-custom development program. Linear
Technology has in place a program to deliver other sample
rate, resolution, gain and filter configurations for nearly
any specified application. These semi-custom designs
are based on existing components with an appropriately
modified passive network. The final subsystem is then
tested to the exact parameters defined for the application.
The final result is a fully integrated, accurately tested and
optimized solution in the same package. For more details
on the semi-custom receiver subsystem program, contact
Linear Technology.
MIXER OPERATION
The RF signal is applied to the inputs of the RF transconductance amplifiers and is then demodulated into I/Q
baseband signals using quadrature LO signals which are
internally generated from an external LO source by precision 90° phase shifters.
9004p
14
LTM9004
OPERATION
Broadband transformers are integrated at both the RF and
LO inputs to enable single-ended RF and LO interfaces.
In the high frequency band (1.5GHz to 2.7GHz), both RF
and LO ports are internally matched to 50Ω. No external
matching components are needed. For the lower frequency
bands (800MHz to 1.5GHz), a simple network with series
and/or shunt capacitors can be used as the impedance
matching network.
CONVERTER OPERATION
DC OFFSET ADJUSTMENT
Each pipelined stage contains an ADC, a reconstruction
DAC and an interstage residue amplifier. In operation, the
ADC quantizes the input to the stage and the quantized
value is subtracted from the input by the DAC to produce a
residue. The residue is amplified and output by the residue
amplifier. Successive stages operate out of phase so that
when the odd stages are outputting their residue, the even
stages are acquiring that residue and visa versa.
Each channel includes provision for adjustment of the DC
offset voltage presented at the input of the A/D converter.
There are two adjust terminals for each channel, so that
the common mode and differential mode DC offset may
be independently trimmed. These terminals are designed
to accept a source or sink current of up to 0.3mA. If the
currents through the two terminals are not equal, then a
differential DC offset will be created. If they are equal, then
the resulting DC offset will be common mode only. As an
example, sinking 0.1mA from one terminal and 0.11mA
from the other terminal will yield a differential DC offset of
approximately 5.9mV or 48LSB. A maximum DC offset of
approximately 178mV or 1457LSB can be imposed by applying a 5V differential voltage to the adjust terminals.
AMPLIFIER OPERATION
Each channel of the LTM9004 consists of two stages of
DC-coupled, low noise and low distortion fully differential
op amps/ADC drivers. Each stage implements a 2-pole
active lowpass filter using a high speed, high performance
operational amplifier and precision passive components.
The cascade of two stages is designed to provide maximum
gain and phase flatness, along with adjacent channel and
blocker rejection. The lowpass response can be configured for different cutoff frequencies within the range of
the amplifiers. LTM9004-AA, for example, implements a
lowpass filter designed for 1.92MHz.
ADC INPUT NETWORK
The analog-to-digital converter (ADC) shown in Figure 1 is
a dual CMOS pipelined multistep converter. The converter
has six pipelined ADC stages; a sampled analog input will
result in a digitized value six cycles later (see the Timing
Diagrams section). The CLK inputs are single ended. The
ADC has two phases of operation, determined by the state
of the CLK input pins.
When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors,
inside the Input S/H shown in the Block Diagram. At the
instant that CLK transitions from low to high, the sampled
input is held. While CLK is high, the held input voltage
is buffered by the S/H amplifier which drives the first
pipelined ADC stage. The first stage acquires the output
of the S/H during this high phase of CLK. When CLK goes
back low, the first stage produces its residue which is
acquired by the second stage. At the same time, the input
S/H goes back to acquiring the analog input. When CLK
goes back high, the second stage produces its residue
which is acquired by the third stage. An identical process
is repeated for the third, fourth and fifth stages, resulting
in a fifth stage residue that is sent to the sixth stage ADC
for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
The passive network between the second amplifier output
stages and the ADC input stages provides a 1st order
topology configured for lowpass response.
9004p
15
LTM9004
APPLICATIONS INFORMATION
RF INPUT
Figure 3 shows the mixer’s RF input which consists of an
integrated transformer and high linearity transconductance amplifiers. The primary side of the transformer is
connected to the RF input pin. The secondary side of the
transformer is connected to the differential inputs of the
transconductance amplifiers. Under no circumstances
should an external DC voltage be applied to the RF input
pin. DC current flowing into the primary side of the transformer may cause damage to the integrated transformer.
A series blocking capacitor should be used to AC-couple
the RF input port to the RF signal source.
EXTERNAL
MATCHING
NETWORK FOR
LOW BAND AND
MID BAND
C11
TO I MIXER
RF
INPUT
E2
RF
C10
TO Q MIXER
E3
9004 F05
Figure 3. RF Input Interface
0
RETURN LOSS (dB)
–5
–10
–15
–20
–25
–30
100
NO
MATCHING
ELEMENTS
1.95GHz
MATCH
(2.7nH +
1.8pF)
700MHz
MATCH
(18pF +
8.2pF)
1000
FREQUENCY (MHz)
10000
9004 F04
Figure 4. RF Port Return Loss vs Frequency
The RF input port is internally matched over a wide frequency range from 1.5GHz to 2.7GHz with input return loss
typically better than 10dB. No external matching network is
needed for this frequency range. When the part is operated
at lower frequencies, however, the input return loss can be
improved with the matching network shown in Figure 3.
Shunt capacitor C10 and series capacitor C11 can be
selected for optimum input impedance matching at the
desired frequency as illustrated in Figure 4. For lower frequency band operation, the external matching component
C11 can serve as a series DC blocking capacitor.
The RF input impedance and S11 parameters (without
external matching components) are listed in Table 1.
Table 1. RF Input Impedance
FREQUENCY
(MHz)
MAGNITUDE
PHASE
R (Ω)
X (Ω)
500
0.78
–139.7
16.1
–10.7
600
0.69
–166.6
10.1
–3.8
700
0.60
163.7
14.0
3.8
800
0.52
132.6
25.8
6.9
900
0.48
102.7
41.9
3.4
1000
0.45
77.4
58.8
–4.3
1100
0.42
56.6
74.9
–11.4
1200
0.38
40.1
86.4
–12.4
1300
0.31
25.7
87.6
–7.1
1400
0.22
10.9
76.8
–1.4
1500
0.10
–14.5
60.9
0.3
1600
0.06
–132.9
45.9
–0.2
1700
0.19
–170.7
34.6
–0.4
1800
0.30
–177.7
26.8
0.2
1900
0.40
–172.1
21.8
1.1
2000
0.47
–169.4
18.7
1.9
2100
0.51
–168.6
16.7
2.2
2200
0.54
–169.3
15.4
2.3
2300
0.55
–172.0
14.7
1.7
2400
0.55
–176.0
14.4
0.9
2500
0.54
–178.7
14.9
–0.3
2600
0.52
–172.3
15.9
–1.6
2700
0.50
–164.3
17.6
–3.0
2800
0.49
–155.0
19.9
–4.3
2900
0.48
–144.7
22.9
–5.4
3000
0.48
–134.8
26.4
–6.0
LO Input Port
The mixer’s LO input interface is shown in Figure 5. The
input consists of an integrated transformer and a precision quadrature phase shifter which generates 0° and
9004p
16
LTM9004
APPLICATIONS INFORMATION
90° phase-shifted LO signals for the LO buffer amplifiers
driving the I/Q mixers. The primary side of the transformer
is connected to the LO input pin. The secondary side of
the transformer is connected to the differential inputs of
the LO quadrature generator. Under no circumstances
should an external DC voltage be applied to the input pin.
DC current flowing into the primary side of the transformer
may damage the transformer. A series blocking capacitor
should be used to AC-couple the LO input port to the LO
signal source.
EXTERNAL
MATCHING
NETWORK FOR
LOW BAND AND
MID BAND
C13
LO
INPUT
H4
H3
C12
LO QUADRATURE
GENERATOR AND
BUFFER AMPLIFIERS
LO
9004 F05
Figure 5. LO Input Interface
0
RETURN LOSS (dB)
–5
–10
–15
–20
–25
–30
100
NO MATCHING
ELEMENTS
1.95GHz MATCH
(2.7nH + 1.5pF)
700MHz MATCH
(15pF + 6.8pF)
1000
FREQUENCY (MHz)
10000
The LO input impedance and S11 parameters (without
external matching components) are listed in Table 2.
Table 2. LO Input Impedance
FREQUENCY
(MHz)
MAGNITUDE
PHASE
R (Ω)
X (Ω)
500
0.77
–143.2
14.8
–10.0
600
0.66
–172.6
10.6
–2.0
700
0.55
154.5
17.8
5.1
800
0.46
119.8
33.1
5.5
900
0.41
88.8
50.8
–0.3
1000
0.39
63.9
67.5
–7.4
1100
0.35
44.9
80.2
–10.1
1200
0.30
31.5
83.4
–7.2
1300
0.23
22.7
76.9
–3.1
1400
0.14
20.7
65.2
–0.9
1500
0.05
47.3
53.6
–0.1
1600
0.08
139.3
44.1
0.3
1700
0.17
152.3
36.9
0.9
1800
0.25
154.7
31.7
1.6
1900
0.31
157.5
27.9
2.0
2000
0.35
160.5
25.1
2.2
2100
0.38
164.9
23.1
2.0
2200
0.41
170.3
21.4
1.4
2300
0.42
177.7
20.2
0.4
2400
0.44
–173.8
19.6
–1.0
2500
0.46
–164.6
19.7
–2.6
2600
0.48
–155.7
20.2
–4.1
2700
0.51
–147.1
21.2
–5.6
2800
0.54
–139.2
22.8
–6.8
2900
0.56
–131.5
25.2
–7.6
3000
0.58
–124.9
27.9
–7.9
9004 F06
Figure 6. LO Return Loss vs Frequency
The LO input port is internally matched over a wide frequency range from 1.5GHz to 2.7GHz with input return
loss typically better than 10dB. No external matching
network is needed for this frequency range. When the part
is operated at a lower frequency, the input return loss can
be improved with the matching network shown in Figure
8. Shunt capacitor C12 and series capacitor C13 can be
selected for optimum input impedance matching at the
desired frequency as illustrated in Figure 6. For lower
frequency operation, external matching component C13
can serve as the series DC blocking capacitor.
ADC Reference
The internal voltage reference can be configured for two
pin-selectable ADC input ranges. Tying the SENSE pin to
VDD selects the default range; tying the SENSE pin to 1.5V
selects a 3dB lower range. An external reference can be
used by applying its output directly or through a resistor
divider to SENSE. It is not recommended to drive the
SENSE pin with a logic device. The SENSE pin should be
tied to the appropriate level as close to the converter as
possible. The SENSE pin is internally bypassed to ground
with a 1μF ceramic capacitor.
9004p
17
LTM9004
APPLICATIONS INFORMATION
Enable Interface
The enable voltage necessary to turn on the mixer is 2V.
To disable or turn off the mixer, this voltage should be
below 1V. If this pin is not connected, the mixer is disabled. However, it is not recommended that the pin be left
floating for normal operation.
The AMP1ENABLE and AMP2ENABLE pins are CMOS
logic inputs with 100k internal pull-up resistors. If the
pin is driven low, the amplifier powers down with Hi-Z
outputs. If the pin is left unconnected or driven high, the
part is in normal active operation. Some care should be
taken to control leakage currents at this pin to prevent
inadvertently putting it into shutdown. The turn-on and
turn-off time between the shutdown and active states are
typically less than 1μs.
is achieved with a logic low level on the SHDN pins and a
high level disables the respective functions.
It is not recommended to enable or shut down individual
components separately. These pins are separated for test
purposes.
Driving the ADC Clock Inputs
The CLK inputs can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with a
low-jitter squaring circuit before the CLK pin (Figure 7).
CLEAN
SUPPLY
4.7μF
FERRITE
BEAD
0.1μF
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting ADCSHDNx to GND results
in normal operation. Connecting ADCSHDNx to VDD and
OEx to VDD results in sleep mode, which powers down
all circuitry including the reference and the ADC typically
dissipates 1mW. When exiting sleep mode, it will take
milliseconds for the output data to become valid because
the reference capacitors have to recharge and stabilize.
Connecting ADCSHDNx to VDD and OEx to GND results
in nap mode and the ADC typically dissipates 30mW. In
nap mode, the on-chip reference circuit is kept on, so that
recovery from nap mode is faster than that from sleep
mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Channels I and Q have independent ADCSHDN pins
(ADCSHDNI, ADCSHDNQ.) I-Channel is controlled by
ADCSHDNI and OEI, and Q-Channel is controlled by
ADCSHDNQ and OEQ. The nap, sleep and output enable
modes of the two channels are completely independent,
so it is possible to have one channel operating while the
other channel is in nap or sleep mode.
Note that ADCSHDN has the opposite polarity as MIXENABLE, AMP1ENABLE and AMP2ENABLE. Normal operation
SINUSOIDAL
CLOCK
INPUT
1k
0.1μF
CLK
50Ω
1k
LTM9004
NC7SVU04
9004 F07
Figure 7. Sinusoidal Single-Ended CLK Driver
The noise performance of the ADC can depend on the clock
signal quality as much as on the analog input. Any noise
present on the CLK signal will result in additional aperture
jitter that will be RMS summed with the inherent ADC
aperture jitter. In applications where jitter is critical, such
as when digitizing high input frequencies, use as large an
amplitude as possible. Also, if the ADC is clocked with a
sinusoidal signal, filter the CLK signal to reduce wideband
noise and distortion products generated by the source.
It is recommended that CLKI and CLKQ are shorted together and driven by the same clock source. If a small
time delay is desired between when the two channels
sample the analog inputs, CLKI and CLKQ can be driven
by two different signals. If this time delay exceeds 1ns,
the performance of the part may degrade. CLKI and CLKQ
should not be driven by asynchronous signals.
9004p
18
LTM9004
APPLICATIONS INFORMATION
Figure 8 and Figure 9 show alternatives for converting a
differential clock to the single-ended CLK input. The use
of a transformer provides no incremental contribution
to phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz will
degrade the SNR compared to the transformer solution.
The nature of the received signals also has a large bearing on how much SNR degradation will be experienced.
For high crest factor signals such as WCDMA or OFDM,
where the nominal power level must be at least 6dB to
8dB below full scale, the use of these translators will have
a lesser impact.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may
be desirable in cases where lower voltage differential
signals are considered. The center tap may be bypassed
to ground through a capacitor close to the ADC if the
differential signals originate on a different plane. The
use of a capacitor at the input may result in peaking, and
depending on transmission line length may require a 10Ω
to 20Ω series resistor to act as both a lowpass filter for
high frequency noise that may be induced into the clock
line by neighboring digital signals, as well as a damping
mechanism for reflections.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the ADC is 125Msps.
The lower limit of the sample rate is determined by the
droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency
for the LTM9004 is 1Msps.
Clock Duty Cycle Stabilizer
An optional clock duty cycle stabilizer circuit ensures high
performance even if the input clock has a non 50% duty
cycle. Using the clock duty cycle stabilizer is recommended
for most applications. To use the clock duty cycle stabilizer,
the MODE pin should be connected to 1/3VDD or 2/3VDD
using external resistors.
This circuit uses the rising edge of the CLK pin to sample
the analog input. The falling edge of CLK is ignored and
the internal falling edge is generated by a phase-locked
loop. The input clock duty cycle can vary from 40% to
60% and the clock duty cycle stabilizer will maintain a
constant 50% internal duty cycle. If the clock is turned off
for a long period of time, the duty cycle stabilizer circuit
will require a hundred clock cycles for the PLL to lock
onto the input clock.
CLEAN
SUPPLY
4.7μF
ETC1-1T
FERRITE
BEAD
0.1μF
CLK
CLK
LTM9004
5pF-30pF
DIFFERENTIAL
CLOCK
INPUT
LTM9004
9004 F09
0.1μF
100Ω
FERRITE
BEAD
VCM
9004 F08
Figure 9. LVDS or PECL CLK Drive Using a Transformer
Figure 8. CLK Driver Using an LVDS or PECL to
CMOS Converter
9004p
19
LTM9004
APPLICATIONS INFORMATION
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50% (±5%) duty cycle.
LTM9004
OVDD
VDD
VDD
0.5V
TO 3.6V
0.1μF
OVDD
DATA
FROM
LATCH
DIGITAL OUTPUTS
Table 3 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit. Note that
OF is high when an overflow or underflow has occurred
on either channel A or channel B.
PREDRIVER
LOGIC
OF
TYPICAL
DATA
OUTPUT
OE
OGND
9004 F10
Figure 10. Digital Output Buffer
Table 3. Output Codes vs Input Voltage
INPUT
43Ω
D13 – D0
(OFFSET BINARY)
D13 – D0
(2’S COMPLEMENT)
Overvoltage
1
11 1111 1111 1111
01 1111 1111 1111
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Maximum
0
0
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1110
Data Format
0
0
0
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
Minimum
0
0
00 0000 0000 0001
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
Undervoltage
1
00 0000 0000 0000
10 0000 0000 0000
Digital Output Modes
Figure 10 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping resistors.
As with all high speed/high resolution converters the digital output loading can affect the performance. The digital
outputs of the ADC should drive a minimal capacitive load
to avoid possible interaction between the digital outputs
and sensitive input circuitry. For full speed operation, the
capacitive load should be kept under 10pF.
Using the MODE pin, the ADC parallel digital output can be
selected for offset binary or 2’s complement format. Note
that MODE controls both I and Q channels. Connecting
MODE to GND or 1/3 VDD selects straight binary output
format. Connecting MODE to 2/3 VDD or VDD selects 2’s
complement output format. An external resistive divider
can be used to set the 1/3 VDD or 2/3 VDD logic values.
Table 4 shows the logic states for the MODE pin.
Table 4. MODE Pin Function
MODE PIN
OUTPUT FORMAT
CLOCK DUTY CYCLE
STABILIZER
0
Straight Binary
Off
1/3VDD
Straight Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overflow Bit
When OF outputs a logic high the converter is either overranged or underranged on I-channel or Q-channel. Note
that both channels share a common OF pin. OF is disabled
when I-channel is in sleep or nap mode.
9004p
20
LTM9004
APPLICATIONS INFORMATION
Output Clock
Design Example – UMTS Uplink FDD System
The ADC has a delayed version of the CLKQ input available
as a digital output, CLKOUT. The falling edge of the CLKOUT
pin can be used to latch the digital output data. CLKOUT
is disabled when channel B is in sleep or nap mode.
The LTM9004 can be used with an RF front end to build a
complete UMTS band uplink receiver. An RF front end will
consist of a diplexer, along with one or more LNAs and
bandpass filters. Here is an example of typical performance
for such a frontend:
Output Driver Power
Rx frequency range:
1920 to 1980 MHz
RF gain:
23.5dB maximum
AGC range:
20dB
Noise figure:
1.6dB
IIP2:
50dBm
IIP3:
0dBm
OVDD can be powered with any voltage from 500mV up to
the VDD of the part. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The
logic outputs will swing between OGND and OVDD.
P1dB:
–9.5dBm
Rejection at 20MHz:
2dB
Rejection at Tx band:
96dB
Output Enable
Minimum performance of the receiver is detailed in the
3GPP TS25.104 V7.4.0 specification. We will use the
medium area basestation in operating band I for this
example.
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same supply that powers the logic being driven.
For example, if the converter drives a DSP powered by a
1.8V supply, then OVDD should be tied to that same 1.8V
supply.
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The
data access and bus relinquish times are too slow to
allow the outputs to be enabled and disabled during full
speed operation. The output Hi-Z state is intended for use
during long periods of inactivity. Channels I and Q have
independent output enable pins (OEI, OEQ.)
Digital Output Multiplexer
The digital outputs of the ADC can be multiplexed onto a
single data bus. The MUX pin is a digital input that swaps
the two data busses. If MUX is high, I-channel comes out
on DI0 to DI13; Q-channel comes out on DQ0 to DQ13. If
MUX is low, the output busses are swapped and I-channel
comes out on DQ0 to DQ13; Q-channel comes out on DI0
to DI13. To multiplex both channels onto a single output
bus, connect MUX, CLKI and CLKQ together (see the Timing Diagrams for the multiplexed mode.) The multiplexed
data is available on either data bus – the unused data bus
can be disabled with its OE pin.
Sensitivity is a primary consideration for the receiver; the
requirement is ≤–121dBm, for an input SNR of –19.8dB/5
MHz. That means the effective noise floor at the receiver
input must be ≤–169.2dBm/Hz. Given the effective noise
contribution of the RF frontend, the maximum allowable
noise due to the LTM9004 must then be –148.5dBm/Hz.
Typical input noise for the LTM9004 is –150dBm/Hz,
which translates to a calculated system sensitivity of
–121.7dBm.
To operate in the presence of co-channel interfering signals, the receiver must have sufficient dynamic range
at maximum sensitivity. The UMTS specification calls
for a maximum co-channel interferer of –73dBm. At the
LTM9004 input this amounts to –49.5dBm.
With the RF AGC set for minimum gain, the receiver must
be able to demodulate the largest anticipated desired signal
from the handset. Assuming a handset average power of
9004p
21
LTM9004
APPLICATIONS INFORMATION
+28dBm, the minimum path loss called out in the specification is 53dB. The maximum signal level is then –25dBm
at the receiver input, or –21.5dBm at the LTM9004 input.
This requirement ultimately sets the maximum signal the
LTM9004 must accommodate at or below –1dBFS.
There are several blocker signals detailed in the UMTS
system specification. Only a specified amount of desensitization is allowed in the presence of these signals. The
first of these is an adjacent channel 5MHz away, at a level
of –52dBm. The signal reaching the LTM9004 input will
be –28.5dBm.
The receiver must also contend with a –40dBm interfering channel ≥10MHz away. The RF frontend will offer no
rejection of this channel, so it amounts to –16.5dBm at
the LTM9004 input at an offset of ≥10MHz.
Out of band blockers must also be accommodated, but
these are at the same level as the inband blockers which
have already been addressed.
In all of these cases, the typical input level for –1dBFS
of the LTM9004 is well above the maximum anticipated
signal levels. Note that the crest factor for the modulated
channels will be on the order of 10dB to 12dB, so the
largest of these will reach a peak power of approximately
–5dBm at the module input.
The largest blocking signal is the –15dBm CW tone ≥ 20MHz
beyond the receive band edges. The RF frontend will offer only 2dB rejection of this tone, so it will appear at the
input of the LTM9004 at +6.5dBm. Here again, a signal
at this level must not desensitize the baseband module.
The input P1dB of the LTM9004 is +11.2dBm, which will
accommodate this signal.
Another source of undesired signal power is leakage from
the transmitter. Since this is an FDD application, the receiver described herein will be coupled with a transmitter
operating simultaneously. The transmitter output level is
assumed to be ≤+38dBm, with a transmit to receive isolation of 96dB. Leakage appearing at the LTM9004 input is
then –34.5dBm, offset from the receive signal by at least
130MHz. As we have discussed above, this level of signal
will not compress the module.
One challenge of direct conversion architectures is 2nd
order linearity. Insufficient 2nd order linearity will allow
any signal, wanted or unwanted, to create DC offset or
pseudo-random noise at baseband. The blocking signals
detailed above will then degrade sensitivity if this pseudorandom noise approaches the noise level of the receiver.
The system specification allows for sensitivity degradation in the presence of these blockers in each case. Per
the system specification, the –40dBm blocking channel
may degrade sensitivity to –115dBm. This is equivalent
to increasing the effective input noise of the receiver to
–163.2dBm/Hz. The allowable 2nd order distortion referred
to the LTM9004 input is then –139.7dBm/Hz, with an input
signal level of –16.5dBm applied. The 2nd order distortion
produced in the LTM9004 will be much less than this, and
resulting predicted sensitivity will be –116.9dBm.
The –15dBm CW blocker will also give rise to a 2nd order
product; in this case the product is a DC offset. DC offset
is undesirable, as it reduces the maximum signal the A/D
converter can process. The one sure way to alleviate the
effects of DC offset is to ensure the 2nd order linearity of
the baseband module is high enough. Specified DC offset
due to this signal is 11mV.
Note that the transmitter leakage is not included in the
system specification, so the sensitivity degradation due
to this signal must be held to a minimum. The 2nd order
distortion generated in the LTM9004 is such that the loss
of sensitivity will be <0.1dB.
There is only one requirement for 3rd order linearity in
the specification. In the presence of two interferers, the
sensitivity must not degrade below –115dBm. The interferers are a CW tone and a WCDMA channel at –48dBm
each. These will appear at the LTM9004 input at –24.5dBm
each. Their frequencies are such that they are 10MHz and
20MHz away from the desired channel, so the 3rd order
intermodulation product falls at baseband. Here again, this
product appears as pseudo-random noise and thus will
reduce signal to noise ratio. For a sensitivity of –115dBm,
the allowable 3rd order distortion referred to the LTM9004
input is then –139.7dBm/Hz. The 3rd order distortion
produced in the LTM9004 will be much less than this, and
the predicted sensitivity degradation is <0.1dB.
9004p
22
LTM9004
APPLICATIONS INFORMATION
Supply Sequencing
The VCC pins provide the supply to the mixer and all amplifiers and the VDD pins provide the supply to the ADC. The
mixer, amplifiers and ADC are separate integrated circuits
within the LTM9004; however, there are no supply sequencing considerations beyond standard practice.
Grounding and Bypassing
The LTM9004 requires a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTM9004 has been optimized for a flowthrough layout so
that the interaction between inputs and digital outputs is
minimized. A continuous row of ground pads facilitate a
layout that ensures that digital and analog signal lines are
separated as much as possible.
• Use large PCB copper areas for ground. This helps to
dissipate heat in the package through the board and
also helps to shield sensitive on-board analog signals.
Common ground (GND) and output ground (OGND)
are electrically isolated on the LTM9004, but can be
connected on the PCB underneath the part to provide
a common return path.
• Use multiple ground vias. Using as many vias as possible helps to improve the thermal performance of the
board and creates necessary barriers separating analog
and digital traces on the board at high frequencies.
• Separate analog and digital traces as much as possible, using vias to create high frequency barriers.
This will reduce digital feedback that can reduce the
signal-to-noise ratio (SNR) and dynamic range of the
LTM9004.
The LTM9004 is internally bypassed with the ADC (VDD),
mixer and amplifier (VCC) supplies returning to a common
ground (GND). The digital output supply (OVDD) is returned
to OGND. A 0.1μF bypass capacitor should be placed at
each of the two OVDD pins. Additional bypass capacitance
is optional and may be required if power supply noise is
significant.
Figures 11 through 14 give a good example of the recommended layout.
Heat Transfer
The LTM9004 employs gold-finished pads for use with
Pb-based or tin-based solder paste. It is inherently Pb-free
and complies with the JEDEC (e4) standard. The materials declaration is available online at http://www.linear.
com/leadfree/mat_dec.jsp.
Most of the heat generated by the LTM9004 is transferred
through the bottom-side ground pads. For good electrical
and thermal performance, it is critical that all ground pins
are connected to a ground plane of sufficient area with as
many vias as possible.
The quality of the paste print is an important factor in
producing high yield assemblies. It is recommended to
use a type 3 or 4 printing no-clean solder paste. The solder
stencil design should follow the guidelines outlined in
Application Note 100.
Recommended Layout
The high integration of the LTM9004 makes the PCB
board layout simple. However, to optimize its electrical
and thermal performance, some layout considerations
are still necessary.
9004p
23
LTM9004
APPLICATIONS INFORMATION
Figure 11. Layer 1
Figure 12. Layer 2
9004p
24
LTM9004
APPLICATIONS INFORMATION
Figure 13. Layer 3
Figure 14. Layer 4
9004p
25
LTM9004
TYPICAL APPLICATIONS
(Reserve this page for graphics to come.)
9004p
26
LTM9004
PACKAGE DESCRIPTION
LGA Package
204-Lead (22mm × 15mm × 2.82mm)
(Reference LTC DWG # 05-08-1822 Rev Ø)
aaa Z
15
BSC
X
2.670 – 2.970
Y
M
L
K
J
H
G
F
E
D
C
B
Ø(0.635)
PAD 1
A
1
0.12 – 0.28
2
PAD 1
CORNER
3
4
4
5
6
7
8
22
BSC
20.32
BSC
9
10
MOLD
CAP
SUBSTRATE
11
12
0.27 – 0.37
2.40 – 2.60
13
1.27
BSC
Z
bbb Z
DETAIL B
14
15
16
17
aaa Z
PACKAGE TOP VIEW
PADS
SEE NOTES
13.97
BSC
3
PACKAGE BOTTOM VIEW
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
DETAIL B
DETAIL A
0.635 ±0.025 SQ. 204x
eee S X Y
10.1600
8.8900
7.6200
DETAIL A
6.3500
5.0800
3.8100
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2.5400
2. ALL DIMENSIONS ARE IN MILLIMETERS
1.2700
0.0000
1.2700
3
LAND DESIGNATION PER JESD MO-222
4
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
2.5400
5. PRIMARY DATUM -Z- IS SEATING PLANE
3.8100
6. THE TOTAL NUMBER OF PADS: 204
LTMXXXXXX
μModule
COMPONENT
PIN “A1”
TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
5.0800
SYMBOL TOLERANCE
aaa
0.15
bbb
0.10
eee
0.05
6.3500
7.6200
LGA 204 0108 REV Ø
8.8900
10.1600
SUGGESTED PCB LAYOUT
TOP VIEW
9004p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTM9004
TYPICAL APPLICATION
VCC = 5V
VCC1 = 5V
0.1μF
LTM9004
~CS/LD
SDI
SCK
SDO
0°
RF
90°
REF
LTC2634-12 (OR LTC2654-16)
LO
I+_ADJ
I–_ADJ
Q+_ADJ
Q–_ADJ
0.1μF
9004 TA02
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9004p
28 Linear Technology Corporation
LT 1010 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010
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