MT7687F Datasheet

MT7687F Datasheet
MT7687F DATASHEET
Version:
1.03
Release date: 2016-12-08
© 2015 - 2017 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s). MediaTek cannot grant you
permission for any material that is owned by third parties. You may only use or reproduce this document if you have agreed to and been
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CLAIMS RELATING TO OR ARISING OUT OF THIS DOCUMENT OR ANY USE OR INABILITY TO USE THEREOF. Specifications contained herein are
subject to change without notice.
MT7687F
Internet-of-Things Wireless Connectivity
Document Revision History
Revision
Date
Description
1.00
2016-01-12
Initial version.
1.01
2016-05-10
1. Modify section 1.2.3 for adding SIP flash information.
2. Modify table 4.2 for wider temperature specification.
3. Modify table 5.8 for wider temperature specification.
1.02
2016-11-04
Add the power performance summary.
1.03
2016-12-08
1. Add SPI Slave description.
2. Update Auxilliary ADC specifications of Table 4-6
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MT7687F
Internet-of-Things Wireless Connectivity
Table of Contents
Document Revision History ............................................................................................................. 2
Table of Contents ............................................................................................................................ 3
List of Tables ................................................................................................................................... 6
List of Figures .................................................................................................................................. 7
1
System Overview ................................................................................................................... 9
1.1 General Description .............................................................................................................. 9
1.2
2
Features ................................................................................................................................ 9
1.2.1
Technology and package ...................................................................................... 9
1.2.2
Power management and clock source ................................................................. 9
1.2.3
Platform ............................................................................................................... 9
1.2.4
WLAN ................................................................................................................. 10
1.2.5
Miscellaneous .................................................................................................... 10
1.3
Applications ........................................................................................................................ 10
1.4
Block Diagram ..................................................................................................................... 10
Functional Description ......................................................................................................... 12
2.1 Overview............................................................................................................................. 12
2.2
2.3
2.4
Power Management Unit ................................................................................................... 12
2.2.1
PMU Architecture .............................................................................................. 12
2.2.2
Chip Power Plan ................................................................................................. 13
2.2.3
Digital Power Domain and Power States ........................................................... 13
Clock and Reset Generation ............................................................................................... 16
2.3.1
Clock ................................................................................................................... 16
2.3.2
Reset................................................................................................................... 20
Application Processor Subsystem ...................................................................................... 20
2.4.1
CPU ..................................................................................................................... 20
2.4.2
Cache and Tightly Coupled Memory .................................................................. 21
2.4.3
Bus Fabric ........................................................................................................... 22
2.4.4
Serial Flash Controller ........................................................................................ 23
2.4.5
DMA ................................................................................................................... 23
2.4.6
General Purpose Timer ...................................................................................... 25
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MT7687F
Internet-of-Things Wireless Connectivity
2.5
2.6
2.7
2.8
3
2.4.7
Watchdog Timer................................................................................................. 26
2.4.8
Efuse ................................................................................................................... 27
2.4.9
Interrupt Controller............................................................................................ 27
2.4.10
Power-on Sequence ........................................................................................... 30
2.4.11
Memory Map ..................................................................................................... 33
2.4.12
SYSRAM_CM4..................................................................................................... 38
2.4.13
Crypto engine ..................................................................................................... 38
Peripherals.......................................................................................................................... 38
2.5.1
GPIO Interface .................................................................................................... 38
2.5.2
UART Interface ................................................................................................... 42
2.5.3
I2C Serial Interface ............................................................................................. 43
2.5.4
Auxiliary ADC function ....................................................................................... 43
2.5.5
SPI Master Interface ........................................................................................... 44
2.5.6
SPI Slave Interface .............................................................................................. 45
2.5.7
I2S Interface ....................................................................................................... 46
2.5.8
Pulse Width Modulation (PWM) ........................................................................ 48
2.5.9
IrDA .................................................................................................................... 49
Radio MCU Subsystem ....................................................................................................... 49
2.6.1
CPU ..................................................................................................................... 49
2.6.2
RAM/ROM .......................................................................................................... 49
2.6.3
Memory map...................................................................................................... 49
2.6.4
N9 Bus Fabric...................................................................................................... 52
2.6.5
CIRQ.................................................................................................................... 53
Wi-Fi Subsystem ................................................................................................................. 55
2.7.1
Wi-Fi MAC .......................................................................................................... 55
2.7.2
WLAN Baseband ................................................................................................. 55
2.7.3
WLAN RF............................................................................................................. 55
RTC ...................................................................................................................................... 55
Radio Characteristics ........................................................................................................... 57
3.1 Wi-Fi Radio Characteristics ................................................................................................. 57
3.1.1
Wi-Fi RF Block Diagram ...................................................................................... 57
3.1.2
Wi-Fi 2.4GHz Band RF Receiver Specifications................................................... 57
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MT7687F
Internet-of-Things Wireless Connectivity
3.1.3
4
5
Wi-Fi 2.4GHz Band RF Transmitter Specifications ............................................. 59
Electrical Characteristics ...................................................................................................... 61
4.1 Absolute Maximum Rating ................................................................................................. 61
4.2
Recommended Operating Range ....................................................................................... 61
4.3
DC Characteristics............................................................................................................... 61
4.4
XTAL Oscillator.................................................................................................................... 62
4.5
PMU Characteristics ........................................................................................................... 62
4.6
Auxiliary ADC Characteristics ............................................................................................. 63
4.7
Thermal Characteristics ...................................................................................................... 65
4.8
Power Performance Summary ........................................................................................... 65
Package Specifications ......................................................................................................... 67
5.1 Pin Layout ........................................................................................................................... 67
5.2
Pin Description ................................................................................................................... 68
5.3
Pin Multiplexing .................................................................................................................. 70
5.4
Bootstrap ............................................................................................................................ 75
5.5
Package information .......................................................................................................... 77
5.6
Ordering information ......................................................................................................... 77
5.7
Top Marking ....................................................................................................................... 78
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MT7687F
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List of Tables
Table 2-1. MTCMOS Power Domain ...................................................................................................... 13
Table 2-2. Power States for CM4 Subsystem ......................................................................................... 14
Table 2-3. Power States for N9 Subsystem ............................................................................................ 15
Table 2-4. Power State Transition Scenarios for N9 .............................................................................. 16
Table 2-5. Power State Transition Scenarios for CM4 ........................................................................... 16
Table 2-6. Cortex-M4 Clock Rate ........................................................................................................... 17
Table 2-7. N9 Clock Rate ....................................................................................................................... 18
Table 2-8. Peripheral Clock Rate............................................................................................................ 18
Table 2-9. TCM and Cache Configuration .............................................................................................. 21
Table 2-10. Flash Controller Support Read Mode ................................................................................. 23
Table 2-11. DMA Use for Hardware Functions ...................................................................................... 24
Table 2-12. General Purpose Timer Types............................................................................................. 26
Table 2-13. CM4 NVIC Interrupt Source ................................................................................................ 27
Table 2-14. CM4 External Interrupt De-Bounce Period......................................................................... 29
Table 2-15. CM4 Memory Map ............................................................................................................. 34
Table 2-16. Functional Description of AGPIO ........................................................................................ 41
Table 2-17. SPI Pin Description.............................................................................................................. 45
Table 2-18. I2S Pin Description.............................................................................................................. 47
Table 2-19. I2S Slave Mode ................................................................................................................... 47
Table 2-20. PWM Modes ....................................................................................................................... 48
Table 2-21. N9 Memory Map ................................................................................................................ 49
Table 3-1. 2.4GHz RF Receiver Specification ......................................................................................... 57
Table 3-2. 2.4GHz RF Transmitter Specifications ................................................................................... 59
Table 4-1 Absolute Maximum Rating .................................................................................................... 61
Table 4-2. Recommended Operating Range ......................................................................................... 61
Table 4-3. DC Characteristics ................................................................................................................. 61
Table 4-4. XTAL Oscillator Requirements .............................................................................................. 62
Table 4-5. PMU Electrical Characteristics .............................................................................................. 62
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MT7687F
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Table 4-6. Auxiliary ADC Specifications ................................................................................................ 63
Table 4-7. Thermal Characteristics ........................................................................................................ 65
Table 4-8. Current consumption in different scenarios ........................................................................ 65
Table 5-1. Pin Map ................................................................................................................................ 67
Table 5-2. Pin Descriptions .................................................................................................................... 68
Table 5-3. Pin Multiplexing .................................................................................................................... 70
Table 5-4. Bootstrap Option– Flash Access Mode................................................................................. 75
Table 5-5. Bootstrap Option – XTAL Clock Mode .................................................................................. 76
Table 5-6. Bootstrap Option – 32KHz Clock Mode ................................................................................ 76
Table 5-7. Bootstrap Option — Chip Mode ........................................................................................... 76
Table 5-8. Ordering Information ........................................................................................................... 77
List of Figures
Figure 1-1. System-on-Chip Block Diagram ........................................................................................... 11
Figure 2-1. Chip Power Block Diagram .................................................................................................. 12
Figure 2-2. MT7687F Power State ......................................................................................................... 14
Figure 2-3. Clock Generation Block Diagram......................................................................................... 17
Figure 2-4. Clock Domains in N9 and CM4 Peripherals ......................................................................... 19
Figure 2-5. Reset Structure ................................................................................................................... 20
Figure 2-6. CM4 Subsystem – Bus Fabric .............................................................................................. 22
Figure 2-7. Virtual FIFO Concept ........................................................................................................... 24
Figure 2-8. PMU Power-on Sequence ................................................................................................... 30
Figure 2-9. WDT Structure .................................................................................................................... 32
Figure 2-10. Sleep/Wakeup Sequence ................................................................................................. 32
Figure 2-11. AGPIO/GPIO Block Diagram (Left: AGPIO; Right: GPIO).................................................... 39
Figure 2-12. AGPIO Configured as Output Multiplexing ...................................................................... 40
Figure 2-13. AGPIO Configured as Input Multiplexing .......................................................................... 41
Figure 2-14. AGPIO Configured as Input, Output, or Analog Mode ...................................................... 42
Figure 2-15. GPIO Configured as Open Drain Mode ............................................................................. 42
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MT7687F
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Figure 2-16. Auxiliary ADC Block Diagram (Analog Part) ...................................................................... 43
Figure 2-17. Auxiliary ADC Block Diagram ............................................................................................ 44
Figure 2-18. Auxiliary ADC Clock Timing Diagram ................................................................................. 44
Figure 2-19. SPI Timing Diagram ........................................................................................................... 45
Figure 2-20. SPI Slave Block Diagram .................................................................................................... 46
Figure 2-21. I2S Signal Waveform ......................................................................................................... 48
Figure 2-22. N9 Bus Fabric .................................................................................................................... 52
Figure 2-23. N9 interrupt controller...................................................................................................... 53
Figure 3-1. 2.4GHz RF Block Diagram ................................................................................................... 57
Figure 5-1. Package Outline Drawing .................................................................................................... 77
Figure 5-2. Top Marking ........................................................................................................................ 78
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MT7687F
Internet-of-Things Wireless Connectivity
1
1.1
System Overview
General Description
MT7687F is a highly integrated single chip which features an application processor, a low power 1x1
11n single-band Wi-Fi subsystem, and a Power Management Unit. The application processor
subsystem contains an ARM Cortex-M4 with floating point MCU. It also includes many peripherals,
including UART, I2C, SPI, I2S, PWM, IrDA, and auxiliary ADC. It also includes embedded SRAM/ROM
and a 2MB serial flash in package .
The Wi-Fi subsystem contains the 802.11b/g/n radio, baseband, and MAC that are designed to meet
both the low power and high throughput application. It also contains a 32-bit RISC CPU that could
fully offload the application processor.
1.2
Features
1.2.1
Technology and package

1.2.2
Power management and clock source


1.2.3
8mm x 8mm 68-pin QFN package.
Integrate high efficiency power management unit with single 3.3V power supply
input
40/26/52MHz source crystal clock support with low power operation in idle mode
Platform



ARM Cortex-M4 MCU with FPU with up to 192MHz clock speed
Embedded 352KB SRAM and 64KB boot ROM
2MB Quad Peripheral Interface (QPI) mode SIP serial Flash. Can also suppport
external serial flash up to 16MB












Supports eXecute In Place (XIP) on flash
32KB cache in XIP mode
Hardware crypto engines including AES, DES/3DES, SHA2 for network security
28 General Purpose IOs multiplexed with other interfaces
Two UART interfaces with hardware flow control and one UART for debug, all
multiplexed with GPIO
One SPI master interface multiplexed with GPIO
One SPI slave interface multiplexed with GPIO
Two I2C master interface multiplexed with GPIO
One I2S interface multiplexed with GPIO
Four channel 12-bit ADC multiplexed with GPIO
28 PWM multiplexed with GPIO
25 channels DMA
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MT7687F
Internet-of-Things Wireless Connectivity

1.2.4
WLAN













1.2.5
Dedicated high-performance 32-bit RISC CPU N9 up to 160MHz clock speed
IEEE 802.11 b/g/n compliant
Supports 20MHz, 40MHz bandwidth in 2.4GHz band
Dual-band 1T1R mode with data rate up to 150Mbps
Supports STBC, LDPC
Greenfield, mixed mode, legacy modes support
IEEE 802.11e support
Security support for WFA WPA/WPA2 personal, WPS2.0
Supports 802.11w protected managed frames
QoS support of WFA WMM
Integrated LNA, PA, and T/R switch
Optional external LNA and PA support.
RX diversity support with additional RX input
Miscellaneous

1.3
Low power RTC mode with 32KHz crystal support
Integrates 4Kbit efuse to store device specific information and RF calibration data.
Applications
MT7687F is designed for Internet-of-Things based on the Mediatek’s low power technology and WiFi design.
1.4
Block Diagram
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SPI flash
UART x 1
EFUSE
(4Kb)
ILM/DLM
SRAM/ROM
SPI Flash
controller
Clock
generation
25 channel
Generic DMA
PMU
TCM / Cache
(96KB)
IrDA
40/26/52MHz XTAL
N9 CPU
SYSRAM
N9 subsystem
Wi-Fi RF
CM4 SYSRAM
(256KB)
ARM Cortex
M4F
UART x 2
UART x 2
Debug
UART x 2
GPIO/PWM x 28
Wi-Fi singleband RF
Crypto Engine
Wi-Fi baseband
Wi-Fi MAC
Wi-Fi PSE
UART x 2
I2C x 2
Watch Dog
Timer
4 channel
Auxiliary ADC
General
Purpose Timer
SPI
RTC
I2S
M4 subsystem
32KHz XTAL
Figure 1-1. System-on-Chip Block Diagram
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MT7687F
Internet-of-Things Wireless Connectivity
2
Functional Description
2.1
Overview
2.2
Power Management Unit
A single regulated 3.3V power supply is required for the MT7687F. It could be from DC-DC converter
to convert higher voltage supply to 3.3V or boost from a lower voltage supply to 3.3V.
The Power Management Unit (PMU) contains Under-Voltage Lockout (UVLO) circuit, several Low
Drop-out Regulators (LDOs), a highly efficient buck converter, and a reference band-gap circuit. The
circuits are optimized for low quiescent current, low drop-out voltage, efficient line/load regulation,
high ripple rejection, and low output noise.
AVDD45_BUCK
AVDD45_MISC
1.6V
LXBK
BUCK/SLDOH
(3.3V)
3.3V
1.15V
AVDD16_CLDO
CLDO/SLDOL
(1.6V)
AVDD12_VCORE
DVDD11
Digital core
(1.15V)
RF(3.3V)
AVDD33_WF0_A_TX
AVDD33_WF0_A_PA
AVDD33_WF0_G_TX
AVDD33_WF0_G_PA
DVDDIO
ALDO
(3.3V)
AVDD16_WF0_AFE
AVDD16_XO
IO (3.3V)
AVDD25_ALDO_OUT
RF LDO/RF
core (1.6V)
2.5V
VSS
VSS
ELDO
(3.3V to 2.5V)
AVSS45_BUCK
VSS
PMU_DIO33_OUT
3.3V
AVDD25_AUXADC
ADC
(2.5V)
AVSS25_AUXADC
Figure 2-1. Chip Power Block Diagram
2.2.1
PMU Architecture
The PMU integrates 5 LDOs and one buck converter.
The four LDOs are CLDO, ALDO, high-voltage SLDO (SLDO-H) and low-voltage SLDO (SLDO-L). SLDO
stands for sleep mode LDO, and CLDO stands for digital core LDO. The buck converter converts
1.6~1.8V output to other subsystems in MT7687F. It can be operated in PFM mode or PWM mode.
Through an external on-board LC filter (2.2uH inductor and 10uF cap), it outputs a low ripple
1.6~1.8V to Wi-Fi RF system, and CLDO. CLDO is under BUCK domain, and then it outputs 1.15V for
whole chip digital logics used. ALDO is also from 3.3V chip supply input and generates 2.5V for the
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MT7687F
Internet-of-Things Wireless Connectivity
auxiliary ADC. The two SLDOs have 1.8V and 0.85V output voltage respectively. They are used to
keep BUCK and CLDO output voltage while MT7687F is in sleep mode to reduce current consumption.
Once MT7687F goes into deep sleep mode, BUCK, ALDO, and CLDO can be shut down. BUCK output
voltage will be kept by SLDO-H, and CLDO output will be kept by SLDO-L.
PMU also integrated the ELDO (Efuse LDO). It provides 2.5V output voltage to the internal Efuse
macro in programming mode.
2.2.2
Chip Power Plan
The 3.3V power source is directly supplied to the switching regulator, digital I/Os, and RF-related
circuit. It is converted to 2.5V by the LDO for ADC analog circuit. It is converted to 1.6V by the buck
converter for low voltage circuits. The built-in digital LDOs and RF LDOs converts 1.6V to 1.15V for
digital, RF, and BBPLL core circuits.
2.2.3
Digital Power Domain and Power States
The digital circuit is separated into five power domains. They are TOP_AON, TOP_OFF(N9), WF_OFF
and CM4_SYS. Except TOP_AON, each power domain can be turned on and off individually.
Table 2-1. MTCMOS Power Domain
Domain
Description
Circuit Included
OFF Condition
TOP_AON
Always-on power domain,
It includes:
N/A
which keeps the minimum
circuit powered to wake up
from the sleep mode upon
receiving a wake-up event.
Chip level configuration
register.
Sleep mode controller;
External interrupt controller;
Part of the Wi-Fi MAC that
handles the beacon filtering.
Sustain and backup memory
that stores the RAM code
and the register values that
need to be kept during sleep
mode.
TOP_OFF(N9)
The power domain can be
The whole N9 subsystem, N9
N9 is in sleep mode
power gated in Wi-Fi power
peripherals, and part of the
and no DMA functions
save mode.
Wi-Fi MAC circuit are
are enabled.
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Internet-of-Things Wireless Connectivity
Domain
Description
Circuit Included
OFF Condition
included.
WF_OFF
The power domain can be
The whole Wi-Fi baseband
Wi-Fi is disabled.
power gated when Wi-Fi is
and part of the MAC
N9 is in standby mode
not used and in Wi-Fi power
subsystem are included.
or in sleep mode.
The power domain is not
The whole Cortex-M4
N/A
powered gated when
subsystem and Cortex-M4
Cortex-M4 is used.
peripherals are included.
save mode.
CM4_OFF
The MT7687F power state diagram is illustrated below. There are two sleep mode controllers,
controlled by N9 and CM4, respectively.
The N9 power state and CM4 power state operates independently. When both enter the sleep mode,
the XTAL and PMU can be changed to the low power mode to further lower the current consumption.
Wi-Fi ON
PLL clock
XTAL 26MHz
CM4 sleep
Enter sleep mode
Enter sleep mode
CM4 standby
Wake-up from sleep timer expired or interrupt
PLL Clock
XTAL 26MHz
N9 sleep
XTAL 32KHz
XTAL 32KHz
PMU sleep
N9 standby
Wake-up from sleep timer expired or interrupt
N9 active
CM4 active
XTAL/PMU in low
power mode
When both CM4 and N9
are in sleep mode, XTAL
and PMU is changed
to low power mode.
MCU idle
Wi-Fi ON
PLL clock
PMU sleep
XTAL/PMU in low
power mode
Figure 2-2. MT7687F Power State
Table 2-2. Power States for CM4 Subsystem
MCU mode
CM4 active
Description
MCU executing code at PLL clock
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MCU mode
Description
CM4
MCU subsystem clocks are gated off and the state of the entire
standby
subsystem is retained. PLL is off.
CM4 sleep
MCU subsystem clocks are gated off and the state of the entire
subsystem is retained. Only 32KHz clock from XTAL is active. MCU
is configured to wake up on the expiry of the internal timer and
external wake-up events.
PMU sleep
CM4_OFF is power gated. XTAL and PMU operate in low power
mode. MCU is configured to wake up on the expiry of the internal
timer and external wake-up events.
Table 2-3. Power States for N9 Subsystem
MCU mode
Description
N9 active
MCU executing code at PLL clock.
MCU idle
MCU clock is gated off, while MCU subsystem clocks are on to
maintain the operation of Wi-Fi function, like listening to beacon.
PLL is on.
N9 standby
MCU subsystem clocks are gated off and the state of the entire
subsystem is retained. PLL is off.
N9 sleep
MCU subsystem clocks are gated off and the state of the entire
subsystem is retained. Only 32KHz clock from XTAL is active. MCU
is configured to wake up on the expiry of the internal timer,
external wake-up events, or the wake-up events from Wi-Fi radio.
PMU sleep
TOP_OFF (N9) and WF_OFF are power gated. XTAL and PMU
operate in low power mode. The state information is retained in
back-up buffer (sleep-mode memory) and can be restored when
wake-up. MCU is configured to wake up on the expiry of the
internal timer, external wake-up events, or the wake-up events
from Wi-Fi radio.
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The typical scenarios which N9 operates in and the power state transition are summarized in the
following table.
Table 2-4. Power State Transition Scenarios for N9
Scenario
1
Description
All functions are idle and the N9 firmware triggers to enter the
State transition
Active à Standby à Sleep
sleep mode.
2
Wi-Fi DTIM timer is expired and the hardware wakes up to listen
Sleep à MCU idle (Wi-Fi ON) à
to beacon and then goes to sleep again when It is not necessary
sleep
to wake up N9 to process the data.
3
Wi-Fi DTIM timer is expired and the hardware wakes up to listen
Sleep à MCU idle (Wi-Fi ON) à
to beacon and then wake up N9 to process the data.
Active
The typical scenarios which CM4 operates in and the power state transition are summarized in the
following table.
Table 2-5. Power State Transition Scenarios for CM4
Scenario
1
Description
All functions are idle and the CM4 firmware triggers to enter the
State transition
Active à Standby à Sleep
sleep mode.
2
The wake-up event (wake-up event from N9 or other sources)
Sleep à Standby à Active
triggers CM4 to wake up.
2.3
Clock and Reset Generation
2.3.1
Clock
MT7687F connects to the XTAL or external clock source as the single clock source of the whole
system. The XTAL oscillator can support the XTAL frequencies from among 40, 26, and 52MHz.
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XTAL CLOCK
XTAL
oscillator
RF PLL
WF RF
RF power domain
PLL1
f = 40/
26/52MHz
DIV
832MHz
640MHz
64MHz
81021170[12:8]
AON power domain
1
0
PMU
BGCLK
(25KHz)
32MHz
PLL2
960MHz
81021100[17:16]
0
DIV 794
F32K CLOCK
2
830081B4[23:19]
81021100[31:21]
FLASH CLOCK CM4 power domain
DIV
830081B4[7:3]
830081B4[14:13]
2
DIV
80021114[21:20]
1-32 step 1
PMU power domain
DIV 12
80MHz
DIV 1
960MHz
DIV 3
320MHz
WF_RXADC_CLK
WF_TXDAC_CLK
WF_DIG_CLK
DIV 8
81021100[15:14]
1
3
0
2-32 step 0.5
DIV 5
4
160MHz
81021100[9:4]
81021100[2:0]
N9 CLOCK
1-160MHz
0
1
830081B0[15:14]
1
3
0
2-32 step 0.5
DIV 5
4
830081B0[9:4]
192MHz
CM4 CLOCK
1-192MHz
0
1
DIV options:
480, 240, 120, 60,
30, 20, 15, 12, 10
830081B0[2:0]
120MHz
DIV
SPI CLOCK
24000028[27:16]
830081B4[17]
1
DIV
XPLL (Audio Frac-N)
±1% (0.01% granularity)
16MHz
250, 500KHz
1, 2, 4, 6, 8, 10, 12MHz
830B0000[27:24]
16MHz
I2S_MCLK
2
DIV 2
8300A600[2:1]
0
2
DIV 13 2MHz
PWM CLOCK
1
830081B4[12:8]
AUXADC CLOCK
DIV options: 520,260,130,65
DIV
83090244[15:0] 83090248[15:0]
I2C CLOCK
50, 100, 200, 400KHz
DIV options: 2708,1354,677,226
DIV
830A0244[15:0]830A0248[15:0]
UART CLOCK
9.6, 19.2, 38.4, 115.2KHz
Figure 2-3. Clock Generation Block Diagram



PLL1 is used to generate the clock sources for PLL2.
PLL2 is used to generate the clock sources for Wi-Fi, N9 core, Cortex-M4 core, and bus fabric.
XPLL is used to generate the clock sources for I2S (for external audio CODEC).
The options of clock rate for MCU are listed below.
Table 2-6. Cortex-M4 Clock Rate
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Reference Clock
(MHz)
MCU Clock
(MHz, XTAL mode)
40
40
26
26
52
52
MCU Clock
(MHz, PLL mode)
30, 32, 40, 48, 60, 80,
96, 120, 160, 192.
Table 2-7. N9 Clock Rate
Reference Clock (MHz)
MCU Clock
MCU Clock
(MHz, XTAL mode)
(MHz, PLL mode)
40
40
26
26
52
52
30, 32, 40, 48, 60, 80,
96, 120, 160, 192.
Table 2-8. Peripheral Clock Rate
PWM
Peripheral Clock Rate
Support SPEC
XTAL clock with DIV13 (Default)
200Hz at minimum.
XTAL clock
F32K clock
UART
XTAL clock with DIV
9.6, 19.2, 38.4, 115.2K
I2C
XTAL clock with DIV
50, 100, 200, 400KHz
SPI
XTAL clock with DIV (Default)
4, 6, 8, 10, 12MHz
Flash
XTAL clock with DIV (Default)
64MHz.
CM4 clock with DIV
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CM4 CLOCK
CM4
TCM
Cache
I2S
AHB
ASYNC
Bridge
x2
HIF SYS
WF
N9 CLOCK
INT
WDT SYSRAM GDMA MTK
Security
GPT
ADC
Flash
CTRL
SPI
I2C
x2
UART
x2
PWM
x40
ADC
CLOCK
FLASH
CLOCK
SPI
CLOCK
I2C
CLOCK
UART
CLOCK
PWM
CLOCK
Figure 2-4. Clock Domains in N9 and CM4 Peripherals
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2.3.2
Reset
MT7687F has three global resets: XRESETN, CM4_RESETN, and N9_RESETN. The figure below shows
the module that the reset signals are applied to.
Chip Cold Reset Event
Chip Cold Reset Event
Or
CM4 Host Reset Event
Chip Cold Reset Event
Or
N9 Host Reset Event
XRESETN Reset Tree
(1)CM4 WDT and GPT module
(2)CM4 WIC module
(3)N9 WDT and GPT module
(4)N9 interrupt module
(5)AON module (top MISC logic always on during sleep)
CM4_RESETN Reset Tree
CM4 MCU and all modules on CM4 bus other than XRESETN reset
tree
N9_RESETN Reset Tree
N9 MCU and all modules on N9 bus other than XRESETN reset
tree
Figure 2-5. Reset Structure
2.4
Application Processor Subsystem
The MCU subsystem consists of a 32-bit MCU, the AHB/APB bus matrix, internal RAM/ROM with
ROM patch function, the flash controller, and the system peripherals including Direct Memory Access
(DMA) engine and the General Purpose Timer (GPT).
2.4.1
CPU
MT7687F features an ARM Cortex-M4 processor, which is the most energy efficient ARM processor
available. It supports the clock rates from 1MHz up to 192MHz.
The MCU executes the Thump-2 instruction set for optimal performance and code size, including
hardware division, single cycle multiplication, and bit-field manipulation.
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MT7687F includes the memory protection unit (MPU) in Cortex-M4 MCU that provides memory
protection features. It can be used to detect unexpected memory access.
MT7687F also includes floating point unit (FPU) in Corxex-M4 process to support DSP related
function.
2.4.2
Cache and Tightly Coupled Memory
MT7687F has a cache for Cortex-M4 to improve the efficiency of the code and data fetch from the
external flash. The only cacheable memory region is the external flash.
MT7687F also has a Tightly-Coupled-Memory (TCM), a zero-wait-state memory which is dedicated
for Cortex-M4 and can be accessed by Cortex-M4 exclusively. It is a memory space for the critical
code such as interrupt service routines which needs to be executed with minimum latency. The DMA
engines on AHB bus can’t access TCM.
The total size of memory of the cache and the TCM is 96KB. Four software-configurable options differ
in the size of cache, the size of TCM, and the cache associativity. The user can select the option which
maximizes the performance.
The cache system has the following features:




Configurable 1/2/4-way set associative (8KB/16KB/32KB)
Each way has 256 cache lines with 8-word link size
20-bit tag memory: 19-bit high address and 1-bit valid bit
2-bit dirty memory: each dirty bit identifies the dirtiness of half cache line
The size of SRAM is 96KB. It can be configured to the following configuration




96KB TCM, no cache
88KB TCM, 8KB cache (1 way, direct mapped)
80KB TCM, 16KB cache (2 way set-associative)
64KB TCM, 32KB cache (4 way set-associative)
The configuration setting and the memory configuration are shown in the following table.
Table 2-9. TCM and Cache Configuration
0x0153_0000[9:8]
Functional Description
Start Address
End Address
00b
96KB TCM, no cache
0x0010_0000
0x0011_7FFF
01b
88KB TCM, 8KB cache, direct mapped
0x0010_0000
0x0011_5FFF
10b
80KB TCM, 16KB cache, 2-way set-associative
0x0010_0000
0x0011_3FFF
11b
64KB TCM, 32KB cache, 4-way set associative
0x0010_0000
0x0010_FFFF
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The cache controller provides the user ways to perform cache operations including invalidate
single/all cache lines as well as flush one/all cache lines.
To facilitate tuning the system performance, the cache controller can record the statistics of the
cache hit count and the number of cacheable memory access. Cache hit rate can be obtained by
dividing the cache hit count by the number of memory access.
2.4.3
Bus Fabric
MT7687F implements AHB/APB bus fabric to connect the MCU, memory, IO peripherals, and the
radio subsystem.


ILM/DLM: Instruction Local Memory / Data Local Memory, the zero-wait-state local
memory for Radio MCU.
Wi-Fi HIF: The data interface to Wi-Fi Packet switch engine.
ARM Cortex M4
ILM/DLM
N9
SYSTEM DCODE
ICODE
TCM ROM
AHB mux
Asyncrhrous AHB-2AHB bridge
(N9 bus to CM4 bus)
Crypto
Engine
Generic DMA
Cache
Controller
TCM/Cache
(96KB)
XIP
CM4 AHB bus
APB
bridge
I2S
Wi-Fi HIF
SPI flash
SYSRAM_
CM4
(256KB)
N9 AHB bus
APB2 bus
BT FIFO
I/F
I2C-2
I2C-1
UART2
UART1
AUX
ADC
TOP &
CM4
CONFIG
Asyncrhrous AHB-2AHB bridge
(CM4 bus to N9 bus)
PWM
SPI-M
GPT
WDT
GDMA
CONFIG
APB
bridge
APB
bridge
APB1 bus
APB0 bus
Interface to radio subsystem
Indium peripherals
Figure 2-6. CM4 Subsystem – Bus Fabric
The AHB bus arbitration adopts round-robin scheme.
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The N9 subsystem and Cortex-M4 subsystem are in different clock domains, so the asynchronous
bridges are inserted in the bus fabric. N9 has the ability to (but would be rarely used) all the M4
peripherals.
2.4.4
Serial Flash Controller
MT7687F features a serial flash controller that can support the serial flash with the read mode of
(JEDEC) standard SPI mode, SPI-Quad mode, QPI (Quad Peripheral Interface) mode, Dual IO mode,
and Dual-Output mode.
The frequency of the serial clock rate is up to 64MHz. That provides 256Mbps equivalent throughput
on flash when SPI-quad mode or QPI mode is used.
Table 2-10. Flash Controller Support Read Mode
Read Mode
Description
SPI
1xIO for receiving command and address, 1xIO for output data
SPI-Quad
1xIO for receiving command, 4xIO for address, 4xIO for output data
QPI
4xIO for receiving command/address and output data
Dual-IO
1xIO for command, 2xIO for address and output data
Dual-Output
1xIO for receiving command, 2xIO for address and output data
The Serial Flash Controller Supports Two Operation Modes:
Direct read mode, which supports a high-throughput direct-access through AHB bus
Macro access mode, which supports flash access with arbitrary command and is through APB
bus.


2.4.5
DMA
Direct memory access (DMA) is used to transfer data between memory ↔ memory as well as
memory ↔ peripherals without MCU intervention.
2.4.5.1
DMA Functional Description
There are three types of DMA channels supported in MT7687F.



Full-size DMA: Both the source address and the destination address are programmable. It is
normally used for memory copy.
Half-size DMA: Either the source address or the destination address is programmable. It is
normally used for data movement between memory and peripherals.
Virtual FIFO DMA (VFF DMA): It is a half-size DMA with an additional FIFO control engine. It is
used to provide the buffering capacity for peripherals including UART.
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2.4.5.1.1
Virtual FIFO
Virtual FIFO DMA is designed to offload the control of the serial interface. The difference between
the virtual FIFO DMA and the full-size/half-size DMA is that the virtual DMA contains an additional
FIFO controller.
The figure below illustrates the operations of virtual FIFO DMA used for UART RX.
READ: DMA controller reads data from UART and increments the WRITE pointer of the FIFO
controller.
WRITE; DMA controller writes data that was area from UART to SRAM in the area defined
before enabling the virtual FIFO.
READ: MCU reads data when FIFO is not empty and the amount of data is over a pre-defined
threshold. The read transaction will be finished only when DMA controller reads back the
data from SRAM.
READ: DMA controller reads data from SRAM and increments the READ pointer of the FIFO
controller.




Destination Address
READ pointer
(MCU)
DMA
MCU
(1) READ
FIFO size
(3) READ
memory
(4) READ
WRITE pointer
(UART RX)
(2) WRITE
SRAM
UART
Figure 2-7. Virtual FIFO Concept
2.4.5.2
DMA Channels and Priority Control
There are two full-size DMA channels, 10 half- size DMA channels, and 13 virtual FIFO DMA channels
in MT7687F.
Table 2-11. DMA Use for Hardware Functions
Hardware Function
DMA Type
Radio (Wi-Fi)
Half size DMA x 1
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Hardware Function
DMA Type
UART (x2)
Virtual FIFO DMA x 4
I2S
Virtual FIFO DMA x 2
ADC
Virtual FIFO DMA x 1
I2C (x2)
Half size DMA x 4
SPI-M
Half size DMA x 2
Secure boot
Full size DMA x 1
Reserved
Full size DMA x 1, half size DMA x 3 and virtual FIFO DMA x 4.
The DMA provides two levels of scheduling scheme among all channels.
The 1st level scheduling follows the strict-priority scheme. All channels can be grouped into four
priority groups. Group one gets the highest priority, then group two, and so on.
The 2nd level scheduling follows the round-robin scheme. Every channel in the same priority group
has equal opportunity to use the bandwidth and was served sequentially.
The arbitration is done per AHB transaction. When one AHB transaction is finished, the scheduler will
follow the above mechanism to select the next DMA channel to serve.
2.4.6
General Purpose Timer
MT7687F includes the General Purpose Timer (GPT).
Five independent timers are included. Timer 0, 1, and 3 are interrupt-based timers, while timer 2 and
timer 4 are free-run timers.
Two modes are defined in interrupt-based timers:


One-shot mode—the timer stops when the timer counts down to 0.
Auto-repeat mode—the timer re-starts when the timer counts down to 0.
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Table 2-12. General Purpose Timer Types
Mode
Clock speed
Interrupt Source
GPT0
Interrupt-based
1KHz or 32KHz
GPT
GPT1
Interrupt-based
1KHz or 32KHz
GPT2
Free-run
1KHz or 32KHz
n/a
GPT3
Interrupt based
26MHz (oscillator clock)
GPT3
GPT4
Free-run
Bus clock or bus clock / 2
n/a
2.4.7
Watchdog Timer
MT7687F features the watchdog timer for CM4, which is used to recover the system to the initial
status when the system hangs due to some malfunction.
WDT provides two ways to generate the WDT event:


Triggered by the time-out event (by configuring WDT_MODE:0x83080030 and
WDT_LENGTH:0x83080034). The WDT has an 11-bit counter and it uses the 32 KHz clock.
The software regularly restarts the timer to prevent it from expiring. If it fails to restart the
WDT, the timer would expire and generate a WDT event.
Triggered by software programming (WDT_SWRST:0x83080044).
WDT provides the following options when a WDT event is generated:

0x83080030[3]=0: Reset mode
- 0x8300917C[16] = 1: WDT whole chip mode. Reset the whole chip including CM4 and N9
subsystems.
- 0x8300917C[16] = 0: WDT MCU mode. Reset CM4 subsystem only.

0x83080030[3]=1: Interrupt mode
-Issue an interrupt to CM4 instead of resetting whole chip or CM4 subsystem.
The WDT module can only be reset by the external reset (SYS_RST_N) and the PMU reset. Some WDT
control registers feature a key protection mechanism such that an unintentional access would be
prevented.
WDT also provides the capability for CM4 software to interrupt N9 or reset N9 (by configuring
WDT_DUAL_CORE:0x83080080).
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2.4.8
Efuse
MT7687F uses embedded Efuse to store device specific configuration information such as MAC
addresses, and power control settings.
The major fields defined in the Efuse:
Wi-Fi MAC addresses
Wi-Fi country code
Wi-Fi TSSI parameters, TX power level
Wi-Fi NIC configuration: RF front-end configuration, LED mode, baseband configuration




2.4.9
Interrupt Controller
MT7687F integrates the Nested Vectored Interrupt Controller (NVIC) for Cortex-M4. The NVIC
supports
Level and pulse detection of interrupt signals
Configurable priority
Wake-up interrupt controller (WIC) providing ultra-low power sleep mode support



2.4.9.1
Interrupt Sources
The table below listed the NVIC and WIC interrupt sources. In total, there are 49 NVICs, while 23 of
them are external interrupts multiplexed with GPIO functions.
The power domain/subsystem lists the power domain and the subsystem from which the interrupt is
generated.
Table 2-13. CM4 NVIC Interrupt Source
NVIC
No.
Interrupt
source
Power domain /
subsystem
External
interrupt
Wake-up
capability
(1)
De-bounce
Description
INT0
UART1
CM4_OFF/MCUSYS_CM4
UART 1
INT1
DMA_CM4
CM4_OFF/MCUSYS_CM4
Generic DMA in CM4 subsystem
INT2
HIF_CM4
TOP_AON/HIFSYS
INT3
I2C1
CM4_OFF/MCUSYS_CM4
I2C 1
INT4
I2C2
CM4_OFF/MCUSYS_CM4
I2C 2
INT5
UART2
CM4_OFF/MCUSYS_CM4
UART 2
INT6
CRYPTO
CM4_OFF/MCUSYS_CM4
Crypto engine
INT7
SF
CM4_OFF/MCUSYS_CM4
Serial flash controller, for debug
INT8
(Reserved)
INT9
(Reserved)
INT10
WDT_CM4
TOP_AON/MCUSYS_CM4
V
Watchdog timer in CM4
subsystem
INT11
N9_TO_CM4
TOP_AON/MCUSYS_N9
V
N9 software interrupt to CM4
V
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NVIC
No.
Interrupt
source
Power domain /
subsystem
External
interrupt
Wake-up
capability
(1)
De-bounce
Description
_SW1
INT12
SPI_S
CM4_OFF/MCUSYS_CM4
SPI slave
INT13
WDT_N9
TOP_AON/MCUSYS_N9
INT14
ADC
CM4_OFF/MCUSYS_CM4
Auxiliary ADC FIFO
INT15
IRTX
CM4_OFF/MCUSYS_CM4
IrDA TX
INT16
IRRX
CM4_OFF/MCUSYS_CM4
IrDA RX
INT17
(Reserved)
INT18
(Reserved)
INT19
RTC_TIMER
RTC
V
RTC timer interrupt
INT20
GPT3
CM4_OFF/MCUSYS_CM4
V
GPT3 time-out
INT21
RTC_ALARM
RTC
V
RTC alarm interrupt
INT22
(Reserved)
INT23
N9_TO_CM4
_SW2
TOP_AON/MCUSYS_N9
V
N9 software interrupt to CM4
INT24
GPT
TOP_CON/MCUSYS_CM4
V
GPT0 or GPT1 time-out
INT25
ADC_COMP
TOP_AON
V
ADC comparison mode
INT26
(Reserved)
INT27
SPI
INT28
(Reserved)
INT29
(Reserved)
INT30
(Reserved)
INT31
WIC
TOP_AON/MCUSYS_CM4
INT32
SWD_CLK
TOP_AON
WIC[0]
V
Available
GPIO[2]
INT33
I2C1_DATA
TOP_AON
WIC[1]
V
Available
GPIO[25]
INT34
I2C0_CLK
TOP_AON
WIC[2]
V
Available
GPIO[27]
INT35
I2S_MCLK_S
PI_MOSI
TOP_AON
WIC[3]
V
Available
GPIO[29]
INT36
I2S_BCLK_S
PI_CS
TOP_AON
WIC[4]
V
Available
GPIO[32]
INT37
ANT_SEL0
TOP_AON
WIC[5]
V
Available
GPIO[33]
INT38
ANT_SEL1
TOP_AON
WIC[6]
V
Available
GPIO[34]
INT39
GPIO17
TOP_AON
WIC[7]
V
Available
GPIO[36]
INT40
ADC0
TOP_AON
WIC[8]
V
Available
GPIO[57]
INT41
ADC1
TOP_AON
WIC[9]
V
Available
GPIO[58]
INT42
ADC2
TOP_AON
WIC[10]
V
Available
GPIO[59]
V
Watchdog timer in N9 subsystem
CM4_OFF/MCUSYS_CM4
SPI transaction
V (2)
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WIC WAKEUP interrupt CM4
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NVIC
No.
Interrupt
source
Power domain /
subsystem
External
interrupt
Wake-up
capability
(1)
De-bounce
Description
INT43
ADC3
TOP_AON
WIC[11]
V
Available
GPIO[60]
INT56
PWM0
TOP_AON
EINT[0]
V
Available
GPIO[0]
INT57
PWM1
TOP_AON
EINT[1]
V
Available
GPIO[1]
INT58
SWD_DIO
TOP_AON
EINT[2]
V
Available
GPIO[3]
INT59
GPIO0
TOP_AON
EINT[3]
V
Available
GPIO[4]
INT60
GPIO1
TOP_AON
EINT[4]
V
Available
GPIO[5]
INT61
GPIO2
TOP_AON
EINT[5]
V
Available
GPIO[6]
INT62
GPIO3
TOP_AON
EINT[6]
V
Available
GPIO[7]
INT75
GPIO16
TOP_AON
EINT[19]
V
Available
GPIO[35]
INT76
GPIO18
TOP_AON
EINT[20]
V
Available
GPIO[37]
INT77
GPIO19
TOP_AON
EINT[21]
V
Available
GPIO[38]
INT78
GPIO20
TOP_AON
EINT[22]
V
Available
GPIO[39]
Note 1; Capable to wake up CM4 when CM4 is in sleep mode.
Note 2: This interrupt is associated with other wake-up interrupts for CM4 to differentiate wake-up interrupts
from non wake-up interrupts.
2.4.9.2
External Interrupt
MT7687F has the optionally enabled hardware de-bouncing circuit for each interrupt source.
Table 2-14. CM4 External Interrupt De-Bounce Period
Reference clock rate for
Minimum de-bounce
Maximum de-bounce
de-bounce counter (KHz)
period (ms)
period (ms)
000
8
0.13
2
001
4
0.25
4
010
2
0.5
8
011
1
1
16
3-bit prescaler
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Reference clock rate for
Minimum de-bounce
Maximum de-bounce
de-bounce counter (KHz)
period (ms)
period (ms)
100
0.5
2
32
101
0.25
4
64
110
0.125
8
128
111
0.0625
16
256
3-bit prescaler
2.4.10
Power-on Sequence
The power-on control sequence diagram shows how the code reset (PMU_RESET_N) is generated on
chip.
Figure 2-8. PMU Power-on Sequence
2.4.10.1
Power-on Reset (Cold Reset)
The power on reset sequence after chip power on is shown below.
Step 1: N9 reset is de-asserted and boot from ROM (CM4 reset state is still asserted)
Step 2: N9 sets up top configuration registers (such as PLL) and then de-asserts CM4 reset
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Step 3: CM4 boots from ROM while N9 polls the PDA (Patch Decryption Accelerator) status
Step 4: CM4 fetch flash header (N9 FW download length information)
Step 5: CM4 setup PDA and PDA address generator
Step 6: PDA loads firmware from the flash to N9 IDLM
Step 7: N9 executes from IDLM after PDA completes and CM4 executes from Cache/Flash or
TCM.
2.4.10.2
Watchdog Reset
Watchdog reset WDT_N9 is the watchdog timer for N9, and WDT_CM4 is the watchdog timer for
CM4.
When the WDT event of WDT_N9 occurs, WDT_N9 has the capability to


Reset N9 or issue an interrupt to N9.
Issue an interrupt to CM4 (can be masked by CM4 if it is not required to be received).
When the WDT event of WDT_CM4 occurs, WDT_CM4 has the capability to


Reset whole chip or reset CM4 only or issue an interrupt to CM4.
Issue an interrupt to N9 (can be masked by N9 if it’s not required to be received).
For both WDT_N9 and WDT_CM4, the WDT events can be triggered by time-out and software
programming.
For both WDT_N9 and WDT_CM4, the WDT has the capability to reset the other CPU or issue an
interrupt to the other CPU.
CM4_SW_RST_B
81080080[0]
D12: SYS_RST_N
N9 RELEASE CM4
81020018[0]
R16: AVDD45_BUCK
PMU
PMU_RST_B
POR_XRESET_RST_B
SEL: 8300917C[16]
CM4_OFF
RELEASE_CM4_RST_B
CM4_AON_
HRESET_RST_B
CM4_AON_XRESET_RST_B
CM4_HW_RST_B
CM4_RGU_HRESET_RST_B
INT10
CM4 MTCMOS
power CTRL
Y
N
83080030[3]
=1?
NVIC
INT13
WDT_N9 interrupt
N9_WDT_RST_BàINT13
INT23
N9_TO_CM4_SW2 ingterrupt: 81080080[31:30]
WDT_DUAL_CORE_SW_INTàINT23
CM4_WDT_RST_B
WIC
WDT_CM4
AON_XRESET_RST_B
Legend:
Reset:
Interrupt:
CM4
peripherals
ARM CM4
WDT_N9
CM4 to N9 interrupt: 83080080[31:30]
WDT_DUAL_CORE_SW_INTàCIRQ EINT 3
N9_SW_RST_B
83080080[0]
CIRQ EINT3
CIRQ INT22
CIRQ INT10
RGU_HRESET_RST_B
Note:
PMU_RST_B: power-on or over-current protection
CM4_WDT_RST_B: CM4 WDT reset
N9_WDT_RST_B: N9 WDT reset
N9 MTCMOS
power CTRL
CIRQ
N9
peripherals
N9
N9_HW_RST_B
TOP_OFF (N9)
Y
N
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81080030[3]
=1?
N9_WDT_RST_B
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Figure 2-9. WDT Structure
2.4.10.3
Reset Scenarios
The definitions of the cold reset and the warm reset are shown below:


2.4.10.4
Cold Reset: Power on reset and both RAM or peripheral devices will be initialized by
firmware.
Warm Reset: CPU is reset but RAM content is still retained (without firmware redownload). It’s triggered by
o Software reset: Software set WDT reset control register to reset CPU.
o WDT reset: WDT expiration cause CPU to reset if enabled, otherwise interrupt.
o Core reset: Reset by the other CPU (e.g. N9 to reset CM4 or CM4 to reset N9).
o Wake-up from deep sleep mode: Reset by the MTCMOS power control.
Sleep/Wakeup sequence
The sleep/wakeup control sequence is shown in the diagram below.
Figure 2-10. Sleep/Wakeup Sequence
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2.4.11
Memory Map
The table below describes how the peripherals are mapped to the CM4 memory.
When the MCU performs a read transaction to an undefined address, the bus returns 0. When the
MCU performs a write transaction to an undefined address, the bus regards it as an invalid
transaction and does nothing. The memory space of 0x5040_0000 to 0x5FFF_FFFF is an undefined
region and shall not be accessed.
The power domain is identified in the table. The hardware clock gating is associated with the power
control. When the CPU power domain is in power-off mode, it implies that the clock is also gated.
The software clock gating control, identified in the table below, provides the way to disable the
function and lower its power consumption when the function is not used.
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Table 2-15. CM4 Memory Map
Start address
End address
Function
Power Domain
0x0000_0000
0x0000_FFFF
TCM ROM
CM4_OFF
Tightly Coupled
ROM for CM4
0x0010_0000
0x0010_FFFF
TCM RAM0
CM4_OFF
0x0011_0000
0x0011_1FFF
TCM RAM1
CM4_OFF
Tightly Coupled
RAM for CM4
(64KB)
Tightly Coupled
RAM for CM4 (8KB)
0x0011_2000
0x0011_3FFF
TCM RAM2
CM4_OFF
Tightly Coupled
RAM for CM4 (8KB)
0x0011_4000
0x0011_5FFF
TCM RAM3
CM4_OFF
Tightly Coupled
RAM for CM4 (8KB)
0x0011_6000
0x0011_7FFF
TCM RAM4
CM4_OFF
Tightly Coupled
RAM for CM4 (8KB)
0x1000_0000
0x1FFF_FFFF
Serial Flash CM4
CM4_OFF
Serial flash of CM4
0x2000_0000
0x2003_FFFF
SYSRAM_CM4
CM4_OFF
System RAM for
CM4, 256Kbytes
0x2100_0000
0x2100_FFFF
SPI-S
CM4_OFF
0x8300_0200[21]
SPI slave
0x2200_0000
0x2200_FFFF
I2S/Audio
CM4_OFF
0x8300_0200[14]
I2S
0x2400_0000
0x2400_FFFF
SPI-M
CM4_OFF
0x8300_0200[22]
SPI master
0x2500_0000
0x2500_CFFF
SYSRAM_N9
TOP_OFF(N9)
System RAM for N9,
52Kbytes
0x3000_0000
0x3FFF_FFFF
Serial Flash CM4
CM4_OFF
Serial flash of CM4
through system bus
0x5000_0000
0x501F_FFFF
HIF_device
TOP_OFF(N9)
Host interface
device controller
0x5020_0000
0x502F_FFFF
HIF_host_CM4
TOP_AON
Host interface host
controller of Wi-Fi
radio
0x5040_0000
0x5FFF_FFFF
(Undefined)
0x6000_0000
0x6FFF_FFFF
WIFISYS
0x7000_0000
0x70FF_FFFF
PDA DMA port
0x7800_0000
0x7800_FFFF
VFF access port
TOP_OFF(N9)
TOP_OFF(N9)
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Software Clock
gating control
0x8000_0100[5]
Description
Wi-Fi subsystem
Patch Decryption
Accelerator DMA
slave
Virtual FIFO access
ports of N9 DMA
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Start address
End address
Function
Power Domain
Software Clock
gating control
Description
0x7900_0000
0x7900_FFFF
VFF_CM4 access
port
CM4_OFF
0x8300_0200[3]
Virtual FIFO access
ports of CM4 DMA
0x8000_0000
0x800C_FFFF
APB0
TOP_OFF(N9)
APB bridge 0
(synchronous to N9)
0x8000_0000
0x8000_FFFF
CONFG
TOP_OFF(N9)
N9 subsystem
configuration
0x8001_0000
0x8001_FFFF
DMA
TOP_OFF(N9)
Generic DMA
engine for N9
0x8002_0000
0x8002_FFFF
TOP_CFG_OFF
TOP_OFF(N9)
TOP_OFF(N9)
power domain chip
level configuration
(GPIO, PINMUX, RF,
CLK control)
0x8003_0000
0x8003_FFFF
UART
TOP_OFF(N9)
0x8000_0100[6]
UART host interface
for N9
0x8005_0000
0x8005_FFFF
UART_PTA
TOP_OFF(N9)
0x8000_0100[11]
Inter-chip
communication for
PTA
0x8008_0000
0x8008_FFFF
AHB_MON
TOP_OFF(N9)
0x8000_0100[10]
AHB bus monitor
0x800A_0000
0x800A_FFFF
UART_DSN
TOP_OFF(N9)
0x8000_0100[7]
UART for N9 debug
0x800B_0000
0x800B_FFFF
SEC
TOP_OFF(N9)
Secure boot
configuration
0x800C_0000
0x800C_FFFF
HIF
TOP_OFF(N9)
Host interface
configuration
0x8100_0000
0x810C_FFFF
APB1
TOP_OFF(N9)
APB bridge 1
(synchronous to N9)
0x8102_0000
0x8102_FFFF
TOP_CFG_AON
TOP_AON
0x8103_0000
0x8103_FFFF
DBG_CIRQ
TOP_AON
TOP_AON power
domain chip level
configuration (RGU,
PINMUX, PLL, PMU,
XTAL, CLK control)
Debug interrupt
controller for N9
0x8104_0000
0x8104_FFFF
CIRQ
TOP_AON
Interrupt controller
for N9
0x8105_8000
0x8105_FFFF
GPT
TOP_AON
General Purpose
Timer for N9
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Start address
End address
Function
Power Domain
Software Clock
gating control
Description
0x8106_0000
0x8106_FFFF
PTA
TOP_OFF(N9)
0x8000_0100[14]
Packet Traffic
Arbitrator for Wi-Fi
0x8107_0000
0x8107_FFFF
EFUSE_MAC
TOP_OFF(N9)
0x8000_0100[12]
Efuse controller
0x8108_0000
0x8108_FFFF
WDT
TOP_AON
Watchdog Timer for
N9
0x8109_0000
0x8109_FFFF
PDA
TOP_OFF(N9)
Patch Decryption
Accelerator
0x810A_0000
0x810A_FFFF
RDD
TOP_OFF(N9)
0x810C_0000
0x810C_FFFF
RBIST
TOP_OFF(N9)
0x8300_0000
0x810C_FFFF
APB2
CM4_OFF
0x8300_0000
0x8300_7FFF
CONFG_CM4
CM4_OFF
0x8300_8000
0x8300_BFFF
TOP_AON
0x8300_C000
0x8300_EFFF
TOP_CFG_AON_C
M4
CONFG_CM4_AON
0x8300_F000
0x8300_FFFF
SEC_TOP_CM4
CM4_OFF
0x8300_0200[0]
JTAG security for
CM4
0x8301_0000
0x8301_FFFF
DMA_CM4
CM4_OFF
0x8300_0200[3]
Generic DMA
engine for CM4
0x8302_0000
0x8302_FFFF
UART_DSN
CM4_OFF
0x8300_0200[4]
0x8303_0000
0x8303_FFFF
UART1
CM4_OFF
0x8300_0200[5]
UART for CM4
debug
UART 1 for CM4
0x8304_0000
0x8304_FFFF
UART2
CM4_OFF
0x8300_0200[6]
UART 2 for CM4
0x8305_0000
0x8305_FFFF
GPT_CM4
TOP_AON
0x8306_0000
0x8306_FFFF
IrDA
CM4_OFF
0x8000_0100[23]
Wi-Fi debug
RF BIST
configuration
APB bridge 1
(synchronous to
CM4)
System
configuration for
CM4
TOP_AON
configuration
System
configuration for
CM4 in TOP_AON
domain
TOP_AON
General Purpose
Timer for CM4
0x8300_0200[8]
IrDA
0x8300_0200[9]
0x8307_0000
0x8307_FFFF
Serial flash
CM4_OFF
0x8308_0000
0x8308_FFFF
WDT_CM4
TOP_AON
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0x8300_0200[10]
Serial flash macro
access
Watchdog Timer for
CM4
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Start address
End address
Function
Power Domain
Software Clock
gating control
Description
0x8309_0000
0x8309_FFFF
I2C_1
CM4_OFF
0x8300_0200[12]
I2C 1
0x8300_0200[23]
0x830A_0000
0x830A_FFFF
I2C_2
CM4_OFF
0x8300_0200[13]
I2C 2
0x8300_0200[24]
0x830B_0000
0x830B_0FFF
I2S
CM4_OFF
0x8300_0200[14]
I2S configuration
0x830C_0000
0x830C_FFFF
RTC
RTC
0x830D_0000
0x830D_FFFF
AUXADC
CM4_OFF
0x8300_0200[16]
Auxiliary ADC
configuration
0x830F_0000
0x830F_FFFF
Crypto
CM4_OFF
0x8300_0200[18]
Crypto engine
0xA000_0000
0xAFFF_FFFF
PSE
CM4_OFF
Packet switch
engine memory
0xE000_E000
0xE000_EFFF
NVIC, SYSTICK, FPU
CM4_OFF
Nested vectored
interrupt controller
Real time clock
System Control
Space (SYSTICK)
Floating-point unit
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2.4.12
SYSRAM_CM4
SYSRAM, the internal SRAM, is mapped on the system bus interface of Cortex-M4. M4 can carry out
instruction fetches and data accesses to the SYSRAM.
SYSRAM is the internal SRAM that the DMA engine can access. It can be used as a GDMA or VFIFO
buffer, the source and the destination of GDMA controller, for memory-to-memory transfer as well
the transfer between memory and peripherals.
2.4.13
Crypto engine
The crypto engine supports


2.5
AES, DES, and 3DES encryption and decryption engine.
SHA256, SHA512 and MD5 hash engines.
Peripherals
Several peripheral are multiplexed GPIOs. MT7687F has two dedicated UART interfaces with flow
control, one dedicated I2C interface, and one dedicated IrDA interface.
MT7687F also has the 2nd I2C interface, the SPI slave interface, the I2S interface, and the SPI master
interface, but only 2 of the above interfaces can be effective at a time.
The section describes the function of all the peripherals.
2.5.1
GPIO Interface
2.5.1.1
GPIO Function
There are two types of GPIO (General purpose IO) designs in MT7687F: GPIO and AGPIO.
Floating-well design is used in GPIO and AGPIO. It prevents potential leakage problem when the
DVDD33 power supply is not enabled but the pin input is pulled up to 3.3V source.
MT7687F offers GPIO, each with the following configuration options:








Input / Output mode
Slew rate control
Schmitt trigger hysteresis control
Input mode: Floating (Hi-Z), pull-up, or pull-down
Output mode: Active driving, or open drain
Pull up/down control. The pull-up and pull-down resistance is 75KΩ with ±20% variation
over PVT condition
Driving strength: 4mA, 8mA, 12mA, 16mA
Input and output duty cycle tuning
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AGPIO Function Table
G E Function
=============================
0 0 Analog Function (IO <- -> AIO)
0 1 Analog Function (IO <- -> AIO)
--------------------------------------------------1 0 Digital Function (IO -----> O)
1 1 Digital Function (IO <- -- I)
(4 – 16 mA Driving)
IO
Floating Well
4 – 16 mA
I
IO
Floating Well
4 – 16 mA
I
E
E
G
Logic 1 -> Switch on
PU
O
PD
PU
O
PD
AIO_ANALOG_DONT_TOUCH
AGPIO
GPIO
Figure 2-11. AGPIO/GPIO Block Diagram (Left: AGPIO; Right: GPIO)
The digital IO AGPIO function is equivalent to GPIO as shown above. A dedicated internal control
signal is used to select between the digital and analog functions. The IOs are multiplexed with 16
channels ADC.
Output Signal Multiplexing
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Function-[9:1]-AON and Function-[9:0] can all be output to PINX by setting pinx_pinmux_aon_sel and
pinx_pinmux_off_sel, as shown in Figure 2-12 below. Function-[9:1]-AON signals are part of
TOP_AON domain and Function-[9:0] signals are part of TOP_OFF (N9) domain. The output of the
pad is enabled through E and G pad controls which require 2’b11 for digital output mode.
For a specific pin there could be only a limited number of functions available, these functions are
mapped anywhere to the different inputs of the muxes (not always in an incremental scheme).
TOP_AON domain means the circuit is always powered on when PMU supplies the power. TOP_OFF
(N9) domain means the N9 related circuit is powered off in some scenarios when PMU supplies the
power.
pinx_pinmux_aon_sel
PINX
PAD_PINX
I
IO
E
1'b1
G
1'b1
0
ISO
1
Function 1 AON (O)
2
Function 2 AON (O)
0
Function 0 (O)
1
Function 1 (O)
2
Function 2 (O)
9
9
Logic 1
->Switch on PU
pinx_pinmux_off_sel
Function 9 AON (O)
Function 9 (O)
TOP_OFF(N9) domain
O
TOP_AON domain
PD
AIO_ANALOG_DONT_TOUCH
Figure 2-12. AGPIO Configured as Output Multiplexing
Input Signal Multiplexing
Figure 2-13 below shows that PINX is the source of Function-AON-0, while PINX and PINY can both
be the input source for Function-1. The (E, G) setting for both IO is 2’b01 for digital input mode.
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PINX
I
IO
pinx_pinmux_aon_sel
E
1'b0
G
1'b1
1'b0
PINX
Logic 1
->Switch on PU
0
Function AON 0
1
O
pinx_pinmux_aon_sel
PD
pinx_pinmux_sel
1
AIO_ANALOG_DONT_TOUCH
1'b0
1
0
Function 1
0
piny_pinmux_aon_sel
PINY
PINY
I
IO
1'b0
Logic 1
->Switch on PU
E
1'b0
G
1'b1
1
0
TOP_AON domain
TOP_OFF domain
O
PD
AIO_ANALOG_DONT_TOUCH
Figure 2-13. AGPIO Configured as Input Multiplexing
Input / Output / Analog Signal Multiplexing
This figure below shows how function-0, function-1 and Analog-function share the same IO (PINX) by
configuring (E, G) pair internally. G is controlled in off domain.
Table 2-16. Functional Description of AGPIO
(G,E) value
2’b11
2’b10
2’b0x
Function
PINX=Function-0
Function-1=PINX
Analog-function=PINX
(output mode)
(input mode)
(analog mode)
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PINX
IO
I
Function 0
E
G
Logic 1
->Switch on PU
O
Function 1
PD
AIO_ANALOG_DONT_TOUCH
Analog function
Figure 2-14. AGPIO Configured as Input, Output, or Analog Mode
Open Drain Mode
The GPIO can be configured as open drain mode by assigning I=1’b0, G=1’b1 and E=Function-0.
PINX
1'b0
I
IO
Logic 1
->Switch on PU
E
Function 0
G
1'b1
O
PD
AIO_ANALOG_DONT_TOUCH
Figure 2-15. GPIO Configured as Open Drain Mode
2.5.2
UART Interface
MT7687F has two UART interfaces. The UART has M16C450 and M16550A modes of operation,
which are compatible with a range of standard software drivers.MT7687F supports UART with
configurable BAUD rates from 9.6Kbps, 19.2Kbps, 38.4Kbps, 115.2Kbps, and 921.6Kbps.
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2.5.3
I2C Serial Interface
MT7687F features two I2C serial interface master controllers. The two signals of I2C channel 0 are
I2C0_CLK and I2C0_DATA.
I2C0_CLK is a clock signal that is driven by the master.
I2C0_DATA is a bi-directional data signal that can be driven by either the master or the slave.
It supports the clock rate of 50, 100, 200, and 400 KHz.
I2C channel 1 supports the same feature as channel 0.



2.5.4
Auxiliary ADC function
MT7687F features one auxiliary ADC function. The ADC function contains a 4-channel analog switch,
a single-end input asynchronous 12-bit SAR (Successive Approximation Register) ADC, and a digital
averaging function. The digital averaging function can perform on-the-fly averaging function of
1/2/4/8/16/32/64 points. The ADC features the dithering function to enhance the DNL performance.
The ADC uses an external VREF20 as a reference voltage.
AUXADC_MUX[3:0]
AUXADC0
Vin
MUX
Vin
CDAC
Vref
0
AUXADC3
Vin
Vref
Vref
Vref=1.8V
RDAC
VREF20
Vcm buf
0
CMP
SAR
Control
Logic
12
Digital
Output
Vin
Vrdac Vrdac
0
CLK
(2MHz)
VCM
Figure 2-16. Auxiliary ADC Block Diagram (Analog Part)
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Digital averaging
ADC IP (Analog)
4-to-1
MUX
CLKOUT(2MS/s)
ADC
12
12
1/2/4/8/16/32/64
average
Bus
interface
Memory
hclk_ck
Interrupt
AUXADC_MUX[3:0]
MCU
CLK(2MS/s) REG_AVG_MODE[2:0]
ADC_EN
Figure 2-17. Auxiliary ADC Block Diagram
0.5 uS
ADC sampling
2MHz Clock
ADC bit-cycling
Sample #3
ADC sampling
ADC bit-cycling
Sample #4
ADC sampling
ADC bit-cycling
Sample #5
Internal asyn. Clock
AUXADC_DOUT
DOUT #1
DOUT #2
DOUT #3
Figure 2-18. Auxiliary ADC Clock Timing Diagram
Auxiliary ADC Features:





2.5.5
Input channel number: 4 channels
Sampling and output data rate: 2MS/s
DNL without dithering and averaging: <±2LSB
DNL with dithering and averaging: <±1LSB
Dithering function: 16 levels with step size of 4LSB.
SPI Master Interface
MT7687F features one SPI master controller. It is used as an extension interface to control the
peripheral device on expansion port. The SPI master controller supports the clock rates of 0.25, 0.5, 1,
2, 4, 6, 8, 10, and 12MHz. It supports two options of clock polarity (CPOL) and two options of initial
clock phase (CPHA). SPI pins are multiplexed with I2S pins.
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Table 2-17. SPI Pin Description
Signal Name
Signal Description
Direction
CS
Chip select
Output
SCK
Serial clock
Output
MISO
Master in, Slave out
Input
MOSI
Master out, Slave in
Output
CS_N
idle time
Data Transmission
CS_N
CS_N setup time
CS_N hold time
SCK
(CPOL=0)
SCK Edge
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
(CPOL=1)
SAMPLE MOSI/MISO
(CPHA=0)
SAMPLE MOSI/MISO
(CPHA=1)
Figure 2-19. SPI Timing Diagram
2.5.6
SPI Slave Interface
The simple SPI slave module translates 16bits SPI serial protocol to create AHB master transaction
for accessing SYSRAM or configuration registers.
The block diagram shows SPI slave controller, spis_top, was integrated in the CM4 system. SPI Host
can write data into CM4 SYSRAM by controlling slave controller.
SPI slave controller supports interrupt to CM4 system. SPI host can configure register in slave
controller to interrupt CM4 MCU. When CM4 MCU gets the interrupt, it can read status from SPI
slave controller and clear the interrupt. Also, it can read data from SYSRAM.
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CM4_SYS
AHB BUS
spis_top
spis2ahb_top
SPIS_IRQ
spi_ck / spi_cs
spi_mosi / spi_miso
spis2ahb_spi
spitoahb_start
reg00
reg02
reg03
Intf_busy
reg01
SPI clock domain
CIRQ
SYSRAM
spis2ahb_ahbif
system clock domain
CM4
MCU
Reg00~06
spis_ahbslv_adr_if
Figure 2-20. SPI Slave Block Diagram
SPI slave uses SPI2AHB protocol. In AHB write transaction, it should write AHB 32bits data and 32bits
address into spi controller register first, and then kick the AHB_cmd to start AHB write transaction.
After start AHB_cmd, 32bits data will be written into specified 32bits address. In AHB read
transaction, it should write 32bits address into spi controller register first, and then kick the
AHB_cmd to start AHB read transaction. After start AHB_cmd, 32 bits data will be read from
specified 32bits address and stored in spi slave controller.
2.5.7
I2S Interface
MT7687F features one I2S interface, which is used to connect to an external audio codec. The I2S
interface can support the I2S slave mode only. The five I2S signals are shown below. The I2S_MLK
clock frequency is 16MHz.
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Table 2-18. I2S Pin Description
Signal Name
Signal Description
Direction (Slave Mode)
I2S_MCLK
The base clock of the function.
Output
I2S_BCLK
The bit clock of the interface
Input
I2S_FS (LRCLK)
The left/right word select line
Input
of the interface
I2S_TX
Digital audio output
Output
I2S_RX
Digital audio input
Input
MT7687F supplies the MCLK of 16MHz. The external CODEC generates BCLK and LRCLK from MCLK.
When configured as the I2S slave mode, the I2S interface can support two modes.
Table 2-19. I2S Slave Mode
Slave Mode
Bit Width
Input Sample (Uplink)
BCLK
(Input)
512KHz
FS (Input)
16KHz, mono
Output Sample
(Downlink)
16KHz, mono
Mode 1
16b
Mode 2
16b
24KHz, mono
24KHz, mono
768KHz
24KHz
16KHz
The mono data is transferred across the I2S bus as left channel information.
In all of the modes above, when the input data is mono, the data of interest is transferred across the
I2S bus on the left channel.
The I2S pins are multiplexed with SPI pins.
The signal waveform of I2S is shown below.
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1/SR
…
…
I2S_BCLK
I2S_FS
1T delay
R[0]
I2S_TX/RX
L[15]
L[14]
L[13]
…
L[1]
L[2]
L[0]
R[15]
R[14]
R[13]
…
R[2]
R[1]
R[0]
Right channel
Left channel
Figure 2-21. I2S Signal Waveform
2.5.8
Pulse Width Modulation (PWM)
MT7687F features 28 generic PWMs to generate pulse sequences with programmable frequency and
duration for LCD, vibrators, and other devices. The PMU features three configurable pattern options.
Table 2-20. PWM Modes
Mode
1
Description
Waveform
Basic PWM:
LED ON
LED OFF
LED ON
Time
LED OFF
Time
LED ON time (duration) and LED
OFF time (duration) are
configurable.
2
Two-State PWM:
There are two configurable states
S0
S0 Lastingtime
(S0 and S1) for PWM LED.
3
S1
Two-State replay mode:
replay
User can set replay mode with
specified S1_Lasting_Time. PWM
LED would act as
S0
[S0àS1àS0àS1àS0…] with
S0 Lastingtime
S1
S1 Lastingtime
S0
S0 Lastingtime
period time of (S0_Lasting_Time +
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Mode
Description
Waveform
S1_Lasting_Time)
2.5.9
IrDA
IrDA TX module supports consumer IR protocols including NEC, RC-5, RC-6, and the software-based
pulse-width mode. IrDA RX module supports protocols including RC-5 and pulse-width detection
mode.
2.6
Radio MCU Subsystem
2.6.1
CPU
MT7687F features 32-bit CPU N9, with the following features:








2.6.2
5-stage pipeline with extensive clock-gating
Dynamic branch prediction with BTB
16/32-bit mixed instruction format
Multiply-accumulate and multiply-subtract instructions
Instructions optimized for audio applications
Instruction and data local memory
JTAG based debug interface
Programmable data endian control
RAM/ROM
The Radio MCU subsystem features ILM (Instruction Local Memory), DLM (Data Local Memory), and
the SYSRAM. The ROM code is in ILM.
2.6.3
Memory map
The table below describes how the peripherals are mapped to the memory space in Radio MCU
subsystem.
When the MCU performs a read transaction to an undefined address, the bus returns 0. When the
MCU performs a write transaction to an undefined address, the bus regards it as an invalid
transaction and does nothing.
Table 2-21. N9 Memory Map
Start address
0x0000_0000
End address
0x000C_FFFF
Function
ILM ROM
0x000D_0000
0x0011_FFFF
ILM RAM
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Description
Instruction local memory ROM
for N9
Instruction local memory RAM
for N9
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Start address
0x0200_0000
0x0209_0000
0x0040_0000
0x2000_0000
0x2100_0000
0x2200_0000
0x2400_0000
0x3000_0000
End address
0x0200_021C
0x020C_1FFF
0x0040_CFFF
0x2003_FFFF
0x2100_FFFF
0x2200_FFFF
0x2400_FFFF
0x3FFF_FFFF
Function
Patch & CR
DLM RAM
SYSRAM N9
SYSRAM CM4
SPI-S
I2S/Audio
(Reserved)
Serial Flash CM4
Description
N9 ROM patch engine
Data local memory for N9
System RAM for N9
System RAM for CM4 (256KB)
SPI slave
I2S
0x5000_0000
0x501F_FFFF
HIF_device
Host interface device controller
0x5020_0000
0x502F_FFFF
HIF_host_CM4
0x6000_0000
0x7000_0000
0x6FFF_FFFF
0x70FF_FFFF
WIFISYS
PDA DMA port
0x7800_0000
0x7800_0000
VFF access port0
0x7800_0100
0x7800_0100
VFF access port1
0x7900_0000
0x7900_FFFF
0x8000_0000
0x800C_FFFF
VFF_CM4 access
port
APB0
0x8000_0000
0x8001_0000
0x8002_0000
0x8000_FFFF
0x8001_FFFF
0x8002_FFFF
CONFG
DMA
TOP_CFG_OFF
Host interface host controller
of Wi-Fi radio
Wi-Fi subsystem
Patch Decryption Accelerator
DMA slave
Virtual FIFO access port 0 of N9
DMA
Virtual FIFO access port 1 of N9
DMA
Virtual FIFO access ports of
CM4 DMA
APB bridge 0 (synchronous to
N9)
N9 subsystem configuration
Generic DMA engine for N9
TOP_OFF(N9) power domain
chip level configuration (GPIO,
PINMUX, RF, PLL, CLK control)
0x8003_0000
0x8003_FFFF
UART
UART host interface for N9
0x8005_0000
0x8005_FFFF
UART_PTA
0x8008_0000
0x800A_0000
0x800B_0000
0x800C_0000
0x8008_FFFF
0x800A_FFFF
0x800B_FFFF
0x800C_FFFF
AHB_MON
UART_DSN
SEC
HIF
Inter-chip communication for
PTA
AHB bus monitor
UART for N9 debug
Secure boot configuration
Host interface configuration
0x8100_0000
0x810C_FFFF
APB1
0x8102_0000
0x8102_FFFF
TOP_CFG_AON
0x8103_0000
0x8103_FFFF
DBG_CIRQ
0x8104_0000
0x8104_FFFF
CIRQ
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Serial flash controller of CM4
APB bridge 1 (synchronous to
N9)
TOP_AON power domain chip
level configuration (RGU,
PINMUX, PMU, XTAL, CLK
control)
Debug interrupt controller for
N9
Interrupt controller for N9
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Start address
0x8105_8000
End address
0x8105_FFFF
Function
GPT
Description
General Purpose Timer for N9
0x8106_0000
0x8106_FFFF
PTA
Packet Traffic Arbitrator for WiFi coexistence
0x8107_0000
0x8108_0000
0x8109_0000
0x8107_FFFF
0x8108_FFFF
0x8109_FFFF
EFUSE
WDT
PDA
Efuse controller
Watchdog Timer for N9
Patch Decryption Accelerator
0x810A_0000
0x810C_0000
0x8300_0000
0x810A_FFFF
0x810C_FFFF
0x810C_FFFF
RDD
RBIST
APB2
0x8300_0000
0x8300_FFFF
CONFG_CM4
Wi-Fi debug
RF BIST configuration
APB bridge 1 (synchronous to
CM4)
System configuration for CM4
0x8301_0000
0x8301_FFFF
DMA_CM4
Generic DMA engine for CM4
0x8302_0000
0x8303_0000
0x8304_0000
0x8305_0000
0x8302_FFFF
0x8303_FFFF
0x8304_FFFF
0x8305_FFFF
UART_DSN
UART1
UART2
GPT_CM4
0x8306_0000
0x8307_0000
0x8308_0000
0x8309_0000
0x830A_0000
0x830B_0000
0x830D_0000
0x830F_0000
0xA000_0000
0x8306_FFFF
0x8307_FFFF
0x8308_FFFF
0x8309_FFFF
0x830A_FFFF
0x830B_FFFF
0x830D_FFFF
0x830F_FFFF
0xAFFF_FFFF
IrDA
Serial flash
WDT_CM4
I2C_1
I2C_2
I2S
AUXADC
Crypto
PSE
UART for CM4 debug
UART 1 for CM4
UART 2 for CM4
General Purpose Timer for
CM4
IrDA
Serial flash macro access
Watchdog Timer for CM4
I2C 1
I2C 2
I2S configuration
Auxiliary ADC configuration
Crypto engine
Packet switch engine memory
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2.6.4
N9 Bus Fabric
CM4
SYSTEM BUS
Generic DMA
Asyncrhrous AHB-2AHB bridge
(CM4 bus to N9 bus)
Command Batch
(low power data
retention)
ILM ROM (832KB)
ILM RAM (320KB)
DLM RAM (200KB)
N9
N9 AHB bus
Asyncrhrous AHB-2AHB bridge
(N9 bus to CM4 bus)
APB
bridge
WiFi HIF
PSE
APB
bridge
SYSRAM_N9
(52KB)
WIFI MAC
CM4 AHB bus
WIFI Baseband
WIFI RF
APB1 bus
GPT
PTA
CIRQ
RDD
APB0 bus
PDA
GDMA
CONFIG
WDT
EFUSE
MAC
HIF
CONFIG
UART_D
SN
ACCLR
UART_P
TA
UART
TOP
CONFIG
N9
CONFIG
Interface to CM4 bus/peripheral
N9 peripheral
Figure 2-22. N9 Bus Fabric
Functional description:







Command batch: Used to save/restore the critical CR and memory data when entering
and leaving the low power mode.
Wi-Fi HIF: The host control and data interface from N9 to Wi-Fi subsystem.
Wi-Fi PSE: The Packet switch engine used to transfer packet from N9 to Wi-Fi MAC/Radio
or from CM4 to Wi-Fi MAC/Radio, and vice versa.
PDA: Packet Decryption Agent, used to download firmware and decipher the firmware
which is encrypted to avoid eavesdrop.
PTA: Packet Traffic Arbitration, used to do the traffic arbitration of Wi-Fi when the two
radios are transmitting and receiving at the same time.
RDD: The Wi-Fi debug function.
EFUSE: The Efuse macro used for the configuration of Wi-Fi MAC and Radio.
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2.6.5
CIRQ
N9 subsystem uses the interrupt controller CIRQ to control the source selection, mask, edge/level
sensitivity, and software enabling for internal interrupts, as well as the mask and the edge/level
sensitivity for external interrupts.
CIRQ also integrates the de-bounce circuit for external interrupts.
FIQ control
De-bounce
External
interrupt
control
De-bounce
Interrupt
select
IRQ contro
De-bounce
Control register
Figure 2-23. N9 interrupt controller
2.6.5.1
Interrupt sources
The tables below lists the interrupt sources of internal and external interrupts.
There are totally 23 interrupts and 14 external interrupts.
The power domain/subsystem lists the power domain and the subsystem from which the interrupt is
generated.
Interrupt
source
Power domain
/subsystem
INT0
UART
TOP_OFF(N9)/MCUSY
S
UART module
INT1
DMA
TOP_OFF(N9)/MCUSY
S
Generic DMA in N9 subsystem
HIFSYS
TOP_AON/HIF
WIFI_HIF(SDIO)
TOP_OFF(N9)
Thermometer
INT2
INT3
Debounce
Description
(Reserved)
INT4
THERM
INT5
(Reserved)
INT6
WIFI
WF_OFF
ICAP
TOP_OFF(N9)/MCUSY
S
INT7
External
interrupt
Wake-up
capability
(1)
IRQ
No.
Wi-Fi subsystem
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Internal capture in RBIST module
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IRQ
No.
Power domain
/subsystem
INT8
EINT
TOP_AON/MCUSYS
External interrupt
INT9
(Reserved)
INT10
WDT_N9
TOP_AON/MCUSYS
Watch dog timer in N9 subsystem
INT11
AHB_MONITOR
TOP_OFF(N9)/MCUSY
S
AHB monitor
INT12
(Reserved)
INT13
PLC_ACCLR
TOP_OFF(N9)/MCUSY
S
Packet Loss Concealment accelerator
INT14
(Reserved)
INT15
PSE
INT16
(Reserved)
INT17
External
interrupt
Wake-up
capability
(1)
Interrupt
source
Debounce
WF_OFF/PSE
Description
Packet switch engine
HIFSYS
TOP_OFF(N9)/HIFSYS
HIF subsystem
INT18
UART_PTA *
TOP_OFF(N9)/MCUSY
S
UART_PTA module
INT19
PTA *
TOP_OFF(N9)/MCUSY
S
PTA module
INT20
CMBT
TOP_OFF(N9)
INT21
GPT3
TOP_AON/MCUSYS
WDT_CM4
TOP_AON/MCUSYS_C
M4
EINT0
UART_RX
TOP_AON
EINT1
(Reserved)
INT22
EINT2
HIFSYS
TOP_AON/HIF
EINT3
CM4_TO_N9_S
W
TOP_AON/MCUSYS_C
M4
EINT4
(Reserved)
EINT5
PCIE *
TOP_OFF(N9)/HIFSYS
Command batch module
General purpose timer module
CM4 WDT interrupt N9
V
V
Available
V
V
Available
Wake up from UART
V
V
Available
WIFI_HIF (SDIO)
CM4 SW interrupt N9
83080080[31:30] SW_INT
V
V
Available
V
V
Available
V
V
Available
Wake up from PCIe
EINT6
GPT
TOP_AON/MCUSYS
V
V
Available
General purpose timer module (GPT0
timer and GPT1 timer)
EINT7
External interrupt
TOP_AON
V
V
Available
External interrupt
Pin: GPIO58
EINT8
External interrupt
TOP_AON
V
V
Available
External interrupt
Pin: GPIO57
EINT9
External interrupt
TOP_AON
V
V
Available
External interrupt
Pin: GPIO30
EINT10
(Reserved)
V
V
Available
EINT11
External interrupt
TOP_AON
V
V
Available
External interrupt
Pin: GPIO38
EINT12
External interrupt
TOP_AON
V
V
Available
External interrupt
Pin: GPIO39
EINT13
(Reserved)
V
V
Available
*: Not used for MT7687F
Note 1; Capable to wake up N9 when N9 is in sleep mode.
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MT7687F
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2.7
Wi-Fi Subsystem
2.7.1
Wi-Fi MAC
MT7687F MAC supports the following features:














2.7.2
Supports all data rates of 802.11g including 6, 9, 12, 18, 24, 36, 48, and 54Mbps
Supports short GI and all data rates of 802.11n including MCS0 to MCS7
802.11 to 802.3 header translation offload
RX TCP/UDP/IP checksum offload
Supports multiple concurrent clients as an access point
Supports multiple concurrent clients as a repeater
Aggregate MPDU RX (de-aggregation) and TX (aggregation) support
Transmits beamforming as a beamformee
Transmits rate adaptation
Transmits power control
Security
64-bit WEP (WEP-40) and 128-bit WEP (WEP-104) encryption with hardware TKIP and
CKIP processing
AES-CCMP hardware processing
SMS4-WPI (WAPI) hardware processing
WLAN Baseband
MT7687F baseband supports the following features:







2.7.3
20 and 40MHz channels
MCS0-7 (BPSK, r=1/2 through 64QAM, r=5/6)
Short Guard Interval
STBC support
Low Density Parity check (LDPC) coding
Support digital pre-distortion to enhance PA performance
Smoothing (channel estimation) extension to MIMO case
WLAN RF
MT7687F RF supports the following features:




2.8
Integrated 2.4GHzPA and LNA, and T/R switch
Support frequency band
2400-2497MHz
Support RX antenna diversity for both 2.4GHz band to eliminate the requirement of an
external SPDT
RTC
MT7687F features one RTC (Real Time Clock) module. The clock source is the 32.768 KHz Crystal or
an external clock source. RTC has built in an accurate timer to wake up the system when it expires.
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RTC uses a different power rail from PMU. In the hibernate mode, the PMU is turned off while the
RTC module is remained powered on. The RTC module only consumes 3uA in hibernate mode.
RTC has a dedicated PMU control pin PMU_EN_RTC (pin 23) used to turn on the power to the chip
when the RTC timer expires and turn off the power to the chip when it intends to enter the hibernate
mode.
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3
Radio Characteristics
3.1
Wi-Fi Radio Characteristics
3.1.1
Wi-Fi RF Block Diagram
Note:
M
n
lu
a C
B L
L
-C
BBPLL
BG
RFDIG
ADC
WF0_G_RFION
M
ISM TRX
M
TRSW
WF0_G_RFIOP
BW20/40IF_
LPF
Antenna port
RC-cal
R-cal
SX0
(3~4GHz)
Front-end loss with external Balun (2.4GHz band): 2.4GHz band insertion loss is 2dB.
WF0_RXG_AUX_IN
is matching circuits for 50ohm impedance tuning.
Figure 3-1. 2.4GHz RF Block Diagram
3.1.2
Wi-Fi 2.4GHz Band RF Receiver Specifications
The specifications noted in the table below is measured at the antenna port, which includes the
front-end loss.
Table 3-1. 2.4GHz RF Receiver Specification
Parameter
Description
Performance
MIN
TYP
MAX
Unit
2484
MHz
Frequency range
Center channel frequency
2412
RX sensitivity
1 Mbps CCK
-
-96.4
-
dBm
2 Mbps CCK
-
-93.4
-
dBm
5.5 Mbps CCK
-
-91.4
-
dBm
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MT7687F
Internet-of-Things Wireless Connectivity
Parameter
Description
Performance
MIN
TYP
MAX
Unit
11 Mbps CCK
-
-88.4
-
dBm
BPSK rate 1/2, 6 Mbps OFDM
-
-93.4
-
dBm
BPSK rate 3/4, 9 Mbps OFDM
-
-91.1
-
dBm
QPSK rate 1/2, 12 Mbps OFDM
-
-90.3
-
dBm
QPSK rate 3/4, 18 Mbps OFDM
-
-87.9
-
dBm
16QAM rate 1/2, 24 Mbps OFDM
-
-84.6
-
dBm
16QAM rate 3/4, 36 Mbps OFDM
-
-81.2
-
dBm
64QAM rate 1/2, 48 Mbps OFDM
-
-77.0
-
dBm
64QAM rate 3/4, 54 Mbps OFDM
-
-75.7
-
dBm
RX Sensitivity
MCS 0, BPSK rate 1/2
-
-92.7
-
dBm
BW=20MHz
MCS 1, QPSK rate 1/2
-
-89.5
-
dBm
Mixed mode
MCS 2, QPSK rate 3/4
-
-87.1
-
dBm
800ns Guard
Interval
MCS 3, 16QAM rate 1/2
-
-84.1
-
dBm
MCS 4, 16QAM rate 3/4
-
-80.6
-
dBm
MCS 5, 64QAM rate 2/3
-
-76.2
-
dBm
MCS 6, 64QAM rate 3/4
-
-74.8
-
dBm
MCS 7, 64QAM rate 5/6
-
-73.6
-
dBm
RX Sensitivity
MCS 0, BPSK rate 1/2
-
-89.6
-
dBm
BW=40MHz
MCS 1, QPSK rate 1/2
-
-86.8
-
dBm
Mixed mode
MCS 2, QPSK rate 3/4
-
-84.3
-
dBm
800ns Guard
Interval
MCS 3, 16QAM rate 1/2
-
-80.8
-
dBm
MCS 4, 16QAM rate 3/4
-
-77.7
-
dBm
MCS 5, 64QAM rate 2/3
-
-73.1
-
dBm
MCS 6, 64QAM rate 3/4
-
-71.8
-
dBm
MCS 7, 64QAM rate 5/6
-
-70.6
-
dBm
6 Mbps OFDM
-
-10
-
dBm
54 Mbps OFDM
-
-10
-
dBm
MCS0
-
-10
-
dBm
MCS7
-
-20
-
dBm
1 Mbps CCK
-
40
-
dBm
RX sensitivity
Non-STBC
Non-STBC
Maximum Receive
Level
Receive Adjacent
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MT7687F
Internet-of-Things Wireless Connectivity
Parameter
Description
Channel Rejection
3.1.3
Performance
MIN
TYP
MAX
Unit
11 Mbps CCK
-
40
-
dBm
BPSK rate 1/2, 6 Mbps OFDM
-
34
-
dBm
64QAM rate 3/4, 54 Mbps OFDM
-
22
-
dBm
HT20, MCS 0, BPSK rate 1/2
-
33
-
dBm
HT20, MCS 7, 64QAM rate 5/6
-
15
-
dBm
HT40, MCS 0, BPSK rate 1/2
-
29
-
dBm
HT40, MCS 7, 64QAM rate 5/6
-
9
-
dBm
Wi-Fi 2.4GHz Band RF Transmitter Specifications
The specifications in table are measured at the antenna port, which includes the front-end loss.
Table 3-2. 2.4GHz RF Transmitter Specifications
Parameter
Description
Performance
MIN
TYP
MAX
Unit
2412
-
2484
MHz
1 Mbps CCK
-
21
-
dBm
11 Mbps CCK
-
21
-
dBm
6 Mbps OFDM
-
19
-
dBm
54 Mbps OFDM
-
18
-
dBm
HT20, MCS 0
-
18
-
dBm
HT20, MCS 7
-
17.5
-
dBm
HT40, MCS 0
-
17
-
dBm
HT40, MCS 7
-
16.5
-
dBm
6 Mbps OFDM
-
-
-5
dB
54 Mbps OFDM
-
-
-25
dB
HT20, MCS 0
-
-
-5
dB
HT20, MCS 7
-
-
-28
dB
HT40, MCS 0
-
-
-5
dB
HT40, MCS 7
-
-
-28
dB
TSSI closed-loop control across all temperature
range and channels and VSWR ≦ 1.5:1.
-1.5
-
1.5
dB
Frequency range
Output power with
spectral mask and
EVM compliance
TX EVM
Output power
variation(1)
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MT7687F
Internet-of-Things Wireless Connectivity
Parameter
Description
Performance
MIN
TYP
MAX
Unit
-
-
-30
dBc
2nd Harmonic
-
-45
-43
dBm/MHz
3nd Harmonic
-
-45
-43
dBm/MHz
Carrier suppression
Harmonic Output
Power
Note 1: VDD33 voltage is within ±5% of typical value.
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MT7687F
Internet-of-Things Wireless Connectivity
4
Electrical Characteristics
4.1
Absolute Maximum Rating
Table 4-1 Absolute Maximum Rating
Symbol
Parameters
Maximum rating
Unit
VDD33
3.3V Supply Voltage
-0.3 to 3.63
V
TSTG
Storage Temperature
-40 to +125
°C
VESD
ESD protection (HBM)
2000
V
4.2
Recommended Operating Range
Table 4-2. Recommended Operating Range
Symbol
Supply Voltage
Source
Min
Typ
Max
Unit
3.3
3.63
V
3.63
V
V
AVDD45
AVDD45_BUCK, AVDD45_MISC
To be connected to external 3.3V supply
2.97
RTC_3V3
AVDD33
RTC_3V3
To be connected to external supply
1.6
To be connected to external 3.3V supply
2.97
3.3
3.63
DVDDIO
AVDD25
AVDD16
DVDD11
Ta
Tj
AVDD33_WF0_G_PA,
AVDD33_WF0_G_TX, AVDD33
DVDDIO_D, DVDDIO_L,
DVDDIO_R
To be connected to PMU_DIO33_OUT
2.97
3.3
3.63
AVDD25_AUXADC
AVDD16_CLDO, AVDD16,
AVDD16_XO, AVDD16_WF0_AFE
To be connected to PMU ALDO output
To be connected to PMU BUCK output
2.3
1.6
2.5
1.7
2.7
1.8
DVDD11
Operating Ambient Temperature
To be connected to PMU CLDO output
0.86
MT7687FN
MT7687FIN
V
Operating Junction Temperature
4.3
V
1.15
1.3
V
-30
85
C
-40
85
C
MT7687FN
-30
125
C
MT7687FIN
-40
125
C
DC Characteristics
Table 4-3. DC Characteristics
Symbol
Parameter
Conditions
MIN
MAX
Unit
VIL
Input Low Voltage
LVTTL
-0.28
0.8
V
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MT7687F
Internet-of-Things Wireless Connectivity
Symbol
Parameter
Conditions
MIN
MAX
Unit
VIH
Input High Voltage
2
3.63
V
VOL
VOH
Output Low Voltage
Output High Voltage
|IOL| = 4~16 mA
|IOH| = 4~16 mA
-0.28
2.4
0.4
VDD33+0.33
V
V
RPU
Input Pull-Up Resistance
PU=high, PD=low
40
190
KΩ
RPD
Input Pull-Down Resistance
PU=low, PD=high
40
190
KΩ
4.4
XTAL Oscillator
The table below lists the XTAL requirements for the XTAL.
Table 4-4. XTAL Oscillator Requirements
4.5
Parameter
Value
Frequency
26, 40, 52MHz.
Frequency stability
±10 ppm @ 25℃
Aging
±3 ppm/year
PMU Characteristics
Table 4-5. PMU Electrical Characteristics
Parameter
Reference
Conditions
Min
Typ
Max
Unit
2.97
3.3
3.63
V
1.6
1.7
1.8
V
Switching regulator (BUCK)
Vin
Vout
Input Voltage
Output Voltage
Iout
Output Current
AVDD45_BUCK
LXBK
Switching operation
Deep Sleep mode, SLDO-H
enabled
Switching operation
Deep Sleep mode, SLDO-H
enabled
Over-current shutdown
1.8
960
1600
V
800
mA
10
4000
mA
mA
.
Iq
DC/DC
Quiescent
Current
Iload < 1mA
Line Regulation
Iload = 0mA
Load regulation
Iload = 200-400mA
Efficiency
Vin = 3.3V, Iload = 400mA
150
80
85
1.6
1.7
uA
1
%
0.05
mV/mA
%
Core LDO (CLDO)
Vin
Input
AVDD16_CLDO
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V
MT7687F
Internet-of-Things Wireless Connectivity
Vout
Parameter
Output Voltage
Iout
Output Current
Iq
Quiescent
Current
Reference
AVDD12_VCORE
Conditions
Normal operation
Deep Sleep mode, SLDO-L
enabled
Output Voltage
Typ
Max
Unit
1.15
1.3
V
0.85
AVDD25_ALDO
420
mA
10
mA
40
50
uA
2.97
3.3
3.63
V
2.3
2.5
2.7
V
Normal operation
Deep Sleep mode, OFF
Iout
Iq
Output Current
Quiescent
Current
PMU
Vin
Input Voltage
Iq
Quiescent
Current
4.6
V
Normal operation
Deep Sleep mode, SLDO-L
enabled
Analog LDO (ALDO)
Vin
Input Voltage
Vout
Min
0.86
0
V
Normal operation
2.97
AVDD45, AVDD33
and DVDDIO
50
mA
25
50
uA
3.3
3.63
V
50
uA
In Deep Sleep State
Auxiliary ADC Characteristics
This section specifies the electrical characteristics of the auxiliary ADC.
Table 4-6. Auxiliary ADC Specifications
Symbol
Parameter
Min
Typical
Max
Unit
N
Resolution
-
12
-
Bit
FS
Sampling Rate @ N-Bit(1)
-
2
-
MSPS
VPP
Input Swing(2)
-
-
AVDD25
(2.45~2. V
55V)
VIN
Input voltage
0
-
AVDD25
(2.45~2. V
55V)
RIN
Input Impedance:
Unselected channel
Selected channel
400M
-
10K
-
Ohm
DNL
Differential Nonlinearity without dithering and
averaging
-
±1
±2
LSB
(3)
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MT7687F
Internet-of-Things Wireless Connectivity
Symbol
Parameter
INL
Min
Typical
Max
Unit
Integral Nonlinearity without dithering and averaging -
±2
±4
LSB
DNLdither+average
Differential Nonlinearity with dithering and
averaging
-
± 0.5
±1
LSB
INLdither+average
Integral Nonlinearity with dithering and averaging
-
-
±2
LSB
OE
Offset Error
-
-
± 10
mV
FSE
Full Swing Error
-
-
± 50
mV
SNR
Signal to Noise Ratio(2)
60
63
66
dB
Current Consumption
-
-
400
μA
Power-Down Current
Note 1: Given that FS=2MHz
-
-
1
μA
Note 2: At 1K Hz Input Frequency
Note 3: The voltage level is lowered by 0.04V when dithering is on.
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MT7687F
Internet-of-Things Wireless Connectivity
4.7
Thermal Characteristics
ΘJC assumes that all the heat is dissipated through the top of the package, while ΨJt assumes that the
heat is dissipated through the top, sides, and the bottom of the package. Thus it is suggested to use
ΨJt to estimate the junction temperature.
Table 4-7. Thermal Characteristics
Performance
Symbol Description
Typical
Unit
TJ
Maximum Junction Temperature (Plastic Package)
125
°C
ΘJA
Junction to ambient temperature thermal resistance[1]
19.21
°C/W
ΘJC
Junction to case temperature thermal resistance
7.33
°C/W
ΨJt
Junction to the package thermal resistance[2]
1.65
°C/W
Note 1: JEDEC 51-7 system FR4 PCB size: 76.2mm x 114.3mm
Note 2: 8mm x 8mm QFN-68 package
4.8
Power Performance Summary
Table 4-8 lists the current consumptions in VBAT domain. Note that the measurement conditions are
typical conditions for process, voltage (3.3v) and temperature (25°C).
Table 4-8. Current consumption in different scenarios
Scenario
Test Conditions
Legacy Sleep
•
•
•
MCU subsystem clocks are gated off
0.667
mA
•
•
•
Only 32KHz clock from XTAL is
active
System Off
0.0031
mA
Only RTC is alive
WFI Sleep mode[1]
10.79
mA
0.97
mA
14.18
mA
RTC mode[1]
WIFI Radio Off
•
•
•
•
WIFI Connected
•
•
Typical
Unit
The entire subsystem is retained
No SRAM retained
Tickless feature enabled
Legacy Sleep mode[1]
Tickless feature enabled
WFI Sleep mode
Tickless feature enabled
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MT7687F
Internet-of-Things Wireless Connectivity
Scenario
Test Conditions
•
•
•
•
•
•
•
Typical
Unit
DTIM1[2]
Legacy Sleep mode
4.64
mA
DTIM1[2]
Legacy Sleep mode
2.07
mA
Tickless feature enabled
Tickless feature enabled
DTIM10[2]
Note 1: Please refer to LinkIt_for_RTOS_Power_Mode_Developers_Guide.pdf chapter 3.1 for power
modes
Note 2: DTIM, A delivery traffic indication map is a kind of traffic indication map (TIM) which informs
the clients about the presence of buffered multicast/broadcast data on the access point. It is
generated within the periodic beacon at a frequency specified by the DTIM Interval
DTIM 1: DTIM interval = 1, WIFI wake up each beacon period (default 100 ms)
DTIM 10: DTIM interval = 10, WIFI wake up every 10 beacon period (1000ms)
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MT7687F
Internet-of-Things Wireless Connectivity
5
5.1
Package Specifications
Pin Layout
MT7687F uses 8mm x 8mm QFN package of 68-pin with 0.4mm pitch.
1
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
NC
AVDD33
NC
AVDD33_WF0_G_TX
WF0_G_RFIOP
WF0_G_RFION
AVDD33_WF0_G_PA
WF0_RXG_AUX_IN
AVDD16
AVDD33
NC
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
Table 5-1. Pin Map
AVDD33
2 AVDD16_WF0_AFE
SYSRST_B
51
GPIO39
50
3
AVDD16_XO
DVDD11
49
4
XO
DVDDIO_L
48
5
GPIO0
GPIO57
47
6
GPIO1
GPIO58
46
7
GPIO2
GPIO59
45
8
GPIO3
GPIO60
44
9
GPIO4
10
GPIO5
11
GPIO6
AVSS45_BUCK
41
12
GPIO7
LXBK
40
13
DVDDIO_R
AVDD45_BUCK
39
14
DVDD11
15
GPIO24
16
DVDDIO_D
17
DVDD11
VSS
AVDD25_AUXADC 43
AVSS25_AUXADC 42
AVDD15_V2P5NA 38
AVDD16_CLDO
37
AVDD12_VCORE 36
GPIO25
GPIO26
RTC_3V3
RTC_32K_XO
RTC_32K_XI
PMU_EN_RTC
GPIO32
GPIO31
GPIO27
GPIO30
GPIO28
GPIO29
PMU_DIO33_OUT
AVDD25_ALDO_OUT
PMU_EN_WF
ISO_INT_PMU_EN
AVDD45_MISC
PMU_TEST
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
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35
MT7687F
Internet-of-Things Wireless Connectivity
5.2
Pin Description
The section describes the pin functionality of MT7687F chip.
Table 5-2. Pin Descriptions
QFN
Pin Name
Pin description
PU/PD I/O
Supply domain
Reset and Clocks
51
SYSRST_B
External system reset active low
PU
Input
DVDDIO
4
XO
Crystal input or external clock input
N/A
Input
AVDD16_XO
3
AVDD16_XO
RF 1.6V power supply
N/A
Power
Programmable I/O
5
GPIO0
Programmable input/output
PU/PD In/out
DVDDIO
6
GPIO1
Programmable input/output
PU/PD In/out
DVDDIO
7
GPIO2
Programmable input/output
PU/PD In/out
DVDDIO
8
GPIO3
Programmable input/output
PU/PD In/out
DVDDIO
9
GPIO4
Programmable input/output
PU/PD In/out
DVDDIO
10
GPIO5
Programmable input/output
PU/PD In/out
DVDDIO
11
GPIO6
Programmable input/output
PU/PD In/out
DVDDIO
12
GPIO7
Programmable input/output
PU/PD In/out
DVDDIO
15
GPIO24
Programmable input/output
PU/PD In/out
DVDDIO
18
GPIO25
Programmable input/output
PU/PD In/out
DVDDIO
19
GPIO26
Programmable input/output
PU/PD In/out
DVDDIO
26
GPIO27
Programmable input/output
PU/PD In/out
DVDDIO
28
GPIO28
Programmable input/output
PU/PD In/out
DVDDIO
29
GPIO29
Programmable input/output
PU/PD In/out
DVDDIO
27
GPIO30
Programmable input/output
PU/PD In/out
DVDDIO
25
GPIO31
Programmable input/output
PU/PD In/out
DVDDIO
24
GPIO32
Programmable input/output
PU/PD In/out
DVDDIO
57
GPIO33
Programmable input/output
PU/PD In/out
DVDDIO
56
GPIO34
Programmable input/output
PU/PD In/out
DVDDIO
55
GPIO35
Programmable input/output
PU/PD In/out
DVDDIO
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MT7687F
Internet-of-Things Wireless Connectivity
QFN
Pin Name
Pin description
PU/PD I/O
Supply domain
54
GPIO36
Programmable input/output
PU/PD In/out
DVDDIO
53
GPIO37
Programmable input/output
PU/PD In/out
DVDDIO
52
GPIO38
Programmable input/output
PU/PD In/out
DVDDIO
50
GPIO39
Programmable input/output
PU/PD In/out
DVDDIO
47
GPIO57
Programmable input/output
PU/PD In/out
DVDDIO
46
GPIO58
Programmable input/output
PU/PD In/out
DVDDIO
45
GPIO59
Programmable input/output
PU/PD In/out
DVDDIO
44
GPIO60
Programmable input/output
PU/PD In/out
DVDDIO
20
VRTC
RTC domain power supply
N/A
Power
21
RTC_32K_XO
32KHz crystal
N/A
Analog
VRTC
22
RTC_32K_XI
32KHz crystal
N/A
Analog
VRTC
23
PMU_EN_RTC
PMU enable
N/A
Output
VRTC
RTC
WIFI Radio Interface
1,59,
67
AVDD33
RF 3.3v power supply
N/A
Power
62
AVDD33_WF0_G_PA
RF 3.3v power supply
N/A
Power
65
AVDD33_WF0_G_TX
RF 3.3v power supply
N/A
Power
2
AVDD16_WF0_AFE
RF 1.6v power supply
N/A
Power
58,
NC
66,68
No Connected
N/A
Input
61
WF0_RXG_AUX_IN
RF g-band auxiliary RF LNA port
N/A
Input
AVDD33_WF0_G
64
WF0_G_RFIOP
RF g-band RF port
N/A
In/out
AVDD33_WF0_G
63
WF0_G_RFION
RF g-band RF port
N/A
In/out
AVDD33_WF0_G
60
AVDD16
RF 1.6v power supply
N/A
Power
PMU/BUCK
41
AVSS45_BUCK
BUCK ground
N/A
Ground
40
LXBK
BUCK output
N/A
Output
39
AVDD45_BUCK
BUCK power supply
N/A
Input
38
AVDD15_V2P5NA
BUCK internal circuit output cap
N/A
Output
37
AVDD16_CLDO
CLDO supply
N/A
Input
36
AVDD12_VCORE
CLDO output
N/A
Output
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MT7687F
Internet-of-Things Wireless Connectivity
QFN
Pin Name
Pin description
PU/PD I/O
34
AVDD45_MISC
PMU supply
N/A
Input
31
AVDD25_ALDO_OUT
2.5V ALDO output with external cap.
N/A
Output
N/A
Output
Supply domain
This pin output is to provide 3.3V for all
DVDDIO.
30
PMU_DIO33_OUT
And in OFF mode, this pin is 0V.
35
PMU_TEST
PMU test pin
N/A
Output
33
ISO_INT_PMU_EN
Input 0V for non-RTC platform.
Input 3.3V for RTC platform.
N/A
Input
32
PMU_EN_WF
External PMU enable
N/A
Input
Power Supplies
43
AVDD25_AUXADC
Auxiliary ADC 2.5v power supply
N/A
Power
42
AVSS25_AUXADC
Auxiliary ADC ground
N/A
Ground
13
DVDDIO_R
Digital 3.3V input
N/A
Power
16
DVDDIO_D
Digital 3.3V input
N/A
Power
DVDDIO_L
Digital 3.3V input
N/A
Power
14, 17, 30, 49 DVDD11
Digital 1.15V input
N/A
Power
E-PAD
Common Ground
N/A
Ground
48
5.3
VSS
Pin Multiplexing
The pin multiplexing could be controlled via the configuration register A (in TOP_AON domain) and
the configuration register B (in TOP_OFF/N9 domain). When configuration register A is set to 0, the
configuration register B determines the pin function. When configuration register A is not set to 0,
the configuration register A determines the pin function.
The default function of each pin is highlighted with blue background.
The driving strength of all pins is programmable: 4mA, 8mA, 12mA, and 16mA. The default setting
for all pins are 4mA.
Table 5-3. Pin Multiplexing
© 2016 - 2017 MediaTek Inc.
Page 70 of 78
This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).
Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
MT7687F
Internet-of-Things Wireless Connectivity
Pin
5
6
7
8
9
10
11
Pin alias
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
APGIO/
GPIO
AGPIO
AGPIO
AGPIO
AGPIO
GPIO
GPIO
GPIO
Name
Dir
Default
Default
dir
PU/PD
I
PD
Description
Pinx_pinmux_aon_sel
Address
Pinx_pinmux_off_sel
Value
Value
MCU_JTCK
I
N9 JTAG debug port
0
0
ANTSEL[0]
O
RF control
-
1
UART0_RTS_CM4
O
UART0 RTS (CM4)
7
GPIO_TOPOFF[0]
I/O
General purpose input output
GPIO_TOPAON[0]
O
General purpose input output
8
PWM[0]
I/O
Pulse-width-modulated output
9
EINT[0]
I
External interrupt
3
-
MCU_JTMS
I
N9 JTAG debug port
0
0
1
I
PD
0x8102_3020[3:0]
-
0x8002_5100[3:0]
(0x8102_3020[3:0]=0)
3
5
-
ANTSEL[1]
O
RF control
-
UART0_CTS_CM4
I
UART0 CTS (CM4)
7
GPIO_TOPOFF[1]
I/O
General purpose input output
GPIO_TOPAON[1]
I/O
General purpose input output
8
PWM[1]
O
Pulse-width-modulated output
9
EINT[1]
I
External interrupt
3
-
MCU_JTDI
I
N9 JTAG debug port
0
0
I
PD
0x8102_3020[7:4]
-
0x8002_5100[7:4]
(0x8102_3020[7:4]=0)
3
5
-
ANTSEL[2]
O
RF control
-
1
MCU_AICE_TMSC
I/O
N9 debug
-
2
UART0_RX_CM4
I
UART0 RX (CM4)
7
SWD_CLK
O
CM4 SWD debug port
GPIO_TOPOFF[2]
I/O
General purpose input output
-
GPIO_TOPAON[2]
I/O
General purpose input output
8
-
PWM[23]
O
Pulse-width-modulated output
9
-
WIC[0]
I
External interrupt
3
-
MCU_JTRST_B
I
N9 JTAG debug port
0
0
ANTSEL[3]
O
RF control
-
1
[Reserved]
I
[Reserved]
-
2
UART0_TX_CM4
O
UART0 TX (CM4)
7
SWD_DIO
I/O
CM4 SWD debug port
4
0x8002_5100[15:12]
4
GPIO_TOPOFF[3]
I/O
General purpose input output
-
(0x8102_3020[15:12]=0)
5
GPIO_TOPAON[3]
I/O
General purpose input output
8
-
PWM[24]
O
Pulse-width-modulated output
9
-
EINT[2]
I
External interrupt
3
-
PULSE_CNT
I
Pulse counter
2
-
MCU_DBGIN
I
N9 JTAG debug port
0
0
1
I
PD
I
PD
0x8102_3020[11:8]
0x8102_3020[15:12]
4
0x8002_5100[11:8]
(0x8102_3020[11:8]=0)
3
4
5
3
ANTSEL[4]
O
RF control
-
MCU_AICE_TCKC
I
N9 debug
-
SPI_DATA0_EXT *
I/O
External flash interface
7
0x8002_5100[19:16]
3
GPIO_TOPOFF[4]
I/O
General purpose input output
-
(0x8102_3020[19:16]=0)
5
GPIO_TOPAON[4]
I/O
General purpose input output
8
-
PWM[2]
O
Pulse-width-modulated output
9
-
EINT[3]
I
External interrupt
3
-
Debug monitor pin
0
0
[Debug flag]
O
O(Lo
w)
0x8102_3020[19:16]
-
ANTSEL[5]
O
RF control
-
SPI_DATA1_EXT *
O
External flash interface
7
0x8002_5100[23:20]
3
GPIO_TOPOFF[5]
I/O
-
(0x8102_3020[23:20]=0)
5
GPIO_TOPAON[5]
I/O
General purpose input output
8
-
PWM[3]
O
Pulse-width-modulated output
9
-
EINT[4]
I
External interrupt
3
MCU_DBGACKN
O
I
O
General purpose input output
N9 JTAG debug port
© 2016 - 2017 MediaTek Inc.
0x8102_3020[23:20]
0x8102_3020[27:24]
0
1
0x8002_5100[27:24]
Page 71 of 78
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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
0
MT7687F
Internet-of-Things Wireless Connectivity
Pin
12
Pin alias
GPIO7
APGIO/
GPIO
GPIO
Name
Dir
Default
Default
dir
PU/PD
GPIO
GPIO25
GPIO
RF control
-
O
SPI master chip select 1
7
3
GPIO_TOPOFF[6]
I/O
General purpose input output
-
5
GPIO_TOPAON[6]
I/O
General purpose input output
8
-
PWM[4]
O
Pulse-width-modulated output
9
-
EINT[5]
I
External interrupt
3
-
MCU_JTDO
O
N9 JTAG debug port
0
0
1
O(Lo
w)
26
28
GPIO26
GPIO27
GPIO28
GPIO
GPIO
GPIO
1
ANTSEL[7]
O
RF control
-
SPI_CS_0_M_CM4
O
SPI master chip select 0
6
SPI_CS_EXT *
O
External flash interface
GPIO_TOPOFF[7]
I/O
General purpose input output
-
General purpose input output
8
-
0x8102_3020[31:28]
7
2
0x8002_5100[31:28]
(0x8102_3020[31:28]=0)
3
5
PWM[5]
O
Pulse-width-modulated output
9
EINT[6]
I
External interrupt
3
-
[Reserved]
-
0
UART_DSN_TXD_N9
O
UART_DSN TX (N9)
-
1
SPI_MOSI_M_CM4
O
SPI master MOSI
6
2
SPI_DATA2_EXT *
I/O
External flash interface
7
I2C1_CLK
I/O
I2C1 CLK
4
0x8002_510C[3:0]
4
GPIO_TOPOFF[24]
I/O
General purpose input output
-
(0x8102_302C[2:0]=0)
5
GPIO_TOPAON[24]
I/O
General purpose input output
8
-
PWM[25]
O
Pulse width modulation
9
-
[Reserved]
I
[Reserved]
1
-
[Reserved]
O
[Reserved]
2
-
[Reserved]
-
0
I
PU
0x8102_302C[3:0]
3
SPI_MISO_M_CM4
I
SPI master MISO
-
2
SPI_DATA3_EXT *
I/O
External flash interface
7
3
I2C1_DATA
I/O
I2C1 DATA
4
GPIO_TOPOFF[25]
I/O
General purpose input output
-
0x8002_510C[7:4]
5
GPIO_TOPAON[25]
I/O
General purpose input output
8
(0x8102_302C[7:4]=0)
-
PWM[26]
O
Pulse width modulation
9
-
[Reserved]
I/O
Default: Low.
1
-
FRAME_SYNC *
I
3DD synchronization
2
-
WIC[1]
I
External interrupt
3
-
[Reserved]
-
0
2
O
PU
[Reserved]
19
(0x8102_3020[27:24]=0)
O
[Reserved]
18
Pinx_pinmux_off_sel
ANTSEL[6]
[Reserved]
GPIO24
Pinx_pinmux_aon_sel
SPI_CS_1_M_CM4
GPIO_TOPAON[7]
15
Description
0x8102_302C[7:4]
4
SPI_SCK_M_CM4
O
SPI master SCK
6
SPI_CLK_EXT *
O
External flash interface
7
I2S_TX
O
I2S TX
4
0x8002_510C[11:8]
4
GPIO_TOPOFF[26]
I/O
General purpose input output
-
(0x8102_302C[11:8]=0)
5
GPIO_TOPAON[26]
I/O
General purpose input output
8
-
PWM[27]
O
Pulse width modulation
9
-
[Reserved]
I/O
Default: Low.
1
-
SWD_DIO
I/O
CM4 SWD debug port
5
1
3
O
PU
0x8102_302C[11:8]
3
I2C0_CLK
O
I2C0 CLK
4
GPIO_TOPOFF[27]
I/O
General purpose input output
-
GPIO_TOPAON[27]
I/O
General purpose input output
8
0x8002_510C[15:12]
-
PWM[28]
O
Pulse width modulation
9
(0x8102_302C[15:12]=0)
-
[Reserved]
I
PULSE_CNT
I
0x8102_302C[15:12]
5
[Reserved]
1
-
I
Pulse counter input
2
-
WIC[2]
I
External interrupt
3
-
SWD_CLK
I
CM4 SWD debug port
5
1
SPI_INT_S_N9
O
SPI
I2C0_DATA
O
I2C0 DATA
© 2016 - 2017 MediaTek Inc.
0x8102_302C[19:16]
4
0x8002_510C[19:16]
(0x8102_302C[19:16]=0)
Page 72 of 78
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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
2
3
MT7687F
Internet-of-Things Wireless Connectivity
Pin
29
27
25
24
57
Pin alias
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
APGIO/
GPIO
GPIO
GPIO
GPIO
GPIO
AGPIO
Name
Dir
Default
Default
dir
PU/PD
Description
Pinx_pinmux_aon_sel
Pinx_pinmux_off_sel
GPIO_TOPOFF[28]
I/O
General purpose input output
0
5
GPIO_TOPAON[28]
I/O
General purpose input output
8
-
PWM[29]
O
Pulse width modulation
9
-
[Reserved]
I/O
[Reserved]
1
-
I2S_MCLK_S
O
I2S MCLK slave
-
0
SPI_MOSI_S_CM4
I
SPI slave MOSI (CM4)
6
1
SPI_MOSI_S_N9
I
SPI slave MOSI (N9)
-
2
SPI_MOSI_M_CM4
O
SPI master MOSI
7
3
[Reserved]
O
[Reserved]
4
GPIO_TOPOFF[29]
I/O
General purpose input output
GPIO_TOPAON[29]
I/O
General purpose input output
8
PWM[30]
O
Pulse width modulation
9
-
[Reserved]
I/O
[Reserved]
1
-
HOST_ACK
O
2
-
WIC[3]
I
External interrupt
3
-
[Reserved]
O
[Reserved]
5
0
SPI_MISO_S_CM4
O
SPI slave MISO (CM4)
6
1
SPI_MISO_S_N9
O
SPI slave MISO (N9)
0
2
SPI_MISO_M_CM4
I
SPI master MISO
7
I2S_FS
I
I2S slave FS
4
0x8002_5108[27:24]
4
GPIO_TOPOFF[30]
I/O
General purpose input output
0
(0x8102_302C[27:24]=0)
5
GPIO_TOPAON[30]
I/O
General purpose input output
8
-
PWM[31]
O
Pulse width modulation
9
-
[Reserved]
I/O
[Reserved]
1
-
HOST_EINT_B
I
I2S_TX
O
SPI_SCK_S_CM4
SPI_SCK_S_N9
I
I
I
0x8102_302C[23:20]
0x8102_302C[27:24]
-
0x8002_510C[23:20]
(0x8102_302C[23:20]=0)
4
5
-
3
2
-
I2S TX
5
0
I
SPI slave SCK (CM4)
6
1
I
SPI slave SCK (N9)
-
2
SPI_SCK_M
O
SPI master SCK
7
I2S_RX
I
I2S slave RX
GPIO_TOPOFF[31]
I/O
General purpose input output
-
GPIO_TOPAON[31]
I/O
General purpose input output
8
-
PWM[32]
O
Pulse width modulation
9
-
[Reserved]
I/O
[Reserved]
1
-
[Reserved]
O
[Reserved]
5
0
SPI_CS_0_S_CM4
I
SPI slave CS (CM4)
6
1
SPI_CS_0_S_N9
I
SPI slave CS (N9)
-
2
SPI_CS_0_M
O
SPI master CS
7
I2S_BCLK
I
I2S BCLK slave
4
0x8002_5110 [3:0]
4
GPIO_TOPOFF[32]
I/O
General purpose input output
-
(0x8102_3030[3:0]=0)
5
GPIO_TOPAON[32]
I/O
General purpose input output
8
-
PWM[33]
O
Pulse width modulation
9
-
[Reserved]
I/O
[Reserved]
1
-
WIC[4]
I
External interrupt
3
-
WIFI_INT_B
I/O
External interrupt
0
0
ALL_INT_B
I/O
External interrupt
-
1
SWD_DIO
I/O
CM4 SWD debug port
6
2
IR_TX
O
IrDA TX
7
ANTSEL[5]
O
RF control
GPIO_TOPOFF[33]
I/O
General purpose input output
-
GPIO_TOPAON[33]
I/O
General purpose input output
8
-
PWM[34]
O
Pulse width modulation
9
-
PULSE_CNT
I
Pulse counter
1
-
I
I
O
PU
© 2016 - 2017 MediaTek Inc.
0x8102_302C[31:28]
0x8102_3030[3:0]
0x8102_3030 [7:4]
4
4
0x8002_510C[31:28]
(0x8102_302C[31:28]=0)
3
4
5
3
0x8002_5110 [7:4]
(0x8102_3030 [7:4]=0)
Page 73 of 78
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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
3
4
5
MT7687F
Internet-of-Things Wireless Connectivity
Pin
56
55
Pin alias
GPIO34
GPIO35
APGIO/
GPIO
AGPIO
GPIO
Default
Default
dir
PU/PD
53
52
50
GPIO36
GPIO37
GPIO38
GPIO39
GPIO
GPIO
GPIO
GPIO
Pinx_pinmux_aon_sel
Pinx_pinmux_off_sel
Dir
WF_LED_B
O
LED output
2
WIC[5]
I
External interrupt
3
-
MISC_INT_B
I/O
External interrupt
0
0
ALL_INT_B
I/O
-
1
SWD_CLK
I
CM4 SWD debug port
6
2
IR_RX
I
IrDA RX
7
3
ANTSEL[6]
O
RF control
4
GPIO_TOPOFF[34]
I/O
General purpose input output
GPIO_TOPAON[34]
I/O
General purpose input output
8
PWM[35]
O
Pulse width modulation
9
-
FRAME_SYNC *
I
3DD synchronization
1
-
MISC_LED_B
I/O
LED output
2
-
WIC[6]
I
External interrupt
3
-
UART_DSN_TXD_N9
O
UART DSN TX (N9)
0
0
3
O
O
PU
PD
0x8102_3030 [11:8]
-
-
4
0x8002_5110 [11:8]
5
(0x8102_3030 [11:8]=0]
-
UART_DBG_CM4
O
UART DBG TX (CM4)
7
GPIO_TOPOFF[35]
I/O
General purpose input output
-
GPIO_TOPAON[35]
I/O
General purpose input output
I2S_TX
O
I2S TX
5
PWM[18]
O
Pulse-width-modulated output
9
-
[Reserved]
-
0
1
[Reserved]
54
Description
Name
0x8102_3030 [15:12]
8
5
0x8002_5110 [15:12]
-
(0x8102_3030 [15:12]=0)
-
S2A_SPI_IN
I
SPI input
-
UART1_RX_CM4
I
UART1 RX (CM4)
7
GPIO_TOPOFF[36]
I/O
General purpose input output
-
0x8002_5110 [19:16]
5
GPIO_TOPAON[36]
I/O
General purpose input output
8
(0x8102_3030 [19:16]=0)
-
PWM[19]
O
Pulse-width-modulated output
9
-
UART_RXD_N9
I
UART RX (N9)
1
-
WIC[7]
I
External interrupt
3
-
UART_TXD_N9
O
UART TX (N9)
0
0
I
O
PU
PD
0x8102_3030 [19:16]
3
UART1_TX_CM4
O
UART1 TX (CM4)
7
GPIO_TOPOFF[37]
I/O
General purpose input output
-
0x8002_5110 [23:20]
5
GPIO_TOPAON]37]
I/O
General purpose input output
8
(0x8102_3030 [23:20]=0)
-
PWM[20]
O
Pulse-width-modulated output
9
EINT[20]
I
External interrupt
3
-
UART_RTS_N9
O
UART RTS (N9)
0
0
O
PD
0x8102_3030 [23:20]
3
-
PTA_EINT_B
I
Packet traffic arbitration
-
1
IDC_DATA_OUT
O
UART IDC TX (N9)
-
2
UART1_RTS_CM4
O
UART1 RTS (CM4)
7
GPIO_TOPOFF[38]
I/O
General purpose input output
-
0x8002_5110 [27:24]
5
GPIO_TOPAON[38]
I/O
General purpose input output
8
(0x8102_3030 [26:24]=0)
-
PWM[21]
O
Pulse-width-modulated output
9
-
WF_LED_B
I/O
LED output
2
-
EINT[21]
I
External interrupt
3
-
SWD_DIO
I/O
CM4 SWD debug port
6
-
UART_CTS_N9
I
UART CTS (N9)
0
0
I
PU
0x8102_3030 [27:24]
3
PTA_EINT_B
I
Packet traffic arbitration
-
1
IDC_DATA_IN
I
UART IDC RX (N9)
-
2
UART1_CTS_CM4
O
UART1 CTS (CM4)
7
[Reserved]
[Reserved]
0x8102_3030 [31:28]
-
0x8002_5110[31:28]
(0x8102_3030 [31:28]=0)
3
4
GPIO_TOPOFF[39]
I/O
General purpose input output
-
GPIO_TOPAON[39]
I/O
General purpose input output
8
-
PWM[22]
O
Pulse-width-modulated output
9
-
PULSE_COUNT *
I
Pulse counter
1
-
© 2016 - 2017 MediaTek Inc.
Page 74 of 78
This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).
Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
5
MT7687F
Internet-of-Things Wireless Connectivity
Pin
47
46
45
44
Pin alias
GPIO57
GPIO58
GPIO59
GPIO60
APGIO/
GPIO
AGPIO
AGPIO
AGPIO
AGPIO
Default
Default
dir
PU/PD
Description
Pinx_pinmux_aon_sel
Pinx_pinmux_off_sel
Name
Dir
MISC_LED_B
I/O
LED output
2
-
EINT[22]
I
External interrupt
3
-
SWD_CLK
I
CM4 SWD debug port
6
-
[Reserved]
I/O
[Reserved]
-
0
-
1
S2A_SPI_CK
I
MCU_AICE_TCKC
I
N9 debug
-
GPIO_TOPOFF[57]
I/O
General purpose input output
-
0x8002_511C [7:4]
5
GPIO_TOPAON[57]
I/O
General purpose input output
8
O
Pulse-width-modulated output
(0x8102_303C [7:4]=0,
0x8102_300C[6]=0)
-
PWM[36]
[Reserved]
I
WIC[8]
I
PU
0x8102_303C [7:4]
(0x8102_300C[6]=0)
9
2
1
-
I
External interrupt
3
-
ADC_IN0
I
Auxiliary ADC input
[Reserved]
I/O
[Reserved]
0x8102_300C[6]
1
-
-
0
-
1
S2A_SPI_OUT
O
MCU_AICE_TMSC
I/O
N9 debug
GPIO_TOPOFF[58]
I/O
General purpose input output
0x8102_303C[11:8]=0
-
5
GPIO_TOPAON[58]
I/O
General purpose input output
(0x8102_300C[7]=0)
0x8002_511C [11:8]
8
-
PWM[37]
O
Pulse-width-modulated output
9
(0x8102_303C[11:8]=0,
0x8102_300C[7]=0)
[Reserved]
I
[Reserved]
1
-
WIC[9]
I
External interrupt
3
-
ADC_IN1
I
Auxiliary ADC input
[Reserved]
O
[Reserved]
I
PU
-
-
-
0
UART DSN TX (N9)
-
1
CM4 debug port
6
-
O
SWD_DIO
I/O
GPIO_TOPOFF[59]
I/O
General purpose input output
GPIO_TOPAON[59]
I/O
General purpose input output
PWM[38]
O
Pulse-width-modulated output
WF_LED_B
I/O
WIC[10]
0x8102_300C[7]
2
1
UART_DSN_TXD_N9
I
-
0x8102_303C [15:12]
(0x8102_300C[8]=0)
8
2
0x8002_511C [15:12]
(0x8102_303C [15:12]=0,
0x8102_300C[8]=0)
5
-
9
-
LED output
1
-
I
External interrupt
3
-
ADC_IN2
I
Auxiliary ADC input
[Reserved]
I
I
0x8102_300C[8]
1
-
[Reserved]
-
0
2
SWD_CLK
I
CM4 SWD debug port
6
GPIO_TOPOFF[60]
I/O
General purpose input output
-
GPIO_TOPAON[[60]
I/O
General purpose input output
0x8102_303C [19:16]=0
8
PWM[39]
O
Pulse-width-modulated output
(0x8102_300C[9]=0)
9
MISC_LED_B
I/O
LED output
1
-
PULSE_CNT
I
Pulse counter input
2
-
WIC[11]
I
External interrupt
3
-
ADC_IN3
I
Auxiliary ADC input
1
-
0x8102_300C[9]
5
0x8002_511C [19:16]
(0x8102_303C [19:16]=0,
0x8102_300C[9]=0)
Note: * not used in MT7687F
5.4
-
[Reserved]
Bootstrap
The section describes the bootstrap function.
The chip modes are sensed from the device pin during power up. After chip reset, the pull
configuration are stored in a register and determine the device operation mode.
Table 5-4. Bootstrap Option– Flash Access Mode
© 2016 - 2017 MediaTek Inc.
Page 75 of 78
This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).
Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
-
MT7687F
Internet-of-Things Wireless Connectivity
Flash Access Mode
PIN53 (GPIO37)
Normal mode
Pull-down
Recovery mode
Pull-up
Description
(1)
Firmware jumps to flash.
Firmware does not jump to flash and wait for UART
command.
This mode is used for the firmware to jump to SYSRAM
after downloading code from UART.
Note 1: No external pull-down resistor is required because internal pull-down is active during power
up.
Table 5-5. Bootstrap Option – XTAL Clock Mode
XTAL Clock Mode
PIN12 (GPIO7)
PIN52 (GPIO38)
Description
40MHz
Pull-down
Pull-up
Uses 40MHz XTAL.
26MHz
Pull-up
Pull-down
52MHz
Pull-up
Pull-up
(1)
Uses 26MHz XTAL.
Uses 52MHz XTAL.
Note 1: No external pull-down resistor is required because internal pull-down is active during power
up.
Table 5-6. Bootstrap Option – 32KHz Clock Mode
32KHz clock mode
PIN11 (GPIO6)
Description
Internal 32KHz clock
Pull-down
32KHz clock sources from 40/26/52MHz clock.
External 32KHz clock
Pull-up
32KHz clock sources from external pin.
Table 5-7. Bootstrap Option — Chip Mode
Chip mode
PIN55
(GPIO35)
PIN10
(GPIO5)
PIN11
(GPIO6)
PIN12
(GPIO7)
PIN52
(GPIO38)
Normal mode
Pulldown(1)
Don’t care
32KHz clock
mode
control
XTAL clock mode control
Test mode
Pull-up
Description
Chip operates in normal
mode.
Chip operates in test
mode.
Note 1: No external pull-down resistor is required because internal pull-down is active during power
up.
Note 2: When in test mode, the XTAL input clock is 26MHz only.
© 2016 - 2017 MediaTek Inc.
Page 76 of 78
This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).
Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
MT7687F
Internet-of-Things Wireless Connectivity
Pins 10, 11, 12, 52, 53, and 55 are is used for bootstrap. The system design should follow the
following guideline:


5.5
Those pins shall not be used as input functions because the signals from another device
might affect the values sensed.
Those pins shall not be used as an open-drain function because the pull-up resistor
would affect the values sensed.
Package information
Figure 5-1. Package Outline Drawing
5.6
Ordering information
Table 5-8. Ordering Information
Part number
Package
Operational temperature range
© 2016 - 2017 MediaTek Inc.
Page 77 of 78
This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).
Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
MT7687F
Internet-of-Things Wireless Connectivity
MT7687FN
8mm x 8mm x 0.8 mm QFN68
-30~85°C
MT7687FIN
8mm x 8mm x 0.8 mm QFN68
-40~85°C
5.7
Top Marking
MEDIATEK
ARM
MT7687FN
DDDD-####
BBBBBBB
FFFFFFFF
MT7687FN:
DDDD
####
BBBBBBB
FFFFFFF
Part number
: Date code
: Internal control code
: Main die lot number
: Flash die lot number
Figure 5-2. Top Marking
© 2016 - 2017 MediaTek Inc.
Page 78 of 78
This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).
Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
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