HT66F2350/HT66F2360 HT66F2370/HT66F2390

HT66F2350/HT66F2360 HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Revision: V1.00
Date: �����������������
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Table of Contents
Features............................................................................................................. 7
CPU Features.......................................................................................................................... 7
Peripheral Features.................................................................................................................. 7
General Description.......................................................................................... 8
Selection Table.................................................................................................. 9
Block Diagram................................................................................................... 9
Pin Assignment............................................................................................... 10
Pin Descriptions............................................................................................. 12
Absolute Maximum Ratings........................................................................... 24
D.C. Characteristics........................................................................................ 24
Operating Voltage Characteristics.......................................................................................... 24
Standby Current Characteristics............................................................................................ 25
Operating Current Characteristics.......................................................................................... 26
A.C. Characteristics........................................................................................ 27
High Speed Internal Oscillator – HIRC – Frequency Accuracy.............................................. 27
Low Speed Internal Oscillator Characteristics – LIRC........................................................... 27
Low Speed Crystal Oscillator Characteristics – LXT.............................................................. 27
Operating Frequency Characteristic Curves.......................................................................... 28
System Start Up Time Characteristics................................................................................... 28
Input/Output Characteristics......................................................................... 29
Memory Characteristics................................................................................. 29
A/D Converter Characteristics....................................................................... 30
Comparator Electrical Characteristics......................................................... 31
Software Controlled LCD Driver Electrical Characteristics........................ 31
I2C Characteristics.......................................................................................... 32
LVD/LVR Electrical Characteristics............................................................... 32
Power-on Reset Characteristics.................................................................... 33
System Architecture....................................................................................... 34
Clocking and Pipelining.......................................................................................................... 34
Program Counter.................................................................................................................... 35
Stack...................................................................................................................................... 36
Arithmetic and Logic Unit – ALU............................................................................................ 36
Flash Program Memory.................................................................................. 37
Structure................................................................................................................................. 37
Special Vectors...................................................................................................................... 38
Look-up Table......................................................................................................................... 38
Table Program Example......................................................................................................... 38
In Circuit Programming – ICP................................................................................................ 39
On-Chip Debug Support – OCDS.......................................................................................... 40
Rev. 1.00
2
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
In Application Programming – IAP......................................................................................... 41
Data Memory................................................................................................... 50
Structure................................................................................................................................. 50
Data Memory Addressing....................................................................................................... 51
General Purpose Data Memory............................................................................................. 51
Special Purpose Data Memory.............................................................................................. 51
Special Function Register Description......................................................... 55
Indirect Addressing Registers – IAR0, IAR1, IAR2................................................................ 55
Memory Pointers – MP0, MP1H/MP1L, MP2H/MP2L............................................................ 55
Program Memory Bank Pointer – PBP................................................................................... 57
Accumulator – ACC................................................................................................................ 58
Program Counter Low Register – PCL................................................................................... 58
Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 58
Status Register – STATUS..................................................................................................... 59
EEPROM Data Memory................................................................................... 61
EEPROM Data Memory Structure......................................................................................... 61
EEPROM Registers............................................................................................................... 61
Reading Data from the EEPROM.......................................................................................... 63
Writing Data to the EEPROM................................................................................................. 64
Write Protection...................................................................................................................... 64
EEPROM Interrupt................................................................................................................. 64
Programming Considerations................................................................................................. 65
Oscillators....................................................................................................... 66
Oscillator Overview................................................................................................................ 66
System Clock Configurations................................................................................................. 66
External Crystal/Ceramic Oscillator – HXT............................................................................ 67
Internal High Speed RC Oscillator – HIRC............................................................................ 68
External 32.768 kHz Crystal Oscillator – LXT........................................................................ 68
Internal 32kHz Oscillator – LIRC............................................................................................ 69
Operating Modes and System Clocks.......................................................... 69
System Clocks....................................................................................................................... 69
System Operation Modes....................................................................................................... 71
Control Registers................................................................................................................... 72
Operating Mode Switching..................................................................................................... 74
Standby Current Considerations............................................................................................ 78
Wake-up................................................................................................................................. 78
Watchdog Timer.............................................................................................. 79
Watchdog Timer Clock Source............................................................................................... 79
Watchdog Timer Control Register.......................................................................................... 79
Watchdog Timer Operation.................................................................................................... 80
Reset and Initialisation................................................................................... 81
Reset Functions..................................................................................................................... 81
Reset Initial Conditions.......................................................................................................... 85
Rev. 1.00
3
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Input/Output Ports.......................................................................................... 91
Pull-high Resistors................................................................................................................. 92
Port A Wake-up...................................................................................................................... 93
I/O Port Control Registers...................................................................................................... 93
I/O Port Source Current Control............................................................................................. 94
I/O Port Power Source Control............................................................................................... 96
Pin-shared Functions............................................................................................................. 97
I/O Pin Structures................................................................................................................. 108
Read Port Function.............................................................................................................. 109
Programming Considerations................................................................................................110
Timer Modules – TM......................................................................................111
Introduction...........................................................................................................................111
TM Operation........................................................................................................................111
TM Clock Source...................................................................................................................112
TM Interrupts.........................................................................................................................112
TM External Pins...................................................................................................................112
TM Input/Output Pin Selection..............................................................................................113
Programming Considerations................................................................................................114
Standard Type TM – STM..............................................................................115
Standard TM Operation.........................................................................................................115
Standard Type TM Register Description...............................................................................116
Standard Type TM Operation Modes................................................................................... 120
Periodic Type TM – PTM............................................................................... 130
Periodic TM Operation......................................................................................................... 131
Periodic Type TM Register Description................................................................................ 131
Periodic Type TM Operation Modes..................................................................................... 136
Analog to Digital Converter......................................................................... 145
A/D Overview....................................................................................................................... 145
Registers Descriptions......................................................................................................... 146
A/D Converter Reference Voltage........................................................................................ 150
A/D Converter Input Signals................................................................................................. 151
A/D Operation...................................................................................................................... 152
Conversion Rate and Timing Diagram................................................................................. 153
Summary of A/D Conversion Steps...................................................................................... 154
Programming Considerations............................................................................................... 155
A/D Transfer Function.......................................................................................................... 155
A/D Programming Examples................................................................................................ 156
Serial Interface Module – SIM...................................................................... 158
SPI Interface........................................................................................................................ 158
I2C Interface......................................................................................................................... 164
Serial Interface – SPIA.................................................................................. 174
SPIA Interface Operation..................................................................................................... 174
SPIA Registers..................................................................................................................... 175
SPIA Communication........................................................................................................... 178
Rev. 1.00
4
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
SPIA Bus Enable/Disable..................................................................................................... 180
SPIA Operation.................................................................................................................... 180
Error Detection..................................................................................................................... 181
UART Interface.............................................................................................. 182
UART External Pin............................................................................................................... 183
UART Data Transfer Scheme.............................................................................................. 183
UART Status and Control Registers.................................................................................... 183
Baud Rate Generator........................................................................................................... 189
UART Setup and Control..................................................................................................... 190
UART Transmitter................................................................................................................ 191
UART Receiver.................................................................................................................... 192
Managing Receiver Errors................................................................................................... 194
UART Interrupt Structure..................................................................................................... 195
UART Power Down and Wake-up........................................................................................ 196
Comparators................................................................................................. 197
Comparator Operation......................................................................................................... 197
Comparator Registers.......................................................................................................... 197
Input Offset Calibration........................................................................................................ 199
Comparator Interrupt............................................................................................................ 199
Programming Considerations............................................................................................... 199
Software Controlled LCD Driver.................................................................. 200
LCD Operation..................................................................................................................... 200
LCD Bias Current Control.................................................................................................... 201
16-bit Multiplication Division Unit – MDU................................................... 202
MDU Registers..................................................................................................................... 202
MDU Operation.................................................................................................................... 203
Cyclic Redundancy Check – CRC............................................................... 205
CRC Registers..................................................................................................................... 205
CRC Operation..................................................................................................................... 206
Low Voltage Detector – LVD........................................................................ 208
LVD Register........................................................................................................................ 208
LVD Operation...................................................................................................................... 209
Interrupts....................................................................................................... 209
Interrupt Registers................................................................................................................ 209
Interrupt Operation............................................................................................................... 220
External Interrupt.................................................................................................................. 223
Comparator Interrupt............................................................................................................ 223
Multi-function Interrupt......................................................................................................... 223
A/D Converter Interrupt........................................................................................................ 224
Time Base Interrupt.............................................................................................................. 224
TM Interrupt.......................................................................................................................... 226
LVD Interrupt........................................................................................................................ 226
EEPROM Interrupt............................................................................................................... 226
Serial Interface Module Interrupt.......................................................................................... 227
Rev. 1.00
5
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
SPIA Interface Interrupt........................................................................................................ 227
UART Transfer Interrupt....................................................................................................... 227
Interrupt Wake-up Function.................................................................................................. 227
Programming Considerations............................................................................................... 228
Application Circuits...................................................................................... 229
Instruction Set............................................................................................... 230
Introduction.......................................................................................................................... 230
Instruction Timing................................................................................................................. 230
Moving and Transferring Data.............................................................................................. 230
Arithmetic Operations........................................................................................................... 230
Logical and Rotate Operation.............................................................................................. 231
Branches and Control Transfer............................................................................................ 231
Bit Operations...................................................................................................................... 231
Table Read Operations........................................................................................................ 231
Other Operations.................................................................................................................. 231
Instruction Set Summary............................................................................. 232
Table Conventions................................................................................................................ 232
Extended Instruction Set...................................................................................................... 234
Instruction Definition.................................................................................... 236
Extended Instruction Definition............................................................................................ 245
Package Information.................................................................................... 252
48-pin LQFP (7mm×7mm) Outline Dimensions................................................................... 253
64-pin LQFP (7mm×7mm) Outline Dimensions................................................................... 254
Rev. 1.00
6
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Features
CPU Features
• Operating voltage
♦♦ fSYS=8MHz: 2.2V~5.5V
♦♦ fSYS=12MHz: 2.7V~5.5V
♦♦ fSYS=16MHz: 3.3V~5.5V
• Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V
• Power down and wake-up functions to reduce power consumption
• Oscillator type
♦♦ External High Speed Crystal – HXT
♦♦ Internal High Speed RC – HIRC
♦♦ External 32.768kHz Crystal – LXT
♦♦ Internal 32kHz RC – LIRC
• Fully integrated internal 8/12/16MHz oscillator requires no external components
• Multi-mode operation: FAST, SLOW, IDLE and SLEEP
• All instructions executed in one to three instruction cycles
• Table read instructions
• 115 powerful instructions
• 16-level subroutine nesting
• Bit manipulation instruction
Peripheral Features
• Program Memory: Up to 64K×16
• Data Memory: Up to 4096×8
• True EEPROM Memory: Up to 1024×8
• Watchdog Timer function
• Up to 58 bidirectional I/O lines
• Programming I/O source current
• Software controlled 4-SCOM lines LCD driver with 1/2 bias
• Four external interrupt lines shared with I/O pins
• Multiple Timer Modules for time measure, input capture, compare match output, PWM output
function or single pulse output function
• Serial Interfaces Module – SIM for SPI or I2C
• Serial Peripheral Interface – SPIA
• Fully-duplex Universal Asynchronous Receiver and Transmitter Interface – UART
• Dual Time-Base functions for generation of fixed time interrupt signals
• Dual comparator functions
• Up to 16 external channels 12-bit resolution A/D converter
• Integrated Multiplier/Divider Unit – MDU
• Integraged 16-bit Cyclic Redundancy Check function – CRC
• Low voltage reset function
• Low voltage detect function
• European standard IEC 60730 and U.S. UL 60730 certified.
• Wide range of package types
Rev. 1.00
7
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
General Description
The series of devices are Flash Memory A/D type 8-bit high performance RISC architecture
microcontroller. Offering users the convenience of Flash Memory multi-programming features,
these devices also include a wide range of functions and features. Other memory includes an area
of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile data
such as serial number, calibration data, etc.
Analog features include a multi-channel 12-bit A/D converter and dual comparator functions.
Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM
generation functions. Communication with the outside world is catered for by including fully
integrated SPI, UART or I2C interface functions, two popular interfaces which provide designers
with a means of easy comminucation with external peripheral hardware. Protective features such as
an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent
noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical
environments.
A full choice of HXT, LXT, HIRC and LIRC oscillator functions are provided including a fully
integrated system oscillator which requires no external components for its implementation. The
ability to operate and switch dynamically between a range of operating modes using different
clock sources gives users the ability to optimise microcontroller operation and minimise power
consumption.
The inclusion of flexible I/O programming features, Time-Base functions along with many other
features ensure that the devices will find excellent use in applications such as electronic metering,
environmental monitoring, handheld instruments, household appliances, electronically controlled
tools, motor driving in addition to many others.
Rev. 1.00
8
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Selection Table
Most features are common to all devices. The main features distinguishing them are Memory
capacity, I/O count and A/D converter channel number. The following table summarises the main
features of each device.
Part No.
Program
Memory
Data
Data
Memory EEPROM
I/O
External
Interrupt
A/D
Comparators
Timer Module
HT66F2350
8k×16
768×8
256×8
44
4
12-bit×12
2
10-bit PTM×2
16-bit PTM×2
16-bit STM×3
HT66F2360
16k×16
1536×8
256×8
58
4
12-bit×16
2
10-bit PTM×2
16-bit PTM×2
16-bit STM×3
HT66F2370
32k×16
3072×8
512×8
58
4
12-bit×16
2
10-bit PTM×2
16-bit PTM×2
16-bit STM×3
HT66F2390
64k×16
4096×8
1024×8
58
4
12-bit×16
2
10-bit PTM×2
16-bit PTM×2
16-bit STM×3
Part No.
Time Base
SCOM
Stacks
SIM
SPIA
UART
MDU
CRC
HT66F2350
2
4
16
√
√
2
√
√
Package
48LQFP
HT66F2360
2
4
16
√
√
2
√
√
48/64LQFP
HT66F2370
2
4
16
√
√
3
√
√
48/64LQFP
HT66F2390
2
4
16
√
√
3
√
√
48/64LQFP
Note: As devices exist in more than one package format, the table reflects the situation for the package with the
most pins.
Block Diagram
Low
Voltage
Detect
Flash/EEPROM
Programming Circuitry
Low
Voltage
Reset
MDU
EEPROM
Data
Memory
Flash
Program
Memory
Interrupt
Controller
8-bit
RISC
MCU
Core
External
HXT/LXT
Oscillators
CRC
RAM Data
Memory
IAP
Reset
Circuit
Time
Base
Watchdog
Timer
Internal
HIRC/LIRC
Oscillators
12-bit A/D
Converter
Comparators
I/O
Rev. 1.00
Timer
Modules
SIM
(SPI/I2C)
UART
SPIA
9
SCOM
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Pin Assignment
PC6/STP0I/STP0/AN6
PC7/INT3/STCK0/AN7
PD0/INT2/STP1I/STP1/AN8
PD1/STCK1/RX1/AN9
PD2/PTP2I/PTP2/TX1/AN10
PD3/PTCK2/AN11
PD4/PTP3I/RX0/PTP3/C1−
PD5/PTCK3/TX0/C1+
PD6/STP2I/STP2/C1X
PF6/STCK2/RX1/C0−
PF7/STP2I/TX1/STP2/C0+
PB0/STCK2/C0X
PB1/PTCK3
PB2/PTP3I/PTCK2/PTP3
PB3/PTP2I/PTP2
PB4/C1X
PB5/RES
VDD
VSS
PB6/STP1I/STP1/OSC1
PB7/STCK1/OSC2
PA5/INT3/SCK/SCL
PA1/INT0/SCS
PA2/ICPCK/OCDSCK
48 47 46 45 44 43 42 41 40 39 38 37
36
1
35
2
34
3
33
4
5
32
HT66F2350/HT66V2350
31
6
HT66F2360/HT66V2360
7
30
48 LQFP-A
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
PC5/PTCK1/AN5
PC4/PTP1I/PTP1/AN4
PC3/PTCK0/AN3
PC2/PTP0I/PTP0/AN2
PC1/C0X/VREF/AN1
PC0/VREFI/AN0
AVSS
PF5/PTP0I/PTP0/XT1
PF4/PTCK0/XT2
AVDD
PF3/SCK/SCL/SCOM3
PF2/SDI/SDA/SCOM2
PF1/SDO/SCOM1
PF0/SCS/SCOM0
PE4/VDDIO
PE3/PTP1I/PTP1/SCKA
PE2/PTCK1/SDIA
PE1/STP0I/STP0/SDOA
PE0/STCK0/SCSA
PA7/INT1/TX0
PA6/INT0/RX0
PA0/ICPDA/OCDSDA
PA4/INT2/SDI/SDA
PA3/INT1/SDO
PC6/STP0I/STP0/AN6
PC7/INT3/STCK0/AN7
PD0/INT2/STP1I/STP1/AN8
PD1/STCK1/RX1/AN9
PD2/PTP2I/PTP2/TX1/AN10
PD3/PTCK2/AN11
PD4/PTP3I/RX0/PTP3/C1−
PD5/PTCK3/TX0/C1+
PD6/STP2I/STP2/C1X
PF6/STCK2/RX1/C0−
PF7/STP2I/TX1/STP2/C0+
PB0/STCK2/C0X
PB1/PTCK3/TX2
PB2/PTP3I/PTCK2/RX2/PTP3
PB3/PTP2I/PTP2
PB4/C1X
PB5/RES
VDD
VSS
PB6/STP1I/STP1/OSC1
PB7/STCK1/OSC2
PA5/INT3/SCK/SCL
PA1/INT0/SCS
PA2/ICPCK/OCDSCK
48 47 46 45 44 43 42 41 40 39 38 37
36
1
35
2
34
3
33
4
5
32
HT66F2370/HT66V2370
31
6
HT66F2390/HT66V2390
7
30
48 LQFP-A
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
PC5/PTCK1/AN5
PC4/PTP1I/PTP1/AN4
PC3/PTCK0/AN3
PC2/PTP0I/PTP0/AN2
PC1/C0X/VREF/AN1
PC0/VREFI/AN0
AVSS
PF5/PTP0I/PTP0/XT1
PF4/PTCK0/XT2
AVDD
PF3/SCK/SCL/SCOM3
PF2/SDI/SDA/SCOM2
PF1/SDO/SCOM1
PF0/SCS/SCOM0
PE4/VDDIO
PE3/PTP1I/PTP1/SCKA
PE2/PTCK1/SDIA
PE1/STP0I/STP0/SDOA
PE0/STCK0/SCSA
PA7/INT1/TX0
PA6/INT0/RX0
PA0/ICPDA/OCDSDA
PA4/INT2/SDI/SDA
PA3/INT1/SDO
Rev. 1.00
10
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
PC6/STP0I/STP0/AN6
PC7/INT3/STCK0/AN7
PD0/INT2/STP1I/STP1/AN8
PD1/STCK1/RX1/AN9
PD2/PTP2I/PTP2/TX1/AN10
PD3/PTCK2/AN11
PH2/AN12
PH3/AN13
PH4/AN14
PH5/AN15
PD4/PTP3I/RX0/PTP3/C1−
PD5/PTCK3/TX0/C1+
PD6/STP2I/STP2/C1X
PF6/STCK2/RX1/C0−
PF7/STP2I/TX1/STP2/C0+
PB0/STCK2/C0X
PB1/PTCK3
PB2/PTP3I/PTCK2/PTP3
PB3/PTP2I/PTP2
PB4/C1X
PB5/RES
VDD
VSS
PB6/STP1I/STP1/OSC1
PB7/STCK1/OSC2
PG4
PG5
PG6
PG7
PA5/INT3/SCK/SCL
PA1/INT0/SCS
PA2/ICPCK/OCDSCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
HT66F2360/HT66V2360
41
64 LQFP-A
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PC5/PTCK1/AN5
PC4/PTP1I/PTP1/AN4
PC3/PTCK0/AN3
PC2/PTP0I/PTP0/AN2
PC1/C0X/VREF/AN1
PC0/VREFI/AN0
AVSS
PF5/PTP0I/PTP0/XT1
PF4/PTCK0/XT2
AVDD
PG0
PG1
PG2
PG3
PF3/SCK/SCL/SCOM3
PF2/SDI/SDA/SCOM2
PF1/SDO/SCOM1
PF0/SCS/SCOM0
PE4/VDDIO
PE3/PTP1I/PTP1/SCKA
PE2/PTCK1/SDIA
PE1/STP0I/STP0/SDOA
PE0/STCK0/SCSA
PH1
PH0
VSS
VDD
PA7/INT1/TX0
PA6/INT0/RX0
PA0/ICPDA/OCDSDA
PA4/INT2/SDI/SDA
PA3/INT1/SDO
PC6/STP0I/STP0/AN6
PC7/INT3/STCK0/AN7
PD0/INT2/STP1I/STP1/AN8
PD1/STCK1/RX1/AN9
PD2/PTP2I/PTP2/TX1/AN10
PD3/PTCK2/AN11
PH2/AN12
PH3/AN13
PH4/AN14
PH5/AN15
PD4/PTP3I/RX0/PTP3/C1−
PD5/PTCK3/TX0/C1+
PD6/STP2I/STP2/C1X
PF6/STCK2/RX1/C0−
PF7/STP2I/TX1/STP2/C0+
PB0/STCK2/C0X
PB1/PTCK3/TX2
PB2/PTP3I/PTCK2/RX2/PTP3
PB3/PTP2I/PTP2
PB4/C1X
PB5/RES
VDD
VSS
PB6/STP1I/STP1/OSC1
PB7/STCK1/OSC2
PG4
PG5
PG6
PG7
PA5/INT3/SCK/SCL
PA1/INT0/SCS
PA2/ICPCK/OCDSCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
HT66F2370/HT66V2370
41
HT66F2390/HT66V2390
40
64 LQFP-A
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PC5/PTCK1/AN5
PC4/PTP1I/PTP1/AN4
PC3/PTCK0/AN3
PC2/PTP0I/PTP0/AN2
PC1/C0X/VREF/AN1
PC0/VREFI/AN0
AVSS
PF5/PTP0I/PTP0/XT1
PF4/PTCK0/XT2
AVDD
PG0/RX2
PG1/TX2
PG2
PG3
PF3/SCK/SCL/SCOM3
PF2/SDI/SDA/SCOM2
PF1/SDO/SCOM1
PF0/SCS/SCOM0
PE4/VDDIO
PE3/PTP1I/PTP1/SCKA
PE2/PTCK1/SDIA
PE1/STP0I/STP0/SDOA
PE0/STCK0/SCSA
PH1
PH0
VSS
VDD
PA7/INT1/TX0
PA6/INT0/RX0
PA0/ICPDA/OCDSDA
PA4/INT2/SDI/SDA
PA3/INT1/SDO
Note: The OCDSDA and OCDSCK pins are the OCDS dedicated pins and only available for the HT66V23x0
device which is the OCDS EV chip for the HT66F23x0 device.
Rev. 1.00
11
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Pin Descriptions
With the exception of the power pins, all pins on these devices can be referenced by their Port name,
e.g. PA0, PA1 etc, which refer to the digital I/O function of the pins. However these Port pins are
also shared with other function such as the Analog to Digital Converter, Timer Module pins, etc.
The function of each pin is listed in the following table, however the details behind how each pin is
configured is contained in other sections of the datasheet.
HT66F2350/HT66F2360
Pad Name
PA0/ICPDA/
OCDSDA
PA1/INT0/SCS
PA2/ICPCK/
OCDSCK
PA3/INT1/SDO
PA4/INT2/SDI/SDA
Rev. 1.00
Function
OPT
I/T
O/T
Description
PA0
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
ICPDA
—
ST
CMOS
ICP Data/Address pin
OCDSDA
—
ST
CMOS
OCDS Data/Address pin, for EV chip only.
PA1
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
INT0
PAS0
INTEG
INTC0
IFS2
ST
—
SCS
PAS0
IFS2
ST
CMOS
SPI slave select
PA2
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
ICP Clock pin
External Interrupt 0
ICPCK
—
ST
CMOS
OCDSCK
—
ST
—
PA3
PAWU
PAPU
PAS0
ST
CMOS
INT1
PAS0
INTEG
INTC0
IFS2
ST
—
SDO
PAS0
—
CMOS
SPI data output
PA4
PAWU
PAPU
PAS1
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
INT2
PAS1
INTEG
INTC3
IFS2
ST
—
External Interrupt 2
SDI
PAS1
IFS2
ST
—
SPI data input
SDA
PAS1
IFS2
ST
NMOS
12
OCDS Clock pin, for EV chip only.
General purpose I/O. Register enabled pull-up and
wake-up.
External Interrupt 1
I2C data line
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Pad Name
PA5/INT3/SCK/SCL
PA6/INT0/RX0
PA7/INT1/TX0
PB0/STCK2/C0X
Function
OPT
I/T
O/T
Description
PA5
PAWU
PAPU
PAS1
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
INT3
PAS1
INTEG
INTC3
IFS2
ST
—
SCK
PAS1
IFS2
ST
CMOS
SPI serial clock
SCL
PAS1
IFS2
ST
NMOS
I2C clock line
PA6
PAWU
PAPU
PAS1
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
INT0
PAS1
INTEG
INTC0
IFS2
ST
—
External Interrupt 0
RX0
PAS1
IFS3
ST
—
UART0 RX serial data input
PA7
PAWU
PAPU
PAS1
ST
CMOS
INT1
PAS1
INTEG
INTC0
IFS2
ST
—
TX0
PAS1
—
CMOS
UART0 TX serial data output
PB0
PBPU
PBS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
STCK2
PBS0
IFS0
ST
—
C0X
PBS0
—
CMOS
Comparator 0 output
PB1
PBPU
PBS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTCK3
PBS0
IFS0
ST
—
PB2
PBPU
PBS0
ST
CMOS
PTP3I
PBS0
IFS1
ST
—
PTM3 capture input
PTCK2
PBS0
IFS0
ST
—
PTM2 clock input
PTP3
PBS0
—
CMOS
PTM3 output
PB3
PBPU
PBS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTP2I
PBS0
IFS1
ST
—
PTP2
PBS0
—
CMOS
PTM2 output
PB4
PBPU
PBS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
C1X
PBS1
—
CMOS
Comparator 1 output
PB1/PTCK3
PB2/PTP3I/PTCK2/
PTP3
PB3/PTP2I/PTP2
PB4/C1X
Rev. 1.00
13
External Interrupt 3
General purpose I/O. Register enabled pull-up and
wake-up.
External Interrupt 1
STM2 clock input
PTM3 clock input
General purpose I/O. Register enabled pull-up.
PTM2 capture input
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Pad Name
PB5/RES
PB6/STP1I/STP1/
OSC1
PB7/STCK1/OSC2
PC0/VREFI/AN0
PC1/C0X/VREF/
AN1
PC2/PTP0I/PTP0/
AN2
PC3/PTCK0/AN3
PC4/PTP1I/PTP1/
AN4
PC5/PTCK1/AN5
PC6/STP0I/STP0/
AN6
Rev. 1.00
Function
OPT
I/T
O/T
PB5
PBPU
PBS1
RSTC
ST
CMOS
RES
RSTC
ST
—
PB6
PBPU
PBS1
ST
CMOS
STP1I
PBS1
IFS1
ST
—
Description
General purpose I/O. Register enabled pull-up.
External reset input
General purpose I/O. Register enabled pull-up.
STM1 capture input
STP1
PBS1
—
CMOS
OSC1
PBS1
HXT
—
STM1 output
PB7
PBPU
PBS1
ST
CMOS
STCK1
PBS1
IFS0
ST
—
STM1 clock input
OSC2
PBS1
—
HXT
HXT oscillator pin
PC0
PCPU
PCS0
ST
CMOS
HXT oscillator pin
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
VREFI
PCS0
AN
—
A/D Converter reference voltage input
AN0
PCS0
AN
—
A/D Converter analog input
PC1
PCPU
PCS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
Comparator 0 output
C0X
PCS0
—
CMOS
VREF
PCS0
AN
—
A/D Converter reference voltage input
AN1
PCS0
AN
—
A/D Converter analog input
PC2
PCPU
PCS0
ST
CMOS
PTP0I
PCS0
IFS1
ST
—
General purpose I/O. Register enabled pull-up.
PTM0 capture input
PTP0
PCS0
—
CMOS
AN2
PCS0
AN
—
PC3
PCPU
PCS0
ST
CMOS
PTCK0
PCS0
IFS0
ST
—
PTM0 clock input
AN3
PCS0
AN
—
A/D Converter analog input
PC4
PCPU
PCS1
ST
CMOS
PTP1I
PCS1
IFS1
ST
—
PTP1
PCS1
—
CMOS
AN4
PCS1
AN
—
PC5
PCPU
PCS1
ST
CMOS
PTCK1
PCS1
IFS0
ST
—
PTM1 clock input
AN5
PCS1
AN
—
A/D Converter analog input
PC6
PCPU
PCS1
ST
CMOS
STP0I
PCS1
IFS1
ST
—
STP0
PCS1
—
CMOS
AN6
PCS1
AN
—
14
PTM0 output
A/D Converter analog input
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
PTM1 capture input
PTM1 output
A/D Converter analog input
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
STM0 capture input
STM0 output
A/D Converter analog input
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Pad Name
PC7/INT3/STCK0/
AN7
PD0/INT2/STP1I/
STP1/AN8
PD1/STCK1/RX1/
AN9
PD2/PTP2I/PTP2/
TX1/AN10
PD3/PTCK2/AN11
PD4/PTP3I/PTP3/
RX0/C1−
PD5/PTCK3/TX0/
C1+
Rev. 1.00
Function
OPT
I/T
O/T
PC7
PCPU
PCS1
Description
ST
CMOS
INT3
PCS1
INTEG
INTC3
IFS2
ST
—
External Interrupt 3
STCK0
PCS1
IFS0
ST
—
STM0 clock input
AN7
PCS1
AN
—
A/D Converter analog input
PD0
PDPU
PDS0
ST
CMOS
INT2
PDS0
INTEG
INTC3
IFS2
ST
—
External Interrupt 2
STP1I
PDS0
IFS1
ST
—
STM1 capture input
STP1
PDS0
—
CMOS
AN8
PDS0
AN
—
PD1
PDPU
PDS0
ST
CMOS
STCK1
PDS0
IFS0
ST
—
STM1 clock input
RX1
PDS0
IFS3
ST
—
UART1 RX serial data input
AN9
PDS0
AN
—
A/D Converter analog input
PD2
PDPU
PDS0
ST
CMOS
PTP2I
PDS0
IFS1
ST
—
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
STM1 output
A/D Converter analog input
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
PTM2 capture input
PTP2
PDS0
—
CMOS
PTM2 output
TX1
PDS0
—
CMOS
UART1 TX serial data output
AN10
PDS0
AN
—
PD3
PDPU
PDS0
ST
CMOS
PTCK2
PDS0
IFS0
ST
—
PTM2 clock input
AN11
PDS0
AN
—
A/D Converter analog input
PD4
PDPU
PDS1
ST
CMOS
PTP3I
PDS1
IFS1
ST
—
PTP3
PDS1
—
CMOS
RX0
PDS1
IFS3
ST
—
UART0 RX serial data input
C1−
PDS1
—
CMOS
Comparator 1 negative input
PD5
PDPU
PDS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTCK3
PDS1
IFS0
ST
—
A/D Converter analog input
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
PTM3 capture input
PTM3 output
PTM3 clock input
TX0
PDS1
—
CMOS
UART0 TX serial data output
C1+
PDS1
—
CMOS
Comparator 1 positive input
15
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Pad Name
PD6/STP2I/STP2/
C1X
PE0/STCK0/SCSA
PE1/STP0I/STP0/
SDOA
PE2/PTCK1/SDIA
PE3/PTP1I/PTP1/
SCKA
Function
OPT
I/T
O/T
PD6
PDPU
PDS1
ST
CMOS
STP2I
PDS1
IFS1
ST
—
STP2
PDS1
—
CMOS
STM2 output
C1X
PDS1
—
CMOS
Comparator 1 output
PE0
PEPU
PES0
ST
CMOS
General purpose I/O. Register enabled pull-up.
STCK0
PES0
IFS0
ST
—
STM0 clock input
SCSA
PES0
ST
CMOS
SPIA slave select
PE1
PEPU
PES0
ST
CMOS
General purpose I/O. Register enabled pull-up.
STP0I
PES0
IFS
ST
—
PF1/SDO/SCOM1
PF2/SDI/SDA/
SCOM2
Rev. 1.00
General purpose I/O. Register enabled pull-up.
STM2 capture input
STM0 capture input
STP0
PES0
—
CMOS
STM0 inverted output
SDOA
PES0
—
CMOS
SPIA data output
PE2
PEPU
PES0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTCK1
PES0
IFS0
ST
—
PTM1 clock input
SDIA
PES0
ST
—
SPIA data input
PE3
PEPU
PES0
ST
CMOS
PTP1I
PES0
IFS1
ST
—
General purpose I/O. Register enabled pull-up.
PTM1 capture input
PTP1
PES0
—
CMOS
PTM1 output
SCKA
PES0
ST
CMOS
SPIA serial clock
PE4
PEPU
PES1
ST
CMOS
General purpose I/O. Register enabled pull-up.
VDDIO
PES1
PMPS
PWR
—
PF0
PFPU
PFS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
SCS
PFS0
IFS2
ST
CMOS
SPI slave select
SCOM0
PFS0
—
CMOS
Software LCD COM output
PF1
PFPU
PFS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
SDO
PFS0
—
CMOS
SPI data output
SCOM1
PFS0
—
CMOS
Software LCD COM output
PF2
PFPU
PFS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
SDI
PFS0
IFS2
ST
—
SDA
PFS0
IFS2
ST
NMOS
I2C data line
SCOM2
PFS0
—
CMOS
Software LCD COM output
PE4/VDDIO
PF0/SCS/SCOM0
Description
16
PE0~PE3 pin power for level shift
SPI data input
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Pad Name
PF3/SCK/SCL/
SCOM3
PF4/PTCK0/XT2
PF5/PTP0I/PTP0/
XT1
Function
OPT
I/T
O/T
PF3
PFPU
PFS0
Description
ST
CMOS
General purpose I/O. Register enabled pull-up.
SCK
PFS0
IFS2
ST
CMOS
SPI serial clock
SCL
PFS0
IFS2
ST
NMOS
I2C clock line
SCOM3
PFS0
—
CMOS
Software LCD COM output
PF4
PFPU
PFS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTCK0
PFS1
IFS0
ST
—
PTM0 clock input
XT2
PFS1
—
LXT
LXT oscillator pin
PF5
PFPU
PFS1
ST
CMOS
PTP0I
PFS1
IFS1
ST
—
General purpose I/O. Register enabled pull-up.
PTM0 capture input
PTP0
PFS1
—
CMOS
XT1
PFS1
LXT
—
PF6
PFPU
PFS1
ST
CMOS
STCK2
PFS1
IFS0
ST
—
STM2 clock input
RX1
PFS1
IFS3
ST
—
UART1 RX serial data input
C0−
PFS1
—
CMOS
Comparator 0 negative input
PF7
PFPU
PFS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
STP2I
PFS1
IFS1
ST
—
STP2
PFS1
—
CMOS
STM2 output
TX1
PFS1
—
CMOS
UART1 TX serial data output
C0+
PDS1
—
CMOS
Comparator 0 positive input
PG0~PG3
PGn
PGPU
PGS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PG4~PG7
PGn
PGPU
PGS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
PH0~PH1
PHn
PHPU
PHS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PH2
PHPU
PHS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
AN12
PHS0
AN
—
PH3
PHPU
PHS0
ST
CMOS
AN13
PHS0
AN
—
PH4
PHPU
PHS1
ST
CMOS
AN14
PHS1
AN
—
PH5
PHPU
PHS1
ST
CMOS
PF6/STCK2/RX1/
C0−
PF7/STP2I/STP2/
TX1/C0+
PH2/AN12
PH3/AN13
PH4/AN14
PH5/AN15
PTM0 output
LXT oscillator pin
General purpose I/O. Register enabled pull-up.
STM2 capture input
A/D Converter analog input
General purpose I/O. Register enabled pull-up.
A/D Converter analog input
General purpose I/O. Register enabled pull-up.
A/D Converter analog input
General purpose I/O. Register enabled pull-up.
AN15
PHS1
AN
—
A/D Converter analog input
VDD
VDD
—
PWR
—
Positive power supply
VSS
VSS
—
PWR
—
Negative power supply, ground.
Rev. 1.00
17
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Function
OPT
I/T
O/T
AVDD
Pad Name
AVDD
—
PWR
—
Analog positive power supply
Description
AVSS
AVSS
—
PWR
—
Analog negative power supply, ground.
Legend: I/T: Input type;
O/T: Output type;
OPT: Optional by register option;
CMOS: CMOS output;
NMOS: NMOS output;
ST: Schmitt Trigger input;
AN: Analog signal; PWR: Power;
HXT: High frequency crystal oscillator; LXT: Low frequency crystal oscillator
Note: The Ports G and H are available for the HT66F2360 device.
HT66F2370/HT66F2390
Pad Name
PA0/ICPDA/
OCDSDA
PA1/INT0/SCS
PA2/ICPCK/
OCDSCK
PA3/INT1/SDO
PA4/INT2/SDI/SDA
Rev. 1.00
Function
OPT
I/T
O/T
Description
PA0
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
ICPDA
—
ST
CMOS
ICP Data/Address pin
OCDSDA
—
ST
CMOS
OCDS Data/Address pin, for EV chip only.
PA1
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
INT0
PAS0
INTEG
INTC0
IFS2
ST
—
SCS
PAS0
IFS2
ST
CMOS
SPI slave select
PA2
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
ICP Clock pin
External Interrupt 0
ICPCK
—
ST
CMOS
OCDSCK
—
ST
—
PA3
PAWU
PAPU
PAS0
ST
CMOS
INT1
PAS0
INTEG
INTC0
IFS2
ST
—
SDO
PAS0
—
CMOS
SPI data output
PA4
PAWU
PAPU
PAS1
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
INT2
PAS1
INTEG
INTC3
IFS2
ST
—
External Interrupt 2
SDI
PAS1
IFS2
ST
—
SPI data input
SDA
PAS1
IFS2
ST
NMOS
18
OCDS Clock pin, for EV chip only.
General purpose I/O. Register enabled pull-up and
wake-up.
External Interrupt 1
I2C data line
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Pad Name
PA5/INT3/SCK/SCL
PA6/INT0/RX0
PA7/INT1/TX0
PB0/STCK2/C0X
PB1/PTCK3/TX2
PB2/PTP3I/PTCK2/
PTP3/RX2
PB3/PTP2I/PTP2
PB4/C1X
Rev. 1.00
Function
OPT
I/T
O/T
Description
PA5
PAWU
PAPU
PAS1
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
INT3
PAS1
INTEG
INTC3
IFS2
ST
—
SCK
PAS1
IFS2
ST
CMOS
SPI serial clock
SCL
PAS1
IFS2
ST
NMOS
I2C clock line
PA6
PAWU
PAPU
PAS1
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
INT0
PAS1
INTEG
INTC0
IFS2
ST
—
External Interrupt 0
RX0
PAS1
IFS3
ST
—
UART0 RX serial data input
PA7
PAWU
PAPU
PAS1
ST
CMOS
INT1
PAS1
INTEG
INTC0
IFS2
ST
—
TX0
PAS1
—
CMOS
UART0 TX serial data output
PB0
PBPU
PBS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
STCK2
PBS0
IFS0
ST
—
C0X
PBS0
—
CMOS
Comparator 0 output
PB1
PBPU
PBS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTCK3
PBS0
IFS0
ST
—
TX2
PBS0
—
CMOS
UART2 TX serial data output
PB2
PBPU
PBS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTP3I
PBS0
IFS1
ST
—
PTM3 capture input
PTCK2
PBS0
IFS0
ST
—
PTM2 clock input
PTP3
PBS0
—
CMOS
RX2
PBS0
IFS3
ST
—
PB3
PBPU
PBS0
ST
CMOS
PTP2I
PBS0
IFS1
ST
—
PTP2
PBS0
—
CMOS
PTM2 output
PB4
PBPU
PBS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
C1X
PBS1
—
CMOS
Comparator 1 output
19
External Interrupt 3
General purpose I/O. Register enabled pull-up and
wake-up.
External Interrupt 1
STM2 clock input
PTM3 clock input
PTM3 output
UART2 RX serial data input
General purpose I/O. Register enabled pull-up.
PTM2 capture input
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Pad Name
PB5/RES
PB6/STP1I/STP1/
OSC1
PB7/STCK1/OSC2
PC0/VREFI/AN0
PC1/C0X/VREF/
AN1
PC2/PTP0I/PTP0/
AN2
PC3/PTCK0/AN3
PC4/PTP1I/PTP1/
AN4
PC5/PTCK1/AN5
PC6/STP0I/STP0/
AN6
Rev. 1.00
Function
OPT
I/T
O/T
PB5
PBPU
PBS1
RSTC
ST
CMOS
RES
RSTC
ST
—
PB6
PBPU
PBS1
ST
CMOS
STP1I
PBS1
IFS1
ST
—
Description
General purpose I/O. Register enabled pull-up.
External reset input
General purpose I/O. Register enabled pull-up.
STM1 capture input
STP1
PBS1
—
CMOS
OSC1
PBS1
HXT
—
STM1 output
PB7
PBPU
PBS1
ST
CMOS
STCK1
PBS1
IFS0
ST
—
STM1 clock input
OSC2
PBS1
—
HXT
HXT oscillator pin
PC0
PCPU
PCS0
ST
CMOS
HXT oscillator pin
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
VREFI
PCS0
AN
—
A/D Converter reference voltage input
AN0
PCS0
AN
—
A/D Converter analog input
PC1
PCPU
PCS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
Comparator 0 output
C0X
PCS0
—
CMOS
VREF
PCS0
AN
—
A/D Converter reference voltage input
AN1
PCS0
AN
—
A/D Converter analog input
PC2
PCPU
PCS0
ST
CMOS
PTP0I
PCS0
IFS1
ST
—
General purpose I/O. Register enabled pull-up.
PTM0 capture input
PTP0
PCS0
—
CMOS
AN2
PCS0
AN
—
PC3
PCPU
PCS0
ST
CMOS
PTCK0
PCS0
IFS0
ST
—
PTM0 clock input
AN3
PCS0
AN
—
A/D Converter analog input
PC4
PCPU
PCS1
ST
CMOS
PTP1I
PCS1
IFS1
ST
—
PTP1
PCS1
—
CMOS
AN4
PCS1
AN
—
PC5
PCPU
PCS1
ST
CMOS
PTCK1
PCS1
IFS0
ST
—
PTM1 clock input
AN5
PCS1
AN
—
A/D Converter analog input
PC6
PCPU
PCS1
ST
CMOS
STP0I
PCS1
IFS1
ST
—
STP0
PCS1
—
CMOS
AN6
PCS1
AN
—
20
PTM0 output
A/D Converter analog input
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
PTM1 capture input
PTM1 output
A/D Converter analog input
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
STM0 capture input
STM0 output
A/D Converter analog input
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Pad Name
PC7/INT3/STCK0/
AN7
PD0/INT2/STP1I/
STP1/AN8
PD1/STCK1/RX1/
AN9
PD2/PTP2I/PTP2/
TX1/AN10
PD3/PTCK2/AN11
PD4/PTP3I/PTP3/
RX0/C1−
PD5/PTCK3/TX0/
C1+
Rev. 1.00
Function
OPT
I/T
O/T
PC7
PCPU
PCS1
Description
ST
CMOS
INT3
PCS1
INTEG
INTC3
IFS2
ST
—
External Interrupt 3
STCK0
PCS1
IFS0
ST
—
STM0 clock input
AN7
PCS1
AN
—
A/D Converter analog input
PD0
PDPU
PDS0
ST
CMOS
INT2
PDS0
INTEG
INTC3
IFS2
ST
—
External Interrupt 2
STP1I
PDS0
IFS1
ST
—
STM1 capture input
STP1
PDS0
—
CMOS
AN8
PDS0
AN
—
PD1
PDPU
PDS0
ST
CMOS
STCK1
PDS0
IFS0
ST
—
STM1 clock input
RX1
PDS0
IFS3
ST
—
UART1 RX serial data input
AN9
PDS0
AN
—
A/D Converter analog input
PD2
PDPU
PDS0
ST
CMOS
PTP2I
PDS0
IFS1
ST
—
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
STM1 output
A/D Converter analog input
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
PTM2 capture input
PTP2
PDS0
—
CMOS
PTM2 output
TX1
PDS0
—
CMOS
UART1 TX serial data output
AN10
PDS0
AN
—
PD3
PDPU
PDS0
ST
CMOS
PTCK2
PDS0
IFS0
ST
—
PTM2 clock input
AN11
PDS0
AN
—
A/D Converter analog input
PD4
PDPU
PDS1
ST
CMOS
PTP3I
PDS1
IFS1
ST
—
PTP3
PDS1
—
CMOS
RX0
PDS1
IFS3
ST
—
UART0 RX serial data input
C1−
PDS1
—
CMOS
Comparator 1 negative input
PD5
PDPU
PDS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTCK3
PDS1
IFS0
ST
—
A/D Converter analog input
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
PTM3 capture input
PTM3 output
PTM3 clock input
TX0
PDS1
—
CMOS
UART0 TX serial data output
C1+
PDS1
—
CMOS
Comparator 1 positive input
21
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Pad Name
PD6/STP2I/STP2/
C1X
PE0/STCK0/SCSA
PE1/STP0I/STP0/
SDOA
PE2/PTCK1/SDIA
PE3/PTP1I/PTP1/
SCKA
Function
OPT
I/T
O/T
PD6
PDPU
PDS1
ST
CMOS
STP2I
PDS1
IFS1
ST
—
STP2
PDS1
—
CMOS
STM2 output
C1X
PDS1
—
CMOS
Comparator 1 output
PE0
PEPU
PES0
ST
CMOS
General purpose I/O. Register enabled pull-up.
STCK0
PES0
IFS0
ST
—
STM0 clock input
SCSA
PES0
ST
CMOS
SPIA slave select
PE1
PEPU
PES0
ST
CMOS
General purpose I/O. Register enabled pull-up.
STP0I
PES0
IFS
ST
—
PF1/SDO/SCOM1
PF2/SDI/SDA/
SCOM2
Rev. 1.00
General purpose I/O. Register enabled pull-up.
STM2 capture input
STM0 capture input
STP0
PES0
—
CMOS
STM0 inverted output
SDOA
PES0
—
CMOS
SPIA data output
PE2
PEPU
PES0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTCK1
PES0
IFS0
ST
—
PTM1 clock input
SDIA
PES0
ST
—
SPIA data input
PE3
PEPU
PES0
ST
CMOS
PTP1I
PES0
IFS1
ST
—
General purpose I/O. Register enabled pull-up.
PTM1 capture input
PTP1
PES0
—
CMOS
PTM1 output
SCKA
PES0
ST
CMOS
SPIA serial clock
PE4
PEPU
PES1
ST
CMOS
General purpose I/O. Register enabled pull-up.
VDDIO
PES1
PMPS
PWR
—
PF0
PFPU
PFS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
SCS
PFS0
IFS2
ST
CMOS
SPI slave select
SCOM0
PFS0
—
CMOS
Software LCD COM output
PF1
PFPU
PFS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
SDO
PFS0
—
CMOS
SPI data output
SCOM1
PFS0
—
CMOS
Software LCD COM output
PF2
PFPU
PFS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
SDI
PFS0
IFS2
ST
—
SDA
PFS0
IFS2
ST
NMOS
I2C data line
SCOM2
PFS0
—
CMOS
Software LCD COM output
PE4/VDDIO
PF0/SCS/SCOM0
Description
22
PE0~PE3 pin power for level shift
SPI data input
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Pad Name
PF3/SCK/SCL/
SCOM3
PF4/PTCK0/XT2
PF5/PTP0I/PTP0/
XT1
Function
OPT
I/T
O/T
PF3
PFPU
PFS0
Description
ST
CMOS
General purpose I/O. Register enabled pull-up.
SCK
PFS0
IFS2
ST
CMOS
SPI serial clock
SCL
PFS0
IFS2
ST
NMOS
I2C clock line
SCOM3
PFS0
—
CMOS
Software LCD COM output
PF4
PFPU
PFS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTCK0
PFS1
IFS0
ST
—
PTM0 clock input
XT2
PFS1
—
LXT
LXT oscillator pin
PF5
PFPU
PFS1
ST
CMOS
PTP0I
PFS1
IFS1
ST
—
General purpose I/O. Register enabled pull-up.
PTM0 capture input
PTP0
PFS1
—
CMOS
XT1
PFS1
LXT
—
PF6
PFPU
PFS1
ST
CMOS
STCK2
PFS1
IFS0
ST
—
STM2 clock input
RX1
PFS1
IFS3
ST
—
UART1 RX serial data input
C0−
PFS1
—
CMOS
Comparator 0 negative input
PF7
PFPU
PFS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
STP2I
PFS1
IFS1
ST
—
STP2
PFS1
—
CMOS
STM2 output
TX1
PFS1
—
CMOS
UART1 TX serial data output
C0+
PDS1
—
CMOS
Comparator 0 positive input
PG0
PGPU
PGS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
RX2
PGS0
IFS3
ST
—
PG1
PGPU
PGS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
TX2
PGS0
—
CMOS
UART2 TX serial data output
PG2~PG3
PGn
PGPU
PGS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PG4~PG7
PGn
PGPU
PGS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
PH0~PH1
PHn
PHPU
PHS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PH2
PHPU
PHS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
AN12
PHS0
AN
—
PH3
PHPU
PHS0
ST
CMOS
AN13
PHS0
AN
—
PF6/STCK2/RX1/
C0−
PF7/STP2I/STP2/
TX1/C0+
PG0/RX2
PG1/TX2
PH2/AN12
PH3/AN13
Rev. 1.00
23
PTM0 output
LXT oscillator pin
General purpose I/O. Register enabled pull-up.
STM2 capture input
UART2 RX serial data input
A/D Converter analog input
General purpose I/O. Register enabled pull-up.
A/D Converter analog input
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Pad Name
Function
OPT
I/T
O/T
PH4
PHPU
PHS1
ST
CMOS
AN14
PHS1
AN
—
PH5
PHPU
PHS1
ST
CMOS
AN15
PHS1
AN
—
A/D Converter analog input
VDD
VDD
—
PWR
—
Positive power supply
VSS
VSS
—
PWR
—
Negative power supply, ground.
AVDD
AVDD
—
PWR
—
Analog positive power supply
AVSS
AVSS
—
PWR
—
PH4/AN14
PH5/AN15
Legend: I/T: Input type;
OPT: Optional by register option;
NMOS: NMOS output;
AN: Analog signal; HXT: High frequency crystal oscillator; Description
General purpose I/O. Register enabled pull-up.
A/D Converter analog input
General purpose I/O. Register enabled pull-up.
Analog negative power supply, ground.
O/T: Output type;
CMOS: CMOS output;
ST: Schmitt Trigger input;
PWR: Power;
LXT: Low frequency crystal oscillator
Absolute Maximum Ratings
Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V
Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V
Storage Temperature.....................................................................................................-50˚C to 125˚C
Operating Temperature...................................................................................................-40˚C to 85˚C
IOL Total...................................................................................................................................... 80mA
IOH Total.....................................................................................................................................-80mA
Total Power Dissipation.......................................................................................................... 500mW
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute
Maximum Ratings" may cause substantial damage to these devices. Functional operation of
these devices at other conditions beyond those listed in the specification is not implied and
prolonged exposure to extreme conditions may affect devices reliability.
D.C. Characteristics
For data in the following tables, note that factors such as oscillator type, operating voltage, operating
frequency, pin load conditions, temperature and program instruction type, etc., can all exert an
influence on the measured values.
Operating Voltage Characteristics
Ta= -40°C to 85°C
Symbol
Parameter
Operating Voltage – HXT
VDD
Rev. 1.00
Test Conditions
Min.
Typ.
Max.
fSYS=8MHz
2.2
—
5.5
fSYS=12MHz
2.7
—
5.5
Unit
V
fSYS=16MHz
3.3
—
5.5
fSYS=8MHz
2.2
—
5.5
fSYS=12MHz
2.7
—
5.5
fSYS=16MHz
3.3
—
5.5
Operating Voltage – LXT
fSYS=32768Hz
2.2
—
5.5
V
Operating Voltage – LIRC
fSYS=32kHz
2.2
—
5.5
V
Operating Voltage – HIRC
24
V
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Standby Current Characteristics
Ta=25°C
Symbol
Standby Mode
Test Conditions
Min.
Typ.
Max.
—
0.2
0.6
—
0.2
0.8
1
—
0.5
1
1.2
—
1.2
2.4
2.9
—
—
3
3.6
5V
—
—
5
6
2.2V
—
2.4
4
4.8
—
3
5
6
—
5
10
12
—
0.3
0.6
0.8
—
0.5
1.0
1.8
—
1.0
2.0
2.2
—
0.4
0.8
1.0
—
0.6
1.2
1.4
—
1.2
2.4
2.6
—
1.5
3.0
3.2
—
2.0
4.0
4.2
—
0.3
0.6
0.8
—
0.5
1.0
1.2
—
1.0
2.0
2.2
—
0.4
0.8
1.0
—
0.6
1.2
1.4
VDD
Conditions
2.2V
3V
SLEEP Mode
WDT off
5V
2.2V
3V
IDLE0 Mode
3V
WDT on
fSUB on
5V
2.2V
3V
fSUB on, fSYS=8MHz
5V
ISTB
IDLE1 Mode – HIRC
2.7V
3V
fSUB on, fSYS=12MHz
5V
3.3V
5V
fSUB on, fSYS=16MHz
2.2V
3V
fSUB on, fSYS=8MHz
5V
IDLE1 Mode – HXT
Max.
2.7V
3V
fSUB on, fSYS=12MHz
85°C
0.7
5V
—
1.2
2.4
2.6
3.3V
—
1.5
3.0
3.2
—
2.0
4.0
4.2
5V
fSUB on, fSYS=16MHz
Unit μA
μA
μA
mA
mA
mA
mA
mA
mA
Notes: When using the characteristic table data, the following notes should be taken into consideration:
• Any digital inputs are setup in a non floating condition.
• All measurements are taken under conditions of no load and with all peripherals in an off state.
• There are no DC current paths.
• All Standby Current values are taken after a HALT instruction execution thus stopping all instruction
execution.
Rev. 1.00
25
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Operating Current Characteristics
Ta=25°C
Symbol
Operating Mode
Test Conditions
Typ.
Max.
—
8
16
—
10
20
5V
—
30
50
2.2V
—
8
16
—
10
20
—
30
50
1.2
VDD
Conditions
2.2V
SLOW Mode – LXT
SLOW Mode – LIRC
3V
3V
fSYS=32768Hz
fSYS=32kHz
5V
—
0.8
—
1.0
1.5
5V
—
2.0
3.0
2.7V
—
1.2
2.2
—
1.5
2.75
—
3.0
4.5
—
3.2
4.8
—
4.5
7.0
—
0.8
1.2
—
1.0
1.5
—
2.0
3.0
2.2V
3V
FAST Mode – HIRC
IDD
3V
fSYS=8MHz
fSYS=12MHz
5V
3.3V
5V
fSYS=16MHz
2.2V
3V
fSYS=8MHz
5V
FAST Mode – HXT
Min.
2.7V
3V
fSYS=12MHz
5V
3.3V
5V
fSYS=16MHz
—
1.2
2.2
—
1.5
2.75
—
3.0
4.5
—
3.2
4.8
—
4.5
7.0
Unit
μA
μA
mA
mA
mA
mA
mA
mA
Notes: When using the characteristic table data, the following notes should be taken into consideration:
• Any digital inputs are setup in a non floating condition.
• All measurements are taken under conditions of no load and with all peripherals in an off state.
• There are no DC current paths.
• All Operating Current values are measured using a continuous NOP instruction program loop.
Rev. 1.00
26
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
A.C. Characteristics
For data in the following tables, note that factors such as oscillator type, operating voltage, operating
frequency and temperature etc., can all exert an influence on the measured values.
High Speed Internal Oscillator – HIRC – Frequency Accuracy
During the program writing operation the writer will trim the HIRC oscillator at a user selected
HIRC frequency and user selected voltage of either 3V or 5V.
8/12/16MHz
Symbol
Parameter
8MHz Writer Trimmed HIRC
Frequency
12MHz Writer Trimmed HIRC
Frequency
fHIRC
16MHz Writer Trimmed HIRC
Frequency
Test Conditions
VDD
Temp.
3V/5V
2.2V~5.5V
3V/5V
2.7V~5.5V
5V
3.3V~5.5V
Min
Typ
Max
+1%
25°C
-1%
8
-40°C ~ 85°C
-2%
8
+2%
25°C
-2.5%
8
+2.5%
-40°C ~ 85°C
-3%
8
+3%
25°C
-1%
12
+1%
-40°C ~ 85°C
-2%
12
+2%
25°C
-2.5%
12
+2.5%
-40°C ~ 85°C
-3%
12
+3%
25°C
-1%
16
+1%
-40°C ~ 85°C
-2%
16
+2%
25°C
-2.5%
16
+2.5%
-40°C ~ 85°C
-3%
16
+3%
Unit
MHz
MHz
MHz
Notes: 1. The 3V/5V values for VDD are provided as these are the two selectable fixed voltages at which the HIRC
frequency is trimmed by the writer.
2. The row below the 3V/5V trim voltage row is provided to show the values for the full VDD range
operating voltage. It is recommended that the trim voltage is fixed at 3V for application voltage ranges
from 2.2V to 3.3V and fixed at 5V for application voltage ranges from 3.3V to 5.5V.
3. The minimum and maximum tolerance values provided in the table are only for the frequency at which
the writer trims the HIRC oscillator. After trimming at this chosen specific frequency any change in
HIRC oscillator frequency using the oscillator register control bits by the application program will give
a frequency tolerance to within ±20%.
Low Speed Internal Oscillator Characteristics – LIRC
Ta=25°C, unless otherwise specified
Symbol
Parameter
fLIRC
Oscillator Frequency
tSTART
Start Up Time
Test Conditions
VDD
Temp.
2.2V~5.5V
—
Min.
Typ.
Max.
25°C
-2%
32
+2%
-40°C ~ 85°C
-10%
32
+10%
—
—
—
100
Unit
kHz
μs
Low Speed Crystal Oscillator Characteristics – LXT
Ta=25°C
Symbol
fLXT
Parameter
Oscillator Frequency
Duty Cycle Duty Cycle
tSTART
Start Up Time
RNEG
Negative Resistance *
Test Conditions
Conditions
VDD
2.2~5.5V
fSYS=fLXT=32.768kHz
Min.
Typ.
Max.
Unit
-10% 32.768 +10%
kHz
—
—
45
50
55
%
—
—
—
—
500
ms
2.2V
—
3*ESR
—
—
Ω
Note: *: C1, C2 and RP are external components. C1=C2=10pF. RP=10MΩ. CL=7pF, ESR=30kΩ.
Rev. 1.00
27
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Operating Frequency Characteristic Curves
System Operating Frequency
16MHz
12MHz
8MHz
~
~
~
~
~
~
2.2V
2.7V
3.3V
5.5V
Operating Voltage
System Start Up Time Characteristics
Ta=-40°C ~ 85°C
Symbol
Parameter
System Start-up Time
Wake-up from Condition where fSYS is off
tSST
System Start-up Time
Wake-up from Condition where fSYS is on.
Test Conditions
fSYS=fH ~ fH/64, fH=fHXT
—
fSYS=fH ~ fH/64, fH=fHIRC
fSYS=fSUB=fLXT
tRSTD
Typ. Max. Unit
128
—
tHXT
—
16
—
tHIRC
—
1024
—
tLXT
fSYS=fSUB=fLIRC
—
2
—
tLIRC
fSYS=fH ~ fH/64, fH=fHXT or fHIRC
—
2
—
tH
fSYS=fSUB=fLXT or fLIRC
—
2
—
tSUB
fHXT switches from off → on
System Speed Switch Time
fHIRC switches from off → on
FAST to Slow Mode or SLOW to FAST Mode
fLXT switches from off → on
System Reset Delay Time
Reset Source from Power-on Reset or
LVR Hardware Reset
Min.
—
1024
—
tHXT
—
16
—
tHIRC
—
1024
—
tLXT
42
48
54
RRPOR=5V/ms
System Reset Delay Time
LVRC/WDTC/RSTC Software Reset
—
System Reset Delay Time
Reset Source from WDT Overflow
or Reset pin reset
—
ms
14
16
18
Notes: 1. For the System Start-up time values, whether fSYS is on or off depends upon the mode type and the chosen fSYS system oscillator. Details are provided in the System Operating Modes section.
2. The time units, shown by the symbols tHXT, tHIRC etc. are the inverse of the corresponding frequency
values as provided in the frequency tables. For example tHIRC=1/fHIRC, tSYS=1/fSYS etc.
3. If the LIRC is used as the system clock and if it is off when in the SLEEP Mode, then an additional
LIRC start up time, tSTART, as provided in the LIRC frequency table, must be added to the tSST time in the
table above.
4. The System Speed Switch Time is effectively the time taken for the newly activated oscillator to start up.
Rev. 1.00
28
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Input/Output Characteristics
Ta=25°C
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
VIL
Input Low Voltage for I/O Ports 5V
or Input Pins
—
—
0
—
1.5
—
0
—
0.2VDD
VIH
Input High Voltage for I/O
Ports or Input Pins
5V
—
3.5
—
5.0
—
—
0.8VDD
—
VDD
IOL
Sink Current for I/O Pins
16
32
—
32
64
—
3V VOH=0.9VDD, SLEDCn[m+1:m]=00,
5V n=A, B, C, D or E, m=0, 2, 4 or 6
-1.0
-2.0
—
-2.0
-4.0
—
3V VOH=0.9VDD, SLEDCn[m+1:m]=01,
5V n=A, B, C, D or E, m=0, 2, 4 or 6
-1.75
-3.5
—
-3.5
-7.0
—
3V VOH=0.9VDD, SLEDCn[m+1:m]=10,
5V n=A, B, C, D or E, m=0, 2, 4 or 6
-2.5
-5.0
—
-5.0
-10.0
—
3V VOH=0.9VDD, SLEDCn[m+1:m]=11,
5V n=A, B, C, D or E, m=0, 2, 4 or 6
-5.5
-11.0
—
IOH
Source Current for I/O Pins
3V
5V
VOL=0.1VDD
Unit
V
V
mA
mA
-11.0
-22.0
—
RPH
Pull-high Resistance for I/O
Ports(Note)
3V
—
20
60
100
5V
—
10
30
50
ILEAK
Input leakage current
5V VIN=VDD or VIN=VSS
—
—
±1
μA
tTPI
TM Capture Input Minimum
Pulse Width
—
—
0.3
—
—
μs
tTCK
TM Clock Input Minimum
Pulse Width
—
—
0.3
—
—
μs
tINT
Interrupt Input Pin Minimum
Pulse Width
—
—
10
—
—
μs
kΩ
Note: The RPH internal pull high resistance value is calculated by connecting to ground and enabling the input pin
with a pull-high resistor and then measuring the input sink current at the specified supply voltage level.
Dividing the voltage by this measured current provides the RPH value.
Memory Characteristics
Ta=-40°C~85°C
Symbol
VRW
Parameter
VDD for Read / Write
Test Conditions
Min.
Typ.
Max.
Unit
—
VDDmin
—
VDDmax
V
VDD
Conditions
—
Program Flash / Data EEPROM Memory
tDEW
Erase / Write cycle time
—
—
2.2
2.5
2.8
ms
IDDPGM
Programming / Erase current on VDD
—
—
—
—
5.0
mA
EP
Cell Endurance
—
—
100K
—
—
E/W
tRETD
ROM Data Retention time
—
Ta=25°C
—
40
—
Year
—
Device in SLEEP Mode
1.0
—
—
V
RAM Data Memory
VDR
Rev. 1.00
RAM Data Retention voltage
29
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
A/D Converter Characteristics
Ta=25°C
Symbol
Parameter
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
—
—
2.7
—
5.5
V
VADI
Input Voltage
—
—
0
—
VREF
V
VREF
Reference Voltage
—
—
2
—
VDD
V
VREF=VDD, tADCK=0.5μs or 10μs
—
—
±3
LSB
VREF=VDD, tADCK=0.5μs or 10μs
—
—
±4
LSB
—
0.2
0.4
—
0.3
0.6
3V
DNL
Differential Non-linearity
INL
Integral Non-linearity
IADC
Additional Current Consumption
for A/D Converter Enable
3V
tADCK
Clock Period
—
—
0.5
—
10
μs
tADS
Sampling Time
—
—
—
4
—
tADCK
tADC
Conversion Time (Including A/D
Sample and Hold Time)
—
—
—
16
—
tADCK
tON2ST
A/D Converter On-to-Start Time
—
—
μs
IPGA
Additional Current Consumption for
PGA Enable
3V
VCM
PGA Common Mode Voltage Range
VOR
PGA Maximum Output Voltage
Range
3V
5V
VVR
PGA Fix Voltage Output
5V
5V
Rev. 1.00
5V
3V
5V
5V
5V
No load, tADCK =0.5μs
mA
4
—
—
—
300
450
—
400
550
—
VSS 0.3
—
VDD 1.4
V
—
VSS +
0.1
—
VDD 0.1
V
Ta= 25°C
-1%
2
+1%
V
Ta= 25°C
-1%
3
+1%
V
Ta= 25°C
-1%
4
+1%
V
No load
3V
5V
5V
30
μA
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Comparator Electrical Characteristics
Ta=25°C
Symbol
Test Conditions
Parameter
VDD
Conditions
Operating Voltage
—
—
ICMP
Additional Current Consumption
for Comparator Enable
3V
VOS
Input Offset Voltage (Note)
VDD
5V
3V/5V
Min.
CNVTn[1:0]=00
Without calibration,
CNVTn[1:0]=00B, CnOF[4:0]=10000
3V/5V With calibration, CNVTn[1:0]=00B
VCM
Common Mode Voltage Range
AOL
Open Loop Gain
VHYS
Hysteresis
—
3V
5V
3V
5V
3V/5V
3V/5V
tRP
Response Time
3V/5V
3V/5V
CNVTn[1:0]=00
Typ.
Max.
Unit
2.7
—
5.5
V
—
—
3
—
1
3
-10
—
10
-4
—
4
VSS
—
VDD1.4
60
—
—
60
80
—
10
—
30
10
24
30
With 10mV overdrive, CLOAD=3pF,
CNVTn[1:0]=00
—
25
40
With 100mV overdrive, CLOAD=3pF,
CNVTn[1:0]=00
—
20
40
With 10mV overdrive, CLOAD=3pF,
CNVTn[1:0]=01
—
1.5
4
With 100mV overdrive, CLOAD=3pF,
CNVTn[1:0]=01
—
1.2
3
With 10mV overdrive, CLOAD=3pF,
CNVTn[1:0]=10
—
0.8
2
With 100mV overdrive, CLOAD=3pF,
CNVTn[1:0]=10
—
0.5
1.5
With 10mV overdrive, CLOAD=3pF,
CNVTn[1:0]=11
—
0.7
1.5
With 100mV overdrive, CLOAD=3pF,
CNVTn[1:0]=11
—
0.3
1
CNVTn[1:0]=00
CNVTn[1:0]=00
μA
mV
V
dB
mV
μs
Note: The input offset voltage should first be calibrated when the comparator operates with the compared threshold
voltage level lower than 250mV. Otherwise, the input offset voltage will be out of specification.
Software Controlled LCD Driver Electrical Characteristics
Ta=25°C
Symbol
Parameter
Test Conditions
VDD
3V
5V
3V
IBIAS
VDD/2 Bias current
5V
3V
5V
3V
5V
VSCOM
Rev. 1.00
VDD/2 Voltage for LCD SCOM
Output
2.2V~5.5V
Conditions
ISEL[1:0]=00
ISEL[1:0]=01
ISEL[1:0]=10
ISEL[1:0]=11
No load
31
Min.
Typ.
Max.
8
—
16
17.5
25
32.5
18
—
32
35
50
65
35
—
65
70
100
130
70
—
130
140
200
260
0.475VDD 0.5VDD 0.525VDD
Unit
μA
V
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
I2C Characteristics
Ta=25°C
Symbol
Parameter
System Frequency for I2C
Standard Mode (100kHz)
fI2C
System Frequency for I2C Fast
Mode (400kHz)
Test Condition
VDD
Condition
Min.
Typ.
Max.
—
No clock debounce
2
—
—
—
2 system clocks debounce
4
—
—
—
4 system clocks debounce
8
—
—
—
No clock debounce
5
—
—
—
2 system clocks debounce
10
—
—
—
4 system clocks debounce
20
—
—
Unit
MHz
MHz
LVD/LVR Electrical Characteristics
Ta=25°C
Symbol
VLVR
VLVD
Parameter
Low Voltage Reset Voltage
Low Voltage Detect Voltage
Test Conditions
Conditions
VDD
—
—
Min.
Typ.
LVR enabled, voltage select 2.1V
2.1
LVR enabled, voltage select 2.55V
2.55
LVR enabled, voltage select 3.15V
- 5%
3.15
LVR enabled, voltage select 3.8V
3.8
LVD enabled, voltage select 2.0V
2.0
LVD enabled, voltage select 2.2V
2.2
LVD enabled, voltage select 2.4V
2.4
LVD enabled, voltage select 2.7V
LVD enabled, voltage select 3.0V
-5
­ %
2.7
3.0
LVD enabled, voltage select 3.3V
3.3
LVD enabled, voltage select 3.6V
3.6
LVD enabled, voltage select 4.0V
4.0
Max.
Unit
+ 5%
V
+ 5%
V
ILVR
Additional Current
Consumption for LVR Enable
—
LVD disabled, VBGEN=0
—
—
25
μA
ILVD
Additional Current
Consumption for LVD Enable
—
LVR disabled, VBGEN=0
—
—
25
μA
—
For LVR enable, VBGEN=0,
LVD off → on
—
—
15
μs
—
For LVR disable, VBGEN=0,
LVD off → on
—
—
150
μs
tLVDS
LVDO Stable Time
tLVR
Minimum Low Voltage Width to
Reset
—
—
120
240
480
μs
tLVD
Minimum Low Voltage Width to
Interrupt
—
—
60
120
240
μs
Rev. 1.00
32
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Power-on Reset Characteristics
Ta=25°C
Symbol
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VPOR
VDD Start Voltage to Ensure Power-on Reset
—
—
—
—
100
mV
RRPOR
VDD Rising Rate to Ensure Power-on Reset
—
—
0.035
—
—
V/ms
tPOR
Minimum Time for VDD Stays at VPOR to Ensure
Power-on Reset
—
—
1
—
—
ms
VDD
RRPOR
VPOR
Ti�e
tPOR
Rev. 1.00
33
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed
to their internal system architecture. The range of devices take advantage of the usual features found
within RISC microcontrollers providing increased speed of operation and enhanced performance.
The pipelining scheme is implemented in such a way that instruction fetching and instruction
execution are overlapped, hence instructions are effectively executed in one cycle, with the
exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set
operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement,
branch decisions, etc. The internal data path is simplified by moving data through the Accumulator
and the ALU. Certain internal registers are implemented in the Data Memory and can be directly
or indirectly addressed. The simple addressing methods of these registers along with additional
architectural features ensure that a minimum of external components is required to provide a
functional I/O and A/D control system with maximum reliability and flexibility. This makes these
devices suitable for low-cost, high-volume production for controller applications.
Clocking and Pipelining
The main system clock, derived from either a HXT, LXT, HIRC or LIRC oscillator is subdivided
into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented
at the beginning of the T1 clock during which time a new instruction is fetched. The remaining
T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock
cycle forms one instruction cycle. Although the fetching and execution of instructions takes place
in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that
instructions are effectively executed in one instruction cycle. The exception to this are instructions
where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which
case the instruction will take one more instruction cycle to execute.
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
fSYS
(Syste� Clo�k)
Phase Clo�k T1
Phase Clo�k T�
Phase Clo�k T3
Phase Clo�k T4
P�og�a� Counte�
Pipelining
PC
PC+1
Fet�h Inst. (PC)
Exe�ute Inst. (PC-1)
Fet�h Inst. (PC+1)
Exe�ute Inst. (PC)
PC+�
Fet�h Inst. (PC+�)
Exe�ute Inst. (PC+1)
System Clocking and Pipelining
Rev. 1.00
34
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
1
MOV A�[1�H]
�
CALL DELAY
3
CPL [1�H]
4
:
5
:
� DELAY: NOP
Fet�h Inst. 1
Exe�ute Inst. 1
Fet�h Inst. � Exe�ute Inst. �
Fet�h Inst. 3
Flush Pipeline
Fet�h Inst. �
Exe�ute Inst. �
Fet�h Inst. 7
Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the next
instruction to be executed. It is automatically incremented by one each time an instruction is
executed except for instructions, such as "JMP" or "CALL" that demand a jump to a non-consecutive
Program Memory address. For the device whose memory capacity is greater than 8K words the
Program Memory address may be located in a certain program memory bank which is selected by
the program memory bank pointer bits, PBPn. Only the lower 8 bits, known as the Program Counter
Low Register, are directly addressable by the application program.
When executing instructions requiring jumps to non-consecutive addresses such as a jump
instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control
by loading the required address into the Program Counter. For conditional skip instructions, once
the condition has been met, the next instruction, which has already been fetched during the present
instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is
obtained.
Program Counter
Device
High Byte
Low Byte (PCL)
HT66F2350
PC12~PC8
PC7~PC0
HT66F2360
PBP0, PC12~PC8
PC7~PC0
HT66F2370
PBP1~PBP0, PC12~PC8
PC7~PC0
HT66F2390
PBP2~PBP0, PC12~PC8
PC7~PC0
Program Counter
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly; however, as only this low byte
is available for manipulation, the jumps are limited to the present page of memory that is 256
locations. When such program jumps are executed it should also be noted that a dummy cycle
will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is
needed to pre-fetch.
Rev. 1.00
35
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Stack
This is a special part of the memory which is used to save the contents of the Program Counter
only. The stack has multiple levels and is neither part of the data nor part of the program space,
and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is
neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of
the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value
from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but
the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI,
the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use
the structure more easily. However, when the stack is full, a CALL subroutine instruction can still
be executed which will result in a stack overflow. Precautions should be taken to avoid such cases
which might cause unpredictable program branching.
If the stack is overflow, the first Program Counter save in the stack will be lost.
P�og�a� Counte�
Top of Sta�k
Sta�k Level 1
Sta�k Level �
Sta�k
Pointe�
Sta�k Level 3
Botto� of Sta�k
Sta�k Level 1�
:
:
:
P�og�a� Me�o�y
Arithmetic and Logic Unit – ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
• Arithmetic operations:
ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
LADD, LADDM, LADC, LADCM, LSUB, LSUBM, LSBC, LSBCM, LDAA
• Logic operations:
AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
LAND, LOR, LXOR, LANDM, LORM, LXORM, LCPL, LCPLA
• Rotation:
RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
LRRA, LRR, LRRCA, LRRC, LRLA, LRL, LRLCA, LRLC
• Increment and Decrement:
INCA, INC, DECA, DEC
LINCA, LINC, LDECA, LDEC
• Branch decision:
JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
LSZ, LSZA, LSNZ, LSIZ, LSDZ, LSIZA, LSDZA
Rev. 1.00
36
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Flash Program Memory
The Program Memory is the location where the user code or program is stored. For these devices
series the Program Memory are Flash type, which means it can be programmed and re-programmed a
large number of times, allowing the user the convenience of code modification on the same device. By
using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently
debug and develop their applications while also offering a means of field programming and updating.
Device
Capacity
HT66F2350
8K×16
Banks
—
HT66F2360
16K×16
0~1
HT66F2370
32K×16
0~3
HT66F2390
64K×16
0~7
Structure
The Program Memory has a capacity of 8K×16 to 64K×16 bits. The Program Memory is addressed by the
Program Counter and also contains data, table information and interrupt entries. Table data, which can be
setup in any location within the Program Memory, is addressed by a separate table pointer registers.
000H
HT66F2350
HT66F2360
HT66F2370
HT66F2390
Initialisation Vector
Initialisation Vector
Initialisation Vector
Initialisation Vector
Interrupt Vectors
Interrupt Vectors
Interrupt Vectors
Interrupt Vectors
Look-up Table
Look-up Table
Look-up Table
Look-up Table
16 bits
16 bits
16 bits
16 bits
Bank 1
Bank 1
Bank 1
Bank 2
Bank 2
Bank 3
Bank 3
004H
03CH
n00H
nFFH
1FFFH
2000H
3FFFH
4000H
5FFFH
6000H
7FFFH
8000H
Bank 4
9FFFH
A000H
Bank 5
BFFFH
C000H
Bank 6
DFFFH
E000H
Bank 7
FFFFH
Program Memory Structure
Rev. 1.00
37
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The location
000H is reserved for use by these devices reset for program initialisation. After a device reset is
initiated, the program will jump to this location and begin execution.
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can
store fixed data. To use the look-up table, the table pointer must first be setup by placing the address
of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers
define the total address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the Program Memory using
the "TABRD [m]" or "TABRDL [m]" instructions respectively when the memory [m] is located in
sector 0. If the memory [m] is located in other sectors except sector 0, the data can be retrieved from
the program memory using the corresponding extended table read instruction such as "LTABRD [m]"
or "LTABRDL [m]" respectively. When the instruction is executed, the lower order table byte from
the Program Memory will be transferred to the user defined Data Memory register [m] as specified
in the instruction. The higher order table data byte from the Program Memory will be transferred to
the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0".
The accompanying diagram illustrates the addressing data flow of the look-up table.
Program Memory
Add�ess
Last Page o�
TBHP Registe�
TBLP Registe�
Data
1� �its
Registe� TBLH
Use� Sele�ted
Registe�
High Byte
Low Byte
Table Program Example
The accompanying example shows how the table pointer and table data is defined and retrieved from
the device. This example uses raw table data located in the last page which is stored there using the
ORG statement. The value at this ORG statement is "1F00H" which refers to the start address of the
last page within the 8K Program Memory of the device. The table pointer low byte register is setup
here to have an initial value of "06H". This will ensure that the first data read from the data table
will be at the Program Memory address "1F06H" or 6 locations after the start of the last page. Note
that the value for the table pointer is referenced to the first address of the present page pointed by the
TBHP register if the "TABRD [m]" instruction is being used. The high byte of the table data which in
this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m]"
instruction is executed.
Because the TBLH register is a read/write register and can be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
Rev. 1.00
38
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Table Read Program Example
tempreg1 db ? ; temporary register #1
tempreg2 db ? ; temporary register #2
:
mov a,06h ; initialise low table pointer - note that this address is referenced
mov tblp,a ; to the last page or the page that tbhp pointed
mov a,1fh ; initialise high table pointer
movtbhp,a
:
tabrd tempreg1 ; transfers value in table referenced by table pointer data at program
; memory address "1F06H" transferred to tempreg1 and TBLH
dec tblp ; reduce value of table pointer by one
tabrd tempreg2 ; transfers value in table referenced by table pointer data at program
; memory address "1F05H" transferred to tempreg2 and TBLH in this
; example the data "1AH" is transferred to tempreg1 and data "0FH" to
; register tempreg2
:
org 1F00h ; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
In Circuit Programming – ICP
The provision of Flash type Program Memory provides the user with a means of convenient and
easy upgrades and modifications to their programs on the same device.
As an additional convenience, Holtek has provided a means of programming the microcontroller incircuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing
their circuit boards complete with a programmed or un-programmed microcontroller, and then
programming or upgrading the program at a later stage. This enables product manufacturers to easily
keep their manufactured products supplied with the latest program releases without removal and reinsertion of the device.
Holtek Writer Pins
MCU Programming Pins
ICPDA
PA0
Programming Serial Data/Address
Pin Description
ICPCK
PA2
Programming Clock
VDD
VDD
Power Supply
VSS
VSS
Ground
The Program Memory and EEPROM data memory can be programmed serially in-circuit using this
4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line
for the clock. Two additional lines are required for the power supply. The technical details regarding
the in-circuit programming of the device are beyond the scope of this document and will be supplied
in supplementary literature.
During the programming process, the user must take care of the ICPDA and ICPCK pins for data
and clock programming purposes to ensure that no other outputs are connected to these two pins.
Rev. 1.00
39
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
W�ite� Conne�to�
Signals
MCU P�og�a��ing
Pins
W�ite�_VDD
VDD
ICPDA
PA0
ICPCK
PA�
W�ite�_VSS
VSS
*
*
To othe� Ci��uit
Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance
of * must be less than 1nF.
On-Chip Debug Support – OCDS
There is an EV chip named HT66V23x0 which is used to emulate the real MCU device named
HT66F23x0. The EV chip device also provides the "On-Chip Debug" function to debug the real
MCU device during development process. The EV chip and real MCU devices, HT66V23x0 and
HT66F23x0, are almost functional compatible except the "On-Chip Debug" function. Users can
use the EV chip device to emulate the real MCU device behaviors by connecting the OCDSDA
and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS
Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users
use the EV chip device for debugging, the corresponding pin functions shared with the OCDSDA
and OCDSCK pins in the real MCU device will have no effect in the EV chip. However, the two
OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory
programming pins for ICP. For more detailed OCDS information, refer to the corresponding
document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide".
Rev. 1.00
Holtek e-Link Pins
EV Chip OCDS Pins
OCDSDA
OCDSDA
On-Chip Debug Support Data/Address input/output
OCDSCK
OCDSCK
On-Chip Debug Support Clock input
VDD
VDD
Power Supply
VSS
VSS
Ground
40
Pin Description
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
In Application Programming – IAP
These devices offer IAP function to update data or application program to flash ROM. Users can
define any ROM location for IAP, but there are some features which user must notice in using IAP
function.
HT66F2350
Configurations
HT66F2360/HT66F2370
Configurations
HT66F2390
Configurations
Erase Page
32 words / page
Erase Page
64 words / page
Erase Page
128 words / page
Writing Word
32 words / time
Writing Word
64 words / time
Writing Word
128 words / time
Reading Word
1 word / time
Reading Word
1 word / time
Reading Word
1 word / time
In Application Programming Control Registers
The Address register, FARL and FARH, the Data registers, FD0L/FD0H, FD1L/FD1H, FD2L/FD2H
and FD3L/FD3H, and the Control registers, FC0, FC1 and FC2, are the corresponding Flash access
registers located in Data Memory sector 0 and sector 1 respectively for IAP. If using the indirect
addressing method to access the FC0, FC1 and FC2 registers, all read and write operations to the
registers must be performed using the Indirect Addressing Register, IAR1 or IAR2, and the Memory
Pointer pair, MP1L/MP1H or MP2L/MP2H. Because the FC0, FC1 and FC2 control registers are
located at the address of 43H~45H in Data Memory sector 1, the desired value ranged from 43H to
45H must first be written into the MP1L or MP2L Memory Pointer low byte and the value "01H"
must also be written into the MP1H or MP2H Memory Pointer high byte.
Register Name
FC0
Bit
7
6
5
4
3
CFWEN FMOD2 FMOD1 FMOD0 FWPEN
2
1
0
FWT
FRDEN
FRD
FC1
D7
D6
D5
D4
D3
D2
D1
D0
FC2
—
—
—
—
—
—
—
CLWB
A0
FARL
A7
A6
A5
A4
A3
A2
A1
FARH (HT66F2350)
—
—
—
A12
A11
A10
A9
A8
FARH (HT66F2360)
—
—
A13
A12
A11
A10
A9
A8
A8
FARH (HT66F2370)
—
A14
A13
A12
A11
A10
A9
FARH (HT66F2390)
A15
A14
A13
A12
A11
A10
A9
A8
FD0L
D7
D6
D5
D4
D3
D2
D1
D0
FD0H
D15
D14
D13
D12
D11
D10
D9
D8
FD1L
D7
D6
D5
D4
D3
D2
D1
D0
FD1H
D15
D14
D13
D12
D11
D10
D9
D8
FD2L
D7
D6
D5
D4
D3
D2
D1
D0
FD2H
D15
D14
D13
D12
D11
D10
D9
D8
FD3L
D7
D6
D5
D4
D3
D2
D1
D0
FD3H
D15
D14
D13
D12
D11
D10
D9
D8
IAP Registers List
Rev. 1.00
41
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
• FC0 Register
Bit
7
6
5
4
3
2
1
0
Name
CFWEN
FMOD2
FMOD1
FMOD0
FWPEN
FWT
FRDEN
FRD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7CFWEN: Flash Memory Write enable control
0: Flash memory write function is disabled
1: Flash memory write function has been successfully enabled
When this bit is cleared to 0 by application program, the Flash memory write function
is disabled. Note that writing a "1" into this bit results in no action. This bit is used
to indicate that the Flash memory write function status. When this bit is set to 1 by
hardware, it means that the Flash memory write function is enabled successfully.
Otherwise, the Flash memory write function is disabled as the bit content is zero.
Bit 6~4FMOD2~FMOD0: Mode selection
000: Write program memory
001: Page erase program memory
010: Reserved
011: Read program memory
10x: Reserved
110: FWEN mode – Flash memory Write function Enabled mode
111: Reserved
Bit 3FWPEN: Flash memory Write Procedure Enable control
0: Disable
1: Enable
When this bit is set to 1 and the FMOD field is set to "110", the IAP controller will
execute the "Flash memory write function enable" procedure. Once the Flash memory
write function is successfully enabled, it is not necessary to set the FWPEN bit any
more.
Bit 2FWT: Flash memory Write Initiate control
0: Do not initiate Flash memory write or Flash memory write process is completed
1: Initiate Flash memory write process
This bit is set by software and cleared by hardware when the Flash memory write
process is completed.
Bit 1FRDEN: Flash memory Read Enable control
0: Flash memory read disable
1: Flash memory read enable
Bit 0FRD: Flash memory Read Initiate control
0: Do not initiate Flash memory read or Flash memory read process is completed
1: Initiate Flash memory read process
This bit is set by software and cleared by hardware when the Flash memory read
process is completed.
• FC1 Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: Whole chip reset pattern
When user writes a specific value of "55H" to this register, it will generate a reset
signal to reset whole chip.
Rev. 1.00
42
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
• FC2 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
CLWB
R/W
—
—
—
—
—
—
—
R/W
POR
—
—
—
—
—
—
—
0
Bit 7~1
Unimplemented, read as "0"
Bit 0CLWB: Flash memory Write Buffer Clear control
0: Do not initiate Write Buffer Clear process or Write Buffer Clear process is completed
1: Initiate Write Buffer Clear process
This bit is set by software and cleared by hardware when the Write Buffer Clear
process is completed.
• FARL Register
Bit
7
6
5
4
3
2
1
0
Name
A7
A6
A5
A4
A3
A2
A1
A0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Flash Memory Address bit 7 ~ bit 0
• FARH Register – HT66F2350
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
A12
A11
A10
A9
A8
R/W
—
—
—
R/W
R/W
R/W
R/W
R/W
POR
—
—
—
0
0
0
0
0
Bit 7~5
Unimplemented, read as "0"
Bit 4~0
Flash Memory Address bit 12 ~ bit 8
• FARH Register – HT66F2360
Bit
7
6
5
4
3
2
1
0
Name
—
—
A13
A12
A11
A10
A9
A8
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Unimplemented, read as "0"
Bit 5~0
Flash Memory Address bit 13 ~ bit 8
• FARH Register – HT66F2370
Bit
7
6
5
4
3
2
1
0
Name
—
A14
A13
A12
A11
A10
A9
A8
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
3
2
1
0
Bit 7
Unimplemented, read as "0"
Bit 6~0
Flash Memory Address bit 14 ~ bit 8
• FARH Register – HT66F2390
Bit
6
5
4
Name
A15
A14
A13
A12
A11
A10
A9
A8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
7
Flash Memory Address bit 15 ~ bit 8
43
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
• FD0L Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The first Flash Memory data bit 7 ~ bit 0
Note that the data written into the low byte data register FD0L will only be stored in
the FD0L register and not be loaded into the lower 8-bit write buffer.
• FD0H Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The first Flash Memory data bit 15 ~ bit 8
Note that when the 8-bit data is written into the high byte data register FD0H, the
whole 16-bit data stored in the FD0H and FD0L registers will simultaneously be
loaded into the 16-bit write buffer and then the content of the Flash Memory address
register pair, FARH and FARL, will be incremented by one.
• FD1L Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The second Flash Memory data bit 7 ~ bit 0
• FD1H Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The second Flash Memory data bit 15 ~ bit 8
• FD2L Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The third Flash Memory data bit 7 ~ bit 0
• FD2H Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
The third Flash Memory data bit 15 ~ bit 8
44
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
• FD3L Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The fourth Flash Memory data bit 7 ~ bit 0
• FD3H Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The fourth Flash Memory data bit 15 ~ bit 8
Flash Memory Write Function Enable Procedure
In order to allow users to change the Flash memory data through the IAP control registers, users
must first enable the Flash memory write operation by the following procedure:
Step 1. Write "110" into the FMOD2~FMOD0 bits to select the FWEN mode.
Step 2. Set the FWPEN bit to "1". The step 1 and step 2 can be executed simultaneously.
Step 3. The pattern data with a sequence of 00H, 04H, 0DH, 09H, C3H and 40H must be written
into the FD1L, FD1H, FD2L, FD2H, FD3L and FD3H registers respectively.
Step 4. A counter with a time-out period of 300μs will be activated to allow users writing the correct
pattern data into the FD1L/FD1H ~ FD3L/FD3H register pairs. The counter clock is derived
from the LIRC oscillator.
Step 5. If the counter overflows or the pattern data is incorrect, the Flash memory write operation
will not be enabled and users must again repeat the above procedure. Then the FWPEN bit
will automatically be cleared to 0 by hardware.
Step 6. If the pattern data is correct before the counter overflows, the Flash memory write operation
will be enabled and the FWPEN bit will automatically be cleared to 0 by hardware. The
CFWEN bit will also be set to 1 by hardware to indicate that the Flash memory write
operation is successfully enabled.
Step 7. Once the Flash memory write operation is enabled, the user can change the Flash ROM data
through the Flash control register.
Step 8. To disable the Flash memory write operation, the user can clear the CFWEN bit to 0.
Rev. 1.00
45
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Is �ounte�
ove�flow ?
Flash Me�o�y
W�ite Fun�tion
Ena�le P�o�edu�e
No
Yes
FWPEN=0
Set FMOD [�:0] =110 & FWPEN=1
Sele�t FWEN �ode & Sta�t Flash w�ite
Ha�dwa�e a�tivate a �ounte�
Is patte�n
�o��e�t ?
W�tie the following patte�n to Flash Data �egiste�s
FD1L= 00h � FD1H = 04h
FD�L= 0Dh � FD�H = 09h
FD3L= C3h � FD3H = 40h
No
Yes
CFWEN = 1
CFWEN=0
Success
Failed
END
Flash Memory Write Function Enable Procedure
Flash Memory Read/Write Procedure
After the Flash memory write function is successfully enabled through the preceding IAP procedure,
users must first erase the corresponding Flash memory block or page and then initiate the Flash
memory write operation. For these devices the number of the page erase operation is 32, 64 and 128
words per page respectively, the available page erase address is specified by FARH register and the
content of FARL [7:5], FARL [7:6] and FARL [7] bit field respectively.
Erase Page
FARH
FARL [7:5]
0
0000 0000
000
FARL [4:0]
x xxxx
1
0000 0000
001
x xxxx
2
0000 0000
010
x xxxx
3
0000 0000
011
x xxxx
4
0000 0000
100
x xxxx
:
:
:
:
:
:
:
:
254
0001 1111
110
x xxxx
255
0001 1111
111
x xxxx
"x": don’t care
HT66F2350 Erase Page Number and Selection
Rev. 1.00
46
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Erase Page
FARH
FARL [7:6]
0
0000 0000
00
FARL [5:0]
xx xxxx
1
0000 0000
01
xx xxxx
2
0000 0000
10
xx xxxx
3
0000 0000
11
xx xxxx
4
0000 0001
00
xx xxxx
:
:
:
:
:
:
:
:
254
0011 1111
10
xx xxxx
255
0011 1111
11
xx xxxx
"x": don’t care
HT66F2360 Erase Page Number and Selection
Erase Page
FARH
FARL [7:6]
0
0000 0000
00
FARL [5:0]
xx xxxx
1
0000 0000
01
xx xxxx
2
0000 0000
10
xx xxxx
3
0000 0000
11
xx xxxx
4
0000 0001
00
xx xxxx
:
:
:
:
:
:
:
:
510
0111 1111
10
xx xxxx
511
0111 1111
11
xx xxxx
"x": don’t care
HT66F2370 Erase Page Number and Selection
Erase Page
FARH
FARL [7]
FARL [6:0]
0
0000 0000
0
xxx xxxx
1
0000 0000
1
xxx xxxx
2
0000 0001
0
xxx xxxx
3
0000 0001
1
xxx xxxx
4
0000 0010
0
xxx xxxx
:
:
:
:
:
:
:
:
510
1111 1111
0
xxx xxxx
511
1111 1111
1
xxx xxxx
"x": don’t care
HT66F2390 Erase Page Number and Selection
Rev. 1.00
47
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Read
Flash Memory
Set FMOD [2:0]=011
& FRDEN=1
Set Flash Address registers
FARH=xxh, FARL=xxh
Set FRD=1
No
FRD=0 ?
Yes
Read data value:
FD0L=xxh, FD0H=xxh
Read Finish ?
No
Yes
Clear FRDEN bit
END
Read Flash Memory Procedure
Rev. 1.00
48
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Write
Flash Memory
Flash Memory
Write Function
Enable Procedure
Set Page Erase address: FARH/FARL
Set FMOD [2:0]=001 & FWT=1
à Select “Page Erase mode”
& Initiate write operation
No
FWT=0 ?
Yes
Set FMOD [2:0]=000
à Select “Write Flash Mode”
Set Write starting address: FARH/FARL
Write data to data register: FD0L/FD0H
No
Page data
Write finish
Yes
Set FWT=1
No
FWT=0 ?
Yes
Write Finish ?
No
Yes
Clear CFWEN=0
END
Write Flash Memory Procedure
Note: When the FWT or FRD bit is set to 1, the MCU is stopped.
Rev. 1.00
49
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Data Memory
The Data Memory is an 8-bit wide RAM internal memory and is the location where temporary
information is stored.
Divided into two types, the first of Data Memory is an area of RAM where special function registers
are located. These registers have fixed locations and are necessary for correct operation of the
device. Many of these registers can be read from and written to directly under program control,
however, some remain protected from user manipulation. The second area of Data Memory is
reserved for general purpose use. All locations within this area are read and write accessible under
program control.
Switching between the different Data Memory sectors is achieved by properly setting the Memory
Pointers to correct value.
Structure
The Data Memory is subdivided into several sectors, all of which are implemented in 8-bit wide
Memory. Each of the Data Memory sectors is categorized into two types, the Special Purpose Data
Memory and the General Purpose Data Memory.
The address range of the Special Purpose Data Memory for the device is from 00H to 7FH while the
General Purpose Data Memory address range is from 80H to FFH.
Device
Special Purpose
Data Memory
General Purpose
Data Memory
Sectors
Capacity
Sector : Address
HT66F2350
0, 1
768×8
0: 80H~FFH
1: 80H~FFH
:
5: 80H~FFH
HT66F2360
0, 1
1536×8
0: 80H~FFH
1: 80H~FFH
:
11: 80H~FFH
3072×8
0: 80H~FFH
1: 80H~FFH
:
23: 80H~FFH
4096×8
0: 80H~FFH
1: 80H~FFH
:
31: 80H~FFH
HT66F2370
HT66F2390
0, 1
0, 1
Data Memory Summary
Rev. 1.00
50
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
00H
Special Purpose
Data Memory
(Sector 0 ~ Sector 1)
7FH
80H
General Purpose
Data Memory
(Sector 0 ~ Sector N)
FFH
Sector 0
Sector 1
Sector N
Note: N= 5 for HT66F2350;
N=11 for HT66F2360;
N=23 for HT66F2370;
N=31 for HT66F2390
Data Memory Structure
Data Memory Addressing
For these devices that support the extended instructions, there is no Bank Pointer for Data Memory.
The Bank Pointer, PBP, is only available for Program Memory. For Data Memory the desired Sector
is pointed by the MP1H or MP2H register and the certain Data Memory address in the selected
sector is specified by the MP1L or MP2L register when using indirect addressing access.
Direct Addressing can be used in all sectors using the corresponding instruction which can address
all available data memory space. For the accessed data memory which is located in any data
memory sectors except sector 0, the extended instructions can be used to access the data memory
instead of using the indirect addressing access. The main difference between standard instructions
and extended instructions is that the data memory address "m" in the extended instructions can be
from 11 bits to 13 bits depending upon which device is selected, the high byte indicates a sector and
the low byte indicates a specific address.
General Purpose Data Memory
All microcontroller programs require an area of read/write memory where temporary data can be
stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose
Data Memory. This area of Data Memory is fully accessible by the user programming for both
reading and writing operations. By using the bit operation instructions individual bits can be set or
reset under program control giving the user a large range of flexibility for bit manipulation in the
Data Memory.
Special Purpose Data Memory
This area of Data Memory is where registers, necessary for the correct operation of the
microcontroller, are stored. Most of the registers are both readable and writeable but some are
protected and are readable only, the details of which are located under the relevant Special Function
Register section. Note that for locations that are unused, any read instruction to these addresses will
return the value "00H".
Rev. 1.00
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HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Sector 0
IAR0
MP0
IAR1
MP1L
MP1H
ACC
PCL
TBLP
TBLH
TBHP
STATUS
IAR2
MP2L
MP2H
RSTFC
INTC0
INTC1
INTC2
INTC3
PA
PAC
PAPU
PAWU
PB
PBC
PBPU
PC
PCC
PCPU
PD
PDC
PDPU
PE
PEC
PEPU
PF
PFC
PFPU
PMPS
RSTC
VBGRC
MFI0
MFI1
MFI2
MFI3
MFI4
MFI5
INTEG
SCC
HIRCC
HXTC
LXTC
WDTC
LVRC
Sector 1
CRCCR
CRCIN
CRCDL
CRCDH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
IECC
U0SR
U0CR1
U0CR2
TXR_RXR0
BRG0
U1SR
U1CR1
U1CR2
TXR_RXR1
BRG1
PTM1C0
PTM1C1
PTM1DL
PTM1DH
PTM1AL
PTM1AH
PTM1RPL
PTM1RPH
PTM2C0
PTM2C1
PTM2DL
PTM2DH
PTM2AL
PTM2AH
PTM2RPL
PTM2RPH
PTM3C0
PTM3C1
PTM3DL
PTM3DH
PTM3AL
PTM3AH
PTM3RPL
PTM3RPH
STM1C0
STM1C1
STM1DL
STM1DH
STM1AL
STM1AH
STM1RP
STM2C0
STM2C1
STM2DL
STM2DH
STM2AL
STM2AH
STM2RP
Sector 0
LVDC
EEA
Sector 1
EEC
EED
CP0C
CP1C
PTM0C0
PTM0C1
PTM0DL
PTM0DH
PTM0AL
PTM0AH
PTM0RPL
PTM0RPH
STM0C0
STM0C1
STM0DL
STM0DH
STM0AL
STM0AH
STM0RP
SLEDC0
SLEDC1
SLEDC2
FC0
FC1
FC2
MDUWR0
MDUWR1
MDUWR2
MDUWR3
MDUWR4
MDUWR5
MDUWCTRL
CP0VOS
CP1VOS
IFS0
IFS1
IFS2
IFS3
PAS0
PAS1
PBS0
PBS1
PCS0
PCS1
PDS0
PDS1
PES0
PES1
PFS0
PFS1
PSC0R
TB0C
TB1C
PSC1R
SADOL
SADOH
SADC0
SADC1
SADC2
SIMC0
SIMC1
SIMD
SIMA/SIMC2
SIMTOC
SPIAC0
SPIAC1
SPIAD
FARL
FARH
FD0L
FD0H
FD1L
FD1H
FD2L
FD2H
FD3L
FD3H
SCOMC
: Unused, read as 00H
Special Purpose Data Memory Structure – HT66F2350
Rev. 1.00
52
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HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Sector 0
IAR0
MP0
IAR1
MP1L
MP1H
ACC
PCL
TBLP
TBLH
TBHP
STATUS
PBP
IAR2
MP2L
MP2H
RSTFC
INTC0
INTC1
INTC2
INTC3
PA
PAC
PAPU
PAWU
PB
PBC
PBPU
PC
PCC
PCPU
PD
PDC
PDPU
PE
PEC
PEPU
PF
PFC
PFPU
PG
PGC
PGPU
PH
PHC
PHPU
PMPS
RSTC
VBGRC
MFI0
MFI1
MFI2
MFI3
MFI4
MFI5
INTEG
SCC
HIRCC
HXTC
LXTC
WDTC
LVRC
Sector 1
CRCCR
CRCIN
CRCDL
CRCDH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
IECC
U0SR
U0CR1
U0CR2
TXR_RXR0
BRG0
U1SR
U1CR1
U1CR2
TXR_RXR1
BRG1
PTM1C0
PTM1C1
PTM1DL
PTM1DH
PTM1AL
PTM1AH
PTM1RPL
PTM1RPH
PTM2C0
PTM2C1
PTM2DL
PTM2DH
PTM2AL
PTM2AH
PTM2RPL
PTM2RPH
PTM3C0
PTM3C1
PTM3DL
PTM3DH
PTM3AL
PTM3AH
PTM3RPL
PTM3RPH
STM1C0
STM1C1
STM1DL
STM1DH
STM1AL
STM1AH
STM1RP
STM2C0
STM2C1
STM2DL
STM2DH
STM2AL
STM2AH
STM2RP
Sector 0
LVDC
EEA
Sector 1
EEC
EED
CP0C
CP1C
PTM0C0
PTM0C1
PTM0DL
PTM0DH
PTM0AL
PTM0AH
PTM0RPL
PTM0RPH
STM0C0
STM0C1
STM0DL
STM0DH
STM0AL
STM0AH
STM0RP
SLDEC0
SLDEC1
SLDEC2
SLDEC3
MDUWR0
MDUWR1
MDUWR2
MDUWR3
MDUWR4
MDUWR5
MDUWCTRL
CP0VOS
CP1VOS
FC0
FC1
FC2
IFS0
IFS1
IFS2
IFS3
PAS0
PAS1
PBS0
PBS1
PCS0
PCS1
PDS0
PDS1
PES0
PES1
PFS0
PFS1
PGS0
PGS1
PHS0
PHS1
PSC0R
TB0C
TB1C
PSC1R
SADOL
SADOH
SADC0
SADC1
SADC2
SIMC0
SIMC1
SIMD
SIMA/SIMC2
SIMTOC
SPIAC0
SPIAC1
SPIAD
FARL
FARH
FD0L
FD0H
FD1L
FD1H
FD2L
FD2H
FD3L
FD3H
SCOMC
: Unused, read as 00H
Special Purpose Data Memory Structure – HT66F2360
Rev. 1.00
53
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Sector 0
IAR0
MP0
IAR1
MP1L
MP1H
ACC
PCL
TBLP
TBLH
TBHP
STATUS
PBP
IAR2
MP2L
MP2H
RSTFC
INTC0
INTC1
INTC2
INTC3
PA
PAC
PAPU
PAWU
PB
PBC
PBPU
PC
PCC
PCPU
PD
PDC
PDPU
PE
PEC
PEPU
PF
PFC
PFPU
PG
PGC
PGPU
PH
PHC
PHPU
PMPS
RSTC
VBGRC
MFI0
MFI1
MFI2
MFI3
MFI4
MFI5
INTEG
SCC
HIRCC
HXTC
LXTC
WDTC
LVRC
Sector 1
CRCCR
CRCIN
CRCDL
CRCDH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
IECC
U2SR
U2CR1
U2CR2
TXR_RXR2
BRG2
U0SR
U0CR1
U0CR2
TXR_RXR0
BRG0
U1SR
U1CR1
U1CR2
TXR_RXR1
BRG1
PTM1C0
PTM1C1
PTM1DL
PTM1DH
PTM1AL
PTM1AH
PTM1RPL
PTM1RPH
PTM2C0
PTM2C1
PTM2DL
PTM2DH
PTM2AL
PTM2AH
PTM2RPL
PTM2RPH
PTM3C0
PTM3C1
PTM3DL
PTM3DH
PTM3AL
PTM3AH
PTM3RPL
PTM3RPH
STM1C0
STM1C1
STM1DL
STM1DH
STM1AL
STM1AH
STM1RP
STM2C0
STM2C1
STM2DL
STM2DH
STM2AL
STM2AH
STM2RP
Sector 0
LVDC
EEAL
EEAH
EED
CP0C
CP1C
PTM0C0
PTM0C1
PTM0DL
PTM0DH
PTM0AL
PTM0AH
PTM0RPL
PTM0RPH
STM0C0
STM0C1
STM0DL
STM0DH
STM0AL
STM0AH
STM0RP
SLDEC0
SLDEC1
SLDEC2
SLDEC3
MDUWR0
MDUWR1
MDUWR2
MDUWR3
MDUWR4
MDUWR5
MDUWCTRL
CP0VOS
CP1VOS
Sector 1
EEC
FC0
FC1
FC2
IFS0
IFS1
IFS2
IFS3
PAS0
PAS1
PBS0
PBS1
PCS0
PCS1
PDS0
PDS1
PES0
PES1
PFS0
PFS1
PGS0
PGS1
PHS0
PHS1
PSC0R
TB0C
TB1C
PSC1R
SADOL
SADOH
SADC0
SADC1
SADC2
SIMC0
SIMC1
SIMD
SIMA/SIMC2
SIMTOC
SPIAC0
SPIAC1
SPIAD
FARL
FARH
FD0L
FD0H
FD1L
FD1H
FD2L
FD2H
FD3L
FD3H
SCOMC
: Unused, read as 00H
Special Purpose Data Memory Structure – HT66F2370/HT66F2390
Rev. 1.00
54
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Special Function Register Description
Most of the Special Function Register details will be described in the relevant functional section.
However, several registers require a separate description in this section.
Indirect Addressing Registers – IAR0, IAR1, IAR2
The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal
RAM register space, do not actually physically exist as normal registers. The method of indirect
addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers,
in contrast to direct memory addressing, where the actual memory address is specified. Actions on
the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to these registers
but rather to the memory location specified by their corresponding Memory Pointers, MP0, MP1L/
MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data only from Sector
0 while the IAR1 register together with MP1L/MP1H register pair and IAR2 register together with
MP2L/MP2H register pair can access data from any Data Memory sector. As the Indirect Addressing
Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will
return a result of "00H" and writing to the registers indirectly will result in no operation.
Memory Pointers – MP0, MP1H/MP1L, MP2H/MP2L
Five Memory Pointers, known as MP0, MP1L, MP1H, MP2L and MP2H, are provided. These
Memory Pointers are physically implemented in the Data Memory and can be manipulated in the
same way as normal registers providing a convenient way with which to address and track data.
When any operation to the relevant Indirect Addressing Registers is carried out, the actual address
that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0,
together with Indirect Addressing Register, IAR0, are used to access data from Sector 0, while
MP1L/MP1H together with IAR1 and MP2L/MP2H together with IAR2 are used to access data
from all data sectors according to the corresponding MP1H or MP2H register. Direct Addressing can
be used in all data sectors using the corresponding instruction which can address all available data
memory space.
Indirect Addressing Program Example
• Example 1
data .section ‘data’
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 code
org 00h
start:
mov a,04h;
mov block,a
mov a,offset adres1 ;
mov mp0,a ;
loop:
clr IAR0 ;
inc mp0;
sdz block ;
jmp loop
continue:
:
Rev. 1.00
setup size of block
Accumulator loaded with first RAM address
setup memory pointer with first RAM address
clear the data at address defined by MP0
increment memory pointer
check if last memory location has been cleared
55
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
• Example 2
data .section ‘data’
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 ‘code’
org 00h
start:
mov a,04h;
mov block,a
mov a,01h;
mov mp1h,a
mov a,offset adres1 ;
mov mp1l,a ;
loop:
clr IAR1 ;
inc mp1l ;
sdz block ;
jmp loop
continue:
:
setup size of block
setup the memory sector
Accumulator loaded with first RAM address
setup memory pointer with first RAM address
clear the data at address defined by MP1L
increment memory pointer MP1L
check if last memory location has been cleared
The important point to note here is that in the example shown above, no reference is made to specific
RAM addresses.
Direct Addressing Program Example using extended instructions
data .section ‘data’
temp db ?
code .section at 0 code
org 00h
start:
lmov
a,[m]; move [m] data to acc
lsuba, [m+1] ; compare [m] and [m+1] data
snz
c; [m]>[m+1]?
jmp continue; no
lmov
a,[m]; yes, exchange [m] and [m+1] data
movtemp,a
lmova,[m+1]
lmov[m],a
mova,temp
lmov[m+1],a
continue:
:
Note: Here "m" is a data memory address located in any data memory sectors. For example,
m=1F0H, it indicates address 0F0H in Sector 1.
Rev. 1.00
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Program Memory Bank Pointer – PBP
For the series of devices the Program Memory is divided into several banks except for the
HT66F2350 device. Selecting the required Program Memory area is achieved using the Program
Memory Bank Pointer, PBP. The PBP register should be properly configured before the device
executes the "Branch" operation using the "JMP" or "CALL" instruction. After that a jump to a nonconsecutive Program Memory address which is located in a certain bank selected by the program
memory bank pointer bits will occur.
PBP Register – HT66F2360
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
PBP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~1D7~D1: General data bits and can be read or written.
Bit 0PBP0: Program Memory Bank Point bit 0
0: Bank 0
1: Bank 1
PBP Register – HT66F2370
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
PBP1
PBP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~2D7~D2: General data bits and can be read or written.
Bit 1~0PBP1~PBP0: Program Memory Bank Point bit 1 ~ bit 0
00: Bank 0
01: Bank 1
10: Bank 2
11: Bank 3
PBP Register – HT66F2390
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
PBP2
PBP1
PBP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~3D7~D3: General data bits and can be read or written.
Bit 2~0PBP2~PBP0: Program Memory Bank Point bit 2 ~ bit 0
000: Bank 0
001: Bank 1
010: Bank 2
011: Bank 3
100: Bank 4
101: Bank 5
110: Bank 6
111: Bank 7
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
Accumulator – ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user-defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.
Program Counter Low Register – PCL
To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location;
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
Look-up Table Registers – TBLP, TBHP, TBLH
These three special function registers are used to control operation of the look-up table which
is stored in the Program Memory. The TBLP and TBHP registers are the table pointer pair and
indicates the location where the table data is located. Their value must be setup before any table
read instructions are executed. Their value can be changed, for example using the "INC" or "DEC"
instructions, allowing for easy table data pointing and reading. TBLH is the location where the high
order byte of the table data is stored after a table read data instruction has been executed. Note that
the lower order table data byte is transferred to a user defined location.
Rev. 1.00
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Status Register – STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), SC flag, CZ flag, power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/
logical operation and system management flags are used to record the status and operation of the
microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing
the "HALT" or "CLR WDT" instruction or during a system power-up.
The Z, OV, AC, C, SC and CZ flags generally reflect the status of the latest operations.
• C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through
carry instruction.
• AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
• Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
• OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
• PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by
executing the "HALT" instruction.
• TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is
set by a WDT time-out.
• SC is the result of the "XOR" operation which is performed by the OV flag and the MSB of the
current instruction operation result.
• CZ is the operational result of different flags for different instructions. Refer to register
definitions for more details.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and if
the subroutine can corrupt the status register, precautions must be taken to correctly save it.
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
SC
CZ
TO
PDF
OV
Z
AC
C
R/W
R
R
R
R
R/W
R/W
R/W
R/W
POR
x
x
0
0
x
x
x
x
"x": unknown
Bit 7SC: The result of the "XOR" operation which is performed by the OV flag and the
MSB of the instruction operation result.
Bit 6CZ: The operational result of different flags for different instructions.
For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag.
For SBC/ SBCM/ LSBC/ LSBCM instructions, the CZ flag is the "AND" operation
result which is performed by the previous operation CZ flag and current operation zero
flag. For other instructions, the CZ flag will not be affected.
Bit 5TO: Watchdog Time-out flag
0: After power up or executing the "CLR WDT" or "HALT" instruction
1: A watchdog time-out occurred
Bit 4PDF: Power down flag
0: After power up or executing the "CLR WDT" instruction
1: By executing the "HALT" instruction
Bit 3OV: Overflow flag
0: No overflow
1: An operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa
Bit 2Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Bit 1AC: Auxiliary flag
0: No auxiliary carry
1: An operation results in a carry out of the low nibbles, in addition, or no borrow
from the high nibble into the low nibble in subtraction
Bit 0C: Carry flag
0: No carry-out
1: An operation results in a carry during an addition operation or if a borrow does
not take place during a subtraction operation
The "C" flag is also affected by a rotate through carry instruction.
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Advanced A/D Flash MCU with EEPROM
EEPROM Data Memory
These devices contain an area of internal EEPROM Data Memory. EEPROM, which stands for
Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form
of re-programmable memory, with data retention even when its power supply is removed. By
incorporating this kind of data memory, a whole new host of application possibilities are made
available to the designer. The availability of EEPROM storage allows information such as product
identification numbers, calibration values, specific user data, system setup data or other product
information to be stored directly within the product microcontroller. The process of reading and
writing data to the EEPROM memory has been reduced to a very trivial affair.
Device
Capacity
Address
256×8
00H ~ FFH
HT66F2370
512×8
000H ~ 1FFH
HT66F2390
1024×8
000H ~ 3FFH
HT66F2350
HT66F2360
EEPROM Data Memory Structure
The EEPROM Data Memory capacity is up to 1024×8 bits for the series of devices. Unlike the
Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped
into memory space and is therefore not directly addressable in the same way as the other types of
memory. Read and Write operations to the EEPROM are carried out in single byte operations using
an address and data register in sector 0 and a single control register in sector 1.
EEPROM Registers
Three registers control the overall operation of the internal EEPROM Data Memory. These are the
address register, EEA, the data register, EED and a single control register, EEC. As both the EEA
and EED registers are located in sector 0, they can be directly accessed in the same was as any other
Special Function Register. The EEC register, however, being located in sector 1, can be read from
or written to indirectly using the MP1H/MP1L or MP2H/MP2L Memory Pointer pair and Indirect
Addressing Register, IAR1 or IAR2. Because the EEC control register is located at address 40H
in sector 1, the Memory Pointer low byte register, MP1L or MP2L, must first be set to the value
40H and the Memory Pointer high byte register, MP1H or MP2H, set to the value, 01H, before any
operations on the EEC register are executed.
Register Name
Bit
7
6
5
4
3
2
1
0
EEA (HT66F2350/60)
EEA7
EEA6
EEA5
EEA4
EEA3
EEA2
EEA1
EEA0
EEAL (HT66F2370/90)
EEAL7 EEAL6 EEAL5 EEAL4 EEAL3 EEAL2 EEAL1 EEAL0
EEAH (HT66F2370)
—
—
—
—
—
—
—
EEAH0
EEAH (HT66F2390)
—
—
—
—
—
—
EED
D7
D6
D5
D4
D3
D2
EEAH1 EEAH0
D1
D0
EEC
—
—
—
—
WREN
WR
RDEN
RD
EEPROM Registers List
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Advanced A/D Flash MCU with EEPROM
EEA Register – HT66F2350/HT66F2360
Bit
7
6
5
4
3
2
1
0
Name
EEA7
EEA6
EEA5
EEA4
EEA3
EEA2
EEA1
EEA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0EEA7~EEA0: Data EEPROM address bit 7 ~ bit0
EEAL Register – HT66F2370/HT66F2390
Bit
7
6
5
4
3
2
1
0
Name
EEAL7
EEAL6
EEAL5
EEAL4
EEAL3
EEAL2
EEAL1
EEAL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0EEAL7~EEAL0: Data EEPROM low byte address bit 7 ~ bit0
EEAH Register – HT66F2370
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
EEAH0
R/W
—
—
—
—
—
—
—
R/W
POR
—
—
—
—
—
—
—
0
2
1
0
Bit 7~1
Unimplemented, read as "0"
Bit 0EEAH0: Data EEPROM high byte address bit 0
EEAH Register – HT66F2390
Bit
7
6
5
4
3
Name
—
—
—
—
—
—
EEAH1
EEAH0
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1~0EEAH1~EEAH0: Data EEPROM high byte address bit 1 ~ bit 0
EED Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: Data EEPROM data bit 7~bit0
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EEC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
WREN
WR
RDEN
RD
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7~4
Unimplemented, read as "0"
Bit 3WREN: Data EEPROM write enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data
EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM write operations. Note that the WREN bit will automatically be cleared to
zero after the write operation is finished.
Bit 2WR: EEPROM write control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application
program will activate a write cycle. This bit will be automatically reset to zero by the
hardware after the write cycle has finished. Setting this bit high will have no effect if
the WREN has not first been set high.
Bit 1RDEN: Data EEPROM read enable
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data
EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM read operations.
Bit 0RD: EEPROM read control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application
program will activate a read cycle. This bit will be automatically reset to zero by the
hardware after the read cycle has finished. Setting this bit high will have no effect if
the RDEN has not first been set high.
Note: The WREN, WR, RDEN and RD can not be set to "1" at the same time in one instruction. The
WR and RD can not be set to "1" at the same time.
Reading Data from the EEPROM
To read data from the EEPROM, the EEPROM address of the data to be read must first be placed in
the EEA register or EEAL/EEAH register pair. Then the read enable bit, RDEN, in the EEC register
must be set high to enable the read function. If the RD bit in the EEC register is now set high, a
read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit
has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero,
after which the data can be read from the EED register. The data will remain in the EED register
until another read or write operation is executed. The application program can poll the RD bit to
determine when the data is valid for reading.
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Advanced A/D Flash MCU with EEPROM
Writing Data to the EEPROM
To write data to the EEPROM, the EEPROM address of the data to be written must first be placed in
the EEA register or EEAL/EEAH register pair and the data placed in the EED register. To initiate a
write cycle the write enable bit, WREN, in the EEC register must first be set high to enable the write
function. After this, the WR bit in the EEC register must be immediately set high to initiate a write
cycle successfully. These two instructions must be executed consecutively. The global interrupt bit
EMI should also first be cleared before implementing any write operations, and then set high again
after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if
the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer
whose operation is asynchronous to microcontroller system clock, a certain time will elapse before
the data will have been written into the EEPROM. Detecting when the write cycle has finished
can be implemented either by polling the WR bit in the EEC register or by using the EEPROM
interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the
microcontroller, informing the user that the data has been written to the EEPROM. The application
program can therefore poll the WR bit to determine when the write cycle has ended.
Write Protection
Protection against inadvertent write operation is provided in several ways. After the device is
powered on, the Write Enable bit in the control register will be cleared preventing any write
operations. Also at power-on the Memory Pointer high byte register, MP1H or MP2H, will be reset
to zero, which means that Data Memory sector 0 will be selected. As the EEPROM control register
is located in sector 1, this adds a further measure of protection against spurious write operations.
During normal program operation, ensuring that the Write Enable bit in the control register is
cleared will safeguard against incorrect write operations.
EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM
interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However, as
the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt
enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its
associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multifunction interrupts are enabled and the stack is not full, a jump to the associated Multi-function
Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag
will be automatically reset, the EEPROM interrupt flag must be manually reset by the application
program.
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Advanced A/D Flash MCU with EEPROM
Programming Considerations
Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic
by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Memory
Pointer high byte register could be normally cleared to zero as this would inhibit access to sector 1
where the EEPROM control register exist. Although certainly not necessary, consideration might be
given in the application program to the checking of the validity of new write data by a simple read
back process. When writing data the WR bit must be set high immediately after the WREN bit has
been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also
be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that
the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is
totally complete. Otherwise, the EEPROM read or write operation will fail.
Programming Example – for HT66F2350
• Reading data from the EEPROM – polling method
MOV A, EEPROM_ADRES MOV EEA, A
MOV A, 040H
MOV MP1L, A
MOV A, 01H
MOV MP1H, A
SET IAR1.1
SET IAR1.0
BACK:
SZ IAR1.0
JMP BACK
CLR IAR1
CLR MP1H
MOV A, EED
MOV READ_DATA, A
; user defined address
; setup memory pointer low byte MP1L
; MP1L points to EEC register
; setup Memory Pointer high byte MP1H
; set RDEN bit, enable read operations
; start Read Cycle - set RD bit
; check for read cycle end
; disable EEPROM write
; move read data to register
• Writing Data to the EEPROM – polling method
MOV A, EEPROM_ADRES ; user defined address
MOV EEA, A
MOV A, EEPROM_DATA ; user defined data
MOV EED, A
MOV A, 040H
; setup memory pointer low byte MP1L
MOV MP1L, A
; MP1L points to EEC register
MOV A, 01H
; setup Memory Pointer high byte MP1H
MOV MP1H, A
CLR EMI
SET IAR1.3 ; set WREN bit, enable write operations
SET IAR1.2 ; start Write Cycle - set WR bit
SET EMI
BACK:
SZ IAR1.2 ; check for write cycle end
JMP BACK
CLR IAR1 ; disable EEPROM write
CLR MP1H
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HT66F2350/HT66F2360
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Advanced A/D Flash MCU with EEPROM
Oscillators
Various oscillator types offer the user a wide range of functions according to their various application
requirements. The flexible features of the oscillator functions ensure that the best optimisation can
be achieved in terms of speed and power saving. Oscillator selections and operation are selected
through a combination of application program and relevant control registers.
Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources
for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external
components as well as fully integrated internal oscillators, requiring no external components, are
provided to form a wide range of both fast and slow system oscillators. All oscillator options are
selected through register programming. The higher frequency oscillators provide higher performance
but carry with it the disadvantage of higher power requirements, while the opposite is of course true
for the lower frequency oscillators. With the capability of dynamically switching between fast and
slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature
especially important in power sensitive portable applications.
Name
Frequency
Pins
External High Speed Crystal
Type
HXT
400 kHz~16 MHz
OSC1/OSC2
Internal High Speed RC
HIRC
8/12/16 MHz
—
External Low Speed Crystal
LXT
32.768 kHz
XT1/XT2
Internal Low Speed RC
LIRC
32 kHz
—
Oscillator Types
System Clock Configurations
There are four methods of generating the system clock, two high speed oscillators and two low
speed oscillators for all devices. The high speed oscillator is the external crystal/ceramic oscillator,
HXT, and the internal 8/12/16 MHz RC oscillator, HIRC. The two low speed oscillators are the
internal 32 kHz RC oscillator, LIRC, and the external 32.768 kHz crystal oscillator, LXT. Selecting
whether the low or high speed oscillator is used as the system oscillator is implemented using the
CKS2~CKS0 bits in the SCC register and as the system clock can be dynamically selected.
The actual source clock used for the low speed oscillators is chosen via the FSS bit in the SCC
register while for the high speed oscillator the source clock is selected by the FHS bit in the SCC
register. The frequency of the slow speed or high speed system clock is determined using the
CKS2~CKS0 bits in the SCC register. Note that two oscillator selections must be made namely one
high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection
for either the high or low speed oscillator.
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Advanced A/D Flash MCU with EEPROM
fH
High Speed
Os�illato�s
HIRCEN
HXTEN
FHS
fH/�
fH/4
HIRC
fH/8
P�es�ale�
fH
HXT
fSYS
fH/1�
fH/3�
fH/�4
Low Speed
Os�illato�s
FSS
CKS�~CKS0
LXTEN
LXT
fSUB
fSUB
fLIRC
LIRC
fLIRC
System Clock Configurations
External Crystal/Ceramic Oscillator – HXT
The External Crystal/Ceramic System Oscillator is the high frequency oscillator, which is the
default oscillator clock source after power on. For most crystal oscillator configurations, the simple
connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for
oscillation, without requiring external capacitors. However, for some crystal types and frequencies,
to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a
ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as
shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the
crystal or resonator manufacturer’s specification.
For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure
that the crystal and any associated resistors and capacitors along with interconnecting lines are all
located as close to the MCU as possible.
C1
Internal
Oscillator
Circuit
OSC1
RP
RF
OSC�
C�
To inte�nal
�i��uits
Note: 1. RP is no��ally not �equi�ed. C1 and C� a�e �equi�ed.
�. Although not shown OSC1/OSC� pins have a pa�asiti�
�apa�itan�e of a�ound 7pF.
Crystal/Resonator Oscillator
HXT Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
12MHz
0 pF
0 pF
8MHz
0 pF
0 pF
4MHz
0 pF
0 pF
1MHz
100 pF
100 pF
Note: C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values
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Advanced A/D Flash MCU with EEPROM
Internal High Speed RC Oscillator – HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has a fixed frequency of 8/12/16 MHz. Device trimming during the
manufacturing process and the inclusion of internal frequency compensation circuits are used to
ensure that the influence of the power supply voltage, temperature and process variations on the
oscillation frequency are minimised. As a result, at a power supply of 3V or 5V and at a temperature
of 25°C degrees, the selected trimmed oscillation frequency will have a tolerance within 1%. Note
that if this internal system clock is selected, as it requires no external pins for its operation, I/O pins
are free for use as normal I/O pins or other pin-shared functional pins.
External 32.768 kHz Crystal Oscillator – LXT
The External 32.768 kHz Crystal System Oscillator is one of the low frequency oscillator choices,
which is selected via a software control bit, FSS. This clock source has a fixed frequency of 32.768
kHz and requires a 32.768 kHz crystal to be connected between pins XT1 and XT2. The external
resistor and capacitor components connected to the 32.768 kHz crystal are necessary to provide
oscillation. For applications where precise frequencies are essential, these components may be
required to provide frequency compensation due to different crystal manufacturing tolerances. After
the LXT oscillator is enabled by setting the LXTEN bit to 1, there is a time delay associated with the
LXT oscillator waiting for it to start-up.
When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop
microcontroller activity and to conserve power. However, in many microcontroller applications it
may be necessary to keep the internal timers operational even when the microcontroller is in the
SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided.
However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary
to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be
selected in consultation with the crystal or resonator manufacturer’s specification. The external
parallel feedback resistor, Rp, is required.
The pin-shared software control bits determine if the XT1/XT2 pins are used for the LXT oscillator
or as I/O or other pin-shared functional pins.
• If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O
or other pin-shared functional pins.
• If the LXT oscillator is used for any clock source, the 32.768 kHz crystal should be connected to
the XT1/XT2 pins.
For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure
that the crystal and any associated resistors and capacitors along with interconnecting lines are all
located as close to the MCU as possible.
C1
XT1
3�.7�8
kHz
Inte�nal RC
Os�illato�
RP
XT�
C�
Internal
Oscillator
Circuit
To inte�nal
�i��uits
Note: 1. RP� C1 and C� a�e �equi�ed.
�. Although not shown XT1/XT� pins have a pa�asiti�
�apa�itan�e of a�ound 7pF.
External LXT Oscillator
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Internal 32kHz Oscillator – LIRC
The Internal 32 kHz System Oscillator is one of the low frequency oscillator choices, which is
selected via a software control bit, FSS. It is a fully integrated RC oscillator with a typical frequency
of 32 kHz at 5V, requiring no external components for its implementation. Device trimming during
the manufacturing process and the inclusion of internal frequency compensation circuits are used
to ensure that the influence of the power supply voltage, temperature and process variations on the
oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of
25˚C degrees, the fixed oscillation frequency of 32 kHz will have a tolerance within 2%.
Operating Modes and System Clocks
Present day applications require that their microcontrollers have high performance but often still
demand that they consume as little power as possible, conflicting requirements that are especially
true in battery powered portable applications. The fast clocks required for high performance will
by their nature increase current consumption and of course vice-versa lower speed clocks reduce
current consumption. As Holtek has provided these devices with both high and low speed clock
sources and the means to switch between them dynamically, the user can optimise the operation of
their microcontroller to achieve the best performance/power ratio.
System Clocks
Each device has different clock sources for both the CPU and peripheral function operation. By
providing the user with a wide range of clock selections using register programming, a clock system
can be configured to obtain maximum application performance.
The main system clock, can come from either a high frequency, fH, or low frequency, fSUB, source,
and is selected using the CKS2~CKS0 bits in the SCC register. The high speed system clock is
sourced from an HXT or HIRC oscillator, selected via configuring the FHS bit in the SCC register.
The low speed system clock source can be sourced from the internal clock fSUB. If fSUB is selected
then it can be sourced by either the LXT or LIRC oscillators, selected via configuring the FSS bit in
the SCC register. The other choice, which is a divided version of the high speed system oscillator
has a range of fH/2~fH/64.
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Advanced A/D Flash MCU with EEPROM
fH
High Speed
Os�illato�s
HIRCEN
HXTEN
FHS
fH/�
fH/4
HIRC
fH/8
P�es�ale�
fH
HXT
fSYS
fH/1�
fH/3�
fH/�4
FSS
LXTEN
CKS�~CKS0
LXT
fSUB
LIRC
fSUB
fLIRC
fSYS
fPSC0
fSYS/4
Low Speed
Os�illato�s
fSUB
P�es�ale� 0
Ti�e Base 0
TB0[�:0]
CLKSEL0[1:0]
fSYS
fPSC1
fSYS/4
fSUB
CLKSEL1[1:0]
fLIRC
fLIRC
P�es�ale� 1
Ti�e Base 1
TB1[�:0]
WDT
LVR
Device Clock Configurations
Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation
can be stopped to conserve the power or continue to oscillate to provide the clock source,
fH~fH/64, for peripheral circuit to use, which is determined by configuring the corresponding
high speed oscillator enable control bit.
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System Operation Modes
There are six different modes of operation for the microcontroller, each one with its own
special characteristics and which can be chosen according to the specific performance and
power requirements of the application. There are two modes allowing normal operation of the
microcontroller, the FAST Mode and SLOW Mode. The remaining four modes, the SLEEP, IDLE0,
IDLE1 and IDLE2 Mode are used when the microcontroller CPU is switched off to conserve power.
Operation
Mode
CPU
Register Setting
FHIDEN
FSIDEN
CKS2~CKS0
fSYS
FAST
On
x
x
000~110
fH~fH/64
SLOW
On
x
x
111
fSUB
IDLE0
Off
0
1
IDLE1
Off
1
1
IDLE2
Off
1
0
SLEEP
Off
0
0
000~110
Off
111
On
xxx
On
000~110
On
111
Off
xxx
Off
fH
fSUB
fLIRC
On
On
On
On
Off
On
On
On
On
On
On
Off
On
Off
Off
On
On/Off
(1)
On
(2)
Note: 1. The fH clock will be switched on or off by configuring the corresponding oscillator enable
bit in the SLOW mode.
2. The fLIRC clock will be switched on if the WDT function is enabled.
FAST Mode
As the name suggests this is one of the main operating modes where the microcontroller has all of
its functions operational and where the system clock is provided by one of the high speed oscillators.
This mode operates allowing the microcontroller to operate normally with a clock source will come
from one of the high speed oscillators, either the HXT or HIRC oscillators. The high speed oscillator
will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by
the CKS2~CKS0 bits in the SCC register. Although a high speed oscillator is used, running the
microcontroller at a divided clock ratio reduces the operating current.
SLOW Mode
This is also a mode where the microcontroller operates normally although now with a slower speed
clock source. The clock source used will be from fSUB. The fSUB clock is derived from either the
LIRC or LXT oscillator.
SLEEP Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the FHIDEN and
FSIDEN bit are low. In the SLEEP mode the CPU will be stopped and both the high and low speed
oscillators will be switched off. However the fLIRC clock will continue to operate if the WDT function
is enabled by the WDTC register.
IDLE0 Mode
The IDLE0 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the
SCC register is low and the FSIDEN bit in the SCC register is high. In the IDLE0 Mode the CPU will
be switched off but the low speed oscillator will be turned on to drive some peripheral functions.
IDLE1 Mode
The IDLE1 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the
SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU
will be switched off but both the high and low speed oscillators will be turned on to provide a clock
source to keep some peripheral functions operational.
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IDLE2 Mode
The IDLE2 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in
the SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the
CPU and low speed oscillator will be switched off but the high speed oscillator will be turned on to
provide a clock source to keep some peripheral functions operational.
Control Registers
The registers, SCC, HIRCC, HXTC and LXTC, are used to control the system clock and the
corresponding oscillator configurations.
Bit
Register
Name
7
6
5
4
3
2
1
0
SCC
CKS2
CKS1
CKS0
—
FHS
FSS
FHIDEN
FSIDEN
HIRCC
—
—
—
—
HIRC1
HIRC0
HIRCF
HIRCEN
HXTC
—
—
—
—
—
HXTM
HXTF
HXTEN
LXTC
—
—
—
—
—
—
LXTF
LXTEN
System Operating Mode Control Registers List
SCC Register
Bit
7
6
5
4
3
2
1
0
Name
CKS2
CKS1
CKS0
—
FHS
FSS
FHIDEN
FSIDEN
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
POR
0
0
0
—
0
0
0
0
Bit 7~5CKS2~CKS0: System clock selection
000: fH
001: fH/2
010: fH/4
011: fH/8
100: fH/16
101: fH/32
110: fH/64
111: fSUB
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source directly derived from fH or fSUB, a divided version
of the high speed system oscillator can also be chosen as the system clock source.
Bit 4
Unimplemented, read as "0"
Bit 3FHS: High Frequency clock selection
0: HIRC
1: HXT
Bit 2FSS: Low Frequency clock selection
0: LIRC
1: LXT
Bit 1FHIDEN: High Frequency oscillator control when CPU is switched off
0: Disable
1: Enable
This bit is used to control whether the high speed oscillator is activated or stopped
when the CPU is switched off by executing an "HALT" instruction.
Bit 0FSIDEN: Low Frequency oscillator control when CPU is switched off
0: Disable
1: Enable
This bit is used to control whether the low speed oscillator is activated or stopped
when the CPU is switched off by executing an "HALT" instruction. The LIRC
oscillator is controlled by this bit together with the WDT function enable control when
the LIRC is selected to be the low speed oscillator clock source or the WDT function
is enabled respectively. If this bit is cleared to 0 but the WDT function is enabled, the
LIRC oscillator will also be enabled.
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HIRCC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
HIRC1
HIRC0
HIRCF
HIRCEN
R/W
—
—
—
—
R/W
R/W
R
R/W
POR
—
—
—
—
0
0
0
1
Bit 7~4
Unimplemented, read as "0"
Bit 3~2HIRC1~HIRC0: HIRC frequency selection
00: 8 MHz
01: 12 MHz
10: 16 MHz
11: 8 MHz
When the HIRC oscillator is enabled or the HIRC frequency selection is changed by
the application program, the clock frequency will automatically be changed after the
HIRCF flag is set to 1.
Bit 1HIRCF: HIRC oscillator stable flag
0: HIRC unstable
1: HIRC stable
This bit is used to indicate whether the HIRC oscillator is stable or not. When the
HIRCEN bit is set to 1 to enable the HIRC oscillator or the HIRC frequency selection
is changed by the application program, the HIRCF bit will first be cleared to 0 and
then set to 1 after the HIRC oscillator is stable.
Bit 0HIRCEN: HIRC oscillator enable control
0: Disable
1: Enable
HXTC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
HXTM
HXTF
HXTEN
R/W
—
—
—
—
—
R/W
R
R/W
POR
—
—
—
—
—
0
0
0
Bit 7~3
Unimplemented, read as "0"
Bit 2HXTM: HXT mode selection
0: HXT frequency ≤ 10 MHz
1: HXT frequency >10 MHz
This bit is used to select the HXT oscillator operating mode. Note that this bit must
be properly configured before the HXT is enabled. When the OSC1 and OSC2 pins
are enabled and the HXTEN bit is set to 1 to enable the HXT oscillator, it is invalid to
change the value of this bit. Otherwise, this bit value can be changed with no operation
on the HXT function.
Bit 1HXTF: HXT oscillator stable flag
0: HXT unstable
1: HXT stable
This bit is used to indicate whether the HXT oscillator is stable or not. When the
HXTEN bit is set to 1 to enable the HXT oscillator, the HXTF bit will first be cleared
to 0 and then set to 1 after the HXT oscillator is stable.
Bit 0HXTEN: HXT oscillator enable control
0: Disable
1: Enable
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LXTC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
LXTF
LXTEN
R/W
—
—
—
—
—
—
R
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1LXTF: LXT oscillator stable flag
0: LXT unstable
1: LXT stable
This bit is used to indicate whether the LXT oscillator is stable or not. When the
LXTEN bit is set to 1 to enable the LXT oscillator, the LXTF bit will first be cleared
to 0 and then set to 1 after the LXT oscillator is stable.
Bit 0LXTEN: LXT oscillator enable control
0: Disable
1: Enable
Operating Mode Switching
These devices can switch between operating modes dynamically allowing the user to select the best
performance/power ratio for the present task in hand. In this way microcontroller operations that
do not require high performance can be executed using slower clocks thus requiring less operating
current and prolonging battery life in portable applications.
In simple terms, Mode Switching between the FAST Mode and SLOW Mode is executed using the
CKS2~CKS0 bits in the SCC register while Mode Switching from the FAST/SLOW Modes to the
SLEEP/IDLE Modes is executed via the HALT instruction. When an HALT instruction is executed,
whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the
FHIDEN and FSIDEN bits in the SCC register.
FAST
fSYS=fH~fH/64
fH on
CPU run
fSYS on
fSUB on
SLOW
fSYS=fSUB
fSUB on
CPU run
fSYS on
fH on/off
SLEEP
HALT instruction executed
CPU stop
FHIDEN=0
FSIDEN=0
fH off
fSUB off
IDLE0
HALT instruction executed
CPU stop
FHIDEN=0
FSIDEN=1
fH off
fSUB on
IDLE2
HALT instruction executed
CPU stop
FHIDEN=1
FSIDEN=0
fH on
fSUB off
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IDLE1
HALT instruction executed
CPU stop
FHIDEN=1
FSIDEN=1
fH on
fSUB on
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FAST Mode to SLOW Mode Switching
When running in the FAST Mode, which uses the high speed system oscillator, and therefore
consumes more power, the system clock can switch to run in the SLOW Mode by set the
CKS2~CKS0 bits to "111" in the SCC register. This will then use the low speed system oscillator
which will consume less power. Users may decide to do this for certain operations which do not
require high performance and can subsequently reduce power consumption.
The SLOW Mode is sourced from the LXT or LIRC oscillator determined by the FSS bit in the SCC
register and therefore requires this oscillator to be stable before full mode switching occurs.
FAST Mode
CKS2~CKS0 = 111
SLOW Mode
FHIDEN=0, FSIDEN=0
HALT instruction is executed
SLEEP Mode
FHIDEN=0, FSIDEN=1
HALT instruction is executed
IDLE0 Mode
FHIDEN=1, FSIDEN=1
HALT instruction is executed
IDLE1 Mode
FHIDEN=1, FSIDEN=0
HALT instruction is executed
IDLE2 Mode
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SLOW Mode to FAST Mode Switching
In SLOW mode the system clock is derived from fSUB. When system clock is switched back to the
FAST mode from fSUB, the CKS2 ~ CKS0 bits should be set to "000" ~ "110" and then the system
clock will respectively be switched to fH ~ fH/64.
However, if fH is not used in SLOW mode and thus switched off, it will take some time to re-oscillate
and stabilise when switching to the FAST mode from the SLOW Mode. This is monitored using the
HXTF bit in the HXTC register or the HIRCF bit in the HIRCC register. The time duration required
for the high speed system oscillator stabilization is specified in the relevant characteristics.
SLOW Mode
CKS2~CKS0 = 000~110
FAST Mode
FHIDEN=0, FSIDEN=0
HALT instruction is executed
SLEEP Mode
FHIDEN=0, FSIDEN=1
HALT instruction is executed
IDLE0 Mode
FHIDEN=1, FSIDEN=1
HALT instruction is executed
IDLE1 Mode
FHIDEN=1, FSIDEN=0
HALT instruction is executed
IDLE2 Mode
Entering the SLEEP Mode
There is only one way for the device to enter the SLEEP Mode and that is to execute the "HALT"
instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register
equal to "0". In this mode all the clocks and functions will be switched off except the WDT function.
When this instruction is executed under the conditions described above, the following will occur:
• The system clock will be stopped and the application program will stop at the "HALT"
instruction.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be
cleared.
• The WDT will be cleared and resume counting if the WDT function is enabled by the WDTC
register.
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Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT"
instruction in the application program with the FHIDEN bit in the SCC register equal to "0" and the
FSIDEN bit in the SCC register equal to "1". When this instruction is executed under the conditions
described above, the following will occur:
• The fH clock will be stopped and the application program will stop at the "HALT" instruction, but
the fSUB clock will be on.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be
cleared.
• The WDT will be cleared and resume counting if the WDT function is enabled by the WDTC
register.
Entering the IDLE1 Mode
There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT"
instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register
equal to "1". When this instruction is executed under the conditions described above, the following
will occur:
• The fH and fSUB clocks will be on but the application program will stop at the "HALT" instruction.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be
cleared.
• The WDT will be cleared and resume counting if the WDT function is enabled by the WDTC
register.
Entering the IDLE2 Mode
There is only one way for the device to enter the IDLE2 Mode and that is to execute the "HALT"
instruction in the application program with the FHIDEN bit in the SCC register equal to "1" and the
FSIDEN bit in the SCC register equal to "0". When this instruction is executed under the conditions
described above, the following will occur:
• The fH clock will be on but the fSUB clock will be off and the application program will stop at the
"HALT" instruction.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be
cleared.
• The WDT will be cleared and resume counting if the WDT function is enabled by the WDTC
register.
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Standby Current Considerations
As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the
device to as low a value as possible, perhaps only in the order of several micro-amps except in the
IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by
the circuit designer if the power consumption is to be minimised. Special attention must be made
to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed
high or low level as any floating input pins could create internal oscillations and result in increased
current consumption. This also applies to devices which have different package types, as there may
be unbonded pins. These must either be setup as outputs or if setup as inputs must have pull-high
resistors connected.
Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs.
These should be placed in a condition in which minimum current is drawn or connected only to
external circuits that do not draw current, such as other CMOS inputs. Also note that additional
standby current will also be required if the LIRC oscillator has enabled.
In the IDLE1 and IDLE 2 Mode the high speed oscillator is on, if the peripheral function clock
source is derived from the high speed oscillator, the additional standby current will also be perhaps
in the order of several hundred micro-amps.
Wake-up
To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the
CPU will be switched off. However, when the device is woken up again, it will take a considerable
time for the original system oscillator to restart, stabilise and allow normal operation to resume.
After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources
listed as follows:
• An external falling edge on Port A
• An external reset
• A system interrupt
• A WDT overflow
When the device executes the "HALT" instruction, the PDF flag will be set to 1. The PDF flag will
be cleared to 0 if the device experiences a system power-up or executes the clear Watchdog Timer
instruction. If the system is woken up by a WDT overflow, a Watchdog Timer reset will be initiated
and the TO flag will be set to 1. The TO flag is set if a WDT time-out occurs and causes a wake-up
that only resets the Program Counter and Stack Pointer, other flags remain in their original status.
Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin
to wake up the system. When a Port A pin wake-up occurs, the program will resume execution at
the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then
two possible situations may occur. The first is where the related interrupt is disabled or the interrupt
is enabled but the stack is full, in which case the program will resume execution at the instruction
following the "HALT" instruction. In this situation, the interrupt which woke up the device will not
be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled
or when a stack level becomes free. The other situation is where the related interrupt is enabled and
the stack is not full, in which case the regular interrupt response takes place. If an interrupt request
flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related
interrupt will be disabled.
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Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the internal RC oscillator, fLIRC. The LIRC internal
oscillator has an approximate frequency of 32 kHz and this specified internal clock period can vary
with VDD, temperature and process variations. The Watchdog Timer source clock is then subdivided
by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0
bits in the WDTC register.
Watchdog Timer Control Register
A single register, WDTC, controls the required timeout period as well as the enable/disable
operation. This register controls the overall operation of the Watchdog Timer.
WDTC Register
Bit
7
6
5
4
3
2
1
0
Name
WE4
WE3
WE2
WE1
WE0
WS2
WS1
WS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
0
1
1
Bit 7~3WE4~WE0: WDT function enable control
10101: Disabled
01010: Enabled
Other values: Reset MCU
If these bits are changed due to adverse environmental conditions, the microcontroller
will be reset. The reset operation will be activated after a delay time, tSRESET, and the
WRF bit in the RSTFC register will be set to 1.
Bit 2~0WS2~WS0: WDT time-out period selection
000: 28/fLIRC
001: 210/fLIRC
010: 212/fLIRC
011: 214/fLIRC
100: 215/fLIRC
101: 216/fLIRC
110: 217/fLIRC
111: 218/fLIRC
These three bits determine the division ratio of the watchdog timer source clock,
which in turn determines the time-out period.
RSTFC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
RSTF
LVRF
LRF
WRF
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
x
0
0
"x": unknown
Bit 7~4
Unimplemented, read as "0"
Bit 3RSTF: Reset control register software reset flag
Described elsewhere.
Bit 2LVRF: LVR function reset flag
Described elsewhere.
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Bit 1LRF: LVR control register software reset flag
Described elsewhere.
Bit 0WRF: WDT control register software reset flag
0: Not occurred
1: Occurred
This bit is set to 1 by the WDT control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application program.
Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its timer overflows. This means
that in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is
done using the clear watchdog instruction. If the program malfunctions for whatever reason, jumps
to an unknown location, or enters an endless loop, the clear instruction will not be executed in the
correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to
the Watchdog Timer enable/disable function, there are five bits, WE4~WE0, in the WDTC register
to offer the enable/disable control and reset control of the Watchdog Timer. The WDT function will
be enabled when the WE4~WE0 bits are set to a value of 01010B while the WDT function will
be disabled if the WE4~WE0 bits are equal to 10101B. If the WE4~WE0 bits are set to any other
values rather than 01010B and 10101B, it will reset the device after a delay time, tSRESET. After power
on these bits will have a value of 01010B.
WE4 ~ WE0 Bits
WDT Function
10101B
Disable
01010B
Enable
Any other value
Reset MCU
Watchdog Timer Enable/Disable Control
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Four methods can be adopted to clear the contents of the Watchdog Timer.
The first is a WDT reset, which means a certain value except 01010B and 10101B written into the
WE4~WE0 field, the second is using the Watchdog Timer software clear instruction and the third
is via a HALT instruction. The last is an external hardware reset, which means a low level on the
external reset pin if the external reset pin exists by the RSTC register.
There is only one method of using software instruction to clear the Watchdog Timer. That is to use
the single "CLR WDT" instruction to clear the WDT contents.
The maximum time out period is when the 218 division ratio is selected. As an example, with a 32 kHz
LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 second
for the 218 division ratio and a minimum timeout of 8ms for the 28 division ration.
WDTC WE4~WE0 �its
Registe�
Reset MCU
CLR
“HALT”Inst�u�tion
“CLR WDT”Inst�u�tion
Exte�nal �eset pin �eset
LIRC
fLIRC
8-stage Divide�
fLIRC/�8
WS�~WS0
(fLIRC/�8 ~ fLIRC/�18)
WDT P�es�ale�
8-to-1 MUX
WDT Ti�e-out
(�8/fLIRC ~ �18/fLIRC)
Watchdog timer
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Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set
to some predetermined condition irrespective of outside parameters. The most important reset
condition is after power is first applied to the microcontroller. In this case, internal circuitry will
ensure that the microcontroller, after a short delay, will be in a well defined state and ready to
execute the first program instruction. After this power-on reset, certain important internal registers
will be set to defined states before the program commences. One of these registers is the Program
Counter, which will be reset to zero forcing the microcontroller to begin program execution from the
lowest Program Memory address.
In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a
reset condition when the microcontroller is already running, the RES line is forcefully pulled low.
In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to preceed with normal operation after the reset line is
allowed to return high.
The Watchdog Timer overflow is one of many reset types and will reset the microcontroller. Another
reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is
implemented in situations where the power supply voltage falls below a certain threshold. Another
type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset
operations result in different register conditions being setup.
Reset Functions
There are five ways in which a microcontroller reset can occur, through events occurring both
internally and externally.
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to
the microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring that
all pins will be first set to inputs.
VDD
Powe�-on Reset
tRSTD
SST Ti�e-out
Note: tRSTD is power-on delay with typical time=48 ms
Power-On Reset Timing Chart
Rev. 1.00
81
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
RES Pin Reset
As the reset pin is shared with I/O pins, the reset function must be selected using a control register,
RSTC. Although the microcontroller has an internal RC reset function, if the VDD power supply
rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function
may be incapable of providing proper reset operation. For this reason it is recommended that an
external RC network is connected to the RES pin, whose additional time delay will ensure that the
RES pin remains low for an extended period to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain
voltage value, the reset delay time, tRSTD, is invoked to provide an extea delay time after which the
microcontroller will begin normal operation. The abbreviation SST in the figures stands for System
Start-up Time. For most applications a resistor connected between VDD and the RES line and a
capacitor connected betweeb VSS and the RES pin will provide a suitable external reset circuit. Any
wiring connected to the RES pin should be kept as short as possible to minimise any stray noise
interference. For applications that operate within an environment where more noise is present the
Enhanced Reset Circuit shown is recommended.
VDD
0.01µF**
1N4148*
VDD
10kΩ~
100kΩ
300Ω*
RES
0.1µF~1µF
VSS
Note: "*" It is recommended that this component is added for added ESD protection.
"**" It is recommended that this component is added in environments where power line noise
is significant.
External RES Circuit
Pulling the RES pin low using external hardware will also execute a device reset. In this case, as in
the case of other resets, the Progran Counter will reset to zero and program execution initiated from
this point.
RES
0.4VDD
Inte�nal Reset
0.9VDD
tRSTD + tSST
Note: tRSTD is power-on delay with typical time=16 ms
RES Reset Timing Chart
There is an internal reset control register, RSTC, which is used to select the external RES pin
function and provide a reset when the device operates abnormally due to the environmental noise
interference. If the content of the RSTC register is set to any value other than 01010101B or
10101010B, it will reset the device after a delay time, tSRESET. After power on the register will have a
value of 01010101B.
RSTC7 ~ RSTC0 Bits
Reset Function
01010101B
I/O
10101010B
RES
Any other value
Reset MCU
Internal Reset Function Control
Rev. 1.00
82
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
• RSTC Register
Bit
7
6
5
4
3
2
1
0
Name
RSTC7
RSTC6
RSTC5
RSTC4
RSTC3
RSTC2
RSTC1
RSTC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7~0RSTC7~RSTC0: Reset function control
01010101: I/O pin
10101010: RES pin
Other values: Reset MCU
If these bits are changed due to adverse environmental conditions, the microcontroller
will be reset. The reset operation will be activated after a delay time, tSRESET, and the
RSTF bit in the RSTFC register will be set to 1.
All resets will reset this register to POR value except the WDT time out hardware
warm reset. Note that if the register is set to 10101010 to select the RES pin, this
configuration has higher priority than other related pin-shared controls.
• RSTFC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
RSTF
LVRF
LRF
WRF
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
x
0
0
"x": unknown
Bit 7~4
Unimplemented, read as "0"
Bit 3RSTF: Reset control register software reset flag
0: Not occurred
1: Occurred
This bit is set to 1 by the RSTC control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application program.
Bit 2LVRF: LVR function reset flag
Described elsewhere.
Bit 1LRF: LVR control register software reset flag
Described elsewhere.
Bit 0WRF: WDT control register software reset flag
Described elsewhere.
Low Voltage Reset – LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of
the device. The LVR function is always enabled with a specific LVR voltage, VLVR. If the supply
voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing
the battery, the LVR will automatically reset the device internally and the LVRF bit in the RSTFC
register will also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the
range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the LVD/LVR
Electrical Characteristics. If the low supply voltage state does not exceed this value, the LVR will
ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be
selected by the LVS bits in the LVRC register. If the LVS7~LVS0 bits have any other value, which
may perhaps occur due to adverse environmental conditions such as noise, the LVR will reset the
device after a delay time, tSRESET. When this happens, the LRF bit in the RSTFC register will be set
to 1. After power on the register will have the value of 01010101B. Note that the LVR function will
be automatically disabled when the device enters the power down mode.
Rev. 1.00
83
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
LVR
tRSTD + tSST
Inte�nal Reset
Note: tRSTD is power-on delay with typical time=48ms
Low Voltage Reset Timing Chart
• LVRC Register
Bit
7
6
5
4
3
2
1
0
Name
LVS7
LVS6
LVS5
LVS4
LVS3
LVS2
LVS1
LVS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7~0LVS7~LVS0: LVR voltage select
01010101: 2.1V
00110011: 2.55V
10011001: 3.15V
10101010: 3.8V
Other values: Generates a MCU reset – register is reset to POR value
When an actual low voltage condition occurs, as specified by one of the four defined
LVR voltage value above, an MCU reset will generated. The reset operation will be
activated after the low voltage condition keeps more than a tLVR time. In this situation
the register contents will remain the same after such a reset occurs.
Any register value, other than the four defined register values above, will also result in
the generation of an MCU reset. The reset operation will be activated after a delay time,
tSRESET. However in this situation the register contents will be reset to the POR value.
• RSTFC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
RSTF
LVRF
LRF
WRF
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
—
—
—
—
0
x
0
0
"x": unknown
Bit 7~4
Unimplemented, read as "0"
Bit 3RSTF: Reset control register software reset flag
Described elsewhere.
Bit 2LVRF: LVR function reset flag
0: Not occurred
1: Occurred
This bit is set to 1 when a specific low voltage reset condition occurs. Note that this bit
can only be cleared to 0 by the application program.
Bit 1LRF: LVR control register software reset flag
0: Not occurred
1: Occurred
This bit is set to 1 by the LVRC control register contains any undefined LVR voltage
register values. This in effect acts like a software-reset function. Note that this bit can
only be cleared to 0 by the application program.
Bit 0WRF: WDT control register software reset flag
Described elsewhere.
Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as the hardware Low Voltage
Reset except that the Watchdog time-out flag TO will be set to "1".
Rev. 1.00
84
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
WDT Ti�e-out
tRSTD + tSST
Inte�nal Reset
Note: tRSTD is power-on delay with typical time=16 ms
WDT Time-out Reset during NORMAL Operation Timing Chart
Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset.
Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be
cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for tSST details.
WDT Ti�e-out
tSST
Inte�nal Reset
WDT Time-out Reset during SLEEP or IDLE Mode Timing Chart
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are
shown in the table:
TO
PDF
0
0
Power-on reset
Reset Function
u
u
RES or LVR reset during FAST or SLOW Mode operation
1
u
WDT time-out reset during FAST or SLOW Mode operation
1
1
WDT time-out reset during IDLE or SLEEP Mode operation
Note "u" stands for unchanged
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item
Reset Function
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT, Time Base
Clear after reset, WDT begins counting
Timer Modules
Timer Modules will be turned off
Input/Output Ports
I/O ports will be setup as inputs
Stack pointer
Stack pointer will point to the top of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects the microcontroller internal registers.
Rev. 1.00
85
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
HT66F2390
HT66F2370
HT66F2360
HT66F2350
Register
Reset
(Power On)
RES Reset
(Normal
Operation)
LVR Reset
(Normal
Operation)
WDT Time-out
(Normal
Operation)
WDT Time-out
(IDLE/SLEEP)
IAR0
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
MP0
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
IAR1
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
MP1L
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
MP1H
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
●
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
●
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
●
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBHP
●
TBHP
●
TBHP
●
TBHP
STATUS
●
●
PBP
●
●
●
●
PBP
●
PBP
---x xxxx
---u uuuu
---u uuuu
---u uuuu
---u uuuu
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
xx00 xxxx
uuuu uuuu
uuuu uuuu
xx1u uuuu
u u 11 u u u u
---- ---0
---- ---0
---- ---0
---- ---0
---- ---u
---- --00
---- --00
---- --00
---- --00
---- --uu
●
---- -000
---- -000
---- -000
---- -000
---- -uuu
IAR2
●
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP2L
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
MP2H
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
RSTFC
●
●
●
●
---- 0x00
---- uuuu
---- u1uu
---- uuuu
---- uuuu
INTC0
●
●
●
●
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTC1
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTC2
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTC3
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PA
●
●
●
●
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
●
●
●
●
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAPU
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAWU
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PB
●
●
●
●
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
●
●
●
●
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBPU
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PC
●
●
●
●
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
●
●
●
●
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCPU
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PD
●
●
●
●
- 111 1111
- 111 1111
- 111 1111
- 111 1111
-uuu uuuu
PDC
●
●
●
●
- 111 1111
- 111 1111
- 111 1111
- 111 1111
-uuu uuuu
PDPU
●
●
●
●
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
PE
●
●
●
●
- - - 1 1111
- - - 1 1111
- - - 1 1111
- - - 1 1111
---u uuuu
PEC
●
●
●
●
- - - 1 1111
- - - 1 1111
- - - 1 1111
- - - 1 1111
---u uuuu
PEPU
●
●
●
●
---0 0000
---0 0000
---0 0000
---0 0000
---u uuuu
PF
●
●
●
●
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PFC
●
●
●
●
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PFPU
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
●
●
●
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PG
Rev. 1.00
86
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
HT66F2390
HT66F2370
HT66F2360
HT66F2350
Register
Reset
(Power On)
RES Reset
(Normal
Operation)
LVR Reset
(Normal
Operation)
WDT Time-out
(Normal
Operation)
WDT Time-out
(IDLE/SLEEP)
PGC
●
●
●
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PGPU
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PH
●
●
●
- - 11 1111
- - 11 1111
- - 11 1111
- - 11 1111
--uu uuuu
PHC
●
●
●
- - 11 1111
- - 11 1111
- - 11 1111
- - 11 1111
--uu uuuu
●
●
●
--00 0000
--00 0000
--00 0000
--00 0000
--uu uuuu
PMPS
PHPU
●
●
●
●
---- --00
---- --00
---- --00
---- --00
---- --uu
RSTC
●
●
●
●
0101 0101
0101 0101
0101 0101
0101 0101
uuuu uuuu
VBGRC
●
●
●
●
---- ---0
---- ---0
---- ---0
---- ---0
---- ---u
MFI0
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
MFI1
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
MFI2
●
●
●
●
--00 --00
--00 --00
--00 --00
--00 --00
--uu --uu
MFI3
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
●
●
MFI4
●
●
MFI5
●
●
●
●
MFI5
INTEG
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
--00 --00
--00 --00
--00 --00
--00 --00
--uu --uu
●
●
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
SCC
●
●
●
●
000- 0000
000- 0000
000- 0000
000- 0000
uuu- uuuu
HIRCC
●
●
●
●
---- 0001
---- 0001
---- 0001
---- 0001
---- uuuu
HXTC
●
●
●
●
---- -000
---- -000
---- -000
---- -000
---- -uuu
LXTC
●
●
●
●
---- --00
---- --00
---- --00
---- --00
---- --uu
WDTC
●
●
●
●
0 1 0 1 0 0 11
0 1 0 1 0 0 11
0 1 0 1 0 0 11
0 1 0 1 0 0 11
uuuu uuuu
LVRC
●
●
●
●
0101 0101
0101 0101
0101 0101
0101 0101
uuuu uuuu
●
●
LVDC
●
●
EEA
●
●
EEAL
●
EEAH
●
EEAH
●
--00 0000
--00 0000
--00 0000
--00 0000
--uu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
---- ---0
---- ---0
---- ---0
---- ---0
---- ---u
●
---- --00
---- --00
---- --00
---- --00
---- --uu
EED
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
CP0C
●
●
●
●
-000 00--
-000 00--
-000 00--
-000 00--
-uuu uu--
CP1C
●
●
●
●
-000 00--
-000 00--
-000 00--
-000 00--
-uuu uu--
PTM0C0
●
●
●
●
0000 0---
0000 0---
0000 0---
0000 0---
uuuu u---
PTM0C1
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM0DL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM0DH
●
●
●
●
---- --00
---- --00
---- --00
---- --00
---- --uu
PTM0AL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM0AH
●
●
●
●
---- --00
---- --00
---- --00
---- --00
---- --uu
PTM0RPL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
---- --uu
PTM0RPH
●
●
●
●
---- --00
---- --00
---- --00
---- --00
STM0C0
●
●
●
●
0000 0---
0000 0---
0000 0---
0000 0---
uuuu u---
STM0C1
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM0DL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM0DH
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM0AL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM0AH
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM0RP
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
Rev. 1.00
87
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
HT66F2390
HT66F2370
HT66F2360
HT66F2350
Register
Reset
(Power On)
RES Reset
(Normal
Operation)
LVR Reset
(Normal
Operation)
WDT Time-out
(Normal
Operation)
WDT Time-out
(IDLE/SLEEP)
SLEDC0
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
SLEDC1
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
SLEDC2
●
SLEDC3
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
MDUWR0
●
●
●
●
xxxx xxxx
0000 0000
0000 0000
0000 0000
uuuu uuuu
MDUWR1
●
●
●
●
xxxx xxxx
0000 0000
0000 0000
0000 0000
uuuu uuuu
MDUWR2
●
●
●
●
xxxx xxxx
0000 0000
0000 0000
0000 0000
uuuu uuuu
MDUWR3
●
●
●
●
xxxx xxxx
0000 0000
0000 0000
0000 0000
uuuu uuuu
MDUWR4
●
●
●
●
xxxx xxxx
0000 0000
0000 0000
0000 0000
uuuu uuuu
MDUWR5
●
●
●
●
xxxx xxxx
0000 0000
0000 0000
0000 0000
uuuu uuuu
MDUWCTRL
●
●
●
●
00-- ----
00-- ----
00-- ----
00-- ----
uu-- ----
CP0VOS
●
●
●
●
-001 0000
-001 0000
-001 0000
-001 0000
-uuu uuuu
CP1VOS
●
●
●
●
-001 0000
-001 0000
-001 0000
-001 0000
-uuu uuuu
PSC0R
●
●
●
●
---- --00
---- --00
---- --00
---- --00
---- --uu
TB0C
●
●
●
●
0--- -000
0--- -000
0--- -000
0--- -000
u--- -uuu
TB1C
●
●
●
●
0--- -000
0--- -000
0--- -000
0--- -000
u--- -uuu
PSC1R
●
●
●
●
---- --00
---- --00
---- --00
---- --00
SADOL
SADOH
●
●
●
●
●
●
●
●
xxxx ----
xxxx xxxx
xxxx ----
uuuu uuuu
xxxx ----
uuuu uuuu
xxxx ----
uuuu uuuu
---- --uu
uuuu ---(ADRFS=0)
uuuu uuuu
(ADRFS=0)
uuuu uuuu
(ADRFS=0)
---- uuuu
(ADRFS=0)
SADC0
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
SADC1
●
●
●
●
0000 -000
0000 -000
0000 -000
0000 -000
uuuu -uuu
SADC2
●
●
●
●
0-00 0000
0-00 0000
0-00 0000
0-00 0000
u-uu uuuu
SIMC0
●
●
●
●
111 - 0 0 0 0
111 - 0 0 0 0
111 - 0 0 0 0
111 - 0 0 0 0
uuu- uuuu
SIMC1
●
●
●
●
1000 0001
1000 0001
1000 0001
1000 0001
uuuu uuuu
SIMD
●
●
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
SIMA/SIMC2
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
SIMTOC
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
SPIAC0
●
●
●
●
111 - - - 0 0
111 - - - 0 0
111 - - - 0 0
111 - - - 0 0
uuu- --uu
SPIAC1
●
●
●
●
--00 0000
--00 0000
--00 0000
--00 0000
--uu uuuu
SPIAD
●
●
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
FARL
●
●
●
●
FARH
●
FARH
●
FARH
●
FARH
FD0L
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
---0 0000
---0 0000
---0 0000
---0 0000
---u uuuu
--00 0000
--00 0000
--00 0000
--00 0000
--uu uuuu
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD0H
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD1L
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD1H
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD2L
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
Rev. 1.00
88
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
HT66F2390
HT66F2370
HT66F2360
HT66F2350
Register
Reset
(Power On)
RES Reset
(Normal
Operation)
LVR Reset
(Normal
Operation)
WDT Time-out
(Normal
Operation)
WDT Time-out
(IDLE/SLEEP)
FD2H
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD3L
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD3H
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
SCOMC
●
●
●
●
-000 ----
-000 ----
-000 ----
-000 ----
-uuu ----
CRCCR
●
●
●
●
---- ---0
---- ---0
---- ---0
---- ---0
---- ---u
CRCIN
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
CRCDL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
CRCDH
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
IECC
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
U0SR
●
●
●
●
0 0 0 0 1 0 11
0 0 0 0 1 0 11
0 0 0 0 1 0 11
0 0 0 0 1 0 11
uuuu uuuu
U0CR1
●
●
●
●
0000 00x0
0000 00x0
0000 00x0
0000 00x0
uuuu uuuu
U0CR2
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TXR_RXR0
●
●
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BRG0
●
●
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
U1SR
●
●
●
●
0 0 0 0 1 0 11
0 0 0 0 1 0 11
0 0 0 0 1 0 11
0 0 0 0 1 0 11
uuuu uuuu
U1CR1
●
●
●
●
0000 00x0
0000 00x0
0000 00x0
0000 00x0
uuuu uuuu
U1CR2
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TXR_RXR1
●
●
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BRG1
●
●
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
U2SR
●
●
0 0 0 0 1 0 11
0 0 0 0 1 0 11
0 0 0 0 1 0 11
0 0 0 0 1 0 11
uuuu uuuu
U2CR1
●
●
0000 00x0
0000 00x0
0000 00x0
0000 00x0
uuuu uuuu
U2CR2
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TXR_RXR2
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BRG2
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
●
●
0000 0---
0000 0---
0000 0---
0000 0---
uuuu u---
PTM1C0
●
●
PTM1C1
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM1DL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM1DH
●
●
●
●
---- --00
---- --00
---- --00
---- --00
---- --uu
PTM1AL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM1AH
●
●
●
●
---- --00
---- --00
---- --00
---- --00
---- --uu
PTM1RPL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM1RPH
●
●
●
●
---- --00
---- --00
---- --00
---- --00
---- --uu
PTM2C0
●
●
●
●
0000 0---
0000 0---
0000 0---
0000 0---
uuuu u---
PTM2C1
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM2DL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM2DH
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM2AL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM2AH
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM2RPL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM2RPH
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM3C0
●
●
●
●
0000 0---
0000 0---
0000 0---
0000 0---
uuuu u---
PTM3C1
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM3DL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM3DH
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM3AL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
Rev. 1.00
89
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
HT66F2390
HT66F2370
HT66F2360
HT66F2350
Register
Reset
(Power On)
RES Reset
(Normal
Operation)
LVR Reset
(Normal
Operation)
WDT Time-out
(Normal
Operation)
WDT Time-out
(IDLE/SLEEP)
PTM2AH
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM3RPL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM3RPH
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM1C0
●
●
●
●
0000 0---
0000 0---
0000 0---
0000 0---
uuuu u---
STM1C1
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM1DL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM1DH
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM1AL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM1AH
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM1RP
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM2C0
●
●
●
●
0000 0---
0000 0---
0000 0---
0000 0---
uuuu u---
STM2C1
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM2DL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM2DH
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM2AL
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM2AH
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
STM2RP
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
EEC
●
●
●
●
---- 0000
---- 0000
---- 0000
---- 0000
---- uuuu
FC0
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
FC1
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
FC2
●
●
●
●
---- ---0
---- ---0
---- ---0
---- ---0
---- ---u
IFS0
●
●
●
●
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
IFS1
●
●
●
●
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
IFS2
●
●
●
●
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
IFS3
●
●
---- --00
---- --00
---- --00
---- --00
---- --uu
●
●
IFS3
PAS0
●
●
---- -000
---- -000
---- -000
---- -000
---- -uuu
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAS1
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PBS0
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PBS1
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PCS0
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PCS1
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PDS0
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PDS1
●
●
●
●
--00 0000
--00 0000
--00 0000
--00 0000
--uu uuuu
PES0
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PES1
●
●
●
●
---- --00
---- --00
---- --00
---- --00
---- --uu
PFS0
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PFS1
●
PGS0
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PGS1
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PHS0
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PHS1
●
●
●
---- 0000
---- 0000
---- 0000
---- 0000
---- uuuu
Note: "u" stands for unchanged
"x" stands for "unknown"
"-" stands for unimplemented
Rev. 1.00
90
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high selections for all ports and
wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a
wide range of application possibilities.
These devices provide bidirectional input/output lines. These I/O ports are mapped to the RAM
Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of
these I/O ports can be used for input and output operations. For input operation, these ports are
non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A,
[m]", where m denotes the port address. For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
Register
Name
Bit
7
6
5
4
3
2
1
0
PA
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PAC
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
PAPU7
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PAWU
PAWU7
PAWU6
PAWU5
PAWU4
PAWU3
PAWU2
PAWU1
PAWU0
PB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PBC
PBC7
PBC6
PBC5
PBC4
PBC3
PBC2
PBC1
PBC0
PBPU
PBPU7
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0
PC
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PCC
PCC7
PCC6
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
PCPU
PCPU7
PCPU6
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
PD
—
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PDC
—
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDPU
—
PDPU6
PDPU5
PDPU4
PDPU3
PDPU2
PDPU1
PDPU0
PE
—
—
—
PE4
PE3
PE2
PE1
PE0
PEC
—
—
—
PEC4
PEC3
PEC2
PEC1
PEC0
PEPU0
PEPU
—
—
—
PEPU4
PEPU3
PEPU2
PEPU1
PF
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PFC
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
PFPU
PFPU7
PFPU6
PFPU5
PFPU4
PFPU3
PFPU2
PFPU1
PFPU0
"—": Unimplemented, read as "0"
I/O Logic Function Registers List – HT66F2350
Rev. 1.00
91
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Bit
Register
Name
7
6
5
4
3
2
1
0
PA
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PAC
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
PAPU7
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PAWU
PAWU7
PAWU6
PAWU5
PAWU4
PAWU3
PAWU2
PAWU1
PAWU0
PB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PBC
PBC7
PBC6
PBC5
PBC4
PBC3
PBC2
PBC1
PBC0
PBPU
PBPU7
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0
PC
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PCC
PCC7
PCC6
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
PCPU
PCPU7
PCPU6
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
PD
—
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PDC
—
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDPU
—
PDPU6
PDPU5
PDPU4
PDPU3
PDPU2
PDPU1
PDPU0
PE
—
—
—
PE4
PE3
PE2
PE1
PE0
PEC
—
—
—
PEC4
PEC3
PEC2
PEC1
PEC0
PEPU0
PEPU
—
—
—
PEPU4
PEPU3
PEPU2
PEPU1
PF
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PFC
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
PFPU
PFPU7
PFPU6
PFPU5
PFPU4
PFPU3
PFPU2
PFPU1
PFPU0
PG
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
PGC
PGC7
PGC6
PGC5
PGC4
PGC3
PGC2
PGC1
PGC0
PGPU
PGPU7
PGPU6
PGPU5
PGPU4
PGPU3
PGPU2
PGPU1
PGPU0
PH
—
—
PH5
PH4
PH3
PH2
PH1
PH0
PHC
—
—
PHC5
PHC4
PHC3
PHC2
PHC1
PHC0
PHPU
—
—
PHPU5
PHPU4
PHPU3
PHPU2
PHPU1
PHPU0
"—": Unimplemented, read as "0"
I/O Logic Function Registers List – HT66F2360/HT66F2370/HT66F2390
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the
use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when
configured as an input have the capability of being connected to an internal pull-high resistor. These
pull-high resistors are selected using the relevant pull-high control registers and are implemented
using weak PMOS transistors. Note that the pull-high resistor can be controlled by the relevant
pull-high control register only when the pin-shared functional pin is selected as an input or NMOS
output. Otherwise, the pull-high resistors can not be enabled.
PxPU Register
Bit
7
6
5
4
3
2
1
0
Name
PxPU7
PxPU6
PxPU5
PxPU4
PxPU3
PxPU2
PxPU1
PxPU0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
PxPUn: I/O Port x Pin pull-high function control
0: Disable
1: Enable
The PxPUn bit is used to control the pin pull-high function. Here the "x" is the Port name which can
be A, B, C, D, E, F, G and H depending upon the selected device. However, the actual available bits
for each I/O Port may be different.
Rev. 1.00
92
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves
power, a feature that is important for battery and other low-power applications. Various methods
exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port
A pins from high to low. This function is especially suitable for applications that can be woken up
via external switches. Each pin on Port A can be selected individually to have this wake-up feature
using the PAWU register. Note that the wake-up function can be controlled by the wake-up control
registers only when the pin-shared functional pin is selected as general purpose input/output and the
MCU enters the Power down mode.
PAWU Register
Bit
7
6
5
4
3
2
1
0
Name
PAWU7
PAWU6
PAWU5
PAWU4
PAWU3
PAWU2
PAWU1
PAWU0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0PAWU7~PAWU0: Port A pin Wake-up function control
0: Disable
1: Enable
I/O Port Control Registers
Each Port has its own control register which controls the input/output configuration. With this
control register, each I/O pin with or without pull-high resistors can be reconfigured dynamically
under software control. For the I/O pin to function as an input, the corresponding bit of the control
register must be written as a "1". This will then allow the logic state of the input pin to be directly
read by instructions. When the corresponding bit of the control register is written as a "0", the I/O
pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still
be used to read the output register.
However, it should be noted that the program will in fact only read the status of the output data latch
and not the actual logic status of the output pin.
PxC Register
Bit
7
6
5
4
3
2
1
0
Name
PxC7
PxC6
PxC5
PxC4
PxC3
PxC2
PxC1
PxC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
PxCn: I/O Port × Pin type selection
0: Output
1: Input
The PxCn bit is used to control the pin type selection. Here the "x" is the Port name which can be A, B,
C, D, E, F, G and H depending upon the selected device. However, the actual available bits for each
I/O Port may be different.
Rev. 1.00
93
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
I/O Port Source Current Control
These devices support different source current driving capability for each I/O port. With the
selection register, SLEDCn, specific I/O port can support four levels of the source current driving
capability. Users should refer to the I/O Port characteristics section to select the desired source
current for different applications.
Bit
Register
Name
7
6
5
4
3
2
1
0
SLEDC0 SLEDC07 SLEDC06 SLEDC05 SLEDC04 SLEDC03 SLEDC02 SLEDC01 SLEDC00
SLEDC1 SLEDC17 SLEDC16 SLEDC15 SLEDC14 SLEDC13 SLEDC12 SLEDC11 SLEDC10
SLEDC2 SLEDC27 SLEDC26 SLEDC25 SLEDC24 SLEDC23 SLEDC22 SLEDC21 SLEDC20
I/O Port Source Current Control Registers List – HT66F2350
Bit
Register
Name
7
6
5
4
3
2
1
0
SLEDC0 SLEDC07 SLEDC06 SLEDC05 SLEDC04 SLEDC03 SLEDC02 SLEDC01 SLEDC00
SLEDC1 SLEDC17 SLEDC16 SLEDC15 SLEDC14 SLEDC13 SLEDC12 SLEDC11 SLEDC10
SLEDC2 SLEDC27 SLEDC26 SLEDC25 SLEDC24 SLEDC23 SLEDC22 SLEDC21 SLEDC20
SLEDC3 SLEDC37 SLEDC36 SLEDC35 SLEDC34 SLEDC33 SLEDC32 SLEDC31 SLEDC30
I/O Port Source Current Control Registers List – HT66F2360/HT66F2370/HT66F2390
SLEDC0 Register
Bit
Name
7
6
5
4
3
2
1
0
SLEDC07 SLEDC06 SLEDC05 SLEDC04 SLEDC03 SLEDC02 SLEDC01 SLEDC00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6SLEDC07~SLEDC06: PB7~PB4 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
Bit 5~4SLEDC05~SLEDC04: PB3~PB0 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
Bit 3~2SLEDC03~SLEDC02: PA7~PA4 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
Bit 1~0SLEDC01~SLEDC00: PA3~PA0 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
Rev. 1.00
94
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
SLEDC1 Register
Bit
Name
7
6
5
4
3
2
1
0
SLEDC17 SLEDC16 SLEDC15 SLEDC14 SLEDC13 SLEDC12 SLEDC11 SLEDC10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
1
0
Bit 7~6SLEDC17~SLEDC16: PD6~PD4 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
Bit 5~4SLEDC15~SLEDC14: PD3~PD0 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
Bit 3~2SLEDC13~SLEDC12: PC7~PC4 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
Bit 1~0SLEDC11~SLEDC10: PC3~PC0 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
SLEDC2 Register
Bit
Name
7
6
5
4
3
2
SLEDC27 SLEDC26 SLEDC25 SLEDC24 SLEDC23 SLEDC22 SLEDC21 SLEDC20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6SLEDC27~SLEDC26: PF7~PF4 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
Bit 5~4SLEDC25~SLEDC24: PF3~PF0 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
Bit 3~2SLEDC23~SLEDC22: PE4 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
Bit 1~0SLEDC21~SLEDC20: PE3~PE0 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
Rev. 1.00
95
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
SLEDC3 Register – HT66F2360/HT66F2370/HT66F2390
Bit
Name
7
6
5
4
3
2
1
0
SLEDC37 SLEDC36 SLEDC35 SLEDC34 SLEDC33 SLEDC32 SLEDC31 SLEDC30
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6SLEDC37~SLEDC36: PH5~PH4 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
Bit 5~4SLEDC35~SLEDC34: PH3~PH0 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
Bit 3~2SLEDC33~SLEDC32: PG7~PG4 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
Bit 1~0SLEDC31~SLEDC30: PG3~PG0 source current selection
00: source current=Level 0 (min.)
01: source current=Level 1
10: source current=Level 2
11: source current=Level 3 (max.)
I/O Port Power Source Control
These devices support different I/O port power source selections for PE3~PE0. The port power can
come from either the power pin VDD or VDDIO which is determined using the PMPS1~PMPS0
bits in the PMPS register. The VDDIO power pin function should first be selected using the
corresponding pin-shared function selection bits if the port power is supposed to come from the
VDDIO pin. An important point to know is that the input power voltage on the VDDIO pin should
be equal to or less than the device supply power voltage when the VDDIO pin is selected as the port
power supply pin.
PMPS Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
PMPS1
PMPS0
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1~0PMPS1~PMPS0: PE3~PE0 pin power source selection
0x: VDD
1x: VDDIO
Rev. 1.00
96
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more
than one function. Limited numbers of pins can force serious design constraints on designers but by
supplying pins with multi-functions, many of these difficulties can be overcome. For these pins, the
desired function of the multi-function I/O pins is selected by a series of registers via the application
program control.
Pin-shared Function Selection Registers
The limited number of supplied pins in a package can impose restrictions on the amount of functions
a certain device can contain. However by allowing the same pins to share several different functions
and providing a means of function selection, a wide range of different functions can be incorporated
into even relatively small package sizes. Each device includes Port "x" output function Selection
register "n", labeled as PxSn, and Input Function Selection register, labeled as IFSn, which can
select the desired functions of the multi-function pin-shared pins.
When the pin-shared input function is selected to be used, the corresponding input and output
functions selection should be properly managed. For example, if the I2C SDA line is used, the
corresponding output pin-shared function should be configured as the SDI/SDA function by
configuring the PxSn register and the SDA signal input should be properly selected using the IFSn
register. However, if the external interrupt function is selected to be used, the relevant output pinshared function should be selected as an I/O function and the interrupt input signal should be
selected.
The most important point to note is to make sure that the desired pin-shared function is properly
selected and also deselected. For most pin-shared functions, to select the desired pin-shared function,
the pin-shared function should first be correctly selected using the corresponding pin-shared control
register. After that the corresponding peripheral functional setting should be configured and then
the peripheral function can be enabled. However, special point must be noted for some digital input
pins, such as INTn, xTCKn, xTPnI, etc, which share the same pin-shared control configuration with
their corresponding general purpose I/O functions when setting the relevant pin-shared control bit
fields. To select these pin functions, in addition to the necessary pin-shared control and peripheral functional setup aforementioned, they must also be setup as input by setting the corresponding bit
in the I/O port control register. To correctly deselect the pin-shared function, the peripheral function
should first be disabled and then the corresponding pin-shared function control register can be
modified to select other pin-shared functions.
Rev. 1.00
97
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Register Name
PAS0
Bit
7
6
5
4
3
2
1
0
PAS07
PAS06
PAS05
PAS04
PAS03
PAS02
PAS01
PAS00
PAS1
PAS17
PAS16
PAS15
PAS14
PAS13
PAS12
PAS11
PAS10
PBS0
PBS07
PBS06
PBS05
PBS04
PBS03
PBS02
PBS01
PBS00
PBS1
PBS17
PBS16
PBS15
PBS14
PBS13
PBS12
PBS11
PBS10
PCS0
PCS07
PCS06
PCS05
PCS04
PCS03
PCS02
PCS01
PCS00
PCS1
PCS17
PCS16
PCS15
PCS14
PCS13
PCS12
PCS11
PCS10
PDS0
PDS07
PDS06
PDS05
PDS04
PDS03
PDS02
PDS01
PDS00
PDS1
—
—
PDS15
PDS14
PDS13
PDS12
PDS11
PDS10
PES0
PES07
PES06
PES05
PES04
PES03
PES02
PES01
PES00
PES1
—
—
—
—
—
—
PES11
PES10
PFS0
PFS07
PFS06
PFS05
PFS04
PFS03
PFS02
PFS01
PFS00
PFS1
PFS17
PFS16
PFS15
PFS14
PFS13
PFS12
PFS11
PFS10
PGS0
(HT66F2360/70/90)
PGS07
PGS06
PGS05
PGS04
PGS03
PGS02
PGS01
PGS00
PGS1
(HT66F2360/70/90)
PGS17
PGS16
PGS15
PGS14
PGS13
PGS12
PGS11
PGS10
PHS0
(HT66F2360/70/90)
PHS07
PHS06
PHS05
PHS04
PHS03
PHS02
PHS01
PHS00
PHS1
(HT66F2360/70/90)
—
—
—
—
PHS13
PHS12
PHS11
PHS10
IFS0
—
PTCK3PS PTCK2PS PTCK1PS PTCK0PS STCK2PS STCK1PS STCK0PS
IFS1
—
PTP3IPS
IFS2
—
SCSBPS SDISDAPS SCKSCLPS
IFS3 (HT66F2350/60)
—
—
—
IFS3 (HT66F2370/90)
—
—
—
PTP2IPS
PTP1IPS
PTP0IPS
STP2IPS
STP1IPS
STP0IPS
INT3PS
INT2PS
INT1PS
INT0PS
—
—
—
RX1PS
RX0PS
—
—
RX2PS
RX1PS
RX0PS
Pin-shared Function Selection Registers List
• PAS0 Register
Bit
7
6
5
4
3
2
1
0
Name
PAS07
PAS06
PAS05
PAS04
PAS03
PAS02
PAS01
PAS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PAS07~PAS06: PA3 pin function selection
00, 01, 10: PA3/INT1
11: SDO
Bit 5~4PAS05~PAS04: PA2 pin function selection
00, 01, 10, 11: PA2
Bit 3~2PAS03~PAS02: PA1 pin function selection
00, 01, 10: PA1/INT0
11: SCS
Bit 1~0PAS01~PAS00: PA0 pin function selection
00, 01, 10, 11: PA0
Rev. 1.00
98
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
• PAS1 Register
Bit
7
6
5
4
3
2
1
0
Name
PAS17
PAS16
PAS15
PAS14
PAS13
PAS12
PAS11
PAS10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
PAS17~PAS16: PA7 pin function selection
00, 01, 10: PA7/INT1
11: TX0
Bit 5~4PAS15~PAS14: PA6 pin function selection
00, 01, 10: PA6/INT0
11: RX0
Bit 3~2PAS13~PAS12: PA5 pin function selection
00, 01, 10: PA5/INT3
11: SCK/SCL
Bit 1~0PAS11~PAS10: PA4 pin function selection
00, 01, 10: PA4/INT2
11: SDI/SDA
Bit 7~6
• PBS0 Register – HT66F2350/HT66F2360
Bit
7
6
5
4
3
2
1
0
Name
PBS07
PBS06
PBS05
PBS04
PBS03
PBS02
PBS01
PBS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
PBS07~PBS06: PB3 pin function selection
00, 01, 10: PB3/PTP2I
11: PTP2
Bit 5~4PBS05~PBS04: PB2 pin function selection
00, 01, 10: PB2/PTP3I/PTCK2
11: PTP3
Bit 3~2PBS03~PBS02: PB1 pin function selection
00, 01, 10, 11: PB1/PTCK3
Bit 1~0PBS01~PBS00: PB0 pin function selection
00, 01, 10: PB0/STCK2
11: C0X
Bit 7~6
• PBS0 Register – HT66F2370/HT66F2390
Bit
7
6
5
4
3
2
1
0
Name
PBS07
PBS06
PBS05
PBS04
PBS03
PBS02
PBS01
PBS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
PBS07~PBS06: PB3 pin function selection
00, 01, 10: PB3/PTP2I
11: PTP2
Bit 5~4
PBS05~PBS04: PB2 pin function selection
00, 01: PB2/PTP3I/PTCK2
10: RX2
11: PTP3
Bit 3~2PBS03~PBS02: PB1 pin function selection
00, 01, 10: PB1/PTCK3
11: TX2
Bit 1~0PBS01~PBS00: PB0 pin function selection
00, 01, 10: PB0/STCK2
11: C0X
Bit 7~6
Rev. 1.00
99
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
• PBS1 Register
Bit
7
6
5
4
3
2
1
0
Name
PBS17
PBS16
PBS15
PBS14
PBS13
PBS12
PBS11
PBS10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PBS17~PBS16: PB7 pin function selection
00, 01, 10: PB7/STCK1
11: OSC2
Bit 5~4PBS15~PBS14: PB6 pin function selection
00, 01: PB6/STP1I
10: STP1
11: OSC1
Bit 3~2PBS13~PBS12: PB5 pin function selection
00, 01, 10, 11: PB5/RES
Bit 1~0PBS11~PBS10: PB4 pin function selection
00, 01, 10: PB4
11: C1X
• PCS0 Register
Bit
7
6
5
4
3
2
1
0
Name
PCS07
PCS06
PCS05
PCS04
PCS03
PCS02
PCS01
PCS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PCS07~PCS06: PC3 pin function selection
00, 01, 10: PC3/PTCK0
11: AN3
Bit 5~4PCS05~PCS04: PC2 pin function selection
00, 01: PC2/PTP0I
10: PTP0
11: AN2
Bit 3~2PCS03~PCS02: PC1 pin function selection
00: PC1
01: C0X
10: VREF
11: AN1
Bit 1~0PCS01~PCS00: PC0 pin function selection
0x: PC0
10: VREFI
11: AN0
Rev. 1.00
100
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
• PCS1 Register
Bit
7
6
5
4
3
2
1
0
Name
PCS17
PCS16
PCS15
PCS14
PCS13
PCS12
PCS11
PCS10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PCS17~PCS16: PC7 pin function selection
00, 01, 10: PC7/INT3/STCK0
11: AN7
Bit 5~4PCS15~PCS14: PC6 pin function selection
00, 01: PC6/STP0I
10: STP0
11: AN6
Bit 3~2PCS13~PCS12: PC5 pin function selection
00, 01, 10: PC5/PTCK1
11: AN5
Bit 1~0PCS11~PCS10: PC4 pin function selection
00, 01: PC4/PTP1I
10: PTP1
11: AN4
• PDS0 Register
Bit
7
6
5
4
3
2
1
0
Name
PDS07
PDS06
PDS05
PDS04
PDS03
PDS02
PDS01
PDS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PDS07~PDS06: PD3 pin function selection
00, 01, 10: PD3/PTCK2
11: AN11
Bit 5~4PDS05~PDS04: PD2 pin function selection
00: PD2/PTP2I
01: PTP2
10: TX1
11: AN10
Bit 3~2PDS03~PDS02: PD1 pin function selection
00, 01: PD1/STCK1
10: RX1
11: AN9
Bit 1~0PDS01~PDS00: PD0 pin function selection
00, 01: PD0/INT2/STP1I
10: STP1
11: AN8
Rev. 1.00
101
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
• PDS1 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
PDS15
PDS14
PDS13
PDS12
PDS11
PDS10
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Unimplemented, read as "0"
Bit 5~4PDS15~PDS14: PD6 pin function selection
00, 01: PD6/STP2I
10: STP2
11: C1X
Bit 3~2PDS13~PDS12: PD5 pin function selection
00, 01: PD5/PTCK3
10: TX0
11: C1+
Bit 1~0PDS11~PDS10: PD4 pin function selection
00: PD4/PTP3I
01: RX0
10: PTP3
11: C1−
• PES0 Register
Bit
7
6
5
4
3
2
1
0
Name
PES07
PES06
PES05
PES04
PES03
PES02
PES01
PES00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PES07~PES06: PE3 pin function selection
00, 01: PE3/PTP1I
10: PTP1
11: SCKA
Bit 5~4PES05~PES04: PE2 pin function selection
00, 01, 10: PE2/PTCK1
11: SDIA
Bit 3~2PES03~PES02: PE1 pin function selection
00, 01: PE1/STP0I
10: STP0
11: SDOA
Bit 1~0PES01~PES00: PE0 pin function selection
00, 01, 10: PE0/STCK0
11: SCSA
• PES1 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
PES11
PES10
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1~0PES11~PES10: PE4 pin function selection
00, 01, 10: PE4
11: VDDIO
Rev. 1.00
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
• PFS0 Register
Bit
7
6
5
4
3
2
1
0
Name
PFS07
PFS06
PFS05
PFS04
PFS03
PFS02
PFS01
PFS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PFS07~PFS06: PF3 pin function selection
00, 01: PF3
10: SCK/SCL
11: SCOM3
Bit 5~4PFS05~PFS04: PF2 pin function selection
00, 01: PF2
10: SDI/SDA
11: SCOM2
Bit 3~2PFS03~PFS02: PF1 pin function selection
00, 01: PF1
10: SDO
11: SCOM1
Bit 1~0PFS01~PFS00: PF0 pin function selection
00, 01: PF0
10: SCS
11: SCOM0
• PFS1 Register
Bit
7
6
5
4
3
2
1
0
Name
PFS17
PFS16
PFS15
PFS14
PFS13
PFS12
PFS11
PFS10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PFS17~PFS16: PF7 pin function selection
00: PF7/STP2I
01: TX1
10: STP2
11: C0+
Bit 5~4PFS15~PFS14: PF6 pin function selection
00, 01: PF6/STCK2
10: RX1
11: C0−
Bit 3~2PFS13~PFS12: PF5 pin function selection
00, 01: PF5/PTP0I
10: PTP0
11: XT1
Bit 1~0PFS11~PFS10: PF4 pin function selection
00, 01, 10: PF4/PTCK0
11: XT2
Rev. 1.00
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
• PGS0 Register – HT66F2360
Bit
7
6
5
4
3
2
1
0
Name
PGS07
PGS06
PGS05
PGS04
PGS03
PGS02
PGS01
PGS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PGS07~PGS06: PG3 pin function selection
00, 01, 10, 11: PG3
Bit 5~4PGS05~PGS04: PG2 pin function selection
00, 01, 10, 11: PG2
Bit 3~2PGS03~PGS02: PG1 pin function selection
00, 01, 10, 11: PG1
Bit 1~0PGS01~PGS00: PG0 pin function selection
00, 01, 10, 11: PG0
• PGS0 Register – HT66F2370/HT66F2390
Bit
7
6
5
4
3
2
1
0
Name
PGS07
PGS06
PGS05
PGS04
PGS03
PGS02
PGS01
PGS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PGS07~PGS06: PG3 pin function selection
00, 01, 10, 11: PG3
Bit 5~4PGS05~PGS04: PG2 pin function selection
00, 01, 10, 11: PG2
Bit 3~2PGS03~PGS02: PG1 pin function selection
00, 01, 10: PG1
11: TX2
Bit 1~0PGS01~PGS00: PG0 pin function selection
00, 01, 10: PG0
11: RX2
• PGS1 Register – HT66F2360/HT66F2370/HT66F2390
Bit
7
6
5
4
3
2
1
0
Name
PGS17
PGS16
PGS15
PGS14
PGS13
PGS12
PGS11
PGS10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PGS17~PGS16: PG7 pin function selection
00, 01, 10, 11: PG7
Bit 5~4PGS15~PGS14: PG6 pin function selection
00, 01, 10, 11: PG6
Bit 3~2PGS13~PGS12: PG5 pin function selection
00, 01, 10, 11: PG5
Bit 1~0PGS11~PGS10: PG4 pin function selection
00, 01, 10, 11: PG4
Rev. 1.00
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
• PHS0 Register – HT66F2360/HT66F2370/HT66F2390
Bit
7
6
5
4
3
2
1
0
Name
PHS07
PHS06
PHS05
PHS04
PHS03
PHS02
PHS01
PHS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PHS07~PHS06: PH3 pin function selection
00, 01, 10: PH3
11: AN13
Bit 5~4PHS05~PHS04: PH2 pin function selection
00, 01, 10: PH2
11: AN12
Bit 3~2PHS03~PHS02: PH1 pin function selection
00, 01, 10, 11: PH1
Bit 1~0PHS01~PHS00: PH0 pin function selection
00, 01, 10, 11: PH0
• PHS1 Register – HT66F2360/HT66F2370/HT66F2390
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
PHS13
PHS12
PHS11
PHS10
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7~4
Unimplemented, read as "0"
Bit 3~2PHS13~PHS12: PH5 pin function selection
00, 01, 10: PH5
11: AN15
Bit 1~0PHS11~PHS10: PH4 pin function selection
00, 01, 10: PH4
11: AN14
• IFS0 Register
Bit
7
6
5
4
3
2
1
0
Name
—
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
PTCK3PS PTCK2PS PTCK1PS PTCK0PS STCK2PS STCK1PS STCK0PS
Bit 7
Unimplemented, read as "0"
Bit 6PTCK3PS: PTCK3 input source pin selection
0: PD5
1: PB1
Bit 5PTCK2PS: PTCK2 input source pin selection
0: PD3
1: PB2
Bit 4PTCK1PS: PTCK1 input source pin selection
0: PC5
1: PE2
Bit 3PTCK0PS: PTCK0 input source pin selection
0: PC3
1: PF4
Bit 2STCK2PS: STCK2 input source pin selection
0: PF6
1: PB0
Bit 1STCK1PS: STCK1 input source pin selection
0: PD1
1: PB7
Bit 0STCK0PS: STCK0 input source pin selection
0: PC7
1: PE0
Rev. 1.00
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
• IFS1 Register
Bit
7
Name
—
6
5
4
3
2
1
0
PTP3IPS PTP2IPS PTP1IPS PTP0IPS STP2IPS STP1IPS STP0IPS
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as "0"
Bit 6PTP3IPS: PTP3I input source pin selection
0: PD4
1: PB2
Bit 5PTP2IPS: PTP2I input source pin selection
0: PD2
1: PB3
Bit 4PTP1IPS: PTP1I input source pin selection
0: PC4
1: PE3
Bit 3PTP0IPS: PTP0I input source pin selection
0: PC2
1: PF5
Bit 2STP2IPS: STP2I input source pin selection
0: PD6
1: PF7
Bit 1STP1IPS: STP1I input source pin selection
0: PD0
1: PB6
Bit 0STP0IPS: STP0I input source pin selection
0: PC6
1: PE1
• IFS2 Register
Bit
7
Name
—
6
5
4
3
SCSBPS SDISDAPS SCKSCLPS INT3PS
2
1
0
INT2PS
INT1PS
INT0PS
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as "0"
Bit 6SCSBPS: SCS input source pin selection
0: PA1
1: PF0
Bit 5SDISDAPS: SDI/SDA input source pin selection
0: PA4
1: PF2
Bit 4SCKSCLPS: SCK/SCL input source pin selection
0: PA5
1: PF3
Bit 3INT3PS: INT3 input source pin selection
0: PA5
1: PC7
Bit 2INT2PS: INT2 input source pin selection
0: PA4
1: PD0
Bit 1INT1PS: INT1 input source pin selection
0: PA3
1: PA7
Bit 0INT0PS: INT0 input source pin selection
0: PA1
1: PA6
Rev. 1.00
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
• IFS3 Register – HT66F2350/HT66F2360
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
RX1PS
RX0PS
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1RX1PS: RX1 input source pin selection
0: PD1
1: PF6
Bit 0RX0PS: RX0 input source pin selection
0: PA6
1: PD4
• IFS3 Register – HT66F2370/HT66F2390
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
RX2PS
RX1PS
RX0PS
R/W
—
—
—
—
—
R/W
R/W
R/W
POR
—
—
—
—
—
0
0
0
Bit 7~3
Unimplemented, read as "0"
Bit 2RX2PS: RX2 input source pin selection
0: PB2
1: PG0
Bit 1RX1PS: RX1 input source pin selection
0: PD1
1: PF6
Bit 0RX0PS: RX0 input source pin selection
0: PA6
1: PD4
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
I/O Pin Structures
The accompanying diagram illustrates the internal structures of the I/O logic function. As the exact
logical construction of the I/O pin will differ from this drawing, it is supplied as a guide only to
assist with the functional understanding of the logic function I/O pins. The wide range of pin-shared
structures does not permit all types to be shown.
VDD
Pull-high
Register
Select
Control Bit
Data Bus
Write Control Register
D
CK
Q
S
Weak
Pull-up
Q
Chip RESET
I/O pin
Read Control Register
Data Bit
D
Write Data Register
CK
Q
S
Q
IECM
M
U
X
Read Data Register
System Wake-up
Wake-up Select
PA only
Logic Function Input/Output Structure
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
Read Port Function
The READ PORT function is used to manage the reading of the output data from the data latch or I/O
pin, which is specially designed for the IEC60730 self-diagnostic test on the I/O function and A/D
paths. There is a register, IECC, which is used to control the READ PORT function. If the READ
PORT function is disabled, the pin function will operate as the selected pin-shared function. When
a specific data pattern, “11001010”, is written into the IECC register, the internal signal named
IECM will be set high to enable the READ PORT function. If the READ PORT function is enabled,
the value on the corresponding pins will be passed to the accumulator ACC when the read port
instruction “mov acc, Px” is executed where the “x” stands for the corresponding I/O port name.
IECC Register
Bit
7
6
5
4
3
2
1
0
Name
IECS7
IECS6
IECS5
IECS4
IECS3
IECS2
IECS1
IECS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0IECS7~IEC0: READ PORT function enable control bit 7~ bit 0
11001010: IECM=1 – READ PORT function is enabled
Others: IECM=0 – READ PORT function is disabled
READ PORT Function
Disabled
Port Control Register Bit – PxC.n
1
I/O Function
Enabled
0
1
0
Pin value
Digital Input Function
Digital Output Function (except I2C SDA/
SCL)
0
I C SDA/SCL
Data latch value
Pin value
Pin value
2
Analog Function
0
Note: The value on the above table is the content of the ACC register after “mov a, Px” instruction is
executed where “x” means the relevant port name.
The additional function of the READ PORT mode is to check the A/D path. When the READ PORT
function is disabled, the A/D path from the external pin to the internal analog input will be switched
off if the A/D input pin function is not selected by the corresponding selection bits. For the MCU
with A/D converter channels, such as A/D AN15~AN0, the desired A/D channel can be switched on
by properly configuring the external analog input channel selection bits in the A/D Control Register
together with the corresponding analog input pin function is selected. However, the additional
function of the READ PORT mode is to force the A/D path to be switched on. For example, when
the AN0 is selected as the analog input channel as the READ PORT function is enabled, the AN0
analog input path will be switched on even if the AN0 analog input pin function is not selected. In
this way, the AN0 analog input path can be examined by internally connecting the digital output on
this shared pin with the AN0 analog input pin switch and then converting the corresponding digital
data without any external analog input voltage connected.
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
Digital Output
Function
AN0
READ PORT function enabled,
AN0 Pin-shared path switched
on automatically
A/D Converter
AN15
External analog input
channel selection
A/D Channel Input Path Internally Connection
Programming Considerations
Within the user program, one of the things first to consider is port initialisation. After a reset, all
of the I/O data and port control registers will be set to high. This means that all I/O pins will be
defaulted to an input state, the level of which depends on the other connected circuitry and whether
pull-high selections have been chosen. If the port control registers are then programmed to setup
some pins as outputs, these output pins will have an initial high output value unless the associated
port data registers are first programmed. Selecting which pins are inputs and which are outputs can
be achieved byte-wide by loading the correct values into the appropriate port control register or
by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i"
instructions. Note that when using these bit control instructions, a read-modify-write operation takes
place. The microcontroller must first read in the data on the entire port, modify it to the required new
bit values and then rewrite this data back to the output ports.
Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP
or IDLE Mode, various methods are available to wake the device up. One of these is a high to low
transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.
Rev. 1.00
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Timer Modules – TM
One of the most fundamental functions in any microcontroller devices is the ability to control and
measure time. To implement time related functions the device includes several Timer Modules,
generally abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide
operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output
as well as being the functional unit for the generation of PWM signals. Each of the TMs has two
interrupts. The addition of input and output pins for each TM ensures that users are provided with
timing units with a wide and flexible range of features.
The common features of the different TM types are described here with more detailed information
provided in the individual Standard and Periodic TM sections.
Introduction
These devices contain seven TMs and each individual TM can be categorised as a certain type,
namely Standard Type TM or Periodic Type TM. Although similar in nature, the different TM types
vary in their feature complexity. The common features to all of the Standard and Periodic TMs
will be described in this section and the detailed operation regarding each of the TM types will be
described in separate sections. The main features and differences between the two types of TMs are
summarised in the accompanying table.
STM
PTM
Timer/Counter
TM Function
√
√
Input Capture
√
√
Compare Match Output
√
√
PWM Channels
1
1
Single Pulse Output
PWM Alignment
PWM Adjustment Period & Duty
1
1
Edge
Edge
Duty or Period
Duty or Period
TM Function Summary
TM Operation
The different types of TM offer a diverse range of functions, from simple timing operations to PWM
signal generation. The key to understanding how the TM operates is to see it in terms of a free
running count-up counter whose value is then compared with the value of pre-programmed internal
comparators. When the free running count-up counter has the same value as the pre-programmed
comparator, known as a compare match situation, a TM interrupt signal will be generated which
can clear the counter and perhaps also change the condition of the TM output pin. The internal TM
counter is driven by a user selectable clock source, which can be an internal clock or an external pin.
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
TM Clock Source
The clock source which drives the main counter in each TM can originate from various sources.
The selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the
xTMn control registers, where "x" stands for S or P type TM and "n" stands for the specific TM
serial number. The clock source can be a ratio of the system clock, fSYS, or the internal high clock,
fH, the fSUB clock source or the external xTCKn pin. The xTCKn pin clock source is used to allow an
external signal to drive the TM as an external clock source for event counting.
TM Interrupts
The Standard or Periodic type TM has two internal interrupt, one for each of the internal comparator
A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a
TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM
output pin.
TM External Pins
Each of the TMs, irrespective of what type, has two TM input pins, with the label xTCKn and xTPnI
respectively. The xTMn input pin, xTCKn, is essentially a clock source for the xTMn and is selected
using the xTnCK2~xTnCK0 bits in the xTMnC0 register. This external TM input pin allows an
external clock source to drive the internal TM. The xTCKn input pin can be chosen to have either a
rising or falling active edge. The STCKn and PTCKn pins are also used as the external trigger input
pin in single pulse output mode for the STMn and PTMn respectively.
The other xTM input pin, STPnI or PTPnI, is the capture input whose active edge can be a
rising edge, a falling edge or both rising and falling edges and the active edge transition type is
selected using the STnIO1~STnIO0 or PTnIO1~PTnIO0 bits in the STMnC1 or PTMnC1 register
respectively. There is another capture input, PTCKn, for PTMn capture input mode, which can be
used as the external trigger input source except the PTPnI pin.
The TMs each have one output pin, xTPn. The TM output pin can be selected using the
corresponding pin-shared function selection bits described in the Pin-shared Function section. When
the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to
a high or low level or to toggle when a compare match situation occurs. The external xTPn output
pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are
pin-shared with other functions, the TM output function must first be setup using relevant pin-shared
function selection register.
Device
HT66F2350
HT66F2360
HT66F2370
HT66F2390
STM
Input
STCK0, STP0I
STCK1, STP1I
STCK2, STP2I
PTM
Output
Input
Output
STP0
STP1
STP2
PTCK0, PTP0I
PTCK1, PTP1I
PTCK2, PTP2I
PTCK3, PTP3I
PTP0
PTP1
PTP2
PTP3
TM External Pins
Rev. 1.00
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
TM Input/Output Pin Selection
Selecting to have a TM input/output or whether to retain its other shared function is implemented
using the relevant pin-shared function selection registers, with the corresponding selection bits in
each pin-shared function register corresponding to a TM input/output pin. Configuring the selection
bits correctly will setup the corresponding pin as a TM input/output. The details of the pin-shared
function selection are described in the pin-shared function section.
Clock input
CCR capture input
STCKn
STPnI
STMn
CCR output
STPn
STM Function Pin Control Block Diagram (n=0 ~ 2)
Clock/capture input
CCR capture input
PTCKn
PTPnI
PTMn
CCR output
PTPn
PTM Function Pin Control Block Diagram (n=0 ~ 3)
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
Programming Considerations
The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low
and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be
accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in
a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its
related low byte only takes place when a write or read operation to its corresponding high byte is
executed.
As the CCRA and CCRP registers are implemented in the way shown in the following diagram and
accessing these register pairs is carried out in a specific way as described above, it is recommended
to use the "MOV" instruction to access the CCRA and CCRP low byte registers, named xTMnAL
and PTMnRPL, using the following access procedures. Accessing the CCRA or CCRB low byte
registers without following these access procedures will result in unpredictable values.
xTMn Counte� Registe� (Read only)
xTMnDL
xTMnDH
8-�it Buffe�
xTMnAL
xTMnAH
xTMn CCRA Registe� (Read/W�ite)
PTMnRPL PTMnRPH
PTMn CCRP Registe� (Read/W�ite)
Data Bus
The following steps show the read and write procedures:
• Writing Data to CCRA or CCRP
♦♦
Step 1. Write data to Low Byte xTMnAL or PTMnRPL
––note that here data is only written to the 8-bit buffer.
♦♦
Step 2. Write data to High Byte xTMnAH or PTMnRPH
––here data is written directly to the high byte registers and simultaneously data is latched
from the 8-bit buffer to the Low Byte registers.
• Reading Data from the Counter Registers and CCRA or CCRP
Rev. 1.00
♦♦
Step 1. Read data from the High Byte xTMnDH, xTMnAH or PTMnRPH
––here data is read directly from the High Byte registers and simultaneously data is latched
from the Low Byte register into the 8-bit buffer.
♦♦
Step 2. Read data from the Low Byte xTMnDL, xTMnAL or PTMnRPL
––this step reads data from the 8-bit buffer.
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Standard Type TM – STM
The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can
also be controlled with two external input pins and can drive one external output pin.
Device
STM Core
STM Input Pin
STM Output Pin
HT66F2350
HT66F2360
HT66F2370
HT66F2390
16-bit STM
(STM0, STM1, STM2)
STCK0, STP0I
STCK1, STP1I
STCK2, STP2I
STP0
STP1
STP2
CCRP
fSYS/4
fSYS
fH/16
fH/64
fSUB
fSUB
8-bit Comparator P
001
011
16-bit Count-up Counter
100
101
STnON
STnPAU
Counter Clear
0
1
STnCCLR
b0~b15
111
STnCK2~STnCK0
16-bit Comparator A
STMnPF Interrupt
STnOC
b8~b15
010
110
STCKn
Comparator P Match
000
Comparator A Match
Output
Control
Polarity
Control
Pin
Control
STnM1, STnM0
STnIO1, STnIO0
STnPOL
PxSn
STPn
STMnAF Interrupt
STnIO1, STnIO0
Edge
Detector
CCRA
STPnI
Standard Type TM Block Diagram (n=0 ~ 2)
Standard TM Operation
The size of Standard TM is 16-bit wide and its core is a 16-bit count-up counter which is driven by
a user selectable internal or external clock source. There are also two internal comparators with the
names, Comparator A and Comparator P. These comparators will compare the value in the counter
with CCRP and CCRA registers. The CCRP comparator is 8-bit wide whose value is compared the
with highest 8 bits in the counter while the CCRA is the sixteen bits and therefore compares all
counter bits.
The only way of changing the value of the 16-bit counter using the application program, is to
clear the counter by changing the STnON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a STM interrupt signal will also usually be generated. The Standard
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control an output pin. All operating setup conditions are
selected using relevant internal registers.
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
Standard Type TM Register Description
Overall operation of the Standard TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store
the internal 16-bit CCRA value. The STMnRP register is used to store the 8-bit CCRP value. The
remaining two registers are control registers which setup the different operating and control modes.
Bit
Register
Name
7
6
5
4
3
2
1
0
STMnC0
STnPAU
STnCK2
STnCK1
STnCK0
STnON
—
—
—
STMnC1
STnM1
STnM0
STnIO1
STnIO0
STnOC
STMnDL
D7
D6
D5
D4
D3
D2
D1
D0
STMnDH
D15
D14
D13
D12
D11
D10
D9
D8
D0
STnPOL STnDPX STnCCLR
STMnAL
D7
D6
D5
D4
D3
D2
D1
STMnAH
D15
D14
D13
D12
D11
D10
D9
D8
STMnRP
STnRP7
STnRP6
STnRP5
STnRP4
STnRP3
STnRP2
STnRP1
STnRP0
16-bit Standard TM Registers List (n=0 ~ 2)
STMnDL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
STMn Counter Low Byte Register bit 7 ~ bit 0
STMn 16-bit Counter bit 7 ~ bit 0
STMnDH Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
STMn Counter High Byte Register bit 7 ~ bit 0
STMn 16-bit Counter bit 15 ~ bit 8
STMnAL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
STMn CCRA Low Byte Register bit 7 ~ bit 0
STMn 16-bit CCRA bit 7 ~ bit 0
STMnAH Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
STMn CCRA High Byte Register bit 7 ~ bit 0
STMn 16-bit CCRA bit 15 ~ bit 8
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STMnC0 Register
Bit
7
6
5
4
3
2
1
0
Name
STnPAU
STnCK2
STnCK1
STnCK0
STnON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7STnPAU: STMn Counter Pause control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the STMn will remain powered
up and continue to consume power. The counter will retain its residual value when
this bit changes from low to high and resume counting from this value when the bit
changes to a low value again.
Bit 6~4STnCK2~STnCK0: Select STMn Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fSUB
101: fSUB
110: STCKn rising edge clock
111: STCKn falling edge clock
These three bits are used to select the clock source for the STMn. The external pin
clock source can be chosen to be active on the rising or falling edge. The clock source
fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which
can be found in the oscillator section.
Bit 3STnON: STMn Counter On/Off control
0: Off
1: On
This bit controls the overall on/off function of the STMn. Setting the bit high enables
the counter to run while clearing the bit disables the STMn. Clearing this bit to zero
will stop the counter from counting and turn off the STMn which will reduce its power
consumption. When the bit changes state from low to high the internal counter value will
be reset to zero, however when the bit changes from high to low, the internal counter will
retain its residual value until the bit returns high again. If the STMn is in the Compare
Match Output Mode then the STMn output pin will be reset to its initial condition, as
specified by the STnOC bit, when the STnON bit changes from low to high.
Bit 2~0
Rev. 1.00
Unimplemented, read as "0"
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STMnC1 Register
Bit
7
6
5
4
3
Name
STnM1
STnM0
STnIO1
STnIO0
STnOC
2
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
STnPOL STnDPX
0
STnCCLR
Bit 7~6STnM1~STnM0: Select STMn Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the STMn. To ensure reliable
operation the STMn should be switched off before any changes are made to the
STnM1 and STnM0 bits. In the Timer/Counter Mode, the STMn output pin control
will be disabled.
Bit 5~4STnIO1~STnIO0: Select STMn external pin STPn function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Output Mode/Single Pulse Output Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Single Pulse Output
Capture Input Mode
00: Input capture at rising edge of STPnI
01: Input capture at falling edge of STPnI
10: Input capture at rising/falling edge of STPnI
11: Input capture disabled
Timer/Counter Mode
Unused
These two bits are used to determine how the STMn output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the STMn is running.
In the Compare Match Output Mode, the STnIO1 and STnIO0 bits determine how the
STMn output pin changes state when a compare match occurs from the Comparator
A. The TM output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the STMn
output pin should be setup using the STnOC bit in the STMnC1 register. Note that
the output level requested by the STnIO1 and STnIO0 bits must be different from the
initial value setup using the STnOC bit otherwise no change will occur on the STMn
output pin when a compare match occurs. After the STMn output pin changes state,
it can be reset to its initial level by changing the level of the STnON bit from low to
high.
In the PWM Output Mode, the STnIO1 and STnIO0 bits determine how the STMn
output pin changes state when a certain compare match condition occurs. The PWM
output function is modified by changing these two bits. It is necessary to only change
the values of the STnIO1 and STnIO0 bits only after the STMn has been switched off.
Unpredictable PWM outputs will occur if the STnIO1 and STnIO0 bits are changed
when the STMn is running.
Rev. 1.00
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Bit 3STnOC: STMn STPn Output control
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Output Mode/Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the STMn output pin. Its operation depends upon
whether STMn is being used in the Compare Match Output Mode or in the PWM
Mode/Single Pulse Output Mode. It has no effect if the STMn is in the Timer/Counter
Mode. In the Compare Match Output Mode it determines the logic level of the STMn
output pin before a compare match occurs. In the PWM Output Mode/Single Pulse
Output Mode it determines if the PWM signal is active high or active low.
Bit 2STnPOL: STMn STPn Output polarity control
0: Non-inverted
1: Inverted
This bit controls the polarity of the STPn output pin. When the bit is set high the
STMn output pin will be inverted and not inverted when the bit is zero. It has no effect
if the STMn is in the Timer/Counter Mode.
Bit 1STnDPX: STMn PWM duty/period control
0: CCRP – period; CCRA – duty
1: CCRP – duty; CCRA – period
This bit determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
Bit 0STnCCLR: STMn Counter Clear condition selection
0: Comparator P match
1: Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Standard TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the STnCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The STnCCLR bit is not
used in the PWM Output, Single Pulse Output or Capture Input Mode.
STMnRP Register
Bit
7
6
5
4
3
2
1
0
Name
STnRP7
STnRP6
STnRP5
STnRP4
STnRP3
STnRP2
STnRP1
STnRP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0STnRP7~STnRP0: STMn CCRP 8-bit register, compared with the STMn counter bit 15~bit 8
Comparator P match period =
0: 65536 STMn clocks
1~255: (1~255) × 256 STMn clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which
are then compared with the internal counter’s highest eight bits. The result of this
comparison can be selected to clear the internal counter if the STnCCLR bit is set to
zero. Setting the STnCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest eight counter bits, the compare values exist in 256 clock cycle multiples.
Clearing all eight bits to zero is in effect allowing the counter to overflow at its
maximum value.
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
Standard Type TM Operation Modes
The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the STnM1 and STnM0 bits in the STMnC1 register.
Compare Match Output Mode
To select this mode, bits STnM1 and STnM0 in the STMnC1 register, should be set to 00
respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the STnCCLR bit is low, there are two ways in which the counter can be
cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all
zero which allows the counter to overflow. Here both STMnAF and STMnPF interrupt request flags
for Comparator A and Comparator P respectively, will both be generated.
If the STnCCLR bit in the STMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the STMnAF interrupt request flag will
be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore
when STnCCLR is high no STMnPF interrupt request flag will be generated. In the Compare Match
Output Mode, the CCRA can not be set to "0".
As the name of the mode suggests, after a comparison is made, the STMn output pin, will change
state. The STMn output pin condition however only changes state when a STMnAF interrupt request
flag is generated after a compare match occurs from Comparator A. The STMnPF interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the STMn
output pin. The way in which the STMn output pin changes state are determined by the condition of
the STnIO1 and STnIO0 bits in the STMnC1 register. The STMn output pin can be selected using
the STnIO1 and STnIO0 bits to go high, to go low or to toggle from its present condition when a
compare match occurs from Comparator A. The initial condition of the STMn output pin, which is
setup after the STnON bit changes from low to high, is setup using the STnOC bit. Note that if the
STnIO1 and STnIO0 bits are zero then no pin change will take place.
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
Counte� Value
Counte� ove�flow
CCRP=0
0xFFFF
STnCCLR = 0; STnM [1:0] = 00
CCRP > 0
Counte� �lea�ed �y CCRP value
CCRP > 0
Counte�
Resta�t
Resu�e
CCRP
Pause
CCRA
Stop
Ti�e
STnON
STnPAU
STnPOL
CCRP Int.
flag STMnPF
CCRA Int.
flag STMnAF
STMn
O/P Pin
Output pin set to
initial Level Low
if STnOC=0
Output not affe�ted �y STMnAF
flag. Re�ains High until �eset �y
STnON �it
Output Toggle with
STMnAF flag
He�e STnIO [1:0] = 11
Toggle Output sele�t
Note STnIO [1:0] = 10
A�tive High Output sele�t
Output Inve�ts
when STnPOL is high
Output Pin
Reset to Initial value
Output �ont�olled �y
othe� pin-sha�ed fun�tion
Compare Match Output Mode – STnCCLR=0
Note: 1. With STnCCLR=0 a Comparator P match will clear the counter
2. The STMn output pin is controlled only by the STMnAF flag
3. The output pin is reset to its initial state by a STnON bit rising edge
4. n=0 ~ 2
Rev. 1.00
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Counte� Value
STnCCLR = 1; STnM [1:0] = 00
CCRA = 0
Counte� ove�flow
CCRA > 0 Counte� �lea�ed �y CCRA value
0xFFFF
Resu�e
CCRA
Pause
CCRA=0
Stop
Counte� Resta�t
CCRP
Ti�e
STnON
STnPAU
STnPOL
No STMnAF flag
gene�ated on
CCRA ove�flow
CCRA Int.
flag STMnAF
CCRP Int.
flag STMnPF
STMn
O/P Pin
STMnPF not
gene�ated
Output pin set to
initial Level Low
if STnOC=0
Output does
not �hange
Output Toggle with
STMnAF flag
He�e STnIO [1:0] = 11
Toggle Output sele�t
Output not affe�ted �y
STMnAF flag. Re�ains High
until �eset �y STnON �it
Note STnIO [1:0] = 10
A�tive High Output sele�t
Output Inve�ts
when STnPOL is high
Output Pin
Reset to Initial value
Output �ont�olled �y
othe� pin-sha�ed fun�tion
Compare Match Output Mode –STnCCLR=1
Note: 1. With STnCCLR=1 a Comparator A match will clear the counter
2. The STMn output pin is controlled only by the STMnAF flag
3. The output pin is reset to its initial state by a STnON bit rising edge
4. A STMnPF flag is not generated when STnCCLR=1
5. n=0 ~ 2
Rev. 1.00
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Timer/Counter Mode
To select this mode, bits STnM1 and STnM0 in the STMnC1 register should be set to 11
respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output
Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the
STMn output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the STMn output pin is not used in
this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits STnM1 and STnM0 in the STMnC1 register should be set to 10 respectively
and also the STnIO1 and STnIO0 bits should be set to 10 respectively. The PWM function within
the STMn is useful for applications which require functions such as motor control, heating control,
illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the
STMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the STnCCLR bit has no effect as the PWM
period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the other
one is used to control the duty cycle. Which register is used to control either frequency or duty cycle
is determined using the STnDPX bit in the STMnC1 register. The PWM waveform frequency and
duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The STnOC bit in the STMnC1 register is used
to select the required polarity of the PWM waveform while the two STnIO1 and STnIO0 bits are
used to enable the PWM output or to force the STMn output pin to a fixed high or low level. The
STnPOL bit is used to reverse the polarity of the PWM output waveform.
• 16-bit STMn, PWM Output Mode, Edge-aligned Mode, STnDPX=0
CCRP
1~255
0
Period
CCRP×256
65536
Duty
CCRA
If fSYS=16MHz, STMn clock source is fSYS/4, CCRP=2 and CCRA=128,
The STMn PWM output frequency=(fSYS/4)/(2×256)=fSYS/2048=8 kHz, duty=128/(2×256)= 25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
• 16-bit STMn, PWM Output Mode, Edge-aligned Mode, STnDPX=1
CCRP
1~255
Period
0
CCRA
CCRP×256
Duty
65536
The PWM output period is determined by the CCRA register value together with the TM clock
while the PWM duty cycle is defined by the CCRP register value except when the CCRP value is
equal to 0.
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
Counte� Value
STnDPX = 0; STnM [1:0] = 10
Counte� �lea�ed
�y CCRP
Counte� Reset when
STnON �etu�ns high
CCRP
Pause Resu�e
CCRA
Counte� Stop if
STnON �it low
Ti�e
STnON
STnPAU
STnPOL
CCRA Int.
flag STMnAF
CCRP Int.
flag STMnPF
STMn O/P Pin
(STnOC=1)
STMn O/P Pin
(STnOC=0)
PWM Duty Cy�le
set �y CCRA
PWM Pe�iod
set �y CCRP
PWM �esu�es
ope�ation
Output �ont�olled �y
Output Inve�ts
othe� pin-sha�ed fun�tion
when STnPOL = 1
PWM Output Mode – STnDXP=0
Note: 1. Here STnDPX=0 – Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when STnIO [1:0]=00 or 01
4. The STnCCLR bit has no influence on PWM operation
5. n=0 ~ 2
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
Counte� Value
STnDPX = 1; STnM [1:0] = 10
Counte� �lea�ed
�y CCRA
Counte� Reset when
STnON �etu�ns high
CCRA
Pause Resu�e
CCRP
Counte� Stop if
STnON �it low
Ti�e
STnON
STnPAU
STnPOL
CCRP Int.
flag STMnPF
CCRA Int.
flag STMnAF
STMn O/P
Pin (STnOC=1)
STMn O/P
Pin (STnOC=0)
PWM Duty Cy�le
set �y CCRP
PWM Pe�iod
set �y CCRA
PWM �esu�es
ope�ation
Output �ont�olled �y
Output Inve�ts
othe� pin-sha�ed fun�tion
when STnPOL = 1
PWM Output Mode – STnDXP=1
Note: 1. Here STnDPX=1 – Counter cleared by CCRA
2. A counter clear sets the PWM Period
3. The internal PWM function continues even when STnIO [1:0]=00 or 01
4. The STnCCLR bit has no influence on PWM operation
5. n=0 ~ 2
Rev. 1.00
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Single Pulse Output Mode
To select this mode, bits STnM1 and STnM0 in the STMnC1 register should be set to 10
respectively and also the STnIO1 and STnIO0 bits should be set to 11 respectively. The Single Pulse
Output Mode, as the name suggests, will generate a single shot pulse on the STMn output pin.
The trigger for the pulse output leading edge is a low to high transition of the STnON bit, which
can be implemented using the application program. However in the Single Pulse Mode, the STnON
bit can also be made to automatically change from low to high using the external STCKn pin,
which will in turn initiate the Single Pulse output. When the STnON bit transitions to a high level,
the counter will start running and the pulse leading edge will be generated. The STnON bit should
remain high when the pulse is in its active state. The generated pulse trailing edge will be generated
when the STnON bit is cleared to zero, which can be implemented using the application program or
when a compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the STnON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control
the pulse width. A compare match from Comparator A will also generate a STMn interrupt. The
counter can only be reset back to zero when the STnON bit changes from low to high when the
counter restarts. In the Single Pulse Mode CCRP is not used. The STnCCLR and STnDPX bits are
not used in this Mode.
S/W Co��and
SET ˝STnON˝
o�
STCKn Pin
T�ansition
CCRA
Leading Edge
CCRA
T�ailing Edge
STnON �it
0
1
STnON �it
1
0
S/W Co��and
CLR ˝STnON˝
o�
CCRA Co�pa�e
Mat�h
STPn Output Pin
Pulse Width = CCRA Value
Single Pulse Generation
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
Counte� Value
STnM [1:0] = 10 ; STnIO [1:0] = 11
Counte� stopped
�y CCRA
Counte� Reset when
STnON �etu�ns high
CCRA
Pause
Counte� Stops
�y softwa�e
Resu�e
CCRP
Ti�e
STnON
Softwa�e
T�igge�
Auto. set �y
STCKn pin
Clea�ed �y
CCRA �at�h
STCKn pin
Softwa�e
T�igge�
Softwa�e
T�igge�
Softwa�e
Softwa�e T�igge�
Clea�
STCKn pin
T�igge�
STnPAU
STnPOL
No CCRP Inte��upts
gene�ated
CCRP Int. Flag
STMnPF
CCRA Int. Flag
STMnAF
STMn O/P Pin
(STnOC=1)
STMn O/P Pin
(STnOC=0)
Output Inve�ts
when STnPOL = 1
Pulse Width
set �y CCRA
Single Pulse Output Mode
Note: 1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse triggered by the STCKn pin or by setting the STnON bit high
4. A STCKn pin active edge will automatically set the STnON bit high.
5. In the Single Pulse Mode, STnIO [1:0] must be set to "11" and can not be changed.
6. n=0 ~ 2
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
Capture Input Mode
To select this mode bits STnM1 and STnM0 in the STMnC1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal
is supplied on the STPnI pin, whose active edge can be a rising edge, a falling edge or both rising
and falling edges; the active edge transition type is selected using the STnIO1 and STnIO0 bits in
the STMnC1 register. The counter is started when the STnON bit changes from low to high which is
initiated using the application program.
When the required edge transition appears on the STPnI pin the present value in the counter will be
latched into the CCRA registers and a STMn interrupt generated. Irrespective of what events occur
on the STPnI pin the counter will continue to free run until the STnON bit changes from high to
low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP
value can be used to control the maximum counter value. When a CCRP compare match occurs from
Comparator P, a STMn interrupt will also be generated. Counting the number of overflow interrupt
signals from the CCRP can be a useful method in measuring long pulse widths. The STnIO1 and
STnIO0 bits can select the active trigger edge on the STPnI pin to be a rising edge, falling edge or
both edge types. If the STnIO1 and STnIO0 bits are both set high, then no capture operation will
take place irrespective of what happens on the STPnI pin, however it must be noted that the counter
will continue to run. The STnCCLR and STnDPX bits are not used in this Mode.
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
Counte� Value
STnM [1:0] = 01
Counte� �lea�ed
�y CCRP
Counte� Counte�
Stop
Reset
CCRP
YY
Pause
Resu�e
XX
Ti�e
STnON
STnPAU
A�tive
edge
A�tive
edge
A�tive edge
STMn �aptu�e
pin STPnI
CCRA Int.
Flag STMnAF
CCRP Int.
Flag STMnPF
CCRA
Value
STnIO [1:0]
Value
XX
00 – Rising edge
YY
01 – Falling edge
XX
10 – Both edges
YY
11 – Disa�le Captu�e
Capture Input Mode
Note: 1. STnM [1:0]=01 and active edge set by the STnIO [1:0] bits
2. A STMn Capture input pin active edge transfers the counter value to CCRA
3. STnCCLR bit not used
4. No output function -- STnOC and STnPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to
zero.
6. n=0 ~ 2
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Advanced A/D Flash MCU with EEPROM
Periodic Type TM – PTM
The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can
also be controlled with two external input pins and can drive two external output pin.
Device
PTM Core
PTM Input Pin
PTM Output Pin
HT66F2350
HT66F2360
HT66F2370
HT66F2390
10-bit PTM
(PTM0, PTM1)
PTCK0, PTP0I
PTCK1, PTP1I
PTP0
PTP1
16-bit PTM
(PTM2, PTM3)
PTCK2, PTP2I
PTCK3, PTP3I
PTP2
PTP3
CCRP
fSYS/4
fSYS
fH/16
fH/64
fSUB
fSUB
10-bit Comparator P
001
PTMnPF Interrupt
PTnOC
b0~b9
010
011
10-bit Count-up Counter
100
101
110
PTCKn
Comparator P Match
000
PTnON
PTnPAU
Counter Clear
PTnCCLR
b0~b9
111
PTnCK2~PTnCK0
10-bit Comparator A
Comparator A Match
PTnIO1, PTnIO0
CCRA
Output
Control
Polarity
Control
Pin
Control
PTnM1, PTnM0
PTnIO1, PTnIO0
PTnPOL
PxSn
0
1
Edge
Detector
PTPn
PTMnAF Interrupt
IFS
PTnCAPTS
Pin
Control
0
1
PTPnI
10-bit Periodic Type TM Block Diagram (n=0 or 1)
CCRP
fSYS/4
fSYS
fH/16
fH/64
fSUB
fSUB
16-bit Comparator P
001
PTMnPF Interrupt
PTnOC
b0~b15
010
011
16-bit Count-up Counter
100
101
110
PTCKn
Comparator P Match
000
PTnON
PTnPAU
Counter Clear
PTnCCLR
b0~b15
111
PTnCK2~PTnCK0
16-bit Comparator A
CCRA
Output
Control
Polarity
Control
Pin
Control
PTnM1, PTnM0
PTnIO1, PTnIO0
PTnPOL
PxSn
0
1
Comparator A Match
PTPn
PTMnAF Interrupt
IFS
PTnIO1, PTnIO0
PTnCAPTS
Edge
Detector
0
1
Pin
Control
PTPnI
16-bit Periodic Type TM Block Diagram (n=2 or 3)
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Periodic TM Operation
The size of Periodic TM is 10-/16-bit wide and its core is a 10-/16-bit count-up counter which is
driven by a user selectable internal or external clock source. There are also two internal comparators
with the names, Comparator A and Comparator P. These comparators will compare the value in the
counter with CCRP and CCRA registers. The CCRP and CCRA comparators are 10-/16-bit wide
whose value is respectively compared with all counter bits.
The only way of changing the value of the 10-/16-bit counter using the application program is to
clear the counter by changing the PTnON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a PTM interrupt signal will also usually be generated. The Periodic
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control the output pins. All operating setup conditions
are selected using relevant internal registers.
Periodic Type TM Register Description
Overall operation of the Periodic TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 10-/16-bit value, while two read/write register pairs exist
to store the internal 10-/16-bit CCRA and CCRP value. The remaining two registers are control
registers which setup the different operating and control modes.
Register
Name
Bit
7
6
54
4
3
2
1
0
PTMnC0
PTnPAU PTnCK2 PTnCK1 PTnCK0
PTnON
—
—
—
PTMnC1
PTnM1
PTnM0
PTnIO1
PTnIO0
PTnOC
PTMnDL
D7
D6
D5
D4
D3
D2
D1
D0
PTMnDH
—
—
—
—
—
—
D9
D8
PTMnAL
D7
D6
D5
D4
D3
D2
D1
D0
PTMnAH
—
—
—
—
—
—
PTnPOL PTnCAPTS PTnCCLR
D9
D8
PTMnRPL PTnRP7 PTnRP6 PTnRP5 PTnRP4 PTnRP3 PTnRP2
PTnRP1
PTnRP0
PTMnRPH
PTnRP9
PTnRP8
2
1
0
—
—
—
—
—
—
—
—
—
10-bit Periodic TM Registers List (n=0 or 1)
Register
Name
Bit
7
6
5
4
3
PTMnC0
PTnPAU PTnCK2 PTnCK1 PTnCK0
PTnON
PTMnC1
PTnM1
PTnOC
PTnM0
PTnIO1
PTnIO0
PTnPOL PTnCAPTS PTnCCLR
PTMnDL
D7
D6
D5
D4
D3
D2
D1
D0
PTMnDH
D15
D14
D13
D12
D11
D10
D9
D8
PTMnAL
D7
D6
D5
D4
D3
D2
D1
D0
PTMnAH
D15
D14
D13
D12
D11
D10
D9
D8
PTnRP7 PTnRP6 PTnRP5 PTnRP4 PTnRP3 PTnRP2
PTnRP1
PTnRP0
PTMnRPH PTnRP15 PTnRP14 PTnRP13 PTnRP12 PTnRP11 PTnRP10
PTnRP9
PTnRP8
PTMnRPL
16-bit Periodic TM Registers List (n=2 or 3)
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
PTMnDL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
PTMn Counter Low Byte Register bit 7 ~ bit 0
PTMn 10/16-bit Counter bit 7 ~ bit 0
PTMnDH Register (n=0 or 1)
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R
R
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1~0
PTMn Counter High Byte Register bit 1 ~ bit 0
PTMn 10-bit Counter bit 9 ~ bit 8
PTMnDH Register (n=2 or 3)
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
PTMn Counter High Byte Register bit 7 ~ bit 0
PTMn 16-bit Counter bit 15 ~ bit 8
PTMnAL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
PTMn CCRA Low Byte Register bit 7 ~ bit 0
PTMn 10/16-bit CCRA bit 7 ~ bit 0
PTMnAH Register (n=0 or 1)
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Bit 1~0
Unimplemented, read as "0"
PTMn CCRA High Byte Register bit 1 ~ bit 0
PTMn 10-bit CCRA bit 9 ~ bit 8
PTMnAH Register (n=2 or 3)
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
PTMn CCRA High Byte Register bit 7 ~ bit 0
PTMn 16-bit CCRA bit 15 ~ bit 8
132
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Advanced A/D Flash MCU with EEPROM
PTMnRPL Register
Bit
7
6
5
4
3
2
1
0
Name
PTnRP7
PTnRP6
PTnRP5
PTnRP4
PTnRP3
PTnRP2
PTnRP1
PTnRP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0PTnRP7~PTnRP0: PTMn CCRP Low Byte Register bit 7 ~ bit 0
PTMn 10/16-bit CCRP bit 7 ~ bit 0
PTMnRPH Register (n=0 or 1)
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
PTnRP9
PTnRP8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1~0PTnRP9~PTnRP8: PTMn CCRP High Byte Register bit 1 ~ bit 0
PTMn 10-bit CCRP bit 9 ~ bit 8
PTMnRPH Register (n=2 or 3)
Bit
Name
7
6
5
4
3
2
1
PTnRP15 PTnRP14 PTnRP13 PTnRP12 PTnRP11 PTnRP10 PTnRP9
0
PTnRP8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0PTnRP15~PTnRP8: PTMn CCRP High Byte Register bit 7 ~ bit 0
PTMn 16-bit CCRP bit 15 ~ bit 8
PTMnC0 Register
Bit
7
6
5
4
3
2
1
0
Name
PTnPAU
PTnCK2
PTnCK1
PTnCK0
PTnON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7PTnPAU: PTMn Counter Pause control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the PTMn will remain powered
up and continue to consume power. The counter will retain its residual value when
this bit changes from low to high and resume counting from this value when the bit
changes to a low value again.
Bit 6~4PTnCK2~PTnCK0: Select PTMn Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fSUB
101: fSUB
110: PTCKn rising edge clock
111: PTCKn falling edge clock
These three bits are used to select the clock source for the PTMn. The external pin
clock source can be chosen to be active on the rising or falling edge. The clock source
fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which
can be found in the oscillator section.
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Advanced A/D Flash MCU with EEPROM
Bit 3PTnON: PTMn Counter On/Off control
0: Off
1: On
This bit controls the overall on/off function of the PTMn. Setting the bit high enables
the counter to run while clearing the bit disables the PTMn. Clearing this bit to zero
will stop the counter from counting and turn off the PTMn which will reduce its power
consumption. When the bit changes state from low to high the internal counter value
will be reset to zero, however when the bit changes from high to low, the internal
counter will retain its residual value until the bit returns high again. If the PTMn is in
the Compare Match Output Mode then the PTMn output pin will be reset to its initial
condition, as specified by the PTnOC bit, when the PTnON bit changes from low to
high.
Bit 2~0
Unimplemented, read as "0"
PTMnC1 Register
Bit
7
6
5
4
3
2
1
0
Name
PTnM1
PTnM0
PTnIO1
PTnIO0
PTnOC
PTnPOL
PTnCAPTS
PTnCCLR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6PTnM1~PTnM0: Select PTMn Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the PTMn. To ensure reliable
operation the PTMn should be switched off before any changes are made to the
PTnM1 and PTnM0 bits. In the Timer/Counter Mode, the PTMn output pin control
will be disabled.
Bit 5~4PTnIO1~PTnIO0: Select PTMn external pin PTPn or PTPnI function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Output Mode/Single Pulse Output Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Single Pulse Output
Capture Input Mode
00: Input capture at rising edge of PTPnI or PTCKn
01: Input capture at falling edge of PTPnI or PTCKn
10: Input capture at rising/falling edge of PTPnI or PTCKn
11: Input capture disabled
Timer/Counter Mode
Unused
These two bits are used to determine how the PTMn output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the PTMn is running.
In the Compare Match Output Mode, the PTnIO1 and PTnIO0 bits determine how the
PTMn output pin changes state when a compare match occurs from the Comparator A.
The PTMn output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the PTMn
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
output pin should be setup using the PTnOC bit in the PTMnC1 register. Note that
the output level requested by the PTnIO1 and PTnIO0 bits must be different from the
initial value setup using the PTnOC bit otherwise no change will occur on the PTMn
output pin when a compare match occurs. After the PTMn output pin changes state,
it can be reset to its initial level by changing the level of the PTnON bit from low to
high.
In the PWM Output Mode, the PTnIO1 and PTnIO0 bits determine how the TM output
pin changes state when a certain compare match condition occurs. The PTMn output
function is modified by changing these two bits. It is necessary to only change the
values of the PTnIO1 and PTnIO0 bits only after the PTMn has been switched off.
Unpredictable PWM outputs will occur if the PTnIO1 and PTnIO0 bits are changed
when the PTMn is running.
Bit 3PTnOC: PTMn PTPn Output control
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Output Mode/Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the PTMn output pin. Its operation depends upon
whether PTMn is being used in the Compare Match Output Mode or in the PWM
Mode/Single Pulse Output Mode. It has no effect if the PTMn is in the Timer/Counter
Mode. In the Compare Match Output Mode it determines the logic level of the PTMn
output pin before a compare match occurs. In the PWM Mode/Single Pulse Output
Mode it determines if the PWM signal is active high or active low.
Bit 2PTnPOL: PTMn PTPn Output polarity control
0: Non-inverted
1: Inverted
This bit controls the polarity of the PTPn output pin. When the bit is set high the
PTMn output pin will be inverted and not inverted when the bit is zero. It has no effect
if the PTMn is in the Timer/Counter Mode.
Bit 1PTnCAPTS: PTMn Capture Trigger Source selection
0: From PTPnI pin
1: From PTCKn pin
Bit 0PTnCCLR: PTMn Counter Clear condition selection
0: Comparator P match
1: Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Periodic TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the PTnCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The PTnCCLR bit is not
used in the PWM Output, Single Pulse Output or Capture Input Mode.
Rev. 1.00
135
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Advanced A/D Flash MCU with EEPROM
Periodic Type TM Operation Modes
The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the PTnM1 and PTnM0 bits in the PTMnC1 register.
Compare Match Output Mode
To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register, should be set to 00
respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the PTnCCLR bit is low, there are two ways in which the counter can be
cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all
zero which allows the counter to overflow. Here both PTMnAF and PTMnPF interrupt request flags
for Comparator A and Comparator P respectively, will both be generated.
If the PTnCCLR bit in the PTMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the PTMnAF interrupt request flag will
be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore
when PTnCCLR is high no PTMnPF interrupt request flag will be generated. In the Compare Match
Output Mode, the CCRA can not be set to "0".
As the name of the mode suggests, after a comparison is made, the PTMn output pin will change
state. The PTMn output pin condition however only changes state when a PTMnAF interrupt request
flag is generated after a compare match occurs from Comparator A. The PTMnPF interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the PTMn
output pin. The way in which the PTMn output pin changes state are determined by the condition of
the PTnIO1 and PTnIO0 bits in the PTMnC1 register. The PTMn output pin can be selected using
the PTnIO1 and PTnIO0 bits to go high, to go low or to toggle from its present condition when a
compare match occurs from Comparator A. The initial condition of the PTMn output pin, which is
setup after the PTnON bit changes from low to high, is setup using the PTnOC bit. Note that if the
PTnIO1 and PTnIO0 bits are zero then no pin change will take place.
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
Counter Value
0x3FF/
0xFFFF
Counter overflow
CCRP=0
PTnCCLR = 0; PTnM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
Counter
Restart
Resume
CCRP
Pause
CCRA
Stop
Time
PTnON
PTnPAU
PTnPOL
CCRP Int. Flag
PTMnPF
CCRA Int. Flag
PTMnAF
PTMn
O/P Pin
Output pin set to
initial Level Low
if PTnOC=0
Output not affected by
PTMnAF flag. Remains High
until reset by PTnON bit
Output Toggle with
PTMnAF flag
Here PTnIO [1:0] = 11
Toggle Output select
Note PTnIO [1:0] = 10
Active High Output select
Output Inverts
when PTnPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – PTnCCLR=0
Note: 1. With PTnCCLR=0, a Comparator P match will clear the counter
2. The PTMn output pin is controlled only by the PTMnAF flag
3. The output pin is reset to its initial state by a PTnON bit rising edge
4. The 10-bit PTM maximum counter value is 0x3FF while the 16-bit PTM maximum counter value is
0xFFFF.
5. n=0 or 1 for 10-bit PTM while n=2 or 3 for 16-bit PTM
Rev. 1.00
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Advanced A/D Flash MCU with EEPROM
Counter Value
PTnCCLR = 1; PTnM [1:0] = 00
CCRA = 0
Counter overflow
CCRA > 0 Counter cleared by CCRA value
0x3FF/
0xFFFF
Resume
CCRA
Pause
CCRA=0
Stop
Counter Restart
CCRP
Time
PTnON
PTnPAU
PTnPOL
No PTMnAF flag
generated on
CCRA overflow
CCRA Int. Flag
PTMnAF
CCRP Int. Flag
PTMnPF
PTMn
O/P Pin
PTMPF not
generated
Output pin set to
initial Level Low
if PTnOC=0
Output does
not change
Output Toggle with
PTMnAF flag
Here PTnIO [1:0] = 11
Toggle Output select
Output not affected by PTMnAF
flag. Remains High until reset
by PTnON bit
Note PTnIO [1:0] = 10
Active High Output select
Output Inverts
when PTnPOL is
Output Pin
high
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – PTnCCLR=1
Note: 1. With PTnCCLR=1, a Comparator A match will clear the counter
2. The PTMn output pin is controlled only by the PTMnAF flag
3. The output pin is reset to its initial state by a PTnON bit rising edge
4. A PTMnPF flag is not generated when PTnCCLR =1
5. The 10-bit PTM maximum counter value is 0x3FF while the 16-bit PTM maximum counter value is
0xFFFF.
6. n=0 or 1 for 10-bit PTM while n=2 or 3 for 16-bit PTM
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Timer/Counter Mode
To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 11
respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output
Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the
PTMn output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the PTMn output pin is not used in
this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively
and also the PTnIO1 and PTnIO0 bits should be set to 10 respectively. The PWM function within
the PTMn is useful for applications which require functions such as motor control, heating control,
illumination control, etc. By providing a signal of fixed frequency but of varying duty cycle on the
PTMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the PTnCCLR bit has no effect as the PWM
period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the other
one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore
be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The PTnOC bit in the PTMnC1 register is used
to select the required polarity of the PWM waveform while the two PTnIO1 and PTnIO0 bits are
used to enable the PWM output or to force the PTMn output pin to a fixed high or low level. The
PTnPOL bit is used to reverse the polarity of the PWM output waveform.
• 16-bit PTMn, PWM Mode,
CCRP
1~65535
Period
1~65535
Duty
0
65536
CCRA
If fSYS=16MHz, TM clock source select fSYS/4, CCRP=512 and CCRA=128,
The PTMn PWM output frequency=(fSYS/4)/512=fSYS/2048=8kHz, duty=128/512=25%,
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
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Counter Value
PTnM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
PTnON returns high
CCRP
Pause Resume
CCRA
Counter Stop if
PTnON bit low
Time
PTnON
PTnPAU
PTnPOL
CCRA Int. Flag
PTMnAF
CCRP Int. Flag
PTMnPF
PTMn O/P Pin
(PTnOC=1)
PTMn O/P Pin
(PTnOC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
When PTnPOL = 1
PWM Output Mode
Note: 1. The counter is cleared by CCRP.
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when PTnIO [1:0]=00 or 01
4. The PTnCCLR bit has no influence on PWM operation
5. n=0 or 1 for 10-bit PTM while n=2 or 3 for 16-bit PTM
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Single Pulse Output Mode
To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10
respectively and also the PTnIO1 and PTnIO0 bits should be set to 11 respectively. The Single Pulse
Output Mode, as the name suggests, will generate a single shot pulse on the PTMn output pin.
The trigger for the pulse output leading edge is a low to high transition of the PTnON bit, which
can be implemented using the application program. However in the Single Pulse Mode, the PTnON
bit can also be made to automatically change from low to high using the external PTCKn pin,
which will in turn initiate the Single Pulse output. When the PTnON bit transitions to a high level,
the counter will start running and the pulse leading edge will be generated. The PTnON bit should
remain high when the pulse is in its active state. The generated pulse trailing edge will be generated
when the PTnON bit is cleared to zero, which can be implemented using the application program or
when a compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the PTnON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the
pulse width. A compare match from Comparator A will also generate a PTMn interrupt. The counter
can only be reset back to zero when the PTnON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The PTnCCLR is not used in this Mode.
S/W Command
SET“PTnON”
or
PTCKn Pin
Transition
CCRA
Leading Edge
CCRA
Trailing Edge
PTnON bit
0à1
PTnON bit
1à0
S/W Command
CLR“PTnON”
or
CCRA Compare
Match
PTPn Output Pin
Pulse Width = CCRA Value
Single Pulse Generation
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Counter Value
PTnM [1:0] = 10 ; PTnIO [1:0] = 11
Counter stopped
by CCRA
Counter Reset when
PTnON returns high
CCRA
Pause
Counter Stops
by software
Resume
CCRP
Time
PTnON
Software
Trigger
Auto. set by
PTCKn pin
Cleared by
CCRA match
PTCKn pin
Software
Trigger
Software
Trigger
Software
Clear
Software
Trigger
PTCKn pin
Trigger
PTnPAU
PTnPOL
No CCRP Interrupts
generated
CCRP Int. Flag
PTMnPF
CCRA Int. Flag
PTMnAF
PTMn O/P Pin
(PTnOC=1)
PTMn O/P Pin
(PTnOC=0)
Pulse Width
set by CCRA
Output Inverts
when PTnPOL = 1
Single Pulse Output Mode
Note: 1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse triggered by the PTCKn pin or by setting the PTnON bit high
4. A PTCKn pin active edge will automatically set the PTnON bit high.
5. In the Single Pulse Mode, PTnIO [1:0] must be set to "11" and can not be changed.
6. n=0 or 1 for 10-bit PTM while n=2 or 3 for 16-bit PTM
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Capture Input Mode
To select this mode bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal is
supplied on the PTPnI or PTCKn pin, selected by the PTnCAPTS bit in the PTMnC1 register. The
input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the
active edge transition type is selected using the PTnIO1 and PTnIO0 bits in the PTMnC1 register.
The counter is started when the PTnON bit changes from low to high which is initiated using the
application program.
When the required edge transition appears on the PTPnI or PTCKn pin the present value in the
counter will be latched into the CCRA registers and a PTMn interrupt generated. Irrespective of
what events occur on the PTPnI or PTCKn pin the counter will continue to free run until the PTnON
bit changes from high to low. When a CCRP compare match occurs the counter will reset back to
zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP
compare match occurs from Comparator P, a PTMn interrupt will also be generated. Counting the
number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse
widths. The PTnIO1 and PTnIO0 bits can select the active trigger edge on the PTPnI or PTCKn pin
to be a rising edge, falling edge or both edge types. If the PTnIO1 and PTnIO0 bits are both set high,
then no capture operation will take place irrespective of what happens on the PTPnI or PTCKn pin,
however it must be noted that the counter will continue to run.
As the PTPnI or PTCKn pin is pin shared with other functions, care must be taken if the PTMn is in
the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this
pin may cause an input capture operation to be executed. The PTnCCLR, PTnOC and PTnPOL bits
are not used in this Mode.
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Counter Value
PTnM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop
Reset
CCRP
YY
Pause
Resume
XX
Time
PTnON
PTnPAU
Active
edge
Active
edge
Active edge
PTMn capture pin
PTPnI or PTCKn
CCRA Int. Flag
PTMnAF
CCRP Int. Flag
PTMnPF
CCRA
Value
PTnIO [1:0]
Value
XX
00 – Rising edge
YY
01 – Falling edge
XX
10 – Both edges
YY
11 – Disable Capture
Capture Input Mode
Note: 1. PTnM [1:0]=01 and active edge set by the PTnIO [1:0] bits
2. A PTMn Capture input pin active edge transfers the counter value to CCRA
3. PTnCCLR bit not used
4. No output function – PTnOC and PTnPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to
zero.
6. n=0 or 1 for 10-bit PTM while n=2 or 3 for 16-bit PTM
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Analog to Digital Converter
The need to interface to real world analog signals is a common requirement for many electronic
systems. However, to properly process these signals by a microcontroller, they must first be
converted into digital signals by A/D converters. By integrating the A/D conversion electronic
circuitry into the microcontroller, the need for external components is reduced significantly with the
corresponding follow-on benefits of lower costs and reduced component space requirements.
A/D Overview
These devices contain a multi-channel analog to digital converter which can directly interface to
external analog signals, such as that from sensors or other control signals and convert these signals
directly into a 12-bit digital value. It also can convert the internal signals, such as the internal
reference voltage, into a 12-bit digital value. The external or internal analog signal to be converted is
determined by the SAINS and SACS bit fields. Note that when the internal analog signal is selected
to be converted using the SAINS field, the external channel analog input will automatically be
switched off. More detailed information about the A/D input signal selection will be described in the
"A/D Converter Input Signals" section.
The accompanying block diagram shows the internal structure of the A/D converter with temperature
sensor together with its associated registers and control bits.
Device
External Input
Channels
HT66F2350
AN0~AN11
HT66F2360
HT66F2370
HT66F2390
AN0~AN15
Internal Signal
A/D Signal Select
AVDD, AVDD/2, AVDD/4,
VR, VR/2, VR/4,
SAINS3~SAINS0
SACS3~SACS0
AVDD
fSYS
Pin-shared
Selection
SACS3~SACS0
SACKS2~
SACKS0
÷ 2N
(N=0~7)
ADCEN
AVSS
AN0
A/D Clock
AN1
SADOL
A/D Converter
AN11
ADRFS
SADOH
A/D Data
Registers
AN15
SAINS3~SAINS0
START
SAINS3~SAINS0
AVDD
AVDD/2
AVDD/4
ADCEN
A/D Converter
Reference Voltage
SAVRS1~SAVRS0
ADPGAEN
PGAIS
VR
VR/2
VR/4
AVSS
ADBZ
VBGREF
VREFI
Pin-shared
Selection
VRI
VREFI
PGA
VREF
VR
PGAS1~PGAS0
(Gain=1, 1.667, 2.5, 3.333)
AVDD
VREF
Pin-shared
Selection
Note: The external channel is from AN0 to AN11 for the HT66F2350 device.
A/D Converter Structure
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Registers Descriptions
Overall operation of the A/D converter is controlled using five registers. A read only register pair
exists to store the A/D Converter data 12-bit value. Three registers, SADC0, SADC1 and SADC2,
are the control registers which setup the operating conditions and control function of the A/D
converter.
Bit
Register
Name
7
6
5
4
3
2
1
0
SADOL
(ADRFS=0)
D3
D2
D1
D0
—
—
—
—
SADOL
(ADRFS=1)
D7
D6
D5
D4
D3
D2
D1
D0
SADOH
(ADRFS=0)
D11
D10
D9
D8
D7
D6
D5
D4
SADOH
(ADRFS=1)
—
—
—
—
D11
D10
D9
D8
SADC0
START
ADBZ
ADCEN
ADRFS
SACS3
SACS2
SACS1
SACS0
SADC1
SAINS3
SAINS2
SAINS1
SAINS0
—
SACKS2
SACKS1
SACKS0
SADC2
ADPGAEN
—
—
PGAIS
SAVRS1
SAVRS0
PGAGS1
PGAGS0
VBGRC
—
—
—
—
—
—
—
VBGREN
A/D Converter Registers List
A/D Converter Data Registers – SADOL, SADOH
As these devices contain an internal 12-bit A/D converter, it requires two data registers to store the
converted value. These are a high byte register, known as SADOH, and a low byte register, known
as SADOL. After the conversion process takes place, these registers can be directly read by the
microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space
is utilised, the format in which the data is stored is controlled by the ADRFS bit in the SADC0
register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits.
Any unused bits will be read as zero. The A/D data registers contents will be unchanged if the A/D
converter is disabled.
SADOH
ADRFS
SADOL
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A/D Converter Data Registers
A/D Converter Control Registers – SADC0, SADC1, SADC2
To control the function and operation of the A/D converter, three control registers known as SADC0,
SADC1 and SADC2 are provided. These 8-bit registers define functions such as the selection of
which analog signal is connected to the internal A/D converter, the digitised data format, the A/D
clock source as well as controlling the start function and monitoring the A/D converter busy status.
As these devices contain only one actual analog to digital converter hardware circuit, each of the
external and internal analog signals must be routed to the converter. The SAINS field in the SADC1
register and SACS field in the SADC0 register are used to determine which analog signal derived
from the external or internal signals will be connected to the A/D converter. The A/D converter also
contains a programmable gain amplifier, PGA, to generate the A/D converter internal reference
voltage. The overall operation of the PGA is controlled using the SADC2 register.
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The relevant pin-shared function selection bits determine which pins on I/O Ports are used as analog
inputs for the A/D converter input and which pins are not. When the pin is selected to be an A/D
input, its original function whether it is an I/O or other pin-shared function will be removed. In
addition, any internal pull-high resistor connected to the pin will be automatically removed if the pin
is selected to be an A/D converter input.
• SADC0 Register – HT66F2350
Bit
7
6
5
4
3
2
1
0
Name
START
ADBZ
ADCEN
ADRFS
SACS3
SACS2
SACS1
SACS0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7START: Start the A/D Conversion
0→1→0: Start
This bit is used to initiate an A/D conversion process. The bit is normally low but if set
high and then cleared low again, the A/D converter will initiate a conversion process.
Bit 6ADBZ: A/D Converter busy flag
0: No A/D conversion is in progress
1: A/D conversion is in progress
This read only flag is used to indicate whether the A/D conversion is in progress or
not. When the START bit is set from low to high and then to low again, the ADBZ flag
will be set to 1 to indicate that the A/D conversion is initiated. The ADBZ flag will be
cleared to 0 after the A/D conversion is complete.
Bit 5ADCEN: A/D Converter function enable control
0: Disable
1: Enable
This bit controls the A/D internal function. This bit should be set to one to enable
the A/D converter. If the bit is set low, then the A/D converter will be switched off
reducing the device power consumption. When the A/D converter function is disabled,
the contents of the A/D data register pair known as SADOH and SADOL will be
unchanged.
Bit 4ADRFS: A/D conversion data format select
0: A/D converter data format → SADOH=D [11:4]; SADOL=D [3:0]
1: A/D converter data format → SADOH=D [11:8]; SADOL=D [7:0]
This bit controls the format of the 12-bit converted A/D value in the two A/D data
registers. Details are provided in the A/D converter data register section.
Bit 3~0SACS3~SACS0: A/D converter external analog input channel select
0000: External AN0 input
0001: External AN1 input
0010: External AN2 input
0011: External AN3 input
0100: External AN4 input
0101: External AN5 input
0110: External AN6 input
0111: External AN7 input
1000: External AN8 input
1001: External AN9 input
1010: External AN10 input
1011: External AN11 input
11xx: Undefined, input floating.
These bits are used to select which external analog input channel is to be converted.
When the external analog input channel is selected, the SAINS bit field must set to
"0000", "0100" or "11xx". Details are summarized in the "A/D Converter Input Signal
Selection" table.
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• SADC0 Register – HT66F2360/HT66F2370/HT66F2390
Bit
7
6
5
4
3
2
1
0
Name
START
ADBZ
ADCEN
ADRFS
SACS3
SACS2
SACS1
SACS0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7START: Start the A/D Conversion
0→1→0: Start
This bit is used to initiate an A/D conversion process. The bit is normally low but if set
high and then cleared low again, the A/D converter will initiate a conversion process.
Bit 6ADBZ: A/D Converter busy flag
0: No A/D conversion is in progress
1: A/D conversion is in progress
This read only flag is used to indicate whether the A/D conversion is in progress or
not. When the START bit is set from low to high and then to low again, the ADBZ flag
will be set to 1 to indicate that the A/D conversion is initiated. The ADBZ flag will be
cleared to 0 after the A/D conversion is complete.
Bit 5ADCEN: A/D Converter function enable control
0: Disable
1: Enable
This bit controls the A/D internal function. This bit should be set to one to enable
the A/D converter. If the bit is set low, then the A/D converter will be switched off
reducing the device power consumption. When the A/D converter function is disabled,
the contents of the A/D data register pair known as SADOH and SADOL will be
unchanged.
Bit 4ADRFS: A/D conversion data format select
0: A/D converter data format → SADOH=D [11:4]; SADOL=D [3:0]
1: A/D converter data format → SADOH=D [11:8]; SADOL=D [7:0]
This bit controls the format of the 12-bit converted A/D value in the two A/D data
registers. Details are provided in the A/D converter data register section.
Bit 3~0SACS3~SACS0: A/D converter external analog input channel select
0000: External AN0 input
0001: External AN1 input
0010: External AN2 input
0011: External AN3 input
0100: External AN4 input
0101: External AN5 input
0110: External AN6 input
0111: External AN7 input
1000: External AN8 input
1001: External AN9 input
1010: External AN10 input
1011: External AN11 input
1100: External AN12 input
1101: External AN13 input
1110: External AN14 input
1111: External AN15 input
These bits are used to select which external analog input channel is to be converted.
When the external analog input channel is selected, the SAINS bit field must set to
"0000", "0100" or "11xx". Details are summarized in the "A/D Converter Input Signal
Selection" table.
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• SADC1 Register
Bit
7
6
5
4
3
2
1
0
Name
SAINS3
SAINS2
SAINS1
SAINS0
—
SACKS2
SACKS1
SACKS0
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
POR
0
0
0
0
—
0
0
0
Bit 7~4SAINS3~SAINS0: A/D converter input signal select
0000: External source – External analog channel intput, ANn
0001: Internal source – Internal signal derived from AVDD
0010: Internal source – Internal signal derived from AVDD/2
0011: Internal source – Internal signal derived from AVDD/4
0100: External source – External analog channel intput, ANn
0101: Internal source – Internal signal derived from PGA output VR
0110: Internal source – Internal signal derived from PGA output VR/2
0111: Internal source – Internal signal derived from PGA output VR/4
10xx: Internal source – Ground.
11xx: External source – External analog channel intput, ANn
When the internal analog signal is selected to be converted, the external channel signal
input will automatically be switched off regardless of the SACS field value. It will
prevent the external channel input from being connected together with the internal
analog signal.
Bit 3
Unimplemented, read as "0"
Bit 2~0SACKS2~SACKS0: A/D conversion clock source select
000: fSYS
001: fSYS/2
010: fSYS/4
011: fSYS/8
100: fSYS/16
101: fSYS/32
110: fSYS/64
111: fSYS/128
These bits are used to select the clock source for the A/D converter. It is recommended
that the A/D conversion clock frequency should be in the range from 500 kHz to
1MHz by properly configuring the SACKS2~SACKS0 bits.
• SADC2 Register
Bit
7
6
5
4
3
2
Name
ADPGAEN
—
—
PGAIS
SAVRS1
SAVRS0
1
0
R/W
R/W
—
—
R/W
R/W
R/W
R/W
R/W
POR
0
—
—
0
0
0
0
0
PGAGS1 PGAGS0
Bit 7ADPGAEN: PGA enable control
0: Disable
1: Enable
Bit 6~5
Unimplemented, read as "0"
Bit 4PGAIS: PGA input voltage selection
0: From VREFI pin
1: From internal reference voltage VBGREF
Bit 3~2SAVRS1~SAVRS0: A/D converter reference voltage select
00: Internal A/D converter power, AVDD.
01: External VREF pin
1x: Internal PGA output voltage, VR.
These bits are used to select the A/D converter reference voltage source. When the
internal reference voltage source is selected, the reference voltage derived from the
external VREF pin will automatically be switched off.
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Advanced A/D Flash MCU with EEPROM
Bit 1~0PGAGS1~PGAGS0: PGA gain select
00: Gain=1
01: Gain=1.667 – VR=2V as VRI=1.2V
10: Gain=2.5 – VR=3V as VRI=1.2V
11: Gain=3.333 – VR=4V as VRI=1.2V
These bits are used to select the PGA gain. Note that here the gain is guaranteed only
when the PGA input voltage is equal to 1.2V.
• VBGRC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
VBGREN
R/W
—
—
—
—
—
—
—
R/W
POR
—
—
—
—
—
—
—
0
Bit 7~1
Unimplemented, read as "0"
Bit 0VBGREN: Bandgap reference voltage control
0: Disable
1: Enable
This bit is used to enable the internal Bandgap reference circuit. The internal Bandgap
reference circuit should first be enabled before the VBGREF voltage is selected to be
used. A specific start-up time is necessary for the Bandgap circuit to become stable and
accurate.
A/D Converter Reference Voltage
The actual reference voltage supply to the A/D Converter can be supplied from the positive power
supply pin, AVDD, an external reference source supplied on pin VREF or an internal reference
voltage VR determined by the SAVRS1~SAVRS0 bits in the SADC2 register. The internal reference
voltage is amplified through a programmable gain amplifier, PGA, which is controlled by the
ADPGAEN bit in the SADC2 register. The PGA gain can be equal to 1, 1.667, 2.5 or 3.333 and
selected using the PGAGS1~PGAGS0 bits in the SADC2 register. The PGA input can come from the
external reference input pin, VREFI, or an internal Bandgap reference voltage, VBGREF, selected by
the PGAIS bit in the SADC2 register. As the VREFI and VREF pin both are pin-shared with other
functions, when the VREFI or VREF pin is selected as the reference voltage pin, the VREFI or VREF
pin-shared function selection bits should first be properly configured to disable other pin-shared
functions. However, if the internal reference signal is selected as the reference source, the external
reference input from the VREFI or VREF pin will automatically be switched off by hardware.
Note that the internal Bandgap reference circuit should first be enabled before the VBGREF is selected
to be used. A specific start-up time is necessary for the Bandgap circuit to become stable and
accurate.
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A/D Converter Input Signals
All of the external A/D analog input pins are pin-shared with the I/O pins as well as other functions.
The corresponding pin-shared function selection bits in the PxS1 and PxS0 registers, determine
whether the external input pins are setup as A/D converter analog channel inputs or whether they
have other functions. If the corresponding pin is setup to be an A/D converter analog channel input,
the original pin function will be disabled. In this way, pins can be changed under program control
to change their function between A/D inputs and other functions. All pull-high resistors, which are
setup through register programming, will be automatically disconnected if the pins are setup as A/D
inputs. Note that it is not necessary to first setup the A/D pin as an input in the port control register
to enable the A/D input as when the relevant A/D input function selection bits enable an A/D input,
the status of the port control register will be overridden.
As these devices contain only one actual analog to digital converter hardware circuit, each of the
external and internal analog signals must be routed to the converter. The SAINS3~SAINS0 bits in
the SADC1 register are used to determine that the analog signal to be converted comes from the
external channel input or internal analog signal. The SACS3~SACS0 bits in the SADC0 register are
used to determine which external channel input is selected to be converted. If the SAINS3~SAINS0
bits are set to "0000", the external channel input will be selected to be converted and the
SACS3~SACS0 bits can determine which external channel is selected.
When the SAINS field is set to the value of "0x01", "0x10" or "0x11", the internal analog signal will
be selected. If the internal analog signal is selected to be converted, the external channel signal input
will automatically be switched off regardless of the SACS field value. It will prevent the external
channel input from being connected together with the internal analog signal.
SAINS [3:0]
SACS [3:0]
Input Signals
0000,
0100, 11xx
0000~1011
AN0~AN11
Description
11xx
—
0001
xxxx
AVDD
0010
xxxx
AVDD/2
Internal signal derived from AVDD/2
0011
xxxx
AVDD/4
Internal signal derived from AVDD/4
0101
xxxx
VR
0110
xxxx
VR/2
Internal signal derived from PGA output VR/2
0111
xxxx
VR/4
Internal signal derived from PGA output VR/4
10xx
xxxx
GND
Connected to the ground.
External channel analog input ANn.
Floating, no external channel is selected.
Internal signal derived from AVDD
Internal signal derived from PGA output VR
A/D Converter Input Signal Selection – HT66F2350
SAINS [3:0]
SACS [3:0]
Input Signals
0000,
0100, 11xx
Description
0000~1111
AN0~AN15
0001
xxxx
AVDD
0010
xxxx
AVDD/2
Internal signal derived from AVDD/2
0011
xxxx
AVDD/4
Internal signal derived from AVDD/4
0101
xxxx
VR
0110
xxxx
VR/2
Internal signal derived from PGA output VR/2
0111
xxxx
VR/4
Internal signal derived from PGA output VR/4
10xx
xxxx
GND
Connected to the ground.
External channel analog input ANn
Internal signal derived from AVDD
Internal signal derived from PGA output VR
A/D Converter Input Signal Selection – HT66F2360/HT66F2370/HT66F2390
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A/D Operation
The START bit in the SADC0 register is used to start the AD conversion. When the microcontroller
sets this bit from low to high and then low again, an analog to digital conversion cycle will be
initiated.
The ADBZ bit in the SADC0 register is used to indicate whether the analog to digital conversion
process is in progress or not. This bit will be automatically set to 1 by the microcontroller after an
A/D conversion is successfully initiated. When the A/D conversion is complete, the ADBZ bit will
be cleared to 0. In addition, the corresponding A/D interrupt request flag will be set in the interrupt
control register, and if the interrupts are enabled, an internal interrupt signal will be generated. This
A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt
address for processing. If the A/D internal interrupt is disabled, the microcontroller can poll the
ADBZ bit in the SADC0 register to check whether it has been cleared as an alternative method of
detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen
to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the
SACKS2~SACKS0 bits in the SADC1 register. Although the A/D clock source is determined by the
system clock fSYS and by bits SACKS2~SACKS0, there are some limitations on the maximum A/D
clock source speed that can be selected. As the recommended range of permissible A/D clock period,
tADCK, is from 0.5μs to 10μ, care must be taken for system clock frequencies. For example, if the
system clock operates at a frequency of 8MHz, the SACKS2~SACKS0 bits should not be set to 000,
001 or 111. Doing so will give A/D clock periods that are less than the minimum A/D clock period
which may result in inaccurate A/D conversion values. Refer to the following table for examples,
where values marked with an asterisk * show where, depending upon the device, special care must
be taken, as the values may be less than the specified minimum A/D Clock Period.
However, the recommended A/D clock period is from 1μs to 2μ if the input signal to be converted is
the temperature sensor output voltage.
A/D Clock Period (tADCK)
fSYS
SACKS
[2:0]=000
(fSYS)
SACKS
[2:0]=001
(fSYS/2)
SACKS
[2:0]=010
(fSYS/4)
SACKS
[2:0]=011
(fSYS/8)
SACKS
[2:0]=100
(fSYS/16)
SACKS
[2:0]=101
(fSYS/32)
SACKS
[2:0]=110
(fSYS/64)
SACKS
[2:0]=111
(fSYS/128)
1 MHz
1μs
2μs
4μs
8μs
16μs *
32μs *
64μs *
128μs *
2 MHz
500ns
1μs
2μs
4μs
8μs
16μs *
32μs *
64μs *
4 MHz
250ns *
500ns
1μs
2μs
4μs
8μs
16μs *
32μs *
8 MHz
125ns *
250ns *
500ns
1μs
2μs
4μs
8μs
16μs *
12 MHz
83ns *
167ns *
333ns *
667ns
1.33μs
2.67μs
5.33μs
10.67μs *
16 MHz
62.5ns *
125ns *
250ns *
500ns
1μs
2μs
4μs
8μs
A/D Clock Period Examples
Controlling the power on/off function of the A/D converter circuitry is implemented using the
ADCEN bit in the SADC0 register. This bit must be set high to power on the A/D converter. When
the ADCEN bit is set high to power on the A/D converter internal circuitry a certain delay, as
indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if
no pins are selected for use as A/D inputs, if the ADCEN bit is high, then some power will still be
consumed. In power conscious applications it is therefore recommended that the ADCEN is set low
to reduce power consumption when the A/D converter function is not being used.
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Conversion Rate and Timing Diagram
A complete A/D conversion contains two parts, data sampling and data conversion. The data
sampling which is defined as tADS takes 4 A/D clock cycles and the data conversion takes 12 A/D
clock cycles. Therefore a total of 16 A/D clock cycles for an analog signal A/D conversion which is
defined as tADC are necessary.
Maximum single A/D conversion rate=A/D clock period / 16
The accompanying diagram shows graphically the various stages involved in an external channel
input signal analog to digital conversion process and its associated timing. After an A/D conversion
process has been initiated by the application program, the microcontroller internal hardware will
begin to carry out the conversion, during which time the program can continue with other functions.
The time taken for the A/D conversion is 16 tADCK clock cycles where tADCK is equal to the A/D clock
period.
tON2ST
ADCEN
off
on
off
A/D sampling time
tADS
A/D sampling time
tADS
Start of A/D conversion
Start of A/D conversion
on
START
ADBZ
SACS[3:0]
(SAINS=000)
End of A/D
conversion
0011B
A/D channel
switch
End of A/D
conversion
0010B
tADC
A/D conversion time
Start of A/D conversion
0000B
tADC
A/D conversion time
0001B
tADC
A/D conversion time
A/D Conversion Timing
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Summary of A/D Conversion Steps
The following summarises the individual steps that should be executed in order to implement an A/D
conversion process.
• Step 1
Select the required A/D conversion clock by properly programming the SACKS2~SACKS0 bits
in the SADC1 register.
• Step 2
Enable the A/D converter by setting the ADCEN bit in the SADC0 register to one.
• Step 3
Select which signal is to be connected to the internal A/D converter by correctly configuring the
SACS and SAINS bit fields
Selecting the external channel input to be converted, go to Step 4.
Selecting the internal analog signal to be converted, go to Step 5.
• Step 4
If the SAINS field is 0000, 0100 or 11xx, the external channel input can be selected. The desired
external channel input is selected by configuring the SACS field. When the A/D input signal
comes from the external channel input, the corresponding pin should be configured as an A/D
input function by selecting the relevant pin-shared function control bits. Then go to Step 6.
• Step 5
If the SAINS field is set to 0x01, 0x10 or 0x11, the relevant internal analog signal will be
selected. When the internal analog signal is selected to be converted, the external channel analog
input will automatically be disconnected. Then go to Step 6.
• Step 6
Select the A/D converter output data format by configuring the ADRFS bit.
• Step 7
Select the A/D converter reference voltage source by configuring the SAVRS bit field.
Select the PGA input signal and the desired PGA gain if the PGA output voltage, VR, is selected
as the A/D converter reference voltage.
• Step 8
If A/D conversion interrupt is used, the interrupt control registers must be correctly configured
to ensure the A/D interrupt function is active. The master interrupt control bit, EMI, and the A/D
conversion interrupt control bit, ADE, must both be set high in advance.
• Step 9
The A/D conversion procedure can now be initialized by setting the START bit from low to high
and then low again.
• Step 10
If A/D conversion is in progress, the ADBZ flag will be set high. After the A/D conversion
process is complete, the ADBZ flag will go low and then the output data can be read from
SADOH and SADOL registers.
Note: When checking for the end of the conversion process, if the method of polling the ADBZ bit
in the SADC0 register is used, the interrupt enable step above can be omitted.
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Advanced A/D Flash MCU with EEPROM
Programming Considerations
During microcontroller operations where the A/D converter is not being used, the A/D internal
circuitry can be switched off to reduce power consumption, by setting bit ADCEN low in the
SADC0 register. When this happens, the internal A/D converter circuits will not consume power
irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are
used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then
this may lead to some increase in power consumption.
A/D Transfer Function
As the devices contain a 12-bit A/D converter, its full-scale converted digitised value is equal to
FFFH. Since the full-scale analog input value is equal to the actual A/D converter reference voltage,
VREF, this gives a single bit analog input value of reference voltage value divided by 4096.
1 LSB=VREF ÷ 4096
The A/D Converter input voltage value can be calculated using the following equation:
A/D input voltage=A/D output digital value × VREF ÷ 4096
The diagram shows the ideal transfer function between the analog input value and the digitised
output value for the A/D converter. Except for the digitised zero value, the subsequent digitised
values will change at a point 0.5 LSB below where they would change without the offset, and the
last full scale digitised value will change at a point 1.5 LSB below the VREF level.
Note that here the VREF voltage is the actual A/D converter reference voltage determined by the
SAVRS field.
1.5 LSB
FFFH
FFEH
FFDH
A/D Conversion
Result
03H
0.5 LSB
0�H
01H
0
1
�
3
4093 4094 4095 409�
VREF
409�
Analog Input Voltage
Ideal A/D Transfer Function
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Advanced A/D Flash MCU with EEPROM
A/D Programming Examples
The following two programming examples illustrate how to setup and implement an A/D conversion.
In the first example, the method of polling the ADBZ bit in the SADC0 register is used to detect
when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to
determine when the conversion is complete.
Example: using an ADBZ polling method to detect the end of conversion
clr ADE; disable ADC interrupt
mov a,03H; select fSYS/8 as A/D clock and A/D input
mov SADC1,a ; signal comes from external channel
mov a,00H ; select AVDD as the A/D reference voltage source
mov SADC2,a
set ADCEN
mov a,03H ; setup PCS0 to configure pin AN0
mov PCS0,a
mov a,00H ; select AN0 as the A/D external channel input
mov SADC0,a
:
start_conversion:
clr START ; high pulse on start bit to initiate conversion
set START ; reset A/D
clr START ; start A/D
:
polling_EOC:
sz ADBZ ; poll the SADC0 register ADBZ bit to detect end of A/D conversion
jmp polling_EOC ; continue polling
:
mov a,SADOL ; read low byte conversion result value
mov SADOL_buffer,a ; save result to user defined register
mov a,SADOH ; read high byte conversion result value
mov SADOH_buffer,a ; save result to user defined register
:
jmp start_conversion ; start next A/D conversion
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Example: using the interrupt method to detect the end of conversion
clr ADE; disable ADC interrupt
mov a,03H; select fSYS/8 as A/D clock and A/D input
mov SADC1,a ; signal comes from external channel
mov a,00H ; select AVDD as the A/D reference voltage source
mov SADC2,a
set ADCEN
mov a,03h ; setup PCS0 to configure pin AN0
mov PCS0,a
mov a,00h
mov SADC0,a ; select AN0 as the A/D external channel input
:
Start_conversion:
clr START ; high pulse on START bit to initiate conversion
set START ; reset A/D
clr START ; start A/D
clr ADF ; clear ADC interrupt request flag
set ADE; enable ADC interrupt
set EMI ; enable global interrupt
:
:
ADC_ISR: ; ADC interrupt service routine
mov acc_stack,a ; save ACC to user defined memory
mov a,STATUS
mov status_stack,a ; save STATUS to user defined memory
:
mov a,SADOL ; read low byte conversion result value
mov SADOL_buffer,a ; save result to user defined register
mov a,SADOH ; read high byte conversion result value
mov SADOH_buffer,a ; save result to user defined register
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a ; restore STATUS from user defined memory
mov a,acc_stack ; restore ACC from user defined memory
reti
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Advanced A/D Flash MCU with EEPROM
Serial Interface Module – SIM
These devices contain a Serial Interface Module, which includes both the four-line SPI interface or
two-line I2C interface types, to allow an easy method of communication with external peripheral
hardware. Having relatively simple communication protocols, these serial interface types allow
the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or
EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins and therefore the
SIM interface functional pins must first be selected using the corresponding pin-shared function
selection bits. As both interface types share the same pins and registers, the choice of whether the
SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in
the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O pins are selected using pullhigh control registers when the SIM function is enabled and the corresponding pins are used as SIM
input pins.
SPI Interface
The SPI interface is often used to communicate with external peripheral devices such as sensors,
Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI
interface is a synchronous serial data interface that has a relatively simple communication protocol
simplifying the programming requirements when communicating with external hardware devices.
The communication is full duplex and operates as a slave/master type, where the devices can be
either master or slave. Although the SPI interface specification can control multiple slave devices
from a single master, these devices provided only one SCS pin. If the master needs to control
multiple slave devices from a single master, the master can use I/O pin to select the slave devices.
SPI Interface Operation
The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin
names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data
Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins
are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface pins must first
be selected by configuring the pin-shared function selection bits and setting the correct bits in the
SIMC0 and SIMC2 registers. After the desired SPI configuration has been set it can be disabled or
enabled using the SIMEN bit in the SIMC0 register. Communication between devices connected
to the SPI interface is carried out in a slave/master mode with all data transfer initiations being
implemented by the master. The Master also controls the clock signal. As the device only contains
a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set
CSEN bit to 1 to enable SCS pin function, set CSEN bit to 0 the SCS pin will be floating state.
The SPI function in this device offers the following features:
• Full duplex synchronous data transfer
• Both Master and Slave modes
• LSB first or MSB first data transmission modes
• Transmission complete flag
• Rising or falling active clock edge
The status of the SPI interface pins is determined by a number of factors such as whether the device
is in the master or slave mode and upon the condition of certain control bits such as CSEN and
SIMEN.
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SPI Maste�
SPI Slave
SCK
SCK
SDO
SDI
SDI
SDO
SCS
SCS
SPI Master/Slave Connection
Data Bus
SIMD
SDI Pin
TX/RX Shift Registe�
SDO Pin
Clo�k
Edge/Pola�ity
Cont�ol
CKEG �it
CKPOLB �it
WCOL Flag
TRF Flag
ICF Flag
Busy Status
SCK Pin
Clo�k
Sou��e
Sele�t
fSYS
fSUB
PTM0 CCRP �at�h f�equen�y/�
SCS Pin
CSEN �it
SPI Block Diagram
SPI Registers
There are three internal registers which control the overall operation of the SPI interface. These are
the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only
used by the I2C interface.
Bit
Register
Name
7
6
5
4
SIMC0
SIM2
SIM1
SIM0
—
SIMC2
D7
D6
CKPOLB
CKEG
MLS
SIMD
D7
D6
D5
D4
D3
3
2
1
0
SIMEN
SIMICF
CSEN
WCOL
TRF
D2
D1
D0
SIMDEB1 SIMDEB0
SPI Registers List
• SIMD Register
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to
be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the
device can read it from the SIMD register. Any transmission or reception of data from the SPI bus
must be made via the SIMD register.
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
"x": unknown
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There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2
register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used
by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable
function and to set the data transmission clock frequency. Register SIMC2 is used for other control
functions such as LSB/MSB selection, write collision flag, etc.
• SIMC0 Register
Bit
7
6
5
4
Name
SIM2
SIM1
SIM0
—
3
R/W
R/W
R/W
R/W
—
R/W
POR
1
1
1
—
0
2
1
0
SIMEN
SIMICF
R/W
R/W
R/W
0
0
0
SIMDEB1 SIMDEB0
Bit 7~5SIM2~SIM0: SIM Operating Mode Control
000: SPI master mode; SPI clock is fSYS /4
001: SPI master mode; SPI clock is fSYS /16
010: SPI master mode; SPI clock is fSYS /64
011: SPI master mode; SPI clock is fSUB
100: SPI master mode; SPI clock is PTM0 CCRP match frequency/2
101: SPI slave mode
110: I2C slave mode
111: Non SIM function
These bits setup the overall operating mode of the SIM function. As well as selecting
if the I2C or SPI function, they are used to control the SPI Master/Slave selection and
the SPI Master clock frequency. The SPI clock is a function of the system clock but
can also be chosen to be sourced from PTM0. If the SPI Slave Mode is selected then
the clock will be supplied by an external Master device.
Bit 4
Unimplemented, read as "0"
Bit 3~2SIMDEB1~SIMDEB0: I2C Debounce Time Selection
The SIMDEB1~SIMDEB0 bits are only used in the I 2C mode and the detailed
definition is described in the I2C section.
Bit 1SIMEN: SIM Enable Control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is
cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and
SCL lines will lose their SPI or I2C function and the SIM operating current will be
reduced to a minimum value. When the bit is high the SIM interface is enabled. The
SIM configuration option must have first enabled the SIM interface for this bit to be
effective. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0
bits, the contents of the SPI control registers will remain at the previous settings when
the SIMEN bit changes from low to high and should therefore be first initialised by
the application program. If the SIM is configured to operate as an I2C interface via the
SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C
control bits such as HTX and TXAK will remain at the previous settings and should
therefore be first initialised by the application program while the relevant I2C flags
such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states.
Bit 0SIMICF: SIM SPI slave mode Incomplete Transfer Flag
0: SIM SPI slave mode incomplete condition not occurred
1: SIM SPI slave mode incomplete condition occurred
This bit is only available when the SIM is configured to operate in an SPI slave mode.
If the SPI operates in the slave mode with the SIMEN and CSEN bits both being set
to 1 but the SCS line is pulled high by the external master device before the SPI data
transfer is completely finished, the SIMICF bit will be set to 1 together with the TRF
bit. When this condition occurs, the corresponding interrupt will occur if the interrupt
function is enabled. However, the TRF bit will not be set to 1 if the SIMICF bit is set
to 1 by software application program.
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• SIMC2 Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
CKPOLB
CKEG
MLS
CSEN
WCOL
TRF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Undefined bits
These bits can be read or written by the application program.
Bit 5CKPOLB: SPI clock line base condition selection
0: The SCK line will be high when the clock is inactive.
1: The SCK line will be low when the clock is inactive.
The CKPOLB bit determines the base condition of the clock line, if the bit is high,
then the SCK line will be low when the clock is inactive. When the CKPOLB bit is
low, then the SCK line will be high when the clock is inactive.
Bit 4CKEG: SPI SCK clock active edge type selection
CKPOLB=0
0: SCK is high base level and data capture at SCK rising edge
1: SCK is high base level and data capture at SCK falling edge
CKPOLB=1
0: SCK is low base level and data capture at SCK falling edge
1: SCK is low base level and data capture at SCK rising edge
The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs
and inputs data on the SPI bus. These two bits must be configured before data transfer
is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit
determines the base condition of the clock line, if the bit is high, then the SCK line
will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK
line will be high when the clock is inactive. The CKEG bit determines active clock
edge type which depends upon the condition of CKPOLB bit.
Bit 3MLS: SPI data shift order
0: LSB first
1: MSB first
This is the data shift select bit and is used to select how the data is transferred, either
MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.
Bit 2CSEN: SPI SCS pin control
0: Disable
1: Enable
The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the
SCS pin will be disabled and placed into I/O pin or other pin-shared functions. If the
bit is high, the SCS pin will be enabled and used as a select pin.
Bit 1WCOL: SPI write collision flag
0: No collision
1: Collision
The WCOL flag is used to detect whether a data collision has occurred or not. If this
bit is high, it means that data has been attempted to be written to the SIMD register
during a data transfer operation. This writing operation will be ignored if data is being
transferred. This bit can be cleared by the application program.
Bit 0TRF: SPI Transmit/Receive complete flag
0: SPI data is being transferred
1: SPI data transfer is completed
The TRF bit is the Transmit/Receive Complete flag and is set to 1 automatically when
an SPI data transfer is completed, but must cleared to 0 by the application program. It
can be used to generate an interrupt.
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SPI Communication
After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when
data is written to the SIMD register, transmission/reception will begin simultaneously. When the
data transfer is complete, the TRF flag will be set automatically, but must be cleared using the
application program. In the Slave Mode, when the clock signal from the master has been received,
any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into
the SIMD register. The master should output a SCS signal to enable the slave devices before a
clock signal is provided. The slave data to be transferred should be well prepared at the appropriate
moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG
bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal
for various configurations of the CKPOLB and CKEG bits.
The SPI will continue to function even in the IDLE Mode.
SIMEN=1� CSEN=0 (Exte�nal Pull-high)
SCS
SIMEN� CSEN=1
SCK (CKPOLB=1� CKEG=0)
SCK (CKPOLB=0� CKEG=0)
SCK (CKPOLB=1� CKEG=1)
SCK (CKPOLB=0� CKEG=1)
SDO (CKEG=0)
D7/D0
D�/D1
D5/D�
D4/D3
D3/D4 D�/D5
D1/D�
D0/D7
SDO (CKEG=1)
D7/D0
D�/D1
D5/D�
D4/D3
D3/D4 D�/D5
D1/D�
D0/D7
SDI Data Captu�e
W�ite to SIMD
SPI Master Mode Timing
SCS
SCK (CKPOLB=1)
SCK (CKPOLB=0)
SDO
D7/D0
D�/D1
D5/D�
D4/D3
D3/D4 D�/D5
D1/D�
D0/D7
SDI Data Captu�e
W�ite to SIMD
(SDO does not �hange until fi�st SCK edge)
SPI Slave Mode Timing – CKEG=0
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SCS
SCK (CKPOLB=1)
SCK (CKPOLB=0)
SDO
D7/D0
D�/D1
D5/D�
D4/D3
D3/D4 D�/D5
D1/D�
D0/D7
SDI Data Captu�e
W�ite to SIMD
(SDO �hanges as soon as w�iting o��u�s; SDO is floating if SCS=1)
Note: Fo� SPI slave �ode� if SIMEN=1 and CSEN=0� SPI is always ena�led
and igno�es the SCS level.
SPI Slave Mode Timing – CKEG=1
SPI T�ansfe�
Maste�
A
Slave
Maste� o� Slave
?
W�ite Data
into SIMD
Clea� WCOL
Y
SIM[�:0]=000� 001�
010� 011 o� 100
WCOL=1?
SIM[�:0]=101
N
N
Configu�e CKPOLB�
CKEG� CSEN and MLS
T�ans�ission
�o�pleted?
(TRF=1?)
Y
SIMEN=1
Read Data
f�o� SIMD
A
Clea� TRF
T�ansfe�
finished?
N
Y
END
SPI Transfer Control Flow Chart
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I2C Interface
The I 2C interface is used to communicate with external peripheral devices such as sensors,
EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface
for synchronous serial data transfer. The advantage of only two lines for communication, relatively
simple communication protocol and the ability to accommodate multiple devices on the same bus
has made it an extremely popular interface type for many applications.
VDD
SDA
SCL
Devi�e
Slave
Devi�e
Maste�
Devi�e
Slave
I2C Master/Slave Bus Connection
I2C interface Operation
The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As
many devices may be connected together on the same bus, their outputs are both open drain types.
For this reason it is necessary that external pull-high resistors are connected to these outputs. Note
that no chip select line exists, as each device on the I2C bus is identified by a unique address which
will be transmitted and received on the I2C bus.
When two devices communicate with each other on the bidirectional I2C bus, one is known as the
master device and one as the slave device. Both master and slave can transmit and receive data;
however, it is the master device that has overall control of the bus. For these devices, which only
operate in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit
mode and the slave receive mode.
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„ I2C Block Diagram
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Advanced A/D Flash MCU with EEPROM
S T A R T s ig n a l
fro m M a s te r
S e n d s la v e a d d r e s s
a n d R /W b it fr o m M a s te r
A c k n o w le d g e
fr o m s la v e
S e n d d a ta b y te
fro m M a s te r
A c k n o w le d g e
fr o m s la v e
S T O P s ig n a l
fro m M a s te r
The SIMDEB1 and SIMDEB0 bits determine the debounce time of the I2C interface. This uses
the system clock to in effect add a debounce time to the external clock to reduce the possibility
of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be
chosen to be either 2 or 4 system clocks. To achieve the required I2C data transfer speed, there
exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C
Standard or Fast mode operation, users must take care of the selected system clock frequency and
the configured debounce time to match the criterion shown in the following table.
I2C Debounce Time Selection
I2C Standard Mode (100kHz)
I2C Fast Mode (400kHz)
No Debounce
fSYS > 2 MHz
fSYS > 5 MHz
2 system clock debounce
fSYS > 4 MHz
fSYS > 10 MHz
4 system clock debounce
fSYS > 8 MHz
fSYS > 20 MHz
I2C Minimum fSYS Frequency
I2C Registers
There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SIMA, and one
data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store
the data being transmitted and received on the I2C bus. Before the microcontroller writes data to
the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is
received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission
or reception of data from the I2C bus must be made via the SIMD register.
Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN
and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface.
Bit
Register
Name
7
6
5
4
SIMC0
SIM2
SIM1
SIM0
—
SIMC1
HCF
HAAS
HBB
HTX
TXAK
SIMA
IICA6
IICA5
IICA4
IICA3
IICA2
SIMD
D7
D6
D5
D4
D3
D2
3
2
1
0
SIMEN
SIMICF
SRW
IAMWU
RXAK
IICA1
IICA0
—
D1
D0
SIMDEB1 SIMDEB0
SIMTOC SIMTOEN SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0
I2C Registers List
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• SIMD Register
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I2C functions. Before the device writes data to the I2C bus, the actual data to
be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the
device can read it from the SIMD register. Any transmission or reception of data from the I2C bus
must be made via the SIMD register.
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
"x": unknown
• SIMA Register
The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is
the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register
define the device slave address. Bit 0 is not implemented.
When a master device, which is connected to the I2C bus, sends out an address, which matches the
slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is
the same register address as SIMC2 which is used by the SPI interface.
Bit
7
6
5
4
3
2
1
0
Name
IICA6
IICA5
IICA4
IICA3
IICA2
IICA1
IICA0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
POR
x
x
x
x
x
x
x
—
"x": unknown
Bit 7~1IICA6~IICA0: I C slave address
IICA6~IICA0 is the I2C slave address bit 6 ~ bit 0
2
Bit 0
Unimplemented, read as "0"
There are also two control registers for the I2C interface, SIMC0 and SIMC1. The register SIMC0
is used to control the enable/disable function and to set the data transmission clock frequency. The
SIMC1 register contains the relevant flags which are used to indicate the I2C communication status.
• SIMC0 Register
Bit
7
6
5
4
Name
SIM2
SIM1
SIM0
—
3
R/W
R/W
R/W
R/W
—
R/W
POR
1
1
1
—
0
2
1
0
SIMEN
SIMICF
R/W
R/W
R/W
0
0
0
SIMDEB1 SIMDEB0
Bit 7~5SIM2~SIM0: SIM Operating Mode Control
000: SPI master mode; SPI clock is fSYS /4
001: SPI master mode; SPI clock is fSYS /16
010: SPI master mode; SPI clock is fSYS /64
011: SPI master mode; SPI clock is fSUB
100: SPI master mode; SPI clock is PTM0 CCRP match frequency/2
101: SPI slave mode
110: I2C slave mode
111: Non SIM function
These bits setup the overall operating mode of the SIM function. As well as selecting
if the I2C or SPI function, they are used to control the SPI Master/Slave selection and
the SPI Master clock frequency. The SPI clock is a function of the system clock but
can also be chosen to be sourced from PTM0. If the SPI Slave Mode is selected then
the clock will be supplied by an external Master device.
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Bit 4
Unimplemented, read as "0"
Bit 3~2SIMDEB1~SIMDEB0: I2C Debounce Time Selection
00: No debounce
01: 2 system clock debounce
1x: 4 system clock debounce
These bits are used to select the I2C debounce time when the SIM is configured as the
I2C interface function by setting the SIM2~SIM0 bits to "110".
Bit 1SIMEN: SIM Enable Control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is
cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and
SCL lines will lose their SPI or I2C function and the SIM operating current will be
reduced to a minimum value. When the bit is high the SIM interface is enabled. The
SIM configuration option must have first enabled the SIM interface for this bit to be
effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0
bits, the contents of the SPI control registers will remain at the previous settings when
the SIMEN bit changes from low to high and should therefore be first initialised by
the application program. If the SIM is configured to operate as an I2C interface via the
SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C
control bits such as HTX and TXAK will remain at the previous settings and should
therefore be first initialised by the application program while the relevant I2C flags
such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states.
Bit 0SIMICF: SIM SPI Incomplete Flag
The SIMICF bit is only used in the SPI mode and the detailed definition is described
in the SPI section.
• SIMC1 Register
Bit
7
6
5
4
3
2
1
0
Name
HCF
HAAS
HBB
HTX
TXAK
SRW
IAMWU
RXAK
R/W
R
R
R
R/W
R/W
R/W
R/W
R
POR
1
0
0
0
0
0
0
1
Bit 7HCF: I C Bus data transfer completion flag
0: Data is being transferred
1: Completion of an 8-bit data transfer
The HCF flag is the data transfer flag. This flag will be zero when data is being
transferred. Upon completion of an 8-bit data transfer the flag will go high and an
interrupt will be generated.
2
Bit 6HAAS: I2C Bus data transfer completion flag
0: Not address match
1: Address match
The HAAS flag is the address match flag. This flag is used to determine if the slave
device address is the same as the master transmit address. If the addresses match then
this bit will be high, if there is no match then the flag will be low.
Bit 5HBB: I2C Bus busy flag
0: I2C Bus is not busy
1: I2C Bus is busy
The HBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which
will occur when a START signal is detected. The flag will be set to "0" when the bus is
free which will occur when a STOP signal is detected.
Bit 4HTX: I2C slave device transmitter/receiver selection
0: Slave device is the receiver
1: Slave device is the transmitter
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Bit 3TXAK: I2C bus transmit acknowledge flag
0: Slave send acknowledge flag
1: Slave does not send acknowledge flag
The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits
of data, this bit will be transmitted to the bus on the 9th clock from the slave device.
The slave device must always set TXAK bit to "0" before further data is received.
Bit 2SRW: I2C slave read/write flag
0: Slave device should be in receive mode
1: Slave device should be in transmit mode
The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether
the master device wishes to transmit or receive data from the I2C bus. When the
transmitted address and slave address is match, that is when the HAAS flag is set high,
the slave device will check the SRW flag to determine whether it should be in transmit
mode or receive mode. If the SRW flag is high, the master is requesting to read data
from the bus, so the slave device should be in transmit mode. When the SRW flag
is zero, the master will write data to the bus, therefore the slave device should be in
receive mode to read this data.
Bit 1IAMWU: I2C Address Match Wake-Up control
0: Disable
1: Enable – must be cleared by the application program after wake-up
This bit should be set to 1 to enable the I2C address match wake up from the SLEEP
or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or
IDLE mode to enable the I2C address match wake up, then this bit must be cleared by
the application program after wake-up to ensure correction device operation.
Bit 0RXAK: I2C bus receive acknowledge flag
0: Slave receives acknowledge flag
1: Slave does not receive acknowledge flag
The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it
means that a acknowledge signal has been received at the 9th clock, after 8 bits of data
have been transmitted. When the slave device in the transmit mode, the slave device
checks the RXAK flag to determine if the master receiver wishes to receive the next
byte. The slave transmitter will therefore continue sending out data until the RXAK
flag is "1". When this occurs, the slave transmitter will release the SDA line to allow
the master to send a STOP signal to release the I2C Bus.
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I2C Bus Communication
Communication on the I2C bus requires four separate steps, a START signal, a slave device address
transmission, a data transmission and finally a STOP signal. When a START signal is placed on
the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of
data on the bus. The first seven bits of the data will be the slave address with the first bit being the
MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the
SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service
routine, the slave device must first check the condition of the HAAS and SIMTOF bits to determine
whether the interrupt source originates from an address match, 8-bit data transfer completion or
I2C bus time-out occurrence. During a data transfer, note that after the 7-bit slave address has been
transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in
the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or
receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise
the bus; the following are steps to achieve this:
• Step 1
Set the SIM2~SIM0 bits to "110" and SIMEN bit to "1" in the SIMC0 register to enable the I2C
bus.
• Step 2
Write the slave address of the device to the I2C bus address register SIMA.
• Step 3
Set the SIME and SIM Multi-Function interrupt enable bit of the interrupt control register to
enable the SIM interrupt and Multi-function interrupt.
Sta�t
Set SIM[�:0]=110
Set SIMEN
W�ite Slave
Add�ess to SIMA
No
Yes
I�C Bus
Inte��upt=?
CLR SIME
Poll SIMF to de�ide when
to go to I�C Bus ISR
SET SIME and MFnE
Wait fo� Inte��upt
Goto Main P�og�a�
Goto Main P�og�a�
I2C Bus Initialisation Flow Chart
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I2C Bus Start Signal
The START signal can only be generated by the master device connected to the I2C bus and not by
the slave device. This START signal will be detected by all devices connected to the I2C bus. When
detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START
condition occurs when a high to low transition on the SDA line takes place when the SCL line
remains high.
I2C Slave Address
The transmission of a START signal by the master will be detected by all devices on the I2C bus.
To determine which slave device the master wishes to communicate with, the address of the slave
device will be sent out immediately following the START signal. All slave devices, after receiving
this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by
the master matches the internal address of the microcontroller slave device, then an internal I2C bus
interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the
read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then
transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the
status flag HAAS when the addresses match.
As an I2C bus interrupt can come from three sources, when the program enters the interrupt
subroutine, the HAAS and SIMTOF bits should be examined to see whether the interrupt source has
come from a matching slave address, the completion of a data byte transfer or the I2C bus time-out
occurrence. When a slave address is matched, the devices must be placed in either the transmit mode
and then write data to the SIMD register, or in the receive mode where it must implement a dummy
read from the SIMD register to release the SCL line.
I2C Bus Read/Write Signal
The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the
I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to
be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes
to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as
a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I2C
bus, therefore the slave device must be setup to read data from the I2C bus as a receiver.
I2C Bus Slave Address Acknowledge Signal
After the master has transmitted a calling address, any slave device on the I 2C bus, whose
own internal address matches the calling address, must generate an acknowledge signal. The
acknowledge signal will inform the master that a slave device has accepted its calling address. If no
acknowledge signal is received by the master then a STOP signal must be transmitted by the master
to end the communication. When the HAAS flag is high, the addresses have matched and the slave
device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag
is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register
should be set to "1". If the SRW flag is low, then the microcontroller slave device should be setup as
a receiver and the HTX bit in the SIMC1 register should be set to "0".
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I2C Bus Data and Acknowledge Signal
The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged
receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last.
After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before
it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal
from the master receiver, then the slave transmitter will release the SDA line to allow the master
to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD
register. If setup as a transmitter, the slave device must first write the data to be transmitted into the
SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD
register.
When the slave receiver receives the data byte, it must generate an acknowledge bit, known as
TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit
in the SIMC1 register to determine if it is to send another data byte, if not then it will release the
SDA line and await the receipt of a STOP signal from the master.
SCL
Slave Add�ess
Sta�t
1
0
1
SDA
1
0
1
SRW
ACK
1
0
0
Data
SCL
1
0
0
1
0
ACK
1
0
Stop
0
SDA
S=Sta�t (1 �it)
SA=Slave Add�ess (7 �its)
SR=SRW �it (1 �it)
M=Slave devi�e send a�knowledge �it (1 �it)
D=Data (8 �its)
A=ACK (RXAK �it fo� t�ans�itte�� TXAK �it fo� �e�eive�� 1 �it)
P=Stop (1 �it)
S
SA SR M
D
A
D
A
……
S
SA SR M
D
A
D
A
……
P
Note: *When a slave address is matched, the device must be placed in either the transmit mode
and then write data to the SIMD register, or in the receive mode where it must implement a
dummy read from the SIMD register to release the SCL line.
I2C Communication Timing Diagram
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Sta�t
No
No
No
HTX=1?
Yes
HAAS=1?
Yes
SIMTOF=1?
Yes
Yes
SET SIMTOEN
CLR SIMTOF
SRW=1?
No
RETI
Read f�o� SIMD to
�elease SCL Line
RETI
Yes
SET HTX
CLR HTX
CLR TXAK
W�ite data to SIMD to
�elease SCL Line
Du��y �ead f�o� SIMD
to �elease SCL Line
RETI
RETI
RXAK=1?
No
CLR HTX
CLR TXAK
W�ite data to SIMD to
�elease SCL Line
Du��y �ead f�o� SIMD
to �elease SCL Line
RETI
RETI
I2C Bus ISR Flow Chart
I2C Time-out Control
In order to reduce the I2C lockup problem due to reception of erroneous clock sources, a time-out
function is provided. If the clock source connected to the I2C bus is not received for a while, then the
I2C circuitry and registers will be reset after a certain time-out period. The time-out counter starts
to count on an I2C bus "START" & "address match" condition, and is cleared by an SCL falling
edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out period
specified by the SIMTOC register, then a time-out condition will occur. The time-out function will
stop when an I2C "STOP" condition occurs.
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SCL
Sta�t
Slave Add�ess
1
SDA
0
1
1
0
1
SRW
ACK
1
0
0
I�C ti�e-out
�ounte� sta�t
Stop
SCL
1
0
0
1
0
1
0
0
SDA
I�C ti�e-out �ounte� �eset
on SCL negative t�ansition
I2C Time-out
When an I2C time-out counter overflow occurs, the counter will stop and the SIMTOEN bit will
be cleared to zero and the SIMTOF bit will be set high to indicate that a time-out condition has
occurred. The time-out condition will also generate an interrupt which uses the I2C interrupt vector.
When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset
into the following condition:
Register
After I2C Time-out
SIMD, SIMA, SIMC0
No change
SIMC1
Reset to POR condition
I2C Register after Time-out
The SIMTOF flag can be cleared by the application program. There are 64 time-out period selections
which can be selected using the SIMTOS bits in the SIMTOC register. The time-out duration is
calculated by the formula: ((1~64) × (32/fSUB)). This gives a time-out period which ranges from
about 1ms to 64ms.
• SIMTOC Register
Bit
7
6
5
4
3
2
1
0
Name
SIMTOEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0
Bit 7SIMTOEN: SIM I C Time-out control
0: Disable
1: Enable
2
Bit 6SIMTOF: SIM I2C Time-out flag
0: No time-out occurred
1: Time-out occurred
Bit 5~0SIMTOS5~SIMTOS0: SIM I2C Time-out period selection
I2C Time-out clock source is fSUB/32
I2C Time-out period is equal to SIMTOS5 : 0  1
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Serial Interface – SPIA
These devices contain an independent SPI function. It is important not to confuse this independent
SPI function with the additional one contained within the combined SIM function, which is
described in another section of this datasheet. This independent SPI function will carry the name
SPIA to distinguish it from the other one in the SIM.
This SPIA interface is often used to communicate with external peripheral devices such as sensors,
Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI
interface is a synchronous serial data interface that has a relatively simple communication protocol
simplifying the programming requirements when communicating with external hardware devices.
The communication is full duplex and operates as a slave/master type, where the device can be
either master or slave. Although the SPIA interface specification can control multiple slave devices
from a single master, this device is provided only one SCSA pin. If the master needs to control
multiple slave devices from a single master, the master can use I/O pins to select the slave devices.
SPIA Interface Operation
The SPIA interface is a full duplex synchronous serial data link. It is a four line interface with pin
names SDIA, SDOA, SCKA and SCSA. Pins SDIA and SDOA are the Serial Data Input and Serial
Data Output lines, SCKA is the Serial Clock line and SCSA is the Slave Select line. As the SPIA
interface pins are pin-shared with other functions, the SPIA interface pins must first be selected
by configuring the corresponding selection bits in the pin-shared function selection registers.
The SPIA interface function is disabled or enabled using the SPIAEN bit in the SPIAC0 register.
Communication between devices connected to the SPIA interface is carried out in a slave/master
mode with all data transfer initiations being implemented by the master. The master also controls the
clock/signal. As the device only contains a single SCSA pin only one slave device can be utilised.
The SCSA pin is controlled by the application program, set the SACSEN bit to "1" to enable the
SCSA pin function and clear the SACSEN bit to "0" to place the SCSA pin into an I/O function.
SPIA Maste�
SPIA Slave
SCKA
SCKA
SDOA
SDIA
SDIA
SDOA
SCSA
SCSA
SPIA Master/Slave Connection
The SPIA Serial Interface function includes the following features:
• Full-duplex synchronous data transfer
• Both Master and Slave mode
• LSB first or MSB first data transmission modes
• Transmission complete flag
• Rising or falling active clock edge
The status of the SPIA interface pins is determined by a number of factors such as whether the
device is in the master or slave mode and upon the condition of certain control bits such as SACSEN
and SPIAEN.
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Data Bus
SPIAD
SDIA Pin
TX/RX Shift Registe�
Clo�k
Edge/Pola�ity
Cont�ol
SACKEG
SACKPOLB
SAWCOL Flag
SATRF Flag
SPIAICF Flag
Busy
Status
SCKA Pin
Clo�k
Sou��e
Sele�t
fSYS
fSUB
PTM0 CCRP �at�h f�equen�y/�
SCSA Pin
SDOA Pin
SACSEN
SPIA Block Diagram
SPIA Registers
There are three internal registers which control the overall operation of the SPIA interface. These are
the SPIAD data register and two registers SPIAC0 and SPIAC1.
Bit
Register
Name
7
6
5
4
3
2
1
0
SPIAC0
SASPI2
SASPI1
SASPI0
—
—
—
SPIAEN
SPIAICF
SPIAC1
—
—
SPIAD
D7
D6
SACKPOLB SACKEG
D5
D4
SAMLS
D3
SACSEN SAWCOL
D2
D1
SATRF
D0
SPIA Registers List
SPIAD Register
The SPIAD register is used to store the data being transmitted and received. Before the device
writes data to the SPIA bus, the actual data to be transmitted must be placed in the SPIAD register.
After the data is received from the SPIA bus, the device can read it from the SPIAD register. Any
transmission or reception of data from the SPIA bus must be made via the SPIAD register.
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
"x": unknown
There are also two control registers for the SPIA interface, SPIAC0 and SPIAC1. Register SPIAC0
is used to control the enable/disable function and to set the data transmission clock frequency.
Register SPIAC1 is used for other control functions such as LSB/MSB selection, write collision
flag, etc.
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SPIAC0 Register
Bit
7
6
5
4
3
2
1
0
Name
SASPI2
SASPI1
SASPI0
—
—
—
SPIAEN
SPIAICF
R/W
R/W
R/W
R/W
—
—
—
R/W
R/W
POR
1
1
1
—
—
—
0
0
Bit 7~5SASPI2~SASPI0: SPIA Master/Slave clock select
000: SPIA master mode with clock fSYS /4
001: SPIA master mode with clock fSYS /16
010: SPIA master mode with clock fSYS /64
011: SPIA master mode with clock fSUB
100: SPIA master mode with clock PTM0 CCRP match frequency/2
101: SPIA slave mode
11x: SPIA disable
Bit 4~2
Unimplemented, read as "0"
Bit 1SPIAEN: SPIA Enable Control
0: Disable
1: Enable
The bit is the overall on/off control for the SPIA interface. When the SPIAEN bit
is cleared to zero to disable the SPIA interface, the SDIA, SDOA, SCKA and SCSA
lines will lose the SPI function and the SPIA operating current will be reduced to a
minimum value. When the bit is high the SPIA interface is enabled.
Bit 0SPIAICF: SPIA Incomplete Flag
0: SPIA incomplete condition not occurred
1: SPIA incomplete condition occurred
This bit is only available when the SPIA is configured to operate in an SPIA slave
mode. If the SPIA operates in the slave mode with the SPIAEN and SACSEN bits
both being set to 1 but the SCSA line is pulled high by the external master device
before the SPIA data transfer is completely finished, the SPIAICF bit will be set to 1
together with the SATRF bit. When this condition occurs, the corresponding interrupt
will occur if the interrupt function is enabled. However, the SATRF bit will not be set
to 1 if the SPIAICF bit is set to 1 by software application program.
SPIAC1 Register
Bit
7
6
Name
—
—
5
4
SACKPOLB SACKEG
3
SAMLS
2
1
SACSEN SAWCOL
0
SATRF
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Unimplemented, read as "0"
Bit 5SACKPOLB: SPIA clock line base condition selection
0: The SCKA line will be high when the clock is inactive.
1: The SCKA line will be low when the clock is inactive.
The SACKPOLB bit determines the base condition of the clock line, if the bit is high,
then the SCKA line will be low when the clock is inactive. When the SACKPOLB bit
is low, then the SCKA line will be high when the clock is inactive.
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Bit 4SACKEG: SPIA SCKA clock active edge type selection
SACKPOLB=0
0: SCKA is high base level and data capture at SCKA rising edge
1: SCKA is high base level and data capture at SCKA falling edge
SACKPOLB=1
0: SCKA is low base level and data capture at SCKA falling edge
1: SCKA is low base level and data capture at SCKA rising edge
The SACKEG and SACKPOLB bits are used to setup the way that the clock signal
outputs and inputs data on the SPIA bus. These two bits must be configured before
data transfer is executed otherwise an erroneous clock edge may be generated. The
SACKPOLB bit determines the base condition of the clock line, if the bit is high, then
the SCKA line will be low when the clock is inactive. When the SACKPOLB bit is
low, then the SCKA line will be high when the clock is inactive. The SACKEG bit
determines active clock edge type which depends upon the condition of SACKPOLB
bit.
Bit 3SAMLS: SPIA data shift order
0: LSB first
1: MSB first
This is the data shift select bit and is used to select how the data is transferred, either
MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.
Bit 2SACSEN: SPIA SCSA pin control
0: Disable
1: Enable
The SACSEN bit is used as an enable/disable for the SCSA pin. If this bit is low, then
the SCSA pin function will be disabled and can be placed into I/O pin or other pinshared functions. If the bit is high, the SCSA pin will be enabled and used as a select
pin.
Bit 1SAWCOL: SPIA write collision flag
0: No collision
1: Collision
The SAWCOL flag is used to detect whether a data collision has occurred or not.
If this bit is high, it means that data has been attempted to be written to the SPIAD
register during a data transfer operation. This writing operation will be ignored if data
is being transferred. This bit can be cleared by the application program.
Bit 0SATRF: SPIA Transmit/Receive complete flag
0: SPIA data is being transferred
1: SPIA data transfer is completed
The SATRF bit is the Transmit/Receive Complete flag and is set to 1 automatically
when an SPIA data transfer is completed, but must cleared to 0 by the application
program. It can be used to generate an interrupt.
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SPIA Communication
After the SPIA interface is enabled by setting the SPIAEN bit high, then in the Master Mode, when
data is written to the SPIAD register, transmission/reception will begin simultaneously. When the
data transfer is complete, the SATRF flag will be set automatically, but must be cleared using the
application program. In the Slave Mode, when the clock signal from the master has been received,
any data in the SPIAD register will be transmitted and any data on the SDIA pin will be shifted into
the SPIAD registers.
The master should output a SCSA signal to enable the slave device before a clock signal is provided.
The slave data to be transferred should be well prepared at the appropriate moment relative to the
SCSA signal depending upon the configurations of the SACKPOLB bit and SACKEG bit. The
accompanying timing diagram shows the relationship between the slave data and SCSA signal for
various configurations of the SACKPOLB and SACKEG bits. The SPIA will continue to function if
the SPIA clock source is active.
SPIAEN=1� SACSEN=0 (Exte�nal Pull-high)
SCSA
SPIAEN� SACSEN=1
SCKA (SACKPOLB=1� SACKEG=0)
SCKA (SACKPOLB=0� SACKEG=0)
SCKA (SACKPOLB=1� SACKEG=1)
SCKA (SACKPOLB=0� SACKEG=1)
SDOA (SACKEG=0)
D7/D0
D�/D1
D5/D�
D4/D3
D3/D4 D�/D5
D1/D�
D0/D7
SDOA (SACKEG=1)
D7/D0
D�/D1
D5/D�
D4/D3
D3/D4 D�/D5
D1/D�
D0/D7
SDIA Data Captu�e
W�ite to SPIAD
SPIA Master Mode Timing
SCSA
SCKA (SACKPOLB=1)
SCKA (SACKPOLB=0)
SDOA
D7/D0
D�/D1
D5/D�
D4/D3
D3/D4 D�/D5
D1/D�
D0/D7
SDIA Data Captu�e
W�ite to SPIAD
(SDOA does not �hange until fi�st SCKA edge)
SPIA Master Mode Timing – SACKEG=0
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SCSA
SCKA (SACKPOLB=1)
SCKA (SACKPOLB=0)
SDOA
D7/D0
D�/D1
D5/D�
D4/D3
D3/D4 D�/D5
D1/D�
D0/D7
SDIA Data Captu�e
W�ite to SPIAD
(SDOA �hanges as soon as w�iting o��u�s; SDOA is floating if SCSA=1)
Note: Fo� SPIA slave �ode� if SPIAEN=1 and SACSEN=0� SPIA is always
ena�led and igno�es the SCSA level.
SPIA Master Mode Timing – SACKEG=1
SPIA T�ansfe�
Maste�
Maste� o� Slave
?
A
Slave
W�ite Data
into SPIAD
Clea� SAWCOL
Y
SASPI[�:0]=000�
001� 010� 011 o� 100
SAWCOL=1?
SASPIA[�:0]=101
N
N
Configu�e SACKPOLB�
SACKEG� SACSEN and SAMLS
T�ans�ission
�o�pleted?
(SATRF=1?)
Y
SPIAEN=1
Read Data
f�o� SPIAD
A
Clea� SATRF
T�ansfe�
finished?
N
Y
END
SPIA Transfer Control Flow Chart
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SPIA Bus Enable/Disable
To enable the SPIA bus, set SACSEN=1 and SCSA=0, then wait for data to be written into the
SPIAD (TXRX buffer) register. For the Master Mode, after data has been written to the SPIAD
(TXRX buffer) register, then transmission or reception will start automatically. When all the data has
been transferred the SATRF bit should be set. For the Slave Mode, when clock pulses are received
on SCKA, data in the TXRX buffer will be shifted out or data on SDIA will be shifted in.
When the SPIA bus is disabled, the SCKA, SDIA, SDOA and SCSA pins can become I/O pins or
other pin-shared functions using the corresponding pin-shared function selection bits.
SPIA Operation
All communication is carried out using the 4-line interface for either Master or Slave Mode.
The SACSEN bit in the SPIAC1 register controls the overall function of the SPIA interface. Setting
this bit high will enable the SPIA interface by allowing the SCSA line to be active, which can then
be used to control the SPIA interface. If the SACSEN bit is low, the SPIA interface will be disabled
and the SCSA line will be an I/O pin or other pin-shared functions and can therefore not be used for
control of the SPIA interface. If the SACSEN bit and the SPIAEN bit in the SPIAC0 register are
set high, this will place the SDIA line in a floating condition and the SDOA line high. If in Master
Mode the SCKA line will be either high or low depending upon the clock polarity selection bit
SACKPOLB in the SPIAC1 register. If in Slave Mode the SCKA line will be in a floating condition.
If SPIAEN is low, then the bus will be disabled and SCSA, SDIA, SDOA and SCKA pins will all
become I/O pins or other pin-shared functions using the corresponding pin-shared function selection
bits. In the Master Mode the Master will always generate the clock signal. The clock and data
transmission will be initiated after data has been written into the SPIAD register. In the Slave Mode,
the clock signal will be received from an external master device for both data transmission and
reception. The following sequences show the order to be followed for data transfer in both Master
and Slave Mode.
Master Mode
• Step 1
Select the clock source and Master mode using the SASPI2~SASPI0 bits in the SPIAC0 control
register.
• Step 2
Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB shifted
first, this must be same as the Slave device.
• Step 3
Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface.
• Step 4
For write operations: write the data to the SPIAD register, which will actually place the data into
the TXRX buffer. Then use the SCKA and SCSA lines to output the data. After this go to step 5.
For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer
until all the data has been received at which point it will be latched into the SPIAD register.
• Step 5
Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal
to zero then go to the following step.
• Step 6
Check the SATRF bit or wait for a SPIA serial bus interrupt.
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• Step 7
Read data from the SPIAD register.
• Step 8
Clear SATRF.
• Step 9
Go to step 4.
Slave Mode
• Step 1
Select the SPI Slave mode using the SASPI2~SASPI0 bits in the SPIAC0 control register
• Step 2
Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB shifted
first, this setting must be the same with the Master device.
• Step 3
Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface.
• Step 4
For write operations: write the data to the SPIAD register, which will actually place the data into
the TXRX buffer. Then wait for the master clock SCKA and SCSA signal. After this, go to step 5.
For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer
until all the data has been received at which point it will be latched into the SPIAD register.
• Step 5
Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal
to zero then go to the following step.
• Step 6
Check the SATRF bit or wait for a SPIA serial bus interrupt.
• Step 7
Read data from the SPIAD register.
• Step 8
Clear SATRF.
• Step 9
Go to step 4.
Error Detection
The SAWCOL bit in the SPIAC1 register is provided to indicate errors during data transfer. The bit
is set by the SPIA serial Interface but must be cleared by the application program. This bit indicates
a data collision has occurred which happens if a write to the SPIAD register takes place during a
data transfer operation and will prevent the write operation from continuing.
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UART Interface
These devices contain up to three integrated full-duplex asynchronous serial communications UART
interfaces that enable communication with external devices that contain a serial interface. The
UART function has many features and can transmit and receive data serially by transferring a frame
of data with eight or nine data bits per transmission as well as being able to detect errors when the
data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt
which can be used to indicate when a reception occurs or when a transmission terminates.
Decive
UART Interface
HT66F2350/HT66F2360
2
HT66F2370/HT66F2390
3
Each integrated UART function contains the following features:
• Full-duplex, asynchronous communication
• 8 or 9 bits character length
• Even, odd or no parity options
• One or two stop bits
• Baud rate generator with 8-bit prescaler
• Parity, framing, noise and overrun error detection
• Support for interrupt on address detect (last character bit=1)
• Separately enabled transmitter and receiver
• 2-byte Deep FIFO Receive Data Buffer
• RX pin wake-up function
• Transmit and receive interrupts
• Interrupts can be initialized by the following conditions:
♦♦
Transmitter Empty
♦♦
Transmitter Idle
♦♦
Receiver Full
♦♦
Receiver Overrun
♦♦
Address Mode Detect
T�ans�itte� Shift Registe� (TSRn)
MSB ………………………… LSB
TXn Pin RXn Pin
TX Registe� (TXRn)
Re�eive� Shift Registe� (RSRn)
MSB ………………………… LSB
RX Registe� (RXRn)
Buffe�
Baud Rate
Gene�ato� n
fH
Data to �e t�ans�itted
Data �e�eived
MCU Data Bus
UART Data Transfer Block Diagram
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UART External Pin
To communicate with an external serial interface, the internal UARTn has two external pins known
as TXn and RXn. The TXn and RXn pins are the UARTn transmitter and receiver pins respectively.
The TXn and RXn pin function should first be selected by the corresponding pin-shared function
selection register before the UARTn function is used. Along with the UARTENn bit, the TXENn and
RXENn bits, if set, will automatically setup the TXn and RXn pins to their respective TXn output
and RXn input conditions and disable any pull-high resistor option which may exist on the TXn and
RXn pins. When the TXn or RXn pin function is disabled by clearing the UARTENn, TXENn or
RXENn bit, the TXn or RXn pin will be set to a floating state. At this time whether the internal pullhigh resistor is connected to the TXn or RXn pin or not is determined by the corresponding I/O pullhigh function control bit.
UART Data Transfer Scheme
The above diagram shows the overall data transfer structure arrangement for the UARTn interface.
The actual data to be transmitted from the MCU is first transferred to the TXRn register by the
application program. The data will then be transferred to the Transmit Shift Register from where it
will be shifted out, LSB first, onto the TXn pin at a rate controlled by the Baud Rate Generator n.
Only the TXRn register is mapped onto the MCU Data Memory, the Transmit Shift Register is not
mapped and is therefore inaccessible to the application program.
Data to be received by the UARTn is accepted on the external RXn pin, from where it is shifted in,
LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the
shift register is full, the data will then be transferred from the shift register to the internal RXRn
register, where it is buffered and can be manipulated by the application program. Only the TXRn
register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is
therefore inaccessible to the application program.
It should be noted that the actual register for data transmission and reception, although referred to in
the text, and in application programs, as separate TXRn and RXRn registers, only exists as a single
shared register in the Data Memory. This shared register known as the TXR_RXRn register is used
for both data transmission and data reception.
UART Status and Control Registers
There are five control registers associated with the UARTn function. The UnSR, UnCR1 and UnCR2
registers control the overall function of the UARTn, while the BRGn register controls the Baud rate.
The actual data to be transmitted and received on the serial interface is managed through the TXR_
RXRn data registers.
TXR_RXRn Register
The TXR_RXRn register is the data register which is used to store the data to be transmitted on the
TXn pin or being received from the RXn pin.
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
"x": unknown
Bit 7~0D7~D0: UARTn Transmit/Receive Data bits
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UnSR Register
The UnSR register is the status register for the UARTn, which can be read by the program to
determine the present status of the UARTn. All flags within the UnSR register are read only and
further explanations are given below.
Bit
7
6
5
4
3
2
1
0
Name
PERRn
NFn
FERRn
OERRn
RIDLEn
RXIFn
TIDLEn
TXIFn
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
1
0
1
1
Bit 7
PERRn: Parity error flag
0: No parity error is detected
1: Parity error is detected
The PERRn flag is the parity error flag. When this read only flag is "0", it indicates a
parity error has not been detected. When the flag is "1", it indicates that the parity of
the received word is incorrect. This error flag is applicable only if Parity mode (odd or
even) is selected. The flag can also be cleared by a software sequence which involves
a read to the status register UnSR followed by an access to the TXR_RXRn data
register.
Bit 6
NFn: Noise flag
0: No noise is detected
1: Noise is detected
The NFn flag is the noise flag. When this read only flag is "0", it indicates no noise
condition. When the flag is "1", it indicates that the UARTn has detected noise on the
receiver input. The NFn flag is set during the same cycle as the RXIFn flag but will not
be set in the case of as overrun. The NFn flag can be cleared by a software sequence
which will involve a read to the status register UnSR followed by an access to the
TXR_RXRn data register.
Bit 5
FERRn: Framing error flag
0: No framing error is detected
1: Framing error is detected
The FERRn flag is the framing error flag. When this read only flag is "0", it indicates
that there is no framing error. When the flag is "1", it indicates that a framing error
has been detected for the current character. The flag can also be cleared by a software
sequence which will involve a read to the status register UnSR followed by an access
to the TXR_RXRn data register.
Bit 4OERRn: Overrun error flag
0: No overrun error is detected
1: Overrun error is detected
The OERRn flag is the overrun error flag which indicates when the receiver buffer has
overflowed. When this read only flag is "0", it indicates that there is no overrun error.
When the flag is "1", it indicates that an overrun error occurs which will inhibit further
transfers to the TXR_RXRn receive data register. The flag is cleared by a software
sequence, which is a read to the status register UnSR followed by an access to the
TXR_RXRn data register.
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Bit 3RIDLEn: Receiver status
0: data reception is in progress (data being received)
1: no data reception is in progress (receiver is idle)
The RIDLEn flag is the receiver status flag. When this read only flag is "0", it indicates
that the receiver is between the initial detection of the start bit and the completion of
the stop bit. When the flag is "1", it indicates that the receiver is idle. Between the
completion of the stop bit and the detection of the next start bit, the RIDLEn bit is
"1" indicating that the UARTn receiver is idle and the RXn pin stays in logic high
condition.
Bit 2RXIFn: Receive TXR_RXRn data register status
0: TXR_RXRn data register is empty
1: TXR_RXRn data register has available data
The RXIFn flag is the receive data register status flag. When this read only flag is "0",
it indicates that the TXR_RXRn read data register is empty. When the flag is "1", it
indicates that the TXR_RXRn read data register contains new data. When the contents
of the shift register are transferred to the TXR_RXRn register, an interrupt is generated
if RIEn=1 in the UnCR2 register. If one or more errors are detected in the received
word, the appropriate receive-related flags NFn, FERRn, and/or PERRn are set within
the same clock cycle. The RXIFn flag will eventually be cleared when the UnSR
register is read with RXIFn set, followed by a read from the TXR_RXRn register, and
if the TXR_RXRn register has no more new data available.
Bit 1TIDLEn: Transmission status
0: data transmission is in progress (data being transmitted)
1: no data transmission is in progress (transmitter is idle)
The TIDLEn flag is known as the transmission complete flag. When this read only
flag is "0", it indicates that a transmission is in progress. This flag will be set to "1"
when the TXIFn flag is "1" and when there is no transmit data or break character being
transmitted. When TIDLEn is equal to 1, the TXn pin becomes idle with the pin state
in logic high condition. The TIDLEn flag is cleared by reading the UnSR register with
TIDLEn set and then writing to the TXR_RXRn register. The flag is not generated
when a data character or a break is queued and ready to be sent.
Bit 0TXIFn: Transmit TXR data register status
0: character is not transferred to the transmit shift register
1: character has transferred to the transmit shift register (TXR_RXRn data register is
empty)
The TXIFn flag is the transmit data register empty flag. When this read only flag is
"0", it indicates that the character is not transferred to the transmitter shift register.
When the flag is "1", it indicates that the transmitter shift register has received a
character from the TXR_RXRn data register. The TXIFn flag is cleared by reading the
UARTn status register (UnSR) with TXIFn set and then writing to the TXR_RXRn
data register. Note that when the TXENn bit is set, the TXIFn flag bit will also be set
since the transmit data register is not yet full.
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UnCR1 Register
The UnCR1 register together with the UnCR2 register are the UARTn control registers that are used
to set the various options for the UARTn function such as overall on/off control, parity control, data
transfer bit length, etc. Further explanation on each of the bits is given below.
Bit
7
6
5
4
3
2
1
0
Name
UARTENn
BNOn
PRENn
PRTn
STOPSn
TXBRKn
RX8n
TX8n
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
W
POR
0
0
0
0
0
0
x
0
"x": unknown
Bit 7
UARTENn: UARTn function enable control
0: Disable UARTn; TXn and RXn pins are in a high impedance state.
1: Enable UARTn; TXn and RXn pins function as UARTn pins
The UARTENn bit is the UARTn enable bit. When this bit is equal to "0", the
UARTn will be disabled and the RXn pin as well as the TXn pin will be set in a high
impedance state. When the bit is equal to "1", the UARTn will be enabled and the
TXn and RXn pins will function as defined by the TXENn and RXENn enable control
bits. When the UARTn is disabled, it will empty the buffer so any character remaining
in the buffer will be discarded. In addition, the value of the baud rate counter will
be reset. If the UARTn is disabled, all error and status flags will be reset. Also the
TXENn, RXENn, TXBRKn, RXIFn, OERRn, FERRn, PERRn and NFn bits will be
cleared, while the TIDLEn, TXIFn and RIDLEn bits will be set. Other control bits in
UnCR1, UnCR2 and BRGn registers will remain unaffected. If the UARTn is active
and the UARTENn bit is cleared, all pending transmissions and receptions will be
terminated and the module will be reset as defined above. When the UARTn is reenabled, it will restart in the same configuration.
Bit 6BNOn: Number of data transfer bits selection
0: 8-bit data transfer
1: 9-bit data transfer
This bit is used to select the data length format, which can have a choice of either
8-bit or 9-bit format. When this bit is equal to "1", a 9-bit data length format will be
selected. If the bit is equal to "0", then an 8-bit data length format will be selected. If
9-bit data length format is selected, then bits RX8n and TX8n will be used to store the
9th bit of the received and transmitted data respectively.
Bit 5PRENn: Parity function enable control
0: Parity function is disabled
1: Parity function is enabled
This bit is the parity function enable bit. When this bit is equal to 1, the parity function
will be enabled. If the bit is equal to 0, then the parity function will be disabled.
Bit 4PRTn: Parity type selection bit
0: Even parity for parity generator
1: Odd parity for parity generator
This bit is the parity type selection bit. When this bit is equal to 1, odd parity type will
be selected. If the bit is equal to 0, then even parity type will be selected.
Bit 3STOPSn: Number of stop bits selection
0: One stop bit format is used
1: Two stop bits format is used
This bit determines if one or two stop bits are to be used. When this bit is equal to "1",
two stop bits format are used. If the bit is equal to "0", then only one stop bit format is
used.
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Bit 2TXBRKn: Transmit break character
0: No break character is transmitted
1: Break characters transmit
The TXBRKn bit is the Transmit Break Character bit. When this bit is equal to "0",
there are no break characters and the TXn pin operates normally. When the bit is
equal to "1", there are transmit break characters and the transmitter will send logic
zeros. When this bit is equal to "1", after the buffered data has been transmitted, the
transmitter output is held low for a minimum of a 13-bit length and until the TXBRKn
bit is reset.
Bit 1RX8n: Receive data bit 8 for 9-bit data transfer format (read only)
This bit is only used if 9-bit data transfers are used, in which case this bit location
will store the 9th bit of the received data known as RX8n. The BNOn bit is used to
determine whether data transfers are in 8-bit or 9-bit format.
Bit 0TX8n: Transmit data bit 8 for 9-bit data transfer format (write only)
This bit is only used if 9-bit data transfers are used, in which case this bit location
will store the 9th bit of the transmitted data known as TX8n. The BNOn bit is used to
determine whether data transfers are in 8-bit or 9-bit format.
UnCR2 Register
The UnCR2 register is the second of the UARTn control registers and serves several purposes.
One of its main functions is to control the basic enable/disable operation if the UARTn Transmitter
and Receiver as well as enabling the various UARTn interrupt sources. The register also serves to
control the baud rate speed, receiver wake-up function enable and the address detect function enable.
Further explanation on each of the bits is given below.
Bit
7
6
5
4
3
2
1
0
Name
TXENn
RXENn
BRGHn
ADDENn
WAKEn
RIEn
TIIEn
TEIEn
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7TXENn: UARTn Transmitter enable control
0: UARTn Transmitter is disabled
1: UARTn Transmitter is enabled
The TXENn bit is the Transmitter Enable Bit. When this bit is equal to "0", the
transmitter will be disabled with any pending data transmissions being aborted. In
addition the buffers will be reset. If the TXENn bit is equal to "1" and the UARTENn
bit is also equal to 1, the transmitter will be enabled and the TXn pin will be controlled
by the UARTn. Clearing the TXENn bit during a transmission will cause the data
transmission to be aborted and will reset the transmitter.
Rev. 1.00
Bit 6
RXENn: UARTn Receiver enable control
0: UARTn Receiver is disabled
1: UARTn Receiver is enabled
The RXENn bit is the Receiver Enable Bit. When this bit is equal to "0", the receiver
will be disabled with any pending data receptions being aborted. In addition the
receiver buffers will be reset. If the RXENn bit is equal to "1" and the UARTENn bit
is also equal to 1, the receiver will be enabled and the RXn pin will be controlled by
the UARTn. Clearing the RXENn bit during a reception will cause the data reception
to be aborted and will reset the receiver.
Bit 5
BRGHn: Baud Rate speed selection
0: Low speed baud rate
1: High speed baud rate
The bit named BRGHn selects the high or low speed mode of the Baud Rate Generator
n. This bit, together with the value placed in the baud rate register, BRGn, controls the
baud rate of the UARTn. If the bit is equal to 0, the low speed mode is selected.
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Rev. 1.00
Bit 4
ADDENn: Address detect function enable control
0: Address detection function is disabled
1: Address detection function is enabled
The bit named ADDENn is the address detection function enable control bit. When
this bit is equal to 1, the address detection function is enabled. When it occurs, if the
8th bit, which corresponds to RX7n if BNO=0, or the 9th bit, which corresponds to
RX8n if BNOn=1, has a value of "1", then the received word will be identified as an
address, rather than data. If the corresponding interrupt is enabled, an interrupt request
will be generated each time the received word has the address bit set, which is the 8th
or 9th bit depending on the value of the BNOn bit. If the address bit known as the 8th or
9th bit of the received word is "0" with the address detection function being enabled, an
interrupt will not be generated and the received data will be discarded.
Bit 3
WAKEn: RXn pin falling edge wake-up function enable control
0: RXn pin wake-up UARTn function is disabled
1: RXn pin wake-up UARTn function is enabled
The bit is used to control the wake-up UARTn function when a falling edge on the
RXn pin occurs. Note that this bit is only available when the UARTn clock, fH, is
switched off. There will be no RXn pin wake-up UARTn function if the UARTn
clock, fH, exists. If the WAKEn bit is equal to 1 and the UARTn clock, fH, is switched
off, a UARTn wake-up request will be initiated when a falling edge on the RXn pin
occurs. When this request happens and the corresponding interrupt is enabled, an RXn
pin wake-up UARTn interrupt will be generated to inform the MCU to wake up the
UARTn function by switching on the UARTn clock, fH, via the application programs.
Otherwise, the UARTn function can not resume even if there is a falling edge on the
RXn pin when the WAKEn bit is cleared to 0.
Bit 2
RIEn: Receiver interrupt enable control
0: Receiver related interrupt is disabled
1: Receiver related interrupt is enabled
The bit enables or disables the receiver interrupt. If this bit is equal to 1 and when the
receiver overrun flag OERRn or received data available flag RXIFn is set, the UARTn
interrupt request flag will be set. If this bit is equal to 0, the UARTn interrupt request
flag will not be influenced by the condition of the OERRn or RXIFn flags.
Bit 1
TIIEn: Transmitter Idle interrupt enable control
0: Transmitter idle interrupt is disabled
1: Transmitter idle interrupt is enabled
The bit enables or disables the transmitter idle interrupt. If this bit is equal to 1 and
when the transmitter idle flag TIDLEn is set, due to a transmitter idle condition, the
UARTn interrupt request flag will be set. If this bit is equal to 0, the UARTn interrupt
request flag will not be influenced by the condition of the TIDLEn flag.
Bit 0
TEIEn: Transmitter Empty interrupt enable control
0: Transmitter empty interrupt is disabled
1: Transmitter empty interrupt is enabled
The bit enables or disables the transmitter empty interrupt. If this bit is equal to 1 and
when the transmitter empty flag TXIFn is set, due to a transmitter empty condition, the
UARTn interrupt request flag will be set. If this bit is equal to 0, the UARTn interrupt
request flag will not be influenced by the condition of the TXIFn flag.
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Baud Rate Generator
To setup the speed of the serial data communication, the UARTn function contains its own dedicated
baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the
period of which is determined by two factors. The first of these is the value placed in the BRGn
register and the second is the value of the BRGHn bit within the UnCR2 control register. The
BRGHn bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode,
which in turn determines the formula that is used to calculate the baud rate. The value in the BRGn
register, N, which is used in the following baud rate calculation formula determines the division
factor. Note that N is the decimal value placed in the BRGn register and has a range of between 0
and 255.
UnCR2 BRGHn Bit
0
1
Baud Rate (BR)
fH / [64 (N+1)]
fH / [16 (N+1)]
By programming the BRGHn bit which allows selection of the related formula and programming
the required value in the BRGn register, the required baud rate can be setup. Note that because the
actual baud rate is determined using a discrete value, N, placed in the BRGn register, there will be
an error associated between the actual and requested value. The following example shows how the
BRGn register value N and the error value can be calculated.
BRGn Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
"x": unknown
Bit 7~0D7~D0: Baud Rate values
By programming the BRGHn bit in the UnCR2 register which allows selection of the
related formula described above and programming the required value in the BRGn
register, the required baud rate can be setup.
Calculating the Baud Rate and Error Values
For a clock frequency of 4MHz, and with BRGHn set to 0 determine the BRGn register value N, the
actual baud rate and the error value for a desired baud rate of 4800.
From the above table the desired baud rate BR = fH / [64 (N+1)]
Re-arranging this equation gives N = [fH / (BR×64)] - 1
Giving a value for N = [4000000 / (4800×64)] - 1 = 12.0208
To obtain the closest value, a decimal value of 12 should be placed into the BRGn register. This
gives an actual or calculated baud rate value of BR = 4000000 / [64× (12+1)] = 4808
Therefore the error is equal to (4808 - 4800) / 4800 = 0.16%
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UART Setup and Control
For data transfer, the UARTn function utilizes a non-return-to-zero, more commonly known as
NRZ, format. This is composed of one start bit, eight or nine data bits and one or two stop bits.
Parity is supported by the UARTn hardware and can be setup to be even, odd or no parity. For the
most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1,
is used as the default setting, which is the setting at power-on. The number of data bits and stop
bits, along with the parity, are setup by programming the corresponding BNOn, PRTn, PRENn and
STOPSn bits in the UnCR1 register. The baud rate used to transmit and receive data is setup using
the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although
the transmitter and receiver of the UARTn are functionally independent, they both use the same data
format and baud rate. In all cases stop bits will be used for data transmission.
Enabling/Disabling the UART Interface
The basic on/off function of the internal UARTn function is controlled using the UARTENn bit in
the UnCR1 register. If the UARTENn, TXENn and RXENn bits are set, then these two UARTn pins
will act as normal TXn output pin and RXn input pin respectively. If no data is being transmitted on
the TXn pin, then it will default to a logic high value.
Clearing the UARTENn bit will disable the TXn and RXn pins and then these two pins can be used
as an I/O or other pin-shared functional pins by properly configurations. When the UARTn function
is disabled, the buffer will be reset to an empty condition, at the same time discarding any remaining
residual data. Disabling the UARTn will also reset the enable control, the error and status flags with
bits TXENn, RXENn, TXBRKn, RXIFn, OERRn, FERRn, PERRn and NFn being cleared while
bits TIDLEn, TXIFn and RIDLEn will be set. The remaining control bits in the UnCR1, UnCR2 and
BRGn registers will remain unaffected. If the UARTENn bit in the UnCR1 register is cleared while
the UARTn is active, then all pending transmissions and receptions will be immediately suspended
and the UARTn will be reset to a condition as defined above. If the UARTn is then subsequently reenabled, it will restart again in the same configuration.
Data, Parity and Stop Bit Selection
The format of the data to be transferred is composed of various factors such as data bit length,
parity on/off, parity type, address bits and the number of stop bits. These factors are determined by
the setup of various bits within the UnCR1 register. The BNOn bit controls the number of data bits
which can be set to either 8 or 9. The PRTn bit controls the choice if odd or even parity. The PRENn
bit controls the parity on/off function. The STOPSn bit decides whether one or two stop bits are to
be used. The following table shows various formats for data transmission. The address bit, which is
the MSB of the data byte, identifies the frame as an address character or data if the address detect
function is enabled. The number of stop bits, which can be either one or two, is independent of the
data length.
Start Bit
Data Bits
Address Bits
Parity Bit
Stop Bit
Example of 8-bit Data Formats
1
8
0
0
1
1
7
0
1
1
1
7
1
0
1
Example of 9-bit Data Formats
1
9
0
0
1
1
8
0
1
1
1
8
1
0
1
Transmitter Receiver Data Format
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The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data
formats.
UART Transmitter
Data word lengths of either 8 or 9 bits can be selected by programming the BNOn bit in the UnCR1
register. When BNOn bit is set, the word length will be set to 9 bits. In this case the 9th bit, which
is the MSB, needs to be stored in the TX8n bit in the UnCR1 register. At the transmitter core lies
the Transmitter Shift Register, more commonly known as the TSRn, whose data is obtained from
the transmit data register, which is known as the TXR_RXRn register. The data to be transmitted is
loaded into this TXR_RXRn register by the application program. The TSRn register is not written
to with new data until the stop bit from the previous transmission has been sent out. As soon as this
stop bit has been transmitted, the TSRn can then be loaded with new data from the TXR_RXRn
register, if it is available. It should be noted that the TSRn register, unlike many other registers,
is not directly mapped into the Data Memory area and as such is not available to the application
program for direct read/write operations. An actual transmission of data will normally be enabled
when the TXENn bit is set, but the data will not be transmitted until the TXR_RXRn register has
been loaded with data and the baud rate generator has defined a shift clock source. However, the
transmission can also be initiated by first loading data into the TXR_RXRn register, after which the
TXENn bit can be set. When a transmission of data begins, the TSRn is normally empty, in which
case a transfer to the TXR_RXRn register will result in an immediate transfer to the TSRn. If during
a transmission the TXENn bit is cleared, the transmission will immediately cease and the transmitter
will be reset. The TXn output pin can then return to the I/O or other pin-shared function by properly
configurations.
Transmitting Data
When the UARTn is transmitting data, the data is shifted on the TXn pin from the shift register,
with the least significant bit LSB first. In the transmit mode, the TXR_RXRn register forms a buffer
between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format
has been selected, then the MSB will be taken from the TX8n bit in the UnCR1 register. The steps to
initiate a data transfer can be summarized as follows:
• Make the correct selection of the BNOn, PRTn, PRENn and STOPSn bits to define the required
word length, parity type and number of stop bits.
• Setup the BRGn register to select the desired baud rate.
• Set the TXENn bit to ensure that the UARTn transmitter is enabled and the TXn pin is used as a
UARTn transmitter pin.
• Access the UnSR register and write the data that is to be transmitted into the TXR_RXRn
register. Note that this step will clear the TXIFn bit.
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This sequence of events can now be repeated to send additional data. It should be noted that when
TXIFn=0, data will be inhibited from being written to the TXR_RXRn register. Clearing the TXIFn
flag is always achieved using the following software sequence:
1. A UnSR register access
2. A TXR_RXRn register write execution
The read-only TXIFn flag is set by the UARTn hardware and if set indicates that the TXR_RXRn
register is empty and that other data can now be written into the TXR_RXRn register without
overwriting the previous data. If the TEIEn bit is set, then the TXIFn flag will generate an interrupt.
During a data transmission, a write instruction to the TXR_RXRn register will place the data into the
TXR_RXRn register, which will be copied to the shift register at the end of the present transmission.
When there is no data transmission in progress, a write instruction to the TXR_RXRn register will
place the data directly into the shift register, resulting in the commencement of data transmission,
and the TXIFn bit being immediately set. When a frame transmission is complete, which happens
after stop bits are sent or after the break frame, the TIDLEn bit will be set. To clear the TIDLEn bit
the following software sequence is used:
1. A UnSR register access
2. A TXR_RXRn register write execution
Note that both the TXIFn and TIDLEn bits are cleared by the same software sequence.
Transmitting Break
If the TXBRKn bit is set, then the break characters will be sent on the next transmission. Break
character transmission consists of a start bit, followed by 13xN "0" bits, where N=1, 2, etc. If a break
character is to be transmitted, then the TXBRKn bit must be first set by the application program and
then cleared to generate the stop bits. Transmitting a break character will not generate a transmit
interrupt. Note that a break condition length is at least 13 bits long. If the TXBRKn bit is continually
kept at a logic high level, then the transmitter circuitry will transmit continuous break characters.
After the application program has cleared the TXBRKn bit, the transmitter will finish transmitting
the last break character and subsequently send out one or two stop bits. The automatic logic high at
the end of the last break character will ensure that the start bit of the next frame is recognized.
UART Receiver
The UARTn is capable of receiving word lengths of either 8 or 9 bits can be selected by
programming the BNOn bit in the UnCR1 register. When BNOn bit is set, the word length will be
set to 9 bits. In this case the 9th bit, which is the MSB, will be stored in the RX8n bit in the UnCR1
register. At the receiver core lies the Receiver Shift Register more commonly known as the RSRn.
The data which is received on the RXn external input pin is sent to the data recovery block. The data
recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter
operates at the baud rate. After the RXn pin is sampled for the stop bit, the received data in RSRn
is transferred to the receive data register, if the register is empty. The data which is received on the
external RXn input pin is sampled three times by a majority detect circuit to determine the logic
level that has been placed onto the RXn pin. It should be noted that the RSRn register, unlike many
other registers, is not directly mapped into the Data Memory area and as such is not available to the
application program for direct read/write operations.
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Receiving Data
When the UARTn receiver is receiving data, the data is serially shifted in on the external RXn input
pin to the shift register, with the least significant bit LSB first. The TXR_RXRn register is a two
byte deep FIFO data buffer, where two bytes can be held in the FIFO while the 3rd byte can continue
to be received. Note that the application program must ensure that the data is read from TXR_RXRn
before the 3rd byte has been completely shifted in, otherwise the 3rd byte will be discarded and an
overrun error OERRn will be subsequently indicated. The steps to initiate a data transfer can be
summarized as follows:
• Make the correct selection of the BNOn, PRTn, PRENn and STOPSn bits to define the required
word length, parity type and number of stop bits.
• Setup the BRGn register to select the desired baud rate.
• Set the RXENn bit to ensure that the UARTn receiver is enabled and the RXn pin is used as a
UARTn receiver pin.
At this point the receiver will be enabled which will begin to look for a start bit.
When a character is received, the following sequence of events will occur:
• The RXIFn bit in the UnSR register will be set when the TXR_RXRn register has data available.
There will be at most one more character that can be read.
• When the contents of the shift register have been transferred to the TXR_RXRn register and if
the RIEn bit is set, then an interrupt will be generated.
• If during reception, a frame error, noise error, parity error or an overrun error has been detected,
then the error flags can be set.
The RXIFn bit can be cleared using the following software sequence:
1. A UnSR register access
2. A TXR_RXRn register read execution
Receiving Break
Any break character received by the UARTn will be managed as a framing error. The receiver
will count and expect a certain number of bit times as specified by the values programmed into
the BNOn and STOPSn bits. If the break is much longer than 13 bit times, the reception will be
considered as complete after the number of bit times specified by BNOn and STOPSn. The RXIFn
bit is set, FERRn is set, zeros are loaded into the receive data register, interrupts are generated if
appropriate and the RIDLEn bit is set. A break is regarded as a character that contains only zeros
with the FERRn flag being set. If a long break signal has been detected, the receiver will regard it as
a data frame including a start bit, data bits and the invalid stop bit and the FERRn flag will be set.
The receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not
make the assumption that the break condition on the line is the next start bit. The break character
will be loaded into the buffer and no further data will be received until stop bits are received. It
should be noted that the RIDLEn read only flag will go high when the stop bits have not yet been
received. The reception of a break character on the UARTn registers will result in the following:
• The framing error flag, FERRn, will be set.
• The receive data register, TXR_RXRn, will be cleared.
• The OERRn, NFn, PERRn, RIDLEn or RXIFn flags will possibly be set.
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Idle Status
When the receiver is reading data, which means it will be in between the detection of a start bit
and the reading of a stop bit, the receiver status flag in the UnSR register, otherwise known as the
RIDLEn flag, will have a zero value. In between the reception of a stop bit and the detection of
the next start bit, the RIDLEn flag will have a high value, which indicates the receiver is in an idle
condition.
Receiver Interrupt
The read only receive interrupt flag, RXIFn, in the UnSR register is set by an edge generated by the
receiver. An interrupt is generated if RIEn=1, when a word is transferred from the Receive Shift
Register, RSRn, to the Receive Data Register, TXR_RXRn. An overrun error can also generate an
interrupt if RIEn=1.
Managing Receiver Errors
Several types of reception errors can occur within the UARTn module, the following section
describes the various types and how they are managed by the UARTn.
Overrun Error – OERRn
The TXR_RXRn register is composed of a two byte deep FIFO data buffer, where two bytes can be
held in the FIFO register, while a 3th byte can continue to be received. Before the 3th byte has been
entirely shifted in, the data should be read from the TXR_RXRn register. If this is not done, the
overrun error flag OERRn will be consequently indicated.
In the event of an overrun error occurring, the following will happen:
• The OERRn flag in the UnSR register will be set.
• The TXR_RXRn contents will not be lost.
• The shift register will be overwritten.
• An interrupt will be generated if the RIEn bit is set.
The OERRn flag can be cleared by an access to the UnSR register followed by a read to the TXR_
RXRn register.
Noise Error – NFn
Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is
detected within a frame, the following will occur:
• The read only noise flag, NFn, in the UnSR register will be set on the rising edge of the RXIFn
bit.
• Data will be transferred from the shift register to the TXR_RXRn register.
• No interrupt will be generated. However this bit rises at the same time as the RXIFn bit which
itself generates an interrupt.
Note that the NFn flag is reset by an UnSR register read operation followed by a TXR_RXRn
register read operation.
Framing Error – FERRn
The read only framing error flag, FERRn, in the UnSR register, is set if a zero is detected instead of
stop bits. If two stop bits are selected, both stop bits must be high. Otherwise the FERRn flag will be
set. The FERRn flag and the received data will be recorded in the UnSR and TXR_RXRn registers
respectively and the FERRn flag will be cleared in any reset.
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Parity Error – PERRn
The read only parity error flag, PERRn, in the UnSR register, is set if the parity of the received
word is incorrect. This error flag is only applicable if the parity function is enabled, PRENn=1, and
if the parity type, odd or even, is selected. The read only PERRn flag and the received data will be
recorded in the UnSR and TXR_RXRn registers respectively and the flag will be cleared on any
reset. It should be noted that the FERRn and PERRn flags in the UnSR register should first be read
by the application programs before reading the data word.
UART Interrupt Structure
Several individual UARTn conditions can generate a UARTn interrupt. When these conditions
exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are
a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address
detect and an RXn pin wake-up. When any of these conditions are created, if its corresponding
interrupt control is enabled and the stack is not full, the program will jump to its corresponding
interrupt vector where it can be serviced before returning to the main program. Four of these conditions
have the corresponding UnSR register flags which will generate a UARTn interrupt if its associated
interrupt enable control bit in the UnCR2 register is set. The two transmitter interrupt conditions have
their own corresponding enable control bits, while the two receiver interrupt conditions have a shared
enable control bit. These enable bits can be used to mask out individual UARTn interrupt sources.
The address detect condition, which is also a UARTn interrupt source, does not have an associated
flag, but will generate a UARTn interrupt when an address detect condition occurs if its function is
enabled by setting the ADDENn bit in the UnCR2 register. An RXn pin wake-up, which is also a
UARTn interrupt source, does not have an associated flag, but will generate a UARTn interrupt if the
UARTn clock source, fH, is switched off and the WAKEn and RIEn bits in the UnCR2 register are
set when a falling edge on the RXn pin occurs. Note that in the event of an RXn wake-up interrupt
occurring, there will be a certain period of delay, commonly known as the System Start-up Time, for
the oscillator to restart and stabilize before the system resumes normal operation.
Note that the UnSR register flags are read only and cannot be cleared or set by the application
program, neither will they be cleared when the program jumps to the corresponding interrupt
servicing routine, as is the case for some of the other interrupts. The flags will be cleared
automatically when certain actions are taken by the UARTn, the details of which are given in the
UARTn register section. The overall UARTn interrupt can be disabled or enabled by the related
interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether
the interrupt requested by the UARTn module is masked out or allowed.
UnSR Register
UnCR2 Register
Transmitter Empty Flag
TXIFn
TEIEn
Transmitter Idle Flag
TIDLEn
TIIEn
1
RIEn
OR
Receiver Data Available
RXIFn
WAKEn
0
1
Receiver Overrun Flag
OERRn
RXn Pin
Wake-up
0
ADDENn
URnE
0
1
EMI
0
1
Interrupt signal
to MCU
1
0
1
0
UARTn Interrupt
Request Flag
URnF
0
0
1
TXR_RXRn.7 if BNO=0
RX8n if BNO=1
1
UnCR2 Register
UARTn Interrupt Structure
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Address Detect Mode
Setting the Address Detect function enable control bit, ADDENn, in the UnCR2 register, enables this
special function. If this bit is set to 1, then an additional qualifier will be placed on the generation
of a Receiver Data Available interrupt, which is requested by the RXIFn flag. If the ADDENn bit
is equal to 1, then when the data is available, an interrupt will only be generated, if the highest
received bit has a high value. Note that the related interrupt enable control bit and the EMI bit of
the microcontroller must also be enabled for correct interrupt generation. The highest address bit
is the 9th bit if the bit BNOn=1 or the 8th bit if the bit BNOn=0. If the highest bit is high, then the
received word will be defined as an address rather than data. A Data Available interrupt will be
generated every time the last bit of the received word is set. If the ADDENn bit is equal to 0, then a
Receive Data Available interrupt will be generated each time the RXIFn flag is set, irrespective of
the data last bit status. The address detection and parity functions are mutually exclusive functions.
Therefore, if the address detect function is enabled, then to ensure correct operation, the parity
function should be disabled by resetting the parity function enable bit PRENn to zero.
ADDENn
Bit 9 if BNOn=1
Bit 8 if BNOn=0
UARTn Interrupt
Generated
0
√
0
1
1
√
0
X
1
√
ADDENn Bit Function
UART Power Down and Wake-up
When the UARTn clock, fH, is switched off, the UARTn will cease to function. If the MCU switches
off the UARTn clock fH and enters the power down mode while a transmission is still in progress,
then the transmission will be paused until the UARTn clock source derived from the microcontroller
is activated. In a similar way, if the MCU switches off the UART clock fH and enters the power
down mode by executing the "HALT" instruction while receiving data, then the reception of data
will likewise be paused. When the MCU enters the power down mode, note that the UnSR, UnCR1,
UnCR2, transmit and receive registers, as well as the BRGn register will not be affected. It is
recommended to make sure first that the UARTn data transmission or reception has been finished
before the microcontroller enters the power down mode.
The UARTn function contains a receiver RXn pin wake-up function, which is enabled or disabled
by the WAKEn bit in the UnCR2 register. If this bit, along with the UARTn enable bit, UARTENn,
the receiver enable bit, RXENn and the receiver interrupt bit, RIEn, are all set before the MCU
enters the power down mode with the UARTn clock fH being switched off, then a falling edge on the
RXn pin will initiate a RXn pin wake-up UARTn interrupt. Note that as it takes certain system clock
cycles after a wake-up, before normal microcontroller operation resumes, any data received during
this time on the RXn pin will be ignored.
For a UARTn wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global
interrupt enable bit, EMI, and the UARTn interrupt enable bit, URnE, must be set. If the EMI and
URnE bits are not set then only a wake up event will occur and no interrupt will be generated.
Note also that as it takes certain system clock cycles after a wake-up before normal microcontroller
resumes, the UARTn interrupt will not be generated until after this time has elapsed.
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Comparators
Two independent analog conparators are contained in these devices. The comparator functions offer
flexibility via their register controlled features such as power-down, polarity select, response time,
etc. In sharing their pins with normal I/O pins the comparators do not waste precious I/O pins if the
comparator functions are otherwise unused.
CnPOL
Cn+
+
Cn−
−
Pin-shared
Selection
CnOUT
CPnINT
One
Shot
CnX
Pin-shared
Selection
CnEN
Comparators (n=0~1)
Comparator Operation
The devices contain two comparator functions which are used to compare two analog voltages
and provide an output based on their difference. Full control over the two internal comparators is
provided via the control register, CP0C and CP1C, one assigned to each comparator. The comparator
output is recorded via a bit in the control register, but can also be transferred out onto a shared I/O
pin. Additional comparator functions include output polarity, response time and power down control.
Any pull-high resistors connected to the shared comparator input pins will be automatically
disconnected when the comparator is enabled. As the comparator inputs approach their switching
level, some spurious output signals may be generated on the comparator output due to the slow
rising or falling nature of the input signals. This can be minimised by the hysteresis function which
will apply a small amount of positive feedback to the comparator. When the comparator operates
in the normal mode, the hysteresis function will automatically be enabled. However, the hysteresis
function will be disabled when the comparator operates in the input offset calibration mode.
Ideally the comparator should switch at the point where the positive and negative inputs signals are
at the same voltage level. However, unavoidable input offsets introduce some uncertainties here. The
offset calibration function, if executed, will minimise the switching offset value. The comparator
also provides the output response time select function using the CNVTn1~CNVTn0 bits in the
CPnC register.
Comparator Registers
There are four registers for overall comparator operation, two registers, CPnC and CPnVOS, for
each comparator. As corresponding bits in these registers have identical functions, the following
register table applies to the registers.
Bit
Register
Name
7
6
5
4
3
2
1
0
CPnC
—
CnEN
CnPOL
CnOUT
CNVTn1
CNVTn0
—
—
CPnVOS
—
CnOFM
CnRSP
CnOF4
CnOF3
CnOF2
CnOF1
CnOF0
Comparator Registers List (n=0~1)
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CPnC Register
Bit
7
6
5
4
3
2
1
0
Name
—
CnEN
CnPOL
CnOUT
CNVTn1
CNVTn0
—
—
R/W
—
R/W
R/W
R
R/W
R/W
—
—
POR
—
0
0
0
0
0
—
—
Bit 7
Unimplemented, read as "0"
Bit 6CnEN: Comparator enable control
0: Disable
1: Enable
This bit is used to enable the comparator function. If this bit is cleared to zero, the
comparator will be switched off and no power consumed even if analog voltages are
applied to its inputs. When the comparator function is disabled, the comparator output
will be set to zero.
Bit 5CnPOL: Comparator output polarity selection
0: Output not inverted
1: Output inverted
If this bit is cleared to zero, the CnOUT bit will reflect the non-inverted output
condition of the comparator. If this bit is set high, the CnOUT bit will be inverted.
Bit 4CnOUT: Comparator output bit
CnPOL=0
0: Cn+ < Cn–
1: Cn+ > Cn–
CnPOL=1
0: Cn+ > Cn–
1: Cn+ < Cn–
This bit is used to store the comparator output bit. The polarity of this bit is determined
by the voltages on the comparator inputs and by the condition of the CnPOL bit.
Bit 3~2CNVTn1~CNVTn0: Comparator response time selection
00: Response time 0 (max.)
01: Response time 1
10: Response time 2
11: Response time 3 (min.)
These bits are used to select the comparator response time. The detailed response time
specifications are listed in the Comparator Characteristics.
Bit 1~0
Unimplemented, read as "0"
CPnVOS Register
Bit
7
6
5
4
3
2
1
0
Name
—
CnOFM
CnRSP
CnOF4
CnOF3
CnOF2
CnOF1
CnOF0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as "0"
Bit 6CnOFM: Comparator normal operation or input offset calibration mode selection
0: Normal operation mode
1: Input offset calibration mode
This bit is used to enable the comparator input offset calibration function. Refer to the
"Input Offset Calibration" section for the detailed input offset calibration procedures.
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Bit 5CnRSP: Comparator input offset calibration reference input selection
0: Cn– is selected as reference input
1: Cn+ is selected as reference input
Bit 4~0CnOF4~CnOF0: Comparator input offset calibration value
This 5-bit field is used to perform the comparator input offset calibration operation and
the value after the input offset calibration can be restored into this bit field. Refer to
the "Input Offset Calibration" section for more detailed information.
Input Offset Calibration
To operate in the input offset calibration mode, the comparator input pins to be used should first be
selected by properly configuring the corresponding pin-shared function selection bits followed by
setting the CnOFM bit high. The procedure is described in the following.
Step 1. Set CnOFM=1 to enable the comparator input offset calibration mode.
Step 2. Set CnOF [4:0]=00000 and read the CnOUT bit.
Step 3. Increase the CnOF [4:0] value by 1 and then read the CnOUT bit.
If the CnOUT bit state does not changed, then repeat Step 3 until the CnOUT bit state
changes.
If the CnOUT bit state changes, record the CnOF field value as VCnOS1 and then go to Step 4.
Step 4. Set CnOF [4:0]=11111 and read the CnOUT bit.
Step 5. Decrease the CnOF [4:0] value by 1 and then read the CnOUT bit.
If the CnOUT bit state does not changed, then repeat Step 5 until the CnOUT bit state
changes.
If the CnOUT bit state changes, record the CnOF field value as VCnOS2 and then go to Step 6.
Step 6. Restore the comparator input offset calibration value VCnOS into the CnOF [4:0] bit field.
The offset calibration procedure is now finished.
VCnOS1 + VCnOS2
Where VCnOS =
2
Comparator Interrupt
The comparator possesses its own interrupt function. When the comparator output changes state,
its relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump
to its relevant interrupt vector will be executed. Note that it is the changing state of the CnOUT bit
and not the output pin which generates an interrupt. If the microcontroller is in the SLEEP or IDLE
Mode and the Comparator is enabled, then if the external input lines cause the Comparator output to
change state, the resulting generated interrupt flag will also generate a wake-up. If it is required to
disable a wake-up from occurring, then the interrupt flag should be first set high before entering the
SLEEP or IDLE Mode.
Programming Considerations
If the comparator is enabled, it will remain active when the microcontroller enters the SLEEP or
IDLE Mode, however as it will consume a certain amount of power, the user may wish to consider
disabling it before the SLEEP or IDLE Mode is entered. As comparator pins are shared with normal
I/O pins the I/O data bits for these pins will be read as zero regardless of the port control register bit
value due to normal I/O path being switched off if the comparator function is enabled.
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Software Controlled LCD Driver
The devices have the capability of driving external LCD panels. The common pins,
SCOM0~SCOM3, for LCD driving are pin-shared with certain pins on the I/O ports. The LCD
signals (COM) are generated using the application program.
LCD Operation
An external LCD panel can be driven using the devices by configuring the I/O pins as common
pins. The LCD driver function is controlled using the LCD control registers which in addition to
controlling the overall on/off function also controls the R-type bias current on the SCOMn pins. This
enables the LCD COM driver to generate the necessary voltage levels, VSS, VDD/2 and VDD, for LCD
1/2 bias operation.
The SCOMEN bit in the SCOMC register is the overall master control for the LCD driver. The
SCOMn pin is selected to be used for LCD driving by the corresponding pin-shared function
selection bits. Note that the corresponding Port Control register does not need to first setup the pins
as outputs to enable the LCD driver operation.
VDD
VDD/2
SCOM0n
Pin-shared
Selection
ISEL[1:0]
LCDEN
Software Controlled LCD Driver Structure
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LCD Bias Current Control
The LCD COM driver enables a range of selections to be provided to suit the requirement of the
LCD panel which is being used. The bias current choice is implemented using the ISEL1 and ISEL0
bits in the SCOMC register. All COM pins are pin-shared with I/O pins and selected as SCOM pins
using the corresponding pin-shared function selection bits.
SCOMC Register
Bit
7
6
5
4
3
2
1
0
Name
—
ISEL1
ISEL0
SCOMEN
—
—
—
—
R/W
—
R/W
R/W
R/W
—
—
—
—
POR
—
0
0
0
—
—
—
—
Bit 7
Unimplemented, read as "0"
Bit 6~5ISEL1~ISEL0: SCOM typical bias current selection (@VDD=5V)
00: 25μA
01: 50μA
10: 100μA
11: 200μA
Bit 4SCOMEN: Software controlled LCD Driver enable control
0: Disable
1: Enable
The SCOMn lines can be enabled using the corresponding pin-shared selection bits if
the SCOMEN bit is set to 1. When the SCOMEN bit is cleared to 0, then the SCOMn
outputs will be fixed at a VDD level. Note that the corresponding pin-shared selection
bits should first be properly configured before the SCOMn function is enabled.
Bit 3~0
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16-bit Multiplication Division Unit – MDU
The devices each has a 16-bit Multiplication Division Unit, MDU, which integrates a 16-bit
unsigned multiplier and a 32-bit/16-bit divider. The MDU, in replacing the software multiplication
and division operations, can therefore save large amounts of computing time as well as the Program
and Data Memory space. It also reduces the overall microcontroller loading and results in the overall
system performance improvements.
fSYS
MDUWR0
MDUWR1
MDUWR2
MDUWR3
16/32-bit Dividend
/
16-bit Multiplicand
MDWEF
+/-
MDWOV
Shift Control
16-bit Divisor
/
16-bit Multiplier
MDUWR4
MDUWR5
16-Bit MDU Block Diagram
MDU Registers
The multiplication and division operations are implemented in a specific way, a specific write
access sequence of a series of MDU data registers. The status register, MDUWCTRL, provides the
indications for the MDU operation. The data register each is used to store the data regarded as the
different operand corresponding to different MDU operations.
Bit
Register
Name
7
6
5
4
3
2
1
0
MDUWR0
D7
D6
D5
D4
D3
D2
D1
D0
MDUWR1
D7
D6
D5
D4
D3
D2
D1
D0
MDUWR2
D7
D6
D5
D4
D3
D2
D1
D0
MDUWR3
D7
D6
D5
D4
D3
D2
D1
D0
MDUWR4
D7
D6
D5
D4
D3
D2
D1
D0
MDUWR5
D7
D6
D5
D4
D3
D2
D1
D0
—
—
—
—
—
—
MDUWCTRL MDWEF MDWOV
MDU Registers List
MDUWRn Register (n=0~5)
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
"x": unknown
Bit 7~0D7~D0: 16-bit MDU data register n
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MDUWCTRL Register
Bit
7
6
5
4
3
2
1
0
Name
MDWEF
MDWOV
—
—
—
—
—
—
R/W
R
R
—
—
—
—
—
—
POR
0
0
—
—
—
—
—
—
Bit 7MDWEF: 16-bit MDU error flag
0: Normal
1: Abnormal
This bit will be set to 1 if the data register MDUWRn is written or read as the MDU
operation is executing. This bit should be cleared to 0 by reading the MDUWCTRL
register if it is equal to 1 and the MDU operation is completed.
Bit 6MDWOV: 16-bit MDU overflow flag
0: No overflow occurs
1: Multiplication product > FFFFH or Divisor=0
When an operation is completed, this bit will be updated by hardware to a new value
corresponding to the current operation situation.
Bit 5~0
Unimplemented, read as "0"
MDU Operation
For this MDU the multiplication or division operation is carried out in a specific way and is
determined by the write access sequence of the six MDU data registers, MDUWR0~MDUWR5. The
low byte data, regardless of the dividend, multiplicand, divisor or multiplier, must first be written
into the corresponding MDU data register followed by the high byte data. All MDU operations
will be executed after the MDUWR5 register is write-accessed together with the correct specific
write access sequence of the MDUWRn. Note that it is not necessary to consecutively write data
into the MDU data registers but must be in a correct write access sequence. Therefore, a non-write
MDUWRn instruction or an interrupt, etc., can be inserted into the correct write access sequence
without destroying the write operation. The relationship between the write access sequence and the
MDU operation is shown in the following.
• 32-bit/16-bit division operation: Write data sequentially into the six MDU data registers from
MDUWR0 to MDUWR5.
• 16-bit/16-bit division operation: Write data sequentially into the specific four MDU data registers
in a sequence of MDUWR0, MDUWR1, MDUWR4 and MDUWR5 with no write access to
MDUWR2 and MDUWR3.
• 16-bit/16-bit multiplication operation: Write data sequentially into the specific four MDU data
register in a sequence of MDUWR0, MDUWR4, MDUWR1 and MDUWR5 with no write access
to MDUWR2 and MDUWR3.
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After the specific write access sequence is determined, the MDU will start to perform the
corresponding operation. The calculation time necessary for these MDU operations are different.
During the calculation time any read/write access to the six MDU data registers is forbidden. After
the completion of each operation, it is necessary to check the operation status in the MDUWCTRL
register to make sure that whether the operation is correct or not. Then the operation result can
be read out from the corresponding MDU data registers in a specific read access sequence if the
operation is correctly finished. The necessary calculation time for different MDU operations is listed
in the following.
• 32-bit/16-bit division operation: 17× tSYS.
• 16-bit/16-bit division operation: 9× tSYS.
• 16-bit/16-bit multiplication operation: 11× tSYS.
The operation results will be stored in the corresponding MDU data registers and should be read
out from the MDU data registers in a specific read access sequence after the operation is completed.
Noe that it is not necessary to consecutively read data out from the MDU data registers but must be
in a correct read access sequence. Therefore, a non-read MDUWRn instruction or an interrupt, etc.,
can be inserted into the correct read access sequence without destroying the read operation. The
relationship between the operation result read access sequence and the MDU operation is shown in
the following.
• 32-bit/16-bit division operation: Read the quotient from MDUWR0 to MDUWR3 and remainder
from MDUWR4 and MDUWR5 sequentially.
• 16-bit/16-bit division operation: Read the quotient from MDUWR0 and MDUWR1 and
remainder from MDUWR4 and MDUWR5 sequentially.
• 16-bit/16-bit multiplication operation: Read the product sequentially from MDUWR0 to
MDUWR3.
The overall important points for the MDU read/write access sequence and calculation time are
summarized in the following table.
Items
Operations
Write Sequence
First write
↓
↓
↓
↓
Last write
32-bit / 16-bit Division
16-bit / 16-bit Division
Dividend Byte 0 written to MDUWR0
Dividend Byte 1 written to MDUWR1
Dividend Byte 2 written to MDUWR2
Dividend Byte 3 written to MDUWR3
Divisor Byte 0 written to MDUWR4
Divisor Byte 1 written to MDUWR5
Dividend Byte 0 written to MDUWR0
Dividend Byte 1 written to MDUWR1
Divisor Byte 0 written to MDUWR4
Divisor Byte 1 written to MDUWR5
Calculation Time
17 × tSYS
9 × tSYS
Read Sequence
First read
↓
↓
↓
↓
Last read
Quotient Byte 0 read from MDUWR0
Quotient Byte 1 read from MDUWR1
Quotient Byte 2 read from MDUWR2
Quotient Byte 3 read from MDUWR3
Remainder Byte 0 read from MDUWR4
Remainder Byte 1 read from MDUWR5
Quotient Byte 0 read from MDUWR0
Quotient Byte 1 read from MDUWR1
Remainder Byte 0 read from MDUWR4
Remainder Byte 1 read from MDUWR5
16-bit × 16-bit Multiplication
Multiplicand Byte 0 written to MDUWR0
Multiplier Byte 0 written to MDUWR4
Multiplicand Byte 1 written to MDUWR1
Multiplier Byte 1 written to MDUWR5
11 × tSYS
Product Byte 0 read from MDUWR0
Product Byte 1 read from MDUWR1
Product Byte 2 read from MDUWR2
Product Byte 3 read from MDUWR3
MDU Operations Summary
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Cyclic Redundancy Check – CRC
The Cyclic Redundancy Check, CRC, calculation unit is an error detection technique test algorithm
and uses to verify data transmission or storage data correctness. A CRC calculation takes a data
stream or a block of data as input and generates a 16-bit output remainder. Ordinarily, a data stream
is suffixed by a CRC code and used as a checksum when being sent or stored. Therefore, the
received or restored data stream is calculated by the same generator polynomial as described in the
following section.
POLY
CCITT-1�
POLY
CRCIN
CRCDL
CRCDH
CRC-1�
POLY
CRC Block Diagram
CRC Registers
The CRC generator contains an 8-bit CRC data input register, CRCIN, and a CRC checksum
register pair, CRCDH and CRCDL. The CRCIN register is used to input new data and the CRCDH
and CRCDL registers are used to hold the previous CRC calculation result. A CRC control register,
CRCCR, is used to select which CRC generating polynomial is used.
Bit
Register
Name
7
6
5
4
3
2
1
0
CRCIN
D7
D6
D5
D4
D3
D2
D1
D0
CRCDL
D7
D6
D5
D4
D3
D2
D1
D0
CRCDH
D7
D6
D5
D4
D3
D2
D1
D0
CRCCR
—
—
—
—
—
—
—
POLY
CRC Registers List
CRCIN Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: CRC input data register
CRCDL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: 16-bit CRC checksum low byte data register
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CRCDH Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0D7~D0: 16-bit CRC checksum high byte data register
CRCCR Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
POLY
R/W
—
—
—
—
—
—
—
R/W
POR
—
—
—
—
—
—
—
0
Bit 7~1
Unimplemented, read as "0"
Bit 0POLY: 16-bit CRC generating polynomial selection
0: CRC-CCITT: X16 + X12 + X5 + 1
1: CRC-16: X16 + X15 + X2 + 1
CRC Operation
The CRC generator provides the 16-bit CRC result calculation based on the CRC16 and CCITT CRC16
polynomials. In this CRC generator, there are only these two polynomials available for the numeric
values calculation. It can not support the 16-bit CRC calculations based on any other polynomials.
The following two expressions can be used for the CRC generating polynomial which is determined
using the POLY bit in the CRC control register, CRCCR. The CRC calculation result is called as the
CRC checksum, CRCSUM, and stored in the CRC checksum register pair, CRCDH and CRCDL.
• CRC-CCITT: X16 + X12 + X5 + 1.
• CRC-16: X16 + X15 + X2 + 1.
CRC Computation
Each write operation to the CRCIN register creates a combination of the previous CRC value stored
in the CRCDH and CRCDL registers and the new data input. The CRC unit calculates the CRC data
register value is based on byte by byte. It will take one MCU instruction cycle to calculate the CRC
checksum.
• CRC Calculation Procedures:
1. Clear the checksum register pair, CRCDH and CRCDL.
2. Execute an "Exclusive OR" operation with the 8-bit input data byte and the 16-bit CRCSUM high
byte. The result is called the temporary CRCSUM.
3. Shift the temporary CRCSUM value left by one bit and move a "0" into the LSB.
4. Check the shifted temporary CRCSUM value after procedure 3.
If the MSB is 0, then this shifted temporary CRCSUM will be considered as a new temporary CRCSUM.
Otherwise, execute an "Exclusive OR" operation with the shifted temporary CRCSUM in procedure
3 and a data "8005H". Then the operation result will be regarded as the new temporary CRCSUM.
Note that the data to be perform an "Exclusive OR" operation is "8005H" for the CRC-16
polynomial while for the CRC-CCITT polynomial the data is "1021H".
5. Repeat the procedure 3 ~ procedure 4 until all bits of the input data byte are completely calculated.
6. Repeat the procedure 2~ procedure 5 until all of the input data bytes are completely calculated.
Then, the latest calculated result is the final CRC checksum, CRCSUM.
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• CRC Calculation Examples:
• Write 1 byte input data into the CRCIN register and the corresponding CRC checksum are
individually calculated as the following table shown.
CRC Data Input
CRC Polynomial
00H
01H
02H
03H
04H
05H
06H
07H
CRC-CCITT (X16+X12+X5+1)
0000H 1021H 2042H 3063H 4084H 50A5H 60C6H 70E7H
CRC-16 (X16+X15+X2+1)
0000H 8005H 800FH 000AH 801BH 001EH 0014H 8011H
Note: The initial value of the CRC checksum register pair, CRCDH and CRCDL, is zero before
each CRC input data is written into the CRCIN register.
• Write 4 bytes input data into the CRCIN register sequentially and the CRC checksum are
sequentially listed in the following table.
CRC Data Input
CRC Polynomial
CRC-CCITT (X16+X12+X5+1)
CRC-16 (X16+X15+X2+1)
CRCIN=78H→56H→34H→12H
(CRCDH, CRCDL)=FF9FH→BBC3H→A367H→D0FAH
(CRCDH, CRCDL)=0110h→91F1h→F2DEh→5C43h
Note: The initial value of the CRC checksum register pair, CRCDH and CRCDL, is zero before
the sequential CRC data input operation.
• Program Memory CRC Checksum Calculation Example:
1. Clear the checksum register pair, CRCDH and CRCDL.
2. Select the CRC-CCITT or CRC-16 polynomial as the generating polynomial using the POLY bit
in the CRCCR register.
3. Execute the table read instruction to read the program memory data value.
4. Write the table data low byte into the CRCIN register and execute the CRC calculation with the
current CRCSUM value. Then a new CRCSUM result will be obtained and stored in the CRC
checksum register pair, CRCDH and CRCDL.
5. Write the table data high byte into the CRCIN register and execute the CRC calculation with the
current CRCSUM value. Then a new CRCSUM result will be obtained and stored in the CRC
checksum register pair, CRCDH and CRCDL.
6. Repeat the procedure 3 ~ procedure 5 to read the next program memory data value and execute
the CRC calculation until all program memory data are read followed by the sequential CRC
calculation. Then the value in the CRC checksum register pair is the final CRC calculation result.
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Low Voltage Detector – LVD
Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to
monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain
level. This function may be especially useful in battery applications where the supply voltage will
gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated.
The Low Voltage Detector also has the capability of generating an interrupt signal.
LVD Register
The Low Voltage Detector function is controlled using a single register with the name LVDC. Three
bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which
a low voltage condition will be determined. A low voltage condition is indicated when the LVDO
bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage
value. The LVDEN bit is used to control the overall on/off function of the low voltage detector.
Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the
internal low voltage detector circuits. As the low voltage detector will consume a certain amount of
power, it may be desirable to switch off the circuit when not in use, an important consideration in
power sensitive battery powered applications.
LVDC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
LVDO
LVDEN
VBGEN
VLVD2
VLVD1
VLVD0
R/W
—
—
R
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Unimplemented, read as "0"
Bit 5LVDO: LVD output flag
0: No Low Voltage Detected
1: Low Voltage Detected
Bit 4LVDEN: Low Voltage Detector Enable control
0: Disable
1: Enable
Bit 3VBGEN: Bandgap Voltage Output Enable control
0: Disable
1: Enable
Bit 2~0VLVD2~VLVD0: LVD Voltage selection
000: 2.0V
001: 2.2V
010: 2.4V
011: 2.7V
100: 3.0V
101: 3.3V
110: 3.6V
111: 4.0V
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LVD Operation
The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a
pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V.
When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be
set high indicating a low power supply voltage condition. The Low Voltage Detector function is
supplied by a reference voltage which will be automatically enabled. When the device enters the
SLEEP Mode, the low voltage detector will automatically be disabled even if the LVDEN bit is
high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry
to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather
slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions.
VDD
VLVD
LVDEN
LVDO
tLVDS
LVD Operation
The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling
the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been
set high by a low voltage condition. When the device is powered down the Low Voltage Detector
will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set,
causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the
device to wake-up from the IDLE Mode, however if the Low Voltage Detector wake up function is
not required then the LVF flag should be first set high before the device enters the IDLE Mode.
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an
internal function such as a Timer Module or an A/D converter requires microcontroller attention,
their corresponding interrupt will enforce a temporary suspension of the main program allowing the
microcontroller to direct attention to their respective needs. These devices contain several external
interrupt and internal interrupts functions. The external interrupts are generated by the action of the
external INT0 ~ INT3 pins, while the internal interrupts are generated by various internal functions
such as the TMs, Time Base, LVD, EEPROM, SIM, UART and the A/D converter, etc.
Interrupt Registers
Overall interrupt control, which basically means the setting of request flags when certain
microcontroller conditions occur and the setting of interrupt enable bits by the application program,
is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the
accompanying table. The number of registers depends upon the device chosen but fall into three
categories. The first is the INTC0~INTC3 registers which setup the primary interrupts, the second
is the MFI0~MFI5 registers which setup the Multi-function interrupts. Finally there is an INTEG
register to setup the external interrupt trigger edge type.
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Each register contains a number of enable bits to enable or disable individual interrupts as well
as interrupt flags to indicate the presence of an interrupt request. The naming convention of these
follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of
that interrupt followed by either an "E" for enable/disable bit or "F" for request flag.
Function
Enable Bit
Request Flag
EMI
—
—
INTn Pins
INTnE
INTnF
n=0 ~ 3
Comparator
CPnE
CPnF
n=0 ~ 1
A/D Converter
ADE
ADF
—
Time Base
TBnE
TBnF
n=0 ~ 1
Multi-function
MFnE
MFnF
n=0 ~ 5
URnF
n=0 ~ 1 (HT66F2350/60)
n=0 ~ 2 (HT66F2370/90)
Global
UART
URnE
Notes
LVD
LVE
LVF
—
EEPROM write operation
DEE
DEF
—
SIM
SIME
SIMF
—
SPIA
SPIAE
SPIAF
—
PTMnPE
PTMnPF
PTMnAE
PTMnAF
PTM
STM
STMnPE
STMnPF
STMnAE
STMnAF
n=0 ~ 3
n=0 ~ 2
Interrupt Register Bit Naming Conventions
Register Name
INTEG
Bit
7
6
5
4
3
2
1
0
INT3S1
INT3S0
INT2S1
INT2S0
INT1S1
INT1S0
INT0S1
INT0S0
INTC0
—
CP0F
INT1F
INT0F
CP0E
INT1E
INT0E
EMI
INTC1
ADF
MF1F
MF0F
CP1F
ADE
MF1E
MF0E
CP1E
INTC2
MF3F
TB1F
TB0F
MF2F
MF3E
TB1E
TB0E
MF2E
INTC3
MF5F
MF4F
INT3F
INT2F
MF5E
MF4E
INT3E
INT2E
MFI0
STM0AF STM0PF PTM0AF PTM0PF STM0AE STM0PE PTM0AE PTM0PE
MFI1
STM1AF STM1PF PTM1AF PTM1PF STM1AE STM1PE PTM1AE PTM1PE
MFI2
—
—
MFI3
SIMF
SPIAF
MFI4
MFI5
(HT66F2350/60)
MFI5
(HT66F2370/90)
PTM2AF PTM2PF
DEF
LVF
—
—
SIME
SPIAE
PTM2AE PTM2PE
DEE
LVE
STM2AF STM2PF PTM3AF PTM3PF STM2AE STM2PE PTM3AE PTM3PE
—
—
UR1F
UR0F
—
—
UR1E
UR0E
—
UR2F
UR1F
UR0F
—
UR2E
UR1E
UR0E
Interrupt Registers List
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INTEG Register
Bit
7
6
5
4
3
2
1
0
Name
INT3S1
INT3S0
INT2S1
INT2S0
INT1S1
INT1S0
INT0S1
INT0S0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6INT3S1~INT3S0: Interrupt edge control for INT3 pin
00: Disable
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 5~4INT2S1~INT2S0: Interrupt edge control for INT2 pin
00: Disable
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 3~2INT1S1~INT1S0: Interrupt edge control for INT1 pin
00: Disable
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 1~0INT0S1~INT0S0: Interrupt edge control for INT0 pin
00: Disable
01: Rising edge
10: Falling edge
11: Rising and falling edges
INTC0 Register
Bit
7
6
5
4
3
2
1
0
Name
—
CP0F
INT1F
INT0F
CP0E
INT1E
INT0E
EMI
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as "0"
Bit 6CP0F: Comparator 0 interrupt request flag
0: No Request
1: Interrupt Request
Bit 5INT1F: INT1 interrupt request flag
0: No Request
1: Interrupt Request
Bit 4INT0F: INT0 interrupt request flag
0: No Request
1: Interrupt Request
Bit 3CP0E: Comparator 0 interrupt control
0: Disable
1: Enable
Bit 2INT1E: INT1 interrupt control
0: Disable
1: Enable
Bit 1INT0E: INT0 interrupt control
0: Disable
1: Enable
Bit 0EMI: Global interrupt control
0: Disable
1: Enable
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INTC1 Register
Bit
7
6
5
4
3
2
1
0
Name
ADF
MF1F
MF0F
CP1F
ADE
MF1E
MF0E
CP1E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7ADF: A/D Converter interrupt request flag
0: No Request
1: Interrupt Request
Bit 6MF1F: Multi-function 1 interrupt request flag
0: No Request
1: Interrupt Request
Bit 5MF0F: Multi-function 0 interrupt request flag
0: No Request
1: Interrupt Request
Bit 4CP1F: Comparator 1 interrupt request flag
0: No Request
1: Interrupt Request
Bit 3ADE: A/D Converter interrupt control
0: Disable
1: Enable
Bit 2MF1E: Multi-function 1 interrupt control
0: Disable
1: Enable
Bit 1MF0E: Multi-function 0 interrupt control
0: Disable
1: Enable
Bit 0CP1E: Comparator 1 interrupt control
0: Disable
1: Enable
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INTC2 Register
Bit
7
6
5
4
3
2
1
0
Name
MF3F
TB1F
TB0F
MF2F
MF3E
TB1E
TB0E
MF2E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7MF3F: Multi-function 3 interrupt request flag
0: No Request
1: Interrupt Request
Bit 6TB1F: Time Base 1 interrupt request flag
0: No Request
1: Interrupt Request
Bit 5TB0F: Time Base 0 interrupt request flag
0: No Request
1: Interrupt Request
Bit 4MF2F: Multi-function 2 interrupt request flag
0: No Request
1: Interrupt Request
Bit 3MF3E: Multi-function 3 interrupt control
0: Disable
1: Enable
Bit 2TB1E: Time Base 1 interrupt control
0: Disable
1: Enable
Bit 1TB0E: Time Base 0 interrupt control
0: Disable
1: Enable
Bit 0MF2E: Multi-function 2 interrupt control
0: Disable
1: Enable
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INTC3 Register
Bit
7
6
5
4
3
2
1
0
Name
MF5F
MF4F
INT3F
INT2F
MF5E
MF4E
INT3E
INT2E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7MF5F: Multi-function 5 interrupt request flag
0: No Request
1: Interrupt Request
Bit 6MF4F: Multi-function 4 interrupt request flag
0: No Request
1: Interrupt Request
Bit 5INT3F: INT3 interrupt request flag
0: No Request
1: Interrupt Request
Bit 4INT2F: INT2 interrupt request flag
0: No Request
1: Interrupt Request
Bit 3MF5E: Multi-function 5 interrupt control
0: Disable
1: Enable
Bit 2MF4E: Multi-function 4 interrupt control
0: Disable
1: Enable
Bit 1INT3E: INT3 interrupt control
0: Disable
1: Enable
Bit 0INT2E: INT2 interrupt control
0: Disable
1: Enable
Rev. 1.00
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
MFI0 Register
Bit
7
6
5
4
3
2
1
0
Name
STM0AF
STM0PF
PTM0AF
PTM0PF
STM0AE
STM0PE
PTM0AE
PTM0PE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7STM0AF: STM0 Comparator A match Interrupt request flag
0: No Request
1: Interrupt Request
Bit 6STM0PF: STM0 Comparator P match Interrupt request flag
0: No Request
1: Interrupt Request
Bit 5PTM0AF: PTM0 Comparator A match Interrupt request flag
0: No Request
1: Interrupt Request
Bit 4PTM0PF: PTM0 Comparator P match Interrupt request flag
0: No Request
1: Interrupt Request
Bit 3STM0AE: STM0 Comparator A match Interrupt control
0: Disable
1: Enable
Bit 2STM0PE: STM0 Comparator P match Interrupt control
0: Disable
1: Enable
Bit 1PTM0AE: PTM0 Comparator A match Interrupt control
0: Disable
1: Enable
Bit 0PTM0PE: PTM0 Comparator P match Interrupt control
0: Disable
1: Enable
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
MFI1 Register
Bit
7
6
5
4
3
2
1
0
Name
STM1AF
STM1PF
PTM1AF
PTM1PF
STM1AE
STM1PE
PTM1AE
PTM1PE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7STM1AF: STM1 Comparator A match Interrupt request flag
0: No Request
1: Interrupt Request
Bit 6STM1PF: STM1 Comparator P match Interrupt request flag
0: No Request
1: Interrupt Request
Bit 5PTM1AF: PTM1 Comparator A match Interrupt request flag
0: No Request
1: Interrupt Request
Bit 4PTM1PF: PTM1 Comparator P match Interrupt request flag
0: No Request
1: Interrupt Request
Bit 3STM1AE: STM1 Comparator A match Interrupt control
0: Disable
1: Enable
Bit 2STM1PE: STM1 Comparator P match Interrupt control
0: Disable
1: Enable
Bit 1PTM1AE: PTM1 Comparator A match Interrupt control
0: Disable
1: Enable
Bit 0PTM1PE: PTM1 Comparator P match Interrupt control
0: Disable
1: Enable
MFI2 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
PTM2AF
PTM2PF
—
—
PTM2AE
PTM2PE
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
Unimplemented, read as "0"
Bit 5PTM2AF: PTM2 Comparator A match Interrupt request flag
0: No Request
1: Interrupt Request
Bit 4PTM2PF: PTM2 Comparator P match Interrupt request flag
0: No Request
1: Interrupt Request
Bit 3~2
Unimplemented, read as "0"
Bit 1PTM2AE: PTM2 Comparator A match Interrupt control
0: Disable
1: Enable
Bit 0PTM2PE: PTM2 Comparator P match Interrupt control
0: Disable
1: Enable
Rev. 1.00
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
MFI3 Register
Bit
7
6
5
4
3
2
1
0
Name
SIMF
SPIAF
DEF
LVF
SIME
SPIAE
DEE
LVE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7SIMF: SIM Interrupt request flag
0: No Request
1: Interrupt Request
Bit 6SPIAF: SPIA Interrupt request flag
0: No Request
1: Interrupt Request
Bit 5DEF: Data EEPROM Interrupt request flag
0: No Request
1: Interrupt Request
Bit 4LVF: LVD Interrupt request flag
0: No Request
1: Interrupt Request
Bit 3SIME: SIM Interrupt control
0: Disable
1: Enable
Bit 2SPIAE: SPIA Interrupt control
0: Disable
1: Enable
Bit 1DEE: Data EEPROM Interrupt control
0: Disable
1: Enable
Bit 0LVE: LVD Interrupt control
0: Disable
1: Enable
Rev. 1.00
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
MFI4 Register
Bit
7
6
5
4
3
2
1
0
Name
STM2AF
STM2PF
PTM3AF
PTM3PF
STM2AE
STM2PE
PTM3AE
PTM3PE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7STM2AF: STM2 Comparator A match Interrupt request flag
0: No Request
1: Interrupt Request
Bit 6STM2PF: STM2 Comparator P match Interrupt request flag
0: No Request
1: Interrupt Request
Bit 5PTM3AF: PTM3 Comparator A match Interrupt request flag
0: No Request
1: Interrupt Request
Bit 4PTM3PF: PTM3 Comparator P match Interrupt request flag
0: No Request
1: Interrupt Request
Bit 3STM2AE: STM2 Comparator A match Interrupt control
0: Disable
1: Enable
Bit 2STM2PE: STM2 Comparator P match Interrupt control
0: Disable
1: Enable
Bit 1PTM3AE: PTM3 Comparator A match Interrupt control
0: Disable
1: Enable
Bit 0PTM3PE: PTM3 Comparator P match Interrupt control
0: Disable
1: Enable
Rev. 1.00
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HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
MFI5 Register – HT66F2350/HT66F2360
Bit
7
6
5
4
3
2
1
0
Name
—
—
UR1F
UR0F
—
—
UR1E
UR0E
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
Unimplemented, read as "0"
Bit 5UR1F: UART1 transfer interrupt request flag
0: No Request
1: Interrupt Request
Bit 4UR0F: UART0 transfer interrupt request flag
0: No Request
1: Interrupt Request
Bit 3~2
Unimplemented, read as "0"
Bit 1UR1E: UART1 transfer interrupt control
0: Disable
1: Enable
Bit 0UR0E: UART0 transfer interrupt control
0: Disable
1: Enable
MFI5 Register – HT66F2370/HT66F2390
Bit
7
6
5
4
3
2
1
0
Name
—
UR2F
UR1F
UR0F
—
UR2E
UR1E
UR0E
R/W
—
R/W
R/W
R/W
—
R/W
R/W
R/W
POR
—
0
0
0
—
0
0
0
Bit 7
Unimplemented, read as "0"
Bit 6UR2F: UART2 transfer interrupt request flag
0: no request
1: interrupt request
Bit 5UR1F: UART1 transfer interrupt request flag
0: No Request
1: Interrupt Request
Bit 4UR0F: UART0 transfer interrupt request flag
0: No Request
1: Interrupt Request
Bit 3
Unimplemented, read as "0"
Bit 2UR2E: UART2 transfer interrupt control
0: Disable
1: Enable
Bit 1UR1E: UART1 transfer interrupt control
0: Disable
1: Enable
Bit 0UR0E: UART0 transfer interrupt control
0: Disable
1: Enable
Rev. 1.00
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Interrupt Operation
When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A or A/D
conversion completion, etc, the relevant interrupt request flag will be set. Whether the request flag
actually generates a program jump to the relevant interrupt vector is determined by the condition of
the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector;
if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be
generated and the program will not jump to the relevant interrupt vector. The global interrupt enable
bit, if cleared to zero, will disable all interrupts.
When an interrupt is generated, the Program Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller will
then fetch its next instruction from this interrupt vector. The instruction at this vector will usually
be a JMP which will jump to another section of program which is known as the interrupt service
routine. Here is located the code to control the appropriate interrupt. The interrupt service routine
must be terminated with a RETI, which retrieves the original Program Counter address from the
stack and allows the microcontroller to continue with normal execution at the point where the
interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
accompanying diagrams with their order of priority. Some interrupt sources have their own
individual vector while others share the same multi-function interrupt vector. Once an interrupt
subroutine is serviced, all other interrupts will be blocked, as the global interrupt enable bit, EMI
bit will be cleared automatically. This will prevent any further interrupt nesting from occurring.
However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded.
Rev. 1.00
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
If an interrupt requires immediate servicing while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until
the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from
becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that
is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or
IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set
before the device is in SLEEP or IDLE Mode.
Legend
xxF
Request Flag� no auto �eset in ISR
xxF
Request Flag� auto �eset in ISR
xxE
Ena�le Bits
Inte��upts �ontained within
Multi-Fun�tion Inte��upts
EMI auto disa�led in ISR
Inte��upt
Na�e
Request
Flags
Ena�le
Bits
Maste�
Ena�le
INT0 Pin
INT0F
INT0E
EMI
INT1 Pin
INT1F
INT1E
EMI
08H
Co�p. 0
CP0F
CP0E
EMI
0CH
Co�p. 1
CP1F
CP1E
EMI
10H
M. Fun�t. 0
MF0F
MF0E
EMI
14H
M. Fun�t. 1
MF1F
MF1E
EMI
18H
A/D
ADF
ADE
EMI
1CH
Vector P�io�ity
High
04H
STM0 P
STM0PF
STM0PE
STM0 A
STM0AF
STM0AE
PTM0 P
PTM0PF
PTM0PE
PTM0 A
PTM0AF
PTM0AE
STM1 P
STM1PF
STM1PE
STM1 A
STM1AF
STM1AE
PTM1 P
PTM1PF
PTM1PE
PTM1 A
PTM1AF
PTM1AE
PTM� P
PTM�PF
PTM�PE
PTM� A
PTM�AF
PTM�AE
M. Fun�t. �
MF�F
MF�E
EMI
�0H
LVD
LVF
LVE
Ti�e Base 0
TB0F
TB0E
EMI
�4H
EEPROM
DEF
DEE
SPIA
SPIAF
SPIAE
Ti�e Base 1
TB1F
TB1E
EMI
�8H
SIM
SIMF
SIME
M. Fun�t. 3
MF3F
MF3E
EMI
�CH
STM� P
STM�PF
STM�PE
STM� A
STM�AF
STM�AE
INT� Pin
INT�F
INT�E
EMI
30H
PTM3 P
PTM3PF
PTM3PE
INT3 Pin
INT3F
INT3E
EMI
34H
PTM3 A
PTM3AF
PTM3AE
UART 0
UR0F
UR0E
M. Fun�t. 4
MF4F
MF4E
EMI
38H
UART 1
UR1F
UR1E
M. Fun�t. 5
MF5F
MF5E
EMI
3CH
Low
Interrupt Scheme – HT66F2350/HT66F2360
Rev. 1.00
221
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Legend
xxF
Request Flag, no auto reset in ISR
xxF
Request Flag, auto reset in ISR
xxE
Enable Bits
Interrupts contained within
Multi-Function Interrupts
EMI auto disabled in ISR
Interrupt
Name
Request
Flags
Enable
Bits
Master
Enable
INT0 Pin
INT0F
INT0E
EMI
04H
INT1 Pin
INT1F
INT1E
EMI
08H
Comp. 0
CP0F
CP0E
EMI
0CH
Comp. 1
CP1F
CP1E
EMI
10H
M. Funct. 0
MF0F
MF0E
EMI
14H
M. Funct. 1
MF1F
MF1E
EMI
18H
A/D
ADF
ADE
EMI
1CH
Vector Priority
STM0 P
STM0PF
STM0PE
STM0 A
STM0AF
STM0AE
PTM0 P
PTM0PF
PTM0PE
PTM0 A
PTM0AF
PTM0AE
STM1 P
STM1PF
STM1PE
STM1 A
STM1AF
STM1AE
PTM1 P
PTM1PF
PTM1PE
PTM1 A
PTM1AF
PTM1AE
PTM2 P
PTM2PF
PTM2PE
PTM2 A
PTM2AF
PTM2AE
M. Funct. 2
MF2F
MF2E
EMI
20H
Time Base 0
TB0F
TB0E
EMI
24H
Time Base 1
TB1F
TB1E
EMI
28H
M. Funct. 3
MF3F
MF3E
EMI
2CH
INT2 Pin
INT2F
INT2E
EMI
30H
INT3 Pin
INT3F
INT3E
EMI
34H
M. Funct. 4
MF4F
MF4E
EMI
38H
M. Funct. 5
MF5F
MF5E
EMI
3CH
LVD
LVF
LVE
EEPROM
DEF
DEE
SPIA
SPIAF
SPIAE
SIM
SIMF
SIME
STM2 P
STM2PF
STM2PE
STM2 A
STM2AF
STM2AE
PTM3 P
PTM3PF
PTM3PE
PTM3 A
PTM3AF
PTM3AE
UART 0
UR0F
UR0E
UART 1
UR1F
UR1E
UART 2
UR2F
UR2E
High
Low
Interrupt Scheme – HT66F2370/HT66F2390
Rev. 1.00
222
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HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
External Interrupt
The external interrupts are controlled by signal transitions on the pins INT0~INT3. An external
interrupt request will take place when the external interrupt request flags, INT0F~INT3F, are set,
which will occur when a transition, whose type is chosen by the edge select bits, appears on the
external interrupt pins. To allow the program to branch to its respective interrupt vector address,
the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT3E,
must first be set. Additionally the correct interrupt edge type must be selected using the INTEG
register to enable the external interrupt function and to choose the trigger edge type. As the external
interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if
their external interrupt enable bit in the corresponding interrupt register has been set and the external
interrupt pin is selected by the corresponding pin-shared function selection bits. The pin must also
be setup as an input by setting the corresponding bit in the port control register. When the interrupt
is enabled, the stack is not full and the correct transition type appears on the external interrupt pin,
a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the
external interrupt request flags, INT0F~INT3F, will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the
external interrupt pins will remain valid even if the pin is used as an external interrupt input.
The INTEG register is used to select the type of active edge that will trigger the external interrupt.
A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt.
Note that the INTEG register can also be used to disable the external interrupt function.
Comparator Interrupt
The comparator interrupt is controlled by the two internal comparators. A comparator interrupt
request will take place when the comparator interrupt request flags, CP0F or CP1F, are set, a
situation that will occur when the comparator output bit changes state. To allow the program to
branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and comparator
interrupt enable bit, CP0E or CP1E, must first be set. When the interrupt is enabled, the stack is
not full and the comparator inputs generate a comparator output transition, a subroutine call to the
comparator interrupt cector, will take place. When the interrupt is serviced, the comparator interrupt
request flag will be automatically reset and the EMI bit will also be automatically cleared to disable
other interrupts.
Multi-function Interrupt
Within the device there are up to five Multi-function interrupts. Unlike the other independent
interrupts, these interrupts have no independent source, but rather are formed from other existing
interrupt sources, namely the TM interrupts, LVD interrupt, EEPROM write operation interrupt,
SIM interface, SPIA interface and UART interface interrupts.
A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags
MFnF are set. The Multi-function interrupt flags will be set when any of their included functions generate
an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when
the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained
within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt
vectors will take place. When the interrupt is serviced, the related Multi-Function request flag will be
automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
However, it must be noted that, although the Multi-function Interrupt request flags will be
automatically reset when the interrupt is serviced, the request flags from the original source of
the Multi-function interrupts will not be automatically reset and must be manually reset by the
application program.
Rev. 1.00
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HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
A/D Converter Interrupt
The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D
Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is
set, which occurs when the A/D conversion process finishes. To allow the program to branch to its
respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit,
ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion
process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the
interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI
bit will also be automatically cleared to disable other interrupts.
Time Base Interrupt
The function of the Time Base Interrupt is to provide regular time signal in the form of an internal
interrupt. It is controlled by the overflow signal from its internal timer. When this happens its
interrupt request flag, TBnF, will be set. To allow the program to branch to its respective interrupt
vector addresses, the global interrupt enable bit, EMI and Time Base enable bit, TBnE, must first be
set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine
call to its respective vector location will take place. When the interrupt is serviced, the interrupt
request flag, TBnF, will be automatically reset and the EMI bit will be cleared to disable other
interrupts.
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its
clock source, fPSC0 or fPSC1, originates from the internal clock source fSYS, fSYS/4 or fSUB and then
passes through a divider, the division ratio of which is selected by programming the appropriate bits
in the TB0C and TB1C registers to obtain longer interrupt periods whose value ranges. The clock
source which in turn controls the Time Base interrupt period is selected using the CLKSEL0[1:0]
and CLKSEL1[1:0] bits in the PSC0R and PSC1R register respectively.
fSYS
fSYS/4
fSUB
M
U
X
fPSC0
TB0ON
fPSC0/28 ~ fPSC0/215
Prescaler 0
M
U
X
TB0[2:0]
CLKSEL0[1:0]
fSYS
fSYS/4
fSUB
M
U
X
fPSC1
Time Base 0 Interrupt
fPSC1/28 ~ fPSC1/215
Prescaler 1
M
U
X
TB1ON
CLKSEL1[1:0]
Time Base 1 Interrupt
TB1[2:0]
Time Base Interrupts
PSC0R Register
Bit
7
6
5
4
3
2
Name
—
—
—
—
—
—
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
1
0
CLKSEL01 CLKSEL00
Unimplemented, read as "0"
Bit 1~0CLKSEL01~CLKSEL00: Prescaler 0 clock source fPSC0 selection
00: fSYS
01: fSYS/4
1x: fSUB
Rev. 1.00
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HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
PSC1R Register
Bit
7
6
5
4
3
2
Name
—
—
—
—
—
—
1
0
CLKSEL11 CLKSEL10
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1~0CLKSEL11~CLKSEL10: Prescaler 1 clock source fPSC1 selection
00: fSYS
01: fSYS/4
1x: fSUB
TB0C Register
Bit
7
6
5
4
3
2
1
0
Name
TB0ON
—
—
—
—
TB02
TB01
TB00
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
0
0
0
Bit 7TB0ON: Time Base 0 Enable Control
0: Disable
1: Enable
Bit 6~3
Unimplemented, read as "0"
Bit 2~0TB02~TB00: Time Base 0 time-out period selection
000: 28/fPSC0
001: 29/fPSC0
010: 210/fPSC0
011: 211/fPSC0
100: 212/fPSC0
101: 213/fPSC0
110: 214/fPSC0
111: 215/fPSC0
TB1C Register
Bit
7
6
5
4
3
2
1
0
Name
TB1ON
—
—
—
—
TB12
TB11
TB10
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
0
0
0
Bit 7TB1ON: Time Base 1 Enable Control
0: Disable
1: Enable
Bit 6~3
Unimplemented, read as "0"
Bit 2~0TB12~TB10: Time Base 1 time-out period selection
000: 28/fPSC1
001: 29/fPSC1
010: 210/fPSC1
011: 211/fPSC1
100: 212/fPSC1
101: 213/fPSC1
110: 214/fPSC1
111: 215/fPSC1
Rev. 1.00
225
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HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
TM Interrupt
The Standard and Periodic TMs have two interrupts, one comes from the comparator A match
situation and the other comes from the comparator P match situation. All of the TM interrupts
are contained within the Multi-function Interrupts. For all of the TM types there are two interrupt
request flags and two enable control bits. A TM interrupt request will take place when any of the
TM request flags are set, a situation which occurs when a TM comparator P or A match situation
happens.
To allow the program to branch to its respective interrupt vector address, the global interrupt enable
bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE,
must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match
situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take
place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other
interrupts. However, only the related MFnF flag will be automatically cleared. As the TM interrupt
request flags will not be automatically cleared, they have to be cleared by the application program.
LVD Interrupt
The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD
Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs
when the Low Voltage Detector function detects a low power supply voltage. To allow the program
to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage
Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When
the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to
the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the
EMI bit will be automatically cleared to disable other interrupts. However, only the Multi-function
interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically
cleared, it has to be cleared by the application program.
EEPROM Interrupt
The EEPROM Write Interrupt is contained within the Multi-function Interrupt. An EEPROM
Write Interrupt request will take place when the EEPROM Write Interrupt request flag, DEF, is set,
which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective
interrupt vector address, the global interrupt enable bit, EMI, EEPROM Write Interrupt enable bit,
DEE, and associated Multi-function interrupt enable bit must first be set. When the interrupt is
enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective
Multi-function Interrupt vector will take place. When the EEPROM Write Interrupt is serviced, the
EMI bit will be automatically cleared to disable other interrupts. However, only the Multi-function
interrupt request flag will be automatically cleared. As the DEF flag will not be automatically
cleared, it has to be cleared by the application program.
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Serial Interface Module Interrupt
The Serial Interface Module Interrupt, also known as the SIM interrupt, is contained within the
Multi-function Interrupt. A SIM Interrupt request will take place when the SIM Interrupt request
flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM
interface, an I2C slave address match or I2C bus time-out occurrence. To allow the program to
branch to its respective interrupt vector address, the global interrupt enable bit, EMI, the Serial
Interface Interrupt enable bit, SIME, and Multi-function interrupt enable bit must first be set. When
the interrupt is enabled, the stack is not full and any of the above described situations occurs, a
subroutine call to the respective Multi-function Interrupt vector, will take place. When the Serial
Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts,
however only the Multi-function interrupt request flag will be also automatically cleared. As the
SIMF flag will not be automatically cleared, it has to be cleared by the application program.
SPIA Interface Interrupt
The SPIA Interface Module Interrupt is contained within the Multi-function Interrupt. A SPIA
Interrupt request will take place when the SPIA Interrupt request flag, SPIAF, is set, which occurs
when a byte of data has been received or transmitted by the SPIA interface. To allow the program
to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, the Serial
Interface Interrupt enable bit, SPIAE, and Multi-function interrupt enable bit must first be set. When
the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by
the SPIA interface, a subroutine call to the respective Multi-function Interrupt vector, will take place.
When the SPIA Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable
other interrupts. However, only the Multi-function interrupt request flag will be also automatically
cleared. As the SPIAF flag will not be automatically cleared, it has to be cleared by the application
program.
UART Transfer Interrupt
The UART Transfer Interrupt is controlled by several UARTn transfer conditions. When one of these
conditions occurs, an interrupt pulse will be generated to get the attention of the microcontroller.
These conditions are a transmitter data register empty, transmitter idle, receiver data available,
receiver overrun, address detect and an RXn pin wake-up. To allow the program to branch to its
respective interrupt vector address, the global interrupt enable bit, EMI, and UART Interrupt enable
bit, URnE, must first be set. When the interrupt is enabled, the stack is not full and any of the
conditions described above occurs, a subroutine call to the UARTn Interrupt vector, will take place.
When the interrupt is serviced, the UARTn Interrupt flag, URnF, will be automatically cleared. The
EMI bit will also be automatically cleared to disable other interrupts.
Interrupt Wake-up Function
Each of the interrupt functions has the capability of waking up the microcontroller when in the
SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low
to high and is independent of whether the interrupt is enabled or not. Therefore, even though these
devices are in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as
external edge transitions on the external interrupt pins, a low power supply voltage or comparator
input change may cause their respective interrupt flag to be set high and consequently generate
an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an
interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be
set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect
on the interrupt wake-up function.
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Programming Considerations
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being
serviced, however, once an interrupt request flag is set, it will remain in this condition in the
interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by
the application program.
Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt
service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be
automatically cleared, the individual request flag for the function needs to be cleared by the
application program.
It is recommended that programs do not use the "CALL" instruction within the interrupt service
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately.
If only one stack is left and the interrupt is not well controlled, the original control sequence will be
damaged once a CALL subroutine is executed in the interrupt subroutine.
Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE
Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is
required to prevent a certain interrupt from waking up the microcontroller then its respective request
flag should be first set high before enter SLEEP or IDLE Mode.
As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the
contents of the accumulator, status register or other registers are altered by the interrupt service
program, their contents should be saved to the memory at the beginning of the interrupt service
routine.
To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI
instruction in addition to executing a return to the main program also automatically sets the EMI
bit high to allow further interrupts. The RET instruction however only executes a return to the main
program leaving the EMI bit in its present zero state and therefore disabling the execution of further
interrupts.
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Application Circuits
VDD
PA0~PA7
VDD
100kΩ
PB0~PB7
RES
0.1µF
PC0~PC7
0.1µF
PD0~PD6
VSS
OSC
Circuit
OSC
Circuit
Rev. 1.00
PE0~PE4
OSC1
PF0~PF7
OSC2
PG0~PG7
XT1
PH0~PH5
XT2
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Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case
of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5μs and branch or call instructions would be implemented within
1μs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if no
skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of three kinds of MOV instructions, data can be transferred from registers to
the Accumulator and vice-versa as well as being able to move specific immediate data directly into
the Accumulator. One of the most important data transfer applications is to receive data from the
input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in the
destination specified.
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Logical and Rotate Operation
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
bit from where it can be examined and the necessary serial bit set high or low. Another application
which rotate data operations are used is to implement multiplication and division calculations.
Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction
or to a subroutine using the CALL instruction. They differ in the sense that in the case of a
subroutine call, the program must return to the instruction immediately when the subroutine has
been carried out. This is done by placing a return instruction "RET" in the subroutine which will
cause the program to jump back to the address right after the CALL instruction. In the case of a JMP
instruction, the program simply jumps to the desired location. There is no requirement to jump back
to the original jumping off point as in the case of the CALL instruction. One special and extremely
useful set of branch instructions are the conditional branches. Here a decision is first made regarding
the condition of a certain data memory or individual bits. Depending upon the conditions, the
program will continue with the next instruction or skip over it and jump to the following instruction.
These instructions are the key to decision making and branching within the program perhaps
determined by the condition of certain input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m].
i" instructions respectively. The feature removes the need for programmers to first read the 8-bit
output port, manipulate the input data to ensure that other bits are not changed and then output the
port with the correct new data. This read-modify-write process is taken care of automatically when
these bit operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be set as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the "HALT" instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
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Instruction Set Summary
The following table depicts a summary of the instruction set categorised according to function and
can be consulted as a basic instruction reference using the following listed conventions.
Table Conventions
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1
1Note
1Note
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
1
1Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Arithmetic
Add Data Memory to ACC
ADD A,[m]
ADDM A,[m]
Add ACC to Data Memory
ADD A,x
Add immediate data to ACC
ADC A,[m]
Add Data Memory to ACC with Carry
ADCM A,[m]
Add ACC to Data memory with Carry
SUB A,x
Subtract immediate data from the ACC
SUB A,[m]
Subtract Data Memory from ACC
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
SBC A,x
Subtract immediate data from ACC with Carry
SBC A,[m]
Subtract Data Memory from ACC with Carry
SBCM A,[m]
Subtract Data Memory from ACC with Carry, result in Data Memory
DAA [m]
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
Logical AND Data Memory to ACC
OR A,[m]
Logical OR Data Memory to ACC
XOR A,[m]
Logical XOR Data Memory to ACC
ANDM A,[m]
Logical AND ACC to Data Memory
ORM A,[m]
Logical OR ACC to Data Memory
XORM A,[m]
Logical XOR ACC to Data Memory
AND A,x
Logical AND immediate Data to ACC
OR A,x
Logical OR immediate Data to ACC
XOR A,x
Logical XOR immediate Data to ACC
CPL [m]
Complement Data Memory
CPLA [m]
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
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Mnemonic
Description
Cycles Flag Affected
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
2
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
None
2Note
2Note
2Note
None
None
None
2Note
None
1
1Note
1Note
1
1Note
1
1
None
None
None
TO, PDF
None
None
TO, PDF
Bit Operation
CLR [m].i
SET [m].i
Branch Operation
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m]
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if Data Memory is not zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
Table Read Operation
TABRD [m] Read table (specific page) to TBLH and Data Memory
TABRDL [m] Read table (last page) to TBLH and Data Memory
ITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory
Increment table pointer TBLP first and Read table (last page) to TBLH and
ITABRDL [m]
Data Memory
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
SWAP [m]
SWAPA [m]
HALT
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
Note: 1. For skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if
no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the "CLR WDT" instruction the TO and PDF flags may be affected by the execution status. The TO
and PDF flags are cleared after the "CLR WDT" instructions is executed. Otherwise the TO and PDF
flags remain unchanged.
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Extended Instruction Set
The extended instructions are used to support the full range address access for the data memory.
When the accessed data memory is located in any data memory sections except sector 0, the
extended instruction can be used to access the data memory instead of using the indirect addressing
access to improve the CPU firmware performance.
Mnemonic
Description
Cycles
Flag Affected
2
2Note
2
2Note
2
2Note
2
2Note
2Note
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
C
2
2
2
2Note
2Note
2Note
2Note
2
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
2
2Note
2
2Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
2
2Note
2
2Note
2
2Note
2
2Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
2
2Note
None
None
Clear bit of Data Memory
Set bit of Data Memory
2Note
2Note
None
None
Arithmetic
Add Data Memory to ACC
LADD A,[m]
LADDM A,[m] Add ACC to Data Memory
LADC A,[m]
Add Data Memory to ACC with Carry
LADCM A,[m] Add ACC to Data memory with Carry
LSUB A,[m]
Subtract Data Memory from ACC
LSUBM A,[m] Subtract Data Memory from ACC with result in Data Memory
LSBC A,[m]
Subtract Data Memory from ACC with Carry
LSBCM A,[m] Subtract Data Memory from ACC with Carry, result in Data Memory
LDAA [m]
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
LAND A,[m]
Logical AND Data Memory to ACC
LOR A,[m]
Logical OR Data Memory to ACC
LXOR A,[m]
Logical XOR Data Memory to ACC
LANDM A,[m] Logical AND ACC to Data Memory
LORM A,[m]
Logical OR ACC to Data Memory
LXORM A,[m] Logical XOR ACC to Data Memory
LCPL [m]
Complement Data Memory
LCPLA [m]
Complement Data Memory with result in ACC
Increment & Decrement
LINCA [m]
LINC [m]
LDECA [m]
LDEC [m]
Rotate
LRRA [m]
LRR [m]
LRRCA [m]
LRRC [m]
LRLA [m]
LRL [m]
LRLCA [m]
LRLC [m]
Data Move
LMOV A,[m]
LMOV [m],A
Bit Operation
LCLR [m].i
LSET [m].i
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Mnemonic
Description
Cycles Flag Affected
Branch
LSZ [m]
LSZA [m]
LSNZ [m]
LSZ [m].i
LSNZ [m].i
LSIZ [m]
LSDZ [m]
LSIZA [m]
LSDZA [m]
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if Data Memory is not zero
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
2Note
2Note
2Note
2Note
2Note
2Note
2Note
2Note
2Note
None
None
None
None
None
None
None
None
None
3Note
3Note
3Note
None
None
None
3Note
None
2Note
2Note
2Note
2
None
None
None
None
Table Read
LTABRD [m] Read table to TBLH and Data Memory
LTABRDL [m] Read table (last page) to TBLH and Data Memory
LITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory
Increment table pointer TBLP first and Read table (last page) to TBLH and
LITABRDL [m]
Data Memory
Miscellaneous
LCLR [m]
LSET [m]
LSWAP [m]
LSWAPA [m]
Clear Data Memory
Set Data Memory
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Note: 1. For these extended skip instructions, if the result of the comparison involves a skip then up to four cycles
are required, if no skip takes place two cycles is required.
2. Any extended instruction which changes the contents of the PCL register will also require three cycles for
execution.
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Instruction Definition
ADC A,[m]
Description
Operation
Affected flag(s)
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C, SC
ADCM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C, SC
Add Data Memory to ACC
ADD A,[m]
Description
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C, SC
ADD A,x
Description
Operation
Affected flag(s)
Add immediate data to ACC
The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator.
ACC ← ACC + x
OV, Z, AC, C, SC
ADDM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C, SC
AND A,[m]
Description
Operation
Affected flag(s)
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
AND A,x
Description
Operation
Affected flag(s)
Logical AND immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ x
Z
ANDM A,[m]
Description
Operation
Affected flag(s)
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
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CALL addr
Description
Operation
Affected flag(s)
Subroutine call
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Stack ← Program Counter + 1
Program Counter ← addr
None
CLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
CLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
CLR WDT
Description
Operation
Affected flag(s)
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CPL [m]
Description
Operation
Affected flag(s)
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
CPLA [m]
Description
Operation
Affected flag(s)
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
DAA [m]
Description
Operation
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or [m] ← ACC + 60H or
[m] ← ACC + 66H
C
Rev. 1.00
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HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
DEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
DECA [m]
Description
Operation
Affected flag(s)
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
HALT
Description
Operation
Affected flag(s)
Enter power down mode
This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
TO ← 0
PDF ← 1
TO, PDF
INC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
INCA [m]
Description
Operation
Affected flag(s)
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
JMP addr
Description
Operation
Affected flag(s)
Jump unconditionally
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Program Counter ← addr
None
MOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
MOV A,x
Description
Operation
Affected flag(s)
Move immediate data to ACC
The immediate data specified is loaded into the Accumulator.
ACC ← x
None
MOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
Rev. 1.00
238
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HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
NOP
Description
Operation
Affected flag(s)
No operation
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Description
Operation
Affected flag(s)
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
OR A,x
Description
Operation
Affected flag(s)
Logical OR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ x
Z
ORM A,[m]
Description
Operation
Affected flag(s)
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
RET
Description
Operation
Affected flag(s)
Return from subroutine
The Program Counter is restored from the stack. Program execution continues at the restored
address.
Program Counter ← Stack
None
RET A,x
Description
Operation
Affected flag(s)
Return from subroutine and load immediate data to ACC
The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address.
Program Counter ← Stack
ACC ← x
None
RETI
Description
Operation
Affected flag(s)
Return from interrupt
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Program Counter ← Stack
EMI ← 1
None
RL [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
Rev. 1.00
239
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
RLA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
RLC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
RLCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
RR [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
RRA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right with result in ACC
Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
RRC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
Rev. 1.00
240
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HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
RRCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
SBC A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
SBC A, x
Description
Operation
Affected flag(s)
Subtract immediate data from ACC with Carry
The immediate data and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC - [m] - C
OV, Z, AC, C, SC, CZ
SBCM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
SDZ [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
SDZA [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
Rev. 1.00
241
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
SET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
SET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
SIZ [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
SIZA [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
SNZ [m].i
Description
Operation
Affected flag(s)
Skip if Data Memory is not 0
If the specified Data Memory is not 0, the following instruction is skipped. As this requires the
insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
SNZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is not 0
If the specified Data Memory is not 0, the following instruction is skipped. As this requires the
insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m]≠ 0
None
SUB A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C, SC, CZ
Rev. 1.00
242
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
SUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C, SC, CZ
SUB A,x
Description
Operation
Affected flag(s)
Subtract immediate data from ACC
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − x
OV, Z, AC, C, SC, CZ
SWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
SWAPA [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
SZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
SZA [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
SZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
Rev. 1.00
243
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
TABRD [m]
Description
Operation
Affected flag(s)
Read table (specific page) to TBLH and Data Memory
The low byte of the program code (specific page) addressed by the table pointer pair (TBLP and TBHP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
TABRDL [m]
Description
Operation
Affected flag(s)
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
ITABRD [m]
Description
Operation
Affected flag(s)
Increment table pointer low byte first and read table to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
ITABRDL [m]
Description
Operation
Affected flag(s)
Increment table pointer low byte first and read table (last page) to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
XOR A,[m]
Description
Operation
Affected flag(s)
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
XORM A,[m]
Description
Operation
Affected flag(s)
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
XOR A,x
Description
Operation
Affected flag(s)
Logical XOR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ x
Z
Rev. 1.00
244
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Extended Instruction Definition
The extended instructions are used to directly access the data stored in any data memory sections.
LADC A,[m]
Description
Operation
Affected flag(s)
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C, SC
LADCM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C, SC
LADD A,[m]
Description
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C, SC
LADDM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C, SC
LAND A,[m]
Description
Operation
Affected flag(s)
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
LANDM A,[m]
Description
Operation
Affected flag(s)
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
LCLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
LCLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
Rev. 1.00
Add Data Memory to ACC
245
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
LCPL [m]
Description
Operation
Affected flag(s)
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
LCPLA [m]
Description
Operation
Affected flag(s)
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
LDAA [m]
Description
Operation
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or [m] ← ACC + 60H or
[m] ← ACC + 66H
C
LDEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
LDECA [m]
Description
Operation
Affected flag(s)
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
LINC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
LINCA [m]
Description
Operation
Affected flag(s)
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
Rev. 1.00
246
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
LMOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
LMOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
LOR A,[m]
Description
Operation
Affected flag(s)
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
LORM A,[m]
Description
Operation
Affected flag(s)
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
LRL [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
LRLA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
LRLC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
LRLCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
Rev. 1.00
247
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
LRR [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
LRRA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right with result in ACC
Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
LRRC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
LRRCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
LSBC A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
LSBCM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
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Advanced A/D Flash MCU with EEPROM
LSDZ [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
LSDZA [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
LSET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
LSET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
LSIZ [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
LSIZA [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
LSNZ [m].i
Description
Operation
Affected flag(s)
Skip if Data Memory is not 0
If the specified Data Memory is not 0, the following instruction is skipped. As this requires the
insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
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Advanced A/D Flash MCU with EEPROM
LSNZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is not 0
If the content of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m] ≠ 0
None
LSUB A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C, SC, CZ
LSUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C, SC, CZ
LSWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
LSWAPA [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
LSZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
LSZA [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
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Advanced A/D Flash MCU with EEPROM
LSZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
LTABRD [m]
Description
Operation
Affected flag(s)
Read table (current page) to TBLH and Data Memory
The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
LTABRDL [m]
Description
Operation
Affected flag(s)
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
LITABRD [m]
Description
Operation
Increment table pointer low byte first and read table to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
Affected flag(s)
None
LITABRDL [m]
Description
Operation
Affected flag(s)
Increment table pointer low byte first and read table (last page) to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
LXOR A,[m]
Description
Operation
Affected flag(s)
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
LXORM A,[m]
Description
Operation
Affected flag(s)
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
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Advanced A/D Flash MCU with EEPROM
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the package information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant
section to be transferred to the relevant website page.
• Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• The Operation Instruction of Packing Materials
• Carton information
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48-pin LQFP (7mm×7mm) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.020 BSC
—
F
0.007
0.009
0.011
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.004
0.024
―
0.030
0°
―
A
K
α
Symbol
0.008
7°
Dimensions in mm
Min.
Nom.
Max.
A
—
9.00 BSC
—
B
—
7.00 BSC
—
C
—
9.00 BSC
—
D
—
7.00 BSC
—
E
—
0.50 BSC
—
F
0.17
0.22
0.27
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
0°
—
―
0.20
7°
α
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HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
64-pin LQFP (7mm×7mm) Outline Dimensions
Symbol
A
Nom.
Max.
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.016 BSC
—
F
0.005
0.007
0.009
G
0.053
0.055
0.057
H
—
—
0.063
0.006
I
0.002
—
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
—
9.00 BSC
—
B
—
7.00 BSC
—
C
—
9.00 BSC
—
D
—
7.00 BSC
—
E
—
0.40 BSC
—
F
0.13
0.18
0.23
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
—
7°
254
December 06, 2016
HT66F2350/HT66F2360
HT66F2370/HT66F2390
Advanced A/D Flash MCU with EEPROM
Copyright© 2016 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw/en/home.
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