HI-3200, HI-3201 - Holt Integrated Circuits

HI-3200, HI-3201 - Holt Integrated Circuits
HI-3200, HI-3201
AVIONICS DATA MANAGEMENT ENGINE /
ARINC 429 - CAN BUS BRIDGE
June 2017
GENERAL DESCRIPTION
FEATURES
The HI-3200 from Holt Integrated Circuits is a single chip
CMOS data management IC capable of managing, storing
and forwarding avionics data messages between eight
ARINC 429 receive channels, four ARINC 429 transmit
channels and a single CAN / ARINC 825 data bus.
The ARINC 429 and CAN buses may be operated independently, allowing a host CPU to send and receive data
on multiple buses, or the HI-3200 can be programmed to
automatically re-format, re-label, re-packetize and retransmit data from ARINC 429 receive buses to ARINC
429 transmit buses, as well as from ARINC 429 to CAN or
CAN to ARINC 429.
A 32K x 8 on-board memory allows received data to be
logically organized and automatically updated as new
ARINC 429 labels or CAN frames are received.
·
·
·
·
Eight ARINC 429 Receive channels
Four ARINC 429 Transmit channels
CAN Bus / ARINC 825 Interface
32KB on chip user-configurable data storage
memory
· Programmable received data filtering for ARINC 429
and CAN buses
· Programmable transmission schedulers for periodic
ARINC 429 and CAN message broadcasting
· Flexible protocol bridge ARINC 429 to CAN and
CAN to ARINC 429
· SPI Host CPU interface
· Auto-initialization feature allows power-on
configuration or independent operation without CPU
An auto-initialization feature allows configuration information to be up-loaded from an external EEPROM on reset to
facilitate rapid start-up or operation without a host CPU.
PIN CONFIGURATION
ARX2P
ARX1N
ARX1P
ARX0N
ARX0P
SCANEN
CMISO
READY
ESCLK
EMOSI
ECSB
EMISO
RUN
CCSB
ATXMSK
MRST
The HI-3200 interfaces directly with Holt’s HI-8448 octal
ARINC 429 receiver IC, HI-8596 or HI-8592 ARINC 429
line drivers and HI-3110 integrated CAN controller /
transceiver.
AACK 1
CGP2 2
AINT 3
CSTAT 4
SCANSHIFT 5
ARX2N 6
ARX3P 7
VDD 8
GND 9
ARX3N 10
ARX4P 11
ARX4N 12
ARX5P 13
ARX5N 14
ARX6P 15
ARX6N 16
APPLICATION
HI-3200PQI
&
HI-3200PQT
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CMROUT
ATXSLP0
ATX0N
ATX0P
ATX1N
ATX1P
ATXSLP1
VDD
GND
COSC
ATXSLP2
ATX2N
ATX2P
ATX3N
ATX3P
ATXSLP3
ARX7P
ARX7N
MODE0
CMOSI
MODE1
MCLK
MODE2
ARXBIT0
ARXBIT1
HMISO
HSCLK
HMOSI
HCSB
CSCLK
MINT
MINTACK
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CAN Bus
HI-3110
HI-8448
ARINC 429
8 x Receive
CPU
ARINC 429
4 x Transmit
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
The HI-3201 is identical to the HI-3200 except it comes in
an 80-pin PQFP package with eight instead of two ARINC
429 bit monitor pins.
HI-3200
64 - Pin Plastic Quad Flat Pack (PQFP)
(See ordering information for additional pin configurations)
(DS3200 Rev. L)
HOLT INTEGRATED CIRCUITS
www.holtic.com
06/17
HI-3200, HI-3201
BLOCK DIAGRAM
Host CPU
ARINC 825 (CAN)
Interrupt Handler
SPI
ARINC 429
RECEIVE DATA
MEMORY 0
1K x 8
ARINC 825 (CAN)
Descriptor Table
FILTER
TABLE 0
TRANSMIT TIMER
Message 32
“
“
“
Message 2
Message 1
32 x 32 FIFO
LABEL
FILTER
HI-3110
Data
Interfacel
ARINC 825 / CAN
FILTER / MASK
TABLE
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
TRANSMITTER 0
ARINC825 / CAN
RECEIVE DATA
MEMORY
4K x 8
ARINC 429
TRANSMIT
SCHEDULER 0
ARINC 825 (CAN)
TRANSMIT
SCHEDULER
HI-3110
Configuration
& Control
ARINC 429
Descriptor Table 0
TRANSMIT TIMER
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
Auto-Initialization
EEPROM
HOLT INTEGRATED CIRCUITS
2
CMROUT
COSC
CGP2
CSTAT
HI-3110
Transceiver
ARINC 825 (CAN)
FILTER
EEPROM
SPI
CCSB
CSCLK
CMOSI
CMISO
HI-3200
ARINC 825 / CAN Bus
RECEIVER 0
ECSB
ESCLK
EMOSI
EMISO
4 x ARINC 429 Transmit Buses
8 x ARINC 429 Receive Buses
ARINC 429
BIT MATCH
MINTACK
MINT
HCSB
HSCLK
HMOSI
HMISO
AACK
AINT
ARXBIT7
ARXBIT6
ARXBIT5
ARXBIT4
ARXBIT3
ARXBIT2
ARXBIT1
ARXBIT0
ARINC 429
Interrupt Handler
HI-3200, HI-3201
APPLICATION OVERVIEW
The HI-3200 is a flexible device for managing ARINC 429
and ARINC 825 communications and data storage in
many avionics applications. The device architecture
centers around a 32K x 8 static RAM used for data
storage, data filtering tables and table-driven
transmission schedulers. Once configured, the device
can operate autonomously without a host CPU, negating
the need for software development or DO-178
certification. Configuration data may be uploaded into the
device from an external EEPROM, following system
reset.
The device supports up to eight ARINC 429 receive
channels. Received data is stored in on-chip RAM
organized by channel number and label. The data table
continually updates as new labels arrive. Programmable
interrupts and filters alert the host subsystem to labels of
interest.
Each ARINC 429 receive channel also includes a 32
message deep FIFO allowing selected label data to be
queued for subsequent host access.
The HI-3200 includes four independent ARINC 429
transmit channels. Transmission may be controlled
entirely by an external CPU, or autonomously by
programming one or more of the four on-chip ARINC 429
transmit schedulers. These allow periodic transmission
to occur without CPU. Source data for transmission may
be selected from RAM based tables of constants and / or
from the received channel data. Powerful options exist for
constructing ARINC 429 labels as well as controlling their
timing and conditional transmission.
Even when running under the control of schedulers, the
host CPU may insert new labels for transmission at will.
The HI-3200 also supports ARINC 825 (CAN)
communication. An external HI-3110 CAN controller
automatically handles the CAN bus protocol and physical
interface. The HI-3200 configures the HI-3110 at system
initialization and manages all traffic to and from the CAN
bus.
As with ARINC 429, ARINC 825 received data may be
filtered and stored in on-chip RAM, organized by ID field
filters. ARINC 825 frame transmission may be directly
controlled by a host CPU or by an on-chip transmission
scheduler. CAN frames may be built and conditionally
transmitted using the scheduler’s flexible instruction set.
Source data for CAN frames can be from CPU, stored
constants or from received ARINC 429 data tables.
The following examples show eight possible
configurations of how the HI-3200 may be used:
Example 1. ARINC 429 Data reception using on-chip RAM
RECEIVER 7
Channel 7, Label FF
“
“
“
Channel 7, Label 01
Channel 7, Label 00
RECEIVER 6
Channel 6, Label FF
“
“
“
Channel 6, Label 01
Channel 6, Label 00
RECEIVER 5
Channel 5, Label FF
“
“
“
Channel 5, Label 01
Channel 5, Label 00
RECEIVER 4
Channel 4, Label FF
“
“
“
Channel 4, Label 01
Channel 4, Label 00
RECEIVER 3
Channel 3, Label FF
“
“
“
Channel 3, Label 01
Channel 3, Label 00
RECEIVER 2
Channel 2, Label FF
“
“
“
Channel 2, Label 01
Channel 2, Label 00
8 x ARINC 429
Receive Buses
RECEIVER 1
RECEIVER 0
ARINC 429
RECEIVE
INTERRUPT
TABLE
Host CPU
SPI
Channel 0, Label FF
“
“
“
Channel 0, Label 01
Channel 0, Label 00
HOLT INTEGRATED CIRCUITS
3
AACK
HCSB
HSCLK
HMOSI
HMISO
Channel 1, Label FF
“
“
“
Channel 1, Label 01
Channel 1, Label 00
8K x 8 RAM
AINT
HI-3200
HI-3200, HI-3201
Example 2. ARINC 429 Data reception using on-chip filters and FIFOs
FILTER
TABLE 0
8 x ARINC 429
Receive Buses
RECEIVER 0
LABEL
FILTER
Message 32
“
“
“
Message 2
Message 1
32 x 32 FIFO
HCSB
HSCLK
HMOSI
HMISO
SPI
FIFO STATUS
Host CPU
FIFO EMPTY
FIFO THRESHOLD
FIFO FULL
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
ARINC 429
RECEIVE FIFO
INTERRUPT
CONTROL
AINT
AACK
HI-3200
Example 3. ARINC 429 Data transmission directly from CPU
TRANSMITTER 0
Host CPU
HCSB
HSCLK
HMOSI
HMISO
TRANSMITTER 1
4 x ARINC 429
Transmit Buses
SPI
TRANSMITTER 2
TRANSMITTER 3
HI-3200
Example 4. ARINC 429 Data transmission using on-chip schedulers
Descriptor Table 0
Host CPU
HCSB
HSCLK
HMOSI
HMISO
TRANSMIT
SCHEDULER 0
4 x ARINC 429
Transmit Buses
SPI
Descriptor Table 1
TRANSMIT TIMER
Descriptor Table 2
Auto-Initialization
EEPROM
ECSB
ESCLK
EMOSI
EMISO
TRANSMITTER 0
EEPROM
SPI
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
Descriptor Table 3
RAM
HOLT INTEGRATED CIRCUITS
4
HI-3200
HI-3200, HI-3201
Example 5. Autonomous ARINC 429 Data Concentrator / Repeater
RECEIVER 7
Channel 7, Label FF
“
“
“
Channel 7, Label 01
Channel 7, Label 00
RECEIVER 6
Channel 6, Label FF
“
“
“
Channel 6, Label 01
Channel 6, Label 00
RECEIVER 5
Channel 5, Label FF
“
“
“
Channel 5, Label 01
Channel 5, Label 00
8 x ARINC 429
Receive Buses
Descriptor Table 3
RECEIVER 3
Channel 3, Label FF
“
“
“
Channel 3, Label 01
Channel 3, Label 00
RECEIVER 2
Channel 2, Label FF
“
“
“
Channel 2, Label 01
Channel 2, Label 00
TRANSMITTER 3
TRANSMIT TIMER
Descriptor Table 2
Channel 4, Label FF
“
“
“
Channel 4, Label 01
Channel 4, Label 00
RECEIVER 4
TRANSMIT
SCHEDULER 3
TRANSMIT
SCHEDULER 2
TRANSMITTER 2
4 x ARINC 429
Transmit Buses
TRANSMIT TIMER
Descriptor Table 1
TRANSMIT
SCHEDULER 1
TRANSMITTER 1
TRANSMIT TIMER
Channel 1, Label FF
“
“
“
Channel 1, Label 01
Channel 1, Label 00
RECEIVER 1
Descriptor Table 0
Channel 0, Label FF
“
“
“
Channel 0, Label 01
Channel 0, Label 00
RECEIVER 0
TRANSMIT
SCHEDULER 0
TRANSMITTER 0
TRANSMIT TIMER
EEPROM
SPI
ECSB
ESCLK
EMOSI
EMISO
HI-3200
Auto-Initialization
EEPROM
Example 6. ARINC 825 (CAN) bus Monitor / Receiver
ARINC 825 / CAN Bus
ARINC 825 / CAN
FILTER / MASK
TABLE
CCSB
CSCLK
CMOSI
CMISO
HI-3110
Transceiver
CMROUT
COSC
CGP2
CSTAT
HI-3110
Data
Interface
HI-3110
Configuration
& Control
ARINC825 / CAN
FILTER
ARINC825 / CAN
RECEIVE DATA
MEMORY
4K x 8
SPI
ARINC 825 / CAN
INTERRUPT ENABLE
TABLE
Host CPU
ARINC 825 / CAN
INTERRUPT
CONTROL
HI-3200
HOLT INTEGRATED CIRCUITS
5
HCSB
HSCLK
HMOSI
HMISO
MINT
MINTACK
HI-3200, HI-3201
Example 7. ARINC 825 (CAN) Terminal / Data Manager
ARINC 825 / CAN
TRANSMITTER
ARINC825 / CAN
RECEIVE DATA
MEMORY
4K x 8
HCSB
HSCLK
HMOSI
HMISO
SPI
ARINC 825 / CAN
INTERRUPT ENABLE
TABLE
Host CPU
MINT
MINTACK
ARINC825 / CAN
FILTER
HI-3110
Data
Interfacel
HI-3110
Configuration
& Control
ARINC 825 / CAN
INTERRUPT
CONTROL
HI-3200
HOLT INTEGRATED CIRCUITS
6
CCSB
CSCLK
CMOSI
CMISO
CMROUT
COSC
CGP2
CSTAT
HI-3110
Transceiver
ARINC 825 / CAN Bus
ARINC 825 / CAN
FILTER / MASK
TABLE
HI-3200, HI-3201
RECEIVER 7
Channel 7, Label FF
“
“
“
Channel 7, Label 01
Channel 7, Label 00
RECEIVER 6
Channel 6, Label FF
“
“
“
Channel 6, Label 01
Channel 6, Label 00
RECEIVER 5
Channel 5, Label FF
“
“
“
Channel 5, Label 01
Channel 5, Label 00
RECEIVER 4
RECEIVER 3
Channel 3, Label FF
“
“
“
Channel 3, Label 01
Channel 3, Label 00
RECEIVER 2
Channel 2, Label FF
“
“
“
Channel 2, Label 01
Channel 2, Label 00
RECEIVER 1
RECEIVER 0
TRANSMITTER 3
Channel 4, Label FF
“
“
“
Channel 4, Label 01
Channel 4, Label 00
ARINC 429
TRANSMIT
SCHEDULER 3
ARINC 825 (CAN)
Descriptor Table
Channel 1, Label FF
“
“
“
Channel 1, Label 01
Channel 1, Label 00
TRANSMIT TIMER
Channel 0, Label FF
“
“
“
Channel 0, Label 01
Channel 0, Label 00
HI-3110
Data
Interfacel
ARINC 825 / CAN
FILTER / MASK
TABLE
ARINC 429
Descriptor Table 3
ARINC825 / CAN
RECEIVE DATA
MEMORY
4K x 8
TRANSMIT TIMER
ARINC 429
TRANSMIT
SCHEDULER 2
HI-3110
Configuration
& Control
ARINC 825 (CAN)
FILTER
ARINC 429
Descriptor Table 2
TRANSMIT TIMER
TRANSMITTER 1
ARINC 429
TRANSMIT
SCHEDULER 1
ARINC 429
Descriptor Table 1
TRANSMIT TIMER
TRANSMITTER 0
ARINC 429
TRANSMIT
SCHEDULER 0
ARINC 429
Descriptor Table 0
TRANSMIT TIMER
EEPROM
SPI
HI-3200
ECSB
ESCLK
EMOSI
EMISO
4 x ARINC 429
Transmit Buses
TRANSMITTER 2
ARINC 825 (CAN)
TRANSMIT
SCHEDULER
Auto-Initialization
EEPROM
HOLT INTEGRATED CIRCUITS
7
CCSB
CSCLK
CMOSI
CMISO
CMROUT
COSC
CGP2
CSTAT
HI-3110
Transceiver
ARINC 825 / CAN Bus
8 x ARINC 429
Receive Buses
Example 8. ARINC 429 - ARINC 825 (CAN) Autonomous Bridge
HI-3200, HI-3201
PIN DESCRIPTIONS
SIGNAL
AACK
AINT
ARX0N
ARX0P
ARX1N
ARX1P
ARX2N
ARX2P
ARX3N
ARX3P
ARX4N
ARX4P
ARX5N
ARX5P
ARX6N
ARX6P
ARX7N
ARX7P
ARXBIT0-1
ARXBIT2-7
ATX0N
ATX0P
ATX1N
ATX1P
ATX2N
ATX2P
ATX3N
ATX3P
ATXMSK
ATXSLP0
ATXSLP1
ATXSLP2
ATXSLP3
CCSB
CGP2
CMISO
CMOSI
CMROUT
COSC
CSCLK
CSTAT
ECSB
EMISO
EMOSI
ESCLK
GND
HCSB
HMISO
HMOSI
HSCLK
MCLK
MINT
MINTACK
MODE2:0
MRST
PROG (MODE0)
READY
RUN
SCANEN
SCANSHIFT
VDD
FUNCTION
INPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
OUTPUTS
OUTPUTS
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT
OUTPUT
POWER
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUTS
INPUT
INPUT
OUTPUT
INPUT
RESERVED
RESERVED
POWER
DESCRIPTION
ARINC 429 Receiver Interrupt Acknowledge (Active High)
ARINC 429 Receiver Interrupt (Active High)
ARINC 429 Rx negative data input for channel 0
ARINC 429 Rx positive data input for channel 0
ARINC 429 Rx negative data input for channel 1
ARINC 429 Rx positive data input for channel 1
ARINC 429 Rx negative data input for channel 2
ARINC 429 Rx positive data input for channel 2
ARINC 429 Rx negative data input for channel 3
ARINC 429 Rx positive data input for channel 3
ARINC 429 Rx negative data input for channel 4
ARINC 429 Rx positive data input for channel 4
ARINC 429 Rx negative data input for channel 5
ARINC 429 Rx positive data input for channel 5
ARINC 429 Rx negative data input for channel 6
ARINC 429 Rx positive data input for channel 6
ARINC 429 Rx negative data input for channel 7
ARINC 429 Rx positive data input for channel 7
ARINC 429 received payload bit monitor pins 0 and 1
ARINC 429 received payload bit monitor pins 2 through 7 (HI-3201 only)
ARINC 429 Tx channel 0 negative data output to line driver
ARINC 429 Tx channel 0 positive data output to line driver
ARINC 429 Tx channel 1 negative data output to line driver
ARINC 429 Tx channel 1 positive data output to line driver
ARINC 429 Tx channel 2 negative data output to line driver
ARINC 429 Tx channel 2 positive data output to line driver
ARINC 429 Tx channel 3 negative data output to line driver
ARINC 429 Tx channel 3 positive data output to line driver
Turn off ARINC 429 Transmit pins (Holds TXnA/B pins zero)
ARINC 429 Tx channel 0 data rate select output. 1 = high speed, 0 = low speed
ARINC 429 Tx channel 1 data rate select output. 1 = high speed, 0 = low speed
ARINC 429 Tx channel 2 data rate select output. 1 = high speed, 0 = low speed
ARINC 429 Tx channel 3 data rate select output. 1 = high speed, 0 = low speed
SPI chip select for HI-3110 CAN Controller / Transceiver
Signal from HI-3110 CAN Controller / Transceiver indicating CAN Rx data is available
SPI serial data input from HI-3110 CAN Controller / Transceiver
SPI serial data output to HI-3110 CAN Controller / Transceiver
Master Reset signal to HI-3110 CAN Controller / Transceiver
24 MHz CAN reference clock output to HI-3110 CAN Controller / Transceiver
SPI clock for HI-3110 CAN Controller / Transceiver
Signal from HI-3110 CAN Controller / Transceiver indicating CAN Tx FIFO is full
SPI chip select for auto-initialization EEPROM
SPI serial data input from auto-inialization EEPROM
SPI serial data output to auto-initialization EEPROM
SPI clock for auto-initialization EEPROM (8MHz max.)
Chip 0V supply
Chip select. Data is shifted into HMOSI and out of HMISO when HCSB is low
Host CPU SPI interface serial data output
Host CPU SPI interface serial data input
SPI Clock. Data is shifted into or out of the SPI interface using HSCLK
Master 48 MHz (+/- 0.1%) reference clock for ARINC 429 and CAN bus bit timing
Programmable event interrupt output (Active High)
Programmable event interrupt acknowledge (Active High)
MODE2 through MODE0 define HI-3200 start-up and initialization mode
Master Reset to HI-3200 Active High. See RESET AND START-UP section
Multiplexed with MODE0 pin, PROG initiates HI-3200 EEPROM Auto-Initialization
READY goes high when post-RESET initialization is complete
Master enable signal for ARINC 429 and CAN transmit schedulers
Connect to GND
Connect to GND
3.3V power supply
HOLT INTEGRATED CIRCUITS
8
PULL UP/DOWN
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Up
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Downs
Pull-Down
Pull-Down
Pull-Down
HI-3200, HI-3201
HI-3200 MEMORY MAP
0x8XXX
Configuration Registers
0x8000
0x7FFF
CAN TX ID Look-Up Table
0x7C00
0x7BFF
ARINC 429 RX Interrupt Map
Look-up Tables
ARINC 429 RX Enable Map
Can Bus RX Interrupt Map
0x79C0
0x79BF
CAN Bus RX Enable Map
CAN Bus
Transmit Schedule
Table
0x6000
0x5FFF
0x5800
0x57FF
0x5000
0x4FFF
0x4800
0x47FF
0x4000
0x3FFF
0x3400
0x33FF
0x3000
0x2FFF
ARINC 429 TX3
Transmit Schedule
Table
ARINC 429 TX2
Transmit Schedule
Table
ARINC 429 TX1
Transmit Schedule
Table
ARINC 429 TX0
Transmit Schedule
Table
CAN Bus
Receive
Filters
ARINC 429 Log FIFO Space
CAN Bus
Receive
Data
0x2000
0x1FFF
Shaded Area
User - Programmed
ARINC 429
Receive
Data
Non-shaded Area
Data Storage
0x0000
HOLT INTEGRATED CIRCUITS
9
0x7BFF
0x7B00
0x7AFF
0x7A00
0x79FF
0x79E0
0x79DF
0x79C0
HI-3200, HI-3201
HI-3200 REGISTER MAP
ADDRESS R/W
REGISTER
MNEMONIC
ARINC 429 Rx PENDING INTERRUPT
ARINC 429 Rx INTERRUPT ADDRESS 0
ARINC 429 Rx INTERRUPT ADDRESS 1
ARINC 429 Rx INTERRUPT ADDRESS 2
ARINC 429 Rx INTERRUPT ADDRESS 3
ARINC 429 Rx INTERRUPT ADDRESS 4
ARINC 429 Rx INTERRUPT ADDRESS 5
ARINC 429 Rx INTERRUPT ADDRESS 6
ARINC 429 Rx INTERRUPT ADDRESS 7
RESERVED
PENDING INTERRUPT REGISTER
INTERRUPT ADDRESS REGISTER
MUXED FIFO FLAGS
ARINC 429 TX READY BITS
MASTER STATUS REGISTER
MASTER CONTROL REGISTER
APIR
AIAR0
AIAR1
AIAR2
AIAR3
AIAR4
AIAR5
AIAR6
AIAR7
Defines channel(s) with pending Interrupt
ARINC 429 Interrupt Vector channel 0
ARINC 429 Interrupt Vector channel 1
ARINC 429 Interrupt Vector channel 2
ARINC 429 Interrupt Vector channel 3
ARINC 429 Interrupt Vector channel 4
ARINC 429 Interrupt Vector channel 5
ARINC 429 Interrupt Vector channel 6
ARINC 429 Interrupt Vector channel 7
PIR
CIAR
AMFF
ATRB
MSR
MCR
Indicates Interrupt type
CAN bus Interrupt vector
ARINC 429 Multiplexed FIFO flags
ARINC 429 Transmitter Ready flags
Indicates HI-3200 current status
HI-3200 global configuration
0x8000
0x8001
0x8002
0x8003
0x8004
0x8005
0x8006
0x8007
0x8008
0x8009
0x800A
0x800B
0x800C
0x800D
0x800E
0x800F
R*
R
R
R
R
R
R
R
R
R*
R
R
R
R
R/W
0x8010
0x8011
0x8012
0x8013
0x8014
0x8015
0x8016
0x8017
0x8018
0x8019
0x801A
0x801B
0x801C
0x801D
0x801E
0x801F
0x8020
0x8021
0x8022
0x8029
0x802A
0x802B
0x802C
0x802D
0x802E
0x802F
0x8030
0x8031
0x8032
0x8033
0x8034
0x8035
0x803E
0x803F
R/W
ARINC 429 RX CONTROL REGISTER 0
R/W
ARINC 429 RX CONTROL REGISTER 1
R/W
ARINC 429 RX CONTROL REGISTER 2
R/W
ARINC 429 RX CONTROL REGISTER 3
R/W
ARINC 429 RX CONTROL REGISTER 4
R/W
ARINC 429 RX CONTROL REGISTER 5
R/W
ARINC 429 RX CONTROL REGISTER 6
R/W
ARINC 429 RX CONTROL REGISTER 7
R/W
ARINC 429 TX CONTROL REGISTER 0
R/W
ARINC 429 TX CONTROL REGISTER 1
R/W
ARINC 429 TX CONTROL REGISTER 2
R/W
ARINC 429 TX CONTROL REGISTER 3
R/W
ARINC 429 TX REPETITION RATE 0
R/W
ARINC 429 TX REPETITION RATE 1
R/W
ARINC 429 TX REPETITION RATE 2
R/W
ARINC 429 TX REPETITION RATE 3
R/W
ARINC 429 Rx INTERRUPT MASK
R/W ARINC 429 Rx FIFO THRESHOLD VALUE
R/W
ARINC 429 LOOPBACK
R
ARINC 429 Rx FIFO FULL FLAG
R
ARINC 429 Rx FIFO THRESHOLD FLAG
R
ARINC 429 Rx FIFO NOT EMPTY FLAG
R
ARINC 429 TX SEQUENCE POINTER 0
R
ARINC 429 TX SEQUENCE POINTER 1
R
ARINC 429 TX SEQUENCE POINTER 2
R
ARINC 429 TX SEQUENCE POINTER 3
R/W
CAN BUS BIT TIMING REGISTER 0
R/W
CAN BUS BIT TIMING REGISTER 1
R/W
CAN TRANSMIT CONTROL REGISTER
R/W
CAN TX REPETITION RATE
R/W PENDING INTERRUPT ENABLE REGISTER
R/W
ARINC 429 TX READY INT ENABLE
R
CAN TX SEQUENCE POINTER MSB
R
CAN TX SEQUENCE POINTER LSB
Fast Access Registers
Memory mapped register access only
ARXC0
ARXC1
ARXC2
ARXC3
ARXC4
ARXC5
ARXC6
ARXC7
ATXC0
ATXC1
ATXC2
ATXC3
ATXRR0
ATXRR1
ATXRR2
ATXRR3
AIMR
AFTV
ALOOP
AFFF
AFTF
FFNE
ATXSP0
ATXSP1
ATXSP2
ATXSP3
CANBTR0
CANBTR1
CANTXC
CANTXRR
IMR
ATRIE
CANTXSPH
CANTXSPL
DESCRIPTION
Configures ARINC 429 receive channel 0
Configures ARINC 429 receive channel 1
Configures ARINC 429 receive channel 2
Configures ARINC 429 receive channel 3
Configures ARINC 429 receive channel 4
Configures ARINC 429 receive channel 5
Configures ARINC 429 receive channel 6
Configures ARINC 429 receive channel 7
Configures ARINC 429 transmit channel 0
Configures ARINC 429 transmit channel 1
Configures ARINC 429 transmit channel 2
Configures ARINC 429 transmit channel 3
Sets sequence repeat time for ARINC TX0
Sets sequence repeat time for ARINC TX1
Sets sequence repeat time for ARINC TX2
Sets sequence repeat time for ARINC TX3
Enables Interrupts on AINT pin
Sets flag value for ARINC 429 Receive FIFO
Sets loop-back self-test mode
Indicates which FIFOs are full
Indicates which FIFOs hold > (thresh) messages
Indicates which receive FIFOs hold data
Current address of ARINC transmit sequence 0
Current address of ARINC transmit sequence 1
Current address of ARINC transmit sequence 2
Current address of ARINC transmit sequence 3
Sets bit timing parameters for CAN bus
Sets bit timing parameters for CAN bus
Controls CAN bus transmit scheduler
Sets sequence repeat time for CAN transmitter
Enables Interrupts on MINT pin
Enables ARINC 429 TX Ready Interrupts
High order CAN transmit sequence counter
Low order CAN transmit sequence counter
* Register is cleared when read (auto clear)
HOLT INTEGRATED CIRCUITS
10
HI-3200, HI-3201
ADDRESS R/W
0x805F
0x8060
0x8061
0x8062
0x8063
0x8064
0x8065
0x8066
0x8067
0x8068
0x8069
0x806A
0x806B
0x806C
0x806D
0x806E
0x806F
0x8070
0x8071
0x8072
0x8073
0x8074
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
REGISTER
MNEMONIC
PINS ARXBIT[7:0]
PIN ARXBIT0 CONFIG REG 1
PIN ARXBIT0 CONFIG REG 2
PIN ARXBIT1 CONFIG REG 1
PIN ARXBIT1 CONFIG REG 2
PIN ARXBIT2 CONFIG REG 1
PIN ARXBIT2 CONFIG REG 2
PIN ARXBIT3 CONFIG REG 1
PIN ARXBIT3 CONFIG REG 2
PIN ARXBIT4 CONFIG REG 1
PIN ARXBIT4 CONFIG REG 2
PIN ARXBIT5 CONFIG REG 1
PIN ARXBIT5 CONFIG REG 2
PIN ARXBIT6 CONFIG REG 1
PIN ARXBIT6 CONFIG REG 2
PIN ARXBIT7 CONFIG REG 1
PIN ARXBIT7 CONFIG REG 2
BIST CONTROL/STATUS
BIST FAIL ADDRESS [7:0]
BIST FAIL ADDRESS [12:8]
AUTO-INIT FAIL LS ADDRESS [7:0]
AUTO-INIT FAIL MS ADDRESS [15:8]
ARXBIT
ARX0CR1
ARX0CR2
ARX1CR1
ARX1CR2
ARX2CR1
ARX2CR2
ARX3CR1
ARX3CR2
ARX4CR1
ARX4CR2
ARX5CR1
ARX5CR2
ARX6CR1
ARX6CR2
ARX7CR1
ARX7CR2
BISTS
BISTFL
BISTFH
AIFL
AIFH
HOLT INTEGRATED CIRCUITS
11
DESCRIPTION
Values of pins ARXBIT[7:0]
ARINC 429 bit Monitor 0 channel & bit select
ARINC 429 bit Monitor 0 label select
ARINC 429 bit Monitor 1 channel & bit select
ARINC 429 bit Monitor 1 label select
ARINC 429 bit Monitor 2 channel & bit select
ARINC 429 bit Monitor 2 label select
ARINC 429 bit Monitor 3 channel & bit select
ARINC 429 bit Monitor 3 label select
ARINC 429 bit Monitor 4 channel & bit select
ARINC 429 bit Monitor 4 label select
ARINC 429 bit Monitor 5 channel & bit select
ARINC 429 bit Monitor 5 label select
ARINC 429 bit Monitor 6 channel & bit select
ARINC 429 bit Monitor 6 label select
ARINC 429 bit Monitor 7 channel & bit select
ARINC 429 bit Monitor 7 label select
Built-In Self-Test (bits 1,0 are read only)
Low-order failing BIST memory address
High-order failing BIST memory address
Auto-initialization fail address (low-byte)
Auto-initialization fail address (high byte)
HI-3200, HI-3201
HI-3200 SYSTEM CONFIGURATION
Starting at memory address 0x8000, the HI-3200
contains a set of registers that are used to configure the
HI-3200 device and, if used, its associated HI-3110
integrated CAN controller / transceiver.
An SPI by-pass mode allows the user to directly access
the HI-3110, but it is highly recommended that this is
used solely for design debugging purposes and is locked
out in the final design implementation. By-pass mode is
enabled by setting the state of the MODE2:0 pins during
reset. See the Reset and Start-Up Configuration section
for more details.
The user needs only to program the HI-3200
configuration registers to completely define the full
system operation.
The configuration registers are divided into four
categories, as follows;
Configuration information for the HI-3110 is automatically
transferred from the HI-3200 to the HI-3110 immediately
after the RUN input is asserted.
1. HI-3200 global configuration
2. ARINC 429 Receive channel configuration
3. ARINC 429 Transmit channel configuration
4. CAN Bus bit timing configuration
HI-3200 Global Configuration
A4
29
A4 RX
29
C TX
AN
C RX
AN
AF TX
LI
P
The following registers define the HI-3200 top-level configuration:
MASTER CONTROL REGISTER
(Address 0x800F)
7 6
MSB
5
4
3
X
X
X
2
1
0
LSB
Bit Name
R/W
Default Description
7
A429RX
R/W
0
This bit must be set to a “1” to allow the HI-3200 to receive ARINC 429 data on any of the eight
channels. If set to a zero, the HI-3200 will not respond to any ARINC 429 receive bus,
regardless of the state of the ARINC 429 Receive channel Control Registers.
6
A429TX
R/W
0
This bit must be set to a “1” to allow the HI-3200 to transmit ARINC 429 data on any of the four
channels. If set to a zero, the HI-3200 will not output ARINC 429 data and the ARINC 429
transmit sequencers will remain in their reset state.
5
CANRX
R/W
0
This bit must be set to a “1” to allow the HI-3200 to receive CAN Frames from the HI-3110
controller. If set to a zero, the HI-3200 will not respond to any received CAN frames, regardless
of the state of the CAN Bus Control Register.
4
CANTX
R/W
0
This bit must be set to a “1” to allow the HI-3200 to transmit CAN frames. If set to a zero, the
HI-3200 will not output CAN frames and the CAN transmit sequencer will remain in its reset
state.
3
AFLIP
R/W
0
When set to a “1”, this bit switches the bit order of the ARINC 429 label byte in both receive and
transmit channels.
2
-
R/W
0
Not Used
1
-
R/W
0
Not Used
0
-
R/W
0
Not Used
HOLT INTEGRATED CIRCUITS
12
HI-3200, HI-3201
CAN Bus Timing Configuration
Two registers must be programmed to define the CAN
bus data rate and bit sampling segment times. This
information is transferred directly to the HI-3110 CAN
controller’s BTR0 and BTR1 registers following the rising
edge of the RUN input.
SJ
W
SJ 1
W
BR 0
P
BR 5
P
BR 4
P
BR 3
P
BR 2
P
BR 1
P0
The HI-3110 OSCIN clock frequency must be set to
achieve the desired bit rate. The HI-3200 COSC output
signal provides a convenient 24MHz clock source for the
HI-3110. For a full description of CAN Bus timing
requirements, please refer to the Holt HI-3110 data sheet.
CANBTR0
(Address 0x8030)
7 6
MSB
5
4
3
2
1
0
LSB
CANBTR0 defines the value of the Re-synchronization Jump Width (SJW) and the Baud Rate Prescaler (BRP).
Bit
Name
R/W
Default Description
7:6
SJW1:0
R/W
0
These bits are used to compensate for phase shifts between different oscillators on the CAN
bus. They define the maximum number of time quanta (Tq) a bit can be shortened or
lengthened to allow the node to achieve re-synchronization to the edge of an incoming signal.
Note that the time quantum (Tq) is the single unit of time within a bit time.
5:0
BRP5:0
R/W
0
The baud rate prescaler relates the HI-3110 OSCIN clock frequency, fosc, to the CAN bit time
as described in the HI-3110 data sheet.
BRP bits <5:0>
000000: BRP=1
000001: BRP=2
000010: BRP=3
000011: BRP=4
etc.
SA
M
TS P
EG
TS 2
E -2
TS G2
E -1
TS G2
E -0
TS G1
E -3
TS G1
E -2
TS G1
EG -1
10
111111: BRP=64
CANBTR1
(Address 0x8031)
7 6
MSB
5
4
3
2
1
0
LSB
CANBTR1 configures the CAN protocol bit timing segments in terms of time quanta (Tq) and sets the number of
sampling points.
Bit
Name
R/W
Default Description
7
SAMP
R/W
0
This bit configures how many samples are taken per bit. 1 = three samples/bit, 0 = one
sample/bit. Bit sampling occurs at the end of Phase Seg 1.
5:0
TSEG2-2:0
R/W
0
Time segment 2 length. Tseg2 = Phase Seg2 of the CAN bit timing specification. Bits
TSEG2-2:0 specify the number of time quanta in Phase Seg2.
Note: ARINC825 states that there shall be only one sample per bit
Note: Not all combinations are valid, since Phase Seg2 must be greater than SJW.
TSEG2 bits <2:0>
000: Not valid
001: TSeg2 = 2 Tq clock cycles
010: TSeg2 = 3 Tq clock cycles
etc.
111: TSeg2 = 8 Tq clock cycles
HOLT INTEGRATED CIRCUITS
13
HI-3200, HI-3201
CANBTR1 cont.
Bit
Name
R/W
5:0
TSEG1-3:0
R/W
Default Description
0
Time segment 1 length. Tseg1 = Prop Seg + Phase Seg 1 of the CAN protocol bit timing
specification. Bits TSEG1-3:0 specify the number of time quanta in Prop Seg + Phase Seg1.
Note: Not all combinations are valid since Prop Seg = Phase Seg1 >= Phase Seg2. The CAN
protocol states that the minimum number of Tq in a bit time shall be 8.
Note ARINC 825 states that the sample point shall not be less than 75% of the bit time. In this
case, TSeg1 should be a minimum of 5Tq for Phase Seg2 (TSeg2) = 2Tq and SJW = 1Tq.
TSEG2 bits <2:0>
0000: Not valid
0001: TSeg1 = 2 Tq clock cycles
0010: TSeg1 = 3 Tq clock cycles
etc.
1111: TSeg1 = 16 Tq clock cycles
HI-3200 Operational Status Information
R
EA
AC DY
T
SA IVE
F
R E
AM
PR BU
O S
AU G Y
TO
IN
IT
H
I-3
11
0
The Master Status Register may be read at any time to determine the current operational state of the HI-3200:
X
MASTER STATUS REGISTER
(Address 0x800E)
Bit Name
R/W
7 6
MSB
5
4
3
2
1
0
LSB
Default Description
7
READY
R
0
This bit is high, when the READY output pin is high, indicating that the part is able to accept and
respond to host CPU SPI commands
6
ACTIVE
R
0
This bit is high after RUN is asserted and the HI-3200 is in normal operating mode.
5
SAFE
R
0
This bit goes high when the part enters safe mode as a result of a Built-in Self-test fail or autoinitialization fail.
4
RAM BUSY
R
0
This is high during the time the RAM Integrity Check is running and RAM is clearing
3
PROG
R
0
Indicates that the HI-3200 is currently in the EEPROM programming cycle. Note that READY
stays low until the cycle is complete.
2
AUTOINIT
R
0
The HI-3200 is currently loading internal memory, registers and look-up tables from the Autoinitialization EEPROM
1
-
R
0
Not used
0
HI-3110
R
0
The HI-3200 has detected the presence of an HI-3110 device connected to the CAN SPI
port. Note: Only valid when RUN = 1 and CANTX and/or CANRX are enabled. After HI-3110
initialization this bit is not updated in Mode 6 or 7.
HOLT INTEGRATED CIRCUITS
14
HI-3200, HI-3201
ARINC 429 RECEIVE OPERATION
The HI-3200 can receive ARINC 429 messages from up to eight ARINC 429 receive buses. External
analog line receivers handle the physical layer connection
ARINC 429 Receive Channel Configuration
EN
A
R BL
AT E
PA E
R
D ITY
EC E
N
SD OD
10 ER
SD
9
FF
S1
FF
S0
Each of the eight possible ARINC 429 Receive channels is configured using its own Control Register. Register address
0x8010 controls ARINC 429 Receive channel #0, register address 0x8011 controls channel #1 and so on. ARINC 429
Receive Control Registers may be read at any time, but can only be written when the device is in the IDLE state (RUN
input = “0”, READY output = “1”).
ARINC 429 RX CONTROL REGISTER 0 - 7
(Address 0x8010 - 0x8017)
7 6
MSB
5
4
3
2
1
0
LSB
Bit Name
R/W
7
ENABLE
R/W
0
This bit must be set to a “1” to enable ARINC 429 data reception on this channel.
6
HI / LO
R/W
0
Selects the ARINC 429 bit rate for the ARINC 429 receive channel. A “0” selects high-speed
(100Kb/s) and a “1” selects low-speed (12.5Kb/s).
5
PARITYEN
R/W
0
When this bit is a one, the 32nd received ARINC bit is overwritten with a parity flag. The flag bit
is set to a zero when the received ARINC word, including its parity bit has an odd number of
ones. When PARITYEN is a zero, all 32-bits are received without parity checking.
4
DECODER
R/W
0
When DECODER is a “1”, bits 9 and 10 of ARINC 429 words received on this channel must
match the SD9 and SD10 bits in the register. ARINC words received that do not match the SD
conditions are ignored.
3
SD10
R/W
0
If DECODER is set to a “1”, then this bit must match the received ARINC word bit 10 for the
word to be accepted.
2
SD9
R/W
0
If DECODER is set to a “1”, then this bit must match the received ARINC word bit 9 for the
word to be accepted.
R/W
0
FFS1 and FFS0 define when this channel’s FIFO Flag is set, as shown below. The FIFO Flag
will be set in the ARINC 429 Muxed FIFO Flags Register (0x800C). Bit 0 is receive channel 0
FIFO Flag, bit 1 is receive channel 1 FIFO Flag, bit 2 is receive channel 2 FIFO Flag, etc.
1-0 FFS1:0
Default Description
FFS1
FFS0
0
0
FLAG set condition
FLAG never set
0
1
Set FLAG if FIFO NOT EMPTY bit = “1”
1
0
Set FLAG if FIFO > Threshold value
1
1
Set FLAG is FIFO FULL bit “1”
HOLT INTEGRATED CIRCUITS
15
HI-3200, HI-3201
ARINC 429 Received Data Management
The HI-3200 supports eight ARINC 429 receive buses
using on-chip receivers to handle the protocol validation.
The eight ARINC 429 RX Control Registers, ARXC0 - 7,
define the characteristics of each receive channel.
A look-up table is used to enable an interrupt on receipt of a
new ARINC 429 message. Look-up table bit positions preloaded with a “1” will cause an Interrupt to be generated.
When an ARINC 429 message is received by the HI-3200
on any bus, it is checked for protocol compliance. Messages with incorrect encoding are rejected.
When a message is received that triggers an Interrupt, that
channel’s Interrupt bit is set in the ARINC 429 Receive
Pending Interrupt Register. If this bit is unmasked in the
ARINC 429 Receive Interrupt Mask Register, the AINT
output pin is asserted. The label number of the ARINC 429
message causing the interrupt is loaded into that channel’s ARINC 429 Receive Interrupt Address Register
(AIAR0 - AIAR7).
The HI-3200 contains an 8K byte memory for storing
ARINC 429 received data. The memory is organized by
channel number and ARINC 429 label value. Four bytes of
memory are dedicated to each channel / label to store the
32-word ARINC 429 message.
Because the ARINC Receive Memory is organized by
label value, it is not necessary to store the received label
value (first eight bits of the ARINC message) in the
memory. Instead, the first byte is used to store a status
byte.
The ARINC 429 receive function of the HI-3200 is activated by setting the A429RX bit in the Master Control
Register.
The six active bits of the status byte are set to “1” when a
new ARINC word is stored in the memory. These bits flag
the ARINC word as new when the location is interrogated
by the host CPU, any of the four ARINC 429 transmit
schedulers or the CAN Bus transmit scheduler.
ARINC 429 Received Data Memory Organization
0x1FFF
Block 2048
Channel 7, Label FF
0x1FFC
0x000B
Block 3
Channel 0, Label 02
0x0008
0x0007
Block 2
Channel 0, Label 01
0x0003
ARINC data byte 4
0x0002
ARINC data byte 3
Block 1
Channel 0, Label 00
0x0001
ARINC data byte 2
0x0000
Status Byte
0x0004
0x0003
0x0000
Etc.
HOLT INTEGRATED CIRCUITS
16
HI-3200, HI-3201
ARINC 429 Received Data Interrupt Look-Up Table
0x7BFF
0x7BE0
0x7B3F
0x7B20
0x7B1F
0x7B00
Label = 0xF8
Label = 0xFF
Interrupt Look-Up Table
Channel 7
Label = 0x08
Interrupt Look-Up Table
Channel 1
Label = 0x0F
Interrupt Look-Up Table
Channel 0
7
6
5
4
3
2
1
0
Label = 0x00
Label = 0x07
Label = 0x01
STATUS BYTE
X
N
N
EW
H
EW OS
N CA T
EW N
N TX
EW 3
N TX
EW 2
N TX
EW 1
TX
0
ARINC 429 Received Data Status Byte Definition
X
7 6
MSB
5
4
3
2
1
0
LSB
Bit Name
R/W
Default Description
7
-
R/W
0
Not used
6
-
R/W
0
Not used
5
NEWHOST
R/W
0
This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when
the host CPU executes SPI instruction 0xC0 - 0xFF to read the block.
4
NEWCAN
R/W
0
This bit is set when a new ARINC 429 word is received and stored in this block.It is reset when
the CAN Transmit scheduler reads any bytes from the block.
3
NEWTX3
R/W
0
This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #3 reads any bytes from the block.
2
NEWTX2
R/W
0
This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #2 reads any bytes from the block.
1
NEWTX1
R/W
0
This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #1 reads any bytes from the block.
0
NEWTX0
R/W
0
This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #0 reads any bytes from the block.
HOLT INTEGRATED CIRCUITS
17
HI-3200, HI-3201
ARINC 429 Received Data Log FIFO
A 1K x 8 block of memory located between 0x3000 and
0x33FF is reserved for a set of eight ARINC 429 received
data FIFOs. There is one FIFO for each ARINC 429
received data channel. Each FIFO can hold up to 32 ARINC
429 32-bit messages.
The FIFOs are empty following reset. All three status
registers are cleared. When an ARINC 429 message is
written to a FIFO, its FIFO NOT EMPTY bit is set to a “1”.
When the FIFO contains more than the user-defined
number of messages as programmed in the ARINC FIFO
THRESHOLD VALUE register, its FIFO THRESHOLD bit is
set. If the FIFO is allowed to accumulate 32 messages, its
FIFO FULL bit is set. Once a FIFO is full, subsequent
messages continue to be written to the FIFO, and the oldest
message is lost.
A look-up table driven filter defines which ARINC 429
messages are stored in each FIFO. The look-up table is
initialized by the user with a “1” for each bit position
corresponding to a selected channel / label combination.
The look-up table is located at memory address 0x7A00.
The user may generate an Interrupt by enabling one of the
three FIFO status register bits to assert the FLAG bit in the
Pending Interrupt Register. ARINC 429 Control Register
bits 1:0 select the condition to trigger the FLAG interrupt.
When a new ARINC 429 message is received that meets
the programmed conditions for acceptance (Enable lookup table bit = “1”), it is written into the channel’s Receive
Data FIFO. The contents of the FIFO may be read by the
host CPU using dedicated FIFO read SPI Instructions.
The FIFO feature is particularly useful if the application
wishes to accumulate sequential ARINC 429 messages of
the same label value before reading them. The regular
ARINC 429 receive data memory will, of course, overwrite
messages of the same label value if a new message is
received before the host CPU extracts the data.
The status of each channel’s FIFOs is monitored by three
FIFO status registers: FIFO NOT EMPTY, FIFO
THRESHOLD, and FIFO FULL. One bit of each register
reflects the current status of each FIFO.
ARINC 429 Received Data Enable Look-Up Table
0x7AFF
0x7AE0
0x7A3F
0x7A20
0x7A1F
0x7A00
Label = 0xF8
Label = 0xFF
Filter Look-Up Table
Channel 7
Label = 0x08
Filter-Look-Up Table
Channel 1
Label = 0x0F
Filter Look-Up Table
Channel 0
7
6
5
4
3
2
1
0
Label = 0x00
Label = 0x07
Label = 0x01
ARINC 429
received
message
Message 1 (32-bits)
Message 2 (32-bits)
ARINC 429 Received Data FIFO (x8)
Data read by
Host CPU
SPI Instruction
FIFO NOT EMPTY
A FNEn
FIFO THRESHOLD
AFHFn
FIFO FULL
FLAGn
Select
A FFn
ARXCn <1:0>
From
Other
Channels
0 - 32 Messages (32-bits)
HOLT INTEGRATED CIRCUITS
18
}
OR
PIR
FLAG
HI-3200, HI-3201
AF
N
AF E7
N
AF E6
N
AF E5
N
AF E4
N
AF E3
N
AF E2
N
AF E1
N
E0
ARINC 429 Received Data FIFO Status Registers
FIFO NOT EMPTY REGISTER
(Address 0x802B)
Bit Name
R/W
7 6
MSB
5
4
3
2
1
0
LSB
Default Description
AFNE7
R
0
This bit is set to “1” if FIFO #7 contains at least one ARINC 429 message
6
AFNE6
R
0
This bit is set to “1” if FIFO #6 contains at least one ARINC 429 message
5
AFNE5
R
0
This bit is set to “1” if FIFO #5 contains at least one ARINC 429 message
4
AFNE4
R
0
This bit is set to “1” if FIFO #4 contains at least one ARINC 429 message
3
AFNE3
R
0
This bit is set to “1” if FIFO #3 contains at least one ARINC 429 message
2
AFNE2
R
0
This bit is set to “1” if FIFO #2 contains at least one ARINC 429 message
1
AFNE1
R
0
This bit is set to “1” if FIFO #1 contains at least one ARINC 429 message
0
AFNE0
R
0
This bit is set to “1” if FIFO #0 contains at least one ARINC 429 message
AF
T
AF F7
T
AF F6
T
AF F5
T
AF F4
T
AF F3
T
AF F2
T
AF F1
TF
0
7
FIFO THRESHOLD REGISTER
(Address 0x802A)
7 6 5 4 3 2 1 0
LSB
MSB
Bit Name
R/W
Default Description
AFTF7
R
0
This bit is set to “1” if FIFO #7 contains > threshold number of ARINC 429 messages
6
AFTF6
R
0
This bit is set to “1” if FIFO #6 contains > threshold number of ARINC 429 messages
5
AFTF5
R
0
This bit is set to “1” if FIFO #5 contains > threshold number of ARINC 429 messages
4
AFTF4
R
0
This bit is set to “1” if FIFO #4 contains > threshold number of ARINC 429 messages
3
AFTF3
R
0
This bit is set to “1” if FIFO #3 contains > threshold number of ARINC 429 messages
2
AFTF2
R
0
This bit is set to “1” if FIFO #2 contains > threshold number of ARINC 429 messages
1
AFTF1
R
0
This bit is set to “1” if FIFO #1 contains > threshold number of ARINC 429 messages
0
AFTF0
R
0
This bit is set to “1” if FIFO #0 contains > threshold number of ARINC 429 messages
AF
F
AF F7
F
AF F6
F
AF F5
F
AF F4
F
AF F3
F
AF F2
F
AF F1
FF
0
7
FIFO FULL REGISTER
(Address 0x8029)
7 6
MSB
5
4
3
2
1
0
LSB
Bit Name
R/W
Default Description
7
AFFF7
R/W
0
This bit is set to “1” if FIFO #7 contains 32 ARINC 429 messages
6
AFFF6
R/W
0
This bit is set to “1” if FIFO #6 contains 32 ARINC 429 messages
5
AFFF5
R/W
0
This bit is set to “1” if FIFO #5 contains 32 ARINC 429 messages
4
AFFF4
R/W
0
This bit is set to “1” if FIFO #4 contains 32 ARINC 429 messages
3
AFFF3
R/W
0
This bit is set to “1” if FIFO #3 contains 32 ARINC 429 messages
2
AFFF2
R/W
0
This bit is set to “1” if FIFO #2 contains 32 ARINC 429 messages
1
AFFF1
R/W
0
This bit is set to “1” if FIFO #1 contains 32 ARINC 429 messages
0
AFFF0
R/W
0
This bit is set to “1” if FIFO #0 contains 32 ARINC 429 messages
HOLT INTEGRATED CIRCUITS
19
AM
F
AM F7
F
AM F6
F
AM F5
F
AM F4
F
AM F3
F
AM F2
F
AM F1
FF
0
HI-3200, HI-3201
ARINC 429 Muxed FIFO Flags Register
(Address 0x800C)
Bit Name
7 6
MSB
R/W
5
4
3
2
1
0
LSB
Default Description
7
AMFF7
R
0
This bit gives the FIFO Flag Status for ARINC 429 Receive Channel 7. The FIFO Flag Status is
set according to the value of the FFS[1:0] bits in the ARINC 429 Rx Control Register 7
6
AMFF6
R
0
This bit gives the FIFO Flag Status for ARINC 429 Receive Channel 6. The FIFO Flag Status is
set according to the value of the FFS[1:0] bits in the ARINC 429 Rx Control Register 6
5
AMFF5
R
0
This bit gives the FIFO Flag Status for ARINC 429 Receive Channel 5. The FIFO Flag Status is
set according to the value of the FFS[1:0] bits in the ARINC 429 Rx Control Register 5
4
AMFF4
R
0
This bit gives the FIFO Flag Status for ARINC 429 Receive Channel 4. The FIFO Flag Status is
set according to the value of the FFS[1:0] bits in the ARINC 429 Rx Control Register 4
3
AMFF3
R
0
This bit gives the FIFO Flag Status for ARINC 429 Receive Channel 3. The FIFO Flag Status is
set according to the value of the FFS[1:0] bits in the ARINC 429 Rx Control Register 3
2
AMFF2
R
0
This bit gives the FIFO Flag Status for ARINC 429 Receive Channel 2. The FIFO Flag Status is
set according to the value of the FFS[1:0] bits in the ARINC 429 Rx Control Register 2
1
AMFF1
R
0
This bit gives the FIFO Flag Status for ARINC 429 Receive Channel 1. The FIFO Flag Status is
set according to the value of the FFS[1:0] bits in the ARINC 429 Rx Control Register 1
0
AMFF0
R
0
This bit gives the FIFO Flag Status for ARINC 429 Receive Channel 0. The FIFO Flag Status is
set according to the value of the FFS[1:0] bits in the ARINC 429 Rx Control Register 0
ARINC 429 FIFO Threshold Value Register
Threshold
FIFO THRESHOLD VALUE
(Address 0x8021)
Threshold Value
0
0
0
7 6
MSB
5
Default = 0x10
4
3
2
1
0
LSB
Description
00000
Threshold flag is set if at least 1 message is in FIFO (Same as FIFO NOT EMPTY FLAG)
00001
Threshold flag is set if more than one message are in the FIFO
00010
Threshold flag is set if more than two messages are in the FIFO
00011
Threshold flag is set if more than three messages are in the FIFO
10000
Threshold flag is set if more than sixteen messages are in the FIFO (default)
11111
Threshold flag is set if 32 messages are in the FIFO (Same as FIFO FULL FLAG)
ARINC 429 Loop-back Self-Test
The HI-3200 includes an ARINC 429 loop-back feature,
which allows users to exercise the ARINC 429 transmit and
receive channels for self-test purposes. The ARINC 429
Loop-Back register, ALOOP defines which receiver
channels are in loop-back mode. When a “1” is
programmed in the ALOOP bit position for a receiver, then
its ARINC 429 bus connection to the external pins is broken
and instead the input is connected to one of the four ARINC
429 transmit channels. Transmit channel 0 is connected to
receive channel 0 and 1, transmit channel 1 is connected to
receive channels 2 and 3, and so on.
When in loop-back mode, incoming ARINC 429 messages
are ignored by the HI-3200. When running in loop-back
mode the ARINC 429 transmit pins may be disabled by
pulling the TXMSK input high. This prevents test messages
from being output to the external ARINC 429 transmit
buses.
HOLT INTEGRATED CIRCUITS
20
AL
O
AL OP
O 7
AL OP
O 6
AL OP
O 5
AL OP
O 4
AL OP
O 3
AL OP
O 2
AL OP
O 1
O
P0
HI-3200, HI-3201
ARINC 429 LOOPBACK
(Address 0x8022)
7 6
MSB
5
4
3
2
1
0
LSB
Bit Name
R/W
Default Description
7
ALOOP7
R/W
0
This bit is set to “1” to loop-back transmit channel 3 to receiver 7
6
ALOOP6
R/W
0
This bit is set to “1” to loop-back transmit channel 3 to receiver 6
5
ALOOP5
R/W
0
This bit is set to “1” to loop-back transmit channel 2 to receiver 5
4
ALOOP4
R/W
0
This bit is set to “1” to loop-back transmit channel 2 to receiver 4
3
ALOOP3
R/W
0
This bit is set to “1” to loop-back transmit channel 1 to receiver 3
2
ALOOP2
R/W
0
This bit is set to “1” to loop-back transmit channel 1 to receiver 2
1
ALOOP1
R/W
0
This bit is set to “1” to loop-back transmit channel 0 to receiver 1
0
ALOOP0
R/W
0
This bit is set to “1” to loop-back transmit channel 0 to receiver 0
ARINC 429 Bit ordering
ARINC 429 messages consist of a 32-bit sequence as
shown below. The first eight bits that appear on the ARINC
429 bus are the label byte. The next twenty three bits
comprise a data field which presents data in a variety of
formats defined in the ARINC 429 specification. The last bit
transmitted is an odd parity bit.
The ARINC 429 specifies the MSB of the label as ARINC bit
1. Conversely, the data field MSB is bit 31. So the bit
significance of the label byte and data fields are opposite.
The HI-3200 may be programmed to “flip” the bit ordering of
the label byte as soon as it is received and immediately prior
to transmission. This is accomplished by setting the AFLIP
bit to a “1” in the Master Control Register. Note that once the
label byte has been flipped, the HI-3200 handles the flipped
data byte “post-flip” for the purpose of label interrupt
matching, filtering and storage.
The HI-3200 stores the received message as four bytes.
The bytes are stored in memory in little-endian order. That
is to say, the label byte (or status byte) is stored at the
lowest memory address, the byte representing received
bits 9 through 16 is stored at the next address, the byte
representing bits 17 through 24 at the next address and the
byte representing bits 25 though 32 at the highest address.
ARINC 429 Message as received / transmitted on the ARINC 429 serial bus
3
4
5
6
7
9 10 11 12 13 14 15 16
8
17 18 19 20 21 22 23 24
25 26 27 28 29 30 31 32
time
ARINC 429 Message as stored in HI-3200 memory
Byte 3
32 31 30 29 28 27 26 25
32 31 30 29 28 27 26 25
Byte 2
24 23 22 21 20 19 18 17
24 23 22 21 20 19 18 17
Byte 1
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
Byte 0
1
2
3
4
5
6
AFLIP = “0”
Y
PA
R
I
2
SD
SD
1
MSB
DATA
IT
LSB
LSB
LABEL
I
MSB
7
8
8
7
6
5
4
3
AFLIP = “1”
HOLT INTEGRATED CIRCUITS
21
2
1
HI-3200, HI-3201
ARINC 429 Bit Monitor Pins
The HI-3200 has the capability of externally monitoring any
ARINC 429 received payload bit through the pins
ARXBIT[7:0] (Note: The HI-3200 provides external
monitoring of two bits through pins ARXBIT1 and ARXBIT0,
whereas the HI-3201 provides external monitoring of eight
bits through pins ARXBIT7 to ARXBIT0). When the
appropriate ARINC 429 receiver is enabled and the target
label is received, the monitored bit value will be reflected on
the pin. This allows the user to monitor any ARINC 429
AR
X
AR BIT
X 7
AR BIT
X 6
AR BIT
X 5
AR BIT
X 4
AR BIT
X 3
AR BIT
X 2
AR BIT
XB 1
IT
0
received payload bit without performing any host SPI reads.
The following registers configure the functionality of these
monitor pins. Note that all these control register bits are
reset to zero.
PINS ARXBIT[7:0] REGISTER
(Address 0x805F)
Bit Name
R/W
7:0 ARXBIT[7:0]
R/W
7 6
MSB
5
4
3
2
1
0
LSB
Default Description
0
AR
X
AR CR
X 17
AR CR
X 16
AR CR
X 15
AR CR
X 14
AR CR
X 13
AR CR
X 12
AR CR
XC 11
R
10
the
These bits reflect the value of the corresponding pins ARXBIT[7:0]. After reset, all values are
zero. When a monitored ARINC 429 bit changes, this register is updated with the value, which
is reflected on the corresponding pin. The purpose of this register is to allow the user to preset
ARXBIT values after chip reset.
PIN ARXBIT0 CONFIGURATION REGISTER 1
(Address 0x8060)
7 6
MSB
5
4
3
2
1
0
LSB
R/W
Default Description
7:5 ARXCR1[7:5]
R/W
0
These bits select which receive channel (0 through 7) will have bits monitored and reflected on
the pin ARXBIT0.
4:0 ARXCR1[4:0]
R/W
0
These bits select which bit (8 through 31) of the ARINC payload will be reflected on the pin
ARXBIT0. The receiver is specified by bits ARX0CR1[7:5] and the target label is specified
by pin ARXBIT0 Configuration Register 2 described below. Note that bits 0 through 7 of the
ARINC payload are not monitored and selecting these bits results in no effect.
AR
X
AR CR
X 27
AR CR
X 26
AR CR
X 25
AR CR
X 24
AR CR
X 23
AR CR
X 22
AR CR
XC 21
R
20
Bit Name
PIN ARXBIT0 CONFIGURATION REGISTER 2
(Address 0x8061)
Bit Name
R/W
7:0 ARXCR2[7:0]
R/W
7 6
MSB
5
4
3
2
1
0
LSB
Default Description
0
These bits select which label (0 through 255) will have bits monitored and reflected on
the pin ARXBIT0. The receive channel and specific bits monitored are specified in ARXBIT0
Configuration Register 1 described above.
PINS ARXBIT1 Through ARXBIT7 CONFIGURATION REGISTERS
(Addresses 0x8062 to 0x806F)
Each pin ARXBIT1 through ARXBIT7 are also specified by a pair of configuration registers similar to ARXBIT0 described above.
Functionality is exactly the same. The register addresses for each pin specification are listed in the Register Map section (see page
11). Note that HI-3200 provides external monitoring of two bits through pins ARXBIT1 and ARXBIT0, whereas the HI-3201 provides
external monitoring of eight bits through pins ARXBIT7 to ARXBIT0.
HOLT INTEGRATED CIRCUITS
22
HI-3200, HI-3201
CAN BUS RECEIVE OPERATION
The HI-3200 can receive CAN frames from a single CAN bus using an external HI-3110 IC to handle the CAN bus
protocol and physical layer connection
CAN Received Data Management
The HI-3200 interfaces to a CAN bus using an external HI3110 CAN Controller / Transceiver IC. Communication
between the HI-3200 and HI-3110 is handled by a
dedicated high speed serial SPI link. Configuration
parameters are automatically downloaded to the HI-3110
following a positive edge of the RUN input signal.
The HI-3110 handles all aspects of the CAN protocol as well
as the physical layer interface to the CAN bus.
Received CAN frames are passed to the HI-3200 for
filtering and storage. Each incoming frame’s ID and first two
data bytes is compared against a bank of up to 256 userdefined acceptance filters. If the frame meets the filter’s
acceptance criteria, it is stored in the CAN Received Data
Memory. Each acceptance filter consists of a 6-byte match
register and 6-byte mask. A frame is accepted if all
unmasked bits match the corresponding bits in the frame.
The frame is then written into the CAN received data
memory location corresponding to the filter number.
Mask bits are defined as 1 = care and 0 = don’t care. So for
any given CAN frame bit to generate a filter pass condition,
the received frame bit must equal the filter bit if the mask bit
is “1”, or any value if the mask bit is “0”.
The number of filters active at any time is specified by
writing a “1” into the corresponding bit position of the CAN
Filter Enable look-up table. Only those filters identified as
active in the table will be used to determine whether the
frame is accepted.
A CAN Receive Interrupt look-up table mirrors the active
filter table. When a frame is accepted, and its
corresponding Interrupt enable look-up bit is a one, then the
CAN Interrupt bit is set in the Pending Interrupt Register. If
the Interrupt Mask Register does not mask the CAN
Interrupt, then the INT output signal will be asserted on
frame reception and the CAN filter number will be loaded
into the Interrupt Address Register.
It is possible that a received CAN frame may meet the
acceptance criteria for more than one filter. In this case,
only the first (lowest filter number) filter is used to qualify
and store the incoming CAN frame.
The CAN Filter Enable look-up table, CAN Interrupt Enable
look-up table, Filter and Mask definition tables must be
loaded prior to turning on the CAN receiver, either via the
host CPU interface or from the auto-initialization EEPROM.
CAN frames are stored as sixteen-byte blocks as shown in
the following diagram. Each block starts with a CAN frame
Status Byte.
CAN Bus Received Data Filter Enable Look-Up Table
Filter 0xF8
Filter 0xFF
0x79DF
0x79C0
CAN Bus Received Data Filter
Enable Look-Up Table
Filter 0x08
Filter 0x0F
7
6
5
4
3
2
1
0
Filter 0x00
Filter 0x07
HOLT INTEGRATED CIRCUITS
23
Filter 0x01
HI-3200, HI-3201
CAN Bus Received Data Interrupt Enable Look-Up Table
Filter 0xF8
Filter 0xFF
0x79FF
0x79E0
CAN Bus Received Data Interrupt
Enable Look-Up Table
Filter 0x08
Filter 0x0F
7
6
5
4
3
2
1
Filter 0x07
0
Filter 0x00
Filter 0x01
CAN Received Data Filter, Filter Mask and Data Storage Organization
CAN data byte 2
0x3FFF
0x3FF4
Mask 255
CAN data byte 1
Acceptance Filter 255
ID6 to ID0, RTR
ID14 to ID7
ID20 to ID18, SRR, IDE, ID17 to ID15
ID28 to ID21
CAN
FILTER / MAP
TABLE
(3072 x 8)
0x341E
0x3418
0x3412
0x340C
0x3406
0x3400
Mask 2
CAN data byte 2
Acceptance Filter 2
CAN data byte 1
Mask 1
ID6 to ID0, RTR
Acceptance Filter 1
ID14 to ID7
Mask 0
ID20 to ID18, SRR, IDE, ID17 to ID15
Acceptance Filter 0
ID28 to ID21
CAN data byte 8
CAN data byte 7
0x2FFF
Block 255
Filter 255 Frame
CAN data byte 6
0x2FF0
CAN data byte 5
CAN
FILTER
CAN
RECEIVE
DATA
RAM
(4K x 8)
CAN data byte 4
CAN data byte 3
CAN data byte 2
CAN data byte 1
0x202F
Block 2
Filter 2 Frame
0x2020
0x201F
r0, r1,DLC3 to DLC0
ID6 to ID0, RTR
Block 1
Filter 1 Frame
0x2010
0x200F
ID14 to ID7
ID20 to ID18, SRR, IDE, ID17 to ID15
Block 0
Filter 0 Frame
0x2000
ID28 to ID21
Time Tag Lower Byte
Time Tag Upper Byte
CAN Frame Status Byte
HOLT INTEGRATED CIRCUITS
24
HI-3200, HI-3201
X
N
CAN RECEIVED DATA BLOCK STATUS BYTE
N
EW
H
EW OS
N CA T
EW N
N TX
EW 3
N TX
EW 2
N TX
EW 1
TX
0
CAN Bus Received Data Status Byte Definition
5
4
X
7 6
MSB
3
2
1
0
LSB
Bit Name
R/W
Default Description
7
-
R/W
0
Not used
6
-
R/W
0
Not used
5
NEWHOST
R/W
0
This bit is set when a new CAN frame is received and stored in this block. It is reset when
the host CPU executes SPI instruction 0x9C to read the block.
4
NEWCAN
R/W
0
This bit is set when a new CAN frame is received and stored in this block. It is reset when
the CAN Transmit scheduler reads any bytes from the block.
3
NEWTX3
R/W
0
This bit is set when a new CAN frame is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #3 reads any bytes from the block.
2
NEWTX2
R/W
0
This bit is set when a new CAN frame is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #2 reads any bytes from the block.
1
NEWTX1
R/W
0
This bit is set when a new CAN frame is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #1 reads any bytes from the block.
0
NEWTX0
R/W
0
This bit is set when a new CAN frame is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #0 reads any bytes from the block.
HOLT INTEGRATED CIRCUITS
25
HI-3200, HI-3201
ARINC 429 TRANSMIT OPERATION
The HI-3200 has four on-board ARINC 429 transmit channels which directly drive ARINC 429 differential line drivers
such as the Holt HI-8570. ARINC 429 words may be written to the transmitters either directly, using an SPI instruction,
or be generated automatically using the four ARINC 429 message schedulers.
ARINC 429 Transmit Channel Configuration
U
R
ARINC 429 TX CONTROL REGISTER 0 - 3
(Address 0x8018 - 0x801B)
Bit Name
R/W
H
N
/
I / ST
LO OP
PA
R
EV ITY
E /D
SK N / AT
IP OD A
D
Each of the four available ARINC 429 Transmit channels is configured using its own register. Register address 0x8018
controls ARINC 429 Transmit channel #0, register address 0x8019 controls channel #1 and so on. The ATXCn
registers may be written or read at any time.
7 6
MSB
5
4
3
X
X
X
2
1
0
LSB
Default Description
7
RUN / STOP
R/W
0
When zero, transmission from this ARINC 429 transmit channel is suspended after the
currently transmitting label is sent. When this bit is taken high, transmission starts at the
beginning of the descriptor table for this channel.
6
HI / LO
R/W
0
Selects the transmission rate for the ARINC 429 transmit channel. A “0” selects high-speed
(100Kb/s) and a “1” selects low-speed (12.5Kb/s).
5
PARITY / DATA R/W
0
When this bit is a one, the 32nd transmitted ARINC bit is overwritten with a parity flag. When
this bit is a zero, all 32-bits are transmitted as data.
4
EVEN / ODD
R/W
0
When PARITY / DATA is a “1”, this bit defines whether th 32nd transmitted bit is set for Even or
Odd Parity. A “1” selects even parity and a “0” selects odd parity.
3
SKIP
R/W
0
When set a “1’ instructs the transmit sequencer to wait for the next Repetition Rate Counter
rollover before beginning a new transmission cycle. A “0” causes an immediate restart of the
cycle following completion of the prior cycle.
2
-
R/W
0
Not Used
1
-
R/W
0
Not Used
0
-
R/W
0
Not Used
HOLT INTEGRATED CIRCUITS
26
HI-3200, HI-3201
ARINC 429 Transmit Scheduler
Each of the four ARINC 429 transmit channels has its
own transmit controller. The controller is userprogrammed to output ARINC labels in a predefined
order and repetition rate. A sequence of up to 256 ARINC
labels may be transmitted before repeating the sequence.
A descriptor table with up to 256 entries (descriptors) is
compiled by the user to define the sequence of ARINC
429 messages transmitted on each channel. When the
RUN/STOP bit in the ARINC TX Control Register is
asserted, the controller compiles the first 32-bit ARINC
word from the instructions given by the first descriptor
and then transmits it. A Transmit Sequence Pointer then
increments to the next descriptor in the table and the
process is repeated for Descriptor number 2.
ARINC 429 messages continue to be compiled and
transmitted until the last descriptor in the table. The end
of the table is marked by a special descriptor if not all 256
entries are needed. The Sequence Pointer is then reset
to zero.
A Repetition Rate Counter is used to time the start of the
next transmission cycle.
The user is responsible for construction of the descriptor
table and for setting the Repetition Rate prior to asserting
RUN/STOP. Facilities exist for immediate cycle repetition
and for single-cycle operation.
The byte content of each ARINC 429 message
transmitted is user defined by the descriptor contents.
Data bytes may be sourced from the host CPU / autoinitialization EEPROM (immediate data) or from the
ARINC 429 receive memory (ARINC indexed) or CAN
bus receiver memory (CAN indexed). This allows
received ARINC data to be re-transmitted on another bus
with or without filtering, label byte re-assignment or data
modification. It allows data received on the CAN bus to
be re-formatted and re-labelled for automatic ARINC 429
transmission. It also allows data from multiple ARINC 429
receive buses and the CAN bus to be re-packetized into
new ARINC 429 transmitted messages.
Conditional transmission control allows sequenced words
to be skipped if no new data is available.
Each ARINC 429 transmit channel is independently
configured with its own ARINC 429 TX Control Register,
ATXCR0-3, as previously described.
ARINC 429 Transmit Descriptor table
0x47FF
0x47F8
Repetition Rate
Register
0x47F0
Sequence 255 Descriptor Frame
Sequence 254 Descriptor Frame
Repetition rate
counter
Value Byte 4
0x4028
0x4020
(Memory Addresses shown
for ARINC Tx channel 0)
0x4018
0x4010
0x4008
Sequence
pointer
000
0x4000
Sequence 5 Descriptor Frame
Action Byte 4
Sequence 4 Descriptor Frame
Value Byte 3
Sequence 3 Descriptor Frame
Action Byte 3
Sequence 2 Descriptor Frame
Value Byte 2
Sequence 1 Descriptor Frame
Action Byte 2
Sequence 0 Descriptor Frame
Value Byte 1
Action Byte 1
The value of each ARINC 429 label transmitted in the
sequence is defined by its eight-byte descriptor. The
descriptor consists of one “Action byte” and one “Value”
byte for each of the four bytes that make up the ARINC
429 transmitted label.
byte 1 also has one additional op-code to facilitate
sequence flow control.
The construction of Action and Value bytes are described in
the next section.
The four pairs of Action and Value bytes describe where
the data for each byte may be found. Different op-codes
allow the data source to be host CPU populated fixed
values, or values from specific locations within the ARINC
429 receive memory or CAN bus receive memory. Action
HOLT INTEGRATED CIRCUITS
27
HI-3200, HI-3201
Current Sequence number
TRANSMIT SEQUENCE POINTERS 0 -3
(Address 0x802C - 0x802F)
7 6
MSB
5
4
3
The transmit sequence pointer is set to zero on Master
Reset. Once the Control Register RUN / STOP bit goes
high, sequence execution begins at sequence count
zero. After the first word is sent, the pointer is
incremented by one descriptor (counts descriptor
frames).
2
1
0
LSB
This continues until the programmed sequence is
complete. The sequence pointer is then reset to the
beginning of the descriptor table and program execution
begins as soon the channel repetition rate counter time
elapses.
Channel Repetition Period
REPETITION RATE REGISTER
(Address 0x801C - 0x801F)
7 6
MSB
5
The Repetition rate register value defines the time
interval between successive starts of the programmed
transmit sequence for each ARINC 429 transmit channel.
The value is set in binary, with the LSB representing 10
ms. Repetition rate time periods may therefore be set
from 0 ms to 2.55 seconds
If the repetition rate is shorter than the minimum time
needed to transmit all ARINC 429 words in the sequence
(but not zero), the transmit sequence will begin again
immediately if the Control Register SKIP bit is a zero. If
the SKIP bit is a one, the sequencer will wait until the
next rollover of the Repetition Rate Counter before
starting a new cycle.
One-time Sequence Transmission
When the Repetition Rate Register contains zero
(default), sequence transmission occurs just once, upon
0-to-1 transition of the RUN/STOP bit in the Transmit
Control Register. One-time execution of the sequencer is
useful when transmitting ARINC 429 words directly from
the host CPU. One or more immediate-mode descriptors
can be written into the sequence table and transmitted,
then transmit values can be refreshed for the next cycle.
4
3
2
1
0
LSB
There are three ways to retrigger one-time transmission
after its previous completion:
Method 1: Reset the RUN/STOP bit in the Transmit
Control Register to zero. Sequentially write 0xFFFF then
0x0000 into the Repetition Rate Register. Initiate onetime transmission by setting the RUN/STOP bit in the
Transmit Control Register; retransmission occurs
immediately. This method can be used without affecting
the other three transmitters.
Method 2: With the RUN/STOP bit in the Transmit Control
Register already set to logic-1 by the previous one-time
sequence transmission, toggle the state of the RUN input
pin low and then high; retransmission occurs
immediately.
Method 3: With the RUN/STOP bit in the Transmit Control
Register already set to logic-1 by the previous one-time
sequence transmission, toggle the state of A429TX bit 6
in the Master Control Register low and then high;
retransmission occurs immediately.
HOLT INTEGRATED CIRCUITS
28
HI-3200, HI-3201
Op-Code
Index
Value
ARINC 429 BYTE 1 DESCRIPTOR
7 6
MSB
5
4
3
2
1
ACTION BYTE
Op-Code
0
LSB
7 6
MSB
5
4
3
2
1
0
LSB
VALUE BYTE
Index
Value
Description
000
XXXXX
XXXXXXXX
End of sequence. When op-code 000 is encountered by the sequencer
before it reaches sequence number 255, the sequencer resets to zero and
begins the next transmission cycle starting at descriptor number 0 as soon
as the repitition rate counter rolls over. Note that the descriptor table is
cleared following Master Reset, so no ARINC 429 transmissions are
possible until the sequence table has been configured.
001
XXXXX
XXXXXXXX
No-operation. This descriptor is ignored and the sequencer increments to
the next descriptor in the sequence. This opcode may be used to temporarily
suspend transmission of a particular message in the sequence, without
having to modify the remaining bit fields of the descriptor or reloading the
entire descriptor block in order to delete the entry.
010
XXXXX
LLLLLLLL
Immediate data. The value contained in the descriptor value data byte is
loaded into byte 1 (the ARINC 429 “label” byte) of the ARINC
429 label to be transmitted.
011
CCCXX
LLLLLLLL
Immediate data conditional. The NEWTXn bit corresponding to the ARINC
Data RAM location defined by channel “CCC” and label block “LLLLLLLL” is
read. LLLLLLLL is used as Byte 1 if NEWTXn is set for this or any other
conditional opcode within this descriptor frame. If NEWTXn = 0 for all
conditional op codes (within this descriptor frame) then no transmission
occurs for this frame and the sequencer increments to the next descriptor
frame. The NEWTXn bit for the referenced ARINC RAM block is reset.
100
CCCBB
LLLLLLLL
Indexed data. The value of ARINC Data RAM location defined by channel
“CCC”, label block “LLLLLLLL” and byte number “BB” is loaded into byte 1 of
the ARINC 429 label to be transmitted.
101
CCCBB
LLLLLLLL
Indexed data conditional. The NEWTXn bit corresponding to the ARINC
Data RAM location defined by channel “CCC”, label block “LLLLLLLL” and
byte number “BB” is read. The corresponding byte is used as Byte 1 if
NEWTXn is set for this or any other conditional opcode within this
descriptor frame. If NEWTXn = 0 for all conditional op codes (within this
descriptor frame) then no transmission occurs for this frame and the
sequencer increments to the next descriptor frame. The NEWTXn bit for the
referenced ARINC RAM block is reset.
110
XBBBB
NNNNNNNN
CAN byte. The value of the byte at CAN RAM address filter block
“NNNNNNNN”, byte number “BBBB” is loaded into the ARINC buffer byte 1
position to be transmitted.
111
XBBBB
NNNNNNNN
CAN byte conditional. The NEWTXn bit corresponding to the CAN RAM
address filter block “NNNNNNNN”, byte number “BBBB” is read. The
corresponding byte is used as Byte 1 if NEWTXn is set for this or any other
conditional opcode within this descriptor frame. If NEWTXn = 0 for all
conditional op codes (within this descriptor frame) then ARINC word
construction is terminated, no transmission occurs for this frame and the
sequencer increments to the next descriptor frame. The NEWTXn bit for the
referenced CAN RAM address filter block is reset.
HOLT INTEGRATED CIRCUITS
29
HI-3200, HI-3201
Op-Code
Index
Value
ARINC 429 BYTES 2 - 4 DESCRIPTOR
7 6
MSB
5
4
3
2
1
0
LSB
7 6
MSB
ACTION BYTE
Op-Code
5
4
3
2
1
0
LSB
VALUE BYTE
Index
Value
Description
000
XXXXX
XXXXXXXX
No-Op op-code. ARINC 429 word construction will be terminated and the
sequencer will move on to the next descriptor in the table.
001
XXXXX
XXXXXXXX
No-Op op-code. ARINC 429 word construction will be terminated and the
sequencer will move on to the next descriptor in the table.
010
XXXXX
LLLLLLLL
Immediate data. The value contained in the descriptor value data byte is
loaded into this byte position of the ARINC 429 32-bit message to be
transmitted.
011
CCCXX
LLLLLLLL
Immediate data conditional. The NEWTXn bit corresponding to the ARINC
Data RAM location defined by channel “CCC” and label block “LLLLLLLL” is
read. LLLLLLLL is used if NEWTXn is set for this or any other
conditional opcode within this descriptor frame. If NEWTXn = 0 for all
conditional op codes (within this descriptor frame) then no transmission
occurs for this frame and the sequencer increments to the next descriptor
frame. The NEWTXn bit for the referenced ARINC RAM block is reset.
100
CCCBB
LLLLLLLL
Indexed data. The value of ARINC Data RAM location defined by channel
“CCC”, label block “LLLLLLLL” and byte number “BB” is loaded into this byte
position of the ARINC 429 label to be transmitted.
101
CCCBB
LLLLLLLL
Indexed data conditional. The NEWTXn bit corresponding to the ARINC
Data RAM location defined by channel “CCC”, label block “LLLLLLLL” and
byte number “BB” is read. The corresponding byte is used if
NEWTXn is set for this or any other conditional opcode within this
descriptor frame. If NEWTXn = 0 for all conditional op codes (within this
descriptor frame) then no transmission occurs for this frame and the
sequencer increments to the next descriptor frame. The NEWTXn bit for the
referenced ARINC RAM block is reset.
110
XBBBB
NNNNNNNN
CAN byte. The value of the byte at CAN RAM address filter block
“NNNNNNNN”, byte number “BBBB” is loaded into the ARINC buffer byte
position to be transmitted.
111
XBBBB
NNNNNNNN
CAN byte conditional. The NEWTXn bit corresponding to the CAN RAM
address filter block “NNNNNNNN”, byte number “BBBB”
is read. The corresponding byte is used if NEWTXn is set for this or any
other conditional opcode within this descriptor frame. If NEWTXn = 0 for
all conditional op codes (within this descriptor frame) then ARINC word
construction is terminated, no transmission occurs for this frame and the
sequencer increments to the next descriptor frame. The NEWTXn bit for the
referenced CAN RAM address filter block is reset.
HOLT INTEGRATED CIRCUITS
30
HI-3200, HI-3201
ARINC 429 Immediate Transmit Option
The Host CPU may instruct the HI-3200 to transmit an
ARINC 429 message immediately using a special SPI
command. The SPI command selects the transmit
channel and provides the four bytes of data to be sent as
a 32-bit ARINC 429 message.
If the transmit sequencer for the selected channel is
active, then the new message is transmitted as soon as
the current message has been sent. The sequencer then
resumes operation at the next location in the queue.
Both the RUN input and the Master Control Register
A429TX bit must be high to enable any ARINC 429
transmission.
If the transmit channel’s sequencer is not running (ATCR
bit RUN/STOP = “0”), or the sequencer is waiting for the
repetition rate counter to rollover, then the new ARINC
429 message is transmitted without delay.
TX
3
TX RD
2 Y
TX RD
1R Y
TX DY
0R
D
Y
Table 1 lists the host CPU SPI instruction format.
X
ARINC 429 TX READY BITS REGISTER
(Address 0x800D)
X
X
X
7 6
MSB
5
4
3
2
1
0
LSB
Bit Name
R/W
Default Description
7
-
R
0
Not Used
6
-
R
0
Not Used
5
-
R
0
Not Used
4
-
R
0
Not Used
3
TX3RDY
R
1
This bit is set when Transmit Buffer 3 is empty and ready to receive the next 32-bit word for
transmission. The bit is reset when Transmit Buffer 3 is not empty.
2
TX2RDY
R
1
This bit is set when Transmit Buffer 2 is empty and ready to receive the next 32-bit word for
transmission. The bit is reset when Transmit Buffer 2 is not empty.
1
TX1RDY
R
1
This bit is set when Transmit Buffer 1 is empty and ready to receive the next 32-bit word for
transmission. The bit is reset when Transmit Buffer 1 is not empty.
0
TX0RDY
R
1
This bit is set when Transmit Buffer 0 is empty and ready to receive the next 32-bit word for
transmission. The bit is reset when Transmit Buffer 0 is not empty.
NOTE: Immediate Transmit is double-buffered so TXxRDY will remain high after a single message is loaded. If another message
is loaded prior to completion of the first message, RXxRDY will go low, indicating Not Ready status.
HOLT INTEGRATED CIRCUITS
31
HI-3200, HI-3201
CAN BUS TRANSMIT OPERATION
The HI-3200 is able to transmit CAN frames via an external HI-3110 CAN controller / transceiver IC. CAN frames
may be loaded for immediate transmission from the host CPU, or in a pre-programmed sequence using the integrated
CAN frame scheduler.
CAN BUS Transmit Scheduler
CAN frames to be transmitted are constructed and
launched from the CAN Bus transmit scheduler. The
scheduler is user programmed using a descriptor table to
output CAN frames in a predefined order and repetition
rate. To make best use of available memory space, three
different types (Type 1-3) of descriptor tables entry
formats are available. The user may mix descriptor types
in the table.
words to be skipped if no new data is available. CAN
frames are constructed and transmitted until an end of
sequence marker or RAM location 0x79BF is reached.
Note that if 0x79BF is reached before the frame is
completely constructed, that frame will be discarded.
Note that because the CAN bus bandwidth is shared
between all terminals on the bus, sufficient bandwidth to
transmit the entire programmed sequence of frames may
not be available in the time slot programmed. In such
circumstances the user may choose to repeat the
sequence immediately upon completion, or wait until the
next multiple of the programmed repetition rate elapses.
The CAN Indentifier ID and data byte content of each
frame transmitted is user defined and may be sourced
from the host CPU / auto-initialization EEPROM
(immediate data) or bytes from the ARINC 429 receive
memory (ARINC indexed) or CAN bus receiver memory
(CAN indexed). This allows received ARINC and / or CAN
bus data to be re-formated and re-transmited on the CAN
bus. Conditional transmission control allows sequenced
R
U
N
SK / S
IP TO
P
C
O
SC
_M
AS
K
The CAN sequencer operation is controlled by the CAN
Transmit control Register:
CAN TRANSMIT CONTROL REGISTER
(Address 0x8032)
Bit Name
R/W
7 6
MSB
5
X
X
X
X
X
4
3
2
1
0
LSB
Default Description
7
RUN / STOP
R/W
0
When zero, transmission from the CAN Bus transmit channel is suspended after the
currently transmitting frame is sent. When this bit is taken high, transmission starts at the
beginning of the descriptor table.
6
SKIP
R/W
0
When set to “1” instructs the transmit sequencer to wait for the next Repetition Rate Counter
rollover before beginning a new transmission cycle. A “0” causes an immediate restart of the
cycle following completion of the prior cycle.
5
COSC_MASK R/W
0
When set to “1” this bit masks off the COSC pin.
4
-
R/W
0
Not Used
3
-
R/W
0
Not Used
2
-
R/W
0
Not Used
1
-
R/W
0
Not Used
0
-
R/W
0
Not Used
CAN TRANSMIT SEQUENCE POINTER
(Address 0x803E/F)
Current Sequence pointer (MSB)
Current Sequence pointer (LSB)
7 6
MSB
7 6
MSB
5
The transmit sequence pointer is set to 0x6000 on Master
Reset. Once the RUN / STOP bit goes high, sequence
execution begins at sequence count zero (Memory
Address 0x6000). After the first word is sent, the pointer
is incremented to the address of the next descriptor in the
4
3
2
1
0
LSB
5
4
3
2
1
0
LSB
sequence table. This continues until the programmed
sequence is complete. The sequence pointer is then
reset to zero and program execution begins as soon the
CAN repetition rate counter time elapses.
HOLT INTEGRATED CIRCUITS
32
HI-3200, HI-3201
Channel Repetition Period
CAN REPETITION RATE REGISTER
(Address 0x8033)
7 6
MSB
5
4
3
The Repetition rate register value defines the time
interval between successive starts of the programmed
CAN transmit sequence. The value is set in binary, with
the LSB representing 10 ms.
If the repetition rate is shorter than the minimum time
needed to transmit all CAN frames in the sequence (but
not zero), the transmit sequence will begin again
immediately if the CAN Control Register SKIP bit is a
zero. If the SKIP bit is a one, the sequencer will wait until
the next rollover of the Repetition Rate Counter before
starting a new cycle.
2
1
0
LSB
When the Repetition Rate counter is programmed to zero
(default), the transmit sequence shall execute one time
only. A zero - to - one transition of the RUN/STOP bit will
cause the transmit sequence to start. One-time execution
of the sequencer is useful when transmitting CAN frames
directly from the host CPU. One or more immediatemode (Type 1) descriptors can be written into the
sequence table, transmitted, and then refreshed for the
next cycle.
CAN Bus Transmit Descriptor Table
0x79BF
Repetion Rate
Register
End of Sequence marker
Transmit Frame Descriptor n
Repetition rate
counter
Descriptor Byte n
Transmit Frame Descriptor 5
Transmit Frame Descriptor 4
Sequence
pointer
0x6000
Transmit Frame Descriptor 3
Descriptor Byte 2
Transmit Frame Descriptor 2
Descriptor Byte 1
Transmit Frame Descriptor 1
Descriptor Header
}
0 - 24 Bytes
Transmit Frame Descriptor 0
The contents of each CAN frame transmitted in the
sequence is defined by its Frame Descriptor. Each
descriptor consists of one “Descriptor Header Byte” and
from 0 to 24 additional descriptor bytes depending upon,
the descriptor type (type 1 - 3) and the data payload
length. A special descriptor header marks the end of the
descriptor table.
The three different descriptor types allow the user to
make best use of the available descriptor table memory
space while still allowing complete flexibility in defining
frame content and data source. The Descriptor header
byte is of a common format for all three descriptor types.
The CAN Transmit sequence pointer uses information in
the header byte to determine the length of the descriptor
and thus the address of the next descriptor block in the
sequence table.
HOLT INTEGRATED CIRCUITS
33
HI-3200, HI-3201
CAN TRANSMIT DESCRIPTOR HEADER BYTE
DLC
RT
R
Type
r1
7 6
MSB
5
4
3
2
1
0
LSB
Type
RTR
DLC
Description
00
X
XXXX
End of sequence marker.
01
0
NNNN
Type 1 descriptor CAN Data frame. Data Length Code (DLC) indicates the number of data bytes
in the CAN frame 0 - 8. DLC values >8 always have eight data bytes. The number of descriptor
bytes D is given by D=1+(4+N),where N is the DLC value or 8 if DLC>8.
01
1
XXXX
Type 1 descriptor CAN Remote frame. The number of bytes in the descriptor is 5.
10
0
NNNN
Type 2 descriptor CAN Data frame. The number of descriptor bytes is D=2+(2 x N), where N is the
DLC value or 8 if DLC>8.
10
1
XXXX
Type 2 descriptor CAN Remote Frame. The number of descriptor bytes is 2.
11
0
NNNN
Type 3 descriptor CAN Data frame. The number of descriptor bytes is D=9+(2 x N), where N is the
DLC value or 8 if DLC>8.
11
1
XXXX
Type 3 descriptor CAN Remote frame. The number of descriptor bytes is 9.
NOTE: Bit 7 should be set to the value of the reserved bit “r1” of the CAN frame.
Type 1 CAN Transmit Descriptor Frame Format
Type 1 CAN transmit descriptors are used when transmitting frames using CAN Identifier and Data payload values
defined explicitly by the HI-3200 Host CPU or Auto-initialization EEPROM.
The descriptor format is as follows:
CAN Data Byte n
CAN Data Byte 1
}
0 - 8 Bytes
ID6 to ID0, r0
ID14 to ID7
ID20 to ID18, SRR, IDE, ID17 to ID15
ID28 to ID21
Type 1 Descriptor Header Byte
HOLT INTEGRATED CIRCUITS
34
HI-3200, HI-3201
Type 2 CAN Transmit Descriptor Frame Format
Type 2 CAN transmit descriptors use a pre-loaded 256
entry common look-up table to define the CAN ID field of
the transmitted frame.
Data Byte n Action Byte
Data Byte 2 Value Byte
Data Byte 2 Action Byte
Data Byte 1 Value Byte
Data Byte 1 Action Byte
}
0x7FFF
ID Entry 255
0x7FF8
0 - 16 Bytes
Data Byte n Value Byte
CAN Data Byte values may be directly loaded from the
host CPU / Auto-initialization EEPROM, or are read from
the ARINC 429 Received Data RAM or CAN Bus
Received Data RAM as indexed by the two data source
descriptor bytes (op-code byte and index byte).
ID Table Entry # (0 - FF)
ID Entry 2
0x7C08
ID6 to ID0, r0
ID Entry 1
0x7C04
ID14 to ID7
ID Entry 0
0x7C00
ID20 to ID18, SRR, IDE, ID17 to ID15
Type 2 Descriptor Header Byte
ID28 to ID21
Type 2 ID Look-up Table
Type 2 Descriptor Block
Type 2 ID Table Entry
Type 3 CAN Transmit Descriptor Frame Format
Data Byte n Value Byte
Data Byte n Action Byte
Data Byte 1 Value Byte
Data Byte 1 Action Byte
CAN ID4 Value Byte
CAN ID4 Action Byte
CAN ID3 Value Byte
CAN ID3 Action Byte
CAN ID2 Value Byte
CAN ID2 Action Byte
CAN ID1 Value Byte
CAN ID1 Action Byte
}
}
}
}
}
0 - 16 Bytes
Type 3 CAN transmit descriptors are used when
transmitting frames using CAN Identifier and Data
payload extracted from the ARINC 429 Received Data
RAM, CAN Bus Received Data RAM, or host CPU / Autoinitialization EEPROM loaded values.
Source pointer for
ID6 to ID0, r0
Source pointer for
ID14 to ID7
Source pointer for
ID20 to ID18, SRR, IDE, ID17 to ID15
Source pointer for
Type 3 Descriptor Header Byte
Type 3 Descriptor Block
HOLT INTEGRATED CIRCUITS
35
ID28 to ID21
HI-3200, HI-3201
Type 2 and 3 CAN Transmit Descriptor Opcode and Index Bytes
Type 2 and 3 CAN Transmit Discriptor Op-Code and Index byte pairs specify the source of data for their corresponding
CAN frame ID bits and data bytes. Their format and operation is similar to the ARINC 429 descriptor byte pairs:
Op-Code
Index
Value
CAN TRANSMIT OPCODE - INDEX BYTE PAIR
7 6
MSB
5
4
3
2
1
0
LSB
ACTION BYTE
Op-Code
7 6
MSB
5
4
3
2
1
0
LSB
VALUE BYTE
Index
Value
0X0
XXXXX
LLLLLLLL
Immediate data. The value contained in the descriptor value data byte is
loaded into this byte position of the CAN Frame to be transmitted.
Description
0X1
CCCXX
LLLLLLLL
Immediate data conditional. The NEWCAN bit corresponding to the ARINC
Data RAM location defined by channel “CCC” and label block “LLLLLLLL” is
read. LLLLLLLL is used if NEWCAN is set for this or any other
conditional opcode within this descriptor frame. If NEWCAN = 0 for all
conditional op codes (within this descriptor frame) then no transmission
occurs for this frame and the sequencer increments to the next descriptor
frame. The NEWCAN bit for the referenced ARINC RAM block is reset.
100
CCCBB
LLLLLLLL
Indexed data. The value of ARINC Data RAM location defined by channel
“CCC”, label block “LLLLLLLL” and byte number “BB” is loaded into this byte
position of the CAN frame to be transmitted.
101
CCCBB
LLLLLLLL
Indexed data conditional. The NEWCAN bit corresponding to the ARINC
Data RAM location defined by channel “CCC”, label block “LLLLLLLL” and
byte number “BB” is read. The corresponding byte is used if
NEWCAN is set for this or any other conditional opcode within this
descriptor frame. If NEWCAN = 0 for all conditional op codes (within this
descriptor frame) then no transmission occurs for this frame and the
sequencer increments to the next descriptor frame. The NEWCAN bit for the
referenced ARINC RAM block is reset.
110
XBBBB
NNNNNNNN
CAN byte. The value of the byte at CAN RAM address filter block
“NNNNNNNN”, byte number “BBBB” is loaded into the CAN transmit buffer
byte position to be transmitted.
111
XBBBB
NNNNNNNN
CAN byte conditional. The NEWCAN bit corresponding to the CAN RAM
address filter block “NNNNNNNN”, byte number “BBBB”
is read. The corresponding byte is used if NEWCAN is set for this or any
other conditional opcode within this descriptor frame. If NEWCAN = 0 for
all conditional op codes (within this descriptor frame) then ARINC word
construction is terminated, no transmission occurs for this frame and the
sequencer increments to the next descriptor frame. The NEWCAN bit for
the referenced CAN RAM address filter block is reset.
HOLT INTEGRATED CIRCUITS
36
HI-3200, HI-3201
CAN Bus Immediate Transmit Option
The Host CPU may instruct the HI-3200 to transmit an
CAN frame immediately using a special SPI command.
The SPI command describes the CAN frame with 5 to 13
SPI data bytes. The bit format of the data bytes is exactly
the same as a Type 1 transmit descriptor, except the
Type Field of the header byte is “don’t care”.
If the CAN transmit sequencer is not running (CTCR bit
RUN/STOP = “0”), or the sequencer is waiting for the
repetition rate counter to rollover, then the new CAN
frame is transmitted without delay.
If the CAN transmit sequencer is active, then the new
frame is transmitted to HI-3110 as soon as the current
frame has been sent. The sequencer then resumes
operation at the next location in the queue.
Both the RUN input pin and the Master Control Register
CANTX bit must be high to enable any CAN frame
transmission.
Table 1 lists the host CPU SPI instruction format.
HOLT INTEGRATED CIRCUITS
37
HI-3200, HI-3201
RESET AND START-UP
OPERATION
After power-on, the HI-3200 is in an undefined state. The
MRST pin must be taken high to begin device
initialization. The MRST pin may be asserted at any time.
Taking MRST high immediately stops all execution and
sets the READY output low indicating that the part is in
the reset state.
On the falling edge of MRST the HI-3200 samples the
state of the MODE2-0 input pins. This is the only
occasion these inputs are sampled. The state of the
MODE pins determines one of eight possible initialization
sequences (Mode 0 through Mode 7). MODE[2:0] = 000
sets Mode 0, MODE[2:0] = 001 sets Mode 1, MODE[2:0]
= 111 sets Mode 7, etc. See Figure 1, Reset and Start-up
Operation Flow Chart. These eight initialization modes
allow the user to customize the start-up configuration of
the device.
The total time from MRST falling edge to READY pin high
depends on the total number of MCLK cycles (48MHz
clock input) and is summarized in Table 2 for each mode.
For Modes 2 and 3, the RBFFAIL bit-7 should be
cleared to 0 by writing to the BIST Control/Status
register (Address 0x8070) BEFORE taking MRST
high.
To use BIST self-tests, the part needs to be in Mode 4
with the RUN pin low.
Once the initialization is complete, the device enters the
Idle State when the ready pin goes high. In Idle State, the
host CPU may communicate with the HI-3200 memory
and registers using the host CPU SPI link. Note that
when Mode 6 is selected, the host CPU SPI by-passes
the HI-3200 and instead communicates directly with the
HI-3110 CAN controller, if used. When in the Idle State,
The HI-3200 does not transmit or receive any messages
on either the ARINC 429 buses or the CAN bus.
To begin data bus operation, the user must transition the
RUN input from a low to high state. Immediately following
the rising edge of RUN, the HI-3200 configures the HI3110 CAN controller, if used, according to the MODE
selection. The part then enters the Active State and bus
message processing begins.
During initialization, various device configuration tasks
are performed according to the Mode selection set at the
MODE2:0 input pins. The available options are described
below in sub-sections 1-6.
TABLE 2. Start-up Time for each Mode
MODE[2:0]
PINS
MODE
MCLK Cycles
Start-up Time*
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
8,203
948,390
73,744
1,013,931
9
3,339
3,339
3,339
1.71µs
19.76ms
1.54ms
21.0ms
188.0ns
69.6µs
69.6µs
69.6µs
* The time from falling edge of MRST to READY pin high.
HOLT INTEGRATED CIRCUITS
38
HI-3200, HI-3201
1. RAM Integrity Check
5 Enable SPI By-Pass
In Modes 2 and 3, the HI-3200 performs a RAM integrity
check. A read/write check is performed on the entire
RAM space. An incrementing pattern is written to
sequential RAM locations then this pattern is read and
verified. Each RAM location is re-written with the 1s
complement of its current contents then this pattern is
read and verified. The incrementing pattern followed by
its 1s complement ensures that each RAM location can
store both a 1 and 0 state. If the RAM integrity check
fails, the MINT pin is asserted and the Pending Interrupt
Register RAMFAIL bit is set. The part enters the “Safe”
state, in which the HI-3200 is able to accept and respond
to Host CPU SPI Instructions, but cannot enter Normal
Operating mode until the MRST input is taken high to
repeat the initialization sequence. The RAMFAIL Interrupt
is not maskable.
In Mode 6, the host CPU SPI interface completely bypasses the HI-3200, and all communication is directed to
the HI-3110 SPI bus such that the user may directly
access registers within the HI-3110. This “by-pass’ mode
is intended as an aid to debugging only and is not
recommended in the final system design implementation.
2. Clear Data Memory
In Modes 0, 1, 2, 3, 5, 6, and 7, the HI-3200 automatically
clears all memory locations in the address range 0x0000
to 0x33FF. This is the space reserved for ARINC 429 and
CAN message data. Configuration tables and HI-3200
registers are not affected.
3. Initialize Registers and Clear all memory
In addition to clearing data memory (0x0000 to 0x33FF),
Modes 0, 1, 2, and 3 also clear all configuration and lookup tables (0x3400 to 0x7FFF) as well as setting all
registers (0x8000 to 0x807F) to their default states. All
registers default to zero unless otherwise noted.
By-pass mode is exited at the first rising edge of the RUN
pin. Further toggling of the RUN pin will not re-engage
the by-pass mode. Since the host does not have access
to internal HI-3200 registers prior to RUN going high, the
user must first initialize these registers prior to entering
Mode 6.
6. HI-3110 Initialize
In Modes 0 through 5, as soon as the RUN input is
transitioned from low to high, the contents of the CAN
bus configuration registers (CANBTR0, CANBTR1) is
transferred to the HI-3110 and other HI-3110 reset and
initialization tasks are performed.
The following values are written to the HI-3110 registers
in the sequence outlined below.
Write 0x88 to HI-3110 CTRL1 Register
Write Register 0x8030 to HI-3110 BTR0 Register
Write Register 0x8031 to HI-3110 BTR1 Register
Write 0x40 to HI-3110 STATE Register
Write 0x65 to HI-3110 GPINE Register
Write 0x07 to HI-3110 CTRL0 Register
The HI-3200 communicates with the HI-3110 over its
dedicated SPI bus.
4. Auto-Initialize from EEPROM
The contents of the Auto-Initialization EEPROM are
copied into the HI-3200 memory and registers via the
EEPROM SPI interface. The part verifies the integrity of
the data transfer from the EEPROM by running through a
byte-by-byte compare routine and a checksum validation.
If a compare error is detected, the AUTOERR bit is set in
the Pending Interrupt Register, the MINT output is
asserted, the location of the error is captured in the
AUTO-INIT FAIL ADDRESS registers 0x8073 (Auto-Init
Fail LS address) and 0x8074 (Auto-Init Fail MS address)
and the part enters the Safe state. If a checksum error is
detected, the CHKERR bit is set in the Pending Interrupt
Register, the MINT output is asserted and the part enters
the Safe state. The AUTOERR and the CHKERR
interrupts are not maskable.
Following HI-3110 initialization, the HI-3200 enters the
ACTIVE state and bus message processing begins.
Once initialization is complete, the part enters the Idle
state. The host CPU may read and write HI-3200 internal
memory and registers in Modes 0, 1, 2, 3, 4, 5, and 7. If
not using the auto-initizarion feature, the host CPU
should configure the device at this time.
HOLT INTEGRATED CIRCUITS
39
HI-3200, HI-3201
MRST driven to “1”
Stop execution, READY => 0
RESET STATE
MRST driven to “0”
Sample MODE2:0 inputs
MODE 0
MODE 1
MODE 2
MODE 3
MODE 4
MODE 5
MODE 6
MODE 7
No
No
Yes
Yes
No
No
No
No
Clear data memory
(0x0000 - 0x33FF)
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Initialize Registers and
Clear Configuration Tables
(0x3400 - 0xFFFF)
Yes
Yes
Yes
Yes
No
No
No
No
Auto-Initialize from
EEPROM
No
Yes
No
Yes
No
No
No
No
Enable SPI By-Pass
No
No
No
No
No
No
Yes
No
Perform
RAM Integrity Check
No
Set RAMFAIL
INT = 1
No
Set AUTOERROR
INT = 1
RAM Pass
?
Yes
Copy OK
?
Yes
READY => 1
SAFE STATE
IDLE STATE
RUN driven 0 - 1
MODE 0
MODE 1
MODE 2
MODE 3
MODE 4
MODE 5
MODE 6
MODE 7
HI-3110 Initialize
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Disable SPI By-Pass
n/a
n/a
n/a
n/a
n/a
n/a
Yes
n/a
ACTIVE STATE
Figure 1. Reset and Start-up Operation flow chart.
HOLT INTEGRATED CIRCUITS
40
HI-3200, HI-3201
INTERRUPT HANDLING
The HI-3200 includes a simple, user-selectable Interrupt
Handler. Two types of Interrupt are possible - Message
Event Driven (ARINC 429 or CAN Bus), and Fault Driven.
ARINC 429 Receive Interrupts
As described earlier, the user can elect to generate an
interrupt upon receipt of an ARINC 429 message on any
combination of the eight available channels and for any
of the possible 256 label byte (ARINC message bits 1-8)
values. Interrupts are enabled when the ARINC 429 Rx
Interrupt look-up bit is a “1”.
CAN Bus Interrupts
An interrupt is generated on receipt of a CAN frame
whose corresponding Filter and Interrupt look-up table
bits are a “1”. The CANRX bit is set in the Pending
Interrupt Register PIR, and the filter number which
accepted the CAN frame is written to the CAN Interrupt
Address Register CIAR. For example, if filter # 0xA1
accepts the frame, the value 0xA1 is written to CIAR.
The Interrupt output, MINT, is asserted (high) if the
Interrupt Mask Register CANRX bit is a “1”.
When a message arrives that is flagged to generate an
Interrupt, that channel’s bit is set in the ARINC 429
Receiver Pending Interrupt Register APIR. The ARINC
429 Interrupt Address Register (AIAR) for that channel is
updated with the ARINC 429 8-bit label value.
A special SPI Instruction allows the user to extract the
received frame information from the CAN receive
memory without having to first determine its sixteen-bit
absolute address. The CIAR value is used as a relative
address pointer.
For example, if ARINC Receive channel 7 is enabled for
Interrupts when messages with ARINC label 0xD4 arrive,
then on receipt of such a message, APIR bit 7 is set to a
“1” and the value 0xD4 is written to AIAR7.
Fault Interrupts
If the corresponding bit in the ARINC 429 Receive
Interrupt Mask Register is a “1” the AINT interrupt output
will go high and stay high until the AACK input pin is
driven high. Driving AACK high, causes the AINT pin to
return to zero.
A special Indexed SPI read instruction is available to
allow the host to efficiently retrieve ARINC 429 messages
which have Interrupts Enabled (see SPI instruction set
section).
Note that if AACK is tied high permanently, the AINT pin
will go high for approximately 1 us before returning to
zero. A host CPU read of the APIR register reads the
current value and resets APIR to 0x00.
There are four fault Interrupt bits in the PIR. Fault
Interrupts are not maskable, and their Interrupt Mask bits
are fixed at a “1”.
COPYERR is set when the HI-3200 detects a mismatch
between RAM and EEPROM after attempting to program
the Auto-initialization EEPROM.
AUTOERR is set when the Auto-Initialization EEPROM
read verification cycle detects a mismatch between the
on-chip memory and EEPROM following autoinitialization.
CHKERR is set when an auto-initialization checksum
error is detected.
The RAMFAIL bit is set if the Built-In Self Test sequence
fails.
HOLT INTEGRATED CIRCUITS
41
AP
IR
AP 7
IR
AP 6
IR
AP 5
IR
AP 4
IR
AP 3
IR
AP 2
IR
AP 1
IR
0
HI-3200, HI-3201
ARINC 429 RECEIVE PENDING INTERRUPT REGISTER
(Address 0x8000)
Bit Name
7:0 APIR[7:0]
R/W
R
7 6
MSB
5
4
3
2
1
0
LSB
Default Description
0
When a message is received on a given channel that triggers an interrupt, that channel’s
corresponding bit is set, e.g. if a message received on Rx channel 5 triggers an interrupt, the
bit APIR5 will be set. If this bit is unmasked in the ARINC 429 Receive Interrupt Mask Register
(see below), the AINT output pin is asserted.
AI
M
R
AI 7
M
R
AI 6
M
R
AI 5
M
R
AI 4
M
R
AI 3
M
R
AI 2
M
R
AI 1
M
R
0
Note: This register is automatically cleared when read.
ARINC 429 RECEIVE INTERRUPT MASK REGISTER
(Address 0x8020)
R/W
7:0 AIMR[7:0]
R/W
5
4
3
2
1
0
LSB
Default Description
0
Each bit in this register, AIMR[7:0], is a mask for a corresponding bit in the ARINC 429 Receive
Pending Interrupt Register (APIR[7:0], described above). Writing a “1” to an AIMR bit
results in assertion of the AINT output pin when the corresponding APIR bit is set (ARINC 429
message received). Writing a “0” to an AIMR bit will mask the corresponding APIR bit in the
ARINC 429 Receive Pending Interrupt Register, resulting in non-assertion of the AINT pin
when an ARINC 429 message is received.
AI
AR
AI n7
AR
AI n6
AR
AI n5
AR
AI n4
AR
AI n3
AR
AI n2
AR
AI n1
AR
n0
Bit Name
7 6
MSB
ARINC 429 RECEIVE INTERRUPT ADDRESS REGISTERS 0 - 7
(Address 0x8001 - 0x8008)
Bit Name
7:0 AIAR0[7:0]
R/W
R
n=0-7
7 6
MSB
5
4
3
2
1
0
LSB
Default Description
0
The label number of the ARINC 429 message causing an interrupt is loaded into this
register. Each channel has a corresponding ARINC 429 Receive Interrupt Address Register
(AIAR0 - AIAR7).
HOLT INTEGRATED CIRCUITS
42
C
O
P
AU YE
TO RR
C E
H R
K R
R ER
AM R
FL FA
AG IL
AT
X
C RD
AN Y
C RX
TX
R
D
Y
HI-3200, HI-3201
PENDING INTERRUPT REGISTER
(Address 0x800A)
7 6
MSB
5
4
3
2
1
0
LSB
The MINT will be asserted when any of the bits in this register are set.
Bit Name
R/W
Default Description
COPYERR
R
0
EE copy error. RAM - EEPROM mismatch
6
AUTOERR
R
0
Auto-inititailization RAM read error
5
CHKERR
R
0
Auto-initialization checksum fail
4
RAMFAIL
R
0
Power-On Reset RAM Integrity Check fail
3
FLAG
R
0
Logical OR of ARINC 429 Receive FIFO FLAG signals
2
ATXRDY
R
0
ARINC 429 Host TX ready. Used with Host SPI op-code 100101TT (see Table 1). Interrupt
when any of the four ARINC 429 transmitters are ready for the next 32-bit word from the host
1
CANRX
R
0
CAN Bus received frame Interrupt
0
CTXRDY
R
0
CAN Host Tx ready. Used with host SPI opcode 10010000. Interrupt when ready for next CAN
frame from host.
C
O
PY
AU E
T RR
C OE
H R
K R
R ER
AM R
FL FA
AG IL
AT IE
X
C RD
AN Y
IE
C RX
TX IE
R
D
YI
E
7
PENDING INTERRUPT ENABLE REGISTER
(Address 0x8034)
Bit Name
R/W
7 6
MSB
5
4
3
2
1
0
LSB
Default Description
7
COPYERR
R
1
COPYERR is not maskable
6
AUTOERR
R
1
AUTOERR is not maskable
5
CHKERR
R
1
CHKERR is not maskable
4
RAMFAIL
R
1
RAMFAIL is not maskable
3
FLAGIE
R/W
0
MINT pin is asserted if this bit is a “1” and the Pending Interrupt Register FLAG bit is set
2
ATXRDYIE
R/W
0
MINT pin is asserted if this bit is a “1” and the Pending Interrupt Register ATXRDY bit is set
1
CANRXIE
R/W
0
MINT pin is asserted if this bit is a “1” and the Pending Interrupt Register CANRX bit is set
0
CTXRDYIE
R/W
0
MINT pin is asserted if this bit is a “1” and the Pending Interrupt Register CTXRDY bit is set
HOLT INTEGRATED CIRCUITS
43
AT
X
AT IE3
X
AT IE2
X
AT IE1
XI
E0
HI-3200, HI-3201
ARINC 429 TX READY INT ENABLE
(Address 0x8035)
X
X
X
X
7 6
MSB
5
4
3
2
1
0
LSB
Bit Name
R/W
Default Description
7
-
R/W
0
Not Used
6
-
R/W
0
Not Used
5
-
R/W
0
Not Used
4
-
R/W
0
Not Used
3
ATXIE3
R/W
0
Setting this bit generates an interrupt when ARINC 429 Transmitter 3 is ready to receive the
next 32-bit word from the host for transmission. The ATXRDY bit in the Pending
Interrupt Register will be set and the MINT pin will be asserted if the ATXRDYIE bit is set in the
Pending Interrupt Enable Register.
2
ATXIE2
R/W
0
Setting this bit generates an interrupt when ARINC 429 Transmitter 2 is ready to receive the
next 32-bit word from the host for transmission. The ATXRDY bit in the Pending
Interrupt Register will be set and the MINT pin will be asserted if the ATXRDYIE bit is set in the
Pending Interrupt Enable Register.
1
ATXIE1
R/W
0
Setting this bit generates an interrupt when ARINC 429 Transmitter 1 is ready to receive the
next 32-bit word from the host for transmission. The ATXRDY bit in the Pending
Interrupt Register will be set and the MINT pin will be asserted if the ATXRDYIE bit is set in the
Pending Interrupt Enable Register.
0
ATXIE0
R/W
0
Setting this bit generates an interrupt when ARINC 429 Transmitter 0 is ready to receive the
next 32-bit word from the host for transmission. The ATXRDY bit in the Pending
Interrupt Register will be set and the MINT pin will be asserted if the ATXRDYIE bit is set in the
Pending Interrupt Enable Register.
CIAR
CAN INTERRUPT ADDRESS REGISTER
(Address 0x800B)
7 6
MSB
5
4
3
2
1
0
LSB
HOLT INTEGRATED CIRCUITS
44
HI-3200, HI-3201
RAM BUILT-IN SELF-TEST
The HI-3200 offers a built-in self-test (BIST) feature which can be used to check RAM integrity. The BIST Control/Status
Register is used to control the BIST function. All tests are destructive, overwriting data present before test commencement.
R
BF
R AIL
BS
R EL
BS 2
R EL
BS 1
R EL
BS 0
TA
RT
R
BF
R AIL
BP
AS
S
NOTE: To use BIST self-tests, the part needs to be in Mode 4 with the RUN pin low.
BIST CONTROL/STATUS REGISTER
(Address 0x8070)
X
7 6
MSB
5
4
3
2
1
0
LSB
This register controls RAM built-in self-test. Bits 0,1 are Read Only.
BIST Control Register bits provide a means for the host to perform RAM self-test at other times. Register bits 6:4 select RAM
test type. Then bit 3 starts the selected RAM test, and bits 1:0 report a fail/pass result after test completion.
Bit No.
Mnemonic Interrupt Type
7
RBFFAIL
6:4
RBSEL2-0 RAM BIST Select Bits 2-0.
This 3-bit field selects the RAM BIST test mode applied when the RBSTART bit is set:
RAM BIST Force Failure.
When this bit is asserted, RAM test failure is forced to verify that RAM BIST logic is functional.
For Modes 2 and 3, the RBFFAIL bit-7 should be cleared to 0 by writing to the BIST
Control/Status register (Address 0x8070) BEFORE taking MRST high.
RBSEL2:0
000
001
010
011
100
101
110
111
SELECTED RAM TEST
Idle
Pattern Test, described below
Write 0x00 to RAM address range 0x0000 - 0x7FFF
Read and verify 0x00 over RAM address range 0x0000 - 0x7FFF
Write 0xFF to RAM address range 0x0000 - 0x7FFF
Read and verify 0xFF over RAM address range 0x0000 - 0x7FFF
Inc / Dec Test performs only steps 5 - 8 of the Pattern Test below
Idle
Description of the RAM BIST “PATTERN” test selected when register bits RBSEL2:0 =
001:
1. Write 0x00 to all RAM locations, 0x0000 through 0x7FFF
2. Repeat the following sequence for each RAM location from 0x0000 through 0x7FFF:
a. Read and verify 0x00
b. Write then read and verify 0x55
c. Write then read and verify 0xAA
d. Write then read and verify 0x33
e. Write then read and verify 0xCC
f. Write then read and verify 0x0F
g. Write then read and verify 0xF0
h. Write then read and verify 0x00
I. Write then read and verify 0xFF
j. Write 0x00 then increment RAM address and go to step (a)
3. Write 0xFF to all RAM locations, 0x0000 through 0x7FFF
4. Repeat the following sequence for each RAM location from 0x0000 through 0x7FFF:
HOLT INTEGRATED CIRCUITS
45
HI-3200, HI-3201
a.
b.
c.
d.
e.
f.
g.
h.
I.
j.
5.
6.
7.
8.
Read and verify 0xFF
Write then read and verify 0x55
Write then read and verify 0xAA
Write then read and verify 0x33
Write then read and verify 0xCC
Write then read and verify 0x0F
Write then read and verify 0xF0
Write then read and verify 0x00
Write then read and verify 0xFF
Write 0xFF then increment RAM address and go to step (a)
Write an incrementing pattern into sequential RAM locations from 0x0000 to 0x7FFF
Read each memory location from 0x0000 to 0x7FFF and verify the contents
Write 1s complement of each cell’s current contents, into each RAM location (same addr range)
Read each memory location and verify the contents
3
RBSTRT
RAM BIST Start.
Writing logic 1 to this bit initiates the RAM BIST test selected by register bits RBSEL2:0. The RBSTRT
bit can only be set in MODE2:0 = 0x04. This bit is automatically cleared upon test completion.
Register bits 1:0 indicate fail / pass test result.
2
---------
Not Used.
1
RBFAIL
RAM BIST Fail.
Device logic asserts this bit when failure occurs while performing the selected RAM test. This bit is
automatically cleared when RBSTRT bit 3 is set. When BIST failure occurs, a clue to the failing RAM
address can be read at register addresses 0x8071 and 0x8072. For speed, the RAM BIST
concurrently tests four consecutive RAM addresses in parallel. If a test failure occurs, register
addresses 0x8071 and 0x8072 can be used to determine the four RAM addresses tested.
0
RBPASS
RAM BIST Pass.
Device logic asserts this bit when the selected RAM test completes without error. This bit is
automatically cleared when RBSTRT bit 3 is set.
BISTFL
LOWER BIST FAIL ADDRESS REGISTER
(Address 0x8071)
7 6
MSB
5
4
3
2
1
0
LSB
BISTFH
UPPER BIST FAIL ADDRESS REGISTER
(Address 0x8072)
X
X
15 14 13 12 11 10 9 8
LSB
MSB
HOLT INTEGRATED CIRCUITS
46
HI-3200, HI-3201
HOST SERIAL PERIPHERAL INTERFACE
In the HI-3200, internal RAM and registers occupy a (32K +
128) x 8 address space. The lowest 32K addresses access
RAM locations and the remaining addresses access
registers. Timing is identical for register operations and
RAM operations via the serial peripheral interface, and
read and write operations have likewise identical timing.
SCK, and output data for each device changes on the
falling edge. These are known as SPI Mode 0 (CPHA = 0,
CPOL = 0) and SPI Mode 3 (CPHA = 1, CPOL = 1). Be sure
to set the host SPI logic for one of these modes.
As seen in Figure 2, the difference between SPI Modes 0
and 3 is the idle state for the SCK signal. There is no
configuration setting in the HI-3200 to select SPI Mode 0 or
Mode 3 because compatibility is automatic. Beyond this
point, the HI-3200 data sheet only shows the SPI Mode 0
SCK signal in timing diagrams.
Host access is only allowed when the part is READY or in
SAFE mode. NOTE: writes will be blocked and reads will
return the Master Status Register value until either of these
modes occur.
The SPI protocol transfers serial data as 8-bit bytes. Once
CS chip select is asserted, the next 8 rising edges on SCK
latch input data into the master and slave devices, starting
with each byte’s most-significant bit. The HI-3200 SPI can
be clocked at 20 MHz.
Serial Peripheral Interface (SPI) Basics
The HI-3200 uses an SPI synchronous serial interface for
host access to registers and RAM. Host serial
communication is enabled through the Chip Select (CS)
pin, and is accessed via a three-wire interface consisting of
Serial Data Input (SI) from the host, Serial Data Output
(SO) to the host and Serial Clock (SCK). All programming
cycles are completely self-timed, and no erase cycle is
required before write.
Multiple bytes may be transferred when the host holds CS
low after the first byte transferred, and continues to clock
SCK in multiples of 8 clocks. A rising edge on CS chip
select terminates the serial transfer and reinitializes the
HI-3200 SPI for the next transfer. If CS goes high before a
full byte is clocked by SCK, the incomplete byte clocked
into the device SI pin is discarded.
The SPI (Serial Peripheral Interface) protocol specifies
master and slave operation; the HI-3200 Host CPU
interface operates as an SPI slave.
In the general case, both master and slave simultaneously
send and receive serial data (full duplex) as shown in
Figure 2 below. When the HI-3200 is sending data on SO
during read operations, activity on its SI input is ignored.
Figures 3 and 4 show actual behavior for the HI-3200 SO
output.
The SPI protocol defines two parameters, CPOL (clock
polarity) and CPHA (clock phase). The possible CPOLCPHA combinations define four possible "SPI Modes."
Without describing details of the SPI modes, the HI-3200
operates in the two modes where input data for each
device ( master and slave) is clocked on the rising edge of
SCK (SPI Mode 0)
0
1
2
3
4
5
6
7
SCK (SPI Mode 3)
0
1
2
3
4
5
6
7
SI
SO
High Z
MSB
LSB
MSB
LSB
High Z
CS
FIGURE 2. Generalized Single-Byte Transfer Using SPI Protocol, SCK is Shown for SPI Modes 0 and 3
HOLT INTEGRATED CIRCUITS
47
HI-3200, HI-3201
0
1
3
2
5
4
6
0
7
1
3
2
5
4
6
7
SCK
SPI Mode 0
MSB
LSB
SI
Command Byte
LSB MSB
MSB
High Z
SO
High Z
Data Byte
CS
Host may continue to assert CS
here to read sequential byte(s)
when allowed by the instruction.
Each byte needs 8 SCK clocks.
FIGURE 3. Single-Byte Read From RAM or a Register
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SPI Mode 0
MSB
LSB MSB
LSB
LSB MSB
SI
Command Byte
SO
Data Byte 0
Data Byte 1
High Z
CS
Host may continue to assert CS
here to write sequential byte(s)
when allowed by the SPI instruction.
Each byte needs 8 SCK clocks.
FIGURE 4. 2-Byte Write To RAM or a Register Pair
HOLT INTEGRATED CIRCUITS
48
HI-3200, HI-3201
HI-3200 SPI COMMANDS
For the HI-3200, each SPI read or write operation begins
with an 8-bit command byte transferred from the host to the
device after assertion of CS. Since HI-3200 command byte
reception is half-duplex, the host discards the dummy byte
it receives while serially transmitting the command byte.
Note: When the primary or fast-access address pointer is
used for auto-incrementing multi-word read/write and
reaches the top of the memory address range (0x7FFF), or
the top of the register address range (0xFFFF) attempts to
read further bytes will result the terminal address (0x7FFF
or 0xFFFF) being output again. The host should avoid this
situation.
Fast Access Commands for Registers 0-15
Two single-byte SPI commands use the current address
pointer value in MAP without first loading or otherwise
modifying it:
The SPI command set includes directly-addressed read
and write commands for registers 0 through 15 (Memory
Address 0x8000 to 0x800F). The 8-bit pattern for these
commands has the general form
0-W-R-R-R-R-0-0
where RRRR is the 4-bit register number, and W signifies
Write when 1, or Read when 0.
Figures 3 and 4 show read and write timing as it appears
for fast-access register operations. The command byte is
immediately followed by a data byte comprising the 8-bit
data word read or written. For a single register read or
write, CS is negated after the data byte is transferred.
Multiple register read or write cycles may be performed by
transferring more than one byte before CS is negated.
Multiple register access occur in address order starting
with the register specified in the SPI instruction.
Note: Register locations not shown in table 1 are
“reserved” and cannot be written using any SPI command.
Further, these register addresses will not provide
meaningful data in response to read commands.
RAM and Register Indirect Addressing
Refer to the HI-3200 SPI command set shown in Table 1.
SPI commands other than fast-access use an address
pointer to indicate the address for read or write
transactions. This sixteen-bit memory address pointer
(MAP) must be initialized before any non-fast-access read
or write operation. Two dedicated SPI instructions are
used to write and read the MAP. SPI Instruction 0x8C
followed by two data bytes is used to write MAP. SPI
instruction 0x88 reads two data bytes from MAP. The first
byte is the most significant eight bytes of the address. For
example, SPI sequence 0x8C, 0x12, 0x34 write the value
0x1234 into the MAP.
Two SPI instructions read and write data bytes to memory
or registers using the MAP as an address pointer. Single or
multi-byte reads and writes may be performed. MAP is
incremented after each byte access.
Two command bytes cannot be “chained”; CS must be
negated after the command, then reasserted for the
following Read or Write command.
Command
0x80
Read Operation
read location addressed by pointer value
Command
0x84
Write Operation
write location addressed by pointer value
Either of these commands can be used to read or write a
single location, or may be used when starting a multi-byte
read or write by using the pointer’s auto-increment feature.
Special Purpose Commands
Several other HI-3200 SPI commands load or otherwise
modify the memory address pointer before initiating a read
or write process. These commands are designed to allow
speedy access to messages received on the ARINC 429 or
CAN buses.
Using a single-byte SPI command, the address pointer can
be directly loaded with the memory address for the last
received ARINC 429 message which triggered an
interrupt.
Op Code 110RRR00
The HI-3200 will retrieve the current ARINC Receive
Interrupt Vector for a given channel (RRR), calculate t h e
memory address for the first word of the c o r r e s p o n d i n g
receive memory data block and write it to the Memory
Address pointer (MAP). Read the location addressed by
the new pointer value.
This command can be used to read just the most recent
ARINC 429 Receive Status Byte, or may be used to start a
four-byte read because memory pointer auto-increment
occurs after the Status Byte is read.
Op Code 111RRR00
The HI-3200 will retrieve the current ARINC Receive
Interrupt Vector for a given channel (RRR), calculate the
memory address for the first word of the corresponding
receive memory data block and write it to the Memory
Address Pointer (MAP). Output the value of the Receive
Interrupt Vector (ARINC 429 label byte).
This command can be used to read just the most recent
ARINC 429 label value received, or may be used to start a
four-byte read to output the entire four-byte ARINC
HOLT INTEGRATED CIRCUITS
49
HI-3200, HI-3201
message, because memory pointer auto-increment
occurs after the label byte is output.
Op Code 0x9C
This command can be used to read just the most recent
CAN frame Information byte received, or may be used to
start a sixteen-byte read to output the entire sixteen-byte
received CAN frame memory block, because memory
pointer auto-increment occurs after the first byte is output.
Op Code 0x90
Writes a CAN frame to the CAN transmit scheduler for
immediate transmission.
Op Code 100101TT
Writes an ARINC 429 message to ARINC 429 transmit
scheduler TT for immediate transmission, where TT
represents the channel number.
TABLE 1. DEFINED INSTRUCTIONS
OP CODE
Binary
OP CODE
Hex
00RRRR00 0x00 - 0x3C
01RRRR00 0x40 - 0x7C
10000000
0x80
10000100
0x84
10001000
0x88
10001100
0x8C
10010000
0x90
100101TT
0x94 - 0x97
10011100
0x9C
101RRR00 0xA0 - 0xBC
110RRR00 0xC0 - 0xDC
111RRR00 0xE0 - 0xFC
Auto
Increment
Number of
Data Bytes
Yes
Yes
Yes
Yes
No
No
No
No
No
Yes
No
No
1++
1++
1++
1++
2
2
5 - 13
4
16
4, 8, 12...
4
4
DESCRIPTION
Fast Register Read from register RRRR
Fast Register Write to register RRRR
Read memory at address MAP
Write memory at address MAP
Read MAP
Write MAP
Transmit CAN Frame
Transmit ARINC 429 message on transmit bus TT
Read CAN Frame at filter block <CIAR>
Read ARINC 429 FIFO # RRR. Reads exactly four bytes
Read ARINC block at receive channel RRR, label <AIARn>
Read ARINC message at receive channel RRR, label <AIARn>
FAST-ACCESS SPI COMMANDS FOR REGISTERS 0-15
Command Bits 5:2 Convey the 4-Bit Register Address
COMMAND BITS
7 6 5 4 3 2 1 0
HEX
BYTE
FAST-ACCESS
READ
COMMAND BITS
7 6 5 4 3 2 1 0
HEX
BYTE
FAST-ACCESS
WRITE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
Read APIR
Read AIAR0
Read AIAR1
Read AIAR2
Read AIAR3
Read AIAR4
Read AIAR5
Read AIAR6
Read AIAR7
Reserved
Read PIR
Read CIAR
Read AMFF
Read ATRB
Read MSR
Read MCR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x40
0x44
0x48
0x4C
0x50
0x54
0x58
0x5C
0x60
0x64
0x68
0x6C
0x70
0x74
0x78
0x7C
N/A (Read only)
N/A (Read only)
N/A (Read only)
N/A (Read only)
N/A (Read only)
N/A (Read only)
N/A (Read only)
N/A (Read only)
N/A (Read only)
Reserved
N/A (Read only)
N/A (Read only)
N/A (Read only)
N/A (Read only)
N/A (Read only)
Write MCR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HOLT INTEGRATED CIRCUITS
50
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HI-3200, HI-3201
HOST SPI BY-PASS
When the HI-3200 is reset and initialization Mode 6 is
selected (by setting MODE2:0 inputs to “110”), the SPI bypass function is enabled when the device is in the idle
state. SPI By-Pass allows the host CPU to communicate
directly with the HI-3110 CAN controller via its dedicated
SPI interface, by-passing the HI-3200. SPI command
sequences from the host CPU may then directly
interrogate or program the attached HI-3110.
SPI By-Pass mode is disabled as soon as the RUN input is
taken high and the device enters the ACTIVE state. Any
further toggling of the RUN pin will not re-initiate SPI bypass mode.
In normal operation, the HI-3200 handles all HI-3110
control functions. SPI By-Pass is intended only as a
system debugging aid.
For a full description of the HI-3110 and its SPI instruction
set, please refer to the latest revision of the HI-3110 data
sheet.
HOLT INTEGRATED CIRCUITS
51
HI-3200, HI-3201
PROGRAMMING THE AUTO-INITIALIZATION EEPROM.
Following reset, the HI-3200 may be completely
configured by automatically copying the contents of an
external EEPROM into HI-3200 memory and registers. An
SPI enabled 64KByte EEPROM is used for this purpose.
The EEPROM memory space is mapped to the HI-3200 as
shown in the diagram below.
All configuration memory blocks are copied. The ARINC
429 Received Data Memory contents, ARINC 429 Receive
log FIFO contents, and CAN Bus Received Data Memory
contents are not copied to or from the EEPROM.
The HI-3200 can be used to program the Auto-Initialization
EEPROM. When the HI-3200 is in its IDLE state (RUN
input = “0”), a three step sequence must be performed to
begin the EEPROM programming cycle:
1. Write data value 0x5A to HI-3200 memory address
0x8FFF.
2. Write data value 0xA5 to HI-3200 memory address
0x8FFF.
3. Apply a positive pulse to the PROG input pin of at least 1
ms.
If the three-step sequence is interrupted by any intervening
host activity between steps 1 and 2, or 2 and 3, or if the
PROG pulse is less than 1 ms, the programming cycle will
not start and the device remains in the IDLE state.
Taking the PROG pin low initiates the cycle. The READY
pin goes low, and the contents of the HI-3200 memory and
registers are copied to the EEPROM. When copying is
complete, the HI-3200 executes a byte-by-byte
comparison of the EEPROM and its own register / memory
contents. If the verification completes successfully, the
READY pin goes high.
A 2’s complement of the checksum is also written to the
EEPROM at location 0x807F. The total read back
checksum should be zero. The following locations are
excluded from the checksum because they are either readonly or unused locations: 0x8000 thru 0x800e, 0x8023 thru
0x802f, 0x8036 thru 0x805e, 0x8070 thru 0x807e.
If the comparison of the EEPROM contents and HI-3200
memory / register contents results in a discrepancy, the HI3200 enters the SAFE state, the PROGERR bit is set in the
Pending Error Register and the INT output is asserted.
The user must clear the PROGERR issue before normal
operation can resume.
0x8XXX
0x8XXX
Configuration Registers
Configuration Registers
0x8000
0x8000
0x7FFF
0x7FFF
CAN TX ID Look-Up Table
CAN TX ID Look-Up Table
0x7C00
0x7C00
0x7BFF
0x79C0
0x79BF
0x7BFF
0x7C00
0x79BF
0x6000
0x5FFF
0x5800
0x57FF
0x5000
0x4FFF
0x4800
0x47FF
0x4000
0x3FFF
0x3400
0x33FF
0x3000
0x2FFF
Look-up Tables
Look-up Tables
CAN Bus
Transmit Schedule
Table
CAN Bus
Transmit Schedule
Table
ARINC 429 TX3
Transmit Schedule
Table
ARINC 429 TX2
Transmit Schedule
Table
ARINC 429 TX1
Transmit Schedule
Table
ARINC 429 TX0
Transmit Schedule
Table
ARINC 429 TX3
Transmit Schedule
Table
ARINC 429 TX2
Transmit Schedule
Table
ARINC 429 TX1
Transmit Schedule
Table
ARINC 429 TX0
Transmit Schedule
Table
CAN Bus
Receive Filters
CAN Bus
Receive Filters
0x6000
0x5FFF
0x5800
0x57FF
0x5000
0x4FFF
0x4800
0x47FF
0x4000
0x3FFF
0x3400
0x3FFF
ARINC 429 Log FIFO Space
ARINC 429 / CAN
Receive Data
0x0000
0x0000
HI-3200 Memory
HOLT INTEGRATED CIRCUITS
52
EEPROM
HI-3200, HI-3201
ABSOLUTE MAXIMUM RATINGS
Supply voltage (VDD)
Logic input voltage range
RECOMMENDED CONDITIONS
Operating Supply Voltage
-0.3 V to +5.0 V
X
VDD....................................... 3.3 VDC ±5%
-0.3 V DC to +3.6 V
X
Power dissipation at 25°C
1.0 W
Reflow Solder Temperature
260°C
Junction Temperature
175°C
Storage Temperature
-65°C to +150°C
Operating Temperature Range
X
Industrial ......................... -40°C to +85°C
Extended ....................... -55°C to +125°C
NOTE: Stresses above absolute maximum ratings or
outside recommended operating conditions may cause
permanent damage to the device. These are stress
ratings only. Operation at the limits is not recommended.
DC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
Operating Voltage
SYMBOL
CONDITION
VDD
Supply Current
MIN
TYP
MAX
UNITS
3.15
3.30
3.45
V
IDD
Min. Input Voltage
(HI)
Max. Input Voltage
(LO)
VIH
50
Digital inputs
VIL
Digital inputs
Digital Inputs Pull-Up / Pull-Down Current
IPUD
Digital inputs and data bus
Min. Output Current
IOH
VOH = 0.8 VDD
(HI)
70%
mA
VDD
30
30%
VDD
100
µA
-6.0
mA
VDD = 3.15 - 3.45 V
Max. Output Current (LO)
IOL
VOL = 0.4 V
Min. Output Voltage
(HI)
VOH
IOUT = -1.0mA, Digital outputs
Max. Output Voltage
(LO)
VOL
IOUT = 1.0mA, Digital outputs
6.0
mA
VDD = 3.15 - 3.45 V
HOLT INTEGRATED CIRCUITS
53
90%
VDD
10%
VDD
HI-3200, HI-3201
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
LIMITS
PARAMETER
SYMBOL
UNITS
MIN
TYP
MAX
SPI Host Bus Interface
SCK clock period
CE set-up time to first SCK rising edge
CE hold time after last SCK falling edge
CE inactive between SPI instructions
SPI SI Data set-up time to SCK rising edge
SPI SI Data hold time after SCK rising edge
SCK high time
SCK low time
SO valid after SCK falling edge
SO high-impedance after CE inactive
tCYC
tCES
tCEH
tCPH
tDS
tDH
tSCKH
tSCKL
tDV
tCHZ
50
25
25
100
10
10
25
25
20
75
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SERIAL INPUT TIMING DIAGRAM
t CPH
t CEH
CE
t CES
SCLK
t DS
t DH
SI
MSB
LSB
SERIAL OUTPUT TIMING DIAGRAM
t CPH
CE
t SCKH
t SCKL
SCLK
t CHZ
t DV
SO
Hi Impedance
MSB
HOLT INTEGRATED CIRCUITS
54
LSB
Hi Impedance
HI-3200, HI-3201
PIN CONFIGURATION FOR HI-3200, 64-PIN QFN PACKAGE
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
ARX2P
ARX1N
ARX1P
ARX0N
ARX0P
SCANEN
CMISO
READY
ESCLK
EMOSI
ECSB
EMISO
RUN
CCSB
ATXMSK
MRST
Notes
1 . All VDD and GND pins must be connected.
2. See data sheet page 1 for HI-3200, 64-Pin PQFP Package Configuration.
HI-3200PCx
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ARX7P
ARX7N
MODE0
CMOSI
MODE1
MCLK
MODE2
ARXBIT0
ARXBIT1
HMISO
HSCLK
HMOSI
HCSB
CSCLK
MINT
MINTACK
AACK
CGP2
AINT
CSTAT
SCANSHIFT
ARX2N
ARX3P
VDD
GND
ARX3N
ARX4P
ARX4N
ARX5P
ARX5N
ARX6P
ARX6N
TOP VIEW
HOLT INTEGRATED CIRCUITS
55
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CMROUT
ATXSLP0
ATX0N
ATX0P
ATX1N
ATX1P
ATXSLP1
VDD
GND
COSC
ATXSLP2
ATX2N
ATX2P
ATX3N
ATX3P
ATXSLP3
HI-3200, HI-3201
PIN CONFIGURATION FOR HI-3201, 80-PIN PQFP PACKAGE
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
ARX2P
ARX1N
ARX1P
ARX0N
ARX0P
SCANEN
ARXBIT5
CMISO
READY
VDD
GND
ESCLK
EMOSI
ECSB
EMISO
RUN
CCSB
ARXBIT4
ATXMSK
MRST
Notes
1 . All VDD and GND pins must be connected.
2. See data sheet page 1 for HI-3200, 64-Pin PQFP Package Configuration.
HI-3201PQI
&
HI-3201PQT
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ARX7P
ARX7N
MODE0
CMOSI
MODE1
MCLK
MODE2
ARXBIT0
VDD
VDD
GND
GND
ARXBIT1
HMISO
HSCLK
HMOSI
HCSB
CSCLK
MINT
MINTACK
AACK
ARXBIT6
CGP2
AINT
ARXBIT7
CSTAT
SCANSHIFT
ARX2N
ARX3P
VDD
VDD
GND
GND
ARX3N
ARX4P
ARX4N
ARX5P
ARX5N
ARX6P
ARX6N
HOLT INTEGRATED CIRCUITS
56
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
CMROUT
ARXBIT3
ATXSLP0
ATX0N
ATX0P
ATX1N
ATX1P
ATXSLP1
VDD
VDD
GND
GND
COSC
ARXBIT2
ATXSLP2
ATX2N
ATX2P
ATX3N
ATX3P
ATXSLP3
HI-3200, HI-3201
ORDERING INFORMATION
HI-3200xx x x
PART
NUMBER
Blank
F
PART
NUMBER
PACKAGE
DESCRIPTION
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free RoHS compliant)
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
No
T
-55°C TO +125°C
T
No
M
-55°C TO +125°C
M
Yes
PART
NUMBER
PACKAGE
DESCRIPTION
PQ
64 THIN PIN PLASTIC QUAD FLAT PACK TQFP (64PQTS)
PC
64-PIN PLASTIC CHIP-SCALE PACKAGE QFN (64PCS)
HI-3201PQ x F
PART
NUMBER
F
PART
NUMBER
PACKAGE
DESCRIPTION
100% Matte Tin (Pb-free RoHS compliant)
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
No
T
-55°C TO +125°C
T
No
M
-55°C TO +125°C
M
Yes
PART
NUMBER
PQ
PACKAGE
DESCRIPTION
80 THIN PIN PLASTIC QUAD FLAT PACK TQFP (80PTQS)
HOLT INTEGRATED CIRCUITS
57
HI-3200, HI-3201
REVISION HISTORY
Document Rev. Date
Description of Change
DS3200
Initial Release.
Corrected typo in ordering information.
Corrected fonts in numerous block diagrams.
Added description for register 0x8035, “ARINC 429 TX Ready INT Enable”. Updated
QFN package dimensions.
Updated Programming for Auto-Initialization EEPROM section. Update Reflow Solder
Temperature.
Added description of ARINC 429 Receive Pending Interrupt Register, ARINC 429
Receive Interrupt Mask Register and ARINC 429 Receive Interrupt Address Registers.
Reverse direction of signals on EEPROM in Block Diagram and Examples 4, 5 and 8.
Add “bar” (active low) to CCSB, ECSB and HCSB signals in Pin Descriptions. Updated
PQFP-64, QFN-64 and PQFP-80 package drawings.
Clarified description of Repetition Rate Register.
Add notes to clear RBFFAIL bit before applying RESET for modes 2 and 3. Add
description of ARINC 429 Muxed FIFO Flags Register and ARINC 429 Tx Ready Bits
Register.
Clarify RUN pin needs to be low to use BIST in Mode 4.
Add tolerance for MCLK input. Correct label for RESET pin (should be MRST pin). Clarify
Active High status for AACK, AINT, MINT and MINTACK pins. Add table showing Start-up
time for each mode (The time from falling edge of MRST to READY pin high).
Specify Pull-up/Pull-down for digital inputs in Pin Description Table. Note EEPROM SPI
clock is 8 MHZ max. Specify max current for digital inputs. Specify maximum output
current for digital outputs.
Clarify function of TXxRDY bits and use of BIST.
New
A
B
C
5/4/11
1/25/12
4/16/12
5/7/13
D
8/13/13
E
10/21/13
F
11/4/13
G
H
01/29/14
08/04/14
I
J
11/04/15
09/06/16
K
10/19/16
L
06/19/17
HOLT INTEGRATED CIRCUITS
58
PACKAGE DIMENSIONS
64 PIN PLASTIC QUAD FLAT PACK (PQFP)
millimeters (inches)
Package Type: 64PQTS
0.50
BSC
(0.0197)
10.00
BSC SQ
(0.394)
12.00
(0.472) BSC SQ
0.22 ± 0.05
(0.009 ± 0.002)
.1.40 ± 0.05
(0.055 ± 0.002)
0.20 R max
(0.008)
See Detail A
1.60 max
(0.063
0° £ Q £ 7°
0.10 ± 0.05
(0.004 ± 0.002)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
0.08 R min
(0.003)
Detail A
64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
millimeters (inches)
Package Type: 64PCS
Electrically isolated heat
sink pad on bottom of
package
9.00
BSC
(0.354)
Connect to any ground or
power plane for optimum
thermal dissipation
7.25 ± 0.50
(0.285 ± 0.020)
0.50
BSC
(0.0197)
9.00
BSC
(0.354)
7.25 ± 0.50
(0.285 ± 0.020)
Top View
Bottom
View
0.25
typ
(0.10)
0.40 ± 0.10
(0.016 ± 0.004)
0.20
typ
(0.008)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
1.00
max
(0.039)
HOLT INTEGRATED CIRCUITS
59
PACKAGE DIMENSIONS
80 PIN PLASTIC QUAD FLAT PACK (PQFP)
millimeters (inches)
Package Type: 80PTQS
10.00
BSC SQ
(0.394)
12.00
(0.472) BSC SQ
0.40
BSC
(0.0157)
0.22 ± 0.05
(0.009 ± 0.002)
0.60 ± 0.15
(0.024 ± 0.006)
1.40 ± 0.05
(0.055 ± 0.002)
See Detail A
1.60 max
(0.630)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
0.10 ± 0.05
(0.004 ± 0.002)
HOLT INTEGRATED CIRCUITS
60
Detail A
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising