CB_I2C

CB_I2C
Features
•
•
•
•
•
•
•
•
•
•
•
•
Macrocell for Inter-IC communication using only two wires (serial clock and data)
Data rates up to 400K bit/sec.
ICs can be either masters or slaves (a master controls the communication bus)
Master and slave can both transmit and receive data
True multi-master protocol allows more than one master on an I2C bus
Each IC on the bus has a unique address
No theoretical limit to the number of ICs which can be attached to a bus (maximum
capacitance is 400 pF)
Small physical size (2000 gates)
Full support of the “Fast” I2C protocol
Baud rate control (software and hardware)
Includes a clock pre-scaler/divider to operate with a high-frequency input clock (over
12 MHz)
Minimum clock frequency of 6 MHz for a good input filter performance
Standard
Interface
Macrocell
Description
The Inter-Integrated Circuit Bus (I2C) has been developed by Philips for interconnecting devices on a system by a unique two-wire bus, comprising serial data (SDA) and
serial clock (SCL).
The CB_I2C macrocell handles bytes transferred autonomously to and from the I2C
bus. The status of the CB_I2C interface and bus can be read from an internal status
register automatically updated at each step of a transfer. It can be driven by a microcontroller or a dedicated sequencer through its internal registers: data, control,
address and status register.
The CB_I2C interface can operate, in “fast” mode or in “normal” mode; this allows
baud rates from 0 to 400K bit/sec. The device supports four modes: Master Transmitter, Master Receiver, Slave Transmitter and Slave Receiver.
The CB_I2C interface recognizes/generates START and STOP conditions, recognizes the stretched low period of the serial clock, adapts its baud rate to the received
SCL frequency, handles bus arbitration, recognizes/generates acknowledges, recognizes its own slave address and general calls.
The I2C has been adopted as a standard by the majority of consumer equipment manufacturers.
CB_I2C
Figure 1. System Diagram
SCL SDA
ASIC
SCOUT
SCIN
Customized
Logic
I/O
Cell
CB_I2C
SDOUT
SDIN
I/O
Cell
Rev. 0877B–09/98
1
Figure 2. CB_I2C Symbol
SCANAI
CB_I2C
SCANAO
SCANBI
SCANBO
SCANCI
SCANCO
SCANDI
Test
SCANDO
SHIFT
SA
Clock/Band Rate
BR0
CR0
BR1
CR1
BR2
CR2
BR3
CR10N
BRX0
CL8
BRX1
CL16
CLI2C
CL32
Interface
POC
ENCLRBIT
RDE
RDN<4:0>
WRN<2:0>
BE
IRI2C
IBT<7:0>
I2C Bus
SCIN
SDIN
2
<- clock ->
<- data ->
SCOUT
SDOUT
CB_I2C
Notes
• The five lines of the RDN bus are not exclusive. Each bit
selects one internal register. So to set more than one bit
to “0” will create contentions on the IBT bus.
• The three lines of the WRN bus are not exclusive. Each
bit select one internal register. So to set more than one
bit to “0” will load the data on the IBT bus into more than
one internal register.
• POC is a synchronous master reset. POC is loaded by
the falling edge of CLI2C.
• ENCLRBIT must be 1 to reset the S1CON.SI flag, during
the write cycle of S1CON.
• The four-line select bus RDN(4:0) selects the five
internal registers as follows:
RDN(4): internal status register (S1IST)
RDN(3): status register (S1STA)
RND(2): address register (S1ADR)
RDN(1): data register (S1DAT)
RDN(0): Control register (S1CON)
• The three-line write enable bus WRN(2:0) selects the
three (writable) internal registers as follows:
WRN(2): Address register (S1ADR)
WRN(1): Data register (S1DAT)
WRN(0): Control register (S1CON)
• During a read cycle of an internal register, RDE and BE
must be high.
• During a write cycle of an internal register, RDE and BE
must be low.
CB_I2C
Table 1. Pin Description
Signal Name
Type
Description
Scan Test Pins
SCANAI
Input
Scan chain input of first scan path
SCANBI
Input
Scan chain input of second scan path
SCANCI
Input
Scan chain input of third scan path
SCANDI
Input
Scan chain input of fourth scan path
SHIFT
Input
Scan mode select. Change during CLI2C low. While SHIFT=1, the scan test shift mode is
enabled.
SA
Input
Scan access. Active high during scan test. Used to control some multiplexers in scan mode.
SCANAO
Output
Scan chain output of first scan path
SCANBO
Output
Scan chain output of second scan path
SCANCO
Output
Scan chain output of third scan path
SCANDO
Output
Scan chain output of fourth scan path
Baud Rate Control
BR0/BR1/BR2/BR3
Input
Baud rate selection inputs
BRX0/BRX1
Input
External bit rate clock.
A rising edge at one of these inputs (as selected by BR2) is synchronized and converted to an
internal enable of one CLI2C cycle duration.
CLI2C
Input
I2C internal clock.
Minimum frequency = 6MHz.
Active edge = falling edge.
CR0/CR1/CR2
Output
Serial control register outputs.
Used to control the baud rate through the control register (software control).
CR10N
Output
Combination of CR1 and CR0: CR10N= CR1 + -CR0
CL8/CL16/CL32
Output
Clock output, frequency is CLI2C/8 - CLI2C/16 - CLI2C/32
Parallel Interface
POC
Input
Power-on-Clear. Synchronous master reset (High)
ENCLRBIT
Input
Enable signal. Interrupt flag (control register) can be cleared only when ENCLRBIT = 1
RDE
Input
Dynamic read enable. When used with an 80C51, RDE is connected to PH1S.
RDN(4:0)
Input
Read enable. Select the CB_I2C internal register to read. Active low.
WRN(2:0)
Input
Write enable. Select the CB_I2C internal register to write. Active low.
BE
Input
Bus enable. Control the CB_I2C internal tri-state buffers. When High, IBT is in output mode.
IBT(7:0)
InOut
Bi-directional data bus. Used to read/write data from/to the internal registers.
IRI2C
Output
CB_I2C interrupt request. Active High.
I2C Bus
SCIN
Input
Serial clock input (SCL)
SDIN
Input
Serial data input (SDA)
SCOUT
Output
Serial clock output (SCL)
SDOUT
Output
Serial data output (SDA)
3
Operating Modes
mode (fast/normal) and the clock input used to generate
the output baud rate.
Master Transmitter
In the Master/Transmitter mode the CB_I2C interface generates the START condition, the slave address and the
transfer direction bit, recognizes the slave acknowledge,
sends the data bytes and generates the STOP condition. If
no acknowledge is received, the CB_I2C interface generates the STOP condition and releases the bus. If it loses
the bus arbitration during the transfer of the slave address,
the CB_I2C interface switches to the slave mode to be able
to recognize its own slave address during the same transfer cycle.
Master Receiver
In the Master/Receiver mode the CB_I2C interface generates the START condition, the slave address and the transfer direction bit, generates the acknowledges at each data
byte received and the STOP condition (or repeated START
condition).
Slave Receiver
In the Slave/Receiver mode an interrupt is requested as
soon as the own slave address is recognized. The interface
generates acknowledges, and recognize the STOP condition.
Slave Transmitter
In the Slave/Transmitter mode the interface recognizes the
START and STOP conditions, its own slave address,
sends the data bytes (through the SDA line) adapting its
baud rate to the received serial clock frequency (SCL).
Baud Rate Selection
The CB_I2C MacroCell includes a clock pre-scaler. This
pre-scaler generates three clock signal: CL8
( CL I2 C_ fr e q /8 ) , CL 1 6 ( CL I 2C _f r eq /1 6 ) a n d CL 3 2
(CLI2C_freq/32). One (or more) of these outputs can be
used to generate a lower frequency clock from a high frequency master clock.
The baud rate can be driven by one of the three input clock
signals: CLI2C (master clock), BRX0, or BRX1. Note that
CLI2C is the MacroCell clock input (so it must not be
stopped and must be at least, of 6MHz), BRX0 and BRX1
are only used to generate the SCL signal. BRX0 and BRX1
are edge sensitive to be independent from the pulse duration and generates an enable of one CLI2C period.
If the CB_I2C interface has to be used with a high frequency master clock (CLI2C), one of the clock pre-scaler
outputs (CL8, CL16 or CL32) can be connected to one of
the external bit rate clocks (BRX1 or BRX0) to generate the
needed baud rate.
The output baud rate is selected by the four input signals
BR3, BR2, BR1 and BR0. The two MSBs select the I2 C
4
CB_I2C
Table 2. Output Baud Rate
BR3
BR2
Mode
Clock input
1
1
Normal
CLI2C
1
0
Fast
CLI2C
0
1
Normal
BRX1
0
0
Normal
BRX0
Note
In the normal mode the high-to-low ratio of the serial clock
(SCL) is 1:1 and the maximum baud rate is 100K bit/s. In
the fast mode, the high-to-low ratio of SCL is 2:3 and the
maximum baud rate is 400K bit/s.
The two LSBs of the baud rate selection bus are used to
select the ratio between the input frequency and the output
baud rate. In the following table “input_f” stands for the frequency of the selected input clock (CLI2C, BRX1 or BRX0):
Table 3. Input Frequency/Output Baud Rate Ratio
BR1
BR0
Normal mode
baud rate
Fast mode
baud rate
0
0
Input_f/120
Input_f/30
0
1
Input_f/100
Input_f/25
1
0
Input_f/80
Input_f/20
1
1
Input_f/60
Input_f/15
The baud rate selection bits of the control register are output (CR2, CR1 and CR0). An additional signal, CR10N is
output too:
CR10N = CR1 + -CR0
These four outputs can be connected to the baud rate
selection inputs (BR3, BR2, BR1 and BR0) to select the
output baud rate through the control register.
The following table gives you the output baud rate according to the values of the baud rate selection bits (BR3 to
BR0 lines), for some common master clock frequencies
(CLI2C).
CB_I2C
Table 4. Output Baud Rate According to Baud Rate Selection Bits
CLI2C
BR3
BR2
BR1
BR0
Output Bit Rate
6
8
10
12
MHz
1
1
0
0
f_CLI2C / 120
50
66.7
83.3
100
kHz
1
1
0
1
f_CLI2C / 100
60
80
100
---
kHz
1
1
1
0
f_CLI2C / 80
75
100
---
---
kHz
1
1
1
1
f_CLI2C / 60
100
---
---
---
kHz
1
0
0
0
f_CLI2C / 30
200
266.7
333.3
400
kHz
1
0
0
1
f_CLI2C / 25
240
320
400
---
kHz
1
0
1
0
f_CLI2C / 20
300
400
---
---
kHz
1
0
1
1
f_CLI2C / 15
400
---
---
---
kHz
0
1
0
0
f_BRX1 / 120
0
1
0
1
f_BRX1 / 100
0
1
1
0
f_BRX1 / 80
0
1
1
1
f_BRX1 / 60
0
0
0
0
f_BRX0 / 120
0
0
0
1
f_BRX0 / 100
0
0
1
0
f_BRX0 / 80
0
1
1
f_BRX0 / 60
0
Notes:
See
Note
Below
(1)
(2)
(1)
1. Normal mode, SCL high-to-low ratio = 1:1
2. Fast mode, SCL high-to-low ratio = 2:3
5
Internal Registers
S1ADR, the Address Register
7
ADD6
6
ADD5
5
ADD4
4
ADD3
3
ADD2
2
ADD1
1
ADD0
0
GC
S1ADR contains the 7-bit I2C address to which the CB_I2C interface will respond when programmed as a slave (transmitter
or receiver). The “Own-Slave-Address” is stored in the 7 most significant bits of S1ADR. The LSB is used to enable the recognition of the “general call address”.
When GC is set to “1” the CB_I2C interface will generate an interrupt (IRI2C line) when the “general call address” is recognized. Otherwise, the CB_I2C will generate an interrupt only when its “Own Slave Address” is recognized.
This register could be loaded with the I2C chip address during the initialization steps.
S1DAT, the Data Shift Register
7
DAT7
6
DAT6
5
DAT5
4
DAT4
3
DAT3
2
DAT2
1
DAT1
0
DAT0
S1DAT contains the incoming byte (just received from the I2C bus) in the receiver mode and the outgoing data (to be send
to the I2C bus) in the transmitter mode.
S1DAT is always shifted from right to left. It means, the first bit transmitted to the I 2C bus is the MSB in the transmitter
mode, and the MSB is the first bit received from the I2C bus in the receiver mode.
During a transmission (when the CB_I2C send data to the I2C bus) while the data is shifted out, the value on the SDA line
is shifted in. So in case of an arbitration lost, S1DAT will contains the correct data (the value read from the bus).
S1CON, the Control Register
7
CR2
6
ENS1
5
STA
4
STO
3
SI
2
AA
1
CR1
0
CR0
S1CON is used to control the CB_I2C interface. By setting the bits of this register you can make the CB_I2C interface generate a START condition, a STOP condition, an acknowledge, you can also control the output bit rate (see “Baud Rate
Selection” on page 4).
The bits of S1CON have the following meanings and functions:
ENS1
enables (or disables) the CB_I2C interface. When set to “0”, the CB_I2C is in “not addressed” slave mode. It means, no
START (or STOP) condition can be generated, the “Own Slave Address” (or the “general call address”) is not recognized/acknowledged, the SCL and SDA lines are disabled (no output is generated, and no input is taken into account).
When set to “1” the CB_I2C is enabled and can perform transmissions in master or slave mode.
It is not recommended to use ENS1 to disable an acknowledge (or the recognition of the chip address), because while
ENS1 is set to “0”, the CB_I2C keeps no trace of the I2C bus status.
STA
enables the generation of a START condition. When set to “1”, the CB_I2C enters the master mode, checks the status of
the I2C bus and generates a START condition if the bus if free. If the bus is not free, the CB_I2C will wait until a STOP condition to generate a START condition (after a minimum time). Set to “0” put the CB_I2C in the slave mode.
STO
controls the generation of a STOP condition. When set to “1” while being in master mode, the CB_I2C generates a STOP
condition. When the STOP condition is detected on bus, the STO bit is automatically cleared. In slave mode the STO bit is
used to recover from a bus error. In such a case, no STOP condition is transmitted, but the interface do as if a STOP condition has been received and switch to the “not addressed” slave mode (the STO bit is then cleared by the interface).
6
CB_I2C
CB_I2C
SI
is a flag/control bit. SI is set to “1” by the CB_I2C interface to indicate that an interrupt has to be serviced. When SI is “1” the
IRI2C line is high, and the SCL line is pulled low. The SI flag must be reset by the controller/sequencer driving the CB_I2C
interface. It means the transfer is suspend until the SI flag is reset.
AA
is the Assert Acknowledge flag. When set to “1” an acknowledge is returned when the “own slave address” is received (or
the general call address has been received while S1ADR.GC is “1”), or when a data byte has been received while being in
the receiver mode.
When AA is reset to “0”, no acknowledge is returned (SDA remains high during the acknowledge SCL clock pulse).
CR2-CR1-CR0
can be used to select the output baud rate. These 3 bits are connected to the CR2-CR1-CR0 outputs of the ES2IC interface. If the CR2-CR1-CR0 outputs are connected to BR inputs, the output baud rate can be selected by loading the appropriate values into S1CON (see “Baud Rate Selection” on page 4).
S1STA, the Status Register
7
ST4
6
ST3
5
ST2
4
ST1
3
ST0
2
0
1
0
0
0
S1STA is the status register. The 3 LSBs of S1STA are always “0”, the 5 MSBs contain the interface status code. S1STA is
updated after each change on the interrupt request line (IRI2C). S1STA should be read after each interrupt request (IRI2C
goes high) to determine the current state of the CB_I2C interface, and the next action to perform (e.g: load the receive data
byte, suspend transfer, generate STOP condition, send data byte,...).
In the following tables are for each value of S1STA, the meaning (current state of the interface), the next action to be performed by the controller/sequencer driving the CB_I2C interface, and the next action the CB_I2C will perform.
In these tables, the following abbreviation are used:
SLA => Slave address
S => START condition
R => Read
W => Write
ACK => Acknowledge
P => STOP condition
MST => Master
SLV => Slave
REC => Receiver
TRX => Transmitter
7
Table 5. Master/Transmitter Mode
Status
Code
Meaning
(status of CB_I2C)
Next action to be done by the controller
Next action CB_I2C will perform
08H
START condition has
been transmitted
Load S1DAT with slave address
and R/W bit. Reset S1CON.SI
Slave address + R/W will be
transmitted. Wait ACK.
10H
Repeated START
condition
transmitted
Load S1DAT with slave address
and R/W bit. Reset S1CON.SI
As above. If R/W = R, CB_I2C
switch into receiver mode.
Load S1DAT with data byte.
Reset S1CON.SI.
--- OR --Set S1CON.STA. Reset S1CON.SI
--- OR --Set S1CON.STO. Reset S1CON.SI
--- OR --Set S1CON.STA, S1CON.STO and reset
S1CON.SI.
Data byte will be transmitted
Wait for ACK.
18H
SLA + W has been sent
ACK received.
Generates repeated START condition
Generates STOP condition.
Generates STOP condition, then generates
a START condition
20H
SLA + W has been sent,
no ACK received.
As above.
As above.
28H
Data byte transmitted
ACK received.
As above.
As above.
30H
Data byte transmitted
no ACK received.
As above.
As above.
Reset S1CON.SI.
--- OR --Set S1CON.STA, reset S1CON.SI
Release I2C bus, switch to slave mode.
38H
Arbitration lost in
SLA + R/W or data byte
Wait until the I2C bus is free to generate a
START condition
Table 6. Master/Receiver Mode
Status
Code
Meaning
(status of CB_I2C)
Next action to be done by the controller
Next action CB_I2C will perform
08H
START condition has
been transmitted
Load S1DAT with slave address
and R/W bit. Reset S1CON.SI
Slave address + R/W will be
transmitted. Wait ACK.
10H
Repeated START
condition transmitted.
Load S1DAT with slave address
and R/W bit. Reset S1CON.SI
As above. If R/W = W, CB_I2C
switch into transmitter mode.
Release I2C bus, switch to slave mode.
Arbitration lost in
SLA + R/W or data byte
Reset S1CON.SI
--- OR --Set S1CON.STA, reset S1CON.SI
38H
Reset S1CON.SI. Set S1CON.AA
40H
8
SLA + R has been sent
ACK received.
--- OR --Reset S1CON.SI. Reset S1CON.AA
CB_I2C
Wait until the I2C bus is free to generate a
START condition
Data byte will be received,
ACK will be returned.
Data byte will be received,
no ACK will be returned.
CB_I2C
Table 6. Master/Receiver Mode
Status
Code
48H
50H
58H
Meaning
(status of CB_I2C)
Next action to be done by the controller
Next action CB_I2C will perform
Set S1CON.STA. Reset S1CON.SI
--- OR --Set S1CON.STO. Reset S1CON.SI
--- OR --Set S1CON.STA, S1CON.STO and reset
S1CON.SI.
Generates repeated START condition
Data byte received,
ACK returned.
Read data byte, reset S1CON.SI
set S1CON.AA
--- OR --Read data byte, reset S1CON.SI
reset S1CON.AA
New data byte will be received
and ACK will be returned.
Generates repeated START condition
Data byte received
no ACK returned.
Read data byte, Set S1CON.STA
Reset S1CON.SI
--- OR --Read data byte, Set S1CON.STO
Reset S1CON.SI
--- OR --Read data byte, Set S1CON.STA,
S1CON.STO and reset S1CON.SI.
Next action to be done by the controller
Next action CB_I2C will perform
Reset S1CON.SI, S1CON.AA = 1
Data byte will be received,
ACK returned.
SLA+R has been sent
no ACK received.
Generates STOP condition
Generates STOP condition, then generates
a START condition
New data byte will be received
and no ACK will be returned.
Generates STOP condition.
Generates STOP condition, then
generates a START condition
Table 7. Slave/Receiver Mode
Status
code
60H
Meaning
(status of CB_I2C)
Own SLA + W received,
ACK returned.
--- OR --Reset S1CON.SI, S1CON.AA = 0
Data byte will be received,
no ACK returned.
Arbitration lost in SLA,
Own SLA received
ACK returned.
As above.
As above.
68H
General call address
received + ACK
returned
As above.
As above.
70H
As above.
As above.
78H
Arbitration lost in SLA,
general call ADD
received + ACK
returned
Addressed with Own
SLA, data byte received
+ ACK returned
As above.
As above.
80H
9
Table 7. Slave/Receiver Mode
Status
code
88H
Meaning
(status of CB_I2C)
Addressed with Own
SLA, data received,
no ACK returned
Next action to be done by the controller
Next action CB_I2C will perform
Read data byte, reset S1CON.SI
reset S1CON.AA
--- OR --Read data byte, reset S1CON.SI
set S1CON.AA
Switch to “not addressed” SLV mode. Own
SLA/general call recognition disabled.
--- OR --Read data byte, reset S1CON.SI
reset S1CON.AA, set S1CON.STA
--- OR --Read data byte, reset S1CON.SI
set S1CON.AA, set S1CON.STA
90H
98H
Addressed by general
call address, data byte
received,
ACK returned.
Addressed by general
call address, data byte
received, no ACK
returned.
A0H
10
Switch to “not addressed” SLV mode. Own
SLA/general call recognition disabled.
START will be transmitted as soon as the
bus becomes free.
Switch to “not addressed” SLV mode.
Acknowledge own SLA and general call (if
S1ADR.GC = 1)
START condition will be sent as soon as the
bus is free.
Read data bye, reset S1CON.SI
set S1CON.AA
--- OR --Read data byte, reset S1CON.SI
reset S1CON.AA
Data byte will be received,
ACK returned.
Read data byte, reset S1CON.SI
set S1CON.AA
Switch to “not addressed” SLV mode.
Acknowledge own SLA and general call (if
S1ADR.GC = 1)
--- OR --Read data byte, reset S1CON.SI
reset S1CON.AA
--- OR --Read data byte, reset S1CON.SI
set S1CON.AA, set S1CON.STA
--- OR ---
STOP or repeated
START condition has
been received while
addressed as SLV/REC
or SLV/TRX.
Switch to “not addressed” SLV mode.
Acknowledge own SLA and general call (if
S1ADR.GC = 1)
Data byte will be received,
no ACK returned.
Switch to “not addressed” SLV mode. Own
SLA/general call recognition disabled.
Switch to “not addressed” SLV mode.
Acknowledge own SLA and general call (if
S1ADR.GC = 1) START condition will be
sent as soon as the bus is free.
Read data byte, reset S1CON.SI
reset S1CON.AA, set S1CON.STA
Switch to “not addressed” SLV mode. Own
SLA/general call recognition disabled.
START will be transmitted as soon as the
bus becomes free.
As above.
As above.
CB_I2C
CB_I2C
Table 8. Slave/Transmitter Mode
Status
Code
A8H
Meaning
(status of CB_I2C)
Own SLA received,
ACK returned
Next action to be done by the controller.
Next action CB_I2C will perform.
Load data byte, reset S1CON.SI
set S1CON.AA
--- OR --Load data byte, reset S1CON.SI
reset S1CON.AA
A new data byte will be transmitted.
Last data byte will be transmitted.
Arbitration lost in SLA,
own SLA received
ACK returned.
As above.
As above.
B0H
Data byte has been
transmitted, ACK has
been received
As above.
As above.
B8H
Reset S1CON.SI, S1CON.AA = 0,
S1CON.STA = 0
Switch to “not addressed” SLV mode.
Own SLA/general call recognition
disabled.
--- OR --Reset S1CON.SI, S1CON.AA = 1,
S1CON.STA = 0
C0H
Data byte has been
transmitted, no ACK
received
--- OR --Reset S1CON.SI, S1CON.AA = 0,
S1CON.STA = 1.
--- OR --Reset S1CON.SI, S1CON.AA = 1,
S1CON.STA = 1
C8H
Last data byte has
been transmitted, ACK
received.
Switch to “not addressed” SLV mode.
Acknowledge own SLA and general call
(if S1ADR.GC = 1)
Switch to “not addressed” SLV
mode. Own SLA/general call
recognition disabled. START
will be transmitted as soon as
the bus becomes free.
Switch to “not addressed” SLV
mode. Acknowledge own SLA and
general call (if S1ADR.GC = 1)
START condition will be sent
as soon as the bus is free.
As above.
As above.
Next action to be done by the controller.
Next action CB_I2C will perform.
Table 9. Miscellaneous States
Status
code
Meaning
(status of CB_I2C)
F8H
No information: The CB_I2C can be proceeding with a transfer, or waiting to be addressed.
00H
Bus error.
Reset S1CON.SI, set S1CON.STO
In all cases, the bus is released,
CB_I2C switches to the “not addressed”
SLV mode, then STO is cleared.
11
Detailed Modes of Operation
The following sequences are not to be followed word-by-word; they are included here to help those who are not familiar
with the I2C interfacing, for those who are beginning with the CB_I2C interface, and to give examples for each major mode
of operation of the CB_I2C MacroCell. In the following sections, when a diagram is included, no value is given for the constraints (because they are process dependent).
Initialization
To initialize the CB_I2C interface, reset the internal registers by setting POC to “1”. On the first clock cycle (high-to-low
edge of CLI2C) POC is loaded into a D-flip-flop to generate the internal signal POCC. POCC is then used as a synchronous reset by all the registers (and memory elements of the CB_I2C). To be taken into account POC should be high during
one CLI2C period. The following diagram shows the constraints on POC:
Figure 3. POC Constraints
CLI2C
POC
PocS
PocH
PocS = POC to CLI2C (high-to-low edge) setup time
PocH = POC from CLI2C (high-to-low edge) hold time
Then (once POC is back to “0”) load the own slave address (the I2C address of your chip) and the general call bit, into the
address register (S1ADR): set WRN(2) = 0, RDE = 0 and BE = 0, apply the own slave address and the GC bit onto the IBT
bus (the data present on IBT is loaded into S1ADR on the next high-to-low edge of CLI2C). The following diagram shows a
write cycle of the S1ADR internal register:
Figure 4. S1ADR Internal Register Write Cycle
CLI2C
RDE
BE
WRN (2:0)
7H
3H
WrnS
IBT (7:0)
WrnH
own slave address
IbtS
WrnS = write enable (WRN) to CLI2C (high-to-low edge) setup time
WrnH = write enable (WRN) from CLI2C (high-to-low edge) hold time
IbtS = data (IBT) to CLI2C (high-to-low edge) setup time.
IbtH = data (IBT) from CLI2C (high-to-low edge) hold time.
12
7H
CB_I2C
IbtH
CB_I2C
Note
The “X” value on the BE and RDE lines means those lines can be either “1” or “0”.
To enable the CB_I2C interface, set the S1CON.ENS1 bit to “1”. In the same write cycle of S1CON, you can set
S1CON.AA to “1”, if you want to recognize the chip address (own slave address previously loaded into S1ADR) and general calls (if S1ADR.GC = 1), set the output baud rate through S1CON.CR2, S1CON.CR1 and S1CON.CR0 (if the baud
rate is to be selected by software). Once S1CON.ENS1 is set, the CB_I2C interface begins checking the I2C bus. If its own
slave address or a general call is detected (and if S1CON.AA = 1) it generates an interrupt request on the IRI2C output and
loads the corresponding status word into S1STA.
The following diagram shows a write cycle of the S1CON internal register:
Figure 5. S1CON Internal Register Write Cycle
CLI2C
RDE
BE
WRN (2:0)
7H
6H
WrnS
IBT (7:0)
7H
WrnH
control word
IbtS
IbtH
WrnS = write enable (WRN) to CLI2C (high-to-low edge) setup time
WrnH = write enable (WRN) from CLI2C (high-to-low edge) hold time
IbtS = data (IBT) to CLI2C (high-to-low edge) setup time.
IbtH = data (IBT) from CLI2C (high-to-low edge) hold time.
Note
The “X” value on the BE and RDE lines means those lines can be either “1” or “0”.
13
Master Transmitter Mode
Before starting the Master/Transmitter mode,
S1CON.ENS1 must be “1”. To start a transfer in Master/Transmitter mode, set S1CON.STA to “1” (during the
same write cycle of S1CON, ENS1 must stay “1”, CR2CR1-CR0 can be used to select the output baud rate, and
AA could be changed). If AA is set to “1”, in case of a loss
of arbitration during the slave address transfer (and direction bit) onto the I2C bus, the CB_I2C will be able to recognize its own slave address (or a general call) and generate
an acknowledge during the same I 2C bus cycle.
Once S1CON.STA is set to “1”, the CB_I2C will test the I2C
bus and generate a START condition as soon as the bus is
free. When the START condition is recognized on the I2C
bus, the interrupt request line (IRI2C) goes high and the
status register (S1STA) loads the appropriate value (08H).
The SI flag (in the control register, S1CON) is also set to
stop the CB_I2C. At this time (in response to the interrupt
request), the controller/sequencer which drives the CB_I2C
interface should perform the following actions:
• load the slave address into the data register (S1DAT).
• reset the SI flag (from the control register, S1CON).
Notes
• If the controller/sequencer can not answer to the CB_I2C
interrupt request (it is performing a real-time task or
treating an interrupt request of an higher priority), the
CB_I2C will stay in a “frozen” state and pull low the SCL
line until the S1CON.SI flag is reset to “0”.
• In the Master/Transmitter mode the LSB of the data byte
loaded into the data register as the slave address is “0”
(it is the direction bit).
The following diagram shows the beginning of a transfer in
Master/Transmitter mode (the read and write cycles of the
internal registers are not detailed):
Figure 6. Beginning of a Transfer in Master/Transmitter Mode
WRN (2:0)
IBT (7:0)
6H
7H
data in
3H
08H
7H
data in
6H
data in
BE/RDE
RDN (4:0)
1FH
17H
1FH
IRI2C
interrupt
request
SCL
START
condition
SDA
write
S1CON
(STA = 1)
14
CB_I2C
read
S1STA
write
S1ADR
reset
S1CON.SI
7H
CB_I2C
Notes
In order to reset the S1CON.SI flag, the input line ENCLRBIT must be set to 1 during the write cycle of S1CON.
“data_in” means a data byte is written into an internal register. BE and RDE have been grouped to make the diagram
more readable; they could be grouped or generated separately in your application.
Once the interrupt flag of the control register (S1CON.SI) is
cleared, the interrupt request line (IRI2C) goes back low
and the CB_I2C interface starts transmitting the slave
address. After the transmission of the last bit (8th) of the
slave address, the CB_I2C releases the SDA line to let the
slave acknowledge its address during the next (9th) SCL
clock pulse. After the ninth SCL clock pulse the status register (S1STA) is updated with the appropriate value (18H if
the acknowledge has been received, 20H if not), and the
interrupt request line goes high to highlight the end of the
first byte transfer (the interrupt flag, S1CON.SI is also set).
The controller/sequencer driving the CB_I2C interface
should then perform the following tasks:
• read the status register (S1STA).
If an acknowledge has been received:
• write the next data byte into the data register (S1DAT)
• clear the interrupt flag (S1CON.STA)
It can also:
• set the STOP bit of the control register, to generate a
STOP condition, or
• set the START bit of the control register, to generate a
repeated START condition, or
• set the START and STOP bits of the control register, to
generate a STOP condition, then a START condition.
• If no acknowledge has been received:
• clear the interrupt flag (S1CON.STA), write the STOP bit
of the control register to generate a STOP condition (or
write the START bit to generate a repeated START
condition).
If the arbitration has been lost, the CB_I2C interface
releases the SDA and SCL lines (to free the I2C bus for the
winning master), generate an interrupt request (IRI2C line)
and load the value 38H into the status register (S1STA). If
the assert acknowledge bit of the control register is “1”, the
CB_I2C interface can recognize its own address and generate an acknowledge in the same I2C bus cycle.
It means, in case of two masters (called MA and MB) generating at the same time, the START condition and the
slave address; if MA is calling MB and MB loses the arbitration, MB will generate a START condition, send the slave
address, (lose the arbitration), switch into the slave mode,
recognize its own slave address and generate an acknowledge (if S1CON.AA = 1) in the same I2C bus cycle (during
the 9 SCL clock cycles).
For each data byte to send the sequence will be as follows:
• write the data byte into the CB_I2C data register
(S1DAT),
• clear the interrupt request flag (S1CON.SI),
CB_I2C sends data byte...
CB_I2C releases the SDA line and generates the ninth
SCL pulse...
the receiver generates the acknowledge...
CB_I2C generates an interrupt request (IRI2C)...
• read the status register,
• write the next data byte into the data register,
• clear the interrupt flag, etc...
The last data byte transfer will be:
• write the data byte into the CB_I2C data register
(S1DAT),
• clear the interrupt request flag (S1CON.SI),
CB_I2C sends data byte...
CB_I2C releases the SDA line and generates the ninth
SCL pulse...
the receiver generates the acknowledge...
CB_I2C generates an interrupt request (IRI2C)...
• read the status register,
• clear the interrupt request bit (S1CON.SI), set the stop
bit (S1CON.STO),
CB_I2C generates the STOP condition...
Once the STOP condition is detected on the I2C bus,
the stop bit is cleared...
Master Receiver Mode
Before starting the Master/Receiver mode, S1CON.ENS1
must be “1”. To start a transfer in Master/Receiver mode,
set S1CON.STA to “1” (during the same write cycle of
S1CON, ENS1 must stay “1”, CR2-CR1-CR0 can be used
to select the output baud rate, and AA could be changed). If
AA is set to “1”, in case of a loss of arbitration during the
slave address transfer (and direction bit) onto the I2C bus,
the CB_I2C will be able to recognize its own slave address
(or a general call) and generate an acknowledge during the
same I2C bus cycle.
Once S1CON.STA is set to “1”, the CB_I2C will test the I2C
bus and generate a START condition as soon as the bus is
free. When the START condition is recognized on the I2C
bus, the interrupt request line (IRI2C) goes high and the
status register (S1STA) loads the appropriate value (08H).
The SI flag (in the control register, S1CON) is also set to
stop the CB_I2C. At this time (in response to the interrupt
request), the controller/sequencer which drives the CB_I2C
interface should perform the following actions:
15
• load the slave address into the data register (S1DAT).
• reset the SI flag (from the control register, S1CON).
Notes
• In the Master/Receiver mode the LSB of the data byte
loaded into the data register is “1” (slave address).
• The first I2C bus cycle (transfer of the slave address and
direction bit, and bus arbitration) is as in the
Master/Transmitter mode.
Then before receiving any data byte, the assert acknowledge bit of the control register should be set to “1” to
acknowledge the received data byte. If for any reason, the
transfer has to be suspended, or before receiving the last
data byte, the assert acknowledge bit of the control register
(S1CON.AA) must be reset to “0” in order for the CB_I2C
interface not to generate an acknowledge at the end of the
next I2C bus cycle. Then the stop bit of the control register
should be set, for the CB_I2C operating in master mode to
generate the STOP condition.
The assert acknowledge bit should be reset at the beginning of the last data byte transfer. By returning no acknowledge, the receiver informs the transmitter that the current
data byte is the last one.
The data bytes transfer cycles are as follows:
• clear the interrupt request flag (S1CON.SI),
CB_I2C receives data byte...
CB_I2C generates the ninth SCL pulse and the
acknowledge...
CB_I2C generates an interrupt request (IRI2C)...
• read the status register,
• read the received data byte from the data register,
• clear the interrupt flag, etc...
The last data byte transfer will be:
• clear the interrupt request flag (S1CON.SI), clear the
assert acknowledge bit of the control register
(S1CON.AA),
CB_I2C receives data byte...
CB_I2C generates the ninth SCL pulse not the
acknowledge...
CB_I2C generates an interrupt request (IRI2C)...
• read the status register,
• read the received data byte from the data register,
• clear the interrupt flag, set the stop bit of the control
register (S1CON.STO),
CB_I2C generates the STOP condition...
Once the STOP condition is detected on the I2C bus,
the stop bit is cleared...
16
CB_I2C
Slave Receiver Mode
As for the other modes, before starting the Slave/Receiver
mode, S1CON.ENS1 must be “1”. In order for the CB_I2C
interface to recognize its own slave address (or a general
call), the assert acknowledge bit of the control register
(S1CON.AA) must be set (S1CON.AA = 1). In the slave
mode, the values of the BR3-BR2-BR1-BR0 lines does not
affect the transfer baud rate; the CB_I2C adapts its input
baud rate to the master baud rate.
Once the own slave address has been recognized, an
interrupt request is generated (IRI2C line goes high), the
status register loads the appropriate value, and the interrupt flag of the control register (S1CON.SI) is set to “1”. The
CB_I2C will pull low the SDA line until the interrupt flag
(S1CON.SI) is reset.
Once S1CON.SI is reset, the SDA line is released and the
interrupt request line goes back low. While resetting the
S1CON.SI flag, the assert acknowledge bit (S1CON.AA)
could be set (or reset) in order for the CB_I2C interface to
generate (or not) an acknowledge after the next data byte
is received. S1CON.AA can be set (or reset) during a data
byte transfer to stop a transmission and isolate the CB_I2C
interface from the I2C bus. In such a case, the current data
byte transfer will continue until the end, no acknowledge
will be returned, and the bus master will generate the
STOP condition. An interrupt request is generated (and has
to be treated) after the following events:
• own slave address received while S1CON.AA = 1
(acknowledge returned)
• generate call address received while S1CON.AA = 1 and
S1ADR.GC = 1 (acknowledge returned)
• arbitration lost in master mode, own slave address
received while S1CON.AA = 1 (acknowledge returned)
• arbitration lost in master mode, general call address
received while S1CON.AA = 1 and S1ADR.GC = 1
(acknowledge returned)
• a data byte has been received while being in
Slave/receiver mode, acknowledge returned (or no
acknowledge returned)
• a STOP or repeated START condition has been received
while being in slave mode (Slave/Receiver or
Slave/Transmitter).
CB_I2C
Slave Transmitter Mode
Bus Error
As for the other modes, before starting the Slave/Transmitter mode, S1CON.ENS1 must be “1”. In order for the
CB_I2C interface to recognize its own slave address (or a
general call), the assert acknowledge bit of the control register (S1CON.AA) must be set (S1CON.AA = 1). In the
slave mode, the values of the BR3-BR2-BR1-BR0 lines
does not affect the transfer baud rate; the CB_I2C adapt its
input baud rate to the master baud rate.
Once the own slave address has been recognized, an
interrupt request is generated (IRI2C line goes high), the
status register loads the appropriate value, and the interrupt flag of the control register (S1CON.SI) is set to “1”. The
CB_I2C will pull low the SDA line until the interrupt flag
(S1CON.SI) is reset.
Once S1CON.SI is reset, the SDA line is released and the
interrupt request line goes back low. While resetting the
S1CON.SI flag, the assert acknowledge bit (S1CON.AA)
could be set (or reset). S1CON.AA can also be set (or
reset) during a data byte transfer to stop a transmission
and isolate the CB_I2C interface from the I2C bus. In such
a case, the current data byte transfer will continue until the
end, the status register will load the value C8H (and generate an interrupt request) and ignore the master receiver; no
more data byte will be transmitted. It means the master
receiver will continue reading “1” (as data) from the I2C bus
(“1” is the “default” value of the I 2C bus, and the acknowledge is generated by the receiver).
An interrupt request is generated (and has to be treated)
after the following events:
• own slave address received while S1CON.AA = 1
(acknowledge returned)
• generate call address received while S1CON.AA = 1 and
S1ADR.GC = 1 (acknowledge returned)
• arbitration lost in master mode, own slave address
received while S1CON.AA = 1 (acknowledge returned)
• arbitration lost in master mode, general call address
received while S1CON.AA = 1 and S1ADR.GC = 1
(acknowledge returned)
• a data byte has been transmitted while being in
Slave/Transmitter mode, acknowledge received (or no
acknowledge received)
• the last data byte has been transmitted while being in
Slave/Transmitter mode, acknowledge received (or no
acknowledge received).
A bus error is detected when a START or a STOP condition
occurs at an illegal position in the I2C transfer cycle. In such
a case, the CB_I2C interface generates an interrupt
request (IRI2C line), loads the status register with 00H and
releases the SDA and SCL lines.
To recover from a bus error, it is recommended to set the
S1CON.STO (STOP bit of the control register) to “1”, and
to reset the interrupt flag (S1CON.SI). then the CB_I2C
interface will not generate any STOP condition (because a
bus error has been detected), but it will act as if a STOP
condition has been produced; It will reset the STOP bit and
enter a defined state.
If a superfluous START condition is generated or a STOP
condition is masked, the I 2 C bus can stay “busy” indefinitely. To exit from the “bus busy” state, set the STOP bit.
The CB_I2C will not generate any STOP condition but will
behave as if a STOP condition was received, then it will
clear the STOP bit, exit from the “bus busy” state, and will
be able to generate a START condition.
17
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising