DDR4 8Gb B_die Unbuffered SODIMM_Rev1.1_Mar.15.book

DDR4 8Gb B_die Unbuffered SODIMM_Rev1.1_Mar.15.book
Rev. 1.1 Mar. 2015
M471A2K43BB1
M474A2K43BB1
260pin Unbuffered SODIMM
based on 8Gb B-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or otherwise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
(c) 2015 Samsung Electronics Co., Ltd. All rights reserved.
-1-
Unbuffered SODIMM
Rev. 1.1
datasheet
DDR4 SDRAM
Revision History
Revision No.
History
Draft Date
Remark
Editor
1.0
- First SPEC Release
Feb. 2015
-
J.Y.Lee
1.1
- Add VDDSPD tolerance on page 8
Mar. 2015
-
J.Y.Lee
- Change Function Block Diagram (without thermal sensor) on page 12
-2-
Unbuffered SODIMM
datasheet
Rev. 1.1
DDR4 SDRAM
Table Of Contents
260pin Unbuffered SODIMM based on 8Gb B-die
1. DDR4 Unbuffered SODIMM Ordering Information........................................................................................................ 4
2. Key Features................................................................................................................................................................. 4
3. Address Configuration .................................................................................................................................................. 4
4. Unbuffered SODIMM Pin Configurations (Front side/Back side) .................................................................................. 5
5. Pin Description ............................................................................................................................................................. 6
6. Input/Output Functional Description.............................................................................................................................. 7
7. Function Block Diagram ................................................................................................................................................ 9
7.1 16GB, 2Gx64 Module (Populated as 2 ranks of x8 DDR4 SDRAMs) ..................................................................... 9
7.2 16GB, 2Gx72 Module (Populated as 2 ranks of x8 DDR4 SDRAMs) .................................................................... 11
8. Absolute Maximum Ratings .......................................................................................................................................... 13
8.1 Absolute Maximum DC Ratings............................................................................................................................... 13
9. AC & DC Operating Conditions..................................................................................................................................... 13
9.1 Recommended DC Operating Conditions ............................................................................................................... 13
10. AC & DC Input Measurement Levels ......................................................................................................................... 14
10.1 AC & DC Logic Input Levels for Single-Ended Signals ......................................................................................... 14
10.2 AC and DC Input Measurement Levels : VREF Tolerances.................................................................................. 14
10.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 15
10.3.1. Differential Signals Definition ......................................................................................................................... 15
10.3.2. Differential Swing Requirements for Clock (CK_t - CK_c) ............................................................................. 15
10.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 16
10.4 Slew Rate Definitions ............................................................................................................................................ 17
10.4.1. Slew Rate Definitions for Differential Input Signals ( CK ) ............................................................................. 17
10.5 Differential Input Cross Point Voltage.................................................................................................................... 18
10.6 Single-ended AC & DC Output Levels................................................................................................................... 19
10.7 Differential AC & DC Output Levels....................................................................................................................... 19
10.8 Single-ended Output Slew Rate ............................................................................................................................ 19
10.9 Differential Output Slew Rate ................................................................................................................................ 20
10.10 Single-ended AC & DC Output Levels of Connectivity Test Mode ...................................................................... 21
10.11 Test Load for Connectivity Test Mode Timing ..................................................................................................... 21
11. DIMM IDD Specification Definition .............................................................................................................................. 22
12. IDD SPEC Table ......................................................................................................................................................... 25
13. Input/Output Capacitance ........................................................................................................................................... 28
14. Electrical Characterisitics and AC Timing ................................................................................................................... 29
14.1 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 29
14.2 Speed Bin Table Note ........................................................................................................................................... 32
15. Timing Parameters by Speed Grade .......................................................................................................................... 33
16. Physical Dimensions................................................................................................................................................... 39
16.1 1Gx8 based 2Gx64 Module (2 Ranks) - M471A2K43BB1 .................................................................................... 39
16.2 1Gx8 based 2Gx72 Module (2 Ranks) - M474A2K43BB1 .................................................................................... 40
-3-
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
1. DDR4 Unbuffered SODIMM Ordering Information
Number of
Rank
Part Number2
Density
Organization
Component Composition1
M471A2K43BB1-CPB/RC
16GB
2Gx64
1Gx8(K4A8G085WB-BC##)*16
2
30mm
M474A2K43BB1-CPB/RC
16GB
2Gx72
1Gx8(K4A8G085WB-BC##)*18
2
30mm
Height
NOTE :
1. "##" - PB/RC
2. RC(2400Mbps 17-17-17)
2. Key Features
Speed
•
•
•
•
•
•
•
•
•
•
•
•
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
11-11-11
13-13-13
15-15-15
17-17-17
Unit
tCK(min)
1.25
1.071
0.938
0.833
ns
CAS Latency
11
13
15
17
nCK
tRCD(min)
13.75
13.92
14.06
14.16
ns
tRP(min)
13.75
13.92
14.06
14.16
ns
tRAS(min)
35
34
33
32
ns
tRC(min)
48.75
47.92
47.06
46.16
ns
JEDEC standard 1.2V ± 0.06V Power Supply
VDDQ = 1.2V ± 0.06V
800 MHz fCK for 1600Mb/sec/pin,933 MHz fCK for 1866Mb/sec/pin, 1067MHz fCK for 2133Mb/sec/pin,1200MHz fCK for 2400Mb/sec/pin
16 Banks (4 Bank Groups)
Programmable CAS Latency: 10,11,12,13,14,15,16,17,18
Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
Programmable CAS Write Latency(CWL) = 9,11 (DDR4-1600) , 10,12 (DDR4-1866) , 11,14 (DDR4-2133) and 12,16 (DDR4-2400)
Burst Length: 8 , 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]
Bi-directional Differential Data Strobe
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower then TCASE 85C, 3.9us at 85C < TCASE 95C
Asynchronous Reset
3. Address Configuration
Organization
Row Address
Column Address
Bank Group Address
Bank Address
Auto Precharge
1Gx8(8Gb) based Module
A0-A15
A0-A9
BG0-BG1
BA0-BA1
A10/AP
-4-
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
4. Unbuffered SODIMM Pin Configurations (Front side/Back side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
VSS
2
VSS
79
DQ30
80
DQ31
157
CS1_n1
158
A13
235
VSS
236
DQ57
3
DQ5
4
DQ4
81
VSS
82
VSS
159
VDD
160
VDD
237
DQ56
238
VSS
VSS
240
DQS7_c
5
VSS
6
VSS
83
DQ26
84
DQ27
161
ODT1
C0,CS2_n,N
239
162
C
7
DQ1
8
DQ0
85
VSS
86
VSS
163
VDD
164
VREFCA
241
242
DQS7_t
C1,CS3_n,N
166
165
C
DM7_n/
DBI7_n
SA2
243
VSS
244
VSS
9
VSS
10
VSS
87
CB5,NC
88
CB4,NC
11
DQS0_c
12
DM0_n/
DBI0_n
89
VSS
90
VSS
167
VSS
168
VSS
245
DQ62
246
DQ63
13
DQS0_t
14
VSS
91
CB1,NC
92
CB0,NC
169
DQ37
170
DQ36
247
VSS
248
VSS
15
VSS
16
DQ6
93
VSS
94
VSS
171
VSS
172
VSS
249
DQ58
250
DQ59
17
DQ7
18
VSS
95
DQS8_c
96
DBI8_n
173
DQ33
174
DQ32
251
VSS
252
VSS
19
VSS
20
DQ2
97
DQS8_t
98
VSS
175
VSS
176
VSS
253
SCL
254
SDA
255
VDDSPD
256
SA0
21
DQ3
22
VSS
99
VSS
100
CB6,NC
177
DQS4_c
178
DM4_n/
DBI4_n
23
VSS
24
DQ12
101
CB2,NC
102
VSS
179
DQS4_t
180
VSS
257
VPP
258
Vtt
25
DQ13
26
VSS
103
VSS
104
CB7,NC
181
VSS
182
DQ39
259
VPP
260
SA1
27
VSS
28
DQ8
105
CB3,NC
106
VSS
183
DQ38
184
VSS
29
DQ9
30
VSS
107
VSS
108
RESET_n
185
VSS
186
DQ35
31
VSS
32
DQS1_c
109
CKE0
110
CKE1
187
DQ34
188
VSS
33
DM1_n/
DBI1_n
34
DQS1_t
111
VDD
112
VDD
189
VSS
190
DQ45
35
VSS
36
VSS
113
BG1
114
ACT_n
191
DQ44
192
VSS
37
DQ15
38
DQ14
115
BG0
116
ALERT_n
193
VSS
194
DQ41
39
VSS
40
VSS
117
VDD
118
VDD
195
DQ40
196
VSS
41
DQ10
42
DQ11
119
A12
120
A11
197
VSS
198
DQS5_c
200
DQS5_t
43
VSS
44
VSS
121
A9
122
A7
199
DM5_n/
DBI5_n
45
DQ21
46
DQ20
123
VDD
124
VDD
201
VSS
202
VSS
47
VSS
48
VSS
125
A8
126
A5
203
DQ46
204
DQ47
49
DQ17
50
DQ16
127
A6
128
A4
205
VSS
206
VSS
51
VSS
52
VSS
129
VDD
130
VDD
207
DQ42
208
DQ43
DM2_n/
DBI2_n
131
A3
132
A2
209
VSS
210
VSS
53
DQS2_c
54
55
DQS2_t
56
VSS
133
A1
134
EVENT_n
211
DQ52
212
DQ53
57
VSS
58
DQ22
135
VDD
136
VDD
213
VSS
214
VSS
59
DQ23
60
VSS
137
CK0_t
138
CK1_t
215
DQ49
216
DQ48
61
VSS
62
DQ18
139
CK0_c
140
CK1_c
217
VSS
218
VSS
63
DQ19
64
VSS
141
VDD
142
VDD
219
DQS6_c
220
DM6_n/
DBI6_n
65
VSS
66
DQ28
143
Parity
144
A0
221
DQS6_t
222
VSS
67
DQ29
68
VSS
145
BA1
146
A10/AP
223
VSS
224
DQ54
69
VSS
70
DQ24
147
VDD
148
VDD
225
DQ55
226
VSS
71
DQ25
72
VSS
149
CS0_n
150
BA0
227
VSS
228
DQ50
73
VSS
74
DQS3_c
151
A14/WE_n
DQ51
230
VSS
75
DM3_n/
DBI3_n
76
DQS3_t
153
VDD
154
VSS
232
DQ60
77
VSS
78
VSS
155
ODT0
156 A15/CAS_n 233
DQ61
234
VSS
152 A16/RAS_n 229
VDD
231
-5-
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
5. Pin Description
Pin Name
Description
Pin Name
Description
A0–A16
SDRAM address bus
SCL
I2C serial bus clock for SPD/TS
BA0, BA1
SDRAM bank select
SDA
I2C serial bus data line for SPD/TS
BG0, BG1
SDRAM bank group select
RAS_n1
WE_n
SDRAM row address strobe
2
SDRAM column address strobe
3
SDRAM write enable
CAS_n
CS0_n–CS1_n
PARITY
VDD
VPP
Rank Select Lines
C0,C1
CKE0, CKE1
SDRAM clock enable lines
ODT0, ODT1
Register on-die termination control lines
ACT_n
SA0~SA2
VREFCA
VSS
I2C slave address select for SPD/TS
SDRAM parity input
SDRAM I/O & core power supply
SDRAM activating power supply
Chip ID lines for 3DS components
SDRAM command/address reference supply
Power supply return (ground)
SDRAM activate
VDDSPD
Serial SPD/TS positive power supply
DIMM memory data bus
ALERT_n
SDRAM ALERT_n
DQS0_t–DQS8_t SDRAM data strobes
(positive line of differential pair)
RESET_n
Set SDRAMs to a Known State
DQS0_c–DQS8_c SDRAM data strobes
(negative line of differential pair)
EVENT_n
TS signals a thermal event has occurred
DQ0–DQ63
CB0–CB7
DM0_n-DM8_n,
DBI0_n-DBI8_n
DIMM ECC check bits
SDRAM data masks/data bus inversion
(x8-based x72 DIMMs)
VTT
Termination supply for the Address, Command and
Control bus
CK0_t, CK1_t
SDRAM clocks (positive line of differential pair)
NC
No connection
CK0_c, CK1_c
SDRAM clocks (negative line of differential pair)
NOTE :
1. RAS_n is a multiplexed function with A16.
2. CAS_n is a multiplexed function with A15.
3. WE_n is a multiplexed function with A14.
[ Table 1 ] Temperature Sensor Characteristics
Temperature Sensor Accuracy
Grade
Range
75 < Ta < 95
-
+/- 0.5
+/- 1.0
B
40 < Ta < 125
-
+/- 1.0
+/- 2.0
-20 < Ta < 125
-
+/- 2.0
+/- 3.0
Min.
Resolution
Typ.
0.25
-6-
Max.
Units
NOTE
-
C
-
C /LSB
-
-
Unbuffered SODIMM
datasheet
Rev. 1.1
DDR4 SDRAM
6. Input/Output Functional Description
Symbol
Type
CK0_t, CK0_c
CK1_t, CK1_c
Input
Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on the
crossing of the positive edge of CK_t and negative edge of CK_c.
CKE0, CKE1
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and device input
buffers and output drivers. Taking CKE LOW provides Precharge Power-Down and Self-Refresh operation
(all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit.
After VREFCA and Internal DQ Vref have become stable during the power on and initialization sequence,
they must be maintained during all operations (including Self-Refresh). CKE must be maintained high
throughout read and write accesses. Input buffers, excluding CK_t,CK_c, ODT and CKE, are disabled
during power-down. Input buffers,excluding CKE, are disabled during Self-Refresh.
CS0_n, CS1_n
CS2_n, CS3_n
Input
Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank
selection on systems with multiple Ranks. CS_n is considered part of the command code.
C0, C1
Input
Chip ID : Chip ID is only used for 3DS for 2and4 high stack via TSV to select each slice of stacked
component. Chip ID is considered part of the command code.
ODT0, ODT1
Input
On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the
DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and DM_n/DBI_n/, signal.
The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM.
ACT_n
Input
Activation Command Input : ACT_n defines the Activation command being entered along with CS_n. The
input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14
RAS_n/A16.
CAS_n/A15.
WE_n/A14
Input
Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the command being
entered. Those pins have multi function. For example, for activation with ACT_n Low, these are Addresses
like A16, A15 and A14 but for non-activation command with ACT_n High, these are Command pins for
Read, Write and other command defined in command truth table
DM_n/DBI_n
Input/
Output
Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data. Input data is masked
when DM_n is sampled LOW coincident with that input data during a Write access. DM_n is sampled on
both edges of DQS. DM is muxed with DBI function by Mode Register A10, A11, A12 setting in MR5. For x8
device, the function of DM is enabled by Mode Register A11 setting in MR1. DBI_n is an input/output
identifing whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/output
after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH.
BG0 - BG1
Input
Bank Group Inputs: BG0 - BG1 define which bank group an Active, Read, Write or Precharge command is
being applied. BG0 also determines which mode register is to be accessed during a MRS cycle. For x4/x8
based SDRAMs, BG0 and BG1 are valid. For x16 based SDRAM components only BG0 is valid.
BA0 - BA1
Input
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is
being applied. Bank address also determines which mode register is to be accessed during a MRS cycle.
A0 - A16
Input
Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/Write
commands to select one location out of the memory array in the respective bank. A10/AP, A12/BC_n,
RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions. See other rows. The address inputs
also provide the op-code during Mode Register Set commands.
A10 / AP
Input
Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should
be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no
Autoprecharge). A10 is sampled during a Precharge command to determine whether the Precharge applies
to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected
by bank addresses.
A12 / BC_n
Input
Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if burst chop (on-the-fly)
will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details.
RESET_n
CMOS
Input
Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is
HIGH. RESET_n must be HIGH during normal operation.
DQ
Input/
Output
Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at
the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the internal Vref level during test via Mode
Register Setting MR4 A4=High. Refer to vendor specific datasheets to determine which DQ is used.
Input/
Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write
data. DDR4 SDRAMs support differential data strobe only and does not support single-ended.
DQS_t, DQS_c
Function
-7-
datasheet
Unbuffered SODIMM
PARITY
Input
ALERT_n
Output
SA0-SA1
Input
RFU
DDR4 SDRAM
Command and Address Parity Input: DDR4 Supports Even Parity check in DRAMs with MR setting. Once
it’s enabled via Register in MR5, then SDRAM calculates Parity with ACT_n, RAS_n/A16, CAS_n/A15,
WE_n/A14, BG0-BG1, BA0-BA1, A16-A0. Input parity should be maintained at the rising edge of the clock
and at the same time with command & address with CS_n LOW
ALERT: It has multi functions such as CRC error flag , Command and Address Parity error flag as Output
signal. If there is error in CRC, then ALERT_n goes LOW for the period time interval and goes back HIGH.
If there is error in Command Address Parity Check, then ALERT_n goes LOW for relatively long period until
on going DRAM internal recovery transaction is complete. During Connectivity Test mode this pin functions
as an input.
Using this signal or not is dependent on the system. In case of not connected as Signal, ALERT_n Pin must
be connected to VDD on DIMM.
Device address for the SPD.
Reserved for Future Use. No on DIMM electrical connection is present.
NC
Rev. 1.1
No Connect: No on DIMM electrical connection is present.
VDD1
Supply
Power Supply: 1.2 V +/- 0.06 V
VSS
Supply
Ground
VTT2
Supply
Power Supply: 0.6 V
VPP
Supply
DRAM Activating Power Supply: 2.5V ( 2.375V min , 2.75V max)
VREFCA
Supply
Reference voltage for CA
VDDSPD
Supply
Power supply used to power the I2C bus on the SPD 2.5V ± 10%.
NOTE :
1. For PC4, VDD is 1.2 V. For PC4L VDD is TBD.
2. For PC4, VTT is 0.6 V. For PC4L VTT is TBD.
-8-
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
7. Function Block Diagram
D0
D2
D1
D3
Front
D5
D15
D14
D6
D7
D13
D12
Back
D11
D10
D9
D8
Address, Command and Control lines
NOTE :
1. Unless otherwise noted, resistor values are 15 ± 5%.
2. ZQ resistors are 240 ± 1%. For all other resistor values refer to the appropriate wiring diagram.
-9-
CS_n
Address
CK
CS_n
Address
CK
CS_n
CK
CK
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
Address
VSS
D4
D11
CKE
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
CS_n
VSS
ZQ
D15
CKE
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
Address
CKE
VSS
ZQ
D14
CKE
ZQ
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
ODT
VSS
ODT
ZQ
ODT
CK
CK
D1
CK
CKE
CKE
D0
CK
CS_n
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
CS_n
DQS3_t
DQS3_c
DQ [31:24]
DBI3_n/DM3_n
CS_n
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
D4
CS_n
DQS1_t
DQS1_c
DQ [15:8]
DBI1_n/DM1_n
CKE
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
ODT
DQS0_t
DQS0_c
DQ [7:0]
DBI0_n/DM0_n
D5
ODT
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
ODT
DQS2_t
DQS2_c
DQ [23:16]
DBI2_n/DM2_n
Address
CKE1
Address
ODT1
CKE0
Address
CS1_n
ODT0
Address
CS0_n
CKE
CK1_t,CK1_c
A[16:0],BA[1:0],
ACT_n,PARITY,BG[1:0]
ODT
CK0_t,CK0_c
A[16:0],BA[1:0],
ACT_n,PARITY,BG[1:0]
ODT
7.1 16GB, 2Gx64 Module (Populated as 2 ranks of x8 DDR4 SDRAMs)
D10
ZQ
VSS
ZQ
VSS
ZQ
VSS
ZQ
VSS
Rev. 1.1
datasheet
VDDSPD
SDA
NC
A0 A1 A2
CS_n
Address
CK
CS_n
Address
CK
CK
CK
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
CS_n
VSS
Address
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
ODT
CKE
VSS
Serial PD without Thermal sensor
SCL
NC
ODT
D9
CKE
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
CS_n
ZQ
VSS
Address
ZQ
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
D8
CKE
ZQ
VSS
ODT
ZQ
D12
CKE
CK
CK
D6
CK
CKE
CKE
D7
CK
CS_n
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
CS_n
DQS5_t
DQS5_c
DQ [47:40]
DBI5_n/DM5_n
CS_n
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
D3
CS_n
DQS7_t
DQS7_c
DQ [63:56]
DBI7_n/DM7_n
CKE
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
ODT
DQS6_t
DQS6_c
DQ [55:48]
DBI4_n/DM4_n
D2
ODT
DQS_t
DQS_c
DQ [7:0]
DBI_n/DM_n
ODT
DQS4_t
DQS4_c
DQ [39:32]
DBI4_n/DM4_n
Address
CKE1
Address
ODT1
CKE0
Address
CS1_n
ODT0
Address
CS0_n
CKE
CK1_t,CK1_c
A[16:0],BA[1:0],
ACT_n,PARITY,BG[1:0]
ODT
CK0_t,CK0_c
A[16:0],BA[1:0],
ACT_n,PARITY,BG[1:0]
DDR4 SDRAM
ODT
Unbuffered SODIMM
D13
ZQ
VSS
ZQ
VSS
ZQ
VSS
ZQ
VSS
Serial PD
VPP
D0-D15
VDD
D0-D15
VTT
SA0 SA1 SA2
VREFCA
D0-D15
VSS
D0-D15
NOTE :
1. Unless otherwise noted, resistor values are 15 ± 5%.
2. ZQ resistors are 240 ± 1%. For all other resistor values refer to the appropriate wiring diagram.
3. SDRAMs for ODD ranks (D8 to D15), which are placed on the back side of the module use the address mirroring for A4-A3, A6-A5, A8-A7, A13A11, BA1-BA0 and BG1-BG0. More detail can be found in the DDR4 SODIMM Common Section of the Design Specification.
- 10 -
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
7.2 16GB, 2Gx72 Module (Populated as 2 ranks of x8 DDR4 SDRAMs)
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
VSS
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
VSS
NOTE :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. Unless otherwise noted, resistor values are 15 ± 5%.
3. See the Net Structure diagrams for all resistors associated with the command, address and control bus.
4. ZQ resistors are 240 ± 1%. For all other resistor values refer to the appropriate wiring diagram.
- 11 -
A,BA,BG,ACT
PAR
CK
CKE
CS_n
CS_n
A,BA,BG,ACT
PAR
CK
ODT
CKE
CS_n
A,BA,BG,ACT
PAR
CK
CKE
ODT
CS_n
A,BA,BG,ACT
PAR
CK
ODT
CKE
CS_n
A,BA,BG,ACT
PAR
CK
CKE
ODT
CS_n
A,BA,BG,ACT
PAR
CK
ODT
CKE
CS_n
A,BA,BG,ACT
PAR
CK
CKE
CS_n
A,BA,BG,ACT
PAR
CK
CS_n
A,BA,BG,ACT
PAR
CK
A,BA,BG,ACT
PAR
CK
CS_n
CS_n
ZQ
ODT
CS_n
A,BA,BG,ACT
PAR
CK
A,BA,BG,ACT
PAR
CK
CS_n
CS_n
A,BA,BG,ACT
PAR
CK
CKE
CKE
ODT
D4
CKE
ZQ
VSS
ZQ
CS_n
DQS8_t
DQS8_c
CB[7:0]
DM8_n/DBI8_n
ZQ
D16
D13
A,BA,BG,ACT
PAR
CK
VSS
D7
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
ODT
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
D15
ZQ
VSS
CS_n
DQS7_t
DQS7_c
DQ [63:56]
DM7_n/DBI7_n
ZQ
D17
ZQ
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
A,BA,BG,ACT
PAR
CK
VSS
D6
D14
ZQ
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
A,BA,BG,ACT
PAR
CK
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
VSS
CS_n
DQS6_t
DQS6_c
DQ [55:48]
DM6_n/DBI6_n
ZQ
D12
ZQ
VSS
D8
D9
ZQ
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
A,BA,BG,ACT
PAR
CK
VSS
D5
ZQ
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
VSS
CKE
DQS5_t
DQS5_c
DQ [47:40]
DM5_n/DBI5_n
ODT
ZQ
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
VSS
D3
D11
ZQ
VSS
ODT
DQS4_t
DQS4_c
DQ [39:32]
DM4_n/DBI4_n
CKE
ZQ
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
VSS
D0
CKE
DQS3_t
DQS3_c
DQ [31:24]
DM3_n/DBI3_n
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
VSS
ODT
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
VSS
CKE
ZQ
ODT
DQS2_t
DQS2_c
DQ [23:16]
DM2_n/DBI2_n
D2
CKE
VSS
ODT
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
D10
ZQ
VSS
ODT
DQS1_t
DQS1_c
DQ [15:8]
DM1_n/DBI1_n
ZQ
CKE
VSS
D1
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
CKE
DQS_t
DQS_c
DQ [7:0]
DM_n/DBI_n
ODT
DQS0_t
DQS0_c
DQ [7:0]
DM0_n/DBI0_n
CS_n
CKE1
A,BA,BG,ACT
PAR
CK
CKE0
CKE
CS1_n
ODT1
ODT
ODT0
ODT
CK1_t,CK1_c
ODT
CK0_t,CK0_c
PARITY
A[16:0],BA[1:0],BG[1:0],ACT_n,
CS0_n
Rev. 1.1
datasheet
Unbuffered SODIMM
D2
D3
D4
DDR4 SDRAM
D5
D6
Front
D1
D0
D8
D7
D10
D9
D17
D16
D14
D15
Back
D11
D12
D13
Address, Command and Control lines
VDDSPD
Serial PD with Thermal sensor
SCL
EVENT_n
SDA
EVENT_n
SA0 SA1 SA2
Serial PD
VPP
D0-D17
VDD
D0-D17
VTT
SA0 SA1 SA2
- 12 -
VREFCA
D0-D17
VSS
D0-D17
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
8. Absolute Maximum Ratings
8.1 Absolute Maximum DC Ratings
[ Table 2 ] Absolute Maximum DC Ratings
Symbol
VDD
VDDQ
VPP
VIN, VOUT
TSTG
Parameter
Rating
Units
NOTE
Voltage on VDD pin relative to Vss
-0.3 ~ 1.5
V
1,3
Voltage on VDDQ pin relative to Vss
-0.3 ~ 1.5
V
1,3
Voltage on VPP pin relative to Vss
-0.3 ~ 3.0
V
4
Voltage on any pin except VREFCA to Vss
-0.3 ~ 1.5
V
1,3
Storage Temperature
-55 to +100
°C
1,2
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA
may be equal to or less than 300 mV
4. VPP must be equal or greater than VDD/VDDQ at all times.
9. AC & DC Operating Conditions
9.1 Recommended DC Operating Conditions
[ Table 3 ] Recommended DC Operating Conditions
Symbol
Parameter
Rating
Min.
Typ.
Max.
Unit
NOTE
VDD
Supply Voltage
1.14
1.2
1.26
V
1,2,3
VDDQ
Supply Voltage for Output
1.14
1.2
1.26
V
1,2,3
VPP
Peak-to-Peak Voltage
2.375
2.5
2.75
V
3
NOTE:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. DC bandwidth is limited to 20MHz.
- 13 -
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
10. AC & DC Input Measurement Levels
10.1 AC & DC Logic Input Levels for Single-Ended Signals
[ Table 4 ] Single-ended AC & DC Input Levels for Command and Address
Symbol
Parameter
VIH.CA(DC75)
DC input logic high
DDR4-1600/1866/2133/2400
Unit
Min.
Max.
VREFCA+ 0.075
VDD
V
V
NOTE
VIL.CA(DC75)
DC input logic low
VSS
VREFCA-0.075
VIH.CA(AC100)
AC input logic high
VREF + 0.1
Note 2
V
1
VIL.CA(AC100)
AC input logic low
Note 2
VREF - 0.1
V
1
VREFCA(DC)
Reference Voltage for ADD, CMD inputs
0.49*VDD
0.51*VDD
V
2,3
NOTE :
1. See “Overshoot and Undershoot Specifications” on section.
2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV)
3. For reference : approx. VDD/2 ± 12mV
10.2 AC and DC Input Measurement Levels : VREF Tolerances.
The DC-tolerance limits and ac-noise limits for the reference voltages VREFCA is illustrated in Figure 1. It shows a valid reference voltage VREF(t) as a
function of time. (VREF stands for VREFCA).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table X.
Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD.
voltage
VDD
VSS
time
Figure 1. Illustration of VREF(DC) tolerance and VREF AC-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF.
"VREF" shall be understood as VREF(DC), as defined in Figure 1.
This clarifies, that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF AC-noise. Timing
and voltage effects due to AC-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
- 14 -
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
10.3 AC and DC Logic Input Levels for Differential Signals
10.3.1 Differential Signals Definition
tDVAC
VIH.DIFF.AC.MIN
Differential Input Voltage (CK-CK)
(CK_t - CK_c)
VIH.DIFF.MIN
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Figure 2. Definition of differential ac-swing and “time above ac-level” tDVAC
NOTE :
1. Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.
2. Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.
10.3.2 Differential Swing Requirements for Clock (CK_t - CK_c)
[ Table 5 ] Differential AC and DC Input Levels
Symbol
Parameter
VIHdiff
DDR4 -1600/1866/2133
DDR4 -2400
unit
NOTE
NOTE 3
V
1
NOTE 3
TBD
V
1
NOTE 3
2 x (VIH(AC) - VREF)
NOTE 3
V
2
2 x (VIL(AC) - VREF)
NOTE 3
2 x (VIL(AC) - VREF)
V
2
min
max
min
max
differential input high
+0.150
NOTE 3
TBD
VILdiff
differential input low
NOTE 3
-0.150
VIHdiff(AC)
differential input high ac
2 x (VIH(AC) - VREF)
VILdiff(AC)
differential input low ac
NOTE 3
NOTE:
1. Used to define a differential signal slew-rate.
2. for CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD and VREFCA;
3. These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals
as well as the limitations for overshoot and undershoot.
[ Table 6 ] Allowed Time Before Ringback (tDVAC) for CK_t - CK_c
Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(AC)| = 200mV
min
max
120
-
4.0
115
-
3.0
110
-
> 4.0
2.0
105
-
1.8
100
-
1.6
95
-
1.4
90
-
1.2
85
-
1.0
80
-
< 1.0
80
-
- 15 -
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
10.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended signals.
CK_t and CK_c have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH.CA(AC) / VIL.CA(AC) ) for ADD/CMD
signals) in every half-cycle.
Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g., if Different value than VIH.CA(AC100)/VIL.CA(AC100) is used
for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK_t and CK_c
VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2
CK
VSEL max
VSEL
VSS or VSSQ
time
Figure 3. Single-ended requirement for differential signals.
Note that, while ADD/CMD signal requirements are with respect to VrefCA, the single-ended components of differential signals have a requirement with
respect to VDD / 2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For singleended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common
mode characteristics of these signals.
[ Table 7 ] Single-ended Levels for CK_t, CK_c
Symbol
Parameter
VSEH
VSEL
DDR4-1600/1866/2133
DDR4-2400
Unit
NOTE
NOTE3
V
1, 2
TBD
V
1, 2
Min
Max
Min
Max
Single-ended high-level for CK_t , CK_c
(VDD/2)+0.100
NOTE3
TBD
Single-ended low-level for CK_t , CK_c
NOTE3
(VDD/2)-0.100
NOTE3
NOTE :
1. For CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD;
2. VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA;
3. These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits (VIH.CA(DC) max, VIL.CA(DC)min) for single-ended
signals as well as the limitations for overshoot and undershoot.
- 16 -
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
10.4 Slew Rate Definitions
10.4.1 Slew Rate Definitions for Differential Input Signals ( CK )
[ Table 8 ] Differential Input Slew Rate Definition
Description
from
Differential input slew rate for rising edge(CK_t - CK_c)
V
Differential input slew rate for falling edge(CK_t - CK_c)
V
ILdiffmax
IHdiffmin
Defined by
to
V
IHdiffmin
VIHdiffmin - VILdiffmax DeltaTRdiff
V
V
V
 IHdiffmin - ILdiffmax DeltaTFdiff
ILdiffmax
NOTE: The differential signal (i,e.,CK_t - CK_c) must be linear between these thresholds.
Differential Input Voltage(i,e, CK_t - CK_c)
Delta TRdiff
V
IHdiffmin
0
V
Delta TFdiff
Figure 4. Differential Input Slew Rate Definition for CK_t, CK_c
- 17 -
ILdiffmax
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
10.5 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each cross point voltage of differential input signals
(CK_t, CK_c) must meet the requirements in Table. The differential input cross point voltage VIX is measured from the actual cross point of true and
complement signals to the midlevel between of VDD and VSS.
VDD
CK_t
Vix
VDD/2
Vix
CK_c
VSEL
VSEH
VSS
Figure 5. Vix Definition (CK)
[ Table 9 ] Cross Point Voltage for Differential Input Signals (CK)
DDR4-1600/1866/2133
Symbol
Parameter
-
Area of VSEH, VSEL
VSEL =< VDD/2 145mV
VDD/2 - 145mV =<
VSEL =< VDD/2 100mV
VDD/2 + 100mV
=< VSEH =< VDD/
2 + 145mV
VDD/2 + 145mV
=< VSEH
VlX(CK)
Differential Input Cross Point Voltage relative to
VDD/2 for CK_t, CK_c
-120mV
-(VDD/2 - VSEL) +
25mV
(VSEH - VDD/2) 25mV
120mV
Symbol
Parameter
-
Area of VSEH, VSEL
TBD
TBD
TBD
TBD
VlX(CK)
Differential Input Cross Point Voltage relative to
VDD/2 for CK_t, CK_c
TBD
TBD
TBD
TBD
min
max
DDR4-2400
min
- 18 -
max
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
10.6 Single-ended AC & DC Output Levels
[ Table 10 ] Single-ended AC & DC Output Levels
Symbol
Parameter
DDR4-1600/1866/2133/2400
Units
VOH(DC)
DC output high measurement level (for IV curve linearity)
1.1 x VDDQ
V
NOTE
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOL(DC)
DC output low measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOH(AC)
AC output high measurement level (for output SR)
(0.7 + 0.15) x VDDQ
V
1
VOL(AC)
AC output low measurement level (for output SR)
(0.7 - 0.15) x VDDQ
V
1
NOTE :
1. The swing of ± 0.15 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test
load of 50Ω to VTT = VDDQ.
10.7 Differential AC & DC Output Levels
[ Table 11 ] Differential AC & DC Output Levels
DDR4-1600/1866/2133/2400
Units
NOTE
VOHdiff(AC)
Symbol
Parameter
AC differential output high measurement level (for output SR)
+0.3 x VDDQ
V
1
VOLdiff(AC)
AC differential output low measurement level (for output SR)
-0.3 x VDDQ
V
1
NOTE :
1. The swing of ± 0.3 × VDDQ is based on approximately 50% of the static differential output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test load
of 50Ω to VTT = VDDQ at each of the differential outputs.
10.8 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for
single ended signals as shown in Table 12 and Figure 6.
[ Table 12 ] Single-ended Output Slew Rate Definition
Measured
Description
Defined by
From
To
Single ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC)-VOL(AC)] / Delta TRse
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC)-VOL(AC)] / Delta TFse
NOTE :
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
VOH(AC)
VTT
VOL(AC)
delta TFse
delta TRse
Figure 6. Single-ended Output Slew Rate Definition
- 19 -
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
[ Table 13 ] Single-ended Output Slew Rate
Parameter
Single ended output slew rate
Symbol
SRQse
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Min
Max
Min
Max
Min
Max
Min
Max
4
9
4
9
4
9
4
9
Units
V/ns
Description: SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
NOTE :
1. In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane.
-Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the
same byte lane are static (i.e. they stay at either high or low).
-Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the
same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the
regular maximum limit of 9 V/ns applies
10.9 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and
VOHdiff(AC) for differential signals as shown in Table 14 and Figure 7.
[ Table 14 ] Differential Output Slew Rate Definition
Measured
Description
Defined by
From
To
Differential output slew rate for rising edge
VOLdiff(AC)
VOHdiff(AC)
[VOHdiff(AC)-VOLdiff(AC)] / Delta TRdiff
Differential output slew rate for falling edge
VOHdiff(AC)
VOLdiff(AC)
[VOHdiff(AC)-VOLdiff(AC)] / Delta TFdiff
NOTE :
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
VOHdiff(AC)
VTT
VOLdiff(AC)
delta TFdiff
delta TRdiff
Figure 7. Differential Output Slew Rate Definition
[ Table 15 ] Differential Output Slew Rate
Parameter
Differential output slew rate
Symbol
SRQdiff
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Min
Max
Min
Max
Min
Max
Min
Max
8
18
8
18
8
18
8
18
Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
diff: Differential Signals
For Ron = RZQ/7 setting
- 20 -
Units
V/ns
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
10.10 Single-ended AC & DC Output Levels of Connectivity Test Mode
Following output parameters will be applied for DDR4 SDRAM Output Signal during Connectivity Test Mode.
[ Table 16 ] Single-ended AC & DC Output Levels of Connectivity Test Mode
DDR4-1600/1866/2133/2400
Unit
VOH(DC)
Symbol
DC output high measurement level (for IV curve linearity)
Parameter
1.1 x VDDQ
V
Notes
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOL(DC)
DC output low measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOB(DC)
DC output below measurement level (for IV curve linearity)
0.2 x VDDQ
V
VOH(AC)
AC output high measurement level (for output SR)
VTT + (0.1 x VDDQ)
V
1
VOL(AC)
AC output below measurement level (for output SR)
VTT - (0.1 x VDDQ)
V
1
NOTE :
1. The effective test load is 50Ω terminated by VTT = 0.5 * VDDQ.
VOH(AC)
VTT
VOL(AC)
TR_output_CT
TR_output_CT
Figure 8. Output Slew Rate Definition of Connectivity Test Mode
[ Table 17 ] Single-ended Output Slew Rate of Connectivity Test Mode
Parameter
DDR4-1600/1866/2133/2400
Symbol
Min
Max
Unit
Output signal Falling time
TF_output_CT
-
10
ns/V
Output signal Rising time
TR_output_CT
-
10
ns/V
10.11 Test Load for Connectivity Test Mode Timing
The reference load for ODT timings is defined in Figure 7.
VDDQ
CT_INPUTS
DQ, DM
DQSL_t , DQSL_c
DQSU_t , DQSU_c
DQS_t , DQS_c
DUT
Rterm = 50 ohm
VSSQ
Timing Reference Points
Figure 9. Connectivity Test Mode Timing Reference Load
- 21 -
0.5*VDDQ
Notes
Unbuffered SODIMM
datasheet
Rev. 1.1
DDR4 SDRAM
11. DIMM IDD Specification Definition
[ Table 18 ] Basic IDD, IPP and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current (AL=0)
IDD0
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High
between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling; Data IO: VDDQ; DM_n:
stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2;
ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD0A
IPP0
Operating One Bank Active-Precharge Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD0
Operating One Bank Active-Precharge IPP Current
Same condition with IDD0
Operating One Bank Active-Read-Precharge Current (AL=0)
IDD1
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High
between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs, Data IO: partially toggling; DM_n: stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2; ODT
Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD1A
IPP1
Operating One Bank Active-Read-Precharge Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD1
Operating One Bank Active-Read-Precharge IPP Current
Same condition with IDD1
Precharge Standby Current (AL=0)
IDD2N
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command,
Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet
for detail pattern
IDD2NA
IPP2N
Precharge Standby Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD2N
Precharge Standby IPP Current
Same condition with IDD2N
Precharge Standby ODT Current
IDD2NT
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command,
Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VSSQ; DM_n: stable at 1; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: toggling according ; Pattern Details: Refer to Component
Datasheet for detail pattern
IDDQ2NT Precharge Standby ODT IDDQ Current
(Optional) Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
IDD2NL
IDD2NG
IDD2ND
IDD2N_par
IDD2P
Precharge Standby Current with CAL enabled
Same definition like for IDD2N, CAL enabled3
Precharge Standby Current with Gear Down mode enabled
Same definition like for IDD2N, Gear Down mode enabled3,5
Precharge Standby Current with DLL disabled
Same definition like for IDD2N, DLL disabled3
Precharge Standby Current with CA parity enabled
Same definition like for IDD2N, CA parity enabled3
Precharge Power-Down Current CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL:
0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0
IPP2P
Precharge Power-Down IPP Current
Same condition with IDD2P
IDD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command,
Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0
- 22 -
Unbuffered SODIMM
datasheet
Rev. 1.1
DDR4 SDRAM
Symbol
Description
IDD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command,
Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks
open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details:Refer to Component Datasheet
for detail pattern
IDD3NA
Active Standby Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD3N
IPP3N
Active Standby IPP Current
Same condition with IDD3N
IDD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: sRefer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command,
Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks open;
Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0
IPP3P
Active Power-Down IPP Current
Same condition with IDD3P
IDD4R
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 82; AL: 0; CS_n: High between RD;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different
data between one burst and the next one according ; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling through
banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to
Component Datasheet for detail pattern
IDD4RA
Operating Burst Read Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD4R
IDD4RB
Operating Burst Read Current with Read DBI
Read DBI enabled3, Other conditions: see IDD4R
IPP4R
Operating Burst Read IPP Current
Same condition with IDD4R
IDDQ4R
(Optional)
Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
IDDQ4RB
(Optional)
Operating Burst Read IDDQ Current with Read DBI
Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current
IDD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High between WR;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different
data between one burst and the next one ; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through banks:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at HIGH; Pattern Details: Refer to Component
Datasheet for detail pattern
IDD4WA
Operating Burst Write Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD4W
IDD4WB
Operating Burst Write Current with Write DBI
Write DBI enabled3, Other conditions: see IDD4W
IDD4WC
Operating Burst Write Current with Write CRC
Write CRC enabled3, Other conditions: see IDD4W
IDD4W_par
Operating Burst Write Current with CA Parity
CA Parity enabled3, Other conditions: see IDD4W
IPP4W
Operating Burst Write IPP Current
Same condition with IDD4W
IDD5B
Burst Refresh Current (1X REF)
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High between
REF; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at 1; Bank
Activity: REF command every nRFC ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details:
Refer to Component Datasheet for detail pattern
IPP5B
Burst Refresh Write IPP Current (1X REF)
Same condition with IDD5B
IDD5F2
Burst Refresh Current (2X REF)
tRFC=tRFC_x2, Other conditions: see IDD5B
IPP5F2
Burst Refresh Write IPP Current (2X REF)
Same condition with IDD5F2
- 23 -
Unbuffered SODIMM
datasheet
Symbol
Rev. 1.1
DDR4 SDRAM
Description
IDD5F4
Burst Refresh Current (4X REF)
tRFC=tRFC_x4, Other conditions: see IDD5B
IPP5F4
Burst Refresh Write IPP Current (4X REF)
Same condition with IDD5F4
IDD6N
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: Refer
to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO:
High; DM_n: stable at 1; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MIDLEVEL
IPP6N
Self Refresh IPP Current: Normal Temperature Range
Same condition with IDD6N
IDD6E
Self-Refresh Current: Extended Temperature Range)
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended4; CKE: Low; External clock: Off; CK_t and CK_c: LOW; CL:
Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n, Command, Address, Bank Group Address, Bank Address, Data
IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode
Registers2; ODT Signal: MID-LEVEL
IPP6E
Self Refresh IPP Current: Extended Temperature Range
Same condition with IDD6E
IDD6R
Self-Refresh Current: Reduced Temperature Range
TCASE: 0 - 45°C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: Refer
to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO:
High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode
Registers2; ODT Signal: MID-LEVEL
IPP6R
Self Refresh IPP Current: Reduced Temperature Range
Same condition with IDD6R
IDD6A
Auto Self-Refresh Current
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: Refer to
Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO:
High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
MID-LEVEL
IPP6A
Auto Self-Refresh IPP Current
Same condition with IDD6A
IDD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL:
CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data
IO: read data bursts with different data between one burst and the next one ; DM_n: stable at 1; Bank Activity: two times interleaved cycling
through banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern
Details: Refer to Component Datasheet for detail pattern
IPP7
Operating Bank Interleave Read IPP Current
Same condition with IDD7
IDD8
Maximum Power Down Current TBD
IPP8
Maximum Power Down IPP Current Same condition with IDD8
NOTE :
1. Burst Length: BL8 fixed by MRS: set MR0 [A1:0=00].
2. Output Buffer Enable
- set MR1 [A12 = 0] : Qoff = Output buffer enabled
- set MR1 [A2:1 = 00] : Output Driver Impedance Control = RZQ/7
RTT_Nom enable
- set MR1 [A10:8 = 011] : RTT_NOM = RZQ/6
RTT_WR enable
- set MR2 [A10:9 = 01] : RTT_WR = RZQ/2
RTT_PARK disable
- set MR5 [A8:6 = 000]
3. CAL enabled : set MR4 [A8:6 = 001] : 1600MT/s
010] : 1866MT/s, 2133MT/s
011] : 2400MT/s
Gear Down mode enabled :set MR3 [A3 = 1] : 1/4 Rate
DLL disabled : set MR1 [A0 = 0]
CA parity enabled :set MR5 [A2:0 = 001] : 1600MT/s,1866MT/s, 2133MT/s
010] : 2400MT/s
Read DBI enabled : set MR5 [A12 = 1]
Write DBI enabled : set :MR5 [A11 = 1]
4. Low Power Array Self Refresh (LP ASR) : set MR2 [A7:6 = 00] : Normal
01] : Reduced Temperature range
10] : Extended Temperature range
11] : Auto Self Refresh
5. IDD2NG should be measured after sync pules(NOP) input.
- 24 -
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
12. IDD SPEC Table
IDD and IPP values are for full operating range of voltage and temperature unless otherwise noted. IDD and IPP values are for full operating range of voltage and temperature unless otherwise noted.
[ Table 19 ] IDD and IDDQ Specification
M471A2K43BB1-CPB/RC :
16GB(2Gx64) Module
Symbol
DDR4-2133
DDR4-2400
15-15-15
17-17-17
1.2V
Unit
1.2V
IDD Max.
IPP Max.
IDD Max.
IPP Max.
IDD0
456
56
480
56
mA
IDD0A
472
56
496
56
mA
IDD1
576
56
608
56
mA
IDD1A
592
56
632
56
mA
IDD2N
352
48
368
48
mA
IDD2NA
376
48
392
48
mA
IDD2NT
376
48
392
48
mA
IDD2NL
296
48
320
48
mA
IDD2NG
352
48
368
48
mA
IDD2ND
336
48
352
48
mA
IDD2N_par
360
48
376
48
mA
IDD2P
256
48
256
48
mA
IDD2Q
336
48
352
48
mA
IDD3N
464
48
472
48
mA
IDD3NA
480
48
488
48
mA
IDD3P
336
48
352
48
mA
IDD4R
1000
48
1088
48
mA
IDD4RA
1032
48
1128
48
mA
IDD4RB
1016
48
1112
48
mA
IDD4W
848
48
904
48
mA
IDD4WA
880
48
944
48
mA
IDD4WB
928
48
904
48
mA
IDD4WC
768
48
824
48
mA
IDD4W_par
912
48
976
48
mA
IDD5B
1928
168
1960
168
mA
IDD5F2
1408
144
1424
144
mA
IDD5F4
1200
136
1224
136
mA
IDD6N
368
64
368
64
mA
IDD6E
544
80
544
80
mA
IDD6R
256
56
256
56
mA
IDD6A
352
64
352
64
mA
IDD7
1536
88
1568
92
mA
IDD8
176
48
176
48
mA
NOTE :
1. DIMM IDD SPEC is based on the condition that de-actived rank(IDLE) is IDD2N. Please refer to Table 20.
2. IDD current measure method and detail patterns are described on DDR4 component datasheet.
3. VDD and VDDQ are merged on module PCB.
4. DIMM IDD SPEC is measured with Qoff condition. (IDDQ values are not considered)
- 25 -
NOTE
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
M474A2K43BB1-CPB/RC :
16GB(2Gx72) Module
Symbol
DDR4-2133
DDR4-2400
15-15-15
17-17-17
1.2V
Unit
1.2V
IDD Max.
IPP Max.
IDD Max.
IPP Max.
IDD0
513
63
540
63
mA
IDD0A
531
63
558
63
mA
IDD1
648
63
684
63
mA
IDD1A
666
63
711
63
mA
IDD2N
396
54
414
54
mA
IDD2NA
423
54
441
54
mA
IDD2NT
423
54
441
54
mA
IDD2NL
333
54
360
54
mA
IDD2NG
396
54
414
54
mA
IDD2ND
378
54
396
54
mA
IDD2N_par
405
54
423
54
mA
IDD2P
288
54
288
54
mA
IDD2Q
378
54
396
54
mA
IDD3N
522
54
531
54
mA
IDD3NA
540
54
549
54
mA
IDD3P
378
54
396
54
mA
IDD4R
1125
54
1224
54
mA
IDD4RA
1161
54
1269
54
mA
IDD4RB
1143
54
1251
54
mA
IDD4W
954
54
1017
54
mA
IDD4WA
990
54
1062
54
mA
IDD4WB
1044
54
1017
54
mA
IDD4WC
864
54
927
54
mA
IDD4W_par
1026
54
1098
54
mA
IDD5B
2169
189
2205
189
mA
IDD5F2
1584
162
1602
162
mA
IDD5F4
1350
153
1377
153
mA
IDD6N
414
72
414
72
mA
IDD6E
612
90
612
90
mA
IDD6R
288
63
288
63
mA
IDD6A
396
72
396
72
mA
IDD7
1728
99
1764
104
mA
IDD8
198
54
198
54
mA
NOTE :
1. DIMM IDD SPEC is based on the condition that de-actived rank(IDLE) is IDD2N. Please refer to Table 20.
2. IDD current measure method and detail patterns are described on DDR4 component datasheet.
3. VDD and VDDQ are merged on module PCB.
4. DIMM IDD SPEC is measured with Qoff condition. (IDDQ values are not considered)
- 26 -
NOTE
datasheet
Unbuffered SODIMM
[ Table 20 ] DIMM Rank Status
SEC DIMM
Operating Rank
The other Rank
IDD0
IDD0
IDD2N
IDD2N
IDD1
IDD1
IDD2P
IDD2P
IDD2P
IDD2N
IDD2N
IDD2N
IDD2Q
IDD2Q
IDD2Q
IDD3P
IDD3P
IDD3P
IDD3N
IDD3N
IDD3N
IDD4R
IDD4R
IDD2N
IDD4W
IDD4W
IDD2N
IDD5B
IDD5B
IDD2N
IDD6
IDD6
IDD6
IDD7
IDD7
IDD2N
IDD8
IDD8
IDD8
- 27 -
Rev. 1.1
DDR4 SDRAM
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
13. Input/Output Capacitance
[ Table 21 ] Silicon Pad I/O Capacitance
Symbol
Parameter
CIO
DDR4-1600/1866/2133
DDR4-2400
Unit
NOTE
1.15
pF
1,2,3
-0.1
0.1
pF
1,2,3,11
0.05
-
0.05
pF
1,2,3,5
0.8
0.2
0.7
pF
1,3
min
max
min
max
Input/output capacitance
0.55
1.4
0.55
CDIO
Input/output capacitance delta
-0.1
0.1
CDDQS
Input/output capacitance delta DQS_t and DQS_c
-
CCK
Input capacitance, CK_t and CK_c
0.2
CDCK
Input capacitance delta CK_t and CK_c
-
0.05
-
0.05
pF
1,3,4
CI
Input capacitance(CTRL, ADD, CMD pins only)
0.2
0.8
0.2
0.7
pF
1,3,6
CDI_ CTRL
Input capacitance delta(All CTRL pins only)
-0.1
0.1
-0.1
0.1
pF
1,3,7,8
CDI_ ADD_CMD
Input capacitance delta(All ADD/CMD pins only)
-0.1
0.1
-0.1
0.1
pF
1,2,9,10
CALERT
Input/output capacitance of ALERT
0.5
1.5
0.5
1.5
pF
1,3
CZQ
Input/output capacitance of ZQ
0.5
2.3
0.5
2.3
pF
1,3,12
CTEN
Input capacitance of TEN
0.2
2.3
0.2
2.3
pF
1,3,13
NOTE:
1. This parameter is not subject to production test. It is verified by design and characterization. The silicon only capacitance is validated by de-embedding the package L & C
parasitic. The capacitance is measured with VDD, VDDQ, VSS, VSSQ applied with all other signal pins floating. Measurement procedure tbd.
2. DQ, DM_n, DQS_T, DQS_c, TDQS_T, TDQS_C. Although the DM, TDQS_T and TDQS_C pins have different functions, the loading matches DQ and DQS
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value CK_T-CK_C
5. Absolute value of CIO(DQS_T)-CIO(DQS_c)
6. CI applies to ODT, CS_n, CKE, A0-A17, BA0-BA1, BG0-BG1, RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR.
7. CDI CTRL applies to ODT, CS_n and CKE
8. CDI_CTRL = CI(CTRL)-0.5*(CI(CLK_T)+CI(CLK_C))
9. CDI_ADD_ CMD applies to, A0-A17, BA0-BA1, BG0-BG1,RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR.
10. CDI_ADD_CMD = CI(ADD_CMD)-0.5*(CI(CLK_T)+CI(CLK_C))
11. CDIO = CIO(DQ,DM)-0.5*(CIO(DQS_T)+CIO(DQS_c))
12. Maximum external load capacitance on ZQ pin: tbd pF.
13.TEN pin may be DRAM internally pulled low through a weak pull-down resistor to VSS. In this case CTEN might not be valid and system shall verify TEN signal with Vendor
specific information.
- 28 -
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
14. Electrical Characterisitics and AC Timing
14.1 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
[ Table 22 ] DDR4-1600 Speed Bins and Operations
Speed Bin
DDR4-1600
CL-nRCD-nRP
11-11-11
Unit
NOTE
10
Parameter
Symbol
min
max
Internal read command to first data
tAA
13.75
18.00
ns
Internal read command to first data with read DBI enabled
tAA_DBI
tAA(min) + 2nCK
tAA(max) +2nCK
ns
10
ACT to internal read or write delay time
tRCD
13.75
-
ns
10
PRE command period
tRP
13.75
-
ns
10
ACT to PRE command period
tRAS
35
9 x tREFI
ns
10
tRC
48.75
-
ns
10
ns
1,2,3,4,9
ns
1,2,3,4,9
ns
1,2,3,4
ns
1,2,3,4
ns
1,2,3
ACT to ACT or REF command period
Normal
CWL = 9
CWL = 9,11
Read DBI
CL = 9
CL = 11
tCK(AVG)
CL = 10
CL = 12
tCK(AVG)
Reserved
CL = 10
CL = 12
tCK(AVG)
CL = 11
CL = 13
tCK(AVG)
1.25
CL = 12
CL = 14
tCK(AVG)
1.25
1.5
1.6
Reserved
<1.5
<1.5
Supported CL Settings
10,11,12
nCK
Supported CL Settings with read DBI
12,13,14
nCK
Supported CWL Settings
9,11
nCK
[ Table 23 ] DDR4-1866 Speed Bins and Operations
Speed Bin
DDR4-1866
CL-nRCD-nRP
Parameter
13-13-13
Symbol
min
Unit
NOTE
max
Internal read command to first data
tAA
13.92
18.00
ns
10
Internal read command to first data with read DBI enabled
tAA_DBI
tAA(min) + 2nCK
tAA(max) +2nCK
ns
10
ACT to internal read or write delay time
tRCD
13.92
-
ns
10
PRE command period
tRP
13.92
-
ns
10
ACT to PRE command period
tRAS
34
9 x tREFI
ns
10
ACT to ACT or REF command period
tRC
47.92
-
ns
10
ns
1,2,3,4,9
CWL = 9
CWL = 9,11
CWL = 10,12
Normal
Read DBI
CL = 9
CL = 11
tCK(AVG)
CL = 10
CL = 12
tCK(AVG)
CL = 10
CL = 12
tCK(AVG)
Reserved
1.5
1.6
Reserved
ns
1,2,3,4,9
ns
4
CL = 11
CL = 13
tCK(AVG)
1.25
<1.5
ns
1,2,3,4,6
CL = 12
CL = 14
tCK(AVG)
1.25
<1.5
ns
1,2,3,6
CL = 12
CL = 14
tCK(AVG)
ns
1,2,3,4
CL = 13
CL = 15
tCK(AVG)
1.071
<1.25
ns
1,2,3,4
CL = 14
CL = 16
tCK(AVG)
1.071
<1.25
ns
1,2,3
Reserved
Supported CL Settings
10,11,12,13,14
Supported CL Settings with read DBI
12,13,14,15,16
nCK
Supported CWL Settings
9,10,11,12
nCK
- 29 -
nCK
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
[ Table 24 ] DDR4-2133 Speed Bins and Operations
Speed Bin
DDR4-2133
CL-nRCD-nRP
15-15-15
Parameter
Symbol
Internal read command to first data
tAA
Internal read command to first data with read DBI
enabled
tAA_DBI
ACT to internal read or write delay time
tRCD
PRE command period
tRP
ACT to PRE command period
tRAS
ACT to ACT or REF command period
tRC
Normal
CWL = 9
CWL = 9,11
CWL = 10,12
CWL = 11,14
Unit
NOTE
18.00
ns
10
tAA(max) + 3nCK
ns
10
-
ns
10
-
ns
10
9 x tREFI
ns
10
-
ns
10
ns
1,2,3,4,9
ns
1,2,3,4,9
min
max
14.06
(13.75)5
tAA(min) + 3nCK
14.06
(13.75)5
14.06
(13.75)5
33
47.06
(46.75)5
Read DBI
CL = 9
CL = 11
tCK(AVG)
CL = 10
CL = 12
tCK(AVG)
Reserved
1.5
1.6
CL = 11
CL = 13
tCK(AVG)
1.25
<1.5
ns
1,2,3,4,7
CL = 12
CL = 14
tCK(AVG)
1.25
<1.5
ns
1,2,3,7
CL = 13
CL = 15
tCK(AVG)
1.071
<1.25
ns
1,2,3,4,7
CL = 14
CL = 16
tCK(AVG)
1.071
<1.25
ns
1,2,3,7
CL = 14
CL = 17
tCK(AVG)
CL = 15
CL = 18
tCK(AVG)
0.938
Reserved
CL = 16
CL = 19
tCK(AVG)
0.938
<1.071
<1.071
ns
1,2,3,4
ns
1,2,3,4
ns
1,2,3
Supported CL Settings
10,11.12,13,14,15,16
nCK
Supported CL Settings with read DBI
12,13,14,15,16,18,19
nCK
Supported CWL Settings
9,10,11,12,14
nCK
- 30 -
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
[ Table 25 ] DDR4-2400 Speed Bins and Operations
Speed Bin
DDR4-2400
CL-nRCD-nRP
17-17-17
Parameter
Symbol
Internal read command to first data
tAA
Internal read command to first data with read DBI
enabled
tAA_DBI
ACT to internal read or write delay time
tRCD
PRE command period
tRP
ACT to PRE command period
tRAS
ACT to ACT or REF command period
tRC
Normal
CWL = 9
CWL = 9,11
CWL = 10,12
CWL = 11,14
CWL = 12,16
Unit
NOTE
18.00
ns
10
tAA(max) + 3nCK
ns
10
-
ns
10
-
ns
10
9 x tREFI
ns
10
-
ns
10
ns
1,2,3,4,9
ns
1,2,3,4,9
min
max
14.16
(13.75)5
tAA(min) + 3nCK
14.16
(13.75)5
14.16
(13.75)5
32
46.16
(45.75)5
Read DBI
CL = 9
CL = 11
tCK(AVG)
CL = 10
CL = 12
tCK(AVG)
Reserved
1.5
CL = 10
CL = 12
tCK(AVG)
CL = 11
CL = 13
tCK(AVG)
1.25
CL = 12
CL = 14
tCK(AVG)
1.25
CL = 12
CL = 14
tCK(AVG)
CL = 13
CL = 15
tCK(AVG)
1.071
CL = 14
CL = 16
tCK(AVG)
1.071
CL = 14
CL = 17
tCK(AVG)
CL = 15
CL = 18
tCK(AVG)
0.938
CL = 16
CL = 19
tCK(AVG)
0.938
CL = 15
CL = 18
tCK(AVG)
1.6
Reserved
ns
4
<1.5
ns
1,2,3,4,8
<1.5
ns
1,2,3,8
ns
4
<1.25
ns
1,2,3,4,8
<1.25
ns
1,2,3,8
Reserved
Reserved
<1.071
<1.071
Reserved
CL = 16
CL = 19
tCK(AVG)
CL = 17
CL = 20
tCK(AVG)
0.833
Reserved
<0.938
CL = 18
CL = 21
tCK(AVG)
0.833
<0.938
ns
4
ns
1,2,3,4,8
ns
1,2,3,8
ns
1,2,3,4
ns
1,2,3,4
ns
1,2,3
Supported CL Settings
10,11,12,13,14,15,16,17,18
nCK
Supported CL Settings with read DBI
12,13,14,15,16,18,19,20,21
nCK
Supported CWL Settings
9,10,11,12,14,16
nCK
- 31 -
Unbuffered SODIMM
datasheet
Rev. 1.1
DDR4 SDRAM
14.2 Speed Bin Table Note
Absolute Specification
- VDDQ = VDD = 1.20V +/- 0.06 V
- VPP = 2.5V +0.25/-0.125 V
- The values defined with above-mentioned table are DLL ON case.
- DDR4-1600, 1866, 2133 and 2400 Speed Bin Tables are valid only when Geardown Mode is disabled.
1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making a selection of tCK(avg), both need to be fulfilled: Requirements from
CL setting as well as requirements from CWL setting.
2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be
guaranteed. An application should use the next smaller JEDEC standard tCK(avg) value (1.5, 1.25, 1.071, 0.938 or 0.833 ns) when calculating CL [nCK] = tAA [ns] / tCK(avg)
[ns], rounding up to the next ‘Supported CL’, where tAA = 12.5ns and tCK(avg) = 1.3 ns should only be used for CL = 10 calculation.
3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg) down to the next valid speed bin (i.e. 1.5ns or 1.25ns or 1.071 ns or
0.938 ns or 0.833 ns). This result is tCK(avg).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier's data sheet and/or the DIMM SPD
information if and how this setting is supported.
6. Any DDR4-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
7. Any DDR4-2133 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
8. Any DDR4-2400 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
9. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.
10. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the Speed Bin Tables.
- 32 -
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
15. Timing Parameters by Speed Grade
[ Table 26 ] Timing Parameters by Speed Bin for DDR4-1600 to DDR4-2400
Speed
Parameter
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Units
NOTE
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tCK
(DLL_OFF)
8
20
8
20
8
20
8
20
Average Clock Period
tCK(avg)
1.25
<1.5
1.071
<1.25
0.938
<1.071
0.833
<0.938
ns
Average high pulse width
tCH(avg)
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tCK(avg)
Average low pulse width
tCL(avg)
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tCK(avg)
Absolute Clock Period
tCK(abs)
tCK(avg)min
+
tJIT(per)min_
to t
tCK(avg)m ax
+ tJIT(per)m
ax_tot
tCK(avg)min
+
tJIT(per)min_
to t
tCK(avg)m ax
+ tJIT(per)m
ax_tot
tCK(avg)min
+
tJIT(per)min_
to t
tCK(avg)m
ax +
tJIT(per)m
ax_tot
tCK(avg)min
+
tJIT(per)min
_to t
tCK(avg)m
ax +
tJIT(per)m
ax_tot
tCK(avg)
Absolute clock HIGH pulse width
tCH(abs)
0.45
-
0.45
-
0.45
-
0.45
-
tCK(avg)
23
Absolute clock LOW pulse width
tCL(abs)
0.45
-
0.45
-
0.45
-
0.45
-
tCK(avg)
24
Clock Period Jitter- total
JIT(per)_tot
-63
63
-54
54
-47
47
-42
42
ps
23
Clock Period Jitter- deterministic
JIT(per)_dj
-31
31
-27
27
-23
23
-21
21
ps
26
Clock Period Jitter during DLL locking period
tJIT(per, lck)
-50
50
-43
43
-38
38
-33
33
ps
Cycle to Cycle Period Jitter
tJIT(cc)_total
125
107
94
83
ps
25
Cycle to Cycle Period Jitter deterministic
tJIT(cc)_dj
63
54
47
42
ps
26
Cycle to Cycle Period Jitter during
DLL locking period
tJIT(cc, lck)
100
86
75
67
ps
Clock Timing
Minimum Clock Cycle Time (DLL off
mode)
Duty Cycle Jitter
ns
tJIT(duty)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
Cumulative error across 2 cycles
tERR(2per)
-92
92
-79
79
-69
69
-61
61
ps
Cumulative error across 3 cycles
tERR(3per)
-109
109
-94
94
-82
82
-73
73
ps
Cumulative error across 4 cycles
tERR(4per)
-121
121
-104
104
-91
91
-81
81
ps
Cumulative error across 5 cycles
tERR(5per)
-131
131
-112
112
-98
98
-87
87
ps
Cumulative error across 6 cycles
tERR(6per)
-139
139
-119
119
-104
104
-92
92
ps
Cumulative error across 7 cycles
tERR(7per)
-145
145
-124
124
-109
109
-97
97
ps
Cumulative error across 8 cycles
tERR(8per)
-151
151
-129
129
-113
113
-101
101
ps
Cumulative error across 9 cycles
tERR(9per)
-156
156
-134
134
-117
117
-104
104
ps
Cumulative error across 10 cycles
tERR(10per)
-160
160
-137
137
-120
120
-107
107
ps
Cumulative error across 11 cycles
tERR(11per)
-164
164
-141
141
-123
123
-110
110
ps
Cumulative error across 12 cycles
tERR(12per)
-168
168
-144
144
-126
126
-112
112
ps
Cumulative error across 13 cycles
tERR(13per)
-172
172
-147
147
-129
129
-114
114
ps
Cumulative error across 14 cycles
tERR(14per)
-175
175
-150
150
-131
131
-116
116
ps
Cumulative error across 15 cycles
tERR(15per)
-178
178
-152
152
-133
133
-118
118
ps
Cumulative error across 16 cycles
tERR(16per)
-180
189
-155
155
-135
135
-120
120
ps
Cumulative error across 17 cycles
tERR(17per)
-183
183
-157
157
-137
137
-122
122
ps
Cumulative error across 18 cycles
tERR(18per)
-185
185
-159
159
-139
139
-124
124
ps
tERR(nper)min = ((1 + 0.68ln(n)) * tJIT(per)_total min)
tERR(nper)max = ((1 + 0.68ln(n)) * tJIT(per)_total max)
Cumulative error across n = 13, 14 .
. . 49, 50 cycles
tERR(nper)
Command and Address setup time
to CK_t, CK_c referenced to
Vih(ac) / Vil(ac) levels
tIS(base)
115
-
100
-
80
-
62
-
ps
Command and Address setup time
to CK_t, CK_c referenced to Vref
levels
tIS(Vref)
215
-
200
-
180
-
162
-
ps
Command and Address hold time
to CK_t, CK_c referenced to
Vih(dc) / Vil(dc) levels
tIH(base)
140
-
125
-
105
-
87
-
ps
Command and Address hold time
to CK_t, CK_c referenced to Vref
levels
tIH(Vref)
215
-
200
-
180
-
162
-
ps
Control and Address Input pulse
width for each input
tIPW
600
-
525
-
460
-
410
-
ps
tCCD_L
max(5 nCK,
6.250 ns)
-
max(5 nCK,
5.355 ns)
-
max(5 nCK,
5.355 ns)
-
max(5 nCK,
5 ns)
-
nCK
35,36
ps
Command and Address Timing
CAS_n to CAS_n command delay
for same bank group
- 33 -
34
Rev. 1.1
datasheet
Unbuffered SODIMM
Speed
DDR4-1600
DDR4 SDRAM
DDR4-1866
DDR4-2133
DDR4-2400
Units
NOTE
-
nCK
34
Max(4nCK,5
.3ns)
-
nCK
34
-
Max(4nCK,3
.3ns)
-
nCK
34
Max(4nCK,3.
7ns)
-
Max(4nCK,3
.3ns)
-
nCK
34
-
Max(4nCK,6.
4ns)
-
Max(4nCK,6
.4ns)
-
nCK
34
Max(4nCK,5.
3ns)
-
Max(4nCK,5.
3ns)
-
Max(4nCK,4
.9ns)
-
nCK
34
-
Max(4nCK,5.
3ns)
-
Max(4nCK,5.
3ns)
-
Max(4nCK,4
.9ns)
-
nCK
34
Max(28nCK,3
5ns)
-
Max(28nCK,3
0ns)
-
Max(28nCK,3
0ns)
-
Max(28nCK,
30ns)
-
ns
34
tFAW_1K
Max(20nCK,2
5ns)
-
Max(20nCK,2
3ns)
-
Max(20nCK,2
1ns)
-
Max(20nCK,
21ns)
-
ns
34
Four activate window for 1/2KB
page size
tFAW_1/2K
Max(16nCK,2
0ns)
-
Max(16nCK,1
7ns)
-
Max(16nCK,1
5ns)
-
Max(16nCK,
13ns)
-
ns
34
Delay from start of internal write
transaction to internal read command for different bank group
tWTR_S
max(2nCK,2.
5ns)
-
max(2nCK,2.
5ns)
-
max(2nCK,2.
5ns)
-
max (2nCK,
2.5ns)
-
Delay from start of internal write
transaction to internal read command for same bank group
tWTR_L
max(4nCK,7.
5ns)
-
max(4nCK,7.
5ns)
-
max(4nCK,7.
5ns)
-
max
(4nCK,7.5ns
)
-
Internal READ Command to PRECHARGE Command delay
tRTP
max(4nCK,7.
5ns)
-
max(4nCK,7.
5ns)
-
max(4nCK,7.
5ns)
-
max
(4nCK,7.5ns
)
-
WRITE recovery time
tWR
15
-
15
-
15
-
15
-
ns
1
Write recovery time when CRC and
DM are enabled
tWR_CRC
_DM
tWR+max
(4nCK,3.75ns
)
-
tWR+max
(5nCK,3.75ns
)
-
tWR+max
(5nCK,3.75ns
)
-
tWR+max
(5nCK,3.75n
s)
-
ns
1, 28
delay from start of internal write
transaction to internal read command for different bank group with
both CRC and DM enabled
tWTR_S_C
RC_DM
tWTR_S+ma
x
(4nCK,3.75ns
)
-
tWTR_S+ma
x
(5nCK,3.75ns
)
-
tWTR_S+ma
x
(5nCK,3.75ns
)
-
tWTR_S+m
ax
(5nCK,3.75n
s)
-
ns
2,
29,34
delay from start of internal write
transaction to internal read command for same bank group with
both CRC and DM enabled
tWTR_L_C
RC_DM
tWTR_L+max
(4nCK,3.75ns
)
-
tWTR_L+max
(5nCK,3.75ns
)
-
tWTR_L+max
(5nCK,3.75ns
)
-
tWTR_L+m
ax
(5nCK,3.75n
s)
-
ns
DLL locking time
tDLLK
597
-
597
-
768
-
768
-
nCK
Mode Register Set command cycle
time
tMRD
8
-
8
-
8
-
8
-
nCK
Mode Register Set command update delay
tMOD
max(24nCK,1
5ns)
-
max(24nCK,1
5ns)
-
max(24nCK,1
5ns)
-
max(24nCK,
15ns)
-
Multi-Purpose Register Recovery
Time
tMPRR
1
-
1
-
1
-
1
-
nCK
Multi Purpose Register Write Recovery Time
tWR_MPR
tMOD (min)
+ AL + PL
-
tMOD (min)
+ AL + PL
-
tMOD (min)
+ AL + PL
-
tMOD (min)
+ AL + PL
-
-
Auto precharge write recovery +
precharge time
tDAL(min)
DQ0 or DQL0 driven to 0 set-up
time to first DQS rising edge
tPDA_S
0.5
-
0.5
-
0.5
-
0.5
-
UI
45,47
DQ0 or DQL0 driven to 0 hold time
from last DQS fall-ing edge
tPDA_H
0.5
-
0.5
-
0.5
-
0.5
-
UI
46,47
tCAL
3
-
4
-
4
-
5
-
nCK
tDQSQ
-
0.16
-
0.16
-
0.16
-
0.16
tCK(avg)
/2
13,18
tQH
0.76
-
0.76
-
0.76
-
0.76
-
tCK(avg)
/2
13,17,1
8
tDVWd
0.63
-
0.63
-
0.64
-
0.64
-
UI
16,17,1
8
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
CAS_n to CAS_n command delay
for different bank group
tCCD_S
4
-
4
-
4
-
4
ACTIVATE to ACTIVATE Command
delay to different bank group for
2KB page size
tRRD_S(2K)
Max(4nCK,6n
s)
-
Max(4nCK,5.
3ns)
-
Max(4nCK,5.
3ns)
-
ACTIVATE to ACTIVATE Command
delay to different bank group for
2KB page size
tRRD_S(1K)
Max(4nCK,5n
s)
-
Max(4nCK,4.
2ns)
-
Max(4nCK,3.
7ns)
ACTIVATE to ACTIVATE Command
delay to different bank group for 1/
2KB page size
tRRD_S(1/
2K)
Max(4nCK,5n
s)
-
Max(4nCK,4.
2ns)
-
ACTIVATE to ACTIVATE Command
delay to same bank group for 2KB
page size
tRRD_L(2K)
Max(4nCK,7.
5ns)
-
Max(4nCK,6.
4ns)
ACTIVATE to ACTIVATE Command
delay to same bank group for 1KB
page size
tRRD_L(1K)
Max(4nCK,6n
s)
-
ACTIVATE to ACTIVATE Command
delay to same bank group for 1/2KB
page size
tRRD_L(1/
2K)
Max(4nCK,6n
s)
Four activate window for 2KB page
size
tFAW_2K
Four activate window for 1KB page
size
Programmed WR + roundup ( tRP / tCK(avg))
1,2,e,
34
1,34
3,30,34
33
nCK
CS_n to Command Address Latency
CS_n to Command Address Latency
DRAM Data Timing
DQS_t,DQS_c to DQ skew, per
group, per access
DQ output hold time from
DQS_t,DQS_c
Data Valid Window per device: tQH
- tDQSQ for a device
- 34 -
Rev. 1.1
datasheet
Unbuffered SODIMM
Speed
DDR4-1600
DDR4 SDRAM
DDR4-1866
DDR4-2133
DDR4-2400
Units
NOTE
-
UI
16,17,1
8
0.9
NOTE44
tCK
40
1.8
NOTE44
tCK
41
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Data Valid Window per device, per
pin: tQH - tDQSQ each device’s output
tDVWp
0.66
-
0.66
-
0.69
-
0.72
0.9
NOTE44
0.9
NOTE44
0.9
NOTE44
NA
NA
NA
NA
NA
NA
Data Strobe Timing
DQS_t, DQS_c differential READ
Preamble
tRPRE
DQS_t, DQS_c differential READ
Postamble
tRPST
0.33
TBD
0.33
TBD
0.33
TBD
0.33
TBD
tCK
DQS_t,DQS_c differential output
high time
tQSH
0.4
-
0.4
-
0.4
-
0.4
-
tCK
21
DQS_t,DQS_c differential output
low time
tQSL
0.4
-
0.4
-
0.4
-
0.4
-
tCK
20
0.9
-
0.9
-
0.9
-
0.9
-
tCK
42
NA
NA
NA
NA
NA
NA
1.8
NA
tCK
43
DQS_t, DQS_c differential WRITE
Preamble
tWPRE
DQS_t, DQS_c differential WRITE
Postamble
tWPST
0.33
TBD
0.33
TBD
0.33
TBD
0.33
TBD
tCK
DQS_t and DQS_c low-impedance
time (Referenced from RL-1)
tLZ(DQS)
-450
225
-390
195
-360
180
-300
150
ps
DQS_t and DQS_c high-impedance
time (Referenced from RL+BL/2)
tHZ(DQS)
-
225
-
195
-
180
-
150
ps
DQS_t, DQS_c differential input low
pulse width
tDQSL
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
tCK
DQS_t, DQS_c differential input
high pulse width
tDQSH
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
tCK
DQS_t, DQS_c rising edge to CK_t,
CK_c rising edge (1 clock preamble)
tDQSS
-0.27
0.27
-0.27
0.27
-0.27
0.27
-0.27
0.27
tCK
DQS_t, DQS_c falling edge setup
time to CK_t, CK_c rising edge
tDSS
0.18
-
0.18
-
0.18
-
0.18
-
tCK
DQS_t, DQS_c falling edge hold
time from CK_t, CK_c rising edge
tDSH
0.18
-
0.18
-
0.18
-
0.18
-
tCK
DQS_t, DQS_c rising edge output
timing locatino from rising CK_t,
CK_c with DLL On mode
tDQSCK
(DLL On)
-225
225
-195
195
-180
180
-175
175
ps
37,38,3
9
DQS_t, DQS_c rising edge output
variance window per DRAM
tDQSCKI
(DLL On)
290
ps
37,38,3
9
370
330
310
MPSM Timing
Command path disable delay upon
MPSM entry
tMPED
tMOD(min) +
tCPDED(min)
-
tMOD(min) +
tCPDED(min)
-
tMOD(min) +
tCPDED(min)
-
tMOD(min)
+
tCPDED(min)
-
Valid clock requirement after MPSM
entry
tCKMPE
tMOD(min) +
tCPDED(min)
-
tMOD(min) +
tCPDED(min)
-
tMOD(min) +
tCPDED(min)
-
tMOD(min)
+
tCPDED(min)
-
Valid clock requirement before
MPSM exit
tCKMPX
tCKSRX(min)
tCKSRX(min)
tCKSRX(min)
tCKSRX(mi
n)
-
Exit MPSM to commands not
requiring a locked DLL
tXMP
txs(imin)
txs(imin)
txs(imin)
txs(imin)
-
tXMPDLL
tXMP(min) +
tXSDLL(min)
tXMP(min) +
tXSDLL(min)
tXMP(min) +
tXSDLL(min)
tXMP(min) +
tXSDLL(min)
-
tMPX_S
tISmin + tIHmin
-
tISmin + tIHmin
-
tISmin + tIHmin
-
tISmin + tIHmin
-
Power-up and RESET calibration
time
tZQinit
1024
-
1024
-
1024
-
1024
-
nCK
Normal operation Full calibration
time
tZQoper
512
-
512
-
512
-
512
-
nCK
tZQCS
128
-
128
-
128
-
128
-
nCK
Exit Reset from CKE HIGH to a valid
command
tXPR
max
(5nCK,tRFC(
min)+
10ns)
-
max
(5nCK,tRFC(
min)+
10ns)
-
max
(5nCK,tRFC(
min)+
10ns)
-
max
(5nCK,tRFC
(min)+10ns)
-
Exit Self Refresh to commands not
requiring a locked DLL
tXS
tRFC(min)+1
0ns
-
tRFC(min)+1
0ns
-
tRFC(min)+1
0ns
-
tRFC(min)+
10ns
-
SRX to commands not requiring a
locked DLL in Self Refresh ABORT
tXS_ABORT(
min)
tRFC4(min)+
10ns
-
tRFC4(min)+
10ns
-
tRFC4(min)+
10ns
-
tRFC4(min)
+10ns
-
Exit MPSM to commands requiring
a locked DLL
CS setup time to CKE
Calibration Timing
Normal operation Short calibration
time
Reset/Self Refresh Timing
- 35 -
datasheet
Unbuffered SODIMM
Speed
Parameter
Rev. 1.1
DDR4-1600
DDR4 SDRAM
DDR4-1866
DDR4-2133
DDR4-2400
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Exit Self Refresh to ZQCL,ZQCS
and MRS (CL,CWL,WR,RTP and
Gear Down)
tXS_FAST
(min)
tRFC4(min)+
10ns
-
tRFC4(min)+
10ns
-
tRFC4(min)+
10ns
-
tRFC4(min)
+10ns
-
Exit Self Refresh to commands requiring a locked DLL
tXSDLL
tDLLK(min)
-
tDLLK(min)
-
tDLLK(min)
-
tDLLK(min)
-
Minimum CKE low width for Self refresh entry to exit timing
tCKESR
tCKE(min)+1
nCK
-
tCKE(min)+1
nCK
-
tCKE(min)+1
nCK
-
tCKE(min)+
1nCK
-
Minimum CKE low width for Self refresh entry to exit timing with CA
Parity enabled
tCKESR_
PAR
tCKE(min)+
1nCK+PL
-
tCKE(min)+
1nCK+PL
-
tCKE(min)+
1nCK+PL
-
tCKE(min)+
1nCK+PL
-
Valid Clock Requirement after Self
Refresh Entry (SRE) or PowerDown Entry (PDE)
tCKSRE
max(5nCK,10
ns)
-
max(5nCK,10
ns)
-
max(5nCK,10
ns)
-
max
(5nCK,10ns)
-
Valid Clock Requirement after Self
Refresh Entry (SRE) or PowerDown when CA Parity is enabled
tCKSRE_PAR
max
(5nCK,10ns)
+PL
-
max
(5nCK,10ns)
+PL
-
max
(5nCK,10ns)
+PL
-
max
(5nCK,10ns)
+PL
-
Valid Clock Requirement before Self
Refresh Exit (SRX) or Power-Down
Exit (PDX) or Reset Exit
tCKSRX
max(5nCK,10
ns)
-
max(5nCK,10
ns)
-
max(5nCK,10
ns)
-
max
(5nCK,10ns)
-
tXP
max
(4nCK,6ns)
-
max
(4nCK,6ns)
-
max
(4nCK,6ns)
-
max
(4nCK,6ns)
-
tCKE
max (3nCK,
5ns)
-
max (3nCK,
5ns)
-
max (3nCK,
5ns)
-
max
(3nCK, 5ns)
-
Units
NOTE
Power Down Timing
Exit Power Down with DLL on to any
valid command;Exit Precharge
Power Down with DLL frozen to
commands not requiring a locked
DLL
CKE minimum pulse width
Command pass disable delay
31,32
tCPDED
4
-
4
-
4
-
4
-
tPD
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
Timing of ACT command to Power
Down entry
tACTPDEN
1
-
1
-
2
-
2
-
nCK
7
Timing of PRE or PREA command
to Power Down entry
tPRPDEN
1
-
1
-
2
-
2
-
nCK
7
Timing of RD/RDA command to
Power Down entry
tRDPDEN
RL+4+1
-
RL+4+1
-
RL+4+1
-
RL+4+1
-
nCK
Timing of WR command to Power
Down entry (BL8OTF, BL8MRS,
BC4OTF)
tWRPDEN
WL+4+(tWR/
tCK(avg))
-
WL+4+(tWR/
tCK(avg))
-
WL+4+(tWR/
tCK(avg))
-
WL+4+(tWR
/tCK(avg))
-
nCK
4
tWRAPDEN
WL+4+WR+1
-
WL+4+WR+1
-
WL+4+WR+1
-
WL+4+WR+
1
-
nCK
5
Timing of WR command to Power
Down entry (BC4MRS)
tWRPBC4DEN
WL+2+(tWR/
tCK(avg))
-
WL+2+(tWR/
tCK(avg))
-
WL+2+(tWR/
tCK(avg))
-
WL+2+(tWR
/tCK(avg))
-
nCK
4
Timing of WRA command to Power
Down entry (BC4MRS)
tWRAPBC4DEN
WL+2+WR+1
-
WL+2+WR+1
-
WL+2+WR+1
-
WL+2+WR+
1
-
nCK
5
Timing of REF command to Power
Down entry
tREFPDEN
1
-
1
-
2
-
2
-
nCK
7
Timing of MRS command to Power
Down entry
tMRSPDEN
tMOD(min)
-
tMOD(min)
-
tMOD(min)
-
tMOD(min)
-
Mode Register Set command cycle
time in PDA mode
tMRD_PDA
max(16nCK,1
0ns)
Mode Register Set command update delay in PDA mode
tMOD_PDA
Power Down Entry to Exit Timing
Timing of WRA command to Power
Down entry (BL8OTF, BL8MRS,
BC4OTF)
nCK
6
PDA Timing
max(16nCK,1
0ns)
tMOD
max(16nCK,1
0ns)
tMOD
max(16nCK,
10ns)
tMOD
tMOD
ODT Timing
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
tAONAS
1.0
9.0
1.0
9.0
1.0
9.0
1.0
9.0
ns
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
tAOFAS
1.0
9.0
1.0
9.0
1.0
9.0
1.0
9.0
ns
tADC
0.3
0.7
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
First DQS_t/DQS_n rising edge after write leveling mode is programmed
tWLMRD
40
-
40
-
40
-
40
-
nCK
12
DQS_t/DQS_n delay after write leveling mode is programmed
tWLDQSEN
25
-
25
-
25
-
25
-
nCK
12
Write leveling setup time from rising
CK_t, CK_c crossing to rising
DQS_t/DQS_n crossing
tWLS
0.13
-
0.13
-
0.13
-
0.13
-
tCK(avg)
Write leveling hold time from rising
DQS_t/DQS_n crossing to rising
CK_t, CK_ crossing
tWLH
0.13
-
0.13
-
0.13
-
0.13
-
tCK(avg)
RTT dynamic change skew
Write Leveling Timing
- 36 -
datasheet
Unbuffered SODIMM
Speed
Parameter
Rev. 1.1
DDR4-1600
DDR4 SDRAM
DDR4-1866
DDR4-2133
DDR4-2400
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Write leveling output delay
tWLO
0
9.5
0
9.5
0
9.5
0
9.5
Write leveling output error
tWLOE
Units
NOTE
ns
ns
CA Parity Timing
Commands not guaranteed to be
executed during this time
tPAR_UNKNOWN
-
PL
-
PL
-
PL
-
PL
Delay from errant command to
ALERT_n assertion
tPAR_ALER
T_ON
-
PL+6ns
-
PL+6ns
-
PL+6ns
-
PL+6ns
Pulse width of ALERT_n signal
when asserted
tPAR_ALER
T_PW
48
96
56
112
64
128
72
144
nCK
Time from when Alert is asserted till
controller must start providing DES
commands in Persistent CA parity
mode
tPAR_ALER
T_RSP
-
43
-
50
-
57
-
64
nCK
Parity Latency
PL
4
4
4
5
nCK
CRC Error Reporting
CRC error to ALERT_n latency
tCRC_ALER
T
3
13
3
13
3
13
3
13
ns
CRC ALERT_n pulse width
CRC_ALER
T_PW
6
10
6
10
6
10
6
10
nCK
2Gb
160
-
160
-
160
-
160
-
ns
34
4Gb
260
-
260
-
260
-
260
-
ns
34
8Gb
350
-
350
-
350
-
350
-
ns
34
16Gb
TBD
-
TBD
-
TBD
-
TBD
-
ns
34
2Gb
110
-
110
-
110
-
110
-
ns
34
4Gb
160
-
160
-
160
-
160
-
ns
34
8Gb
260
-
260
-
260
-
260
-
ns
34
16Gb
TBD
-
TBD
-
TBD
-
TBD
-
ns
34
2Gb
90
-
90
-
90
-
90
-
ns
34
4Gb
110
-
110
-
110
-
110
-
ns
34
8Gb
160
-
160
-
160
-
160
-
ns
34
16Gb
TBD
-
TBD
-
TBD
-
TBD
-
ns
34
tREFI
tRFC1 (min)
tRFC2 (min)
tRFC4 (min)
- 37 -
Unbuffered SODIMM
datasheet
Rev. 1.1
DDR4 SDRAM
NOTE :
1. Start of internal write transaction is defined as follows :
For BL8 (Fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL.
2. A separate timing parameter will cover the delay from write to read when CRC and DM are simultaneously enabled
3. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
4. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR/tCK to the next integer.
5. WR in clock cycles as programmed in MR0.
6. tREFI depends on TOPER.
7. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down
IDD spec will not be applied until finishing those operations.
8. For these parameters, the DDR4 SDRAM device supports tnPARAM[nCK]=RU{tPARAM[ns]/tCK(avg)[ns]}, which is in clock cycles assuming all input clock jitter
specifications are satisfied
9. When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR.
10. When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S.
11. When CRC and DM are both enabled tWTR_L_CRC_DM is used in place of tWTR_L.
12. The max values are system dependent.
13. DQ to DQS total timing per group where the total includes the sum of deterministic and random timing terms for a specified BER. BER spec and measurement method are
tbd.
14. The deterministic component of the total timing. Measurement method tbd.
15. DQ to DQ static offset relative to strobe per group. Measurement method tbd.
16. This parameter will be characterized and guaranteed by design.
17 When the device is operated with the input clock jitter, this parameter needs to be derated by the actual tjit(per)_total of the input clock. (output deratings are relative to the
SDRAM input clock). Example tbd.
18. DRAM DBI mode is off.
19. DRAM DBI mode is enabled. Applicable to x8 and x16 DRAM only.
20. tQSL describes the instantaneous differential output low pulse width on DQS_t - DQS_c, as measured from on falling edge to the next consecutive rising edge
21. tQSH describes the instantaneous differential output high pulse width on DQS_t - DQS_c, as measured from on falling edge to the next consecutive rising edge
22. There is no maximum cycle time limit besides the need to satisfy the refresh interval tREFI
23. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge
24. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge
25. Total jitter includes the sum of deterministic and random jitter terms for a specified BER. BER target and measurement method are tbd.
26. The deterministic jitter component out of the total jitter. This parameter is characterized and gauranteed by design.
27. This parameter has to be even number of clocks
28. When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR.
29. When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S.
30. When CRC and DM are both enabled tWTR_L_CRC_DM is used in place of tWTR_L.
31. After CKE is registered LOW, CKE signal level shall be maintained below VILDC for tCKE specification ( Low pulse width ).
32. After CKE is registered HIGH, CKE signal level shall be maintained above VIHDC for tCKE specification ( HIGH pulse width ).
33. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
34. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the Speed Bin Tables.
35. This parameter must keep consistency with Speed-Bin Tables shown in Device Operation.
36. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.
UI=tCK(avg).min/2
37. applied when DRAM is in DLL ON mode.
38. Assume no jitter on input clock signals to the DRAM
39. Value is only valid for RZQ/7
40. 1tCK toggle mode with setting MR4:A11 to 0
41. 2tCK toggle mode with setting MR4:A11 to 1, which is valid for DDR4-2400 speed grade.
42. 1tCK mode with setting MR4:A12 to 0
43. 2tCK mode with setting MR4:A12 to 1, which is valid for DDR4-2400 speed grade.
44. The maximum read preamble is bounded by tLZ(DQS)min on the left side and tDQSCK(max) on the right side. See Device Operation.
to Data Strobe Relationship”. Boundary of DQS Low-Z occur one cycle earlier in 2tCK toggle mode which is illustrated in See Device Operation Preamble”.
45.DQ falling signal middle-point of transferring from High to Low to first rising edge of DQS diff-signal cross-point
46. last falling edge of DQS diff-signal cross-point to DQ rising signal middle-point of transferring from Low to High
47. VrefDQ value must be set to either its midpoint or Vcent_DQ(midpoint) in order to capture DQ0 or DQL0 low level for entering PDA mode.
- 38 -
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
16. Physical Dimensions
16.1 1Gx8 based 2Gx64 Module (2 Ranks) - M471A2K43BB1
Units : Millimeters
69.60
30.00
65.60
Max 3.7
B
A
35.50
28.50
1.2 ± 0.10
1.375
0.35 ± 0.03
0.50
4.00 ± 0.10
0.25 Max
2.55
1.00 ± 0.05
0.25 Max
0.30 Max
Detail A
Detail B
The used device is 1G x8 DDR4 SDRAM, Flip-Chip.
DDR4 SDRAM Part NO : K4A8G085WB - BC**
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
- 39 -
Rev. 1.1
datasheet
Unbuffered SODIMM
DDR4 SDRAM
16.2 1Gx8 based 2Gx72 Module (2 Ranks) - M474A2K43BB1
Units : Millimeters
69.60
30.00
65.60
Max 3.7
B
A
35.50
28.50
1.2 ± 0.10
1.375
0.35 ± 0.03
0.50
4.00 ± 0.10
0.25 Max
2.55
1.00 ± 0.05
0.25 Max
0.30 Max
Detail A
Detail B
The used device is 1G x8 DDR4 SDRAM, Flip-Chip.
DDR4 SDRAM Part NO : K4A8G085WB - BC**
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
- 40 -
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising