Intel® I/O Controller Hub 9M/ 82567LF/LM/V NVM Map and

Intel® I/O Controller Hub 9M/ 82567LF/LM/V NVM Map and
Intel® I/O Controller Hub 9M/
82567LF/LM/V NVM Map and
Information Guide
November 2008
317093-005
Revision 2.1
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NVM Information Guide—ICH9M/82567LF/LM/V
Contents
1.0
Non-Volatile Memory (NVM) ...................................................................................... 5
1.1
Introduction ....................................................................................................... 5
1.2
NVM Programming Procedure Overview .................................................................. 5
1.3
EEUPDATE Utility................................................................................................. 7
1.3.1 Command Line Parameters ........................................................................ 7
1.4
LAN NVM Format and Contents.............................................................................. 8
1.4.1 Ethernet Individual Address (Words 00h - 02h) ............................................ 9
1.4.2 Reserved (Word 03h).............................................................................. 10
1.4.3 Reserved (Word 04h).............................................................................. 10
1.4.4 Image Version Information (Word 05h) ..................................................... 10
1.4.5 Reserved (Words 06h and 07h) ................................................................ 10
1.4.6 PBA Low, PBA High (Words 08h and 09h) .................................................. 11
1.4.7 PCI Initialization Control (Word 0Ah)......................................................... 11
1.4.8 Subsystem ID (Word 0Bh) ....................................................................... 12
1.4.9 Subsystem Vendor ID (Word 0Ch) ............................................................ 12
1.4.10 Device ID (Word 0Dh)............................................................................. 12
1.4.11 Vendor ID (Word 0Eh) ............................................................................ 12
1.4.12 Device Rev ID (Word 0Fh) ....................................................................... 12
1.4.13 LAN Power Consumption (Word 10h) ........................................................ 12
1.4.14 Reserved Words 11h and 12h .................................................................. 13
1.4.15 Shared Initialization Control (Word 13h).................................................... 13
1.4.16 Extended Configuration Word 1 (Word 14h) ............................................... 14
1.4.17 Extended Configuration Word 2 (Word 15h) ............................................... 14
1.4.18 Extended Configuration Word 3 (Word 16h) ............................................... 14
1.4.19 LED 1 Configuration and Power Management (Word 17h)............................. 15
1.4.20 LED 0 and 2 Configuration Defaults (Word 18h).......................................... 17
1.4.21 Reserved Word 19h ................................................................................ 18
1.4.22 Reserved Word 1Ah ................................................................................ 18
1.4.23 Reserved Word 1Bh ................................................................................ 18
1.4.24 Reserved Word 1Ch ................................................................................ 18
1.4.25 Reserved Word 1Dh................................................................................ 18
1.4.26 Device ID (Word 1Eh) ............................................................................. 18
1.4.27 Device ID (Word 1Fh) ............................................................................. 18
1.4.28 Reserved Words 20h, 22h, and 23h .......................................................... 19
1.4.29 Device ID (Word 21h) ............................................................................. 19
1.4.30 Reserved Words 24h - 2Fh ...................................................................... 19
1.4.31 PXE Words (Words 30h - 3Eh).................................................................. 19
1.4.32 Checksum (Word 3Fh) ............................................................................ 23
A
ICH9M NVM Contents and Sample Images ............................................................... 24
A.1
82567LF/LM/V NVM Image with ICH9M ................................................................ 25
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ICH9M/82567LF/LM/V—NVM Information Guide
Revision History
Rev
Rev Date
Description
2.1
November 2008
Updated Table 19 and Table 21.
Updated Section 1.4.14.
2.01
March 2008
Initial public release.
0.8
October 2007
Updated to reflect the ICH9M/82567, stepping A2, revision 1.6 NVM image.
0.6
August 2007
Updated bit descriptions.
0.5
June 2007
Initial release (Intel Confidential)
1. The revision designation conventions have changed. Revision 2.0 is now the revision associated with product
announcement; previously the value was 1.0. Note that there have been no interim releases between 0.8 and
2.0.
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ICH9M/82567LF/LM/V—NVM Information Guide
1.0
Non-Volatile Memory (NVM)
1.1
Introduction
The document is intended for designs using a 10/100/1000 Mb/s Media Access
Controller (MAC) that is integrated into an Intel® I/O Control Hub 9M (ICH9M) device in
conjunction with an 82567LF/82567LM/82567V Physical Layer Transceiver (PHY).
The NVM space is used for hardware and software configuration. It is also read by
software to determine and configure specific design features.
Unless otherwise specified, all numbers in this document use the following numbering
convention:
• Numbers that do not have a suffix are decimal (base 10).
• Numbers with a suffix of “h” are hexadecimal (base 16).
• Numbers with a suffix of “b” are binary (base 2).
1.2
NVM Programming Procedure Overview
The LAN NVM shares space on an SPI Flash device (or devices) along with the BIOS,
Manageability Firmware, and a Flash Descriptor Region. It is programmed through the
ICH9M. This combined image is shown in Figure 1. The Flash Descriptor Region is used
to define vendor specific information and the location, allocated space, and read and
write permissions for each region. The Manageability (ME) Region contains the code
and configuration data for ME functions such as Intel® Active Management Technology,
ASF, and Advanced Fan Speed Control. The system BIOS is contained in the BIOS
Region. The ME Region and BIOS Region are beyond the scope of this document and a
more detailed explanation of these areas can be found in the Intel® I/O Controller Hub
9 (ICH9M) Family External Design Specification (ICH9M EDS). This document describes
the LAN image contained in the Gigabit Ethernet (GbE) region.
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NVM Information Guide—ICH9M/82567LF/LM/V
BIOS
Region 1
ME
Region 2
GbE
Region 3
Flash Descriptor
Region 0
Figure 1.
LAN NVM Regions
To access the NVM, it is essential to correctly setup the following:
1. A valid Flash Descriptor Region must be present. Details for the Flash Descriptor
Region are contained in the ICH9M EDS. The FTOOLc.exe utility provides the
easiest method of configuring this descriptor region. This process is described in
detail in the Intel® Active Management Technology OEM Bring-Up Guide.
FTOOLc.exe and the Intel® Active Management Technology OEM Bring-Up Guide
can be obtained as part of the Intel® Active Client Manager kit on ARMS
(https://platformsw.intel.com/) or by contacting your local Intel® representative.
2. The GbE region is an 8 KB ->2* 4 KB (if erase sector size is larger than 4 KB, then
GbE region is 2 times the erase sector size) and must be part of the original image
flashed onto the part.
3. For Intel® LAN tools and drivers to work correctly, the BIOS must set the VSCC
registers correctly.
There are two sets of VSCC registers, the upper (UVSCC) and lower (LVSCC). Note
that the LVSCC register is only used if the NVM attributes change. For example, the
use of a second flash component, a change in erase size between segments, etc.
Due to the architecture of the ICH9M, if these registers are not set correctly, the
LAN tools might not report an error message even though the NVM contents remain
unchanged. Refer to the ICH9M EDS for more information.
4. The GbE region of the NVM must be accessible. To keep this region accessible, the
Protected Range register of the GbE LAN Memory Mapped Configuration registers
must be set to their default value of 0000 0000h. (The GbE Protected Range
registers are described in the ICH9M EDS).
5. When using the 82567, bit 19 of the ICH9M STRP0 register must be set to 1b to
configure PCI Express* (PCIe*) port 6 as GLCI. Refer to the ICH9M EDS for more
details.
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ICH9M/82567LF/LM/V—NVM Information Guide
6. The sector size of the NVM must equal 256 bytes, 4 KB, or 64 KB. When a Flash
device that uses a 64 KB sector erase is used, the GbE region size must equal
128 KB. If the Flash part uses a 4 KB or 256-byte sector erase, then the GbE region
size must be set to 8 KB.
The NVM image contains both static and dynamic data. The static data is the basic
platform configuration, and includes OEM specific configuration bits as well as the
unique Printed Circuit Board Assembly (PBA). The dynamic data holds the product’s
Ethernet Individual Address (IA) and Checksum. This file can be created in a simple
text editor and follows the format shown in Appendix A, which provides examples of
GbE Region NVM maps for ICH9M-based designs.
1.3
EEUPDATE Utility
Intel® has created an EEUPDATE utility that can be used to update the GbE region
images during in-circuit programming. The tool uses two basic data files outlined in the
following section (static data file and IA address file). The EEUPDATE utility is flexible
and can be used to update the entire GbE region image or only the IA address of the
LAN controller. In addition, it also corrects the GbE component checksum field after the
region is modified (FTOOLc does not have this ability). For more information on how to
use EEUPDATE, refer to the eeupdate.txt file that is included with the EEUPDATE
utility.
To obtain a copy of this program, contact your Intel® representative.
1.3.1
Command Line Parameters
The DOS command format is as follows:
EEUPDATE Parameter_1 Parameter_2
where:
Parameter_1 = /D or /A
/D is used to update the entire GbE region image.
/A is used to update just the Ethernet Individual Address.
Parameter_2 = filename
In Example 1, Parameter_2 is file1.eep, which contains the complete NVM image in
a specific format used to update the complete GbE region. All comments in the .eep
file must be preceded by a semicolon (;).
Example 1.
EEUPDATE /D file1.eep
In Example 1, Parameter 2 is file2.dat, which contains a list of IA addresses. The
EEUPDATE utility finds the first unused address from this file and uses it to update the
NVM. An address is marked used if it is followed by a date stamp. When the utility uses
a specific address, a log file called eelog.dat is updated with that address. This updated
file should be used as the .dat file for the next update.
Appendix A provides an example of the raw GbE region contents.
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NVM Information Guide—ICH9M/82567LF/LM/V
1.4
LAN NVM Format and Contents
Table 1 lists the NVM maps for the LAN region. Each word listed is described in detail in
the following sections.
Table 1.
8
LAN NVM Address Map
LAN
Word
Offset
NVM
Byte
Offset
HIgh Byte (Bits 15:8)
Low Byte (Bits 7:0)
Used By
Image
Value
00h
00h
Ethernet Individual Address
Byte 2
Ethernet Individual Address
Byte 1
HWShared
IA (2,1)
01h
02h
Ethernet Individual Address
Byte 4
Ethernet Individual Address
Byte 3
HWShared
IA (4,3)
02h
04h
Ethernet Individual Address
Byte 6
Ethernet Individual Address
Byte 5
HWShared
IA (6,5)
03h
06h
Reserved
SW
0800h
04h
08h
Reserved
SW
FFFFh
05h
0Ah
Reserved
SW
06h
0Ch
Reserved
SW
FFFFh
07h
0Eh
Reserved
SW
FFFFh
08h
10h
PBA Low
SW
09h
12h
PBA High
SW
0Ah
14h
PCI Initialization Control Word
HW-PCI
0Bh
16h
Subsystem ID
HW-PCI
0Ch
18h
Subsystem Vendor ID
HW-PCI
0Dh
1Ah
Device ID
HW-PCI
0Eh
1Ch
Vendor ID
HW-PCI
0Fh
1Eh
Device Rev ID
HW-PCI
10h
20h
LAN Power Consumption
HW-PCI
11h
22h
Reserved
12h
24h
Reserved
13h
26h
Shared Initialization Control Word
HWShared
14h
28h
Extended Configuration Word 1
HWShared
15h
2Ah
Extended Configuration Word 2
HWShared
16h
2Ch
Extended Configuration Word 3
HWShared
17h
2Eh
LEDCTL 1
HWShared
18h
30h
LEDCTL 0 2
HWShared
19h
32h
Reserved
HWShared
2B00h
1Ah
34h
Reserved
HWShared
0043h
ICH9M/82567LF/LM/V—NVM Information Guide
LAN
Word
Offset
NVM
Byte
Offset
1Bh
36h
Reserved
1Ch
38h
Reserved
10F5h
Low Byte (Bits 7:0)
Used By
Image
Value
1Dh
3Ah
Reserved
BAADh
1Eh
3Ch
82567LM Device ID
10F5h
1Fh
3Eh
82567LF Device ID
10BFh
20h
40h
Reserved
BAADh
21h
42h
82567V Device ID
10CBh
22h
44h
Reserved
BAADh
BAADh
23h
46h
Reserved
24h:2Fh
48h:5Eh
Reserved
30h:3Eh
60h:7Dh
PXE Software Region
PXE
3Fh
7Eh
Software Checksum (bytes 00h through 7Dh)
SW
Notes:
1.
2.
3.
4.
1.4.1
HIgh Byte (Bits 15:8)
SW = Software: This is access from the network configuration tools and drivers.
PXE = PXE Boot Agent: This is access from the PXE Option ROM code in BIOS.
HW-Shared = Hardware - Shared: This is read on when the Shared Configuration is reset.
HW-PCI = Hardware - PCI: This is read when the PCI Configuration is reset.
Ethernet Individual Address (Words 00h - 02h)
The Ethernet Individual Address (IA) is a six-byte field that must be unique for each
adapter card or LOM and unique for each copy of the NVM image. The first three bytes
are vendor specific. (For example, these bytes equal 00 A0 C9 for Intel® products.) The
last three bytes must be unique for each copy of the NVM. OEM versions of the product
might be required to have non-Intel® ID’s in the first three byte positions. The value
from this field is loaded into the Receive Address Register 0 (RAL0/RAH0). The Intel®
default is listed in Table 2.
Table 2.
Ethernet Individual Address (Words 00h - 02h)
Individual Address Byte
Word 00
Note:
Manufacturer
MAC Address
Intel® Products
00A0C9XXYYZZh
Byte
2
A0h
Byte
1
00h
Word 01
Byte
4
XXh
Byte
3
C9h
Word 02
Byte
6
ZZh
Byte
5
YYh
The Ethernet IA is byte swapped, as listed in Table 2.
The IA bytes read from the NVM are used by the ICH9M until an IA Setup command is
issued by software. The IA defined by the IA Setup command overrides the IA read
from the NVM.
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NVM Information Guide—ICH9M/82567LF/LM/V
1.4.2
Reserved (Word 03h)
Table 3.
Reserved (Word 03h)
Bit
15:12
Name
Reserved
Default
0000b
These bits are reserved and should be set to 0000b.
11
IBA LOM
1b
Must be set to 1b for Intel® Boot Agent (IBA) to function correctly.
10:0
Reserved
00h
These bits are reserved and should be set to 00h.
1.4.3
Reserved (Word 04h)
Table 4.
Reserved (Word 04h)
Bit
15:0
1.4.4
Description
Name
Reserved
Default
FFFFh
Description
These bits are reserved and should be set to FFFFh.
Image Version Information (Word 05h)
This is a reserved word and cannot be changed.
1.4.5
Reserved (Words 06h and 07h)
Table 5.
Reserved (Words 06h and 07h)
Bit
15:0
10
Name
Reserved
Default
FFFFh
Description
This field is reserved and should be set to FFFFh.
ICH9M/82567LF/LM/V—NVM Information Guide
1.4.6
PBA Low, PBA High (Words 08h and 09h)
The nine digit printed board assembly (PBA) number used for Intel® manufactured
adapter cards are stored in a four-byte field. The dash and the first digit of the threedigit suffix are not stored. The default for both words is FFFFh.
1.4.6.1
PBA Example
If the PBA Number is “123456-003”
then word 08h = 1234h and word 09h = 5603h.
Through the course of hardware changes, the suffix field (byte 4) is incremented. The
purpose of this information is to enable customer support (or any user) to identify the
exact revision level of a product. The software device driver should not rely on this field
to identify the product or its capabilities.
1.4.7
PCI Initialization Control (Word 0Ah)
This word contains initialization values that:
• Set defaults for some internal registers.
• Enable/disable specific features.
• Determine which PCI configuration space values are loaded from the NVM.
Table 6.
Initialization Control Word (Word 0Ah)
Bit
Name
Default
Description
15:12
Reserved
0001b
11:8
Reserved
0000b
These bits are reserved and should be set to 0000b.
1b
Auxiliary Power Indication
If set and if PM Ena is set, D3cold wake-up is advertised in the PMC
register of the PCI function.
0b = No AUX power.
1b = AUX power.
7
AUX PWR
This field is reserved and must be set to 0001b.
6
PM Enable
1b
Power Management Enable (PME-WoL)
Enables asserting PME in the PCI function at any power state. This
bit affects the advertised PME_Support indication in the PMC
register of the PCI function.
0b = Disable.
1b = Enable.
5:3
Reserved
000b
These bits are reserved and must be set to 000b.
2
Reserved
0b
This bit is reserved and should be set to 0b.
1b
Load Subsystem IDs from EEPROM
When set to 1b, indicates that the device is to load its PCI
Subsystem ID and Subsystem Vendor ID from the NVM (words 0Bh
and 0Ch).
0b = Load from MAC fuses.
1b = Load from NVM.
1b
Load Vendor/Device IDs from EEPROM
When set to 0b, the ICH9M loads its PCI Vendor and Device IDs
built into the MAC.
When set to 1b, the ICH9M loads its PCI Vendor ID from NVM word
0Eh and the Device ID from NVM word 0Dh.
0b = Load from MAC fuses.
1b = Load from NVM.
1
0
Load Subsystem IDs
Load Vendor/Device
IDs
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NVM Information Guide—ICH9M/82567LF/LM/V
1.4.8
Subsystem ID (Word 0Bh)
If Load Subsystem IDs bit of word 0Ah is set to 1b, this word is read in to initialize the
Subsystem ID. The Subsystem ID default value is 0000h.
1.4.9
Subsystem Vendor ID (Word 0Ch)
If Load Subsystem IDs bit of word 0Ah is set to 1b, this word is read in to initialize the
Subsystem Vendor ID. The Subsystem Vendor ID default value is 8086h.
1.4.10
Device ID (Word 0Dh)
If the Load Vendor/Device IDs bit in word 0Ah is set to 1b, this word is read to initialize
the Device ID of the LAN function using words 21h, 1Eh or 1Fh.
Device IDs for Intel® Platform LAN Connects
Table 7.
Device ID
1.4.11
Adapter
10F5h
Intel® 82567LM Gigabit Ethernet Controller
10BFh
Intel® 82567LF Gigabit Ethernet Controller
10CBh
Intel® 82567V Gigabit Ethernet Controller
Vendor ID (Word 0Eh)
If the Load Vendor/Device IDs bit in word 0Ah is set to 1b, this word is read to initialize
the Vendor ID. The default Vendor ID value is 8086h.
1.4.12
Device Rev ID (Word 0Fh)
Table 8.
Device Rev ID (Word 0Fh)
Bit
15:0
1.4.13
Name
Default
Reserved
00h
Description
These bits are reserved and must be set to 00h.
LAN Power Consumption (Word 10h)
This word is only relevant when power management is enabled.
Table 9.
LAN Power Consumption (Word 10h)
Bit
Default
Description
The value in this field is reflected in the PCI Power Management
Data Register of the LAN function for D0 power consumption
and dissipation (Data_Select = 0 or 4). Power is defined in 100
mW units and includes the external logic required for the LAN
function. Defined to be 1.3 W.
15:8
LAN D0
Power
0Dh
7:5
Reserved
000b
These bits are reserved and should be set to 000b.
01h
The value in this field is reflected in the PCI Power Management
Data Register of the LAN function for D3 power consumption
and dissipation (Data_Select = 3 or 7). Power is defined in 100
mW units and includes the external logic required for the LAN
function. The most significant bits in the Data Register that
reflects the power values are padded with zeros. Defined to be
100 mW.
4:0
12
Name
LAN D3
Power
ICH9M/82567LF/LM/V—NVM Information Guide
1.4.14
Reserved Words 11h and 12h
Table 10.
Reserved (Words 11h and 12h)
Bit
15:0
1.4.15
Name
Reserved
Default
00h
Description
These bits are reserved and should be set to 00h.
Shared Initialization Control (Word 13h)
This word controls general initialization values.
Table 11.
Shared Initialization Control (Word 13h)
Bit
Name
Default
Description
15:14
SIGN
10b
This is a 2-bit field indicating whether a valid NVM is present to the
MAC. If this field does not equal 10b, the MAC does not read the
NVM data and uses default values for device configuration.
00b = Invalid NVM.
01b = Invalid NVM.
10b = Valid NVM present.
11b = Invalid NVM.
13:11
Reserved
000b
These bits are reserved and should be set to 000b.
10
Reserved
1b
Reserved. Should be set to 1b.
9
PHY PD Enable
1b
PHY Power Down in D3/Dr (if WoL is disabled)
0b = Disable power down in non D0.
1b = Enable power down in non D0.
This bit is loaded to the PHY Power Down Enable bit in the
CTRL_EXT register.
8:5
Reserved
0000b
These bits are reserved and should be set to 0000b.
4
FRCSPD
0b
Force Speed Enable
Default setting for the Force Speed bit in the Device Control
register (CTRL[11]). The hardware default value is 0b.
3
FD
0b
Force Duplex
Default setting for duplex setting. Mapped to CTRL[0]. The
hardware default value is 0b.
2:0
Reserved
101b
These bits are reserved and should be set to 101b.
13
NVM Information Guide—ICH9M/82567LF/LM/V
1.4.16
Extended Configuration Word 1 (Word 14h)
Table 12.
Extended Configuration Word 1 (Word 14h)
Bit
1.4.17
Table 13.
Table 14.
Description
Reserved
0b
Reserved
14
Reserved
0b
Reserved
13
Reserved
1b
Reserved
12
OEM Write Enable
1b
When set, enables auto load of the OEM bits from the PHY_CTRL
register to the 82567. It is loaded to the EXTCNF_CTRL register.
0b = Disable.
1b = Enable.
11:0
Extended
Configuration
Pointer
020h
This field defines the base address (in Dwords) of the extended
configuration area in the NVM. It should equal a non-zero value.
Extended Configuration Word 2 (Word 15h)
Extended Configuration Word 2 (Word 15h)
Name
Default
Description
15:8
Extended PHY
Length
0000101b
This field identifies the size (in Dwords) of the extended PHY
configuration area.
For the 82567 PHY, if the extended PHY configuration area is
disabled, the length must be set to 00h.
7:0
Reserved
00h
These bits are reserved and should be set to 00h.
Extended Configuration Word 3 (Word 16h)
Extended Configuration Word 3 (Word 16h)
Bit
15:0
14
Default
15
Bit
1.4.18
Name
Name
Reserved
Default
00h
Description
These bits are reserved and should be set to 00h.
ICH9M/82567LF/LM/V—NVM Information Guide
1.4.19
LED 1 Configuration and Power Management (Word 17h)
This field specifies the default values for the LEDCTL register fields controlling the LED1
(LINK_1000) output behaviors and the OEM fields defining the PHY power management
parameters loaded to the PHY_CTRL register.
Table 15.
LED 1 Configuration and Power Management (Word 17h)
Bit
15
Name
Reserved
Default
Description
1b
Reserved
When this bit is set, GbE operation is disabled in all power states
(including D0a).
0b = GbE enabled.
1b = GbE disabled.
14
GbE Disable
0b
13:12
Reserved
00b
These bits are reserved and should be set to 000b.
1b
This bit disables GbE operation in non-D0a states. This bit must be
set since GbE is not supported in Sx mode by the platform.
0b = GbE enabled.
1b = GbE disabled.
1b
The Low Power Link Up enables link at the lowest speed supported
by both link partners in non-D0a states. This bit must be set if
LPLU Enable bit is set.
0b = Low Power Link Up is disabled.
1b = Low Power Link Up is enabled in all non-D0a states.
The Low Power Link Up enables link at the lowest speed supported
by both link partners in all power states. This bit enables a
decrease in link speed in all power states.
0b = Low Power Link Up is disabled.
1b = Low Power Link Up is enabled in all power states.
11
GbE Disable in nonD0a
10
LPLU Enable in nonD0a
9
LPLU Enable
0b
8
Reserved
1b
Reserved.
7
LED1 Blink
0b
This bit indicates the initial value of the LED1_BLINK field.
0b = LED1 is non-blinking (recommended).
1b = LED1 is blinking.
6
LED1 Invert
0b
This bit indicates the initial value of the LED1_IVRT field.
0b = LED1 has an active low output.
1b = LED1 has an active high output.
5
LED1 Blink Mode
0b
This bit defines the LED1 blink mode:
0b = Slow rate.
1b = Fast rate.
This field should be identical to LED0 Blink Mode.
4
Reserved
0b
Reserved
0111b
These bits represent the initial value of the LED1_MODE field,
which specifies the event, state, or pattern displayed on LED1
(LINK_1000) output. Table 16 defines the values for LED1 Mode.
A value of 0111b indicates that a 1000 Mb/s link is established and
maintained.
3:0
LED1 Mode
The following table lists the LED modes defined in bits 3:0 of this word.
15
NVM Information Guide—ICH9M/82567LF/LM/V
Table 16.
16
LED Modes
Mode (Bits
3:0)
Selected Mode
Source Indication
0000b
LINK_10/1000
Asserted when either 10 Mb/s or 1000 Mb/s link is established
and maintained.
0001b
LINK_100/1000
0010b
LINK-UP
0011b
FILTER_ACTIVITY
Asserted when link is established and packets are being
transmitted or received that passed MAC filtering.
0100b
LINK/ACTIVITY
Asserted when link is established and when there is no
transmit or receive activity.
0101b
LINK_10
Asserted when either 100 Mb/s or 1000 Mb/s link is
established and maintained.
Asserted when any speed link is established and maintained.
Asserted when a 10 Mb/s link is established and maintained.
0110b
LINK_100
Asserted when a 100 Mb/s link is established and maintained.
0111b
LINK_1000
Asserted when a 1000 Mb/s link is established and maintained.
1000b
Reserved
1001b
FULL_DUPLEX
1010b
COLLISION
1011b
ACTIVITY
1100b
BUS_SIZE
1101b
PAUSED
Reserved.
Asserted when the link is configured for full duplex operation.
Asserted when a collision is observed.
Asserted when link is established and packets are being
transmitted or received.
Asserted when the MAC detects a 1-lane PCIe* connection.
Asserted when the MAC transmitter is flow controlled.
1110b
LED_ON
Always asserted.
1111b
LED_OFF
Always de-asserted.
ICH9M/82567LF/LM/V—NVM Information Guide
1.4.20
LED 0 and 2 Configuration Defaults (Word 18h)
This NVM word specifies the hardware defaults for the LEDCTL register fields controlling
the LED0 (LINK/ACTIVITY) and LED2 (LINK_100) output behaviors.
Table 17.
LED 0 and 2 Configuration Defaults (Word 18h)
Bit
Name
Default
Description
15
LED2 Blink
0b
This bit indicates the initial value of the LED2_BLINK field.
0b = LED2 is non-blinking.
1b = LED2 is blinking.
14
LED2 Invert
0b
This bit indicates the initial value of the LED2_IVRT field.
0b = LED2 has an active low output.
1b = LED2 has an active high output.
13
LED2 Blink Mode
0b
This bit defines the LED2 blink mode:
0b = Slow rate.
1b = Fast rate.
12
Reserved
0b
This bit is reserved and should be set to 0b.
11:8
LED2 Mode
0110b
These bits represent the initial value of the LED2_MODE field,
which specifies the event, state, or pattern displayed on LED2
(LINK_100) output. A value of 0110b causes this to indicate 100
Mb/s operation.
7
LED0 Blink
1b
This bit indicates the initial value of the LED0_BLINK field.
0b = LED0 is non-blinking (recommended).
1b = LED0 is blinking.
6
LED0 Invert
0b
This bit indicates the initial value of the LED0_IVRT field.
0b = LED0 has an active low output.
1b = LED0 has an active high output.
5
LED0 Blink Mode
0b
This bit define the LED0 blink mode:
0b = Slow rate.
1b = Fast rate.
4
Reserved
0b
This bit is reserved and should be set to 0b.
3:0
LED0 Mode
0100b
These bits represent the initial value of the LED0_MODE field,
which specifies the event, state, or pattern displayed on LED0
(LINK_UP/Activity) output. Table 16 defines the values for LED0
Mode.
Table 16, “LED Modes” lists the LED modes defined in bits 3:0 of this word.
17
NVM Information Guide—ICH9M/82567LF/LM/V
1.4.21
Reserved Word 19h
Bit
15:0
1.4.22
15:0
15:0
15:0
15:0
15:0
0043h
Description
Reserved
Name
Reserved
Default
00h
Description
These bits are reserved and should be set to 00h.
Name
Reserved
Default
10F5h
Description
These bits are reserved and should be set to 10F5h.
Name
Reserved
Default
BAADh
Description
These bits are reserved and should be set to BAADh.
Name
DeviceID
Default
10F5h
Description
Device ID on PCI configuration space when the PHY is the
82567LM.
Device ID (Word 1Fh)
Bit
15:0
18
Reserved
Default
Device ID (Word 1Eh)
Bit
1.4.27
Name
Reserved Word 1Dh
Bit
1.4.26
Reserved
Reserved Word 1Ch
Bit
1.4.25
2B00h
Description
Reserved Word 1Bh
Bit
1.4.24
Reserved
Default
Reserved Word 1Ah
Bit
1.4.23
Name
Name
DeviceID
Default
10BFh
Description
Device ID on PCI configuration space when the PHY is the
82567LF.
ICH9M/82567LF/LM/V—NVM Information Guide
1.4.28
Reserved Words 20h, 22h, and 23h
Bit
15:0
1.4.29
Name
Reserved
15:0
These bits are reserved and should be set to BAADh.
Name
DeviceID
Default
Description
Device ID on PCI configuration space when the PHY is the
82567V.
10CBh
Reserved Words 24h - 2Fh
Bit
15:0
1.4.31
BAADh
Description
Device ID (Word 21h)
Bit
1.4.30
Default
Name
Reserved
Default
00h
Description
These bits are reserved and should be set to 00h.
PXE Words (Words 30h - 3Eh)
Words 30h through 3Eh (bytes 60h through 7Dh) have been reserved for configuration
and version values to be used by PXE code.
1.4.31.1
Boot Agent Main Setup Options (Word 30h)
The boot agent software configuration is controlled by the NVM with the main setup
options stored in word 30h. These options are those that can be changed by using the
Control-S setup menu or by using the IBA Intel® Boot Agent Utility (IBAUTIL). Note
that these settings only apply to Boot Agent software.
19
NVM Information Guide—ICH9M/82567LF/LM/V
Table 18.
Boot Agent Main Setup Options
Bit
Description
PPB
PXE Presence.
Setting this bit to 0b Indicates that the image in the Flash contains a
PXE image.
Setting this bit to 1b indicates that no PXE image is contained.
The default for this bit is 0b for backwards compatibility with existing
systems already in the field.
If this bit is set to 0b, EEPROM word 32h (PXE Version) is valid. When
EPB is set to 1b and this bit is set to 0b, indicates that both images are
present in the Flash.
14
EPB
EFI Presence.
Setting this bit to 1b Indicates that the image in the Flash contains an
EFI image.
Setting this bit to 0b indicates that no EFI image is contained.
The default for this bit is 0b for backwards compatibility with existing
systems already in the field.
If this bit is set to 1b, EEPROM word 33h (EFI Version) is valid. When
PPB is set to 0b and this bit is set to 1b, indicates that both images
(PXE and EFI) are present in the Flash.
13
Reserved
Reserved for future use. This bit must be set to 0b.
12
FDP
Force Full Duplex.
Set this bit to 0b for half duplex and 1b for full duplex.
Note that this bit is a don’t care unless bits 10 and 11 are set.
11:10
FSP
Force Speed.
These bits determine speed.
01b = 10 Mb/s
10b = 100 Mb/s
11b = Not allowed.
All zeros indicate auto-negotiate (the current bit state).
Note that bit 12 is a don’t care unless these bits are set.
9
Reserved
Reserved
Set this bit to 0b.
8
DSM
Display Setup Message.
If this bit is set to 1b, the "Press Control-S" message appears after the
title message.
The default for this bit is 1b.
7:6
PT
Prompt Time. These bits control how long the "Press Control-S" setup
prompt message appears, if enabled by DIM.
00b = 2 seconds (default)
01b = 3 seconds
10b = 5 seconds
11b = 0 seconds
Note that the Ctrl-S message does not appear if 0 seconds prompt time
is selected.
5
Reserved
Reserved
15
20
Name
ICH9M/82567LF/LM/V—NVM Information Guide
Bit
1.4.31.2
Name
Description
4:3
DBS
Default Boot Selection. These bits select which device is the default
boot device. These bits are only used if the agent detects that the BIOS
does not support boot order selection or if the MODE field of word 31h
is set to MODE_LEGACY.
00b = Network boot, then local boot
01b = Local boot, then network boot
10b = Network boot only
11b = Local boot only
2
Reserved
Reserved
1:0
PS
Protocol Select. These bits select the boot protocol.
00b = PXE (default value).
01b = Reserved.
Other values are undefined.
Boot Agent Configuration Customization Options (Word 31h)
Word 31h contains settings that can be programmed by an OEM or network
administrator to customize the operation of the software. These settings cannot be
changed from within the Control-S setup menu or the IBA Intel® Boot Agent utility. The
lower byte contains settings that would typically be configured by a network
administrator using the Intel® Boot Agent utility; these settings generally control which
setup menu options are changeable. The upper byte are generally settings that would
be used by an OEM to control the operation of the agent in a LOM environment,
although there is nothing in the agent to prevent their use on a NIC implementation.
Table 19.
Boot Agent Configuration Customization Options (Word 31h)
Bit
Name
Description
15:14
SIG
Signature. These bits must be set to 01b to indicate that this word has
been programmed by the agent or other configuration software.
13:11
Reserved
Reserved for future use. All bits must be set to 0b.
MODE
Selects the agent's boot order setup mode. This field changes the
agent's default behavior in order to make it compatible with systems
that do not completely support the BBS and PnP Expansion ROM
standards. Valid values and their meanings are:
000b = Normal behavior. The agent attempts to detect BBS and PnP
Expansion ROM support as it normally does.
001b = Force Legacy mode. The agent does not attempt to detect BBS
or PnP Expansion ROM supports in the BIOS and assumes the BIOS is
not compliant. The BIOS boot order can be changed in the Setup Menu.
010b = Force BBS mode. The agent assumes the BIOS is BBScompliant, even though it may not be detected as such by the agent's
detection code. The BIOS boot order CANNOT be changed in the Setup
Menu.
011b = Force PnP Int18 mode. The agent assumes the BIOS allows
boot order setup for PnP Expansion ROMs and hooks interrupt 18h (to
inform the BIOS that the agent is a bootable device) in addition to
registering as a BBS IPL device. The BIOS boot order CANNOT be
changed in the Setup Menu.
100b = Force PnP Int19 mode. The agent assumes the BIOS allows
boot order setup for PnP Expansion ROMs and hooks interrupt 19h (to
inform the BIOS that the agent is a bootable device) in addition to
registering as a BBS IPL device. The BIOS boot order CANNOT be
changed in the Setup Menu.
101b = Reserved for future use. If specified, treated as value 000b.
110b = Reserved for future use. If specified, treated as value 000b.
111b = Reserved for future use. If specified, treated as value 000b.
10:8
21
NVM Information Guide—ICH9M/82567LF/LM/V
Bit
7:6
Description
Reserved
Reserved for future use. These bits must be set to 0b.
DFU
Disable Flash Update.
If set to 1b, no updates to the Flash image using PROSet is allowed.
The default for this bit is 0b; allow Flash image updates using PROSet.
4
DLWS
Disable Legacy Wakeup Support.
If set to 1b, no changes to the Legacy OS Wakeup Support menu
option is allowed.
The default for this bit is 0b; allow Legacy OS Wakeup Support menu
option changes.
3
DBS
Disable Boot Selection.
If set to 1b, no changes to the boot order menu option is allowed.
The default for this bit is 0b; allow boot order menu option changes.
2
DPS
Disable Protocol Select.
If set to 1b, no changes to the boot protocol is allowed.
The default for this bit is 0b; allow changes to the boot protocol.
DTM
Disable Title Message.
If set to 1b, the title message displaying the version of the boot agent
is suppressed; the Control-S message is also suppressed. This is for
OEMs who do not want the boot agent to display any messages at
system boot.
The default for this bit is 0b; allow the title message that displays the
version of the boot agent and the Control-S message.
DSM
Disable Setup Menu.
If set to 1b, no invoking the setup menu by pressing Control-S is
allowed. In this case, the EEPROM can only be changed via an external
program.
The default for this bit is 0b; allow invoking the setup menu by
pressing Control-S.
5
1
0
1.4.31.3
Name
Boot Agent Configuration Customization Options (Word 32h)
Word 32h is used to store the version of the boot agent that is stored in the Flash
image. When the Boot Agent loads, it can check this value to determine if any first-time
configuration needs to be performed. The agent then updates this word with its
version. Some diagnostic tools to report the version of the Boot Agent in the Flash also
read this word. The contents of this word might be undefined until IBA is enabled, after
which the word is updated the next time it runs (if its incorrect).
Table 20.
Boot Agent Configuration Customization Options (Word 32h)
Bit
22
Name
Description
15:12
MAJOR
PXE boot agent major version. The default for these bits is 1111b.
11:8
MINOR
PXE boot agent minor version. The default for these bits is 0010b.
7:0
BUILD
PXE boot agent build number. The default for these bits is 00101000b.
ICH9M/82567LF/LM/V—NVM Information Guide
1.4.31.4
IBA Capabilities (Word 33h)
Word 33h is used to enumerate the boot technologies that have been programmed into
the Flash. It is updated by IBA configuration tools and is not updated or read by IBA.
Table 21.
IBA Capabilities
Bit
1.4.32
Name
Description
15:14
SIG
Signature. These bits must be set to 01b to indicate that this word has
been programmed by the agent or other configuration software.
13:4
Reserved
Reserved for future use. All bits must be set to 00h.
3
EFI
EFI UNDI capability is present in Flash.
0b = The EFI code is not present (default).
1b = The EFI code is present.
2
Reserved
Reserved. Must be set to 1b.
1
UNDI
PXE/UNDI capability is present in Flash.
1b = The PXE base code is present (default).
0b = The PXE base code is not present.
0
BC
PXE base code is present in Flash.
0b = The PXE base code is present.
1b = The PXE base code is not present (default).
Checksum (Word 3Fh)
The Checksum word (NVM bytes 7Eh and 7Fh) is used to ensure that the base NVM
image is valid. Its value should be calculated by adding all words (00h through 3Fh)/
bytes (00h-7Eh), including the Checksum word itself. The sum, including the
Checksum, should equal BABAh. The initial value before the values are added together
should be 0000h, and the carry bit should be ignored after each addition. If the OEM
does not desire to calculate the checksum, LAD programming tools and drivers will
detect if the checksum is incorrect and fix it in the image.
Note:
The default image always has a checksum value of FFFFh. The LAD programming tools
(EEUPDATE or LANCONF) update the checksum when the image is programmed.
23
NVM Information Guide—ICH9M/82567LF/LM/V
Appendix A ICH9M NVM Contents and Sample Images
This section contains a sample of raw NVM contents for the ICH9M. All values for these
images are hexadecimal.
Table 22.
LAN NVM Contents
Word
24
Description
00h:02h
Ethernet Individual Address
03h:04h
Reserved
05h
Image Version Information 1
06h:07h
Reserved
08h:09h
PBA Bytes
0Ah
PCI Initialization Control Word
0Bh
Subsystem ID
0Ch
Subsystem Vendor ID
0Dh
Device ID
0Eh
Vendor ID
0Fh
Device Revision ID
10h
LAN Power Consumption
11h:12h
Reserved
13h
Shared Initialization Control Word
14h:16h
Extended Configuration Words
17h:18h
LEDCTRL Words
19h:1Bh
Reserved
1Ch
82567LM Device ID
1Dh
Reserved
1Eh
82567LM Device ID
1Fh
82567LF Device ID
20h
Reserved
21h
82567V Device ID
22h:23h
Reserved
24:2Fh
Reserved
30h:3Eh
PXE Region
3Fh
Software Checksum
ICH9M/82567LF/LM/V—NVM Information Guide
A.1
82567LF/LM/V NVM Image with ICH9M
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
8888 8888 8887 0800 FFFF 1083 FFFF FFFF
FFFF FFFF 10C3 0000 8086 10F5 8086 0000
0D01 0000 0000 8605 3020 0A00 0000 8D07
0684 2B00 0043 0000 10F5 BAAD 10F5 10BF
BAAD 10CB BAAD BAAD 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0100 4000 1228 4007 FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
;
;-----------Range [0x40-0x7F]---------6020 001F 0002 0013 8000 001D 00FF 0016
CCDD 0018 2011 0017 DDDD 0018 2012 0017
8000 001D 0000 001F FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
;
;-----------Range [0x80-0xBF]---------FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
;
25
NVM Information Guide—ICH9M/82567LF/LM/V
Note:
26
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