DAC712 16-BIT DIGITAL-TO-ANALOG CONVERTER With 16

DAC712 16-BIT DIGITAL-TO-ANALOG CONVERTER With 16
®
DAC712
DAC
712
DAC
712
16-BIT DIGITAL-TO-ANALOG CONVERTER
With 16-Bit Bus Interface
FEATURES
DESCRIPTION
● HIGH-SPEED 16-BIT PARALLEL DOUBLEBUFFERED INTERFACE
DAC712 is a complete 16-bit resolution D/A converter
with 16 bits of monotonicity over temperature.
● VOLTAGE OUTPUT: ±10V
● 13-, 14-, AND 15-BIT LINEARITY GRADES
DAC712 has a precision +10V temperature compensated voltage reference, ±10V output amplifier and
16-bit port bus interface.
● 16-BIT MONOTONIC OVER
TEMPERATURE (L GRADE)
● POWER DISSIPATION: 600mW max
The digital interface is fast, 60ns minimum write pulse
width, is double-buffered and has a CLEAR function
that resets the analog output to bipolar zero.
● GAIN AND OFFSET ADJUST: Convenient
for Auto-Cal D/A Converters
● 28-LEAD DIP AND SOIC PACKAGES
GAIN and OFFSET adjustment inputs are arranged so
that they can be easily trimmed by external D/A
converters as well as by potentiometers.
DAC712 is available in two linearity error performance grades: ±4LSB and ±2LSB and three differential linearity grades: ±4LSB, ±2LSB, and ±1LSB. The
DAC712 is specified at power supply voltages of
±12V and ±15V.
DB0
DB15
A1
Input Latch
A0
16
DAC712 is packaged in a 28-pin 0.3" wide plastic DIP
and in a 28-lead wide-body plastic SOIC. The
DAC712P, U, PB, UB, are specified over the –40°C to
+85°C temperature range and the DAC712PK, UK,
PL, UL are specified over the 0°C to +70°C range.
WR
CLR
D/A Latch
16
Reference
Circuit
Gain Adjust
16-Bit D/A Converter
VOUT
VREF OUT
+10V
Bipolar Offset Adjust
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1994 Burr-Brown Corporation
PDS-1164G
Printed in U.S.A. May, 1998
SPECIFICATIONS
ELECTRICAL
At TA = 25°C, +VCC = +12V and +15V, –VCC = –12V and –15V, unless otherwise noted.
DAC712P, U
PARAMETER
MIN
TYP
DAC712PB, UB
MAX
MIN
TYP
MAX
UNITS
INPUT
16
✻
Binary Two’s Complement
✻
RESOLUTION
DIGITAL INPUTS
Input Code
Logic Levels(1)
VIH
VIL
IIH (VI = +2.7V)
IIL (VI = +0.4V)
+2.0
0
+VCC – 1.4
+0.8
±10
±10
✻
✻
Bits
✻
✻
✻
✻
V
V
µA
µA
±2
±4
±2
±4
LSB
LSB
LSB
LSB
Bits
%
%
% FSR(2)
mV
% FSR
mV
% FSR/% VCC
ppm FSR/% VCC
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error
TMIN to TMAX
Differential Linearity Error
TMIN to TMAX
Monotonicity Over Temp
Gain Error(3)
TMIN to TMAX
Bipolar Zero Error(3)
±4
±8
±4
±8
13
14
±0.1
±0.2
±0.1
±20
±0.2
±40
±0.003
±30
TMIN to TMAX
Power Supply Sensitivity Of Full Scale:
DYNAMIC PERFORMANCE
Settling Time (to ±0.003%FSR, 5kΩ || 500pF Load)(4)
20V Output Step
1 LSB Output Step(5)
Output Slew Rate
Total Harmonic Distortion + Noise
0dB, 1001Hz, fS = 100kHz
–20dB, 1001Hz, fS = 100kHz
–60dB, 1001Hz, fS = 100kHz
SINAD
1001Hz, fS = 100kHz
Digital Feedthrough(5)
Digital-to-Analog Glitch Impulse(5)
Output Noise Voltage (Includes Reference)
ANALOG OUTPUT
Output Voltage Range
+VCC, –VCC = ±11.4V
Output Current
Output Impedance
Short Circuit to ACOM, Duration
REFERENCE VOLTAGE
Voltage
TMIN to TMAX
Output Resistance
Source Current
Short Circuit to ACOM, Duration
±0.1
±0.15
✻
✻
±0.15
±30
✻
✻
✻
✻
✻
0.005
0.03
3.0
✻
✻
✻
%
%
%
87
2
15
120
✻
✻
✻
✻
dB
nV-s
nV-s
nV/√Hz
±10
±5
10
✻
✻
+10.000
V
mA
Ω
✻
✻
0.1
Indefinite
+9.975
+9.960
µs
µs
V/µs
6
4
10
+10.025
+10.040
✻
✻
✻
✻
✻
V
V
Ω
mA
✻
✻
✻
✻
V
V
✻
✻
✻
✻
✻
✻
mA
mA
mW
✻
✻
°C
°C
✻
1
✻
2
✻
Indefinite
POWER SUPPLY REQUIREMENTS
Voltage: +VCC
–VCC
Current (No Load, ±15V Supplies)
+VCC
–VCC
Power Dissipation(6)
TEMPERATURE RANGES
Specification
All Grades
Storage
Thermal Coefficient θJA
DIP Package
SOIC Package
+11.4
–11.4
+15
–15
+16.5
–16.5
13
22
525
15
25
600
–40
–60
+85
+150
✻
✻
✻
✻
✻
✻
75
75
°C/W
°C/W
✻ Specifications are the same as grade to the left.
NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for a ±10V
output, FSR = 20V. (3) Errors externally adjustable to zero. (4) Maximum represents the 3σ limit. Not 100% tested for this parameter. (5) For the worst case code changes:
FFFFHEX to 0000HEX and 0000HEX to FFFFHEX. These are Binary Two’s Complement (BTC) codes. (6) Typical supply voltages times maximum currents.
®
DAC712
2
SPECIFICATIONS
ELECTRICAL
At TA = +25°C, +VCC = +12V and +15V, –VCC = –12V and –15V, unless otherwise noted.
DAC712PK, UK
PARAMETER
MIN
TYP
DAC712PL, UL
MAX
MIN
TYP
MAX
UNITS
INPUT
16
✻
Binary Two’s Complement
✻
RESOLUTION
DIGITAL INPUTS
Input Code
Logic Levels(1)
VIH
VIL
IIH (VI = +2.7V)
IIL (VI = +0.4V)
+2.0
0
+VCC – 1.4
+0.8
±10
±10
✻
✻
Bits
✻
✻
✻
✻
V
V
µA
µA
±2
±2
±1
±1
LSB
LSB
LSB
LSB
Bits
%
%
% FSR(2)
mV
% FSR
mV
%FSR/% VCC
ppm FSR/% VCC
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error
TMIN to TMAX
Differential Linearity Error
TMIN to TMAX
Monotonicity Over Temp
Gain Error(3)
TMIN to TMAX
Bipolar Zero Error(3)
±2
±2
±2
±2
15
16
±0.1
±0.15
±0.1
±20
±0.15
±30
±0.003
±30
TMIN to TMAX
Power Supply Sensitivity of Full Scale
DYNAMIC PERFORMANCE
Settling Time (to ±0.003%FSR, 5kΩ || 500pF Load)(4)
20V Output Step
1LSB Output Step(5)
Output Slew Rate
Total Harmonic Distortion + Noise
0dB, 1001Hz, fS = 100kHz
–20dB, 1001Hz, fS = 100kHz
–60dB, 1001Hz, fS = 100kHz
SINAD
1001Hz, fS = 100kHz
Digital Feedthrough(5)
Digital-to-Analog Glitch Impulse(5)
Output Noise Voltage (includes reference)
ANALOG OUTPUT
Output Voltage Range
+VCC, –VCC = ±11.4V
Output Current
Output Impedance
Short Circuit to ACOM, Duration
REFERENCE VOLTAGE
Voltage
TMIN to TMAX
Output Resistance
Source Current
Short Circuit to ACOM, Duration
POWER SUPPLY REQUIREMENTS
Voltage: +VCC
–VCC
Current (No Load, ±15V Supplies)
+VCC
–VCC
Power Dissipation(6)
TEMPERATURE RANGES
Specification
All Grades
Storage
Thermal Coefficient, θJA
DIP Package
SOIC Package
6
4
10
✻
±0.02
✻
✻
±0.15
✻
✻
✻
✻
✻
✻
10
✻
✻
✻
%
%
%
87
2
15
120
✻
✻
✻
✻
dB
nV–s
nV–s
nV/√Hz
✻
✻
+10.000
V
mA
Ω
✻
✻
0.1
Indefinite
+10.025
+10.040
✻
✻
✻
✻
✻
V
V
Ω
mA
✻
✻
✻
✻
V
V
✻
✻
✻
✻
✻
mA
mA
mW
✻
✻
°C
°C
✻
1
✻
2
✻
Indefinite
+11.4
–11.4
µs
µs
V/µs
0.005
0.03
3.0
±10
±5
+9.975
+9.960
10
+15
–15
+16.5
–16.5
13
22
525
15
25
600
0
–60
+70
+150
75
75
✻
✻
✻
✻
°C/W
°C/W
✻
✻
✻ Same specification as grade to the left.
NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for a ±10V
output, FSR = 20V. (3) Errors externally adjustable to zero. (4) Maximum represents the 3σ limit. Not 100% tested for this parameter. (5) For the worst case code changes:
FFFFHEX to 0000HEX and 0000HEX to FFFFHEX. These are Binary Two’s Complement (BTC) codes. (6) Typical supply voltages times maximum currents.
®
3
DAC712
ABSOLUTE MAXIMUM RATINGS
TIMING DIAGRAM
+VCC to COMMON ...................................................................... 0V, +17V
–VCC to COMMON ...................................................................... 0V, –17V
+VCC to –VCC ........................................................................................ 34V
Digital Inputs to COMMON .......................................... –1V to +VCC –0.7V
External Voltage Applied to BPO and Range Resistors ..................... ±VCC
VREF OUT ...................................................... Indefinite Short to COMMON
VOUT ............................................................ Indefinite Short to COMMON
Power Dissipation .......................................................................... 750mW
Storage Temperature ...................................................... –60°C to +150°C
Lead Temperature (soldering, 10s) ................................................ +300°C
tAW
tAH
A0, A1
tDW
D0-D15
tDH
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
WR
tWP
PACKAGE INFORMATION
TIMING SPECIFICATIONS
PRODUCT
PACKAGE
PACKAGE DRAWING
NUMBER(1)
DAC712P
DAC712U
DAC712PB
DAC712UB
DAC712PK
DAC712UK
DAC712PL
DAC712UL
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
246
217
246
217
246
217
246
217
TA = –40°C to +85°C, +VCC = +12V or +15V, –VCC = –12V or –15V.
SYMBOL
tDW
tAW
tAH
tDH
tWP(1)
tCP
PARAMETER
MIN
Data Valid to End of WR
A0, A1 Valid to End of WR
A0, A1 Hold after End of WR
Data Hold after end of WR
Write Pulse Width
CLEAR Pulse Width
50
50
10
10
50
200
MAX
UNITS
ns
ns
ns
ns
ns
ns
NOTES: (1) For single-buffered operation, tWP is 80ns min. Refer to page 10.
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
TRUTH TABLE
ORDERING INFORMATION
PRODUCT
TEMPERATURE
RANGE
LINEARITY
ERROR MAX
at +25°C
DIFFERENTIAL
LINEARITY ERROR
MAX at +25°C
DAC712P
DAC712U
DAC712PB
DAC712UB
DAC712PK
DAC712UK
DAC712PL
DAC712UL
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
±4LSB
±4LSB
±2LSB
±2LSB
±2LSB
±2LSB
±2LSB
±2LSB
±4LSB
±4LSB
±2LSB
±2LSB
±2LSB
±2LSB
±1LSB
±1LSB
A0
A1
WR
CLR
DESCRIPTION
0
1
1
0
X
X
1
0
1
0
X
X
1→0→1
1→0→1
1→0→1
0
1
X
1
1
1
1
1
0
Load Input Latch
Load D/A Latch
No Change
Latches Transparent
No Change
Reset D/A Latch
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published specifications.
®
DAC712
4
PIN CONFIGURATION
PIN DESCRIPTIONS
DCOM
1
28
LSB D0
ACOM
2
27
D1
VOUT
3
26
D2
Offset Adjust
4
25
D3
VREF OUT
5
24
D4
Gain Adjust
6
23
D5
+VCC
7
22
D6
–VCC
8
21
D7
CLR
9
20
D8
WR
10
19
D9
A1
11
18
D10
A0
12
17
D11
D15 MSB
13
16
D12
D14
14
15
D13
DAC712
PIN
LABEL
1
2
3
4
5
6
7
8
9
DCOM
ACOM
VOUT
Off Adj
VREF OUT
Gain Adj
+VCC
–VCC
CLR
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
WR
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
Power Supply return for digital currents.
Analog Supply Return.
±10V D/A Output.
Offset Adjust (Bipolar).
Voltage Reference Output.
Gain Adjust.
+12V to +15V Supply.
–12V to –15V Supply.
CLEAR. Sets D/A output to BIPOLAR ZERO
(Active Low).
Write (Active Low).
Enable for D/A latch (Active Low).
Enable for Input latch (Active Low).
Data Bit 15 (Most Significant Bit).
Data Bit 14.
Data Bit 13.
Data Bit 12.
Data Bit 11.
Data Bit 10.
Data Bit 9.
Data Bit 8.
Data Bit 7.
Data Bit 6.
Data Bit 5.
Data Bit 4.
Data Bit 3.
Data Bit 2.
Data Bit 1.
Data Bit 0 (Least Significant Bit).
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
5
DAC712
TYPICAL PERFORMANCE CURVES
POWER SUPPLY REJECTION vs
POWER SUPPLY RIPPLE FREQUENCY
LOGIC vs V LEVEL
1k
2.0
–VCC
100
I Digital Input (µA)
[Change in FSR]/[Change in Supply Voltage]
(ppm of FSR/ %)
At TA = +25°C, VCC = ±15V, unless otherwise noted.
+VCC
10
1
100
1k
10k
100k
WR, A0, A1
CLR
0
DATA
–1.0
–2.0
–0.85
0.1
10
1.0
1M
0
0.85 1.7 2.55
3.4 4.25
5.1 5.95
6.8
V Digital Input
Frequency (Hz)
± FULL SCALE OUTPUT SWING
SETTLING TIME, +10V TO –10V
∆ Around –10V (µV)
VOUT (V)
10
0
2000
+5V
1500
0V
1000
500
0
–500
–1000
–1500
–10
–2000
–2500
Time (10µs/div)
Time (1µs/div)
SETTLING TIME, –10V TO +10V
Spectral Noise Density
1000
+5V
1500
–0V
WR
2000
1000
100
nV/√Hz
∆ Around +10V (µV)
2500
500
0
–500
10
–1000
–1500
–2000
1
–2500
1
Time (1µs/div)
10
100
1k
10k
Frequency (Hz)
®
DAC712
6
100k
1M
10M
WR (V)
2500
DISCUSSION OF
SPECIFICATIONS
DIGITAL FEEDTHROUGH
When the A/D is not selected, high frequency logic activity
on the digital inputs is coupled through the device and shows
up as output noise. This noise is digital feedthrough.
LINEARITY ERROR
Linearity error is defined as the deviation of the analog
output from a straight line drawn between the end points of
the transfer characteristic.
OPERATION
DIFFERENTIAL LINEARITY ERROR
DAC712 is a monolithic integrated-circuit 16-bit D/A converter complete with 16-bit D/A switches and ladder network, voltage reference, output amplifier and microprocessor bus interface.
Differential linearity error (DLE) is the deviation from
1LSB of an output change from one adjacent state to the
next. A DLE specification of ±1/2LSB means that the output
step size can range from 1/2LSB to 3/2LSB when the digital
input code changes from one code word to the adjacent code
word. If the DLE is more positive than –1LSB, the D/A is
said to be monotonic.
INTERFACE LOGIC
DAC712 has double-buffered data latches. The input data
latch holds a 16-bit data word before loading it into the
second latch, the D/A latch. This double-buffered organization permits simultaneous update of several D/A converters.
All digital control inputs are active low. Refer to block
diagram of Figure 1.
MONOTONICITY
A D/A converter is monotonic if the output either increases
or remains the same for increasing digital input values.
Monotonicity of DAC712 is guaranteed over the specification temperature range to 13, 14, 15, and 16 bits for performance grades DAC712P/U, DAC712PB/UB, DAC712PK/
UK, and DAC712PL/UL respectively.
All latches are level-triggered. Data present when the enable
inputs are logic “0” will enter the latch. When the enable
inputs return to logic “1”, the data is latched.
The CLR input resets both the input latch and the D/A latch
to give a bipolar zero output.
SETTLING TIME
Settling time is the total time (including slew time) for the
D/A output to settle to within an error band around its final
value after a change in input. Settling times are specified to
within ±0.003% of Full Scale Range (FSR) for an output
step change of 20V and 1LSB. The 1LSB change is measured at the Major Carry (FFFFHEX to 0000HEX, and 0000HEX
to FFFFHEX: BTC codes), the input transition at which
worst-case settling time occurs.
LOGIC INPUT COMPATIBILITY
TOTAL HARMONIC DISTORTION + NOISE
Total harmonic distortion + noise is defined as the ratio of
the square root of the sum of the squares of the values of the
harmonics and noise to the value of the fundamental frequency. It is expressed in % of the fundamental frequency
amplitude at sampling rate fS.
Digital inputs remain high impedance when power is off.
DAC712 digital inputs are TTL compatible (1.4V switching
level) with low leakage, high impedance inputs. Thus the
inputs are suitable for being driven by any type of 5V logic
such as 5V CMOS logic. An equivalent circuit of a digital
input is shown in Figure 2.
Data inputs will float to logic “0” and control inputs will
float to logic “0” if left unconnected. It is recommended that
any unused inputs be connected to DCOM to improve noise
immunity.
INPUT CODING
DAC712 is designed to accept positive-true binary two’s
complement (BTC) input codes which are compatible with
bipolar analog output operation. For bipolar analog output
configuration, a digital input of 7FFFHEX gives a plus full
scale output, 8000HEX gives a minus full scale output, and
0000HEX gives bipolar zero output.
SIGNAL-TO-NOISE
AND DISTORTION RATIO (SINAD)
SINAD includes all the harmonic and outstanding spurious
components in the definition of output noise power in
addition to quantizing and internal random noise power.
SINAD is expressed in dB at a specified input frequency and
sampling rate, fS.
INTERNAL REFERENCE
DAC712 contains a +10V reference.
The reference output may be used to drive external loads,
sourcing up to 2mA. The load current should be constant,
otherwise the gain and bipolar offset of the converter will
vary.
DIGITAL-TO-ANALOG GLITCH IMPULSE
The amount of charge injected into the analog output from
the digital inputs when the inputs change state. It is measured at half scale at the input codes where as many as
possible switches change state—from 7FFFHEX to 8000HEX.
®
7
DAC712
Gain Adjust
VREF OUT
+VCC
– VCC
6
5
7
8
170Ω
+10V
Reference
15kΩ
250Ω
4
+2.5V
9750Ω
10kΩ
–VCC
Bipolar
Offset
Adjust
D/A Switches
CLR
9
A1
11
A0
12
WR
10
3
VOUT
16-Bit D/A Latch
16-Bit Input Latch
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
DB0
LSB
13
2
1
DB15 ACOM
MSB
DCOM
FIGURE 1. DAC712 Block Diagram.
+VCC
ESD Protection Circuit
Range of
Gain Adjust
≈ ±0.3%
+ Full Scale
R = 1k: A0, A1, WR, CLR
3k: D0...D15
1LSB
Digital
Input
6.8V
Analog Output
R
5pF
–VCC
FIGURE 2. Equivalent Circuit of Digital Inputs.
All Bits
Logic 0
Range of
Offset Adjust
OUTPUT VOLTAGE SWING
Offset Adj.
Translates
the Line
≈ ±0.3%
The output amplifier of DAC712 is committed to a ±10V
output range. DAC712 will provide a ±10V output swing
while operating on ±11.4V or higher voltage supplies.
Full Scale
Range
Bipolar
Offset
Gain Adjust
Rotates the Line
MSB on All
Others Off
All Bits
Logic 1
– Full Scale
Digital Input
FIGURE 3. Relationship of Offset and Gain Adjustments.
GAIN AND OFFSET ADJUSTMENTS
Figure 3 illustrates the relationship of offset and gain adjustments for a bipolar connected D/A converter. Offset should
be adjusted first to avoid interaction of adjustments. See
Table I for calibration values and codes. These adjustments
have a minimum range of ±0.3%.
Offset Adjustment
Apply the digital input code that produces the maximum
negative output voltage and adjust the offset potentiometer
or the offset adjust D/A converter for –10V.
®
DAC712
8
DAC712 CALIBRATION VALUES
1 LEAST SIGNIFICANT BIT = 305µV
DIGITAL INPUT CODE
BINARY TWO’S
COMPLEMENT, BTC
ANALOG
OUTPUT
(V)
DESCRIPTION
7FFFH
|
4000H
|
0001H
+9.999695
+ Full Scale –1LSB
+5.000000
3/4 Scale
+0.000305
BPZ + 1LSB
0000H
0.000000
Bipolar Zero (BPZ)
1
DCOM
28
2
ACOM
27
3
VOUT
26
4
5
25
VREF OUT
6
24
23
+12V to +15V
7
+VCC
22
8
–VCC
21
–12V to –15V
FFFFH
|
C000H
|
8000H
–0.000305
BPZ – 1LSB
0.01µF
–5.000000
1/4 Scale
–10.00000
Minus Full Scale
+
0.01µF
TABLE I. Digital Input and Analog Output Voltage Calibration Values.
Gain Adjustment
Apply the digital input that gives the maximum positive
voltage output. Adjust the gain potentiometer or the gain
adjust D/A converter for this positive full scale voltage.
+
9
20
10
19
11
18
12
17
13
16
14
15
FIGURE 4. Power Supply Connections.
critical settling time may be able to use 0.01µF at –VCC as
well as at +VCC. The capacitors should be located close to
the package.
DAC712 has separate ANALOG COMMON and DIGITAL
COMMON pins. The current through DCOM is mostly
switching transients and are up to 1mA peak in amplitude.
The current through ACOM is typically 5µA for all codes.
INSTALLATION
GENERAL CONSIDERATIONS
Due to the high-accuracy of these D/A converters, system
design problems such as grounding and contact resistance
become very important. A 16-bit converter with a 20V fullscale range has a 1LSB value of 305µV. With a load current
of 5mA, series wiring and connector resistance of only
60mΩ will cause a voltage drop of 300µV. To understand
what this means in terms of a system layout, the resistivity
of a typical 1 ounce copper-clad printed circuit board is 1/2
mΩ per square. For a 5mA load, a 10 milli-inch wide printed
circuit conductor 60 milli-inches long will result in a voltage
drop of 150µV.
Use separate analog and digital ground planes with a single
interconnection point to minimize ground loops. The analog
pins are located adjacent to each other to help isolate analog
from digital signals. Analog signals should be routed as far
as possible from digital signals and should cross them at
right angles. A solid analog ground plane around the D/A
package, as well as under it in the vicinity of the analog and
power supply pins, will isolate the D/A from switching
currents. It is recommended that DCOM and ACOM be
connected directly to the ground planes under the package.
The analog output of DAC712 has an LSB size of 305µV
(–96dB). The noise floor of the D/A must remain below this
level in the frequency range of interest. The DAC712’s noise
spectral density (which includes the noise contributed by the
internal reference,) is shown in the Typical Performance
Curves section.
If several DAC712s are used or if DAC712 shares supplies
with other components, connecting the ACOM and DCOM
lines to together once at the power supplies rather than at
each chip may give better results.
Wiring to high-resolution D/A converters should be routed
to provide optimum isolation from sources of RFI and EMI.
The key to elimination of RF radiation or pickup is small
loop area. Signal leads and their return conductors should be
kept close together such that they present a small capture
cross-section for any external field. Wire-wrap construction
is not recommended.
LOAD CONNECTIONS
Since the reference point for VOUT and VREF OUT is the
ACOM pin, it is important to connect the D/A converter load
directly to the ACOM pin. Refer to Figure 5.
Lead and contact resistances are represented by R1 through
R3. As long as the load resistance RL is constant, R1 simply
introduces a gain error and can be removed by gain adjustment of the D/A or system-wide gain calibration. R2 is part
of RL if the output voltage is sensed at ACOM.
POWER SUPPLY AND
REFERENCE CONNECTIONS
Power supply decoupling capacitors should be added as
shown in Figure 4. Best performance occurs using a 1 to
10µF tantalum capacitor at –VCC. Applications with less
In some applications it is impractical to return the load to the
ACOM pin of the D/A converter. Sensing the output voltage
at the SYSTEM GROUND point is reasonable, because
®
9
DAC712
Nominal values of GAIN and OFFSET occur when the D/A
converters outputs are at approximately half scale, +5V.
there is no change in DAC712 ACOM current, provided that
R3 is a low-resistance ground plane or conductor. In this case
you may wish to connect DCOM to SYSTEM GROUND as
well.
OUTPUT VOLTAGE RANGE CONNECTIONS
The DAC712 output amplifier is connected internally for the
±10V bipolar (20V) output range. That is, the bipolar offset
resistor is connected to an internal reference voltage and the
20V range resistor is connected internally to VOUT. DAC712
cannot be connected by the user for unipolar operation.
GAIN AND OFFSET ADJUST
Connections Using Potentiometers
GAIN and OFFSET adjust pins provide for trim using
external potentiometers. 15-turn potentiometers provide sufficient resolution. Range of adjustment of these trims is at
least ±0.3% of Full Scale Range. Refer to Figure 6.
DIGITAL INTERFACE
BUS INTERFACE
Using D/A Converters
The GAIN ADJUST and OFFSET ADJUST circuits of
DAC712 have been arranged so that these points may be
easily driven by external D/A converters. Refer to Figure 7.
12-bit D/A converters provide an OFFSET adjust resolution
and a GAIN adjust resolution of 30µV to 50µV per LSB
step.
DAC712 has 16-bit double-buffered data bus interface with
control lines for easy interface to interface to a 16-bit bus.
The double-buffered feature permits update of several D/As
simultaneously.
DAC712
10kΩ
10kΩ
VREF
VOUT R1
Bus
Interface
RL
DCOM
ACOM
R2
Alternate Ground
Sense Connection
R3
To +VCC
0.01µF(1)
0.01µF
System Ground
Analog
Power
Supply
To –VCC
NOTE: (1) Locate close to DAC712 package.
FIGURE 5. System Ground Considerations for High-Resolution D/A Converters.
®
DAC712
10
Sense
Output
A0 is the enable control for the DATA INPUT LATCH. A1
is the enable for the D/A LATCH. WR is used to strobe data
into latches enabled by A0, and A1. Refer to the block
diagram of Figure 1 and to Timing Diagram on page 3.
D/A, it should be connected to DCOM also. For this mode
of operation, the width of WR will need to be at least 80ns
minimum to pass data through the DATA INPUT LATCH
and into the D/A LATCH.
CLR sets the INPUT DATA LATCH to all zero and the
D/A LATCH to a code that gives bipolar 0V at the D/A
output.
TRANSPARENT INTERFACE
The digital interface of the DAC712 can be made transparent by asserting AO, A1, and WR LOW, and asserting CLR
HIGH.
SINGLE-BUFFERED OPERATION
To operate the DAC712 interface as a single-buffered latch,
the DATA INPUT LATCH is permanently enabled by
connecting A0 to DCOM. If A1 is not used to enable the
Internal
+10V Reference
VREF OUT
5
R2
500Ω
R1
500Ω
170Ω
250Ω
120Ω
180Ω
Gain Adjust
6
Bipolar Offset Adjust
4
15kΩ
9.75kΩ
10kΩ
R3
27kΩ
R4
10kΩ
≈ +2.5V
3
IDAC
0-2mA
2
±10V VOUT
ACOM
For no external adjustments, pins 4 and 6 are not connected.
External resistors R1 - R4 are standard ±1% values. Range of
adjustment at least ±0.3% FSR.
FIGURE 6. Manual Offset and Gain Adjust Circuits.
®
11
DAC712
Internal
+10V Reference
VREF OUT
5
10kΩ
+10V
170Ω
R1
340Ω
250Ω
R2
500Ω
10kΩ
Gain Adjust
–10V
6
Bipolar Offset Adjust
5kΩ
4
15kΩ
Suggested Op Amps
OPA177GP, GS or
OPA604AP, AU
9.75kΩ
R3
20kΩ
10kΩ
R4
10kΩ
RFB VREF A
0 to 10V
IDAC
0-2mA
Suggested Op Amps
OPA177GP, GS: Single or
OPA2604AP, AU: Dual
3
±10V VOUT
0 to +10V
DAC712
RFB VREF B
For no external adjustments, pins 4 and 6 are not connected.
External resistors R1 - R4 tolerance: ±1%. Range of adjustment at
least ±0.3% FSR.
Suggested D/As
CMOS
DAC7800: Dual: Serial Input, 12-bit Resolution
DAC7801: Dual: 8-bit Port Input, 12-bit Resolution
DAC7802: Dual: 12-bit Port Input, 12-bit Resolution
DAC7528: Dual: 8-bit Port Input, 8-bit Resolution
DAC7545: Dual: 12-bit Port Input, 12-bit Resolution
DAC8043: Single: Serial Input, 12-bit Resolution
BIPOLAR (complete)
DAC813 (Use 11-bit resolution for 0V to +10V output. No op amps required).
FIGURE 7. Gain and Offset Adjustment Using D/A Converters.
®
DAC712
12
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