RT8208E/F

RT8208E/F
RT8208E/F
Programmable Output Voltage Single Synchronous
Buck Controller
General Description
Features
The RT8208E/F is a constant-on-time PWM controller
which provides four resistor programmable DC output
voltages by controlling the G0 and G1 digital input. The
output voltage is programmable from 0.75V to 3.3V. The
RT8208E/F offers the lowest total solution cost in systems
where need output voltage slewing. The RT8208E/F
provides an automatic masking power good output during
output voltage transition.
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The constant-on-time PWM control scheme handles wide
input/output ratios with ease and provides 100ns “instanton” response to load transient while maintaining a
relatively constant frequency. It provides the high efficiency,
excellent transient response, and DC output accuracy
needed for stepping down high voltage batteries to
generate low voltage CPU core, graphics, I/O and chipset
RAM supplies in notebook computers.
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The RT8208E/F achieves high efficiency at a reduced cost
by eliminating the current sense resistor in traditional
current mode PWMs. Efficiency is further enhanced by
its ability to drive very large synchronous rectifier
MOSFETs. The buck conversion allows this device to
directly step down from high voltage batteries for the highest
possible efficiency. Additional features include soft-start,
under voltage protection, programmable over current
protection and non-overlapping gate drive. The RT8208E/
F is available in a WQFN-16L 3x3 package.
Ultra-High Efficiency
Resistor Programmable Output Voltage from 0.75V
to 3.3V with Integrated Transition Support
Quick Load Step Response within 100ns
1% VFB Accuracy over Line and Load
4.5V to 26V Battery Input Range
Resistor Programmable Frequency
Integrated Bootstrap Switch
Resistor Programmable Positive Current Limit by
Low Side RDS(ON) Sense (Lossless Limit)
Negative Current Limiter
Voltage Transient Overshoot Eliminator*
Over Voltage Protection
Under Voltage Protection
4 Steps Current Limit During Soft-Start
Power Good Indicator
RoHS Compliant and Halogen Free
* Patent Pending
Applications
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Notebook Computers
System Power Supplies
I/O Supplies
Programmable-Output Power Supplies
Ordering Information
RT8208
Package Type
QW : WQFN-16L 3x3 (W-Type)
Pin Configurations
Lead Plating System
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)
BOOT
EN/DEM
G1
TON
(TOP VIEW)
16 15 14 13
1
12
2
11
GND
3
10
17
D1
5
6
7
9
8
LGATE
4
D0
G0
VOUT
VDD
FB
PGOOD
WQFN-16L 3x3
DS8208E/F-03 May 2011
UGATE
PHASE
CS
VDDP
Turn-on D0/D1 MOSFET
E : G0/G1 Active-High
F : G0/G1 Active-Low
Note :
Richtek products are :
`
RoHS compliant and compatible with the current require-
`
Suitable for use in SnPb or Pb-free soldering processes.
ments of IPC/JEDEC J-STD-020.
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1
RT8208E/F
Marking Information
RT8208EGQW
RT8208FGQW
30= : Product Code
31= : Product Code
YMDNN : Date Code
30=YM
DNN
YMDNN : Date Code
31=YM
DNN
RT8208EZQW
RT8208FZQW
30 : Product Code
30 YM
DNN
31 : Product Code
YMDNN : Date Code
YMDNN : Date Code
31 YM
DNN
Typical Application Circuit
R3
250k
16
9
VDDP
R2
100k
VIN
4.5V to 26V
RT8208E/F
TON
BOOT 13
VDDP
UGATE
R1
10
2
C2
1µF
VDD
PHASE
G0
FB
R6
18k
CCM/DEM
17 (Exposed Pad)
GND
7
VOUT
C3
0.1µF
R10
0
VOUT
0.9V
Q1
BSC119N03S
L1
1µH
R7
Q2
BSC119N03S
C7
G0
R8
12k
C5* C6*
C1
220µF
3
G1 14
5
D1
6
D0
15 EN/DEM
R5
0
C4
10µF
11
LGATE 8
4 PGOOD
10 CS
PGOOD
12
R4
0
G1
R11*
R12*
R9
60k
1
* : Optional
Functional Pin Description
Pin No.
Pin Name
Pin Function
Output Voltage Pin. Connect to the output of PWM converter. VOUT is an input of the
PWM controller.
Analog supply voltage input for the internal analog integrated circuit. Bypass to GND with
a 1μF ceramic capacitor.
Feedback Input Pin. Connect FB to a resistor voltage divider from VOUT to GND to adjust
output voltage from 0.75V to 3.3V
1
VOUT
2
VDD
3
FB
4
PGOOD
Power good signal open-drain output of PWM converter. This pin will be pulled high when
the output voltage is within the target range.
5
D1
Drain of the internal MOSFET which is controlled by G1.
6
D0
Drain of the internal MOSFET which is controlled by G0.
7
G0
Control Input Pin for the D0 MOSFET. A logic active-high for RT8208E and active-low for
RT8208F to turn on the internal MOSFET at D0.
To be continued
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DS8208E/F-03 May 2011
RT8208E/F
Pin No.
Pin Name
8
LGATE
9
VDDP
10
CS
11
PHASE
12
UGATE
13
BOOT
14
G1
15
EN/DEM
16
TON
Pin Function
Low side N-MOSFET gate driver output for PWM. This pin swings between GND
and VDDP.
VDDP is the gate driver supply for external MOSFETs. Bypass to GND with a 1μF
ceramic capacitor.
Over Current Trip Point Set Input. Connect a resistor from this pin to signal ground
to set threshold for both over current and negative over current limit.
The UGATE High Side Gate Driver Return. Also serves as anode of over current
comparator.
High side N-MOSFET floating gate driver output for the PWM converter. This pin
swings between PHASE and BOOT.
Boost Capacitor Connection for PWM Converter. Connect to an external ceramic
capacitor to PHASE.
Control Input Pin for the D1 MOSFET. A logic active-high for RT8208E and
active-low for RT8208F to turn on the internal MOSFET at D1.
Enable/Diode Emulation Mode Control Input. Connect to VDD for diode–emulation
mode, connect to GND for shutdown and floating the pin for CCM mode.
On Time/Frequency Adjustment Pin. Connect to PHASE through a resistor. TON is
an input for the PWM controller.
The exposed pad must be soldered to a large PCB and connected to GND for
maximum power dissipation.
17 (Exposed pad) GND
Function Block Diagram
G0 G1
TON
SS
(internal)
D1
Control
Logic
TRIG
On-time
Compute
1-SHOT
VOUT
D0
BOOT
R
GM
+
-
S
+
Q
UGATE
DRV
PHASE
Min. TOFF
Q
TRIG
0.75V VREF
+
125% VREF
70% VREF
FB
OV
R Latch
S
Q
UV
R Latch
S
Q
VDDP
1-SHOT
+
GND
Diode
Emulation
-
90% VREF
+
10µA
Thermal
Shutdown
Blanking Signal
Counter
EN
LGATE
DRV
-
+
+
GM
-
CS
-
SS Timer
G0, G1
VDD
DS8208E/F-03 May 2011
PGOOD
EN
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3
RT8208E/F
Absolute Maximum Ratings
(Note 1)
BOOT to PHASE ---------------------------------------------------------------------------------------------------------PHASE to GND
DC ----------------------------------------------------------------------------------------------------------------------------< 20ns ----------------------------------------------------------------------------------------------------------------------z UGATE to PHASE
DC ----------------------------------------------------------------------------------------------------------------------------< 20ns ----------------------------------------------------------------------------------------------------------------------z LGATE to GND
DC ----------------------------------------------------------------------------------------------------------------------------< 20ns ----------------------------------------------------------------------------------------------------------------------z VDD, VDDP, VOUT, EN/DEM, FB, PGOOD, TON to GND ------------------------------------------------------z CS to GND -----------------------------------------------------------------------------------------------------------------z Power Dissipation, PD @ TA = 25°C
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−0.3V to 6V
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WQFN−16L 3x3 -----------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WQFN−16L 3x3, θJA -----------------------------------------------------------------------------------------------------WQFN−16L 3x3, θJC -----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Mode) ---------------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------------
Recommended Operating Conditions
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−0.3V to 32V
−8V to 38V
−0.3V to 6V
−5V to 7.5V
−0.3V to 6
−2.5V to 7.5V
−0.3V to 6V
−0.3V to 6V
1.471W
68°C/W
7.5°C/W
260°C
150°C
−65°C to 150°C
2kV
200V
(Note 4)
Input Voltage, VIN ---------------------------------------------------------------------------------------------------------Supply Voltage, VDD, VDDP ---------------------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------------------------
4.5V to 26V
4.5V to 5.5V
−40°C to 125°C
−40°C to 85°C
Electrical Characteristics
(VIN = 15V, VDD = VDDP = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VDD + VDDP, VFB = 0.8V
--
--
1250
μA
VDD + VDDP
--
1
10
−10
−1
--
0.742
0.750
0.758
V
−1
0.1
1
μA
0.75
--
3.3
V
PWM Controller
Quiescent Supply Current
IQ
Shutdown Current
ISHDN
FB Reference Voltage
VREF
FB Input Bias Current
Output Voltage Range
EN/DEM = GND
VDD = 4.5V to 5.5V
VFB = 0.75V
VOUT
μA
To be continued
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4
DS8208E/F-03 May 2011
RT8208E/F
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
D0 Pull-Down Resistance
D0 to GND, G0 = 5V
--
10
--
Ω
D1 Pull-Down Resistance
D1 to GND, G1 = 5V
VPHASE = 12V, VOUT = 2.5V,
RTON = 250kΩ
--
10
--
Ω
336
420
504
ns
250
400
550
ns
EN/DEM = GND
--
20
--
Ω CS to GND
9
10
11
μA
−10
--
10
mV
PHASE to GND, EN/DEM = 5V
−10
--
5
mV
GND to PHASE, V CS = 50mV
40
50
60
GND to PHASE, V CS = 200mV
190
200
210
Current Limit Setting Range
CS to GND
50
--
200
mV
Output UV Threshold
UVP Detection
60
70
80
%
OVP Detection
120
125
130
%
--
20
--
μs
4.1
4.3
4.5
V
Hysteresis
--
80
--
mV
Current Limit Step Duration at
Soft Start
Each step
--
128
--
clks
UVP Blanking Time
From EN signal going high
--
512
--
clks
--
155
--
°C
--
10
--
°C
On-Time
Minimum Off-Time
VOUT Shutdown Discharge
Resistance
Current Sensing
Current Limiter Source Current
Current Comparator Offset
Zero Crossing Threshold
Fault Protection
Current Limit (Threshold)
OVP Threshold
VFB_OVP
OV Fault Delay
FB forced above OV threshold
Rising edge, PWM disabled below
this level
VDD Under Voltage Lockout
Threshold
Thermal Shutdown
T SHDN
Thermal Shutdown Hysteresis
mV
Driver On-Resistance
UGATE Driver Source
RUGATEsr
BOOT to PHASE = 5V
--
2
5
Ω
UGATE Driver Sink
RUGATEsk
BOOT to PHASE = 5V
--
1
5
Ω
LGATE Driver Source
RLGATEsr
LGATE, High State
--
1
5
Ω
LGATE, Low State
UGATE to PHASE = 2.5V,
BOOT to PHASE = 5V
--
0.5
2.5
Ω
--
1
--
A
LGATE forced to 2.5V
--
1
--
A
LGATE forced to 2.5V
--
3
--
A
LGATE Rising (Phase = 1.5V)
--
30
--
UGATE Rising
--
30
--
VDDP to BOOT, 10mA
--
--
80
LGATE Driver Sink
RLGATEsk
UGATE Gate Driver Source/Sink
Current
LGATE Gate Driver Source
Current
LGATE Gate Driver Sink Current
Dead Time
Internal Boost Charging Switch
On-Resistance
ns
Ω
To be continued
DS8208E/F-03 May 2011
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5
RT8208E/F
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
EN/DEM Low
--
--
0.8
EN/DEM High
2.9
--
--
EN/DEM Floating
--
2
--
G0 Low
--
--
0.8
G0 High
2
--
--
G1 Low
--
--
0.8
G1 High
2
--
--
EN/DEM = VDD
--
1
5
EN/DEM = 0
−5
1
--
G0 = G1 = VDD or GND
−1
--
5
87
90
93
--
125
--
Hysteresis
--
3
--
Fault Propagation Delay
Falling edge, FB forced below PGOOD
trip threshold
--
2.5
--
μs
Output Low Voltage
ISINK = 1mA
--
--
0.4
V
Leakage Current
High state, forced to 5V
--
--
1
μA
Logic I/O
EN/DEM Logic Input Voltage
G0 Logic Input Voltage
G1 Logic Input Voltage
Logic Input Current
V
V
V
μA
PGOOD
PGOOD Threshold
VFB with respect to Reference,
PGOOD from Low to High
VFB with respect to Reference,
PGOOD from High to Low
%
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of
JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
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DS8208E/F-03 May 2011
RT8208E/F
Typical Operating Characteristics
1.8V Efficiency vs. Output Current
90
400
DEM
70
CCM
60
50
40
30
20
VIN = 10V, VOUT = 1.8V
EN = VDD / Floating
10
0
0.001
0.01
0.1
1
Switching Frequency (kHz)1
450
80
Efficiency (%)
Switching Frequency vs. Output Current
100
VIN = 15V, VOUT = 1.8V, EN = VDD / Floating
CCM
350
300
250
200
DEM
150
100
50
0
0.001
10
0.01
Output Current (A)
DEM
Efficiency (%)
80
70
60
CCM
40
30
20
VIN = 15V, VOUT = 1.8V
EN = VDD / Floating
10
0
0.001
0.01
0.1
1
Switching Frequency (kHz)1
450
50
VIN = 15V, VOUT = 1.8V, EN = VDD / Floating
CCM
350
300
250
DEM
200
150
100
50
0
0.001
10
0.01
Efficiency (%)
80
1.8V Efficiency vs. Output Current
DEM
70
CCM
50
40
30
20
VIN = 19V, VOUT = 1.8V
EN = VDD / Floating
10
0
0.001
0.01
0.1
Output Current (A)
DS8208E/F-03 May 2011
1
10
Switching Frequency vs. Output Current
450
60
0.1
Output Current (A)
1
10
Switching Frequency (kHz)1
90
10
400
Output Current (A)
100
1
Switching Frequency vs. Output Current
1.8V Efficiency vs. Output Current
100
90
0.1
Output Current (A)
VIN = 19V, VOUT = 1.8V, EN = VDD / Floating
400
350
CCM
300
250
DEM
200
150
100
50
0
0.001
0.01
0.1
1
10
Output Current (A)
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7
RT8208E/F
Shutdown Input Current vs. Input Voltage
0.9V Load Transient Response
Shutdown Input Current (μA)1
1.0
VOUT
(100mV/Div)
0.8
IOUT
(10A/Div)
0.6
UGATE
(20V/Div)
0.4
0.2
LGATE
(5V/Div)
EN = GND, No Load
0.0
7
9
11
13
15
17
19
21
23
VIN = 12V, EN = Floating, CCM Mode, VOUT = 0.9V
Time (25μs/Div)
25
Input Voltage (V)
Power On From EN (CCM)
Power On From EN (DEM)
VOUT
(1V/Div)
VOUT
(1V/Div)
UGATE
(10V/Div)
UGATE
(10V/Div)
EN
(2V/Div)
PGOOD
(5V/Div)
EN
(5V/Div)
PGOOD
(5V/Div)
EN = Floating, VIN = 12V
VOUT = 0.9V, No Load
Time (400μs/Div)
Time (400μs/Div)
OVP
UVP
VIN = 12V, VOUT = 0.9V
No Load, N = Floating
(CCM Mode)
VIN = 12V, VOUT = 0.9V,
Load, EN = VDD (DEM Mode)
VOUT
(500mV/Div)
VOUT
(500mV/Div)
IL
(10A/Div)
UGATE
(10V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
LGATE
(5V/Div)
Time (40μs/Div)
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8
EN = VDD, VIN = 12V
VOUT = 0.9V, No Load
Time (20μs/Div)
DS8208E/F-03 May 2011
RT8208E/F
VOUT Up Transient (No Load)
VOUT
(1V/Div)
G1
(5V/Div)
VIN = 12V, EN = Floating
(CCM Mode)
VOUT = 0.9V to 1.5V
VOUT Up Transient (Load = 10A)
VOUT
(1V/Div)
G1
(5V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
LGATE
(5V/Div)
RT8208E
VIN = 12V, EN = Floating
(CCM Mode)
VOUT = 0.9V to 1.5V
RT8208E
Time (20μs/Div)
Time (20μs/Div)
VOUT Down Transient (No Load)
VOUT Down Transient (Load = 10A)
VOUT
(1V/Div)
G1
(5V/Div)
VIN = 12V, EN = Floating
(CCM Mode)
VOUT = 1.5V to 0.9V
VIN = 12V, EN = Floating
(CCM Mode)
VOUT = 1.5V to 0.9V
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
RT8208E
Time (20μs/Div)
DS8208E/F-03 May 2011
VOUT
(1V/Div)
G1
(5V/Div)
LGATE
(5V/Div)
RT8208E
Time (20μs/Div)
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9
RT8208E/F
Application Information
The RT8208E/F is a constant-on-time PWM controller
which provides four resistor-programmable DC output
voltages by controlling the G0 and G1 digital input. The
output voltage is programmable from 0.75V to 3.3V. The
constant on-time PWM control scheme handles wide input/
output rations with ease and providing 100ns “instant-on”
response to load steps while maintaining a relatively
constant operating frequency and inductor operating point
over a wide range of input voltages. The topology
circumvents the poor load transient timing problems of
fixed-frequency current mode PWMs while avoiding the
problems caused by widely varying switching frequencies
in conventional constant-on-time and constant off-time
PWM schemes. The DRVTM mode PWM modulator is
specifically designed to have better noise immunity for
such a single output application.
PWM Operation
The Mach ResponseTM, DRVTM mode controller relies on
the output filter capacitor’ s Effective Series Resistance
(ESR) to act as a current sense resistor, so the output
ripple voltage provides the PWM ramp signal. Refer to the
function diagrams of the RT8208E/F, the synchronous high
side MOSFET is turned on at the beginning of each cycle.
After the internal one-shot timer expires, the MOSFET is
turned off. The pulse width of this one shot is determined
by the converter’ s input and output voltages to keep the
frequency fairly constant over the input voltage range.
Another one-shot sets a minimum off-time (400ns typ.).
On-Time Control (tON)
The on-time one-shot comparator has two inputs. One
input monitors the output voltage, while the other input
samples the input voltage and converts it to a current.
This input voltage proportional current is used to charge
an internal on-time capacitor. The on-time is the time
required for the voltage on this capacitor to charge from
zero volts to VOUT, thereby making the on-time of the
high side switch directly proportional to output voltage
and inversely proportional to input voltage. The
implementation results in a nearly constant switching
frequency without the need of a clock generator.
Although this equation provides a good approximation to
start with, the accuracy depends on each design and
selection of the high side MOSFET.
And then the switching frequency (f) is :
VOUT
f=
VIN × tON
RTON is a resistor connected from the PHASE to TON pin.
Mode Selection (EN) Operation
The EN pin enables the supply. When EN/DEM is tied to
VDD, the controller is enabled and operates in diodeemulation mode. When the EN pin is floating, the
RT8208E/F will operate in forced-CCM mode.
Diode-Emulation Mode (EN = High)
In diode-emulation mode, the RT8208E/F automatically
reduces switching frequency at light-load conditions to
maintain high efficiency. This reduction of frequency is
achieved smoothly and without increasing VOUT ripple or
load regulation. As the output current decreases from
heavy-load condition, the inductor current is also reduced,
and eventually comes to the point that its valley touches
zero current, which is the boundary between continuous
conduction and discontinuous conduction modes. By
emulating the behavior of diodes, the low side MOSFET
allows only partial of negative current when the inductor
freewheeling current reach negative. As the load current
is further decreased, it takes longer and longer to discharge
the output capacitor to the level than requires the next
“ON” cycle. The on-time is kept the same as that in the
heavy-load condition. In reverse, when the output current
increases from light load to heavy load, the switching
frequency increases to the preset value as the inductor
current reaches the continuous condition. The transition
load point to the light-load operation can be calculated as
follows (Figure 1) :
ILOAD ≈
(VIN − VOUT )
× tON
2L
where tON is On-time.
tON = 9.6p x RTON x (VOUT + 0.1) / (VIN − 0.3) + 50ns
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10
DS8208E/F-03 May 2011
RT8208E/F
IL
VIN
Slope = (VIN -VOUT) / L
iL, peak
UGATE
VOUT
PHASE
iLoad = iL, peak / 2
LGATE
VOUT
GND
0
tON
t
Figure 1. Boundary Condition of CCM/DEM
The switching waveforms may appear noisy and
asynchronous when light loading causes diode-emulation
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in DEM noise
vs. light-load efficiency is made by varying the inductor
value. Generally, low inductor values produce a broader
efficiency vs. load curve, while higher values result in higher
full-load efficiency (assuming that the coil resistance
remains fixed) and less output voltage ripple. The
disadvantages for using higher inductor values include
larger physical size and degraded load-transient response
(especially at low input voltage levels).
Forced-CCM Mode (EN = floating)
The low noise, forced-CCM mode (EN = floating) disables
the zero-crossing comparator, which controls the low side
switch on-time. This causes the low side gate drive
waveform to become the complement of the high side
gate drive waveform. This in turn causes the inductor
current to reverse at light loads as the PWM loop to
maintain a duty ratio VOUT/VIN. The benefit of forcedCCM mode is to keep the switching frequency fairly
constant, but it comes at a cost : The no-load battery
current can be up to 10mA to 40mA, depending on the
external MOSFETs.
Output Voltage Setting (FB)
The output voltage can be adjusted from 0.75V to 3.3V by
setting the feedback resistor R1 and R2, see Figure 2.
With G0 and G1 in low state, the output voltage is at the
lowest value. Choose R2 to be approximately 20kΩ, and
solve for R1 using the equation :
⎛ R1 ⎞
VOUT = VREF × ⎜ 1+
⎟
⎝ R2 ⎠
where VREF is 0.75V in typical.
DS8208E/F-03 May 2011
FB
G0
G1
R1
R2
Figure 2. Setting VOUT with a Resistor Divider
Output Voltage Transition Control
The RT8208E/F provides two digital control input G0 and
G1 to allow selection among four output voltages. The
output voltage is regulated by comparing the FB pin
(connected to VOUT via an external resistor divider) to
the internal 0.75V reference. The G0 and G1 digital input
control the gate of internal respective MOSFET whose
drain is connected to D0 and D1 respectively. Using Gx,
the user controls whether Dx is grounded or open, which
then controls the resistor divider ratio for VOUT. A logic
high signal on Gx will connect Dx to ground.
When the Gx input changes state, this change quickly
causes three actions :
1. D0 changes state.
2. The power good PGOOD output is temporarily latched
into its present state. This prevents chattering or false
tripping while VOUT moves to the new level.
3. When the Gx changes state whether DEM is set or
not, then enter the PWM mode and counts 32 clock
cycles. For the duration of 32 clock cycles, the OVP
and UVP function is masked. This behavior allows the
output to slew down to the new level without tripping
the OVP or UVP function when the Gx change causes
rapid change of Dx, which in turns cause a rapid change
at FB.
Output voltage is regulated through the FB pin via resistors
R1 through R4 as shown in Figure 3.
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11
RT8208E/F
V OUT
D0
D1
R4
R3
R1
FB
TON
G1
G0
0.75V
V OUT
D0
D1
R3
R4
R1
FB
R2
R2
Control
Logic
GND
G1
G0
Control
Logic
GND
Figure 3. Output Voltage Selection By G0 and G1 Input
The following table shows the equations for VOUT as a
function of digital control input G0 and G1.
Gx
GND
RT8208E RT8208F
Output Voltage Equation
G0 G1 G0 G1
FB
0
0
1
1
VOUT =
R1+R2
x 0.75
R2
LGATE
1
0
0
1
VOUT =
R1+(R2//R3)
x 0.75
(R2//R3)
UGATE
0
VOUT =
R1+(R2//R4)
x 0.75
(R2//R4)
0
1
1
1
1
0
0
VOUT
Initial
VOUT
VOUT
R1+(R2//R3//R4)
=
x 0.75
(R2//R3//R4)
Final
VOUT
Figure 4. Output Voltage Down Transition
Note that the RDS(ON) of the internal MOSFET is in series
with external resistor, which adds typically 10Ω in series.
Gx
GND
Output Voltage Transition Operation
The digital input control pin Gx allows VOUT to transition
to both higher and lower values. For a down transition, the
rapid change Gx from high to low as sudden release either
of external resistors (R3 or R4) will cause FB to go above
the 0.75V threshold. At this time, the LGATE will drive
high to turn on the low side MOSFET and draw current
from the output capacitor via the inductor. LGATE will
remain on until FB falls to 0.75V, at which point a normal
UGATE switching cycle begins, see Figure4. For a down
transition, the low side MOSFET stays on before FB
reaches to 0.75V, thus the negative inductor current will
be increased. If the negative current is too large to trigger
NOCP, the low side MOSFET is turned off which can avoid
too much negative current to damage component. Refer
to the Negative Over Current Limit section for a full
description.
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12
FB
Threshold
FB
UGATE
LGATE
Minimum
off-time
Final VOUT
VOUT
Initial VOUT
Figure 5. Output Voltage Up Transition
DS8208E/F-03 May 2011
RT8208E/F
For an up transition (from lower to higher VOUT) as shown
in Figure5, the Gx change affects Dx and causes FB to
drop below the 0.75V trip point. This quickly trips the FB
comparator regardless of whether DEM is active or not,
generating an UGATE on-time and a subsequent LGATE
will be turned on. At the end of the minimum off-time
(400ns), if FB is still below 0.75V then another UGATE
on-time is started. This sequence continues until the FB
pin exceeds 0.75V.
Gx
GND
FB
Threshold
FB
UGATE
LGATE
Minimum
off-time
Final V OUT
V OUT
Initial V OUT
Figure 6. Output Voltage Up Transition
with Overshooting
If the VOUT change is significant, there can be several
consecutive cycle of UGATE on-time followed by minimum
LGATE time. This can cause a rapid increase in inductor
current: typically it takes only a few switching cycles for
inductor current to rise up to the current limit. At some
point the FB voltage will rise up to the 0.75V reference
and the UGATE pulses will cease, but the inductor’ s LI2
energy must then flow into the output capacitor. This can
create a significant overshoot as shown in Figure6.
The overshooting can be approximated by the following
equation, where ICL is the current limit, VFINAL is the
desired set point for the final voltage, L is in μH and COUT
is in μF.
⎛ I 2 ×L
⎞
VMAX = ⎜ ( CL
) + VFIANL 2 ⎟
⎜ COUT
⎟
⎝
⎠
DS8208E/F-03 May 2011
The Overshoot eliminator (Patent Pending) prevents output
voltage overshooting after rapid changes of Gx. This results
in a gradual change from VOUT(INITIAL) to VOUT(FINAL) and
prevents the buildup of high inductor current and reducing
overshoot.
Current Limit Setting (OCP)
RT8208E/F has cycle-by-cycle current limiting control.
The current limit circuit employs a unique “valley” current
sensing algorithm. If the magnitude of the current sense
signal at CS is above the current limit threshold, the PWM
is not allowed to initiate a new cycle (Figure 7) in order to
provide both good accuracy and a cost effective solution,
the RT8208E/F supports temperature compensated
MOSFET R DS(ON) sensing. The CS pin should be
connected to GND through the trip voltage setting resistor,
RCS. The CS terminal source 10μA ICS current, and the
trip level is set to the CS trip voltage, VCS as in the following
equation.
VCS (mV) = RCS (kΩ) × 10 ( μ A )
Inductor current is monitored by the voltage between the
PGND pin and the PHASE pin. So the PHASE pin should
be connected to the drain terminal of the low side
MOSFET. ICS has temperature coefficient to compensate
the temperature dependency of the RDS(ON). PGND is used
as the positive current sensing node. So PGND should
be connected to the source terminal of the bottom
MOSFET.
As the comparison is done during the OFF state, VCS
sets the valley level of the inductor current. Thus, the
load current at over current threshold, ILOAD_OC, can be
calculated as follows;
ILOAD_OC =
=
VCS
RDS(on)
VCS
RDS(ON)
+
+
Iripple
2
( V − VOUT ) × VOUT
1
× IN
2xLxf
VIN
In an over current condition, the current to the load exceeds
the current to the output capacitor thus the output voltage
tends to fall. Eventually, it crosses the under voltage
protection threshold and shutdown.
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13
RT8208E/F
IL
IL, peak
ILoad
ILIM
t
0
Figure 7. “Vally” Current Limit
Negative Over Current Limit (CCM Mode Only)
The RT8208E/F also supports cycle-by-cycle negative over
current limiting in CCM Mode only. The over-current limit
is set to be negative but is the same absolute value as
the positive over current limit. If output voltage continues
to rising, the low side MOSEFT stays on, thus inductor
current is reduced and reverses direction after it reaches
zero. When there is too much negative current in the
inductor, the low side MOSFET is turned off and the current
flows to VIN through the body diode of the high side
MOSFET. Because this protection limits current to
discharge the output capacitor, output voltage tends to
rise, eventually hitting the over voltage protection threshold
and shutdown. In order to prevent false OVP from triggering,
the low side MOSFET is turned on again 400ns after it is
turned off. If the device hits the negative over current
threshold again before output voltage is discharged to the
target level, the low side MOSFET is turned off and process
repeats. It ensures maximum allowable discharge
capability when output voltage continues to rise. On the
other hand, if the output is discharged to the target level
before negative current threshold is reached, the low side
MOSFET is turned off, the high side MOSFET is then
turn on, and the device resumes normal operation.
MOSFET Gate Driver (UGATE, LGATE)
The high side driver is designed to drive high current, low
RDS(ON) N-MOSFET(s). When configured as a floating
driver, 5V bias voltage is delivered from VDDP supply. The
average drive current is proportional to the gate charge at
VGS = 5V times switching frequency. The instantaneous
drive current is supplied by the flying capacitor between
www.richtek.com
14
BOOT and PHASE pins. A dead time to prevent shoot
through is internally generated between high side
MOSFET off to low side MOSFET on, and low side
MOSFET off to high side MOSFET on. The low side driver
is designed to drive high current, low RDS(ON) N-MOSFETs.
The internal pull-down transistor that drives LGATE low is
robust, with a 0.6Ω typical on resistance. A 5V bias voltage
is delivered from VDDP supply. The instantaneous drive
current is supplied by the flying capacitor between VDDP
and PGND.
For high current applications, some combinations of high
and low side MOSFETs might be encountered that will
cause excessive gate-drain coupling, which can lead to
efficiency-killing, EMI-producing shoot-through currents.
This is often remedied by adding a resistor in series with
BOOT, which increases the turn-on time of the high side
MOSFET without degrading the turn-off time (Figure 8).
VIN
BOOT
R
UGATE
PHASE
Figure 8. Reducing the UGATE Rise Time
Power Good Output (PGOOD)
The power good output is an open-drain output and requires
a pull-up resistor. When the output voltage is 25% above
or 10% below its set voltage, PGOOD will be pulled low. It
is held low until the output voltage returns to within these
tolerances once more. In soft start, PGOOD is actively
held low and is allowed to transition high until soft start is
over and the output reaches 93% of its set voltage. There
is a 2.5μs delay built into PGOOD circuitry to prevent
false transition.
When Gx changes state, PGOOD is immediately latched
into its present state for 32 clock cycle while VOUT and
FB are changed to the new level. After that the latch will
be disabled.
DS8208E/F-03 May 2011
RT8208E/F
POR, UVLO and Soft-Start
Output Inductor Selection
Power On Reset (POR) occurs when VDD rises above to
approximately 4.3V. after POR is triggered. And then, the
RT8208E/F will reset the fault latch and prepare the PWM
for operation. Below 4.1V (MIN), the VDD under voltage
lockout (UVLO) circuitry inhibits switching by keeping
UGATE and LGATE low. A built-in soft-start is used to
prevent surge current from power supply input after EN is
enabled. The maximum allowed current limit is segmented
in 4 steps : 25%, 50%, 75% and 100% during this period,
each step is 128 UGATE clks. The current limit steps can
eliminate the VOUT folded-back in the soft-start duration.
The switching frequency (on-time) and operating point (%
ripple or LIR) determine the inductor value as follows :
Output Over Voltage Protection (OVP)
⎡⎛ L
IPEAK = ILOAD(MAX) + ⎢⎜ IR
⎣⎝ 2
The output voltage can be continuously monitored for over
voltage protection. When the output voltage exceeds 25%
of the its set voltage threshold, over voltage protection is
triggered and the low side MOSFET is latched on. This
activates the low side MOSFET to discharge the output
capacitor. The RT8208E/F is latched once OVP is
triggered and can only be released by VDD or EN power
on reset. There is 20μs delay built into the over voltage
protection circuit to prevent false transitions.
When Gx changes state, the OVP function is masked for
32 clock cycle while VOUT and FB are changed to the
new level. After that the mask will be disabled.
Output Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage protection. When the output voltage is less than
70% of its set voltage threshold, under voltage protection
is triggered and then both UGATE and LGATE gate drivers
are forced low. In order to remove the residual charge on
the output capacitor during the under voltage period, if
PHASE is greater than 1V, the LGATE is forced high until
PHASE is lower than 1V. There is 2.5μs delay built into
the under voltage protection circuit to prevent false
transitions. During soft-start, the UVP blanking time is
512 UGATE clks.
When Gx changes state, the UVP function is masked for
32 clock cycle while VOUT and FB change to the new
level, after which the mask is disable.
DS8208E/F-03 May 2011
L=
TON × ( VIN − VOUT )
LIR × ILOAD(MAX)
Where LIR is the ratio of peak-to-peak ripple current to the
maximum average inductor current. Find a low-pass
inductor having the lowest possible DC resistance that
fits in the allowed dimensions. Ferrite cores are often the
best choice, although powdered iron is inexpensive and
can work well at 200kHz. The core must be large enough
and not to saturate at the peak inductor current (IPEAK) :
⎤
⎞
⎟ × ILOAD(MAX) ⎥
⎠
⎦
Output Capacitor Selection
The output filter capacitor must have low enough Equivalent
Series Resistance (ESR) to meet output ripple and loadtransient requirements, yet have high enough ESR to
satisfy stability requirements. The output capacitance
must also be high enough to absorb the inductor energy
while transiting from full-load to no-load conditions without
tripping the overvoltage fault latch.
Although Mach ResponseTM DRVTM dual ramp valley mode
provides many advantages such as ease-of-use, minimum
external component configuration, and extremely short
response time, due to not employing an error amplifier in
the loop, a sufficient feedback signal needs to be provided
by an external circuit to reduce the jitter level. The required
signal level is approximately 15mV at the comparing point.
This generates VRipple = (VOUT / 0.75) x 15mV at the output
node. The output capacitor ESR should meet this
requirement.
Output Capacitor Stability
Stability is determined by the value of the ESR zero relative
to the switching frequency. The point of instability is given
by the following equation :
fESR =
f
1
≤ SW
2π × ESR × COUT
4
Do not put high value ceramic capacitors directly across
the outputs without taking precautions to ensure stability.
www.richtek.com
15
RT8208E/F
the thermal resistance θJA is 68°C/W on the standard
JEDEC 51-7 four layers thermal test board. The maximum
power dissipation at TA = 25°C can be calculated by
following formula :
PD(MAX) = (125°C − 25°C) / (68°C/W) = 1.471W for
WQFN-16L 3x3 package
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance θJA. For RT8208E/F package, the Figure 9 of
derating curve allows the designer to see the effect of
rising ambient temperature on the maximum power
allowed.
1.8
Maximum Power Dissipation (W)1
Large ceramic capacitors can have a high-ESR zero
frequency and cause erratic and unstable operation.
However, it is easy to add sufficient series resistance by
placing the capacitors a couple of inches downstream from
the inductor and connecting VOUT or FB divider close to
the inductor. There are two related but distinct ways
including double-pulsing and feedback loop instability to
identify the unstable operation. Double-pulsing occurs due
to noise on the output or because the ESR is too low that
there is not enough voltage ramp in the output voltage
signal. This “fools” the error comparator into triggering a
new cycle immediately after 400ns minimum off-time
period has expired. Double-pulsing is more annoying than
harmful, resulting in nothing worse than increased output
ripple. However, it may indicate the possible presence of
loop instability, which is caused by insufficient ESR. Loop
instability can result in oscillation at the output after line
or load perturbations that can trip the over voltage
protection latch or cause the output voltage to fall below
the tolerance limit. The easiest method for stability
checking is to apply a very zero-to-max load transient
and carefully observe the output voltage ripple envelope
for overshoot and ringing. It helps to simultaneously monitor
the inductor current with AC probe. Do not allow more
than one ringing cycle after the initial step-response underor over-shoot.
PD(MAX) = (TJ(MAX) − TA) / θJA
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 9. Derating Curve for RT8208E/F Package
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
Four Layers PCB
1.6
Layout Considerations
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to the converter
instability.
For best performance of the RT8208E/F, the following
guidelines should be strictly followed.
Where T J(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
`
Connect an RC low pass filter from VDDP to VDD, 1μF
and 10Ω are recommended. Place the filter capacitor
close to the IC.
For recommended operating conditions specification of
the RT8208E/F, the maximum junction temperature of the
die is 125°C. The junction to ambient thermal resistance
θJA is layout dependent. For WQFN-16L 3x3 packages,
`
Keep current limit setting network as close as possible
to the IC. Routing of the network should be kept away
from to high voltage switching nodes to prevent it from
coupling.
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16
DS8208E/F-03 May 2011
RT8208E/F
`
Connections from the drivers to the respective gate of
the high side or the low side MOSFET should be as
short as possible to reduce stray inductance.
`
All sensitive analog traces and components such as
VOUT, FB, GND, EN/DEM, PGOOD, OC, VDD, and
TON should be placed away from high voltage switching
nodes such as PHASE, LGATE, UGATE, or BOOT
nodes to prevent it from coupling. Use internal layer(s)
as ground plane(s) and shield the feedback trace from
power traces and components.
`
Current sense connections must always be made using
Kelvin connections to ensure an accurate signal, with
the current limit resistor located at the device.
`
Power sections should connect directly to ground
plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed to minimize loops
and reduce losses.
DS8208E/F-03 May 2011
www.richtek.com
17
RT8208E/F
Outline Dimension
D
SEE DETAIL A
D2
L
1
E
E2
e
b
A
A1
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A3
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
1.300
1.750
0.051
0.069
E
2.950
3.050
0.116
0.120
E2
1.300
1.750
0.051
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 16L QFN 3x3 Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
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18
DS8208E/F-03 May 2011
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