DSP32C Digital Signal Processor

DSP32C Digital Signal Processor
Data Sheet Addendum
November 1996
DSP32C Digital Signal Processor
Products Affected
Problem Resolution
This advisory is effective for issue 5 of the DSP32C.
Issue 5 devices are identified by a device code of the
form DSP32C-X35 (where X is replaced by R or F).
PEN, PWN, and PGN may be synchronized with the
DSP clock to eliminate this potential alignment problem. Figure 1 illustrates a circuit that may be used to
synchronize these inputs. Figure 2 shows the associated timing. The synchronization circuit delays the rise
and fall points of PEN, PWN, and PGN. This added
delay is equal to the maximum time of tCKOHCKOH +
the cp to Q propagation delay of the F74 (tPLH or
tPHL). For an 80 MHz CKI, the maximum delay would
be 12.5 ns + the cp to Q delay of the F74. Subsequently, the user must ensure that other timing specifications listed in Table 1 and Table 2 are not violated.
The design consideration involves external writes to
and reads from the parallel data register (PDR) with
a system clock greater than 66 MHz.
Problem Description
Contents of the PDR register may fail to be transferred to memory during a DMA write operation when
the falling edge of PEN or PWN aligns near the trailing edge of the output clock (CKO). If an external
device overwrites the PDR, the DMA transaction is
not completed. The status of the parallel data full
(PDF) flag and associated pin may be corrupted during this transaction.
A DMA read transaction may fail if the falling edge of
PEN or PGN aligns near the falling edge of CKO. The
PDF flag and associated pin may not correctly
assume a deasserted state.
The failure occurs only when the DSP operates at a
clock frequency greater than 66 MHz, and CKO is
asynchronous with respect to the PEN, PWN, and
PGN signals. To eliminate this potential problem, a
synchronous clocking scheme is needed. This clocking scheme prevents PEN, PWN and PGN from falling a minimum of 3 ns before the falling edge of CKO.
See Figure 2.
Data Sheet Addendum
November 1996
DSP32C Digital Signal Processor
Timing Characteristics
STRAP S AND C TO +5 V
10
FROM CONTROLLER
PORT ENABLE
DSP CKO
13
S
12
11
C
D
Q
9
TO DSP PEN
CP
1/2
F74
STRAP S AND C TO +5 V
10
FROM CONTROLLER
WRITE ENABLE
DSP CKO
13
S
12
11
C
D
Q
9
TO DSP PWN
CP
1/2
F74
STRAP S AND C TO +5 V
10
FROM CONTROLLER
READ ENABLE
DSP CKO
13
S
12
11
D
C
Q
9
TO DSP PGN
CP
1/2
F74
5-5004 (C)
Figure 1. Hardware Workaround
2
Lucent Technologies Inc.
Data Sheet Addendum
November 1996
DSP32C Digital Signal Processor
Timing Characteristics (continued)
CKI
CKO
tCKOHCHOH
PEN
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
PWN
PGN
PEN, PGN, PWN
MUST NOT FALL
IN THIS TIME SLOT
5-5005 (C)
Figure 2. Hardware Workaround Timing
Lucent Technologies Inc.
3
Data Sheet Addendum
November 1996
DSP32C Digital Signal Processor
Timing Characteristics (continued)
CKO VOM–
t91
PAB
VIH–
VIL–
t68
t69
READ
OR
WRITE
t70
WRITE
(PEN + PWN) VIM–
t71
PDB
VIH–
t76g
t72
DATA IN
VIL–
t73
PDF
VOM–
t73a
PIF VOM–
5-3629 (C).a
Figure 3. PIO Timing—Write Cycle (PGN High)
Table 1. Timing Characteristics for PIO Write Cycle (See Figure 3.)
Abbreviated Reference
IEEE * Symbol
Parameter
50 ns
Min
Max†
t68
tPAVPWL
Address Setup
5
—
t69
tPWHPAX
Address Hold
0
—
t70
tPWLPWH
Write Pulse
2T
—
t71
tPDVPWH
Data Setup
10
—
t72
tPWHPDX
Data Hold
0
—
t73
tPWHPDFH
PDF Write Delay
—
T + 15
t73a
tPWHPIFH
PIF Write Delay
—
T + 15
2T
—
3
—
‡
t76g
tPRWHPRWL
PIO Idle
t91
tPWNLCKOL
Write Setup
* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
† T = tCKILCKIL (system clock period).
‡ A minimum 2 x T interval is required for the start of the read or write cycle following the end of the previous read or write
cycle.
4
Lucent Technologies Inc.
Data Sheet Addendum
November 1996
DSP32C Digital Signal Processor
Timing Characteristics (continued)
CKO VoM–
t91a
PAB
VIH–
VIL–
t65
t64
READ
OR
WRITE
t70a
READ
VIM–
(PEN + PWN)
t76g
t67
PDB
VOH–
DATA OUT
VOL–
t66
PDF1 VOM–
t74
PIF1 VOM–
t75
t76a
PDF2 VOM–
t76
PIF2 VOM–
5-3629 (C).b
Notes:
PDF1 and PIF1 reflect the timing when PCR [10] = 0.
PDF2 and PIF2 reflect the timing when PCR [10] = 1.
Figure 4. PIO Timing—Read Cycle (PWN High)
Table 2. Timing Characteristics for PIO Read Cycle (See Figure 4.)
Abbreviated Reference
IEEE Symbol
Parameter
50 ns
Min
Max*
t64
tPAVPRL
Address Setup
5
—
t65
tPRHPAX
Address Hold
0
—
t66
tPRLPDV
Access from Read
—
17
t67
tPRHPDZ
Data Hold from Read
2
7
t70a
tPRLPRH
Read Pulse
2T
—
t74
tPRLPDFL
PDF Read Delay
—
15
t75
tPRLPIFL
PIF Read Delay
—
15
t76
tPRHPIFL
PIF Read Delay
—
T + 15
t76a
tPRHPDFL
PDF Read Delay
—
T + 15
t76g
tPRWHPRWL
†
PIO Idle
2T
—
t90a
tPGNLCKOL
Read Setup
3
—
* T = tCKILCKIL (system clock period).
† A minimum 2 x T interval is required for the start of the read or write cycle following the end of the previous read or write
cycle.
Lucent Technologies Inc.
5
DSP32C Digital Signal Processor
Data Sheet Addendum
November 1996
Notes
6
Lucent Technologies Inc.
Data Sheet Addendum
November 1996
DSP32C Digital Signal Processor
Notes
Lucent Technologies Inc.
7
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET: http://www.lucent.com/micro
U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103,
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106), e-mail docmaster@micro.lucent.com
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Tel. (65) 778 8833, FAX (65) 777 7495
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Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
For data requests in Europe:
MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 324 299, FAX (44) 1734 328 148
For technical inquiries in Europe:
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Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.
Copyright © 1996 Lucent Technologies Inc.
All Rights Reserved
Printed in U.S.A.
November 1996
DA96-015WAM (Must Accompany DS94-084DCON)
Printed On
Recycled Paper
RT
Data Sheet
June 1995
DSP32C Digital Signal Processor
with External Memory Interface
Introduction
Description
AT&T is an industry leader in floating-point digital
signal processing. AT&T's DSP32 architecture was
introduced in 1985 and is now the accepted standard in the speech, signal processing, and telecommunications application areas.
The AT&T DSP32C Digital Signal Processor is a
32-bit, floating-point, programmable integrated circuit. As the second generation to the DSP32, it has
access to a large base of both software and hardware support.
The DSP32C device offers more than three times
the throughput of the DSP32 while offering pin,
source code, and object code upward compatibility.
In addition to powerful DSP devices, AT&T offers
application support to its customers. Application
support is supplied by field engineers, application
notes, application software, and a 24-hour bulletin
board.
The DSP32C is fabricated in AT&T's high-speed,
low-power CMOS technology. Packaging options for
the DSP32C with External Memory Interface include
a standard 133-pin, square ceramic pin-grid-array
(CPGA) package and a 164-pin, JEDEC standard
bumpered quad flat pack (BQFP) package.
Software and hardware development tools are available from both AT&T and third parties to speed development schedules. These tools include a device
software simulator, hardware development board,
and in-circuit emulator. The DSP32C product family
offers high processing power, ease of use, and excellent development support.
Two execution units, the control arithmetic unit
(CAU) and the data arithmetic unit (DAU), operate in
parallel to achieve high throughput. The CAU performs 16- or 24-bit fixed-point arithmetic for logic and
control functions. This unit, which includes 22 general-purpose registers, can execute 20 million instructions per second (MIPS). The DAU performs
32-bit floating-point arithmetic for signal processing
functions. Four 40-bit accumulators are used as inputs/outputs to a floating-point multiplier and a floating-point adder that work in parallel to perform
40 million floating-point operations per second
(MFLOPS).
Table 1. DSP32C Products
Device Code
RAM
Instruction Cycle Time
DSP32C-R35
DSP32C-F35
DSP32C-M4*
3 - 0.5K x 32
3 - 0.5K x 32
4 - 0.5K x 32
80 ns, 60 ns, or 50 ns
80 ns, 60 ns, or 50 ns
80 ns, 70 ns
External Memory
Interface
Yes
Yes
No
* This version of the DSP32C is described in the AT&T DSP32C Without External Memory Interface Data Sheet.
Package
133 CPGA
164 BQFP
68 PLCC
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Table of Contents
Contents
Page
Introduction.......................................................................................................................................................... 1
Description........................................................................................................................................................... 1
Architecture ......................................................................................................................................................... 5
Control Arithmetic Unit (CAU) ....................................................................................................................... 5
Data Arithmetic Unit (DAU) ........................................................................................................................... 5
Internal and External Memory ....................................................................................................................... 5
Serial I/O Unit (SIO) ...................................................................................................................................... 6
Parallel I/O Unit (PIO) ................................................................................................................................... 6
Memory Configuration................................................................................................................................... 6
Memory Addressing ...................................................................................................................................... 8
Interrupt Operation ........................................................................................................................................ 9
Instruction Set .....................................................................................................................................................10
Flags ............................................................................................................................................................ 11
Data Arithmetic (DA) Instructions .................................................................................................................12
Control Arithmetic (CA) Instructions .............................................................................................................14
Instruction Encoding ........................................................................................................................................... 18
DA Instruction Formats ................................................................................................................................18
Encoding for DA Instruction Formats ........................................................................................................... 19
CA Instruction Formats (Eight Format Groups)............................................................................................20
CAU Encoding for CA Instruction Formats .................................................................................................. 23
Register Operation .............................................................................................................................................26
Input/Output Control (ioc) Register ..............................................................................................................26
DAU Control (dauc) Register .......................................................................................................................28
Parallel I/O Register Selection ..................................................................................................................... 29
Parallel I/O Control Register (pcr) ................................................................................................................ 30
Error Source Register (esr) ..........................................................................................................................31
Error Mask Register (emr) ...........................................................................................................................32
Processor Control Word (pcw) Register ...................................................................................................... 33
Pin Information ................................................................................................................................................... 34
Pins by Functional Group Order ..................................................................................................................35
Pins by Numerical Order .............................................................................................................................. 41
Device Requirements and Characteristics .........................................................................................................51
Absolute Maximum Ratings ......................................................................................................................... 51
Handling Precautions ...................................................................................................................................51
Temperature Class Definitions..................................................................................................................... 52
Recommended Operating Conditions .......................................................................................................... 52
Package Thermal Considerations ................................................................................................................ 52
Electrical Characteristics ....................................................................................................................................53
Timing Requirements and Characteristics.......................................................................................................... 54
CKI and CKO Timing....................................................................................................................................54
External Memory Interface (EMI) Timing .....................................................................................................55
Serial I/O (SIO) Timing................................................................................................................................. 59
Parallel I/O (PIO) Timing .............................................................................................................................. 61
Reset and Interrupt Timing...........................................................................................................................62
Bus Request Timing.....................................................................................................................................64
Timing Diagrams ................................................................................................................................................ 65
8-Bit PIO ......................................................................................................................................................71
Outline Diagrams................................................................................................................................................ 74
133-Pin CPGA Package ............................................................................................................................. 74
164-Pin BQFP Package ............................................................................................................................. 75
2
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Description (continued)
Table 2. Features and Benefits of the DSP32C
Features
Full 32-bit floating-point architecture
Increased precision & dynamic range
Instruction started every instruction cycle
Four memory accesses per instruction cycle
Exceptional memory bandwidth
C-like assembly language
Serial and parallel ports with DMA
High bandwidth, nonintrusive I/O
Benefits
Simplifies program development to provide faster
time to market
Much easier algorithm development opens up
new application possibilities
Allows more complex functions or a greater number of simultaneous functions to be implemented
Eliminates memory accessing bottlenecks
Easy to learn/excellent readability
Clean interface to external devices
Lower system cost
Easy interface to PC buses
External control via parallel I/O (PIO)
Hardware data format conversions
Eliminates lengthy software routines
— IEEE* P754 floating-point
Permits shared data with host processor or other
platforms
— Integer conversions:
Increased throughput in:
8-bit unsigned
— Graphics and image processing
16-bit linear
— Applications with 16-bit data
24-bit linear
— HQ digital audio and control applications
— µ-law/A-law conversions
— Telecom and speech applications
Fully vectored interrupt structure with hardware Allows very fast interrupt processing (up to
context save
2 million interrupts/s)
Byte-addressable address space
Efficient storage of 8- and 16-bit data
Lower system cost
Flexible wait-state facility
Greater memory speed selection flexibility than
— Each wait-state is 1/4 instruction cycle
conventional full-cycle wait-states
— Two independent external memory speed Allows mixing of slow and fast memory
partitions
Optimizes system speed/cost requirements
* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Table 3. DSP32C with External Memory Interface Device Speed Options
Minimum Instruction
Cycle Time (ns)
Maximum Clock Frequency
(MHz)
50
80.000
60
66.666
80
50.000
AT&T Microelectronics
3
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Description (continued)
ASN,
MSN[3:0]
AB[21:00]
ADDRESS BUS (24)
MMD[2:0]
PIO
PAB[3:0]
PDB[15:00]
PEN
PGN
PWN
PDF
PIF
par (16)
pare (8)
pdr (16)
pdr2 (16)
pir (16)
pcr (16)
emr (16)
esr (8)
pcw (16)
piop (8)
RAM2
RAM
512 x 32
RWN, DSN, CYCLEIN,
CKO, MGN, MWN, EAPN
DB[31:00]
SRDYN
DI
ILD
ICK
IBF
DO
OLD
OCK
OBE
OSE
OEN
SY
CKI, RESTN, ZN, BREQN
INTREQ1, INTREQ2
IACK1, IACK2, BRACKN, CK0
RAM1
RAM0
RAM
512 x 32
RAM
512 x 32
DATA BUS (32)
DAU
SIO
ibuf (32)
ISR
obuf (32)
OSR
ioc (21)
(32)
(32)
FLOATINGPOINT
(32) MULTIPLIER
IR
ALU 16/24
IR1
(40)
(40)
CAU
PIPELINE
CONTROL
pc (24)
FLOATINGPOINT
ADDER
IR2
(40)
IR3
r1—r14 (24)
r15—r19 (24)
pin (24)
a0—a3 (40)
UTILITY
PINS
pout (24)
IR4
ivtp (24)
dauc
5-3614(C)
LEGEND:
a0—a3
ALU
CAU
DAU
dauc
emr
esr
ibuf
ioc
IR
Accumulators 0—3
Arithmetic logic unit
Control arithmetic unit
Data arithmetic unit
DAU control register
Error mask register
Error source register
Input buffer
Input/output control register
Instruction register
IR1—IR4
ISR
ivtp
obuf
OSR
par
pare
pc
pcr
pcw
Instruction register pipeline
Input shift register
Interrupt vector table pointer
Output buffer
Output shift register
PIO address register
PIO address register extended
Program counter
PIO control register
Processor control word
pdr
pdr2
pin
PIO
piop
pir
pout
r1—r19
RAM
SIO
PIO data register
PIO data register 2
Serial DMA input pointer
Parallel I/O unit
Parallel I/O port register
PIO interrupt register
Serial DMA output pointer
Registers 1—19
Read/write memory
Serial I/O unit
Figure 1. Block Diagram of the DSP32C with External Memory Interface
4
AT&T Microelectronics
Data Sheet
June 1995
Architecture
The DSP32C architecture is being used today to solve
a wide variety of complex problems. A large set of
general-purpose registers simplifies assembly-language programming and allows very efficient compiler
implementations. Both internal and external memory
are treated as a general resource allowing the programmer to freely mix both programs and/or data
within the 16 Mbyte address space.
In addition to its powerful number-crunching capabilities and flexible memory organization, the DSP32C offers many features that allow it to be easily and quickly
integrated into real world systems.
A block diagram of the DSP32C with External Memory
Interface appears in Figure 1. The following subsections describe the components shown in this diagram.
Control Arithmetic Unit (CAU)
The CAU generates memory addresses and performs
16- or 24-bit integer arithmetic at the rate of 20 million
instructions per second. The CAU consists of a 24-bit
arithmetic logic unit (ALU) which performs the integer
arithmetic and logical operations, a 24-bit program
counter (pc) register, and 22 general-purpose 24-bit
registers. All 22 registers can be used for operands in
the execution of 16- or 24-bit integer operations; however, some of these registers also serve special purposes. When addressing 32-bit floating-point
operands, registers r1—r14 are used as memory
pointers (rP), and r15—r19 are used as increment
registers (rI). Register r20, also called pin, is used as
the serial DMA input pointer. Register r21, also called
pout, is used as the serial DMA output pointer.
Register r22, also called interrupt vector table pointer
(ivtp), is used as the base address for the interrupt
vector table.
Data Arithmetic Unit (DAU)
The DAU is configured for multiply/accumulate operations and is the primary execution unit for signal-processing algorithms. The DAU contains a floating-point
multiplier and a floating-point adder, and four 40-bit
accumulators (a0—a3). The multiplier and adder work
in parallel to perform 20 million instructions per second
of the form a = b + c * d. The DAU multiplier operands
(c and d) are 32-bit floating-point numbers (an 8-bit
AT&T Microelectronics
AT&T DSP32C Digital Signal Processor
with External Memory Interface
exponent and a 24-bit mantissa) from memory or an
accumulator. The multiplier always provides one
40-bit input to the adder. The other input can originate
from memory, the I/O ports, or an accumulator. The
operands for this second adder input can be 8-, 16-,
24-, 32-, or 40-bit numbers. The 40-bit operands (8-bit
exponent, 24-bit mantissa, and eight mantissa guard
bits) come from an accumulator (a0—a3). The 8-, 16-,
and 24-bit operands are used in special function instructions whose purpose is data-type conversion. For
either conversions or addition operations, 32-bit
operands may come from memory or I/O registers.
Available conversions are between the DSP32C floating-point format and the following: 8-, 16-, and
24-bit two's complement integer, µ-law, A-law, and
single-precision IEEE floating-point format.
Internal and External Memory
The DSP32C provides on-chip RAM and an external
memory interface for off-chip ROM and/or RAM expansion. All memory can be addressed as 8-, 16-, 24-,
or 32-bit words, with 32-bit data accessed at the same
speed as 8-bit data. Instructions, tables, and data can
be arbitrarily located in on-chip RAM or external memory. The addresses of the various blocks of memory
can be configured in eight different memory modes.
Four of the memory modes provide a DSP32-compatible 16-bit address space. The other four memory
modes provide a full 24-bit address space. See the
Memory Configuration section for more information on
configuring the address space. Regardless of the configuration, the first instruction executed after reset is at
address 0x000000.
Internally, the DSP32C device has 1,536 words of
RAM which are available in all memory configurations.
The on-chip RAM is static and does not need to be refreshed.
The external memory interface can directly address up
to 16 Mbytes of additional memory. The interface supports wait-states and bus arbitration. The external
memory is divided into two sections: a low partition (A)
and a high partition (B). The number of wait-states for
each partition is independently configurable (see
Register Operation, Table 25, pcw Register). Therefore, a mix of slow and fast memories can be used to
provide the necessary throughput at a reasonable
cost.
5
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Architecture (continued)
Memory Configuration
Serial I/O Unit (SIO)
The addresses of the various blocks of memory can be
configured in eight different memory modes. Four of
the memory modes (0—3) provide a DSP32-compatible, 16-bit address space. The other four memory
modes (4—7) provide a full 24-bit address space. Pin
MMD2 selects either the DSP32 compatible 16-bit address space or the expanded 24-bit address space.
Pins MMD0 and MMD1 select memory modes that
determine the location of on-chip memory resources in
the memory address space. Figure 2 shows the
location of memory resources.
The serial I/O unit is used for serial-to-parallel conversion of input data and parallel-to-serial conversion of
output data. SIO inputs are loaded into the input shift
register (ISR) and then into the input buffer (ibuf). SIO
outputs are loaded into the output buffer (obuf) and
then into the output shift register (OSR). This doublebuffering makes back-to-back transfers possible, allowing the DSP32C program to begin a second transfer before the first has been completed. Data widths
can be 8, 16, 24, or 32 bits. The input/output control
(ioc) register in the SIO is used to select various I/O
configurations, bit lengths, internal or external clocks,
and internal or external synchronization (see Register
Operation, Table 19, ioc Register).
Parallel I/O Unit (PIO)
The parallel I/O unit is an on-chip register file and bidirectional data bus that can be used for communication between the DSP32C device and an external device. The external PIO data bus can be 8 or 16 bits
wide. PIO data transfers are made under program or
DMA control. Using PIO DMA, an external device can
download a program or data without interrupting execution of the DSP32C program. The PIO has three 16bit data registers (pdr, pdr2, and pir), a 24-bit address
register (par/pare), a 16-bit processor control word
(pcw), an 8-bit I/O port register (piop), a 16-bit control
register (pcr), a 16-bit error mask register (emr), and
an 8-bit error source register (esr). These registers
are used to control PIO transfers and configure error
control and interrupt features (see Register Operation).
6
Memory accesses can be made without regard to the
type or location of the physical memory; however, to
achieve maximum throughput, instruction/data memory
accesses of floating-point operations must alternate
between physical memories. There are four physical
memories: (1) RAM0, (2) RAM1, (3) external memory
A and B, and (4) RAM2.
The number of wait-states for the external memory
partitions A and B are independently configurable via
the MEMA and MEMB fields of the pcw register. The
number of wait-states may be statically configured or
externally controlled. Statically configured waits of 1,
2, or 3 states allow the DSP32C to access memory
without delays for handshaking (a state is one period
of CKI, or 12.5 ns at maximum clock frequency).
When configured for two or more externally controlled
wait-states, the DSP32C generates wait-states until
the memory acknowledges the transaction via the synchronous ready (SRDYN) handshaking signal.
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Architecture (continued)
Memory Configuration (continued)
MMD2 = 0
(MODES 0—3)
BANK 1
BANK 0
0x0000
0x07FF
0x0800
0x0FFF
0x1000
MMD2 = 1
(MODES 4—7)
0x000000
0x0007FF
0x000800
0x000FFF
0x001000
0x7FFF
0x5FFFFF
0x8000
0x600000
MMD0 = 0
MMD1 = 0
MMD0 = 1
MMD1 = 0
RAM2
RAM2
RAM0
EXTERNAL
MEMORY
A
MMD0 = 0
MMD1 = 1
MMD0 = 1
MMD1 = 1
RAM0
EXTERNAL
MEMORY
A
EXTERNAL
MEMORY
A
EXTERNAL
MEMORY
A
EXTERNAL
MEMORY
B
EXTERNAL
MEMORY
B
EXTERNAL
MEMORY
B
EXTERNAL
MEMORY
B
0xDFFF
0xFFDFFF
0xE000
0xE7FF
0xFFE000
0xFFE7FF
RESERVED
RESERVED
RAM2
RAM2
0xE800
0xEFFF
0xFFE800
0xFFEFFF
RESERVED
RESERVED
RESERVED
RESERVED
0xF000
0xF7FF
0xFFF000
0xFFF7FF
RAM0
RESERVED
RAM0
RESERVED
0xF800
0xFFFF
0xFFF800
0xFFFFFF
RAM1
RAM1
RAM1
RAM1
MODE 0/4
MODE 1/5
MODE 2/6
MODE 3/7
5-3619(C)
Figure 2. DSP32C Memory Configurations
AT&T Microelectronics
7
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Architecture (continued)
Memory Addressing
Each 32-bit word is organized as 4 bytes, e.g., 3, 2, 1,
0, where byte 3 is the most significant byte (MSbyte)
and byte 0 is the least significant byte (LSbyte) (see
Table 4, Memory Addressing). A 16-bit integer is
2 bytes, either 1, 0 (with byte 1 the MSbyte and byte 0
the LSbyte) or 3, 2 (with byte 3 the MSbyte and byte 2
the LSbyte).
Integer operands of 24 bits are organized as 4 bytes.
Byte 2 is the MSbyte, byte 0 is the LSbyte, and byte 3
is a sign extension of byte 2. Integer operands of
24 bits are addressed the same as 32-bit words.
Memory address 0 can refer to an 8-bit byte (byte 0), a
16-bit integer (bytes 1, 0), a 24-bit integer (bytes 2, 1,
0), or a 32-bit word (bytes 3, 2, 1, 0).
The external memory is accessed by a 22-bit external
address bus (AB00—AB21) and four byte select lines
(MSN0—MSN3) (see Table 5, Data Type Memory
Select and Write Data). The bus obtains its data from
the 22 most significant bits of the address bus and selects a 32-bit word in memory. The four byte select
signals (active-low) select bytes within the 32-bit word
(see Pin Information). The value of the byte select
lines is determined by the two least significant bits of
the address and the data type implied in the instruction. The address is specified either directly or via a
register pointer (pc, r1—r22). With the maximum external memory attached, one can address a total of
16M bytes, 8M 16-bit integers, 4M 24-bit integers, or
4M 32-bit words.
Table 4. Memory Addressing
32-Bit Word
16-Bit Integer
Byte
3
7
11
Byte
2
6
10
24-Bit Integer
16-Bit Integer
Byte
1
5
9
etc.
Memory
Address
Byte
0
4
8
0
4
8
Table 5. Data Type Memory Select and Write Data
Data Type
Byte 0
Byte 1
Byte 2
Byte 3
Low 16-bit
High 16-bit
32-bit/24-bit
Data Type Memory Select
MSN3
MSN2
MSN1
1
1
1
1
1
0
1
0
1
0
1
1
1
1
0
0
0
1
0
0
0
MSN0
0
1
1
1
0
1
0
24—31
A
B
C
D
B
D
D
DSP32C Write Data*
16—23
8—15
A
A
B
B
C
C
D
D
A
B
C
D
C
B
0—7
A
B
C
D
A
C
A
* A = write data DB00—DB07; B = write data DB08—DB15; C = write data DB16—DB23; D = write data DB24—DB31.
8
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Architecture (continued)
Interrupt Operation
The DSP32C provides a single-level interrupt facility
with six sources (four internal and two external). The
interrupts are prioritized and are individually maskable
via the INTER field of the pcw register. The sources
are described below in descending priority:
1. External Interrupt One (INTREQ1) — level sensitive.
2. Parallel Buffer Full (PDF) — generated when the
pdr register is loaded.
3. Parallel Buffer Empty (PDE) — generated when
the pdr register is read.
4. SIO Input Buffer Full (IBF) — generated when the
IBF flag is set.
5. SIO Output Buffer Empty (OBE) — generated
when the OBE flag is set.
Before servicing an interrupt, the DSP32C saves the
state of the machine that is invisible to the programmer, as well as DAU accumulators a0—a3 and the
dauc register. Internal states that are visible to the
programmer and need to be saved, except a0—a3 and
the dauc, must be saved and restored by the interrupt
service routine. In response to a given interrupt, the
DSP32C branches to the corresponding address in the
interrupt vector table. The interrupt vector table
contains six pairs of 32-bit words starting at the
location specified in the interrupt vector table pointer
register ivtp (r22). Each pair of words in the table
should contain an unconditional branch to the
appropriate interrupt routine. Note that even when
masked, the interrupt conditions may be tested in
conditional branch instructions (see Instruction Set).
Figure 3 is a memory map of the interrupt vector table.
To return to the interrupted program, the user should
restore the user-visible state of the DSP32C (which
was saved), and then execute the ireturn instruction.
The latter operation restores a0—a3 and the state of
the machine that is not visible to the user.
6. External Interrupt Two (INTREQ2) — level sensitive.
ADDRESS
ivtp+0
+8
32 BITS
INTERRUPT SOURCE
EXTERNAL INTERRUPT 1
PIO BUFFER FULL
+16
PIO BUFFER EMPTY
+24
SIO INPUT BUFFER FULL
+32
SIO OUTPUT BUFFER EMPTY
+40
EXTERNAL INTERRUPT 2
+48
RESERVED
+56
RESERVED
5-3621(C)
Figure 3. Interrupt Vector Table
AT&T Microelectronics
9
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Instruction Set
Table 6. Features and Benefits of the DSP32C Instruction Set
Features
Instruction started every instruction cycle
Benefits
Allows more complex or a greater number of applications to be implemented
Full set of microprocessor-like instructions
Expands the number of applications that can be efficiently handled
Conditional branches
Simplifies programming task*
Conditional ALU operations
Permits very fast, efficient coding*
Eliminates unnecessary branch instructions
Single-cycle pc-relative addressing for position-inde- Simplifies multitask applications*
pendent code
Data stationary coding
Enables parallel operation of arithmetic and logical
operations
Allows efficient compiler implementations*
Provides automatic pipeline control*
Simplifies program development process*
* Provides faster time to market.
The DSP32C assembly language frees programmers
from tedious memorization of assembly-language
mnemonics. Instructions in the DSP32C are patterned
after the C programming language and are entered in
a natural equation syntax. In addition to being easier
to learn, the resulting code is far more readable than
mnemonic-based assembly languages, making code
maintenance much easier.
C-like assembly language →
Easy to learn/excellent
readability
Assembly-language example (32-bit multiply/ accumulate with store to memory):
*r1++ = a0 = a1 + *r2++ * *r3++
The execution of this instruction simply follows the
conventions of the high-level C programming language:
The DSP32C has two general types of instructions that
correspond to the two execution units: data arithmetic
(DA) instructions and control arithmetic (CA) instructions.
Primarily, DA instructions perform 32-bit floating-point
multiply/accumulate operations for signal processing
algorithms. Other DA instructions convert the
DSP32C's internal floating-point data to and from each
of the following types: 8-bit, 16-bit, or 24-bit 2's complement integer; µ-law; A-law; or single-precision IEEE
floating-point.
The CA instructions perform microprocessor operations such as 16-bit and 24-bit integer arithmetic and
logic functions, conditional branching, and moving
data.
“Multiply the 32-bit floating-point values stored in the
memory locations pointed to by registers r2 and r3.
Add the result to the contents of accumulator a1, store
the result in accumulator a0, and write the result to the
32-bit memory location pointed to by register r1. Postincrement pointer registers r1, r2, and r3.”
10
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Instruction Set (continued)
Flags
The DSP32C has internal flags that are affected by the results of certain DA, CA, or I/O instructions and certain
I/O events. These flags, although not directly visible to the user, may be tested by conditional instructions.
Table 7 lists the flags and their meanings.
Table 7. DSP32C Flags
DAU Flags
Flag
N
Z
V
U
Meaning (Flag = 1)
Result is negative
Result is zero
Result overflowed*
Result underflowed*
n
Result is negative
z
Result is zero
c
Carry or borrow out of MSB
v
Result overflowed
i
o
p
P
s
b
r
R
Serial input buffer full
Serial output buffer full
Parallel data register full
Parallel interrupt register full
SY (I/O sync) set (1)
Serial I/O frame boundary
Interrupt pin 1 high (1)
Interrupt pin 2 high (1)
Description
Sign bit = 1.
All 40 bits of accumulator = 0.
| DAU result | > 3.40282 E 38.
| DAU result | < 5.87747 E –39.
CAU Flags
(16-bit) n = b23 (bit 23 of ALU result).
(24-bit) n = b23.
(16-bit) z = b23 + b22 + . . . b1+ b0 (+ = OR).
(24-bit) z = b23 + b22 + . . . b1+ b0.
(16-bit) c = b15c (carry out of ALU bit 15).
(24-bit) c = b23c.
(16-bit) v = b14c ^ b15c (^ = exclusive OR).
(24-bit) v = b22c ^ b23c.
I/O Flags
Pin IBF = 1.
Pin OBE = 0.
Pin PDF = 1.
Pin PIF = 1.
Pin SY = 1.
fbs = 1.
Pin INTREQ1 = 1.
Pin INTREQ2 = 1.
* The DSP3207 Digital Signal Processor Information Manual dated July 1994, Section 3.3.3, contains a detailed description of the floating-point formats and exceptions. The DSP3207 floating-point format and arithmetic is identical to
that of the DSP32C.
DSP32C instructions and the flags affected by each instruction are specified in the following tables. A zero (0)
shown in place of a flag means that the flag is always made zero; a dash (—) in place of a flag means that the flag
is unaffected by the instruction.
The complete DSP32C instruction set, grouped as DA and CA instructions, follows. Where braces, { }, are shown
in an instruction, one of the enclosed items must be chosen. Items enclosed in brackets, [ ], are optional.
Note:
{ } and [ ] are not part of the instruction syntax. Parentheses, ( ), are part of the syntax and must appear
where shown in an instruction. Lower-case letters are part of the syntax and upper-case letters are replaced by immediate data or by a register name (see tables following each instruction group).
AT&T Microelectronics
11
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Instruction Set (continued)
Data Arithmetic (DA) Instructions
The DA instructions are divided into two functional groups: multiply/accumulate and special functions.
Table 8. Data Multiply/Accumulate Instructions
Instruction
[Z=] aN = [–]aM {+,–} Y *X
DAU Flags
Affected
NZVU
aN = [–]aM {+,–} (Z=Y)*X
NZVU
[Z=] aN = [–]Y {+,–} aM *X
NZVU
[Z=] aN = [–]Y*X
NZVU
aN = [–](Z=Y) *X
NZVU
[Z=] aN = [–]Y {+,–}X
NZVU
[Z=] aN = [–]Y
NZVU
aN = [–](Z=Y) {+,–} X
NZVU
Description
The product of the X and Y fields is added to or subtracted from
the accumulator aM (or its negative), and the result is stored in
accumulator aN. The result can also be output according to the
Z field.
The Y field operand is output according to the Z field. The
product of the X and Y fields is added to or subtracted from the
accumulator aM (or its negative), and the sum is stored in accumulator aN.
The product of the X field and the accumulator aM is added to
or subtracted from the Y field (or its negative). The result is
placed in accumulator aN and can also be output according to
the Z field.
The product of the X and Y fields is added to or subtracted from
zero. The result is stored in accumulator aN and can also be
output according to the Z field.
The value of the Y field is output according to the Z field. The
product of the Y and X fields (or the negative of the product) is
stored in accumulator aN.
The sum or difference of the Y and X fields is stored in accumulator aN, and the result can also be output according to the Z
field. Note that X is a multiplier input.
The value of the Y field (or its negative) is placed in accumulator aN and can also be output according to the Z field.
The sum or difference of the Y and X fields is stored in accumulator aN, and Y can also be output according to the Z field.
Table 9. Replacement Table for DA Multiply/Accumulate Instructions
Replace
aN, aM
X, Y
Z
Value †
a0—a3
*rP, *rP++, *rP– –, *rP++rI
a0—a3
ibuf
*rP, *rP++, *rP– –,
*rP++rI, *rP++rIr
obuf
pdr
Description
One of the four DAU accumulators.
32-bit memory location.
One of the four DAU accumulators.
SIO input buffer.
32-bit memory location.
rIr indicates carry reverse add.
SIO output buffer.
PIO data register (pdr concatenated with pdr2).
† rP refers to r1—r14 and is used as a memory pointer. rI refers to r15—r19 and is used as an increment pointer.
12
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Instruction Set (continued)
Data Arithmetic (DA) Instructions (continued)
Table 10. DA Special Function Instructions
Instruction
[Z=] aN = ic(Y)
[Z=] aN = oc(Y)
[Z=] aN = float(Y)
[Z=] aN = float24(Y)
[Z=] aN = int(Y)
[Z=] aN = int24(Y)
[Z=] aN = round(Y)
[Z=] aN = ifalt(Y)
[Z=] aN = ifaeq(Y)
[Z=] aN = ifagt(Y)
[Z=] aN = dsp(Y)
[Z=] aN = ieee(Y)
[Z=] aN = seed(Y)
DAU Flags
Affected
NZ00
—
NZ00
NZ00
—
—
NZVU*
—
—
—
NZVU*
—
NZ0U*
Description
Input conversion, µ-law, A-law, 8-bit linear to float.
Output conversion, float to µ-law, A-law, 8-bit linear (see Table 20).
16-bit integer to float.
24-bit integer to float.
Float to 16-bit integer (round or truncate, dauc[4]).
Float to 24-bit integer (round or truncate, dauc[4]).
Round float (40-bit) to float (32-bit).
If (aN < 0) then [Z =] aN = Y else [Z =] aN.
If (aN = 0) then [Z =] aN = Y else [Z =] aN.
If (aN > 0) then [Z =] aN = Y else [Z =] aN.
IEEE-to-DSP32 format conversion.
DSP32-to- IEEE format conversion.
32-bit to 32-bit reciprocal program seed.
* The DSP3207 Digital Signal Processor Information Manual dated July 1994 contains detailed descriptions of underflow and overflow
for the round, dsp, and seed instructions. These descriptions can be found in the detailed descriptions of each instruction in
Section 4.7 of the manual. The DSP3207 floating-point format, arithmetic, and the round, dsp, and seed instructions are identical to
the DSP32C.
Table 11. Replacement Table for DA Special Function Instructions
Replace
aN
Y‡
Z
Value †
a0—a3
*rP, *rP++, *rP– –, *rP++rI
a0—a3
ibuf
pdr
*rP, *rP++, *rP– –, *rP++rI
obuf
pdr
Description
One of the four DAU accumulators.
32-bit memory location.
One of the four DAU accumulators.
SIO input buffer.
PIO data register (pdr).
32-bit memory location.
SIO output buffer.
PIO data register (pdr concatenated with pdr2).
† rP refers to r1—r14 and is used as a memory pointer. rI refers to r15—r19 and is used as an increment pointer.
‡ Y may not be a0—a3 for the float or dsp special functions.
AT&T Microelectronics
13
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Instruction Set (continued)
Control Arithmetic (CA) Instructions
Table 12. CA Control Instructions
Instruction
if (CA COND) goto {rH, N, rH+N,}
if (rM– –>= 0) goto {rH, N, rH+N,}
if (DA COND) goto {rH, N, rH+N,}
if (IO COND) goto {rH, N, rH+N,}
call {rH, N, M, rH+N,} (rM)
return (rM)
ireturn
do J,{K,rH}
goto {rH, N, M, rH+N}
nop
Flags
Affected
None
Instruction
Format
0
3a
0
0
4
0
0
3b, 3c
0
0
Description
Conditional branch.
Conditional branch.
Conditional branch.
Conditional branch.
Call subroutine.
Return from subroutine.
Return from interrupt.
Do next J + 1 instructions.
K + 1 (or rH + 1) times.
J = 0, 1, 2 . . . 31.
K = rH = 0, 1, 2 . . . 2047.
Unconditional branch.
No operation.
Notes:
The do instruction and the instructions it encompasses are not interruptible, except for the last instruction during the last iteration.
Further, the do instruction cannot be used in an interrupt routine.
A do loop should not contain any goto or call instructions. The assembler does not issue any warnings or errors if this is attempted.
Table 13. Replacement Table for CA Control Group Instructions, CA Conditions (CA COND)
Value
pl
mi
ne
eq
vc
vs
cc
cs
ge
lt
gt
le
hi
ls
CAU Flags*
n=0
n=1
z=0
z=1
v=0
v=1
c=0
c=1
n^v=0
n^v=1
z | (n ^ v) = 0
z | (n ^ v) = 1
c|z=0
c|z=1
Description
Result is nonnegative (plus).
Result is negative (minus).
Result not equal to zero.
Result equal to zero.
Overflow clear, no overflow.
Overflow set, overflowed.
Carry clear, no carry.
Carry set, carry.
Greater than or equal to.
Less than.
Greater than.
Less than or equal to.
Greater than (unsigned number).
Less than (unsigned number).
* Symbol interpretation: ^ = XOR; | = OR.
14
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Instruction Set (continued)
Control Arithmetic (CA) Instructions (continued)
Table 14. Replacement Table for CA Control Group Instructions, DA Conditions (DA COND)
Value
ane
aeq
age
alt
avc
avs
auc
aus
agt
ale
DAU Flags
Z=0
Z=1
N=0
N=1
V=0
V=1
U=0
U=1
N|Z=0
N|Z=1
Description
Not equal to zero.
Equal to zero.
Greater than or equal to zero.
Less than zero.
Overflow clear, no overflow.
Overflow set, overflowed.
Underflow clear, no underflow.
Underflow set, underflowed.
Greater than zero.
Less than or equal to zero.
Table 15. Replacement Table for CA Control Group Instructions, I/O Conditions (IO COND)
Mnemonic
ibe
ibf
obe
obf
pde
pdf
pie
pif
syc
sys
fbc
fbs
ireq1_hi
ireq1_lo
ireq2_hi
ireq2_lo
Condition
ibf = 0
ibf = 1
obe = 1
obe = 0
pdf = 0
pdf = 1
pif = 0
pif = 1
sy = 0
sy = 1
fb = 0
fb = 1
ireq1 = 1
ireq1 = 0
ireq2 = 1
ireq2 = 0
AT&T Microelectronics
Description
Input buffer empty.
Input buffer full.
Output buffer empty.
Output buffer full.
Parallel data register empty.
Parallel data register full.
Parallel interrupt register empty.
Parallel interrupt register full.
Sync signal low.
Sync signal high.
Serial frame boundary clear.
Serial frame boundary set.
INTREQ1 pin is deasserted (1).
INTREQ1 pin is asserted (0).
INTREQ2 pin is deasserted (1).
INTREQ2 pin is asserted (0).
15
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Instruction Set (continued)
Control Arithmetic (CA) Instructions (continued)
Table 16. CA Arithmetic/Logic Instructions
Instruction
rD[e] = rH + N
rD[e] = rS1 + rS2
rD[e] = rD + rS
rD[e] = rS1 – rS2
rD[e] = rS2 – rS1
rD[e] = rD – {N, rS}
rD[e] – {N, rS}
rD[e] = {N, rS} – rD
rD[e] = rD & {N, rS}
rD[e] = rS1 & rS2
rD[e] & {N, rS}
rD[e] = rD | {N, rS}
rD[e] = rS1 | rS2
rD[e] = rD ^ {N, rS}
rD[e] = rS1 ^ rS2
rD[e] = rS / 2
rD[e] = rS >> 1
rD[e] = rS >>> 1
rD[e] = rS <<< 1
rD[e] = –rS
rD[e] = rS * 2
rD[e] = rD # {N, rS}
rD[e] = rS1 # rS2
rD[e] = rD &~ {N, rS}
rD[e] = rS1 &~ rS2
rD[e] = rS
rD[e] = rS {+,–} 1
CAU Flags
Affected
nzvc
Instruction
Format
5a, 5b
nzvc
nzvc
nzvc
nzvc
nzvc
nzvc
nzvc
nz00
nz00
nz00
nz00
nz00
nz00
nz00
nz0c
0z0c
nz0c
nzvc
nzvc
nzvc
nz0c
nz0c
nzvc
nzvc
nzvc
nzvc
6a, 6b
6a, 6b
6a, 6b
6a, 6b
6a, 6b, 6c, 6d
6a, 6b, 6c, 6d
6a, 6b, 6c, 6d
6a, 6b, 6c, 6d
6a, 6b
6a, 6b, 6c, 6d
6a, 6b, 6c, 6d
6a, 6b
6a, 6b, 6c, 6d
6a, 6b
6a, 6b
6a, 6b
6a, 6b
6a, 6b
6a, 6b
6a, 6b
6a, 6b, 6c, 6d
6a, 6b
6a, 6b, 6c, 6d
6a, 6b
6a, 6b
6a, 6b
Description
Three operand add with 16-bit sign extended
immediate.
Triadic add.
Dyadic add.
Triadic left subtract.
Triadic right subtract.
Right subtract.
Compare.
Left subtract.
AND.
Triadic AND.
Bit test.
OR.
Triadic OR.
XOR.
Triadic XOR.
Arithmetic right shift.
Logical right shift.
Rotate right through carry.
Rotate left through carry.
Negate.
Arithmetic left shift.
Dyadic carry reverse add.
Triadic carry reverse add.
Dyadic AND with complement.
Triadic AND with complement.
Assignment.
Increment/decrement.
Except for instructions with immediate operands (N), all CA arithmetic/logic instructions above may also be conditionally executed on the basis of CA conditions. The syntax is as follows:
if (CA COND) instruction
The optional e suffix is for 24-bit (extended) operands. Flags are set according to the rules for 24-bit operands.
N is always 16 bits, and bit 15 is extended to 24 bits, for 24-bit operations.
16
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Instruction Set (continued)
Control Arithmetic (CA) Instructions (continued)
Table 17. CA Data Move Instructions
Instruction
rD = N
rDe = M
{ioc†, dauc} = VALUE
{MEM, *N, obuf, piop} = {rSh, rSl}
{MEM, *N, obuf, pdr, pdr2, pir, pcw} = rS, pcsh
{MEM, *N, obuf} = rSe, pcshe
{rDh, rDl} = {MEM, *N, ibuf, piop}
rD = {MEM, *N, ibuf, pdr, pdr2, pir, pcw}‡
rDe = {MEM, *N, ibuf}
MEM = {ibufl, piop}
MEM = {ibuf, pdr, pdr2, pir, pcw}§
MEM = {ibufe, pdre} §
{obufl, piop} = MEM
{obuf, pdr, pdr2, pir, pcw} = MEM
{obufe, pdre} = MEM
†
‡
§
CAU Flags
Affected
nz00
—
—
—
—
—
nz00
nz00
nz00
—
—
—
—
—
—
Format
Description
6c
8b
5a
7
7
7
7
7
7
7
7
7
7
7
7
16-bit immediate load.
24-bit immediate load.
5- or 21-bit immediate load.
MEM, *N, piop, and obuf are 8 bits.
MEM, *N, and obuf are 16 bits.
MEM, *N, and obuf are 24 bits.
MEM, *N, piop, and ibuf are 8 bits.
MEM, *N, and ibuf are 16 bits.
MEM, *N, and ibuf are 24 bits.
8-bit transfer.
16-bit transfer.
32-bit transfer.
8-bit transfer.
16-bit transfer.
32-bit transfer.
ioc = VALUE may not be used in an interrupt routine.
rD = {pdr, pdr2, pir, pcw} cannot be used in the presence of 32-bit PIO DMA.
MEM = {pdr, pdr2, pir, pcw, pdre} cannot be used in the presence of PIO DMA.
Table 18. Replacement Table for All CA Instructions
Replace
rH
rM, rS, rD
rDh, rSh
Value
pc, r1—r22
r1—r22
r1—r22
rDl, rSl
r1—r22
MEM
*rP, *rP++, *rP– –,
*rP++rI, (P, I = 1—22)
16-bit number
24-bit number
21-bit number or
5-bit number
N
M
VALUE
AT&T Microelectronics
Description
One of 22 general-purpose registers, or the program counter.
One of 22 CAU registers.
High-order bits 8—15 are moved. The low-order bits 0—7 are cleared
for rD and remain unchanged for rS.
Low-order bits 0—7 are moved. The high-order bits are cleared for rD
and remain unchanged for rS.
32-bit, 16-bit, or 8-bit memory location.
Two's complement integer.
Two's complement integer.
VALUE is a 21-bit value for the ioc word and a 5-bit value for the dauc
word.
17
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Instruction Encoding
The following sections specify the device level encoding of the DSP32C instruction set.
DA Instruction Formats
Format 1. [Z=] aN = {+,–} Y {+,–} aM * X
Bit
31
30
29
Field
0
0
1
28
27
26
M
25
24
23
r
F
S
25
24
23
r
F
S
25
24
23
r
F
S
22
21
20—14
13—7
6—0
X
Y
Z
20—14
13—7
6—0
X
Y
Z
20—14
13—7
6—0
X
Y
Z
20—14
13—7
6—0
X
Y
Z
20—14
13—7
6—0
0000000
Y
z
N
Format 2. aN = {+,–} aM {+,–} (Z=Y) * X
Bit
31
30
29
Field
0
1
0
28
27
26
M
22
21
N
Format 3. [Z=] aN = {+,–} aM {+,–} Y * X
Bit
31
30
29
Field
0
1
1
28
27
26
M
22
21
N
Format 4. aN = {+,–} (Z = Y) {+,–} X
Bit
31
30
29
28
27
26
25
24
23
Field
0
0
1
1
1
0
r
F
S
22
21
22
21
N
Format 5. Special Function Instructions
Bit
31
30
29
28
27
26—23
Field
0
1
1
1
1
G
18
N
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Instruction Encoding (continued)
Encoding for DA Instruction Formats
G Field. Specifies a data-type conversion operation.
G
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Operation
ic (input conversion)
oc (output conversion)
float
int
round
ifalt
ifaeq
ifagt
Reserved
Reserved
float24
int24
ieee (convert DSP to IEEE)
dsp (convert IEEE to DSP)
seed
Reserved
M Field. Specifies the accumulator used or a
constant value.
M
000
001
010
011
100
101
110
111
Operation
a0
a1
a2
a3
0.0
1.0
Specifies Format 4 DAU instruction
Reserved
F Field. Specifies sign of operation (adder input).
F
0
1
Operation
+
–
AT&T Microelectronics
S Field. Specifies sign of operation (product).
S
0
1
Operation
+
–
r Field. Specifies bit-reversed addressing mode
(carry-reverse add with register).
r
0
1
Operation
Nonbit-reversed
Bit-reversed
X, Y, Z Fields. These fields indicate register direct or
register indirect modes. The 7-bit fields are divided
into two subfields, p and i (ppppiii). Bits 0—2 of the
7-bit field are labeled i. The i subfield specifies an
rI register in the CAU. Bits 3—6 are labeled p. The
p field specifies an rP register in the CAU.
p Field. Specifies register indirect: *rP, *rP++,
*rP– –, *rP++rI, *rP++rIr.
p
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Operation
Selects register direct†
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
Not allowed
† See i field (p = 0000).
19
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Instruction Encoding (continued)
i Field (p = 0000). Specifies a register-direct
operation: REG. This is a special case of the i field
(when p field equals zero).
Encoding for DA Instruction Formats
(continued)
i
000
001
010
011
100
101
110
111
N Field. Specifies the accumulator used.
N
00
01
10
11
Operation
a0
a1
a2
a3
i Field (p ≠ 0000). Specifies register-indirect: rI,
rP++rI.
i
000
001
010
011
100
101
110
111
Operation (p = 0000)
a0 – X, Y fields only
a1 – X, Y fields only
a2 – X, Y fields only
a3 – X, Y fields only
ibuf – X, Y fields only
obuf – Z field only
pdr – Y, Z fields
No write, Z field only
Operation (p ≠ 0000)
0
r15
r16
r17
r18
r19
–4(f), –2(i), –1(b)
+4(f), +2(i), +1(b)
CA Instruction Formats (Eight Format Groups)
Refer to CAU Encoding for CA Instruction Formats for an explanation of each field, except where actual bit values
(0, 1) are given.
Formats 0 and 1. Conditional Branch: 24-Bit Register-Indirect with 16-Bit Sign-Extended Offset.
Bit
31
30
29
28
27
26—22
21
20—16
15—0
Field
0
0
0
0
0
C
G
H
N
For ireturn instruction, C = 00000, G = 1, H = pcsh = 11110, N = 0.
For nop instruction, C = 00000, G = 0, H = 00000, N = 0.
Format 2. Reserved
Bit
31
30
29
28
27
26
25—20
19—15
14—10
9—5
4—0
Field
0
0
0
0
1
0
—
—
—
—
—
Format 3a. Loop Counter
Bit
31
30
29
28
27
26
25—21
20—16
15—0
Field
0
0
0
0
1
1
M
H
N
20
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Instruction Encoding (continued)
CA Instruction Formats (Eight Format Groups) (continued)
Format 3b. Do Instruction (Immediate)
Bit
31
30
29
28
27
26
25—21
20—16
15—11
10—0
Field
1
0
0
0
1
1
00000
J
00000
K
Format 3c. Do Instruction (Register)
Bit
31
30
29
28
27
26
25—21
20—16
15—5
4—0
Field
1
0
0
0
1
1
00001
J
00000000000
H
Format 4. Call: 24-Bit Register-Indirect with 16-Bit Immediate Offset
Bit
31
30
29
28
27
26
25—21
20—16
15—0
Field
0
0
0
1
0
0
M
H
N
Format 5a. 16-Bit Three Operand Add
Bit
31
30
29
28
27
26
25—21
20—16
15—0
Field
0
0
0
1
0
1
D
H
N
Format 5b. 24-Bit Three Operand Add with 16-Bit Sign-Extended Immediate
Bit
31
30
29
28
27
26
25—21
20—16
15—0
Field
1
0
0
1
0
1
D
H
N
Format 6a. 16-Bit Arithmetic/Logic Group — Register Source
Bit
31
30
29
28
27
26
25
24—21
20—16
15—13
12
11
10
9—5
4—0
Field
0
0
0
1
1
0
0
F
D
C*
G
E
K
S1
S2
* Three least significant bits of the C field (CA conditions only).
Format 6b. 24-Bit Arithmetic/Logic Group — Register Source
Bit
31
30
29
28
27
26
25
24—21
20—16
15—13
12
11
10
9—5
4—0
Field
1
0
0
1
1
0
0
F
D
C*
G
E
K
S1
S2
* Three least significant bits of the C field (CA conditions only).
Format 6c. 16-Bit Arithmetic/Logic Group — Immediate Operand
Bit
31
30
29
28
27
26
25
24—21
20—16
15—0
Field
0
0
0
1
1
0
1
F
D
N
Format 6d. 24-Bit Arithmetic/Logic Group — Immediate Operand
Bit
31
30
29
28
27
26
25
24—21
20—16
15—0
Field
1
0
0
1
1
0
1
F
D
N
AT&T Microelectronics
21
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Instruction Encoding (continued)
CA Instruction Formats (Eight Format Groups) (continued)
Format 7a. Data Move Group — Direct Memory Address
Bit
31
30
29
28
27
26
25
24
Field
0
0
0
1
1
1
0
T
23
22
21
20—16
15—0
0
H
N
W
Format 7b. Data Move Group — Pointer Increment, Memory Address
Bit
31
30
29
28
27
26
25
24
Field
0
0
0
1
1
1
1
T
23
22
W
21
20—16
15—11
10
1
H
—
r
9—5 4—0
P
I
Format 7c. Data Move Group — I/O
Bit
31
30
29
28
27
26
25
24
Field
0
0
0
1
1
1
1
T
23
22
W
21
20—16
15—10
9—5
4—0
0
H
—
00000
R
Format 7d. Data Move Group — Memory to I/O
Bit
31
30
29
28
27
26
25
24
Field
0
0
0
1
1
1
0
T
23
22
W
21
20—16
15—11
10
9—5
4—0
1
R
—
r
P
I
Format 8a. Unconditional Branch: 24-Bit Register-Indirect with 24-Bit Offset
Bit
31
30
29
28—21
20—16
15—0
Field
1
0
1
NE
H
N
Format 8b. 24-Bit Immediate Load
Bit
31
30
29
28—21
20—16
15—0
Field
1
1
0
NE
H
N
Format 8c. Call Subroutine: 24-Bit Direct Immediate Address
Bit
31
30
29
28—21
20—16
15—0
Field
1
1
1
NE
M
N
22
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Instruction Encoding (continued)
CAU Encoding for CA Instruction Formats
C Field. Specifies a CA, DA, or I/O condition. For
Format 6a and 6b instructions, only CA conditions are
allowed, and are specified by the three least significant
bits of the C field.
C
Operation
00xxx
CA Condition
00000
00001
00010
00011
00100
00101
00110
00111
01xxx
01000
01001
01010
01011
01100
01101
01110
01111
10xxx
10000
10001
10010
10011
10100
10101
10110
10111
No condition
n
z
v
c
n^v
z | (n ^ v)
c|z
DA Condition
U
N
Z
V
N|Z
Reserved
Reserved
Reserved
I/O Condition
ibf
obe
pdf
pif
sy
fb
ireq1
ireq2
T Field. Specifies the direction of a transfer to or from
a register.
T
0
1
Operation
Data is moved to a register from memory
Data is moved to memory from a register
AT&T Microelectronics
E Field. Specifies whether the instruction is a two- or
three-operand instruction.
E
0
1
Operation
Two-operand instruction
Three-operand instruction (register source)
K Field. Specifies whether the instruction is to be executed based on the condition field.
K
0
1
Operation
Nonconditional execution
Conditional execution
W Field. Specifies the high or low byte or integer
data.
W
00
01
10
11
Operation
High byte
Low byte
Integer
32 bits
G Field. Specifies whether to branch if the condition
specified in the C field is true or false.
G
0
1
Operation
Branch if condition = 0
Branch if condition = 1
F Field. Specifies the arithmetic/logic group function
encoding.
F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Operation
+ addition
* 2 multiplication by 2
– subtraction {N, rS} – rD
# carry-reverse add
– subtraction rD – {N, rS}
– negation
& ≈ and with complement
– compare (no store)
^ exclusive or
>>>1 rotate right through carry
| bitwise OR
<<<1 rotate left through carry
>>1 shift right by 1
/2 divide by 2
& bitwise AND
& bitwise AND (no store)
23
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Instruction Encoding (continued)
CAU Encoding for CA Instruction Formats
(continued)
S, D, M, or H Fields. Used for register encoding.
S, D, M, or H
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
24
Operation
0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
Program counter (pc)
0
r15
r16
r17
r18
r19
–4(f), –2(i), –1(b)
+4(f), +2(i), +1(b)
r20 (pin)
r21 (pout)
dauc
ioc
Reserved
r22 (ivtp)
pcsh (pc shadow)
Reserved
P Field. Specifies a register-indirect data move: *rP,
*rP++, *rP– –, *rP++rI.
P
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Operation
Selects Format 7C
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
Reserved
Reserved
r15
r16
r17
r18
r19
Reserved
Reserved
r20 (pin)
r21 (pout)
Reserved
Reserved
Reserved
r22 (ivtp)
Reserved
Reserved
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Instruction Encoding (continued)
CAU Encoding for CA Instruction Formats
(continued)
I Field. Specifies a register-indirect operation.
I
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Operation
Reserved
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
Reserved
0
r15
r16
r17
r18
r19
–2(i), –1(b)
+2(i), +1(b)
r20 (pin)
r21 (pout)
Reserved
Reserved
Reserved
r22 (ivtp)
Reserved
Reserved
r Field. Specifies bit-reversed addressing mode
(carry-reverse add with register).
r
0
1
N Field. Specifies a 16-bit integer included as immediate data or as an address.
NE Field. Specifies most significant 8 bits of 24-bit
integer included as an immediate. NE concatenated
with N forms the 24-bit integer.
R Field (P = 00000). Specifies a register-direct operation. This field is valid when the P field is zero.
R
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
.
.
.
11101
11110
11111
Operation (P = 00000)
Reserved
Reserved
Reserved
Reserved
ibuf
obuf
pdr
Reserved
Reserved
Reserved
Reserved*
Reserved
Reserved
Reserved
piop
Reserved
Reserved
Reserved
Reserved
Reserved
pdr2
Reserved
pir
Reserved
.
.
.
Reserved
pcw
Reserved
* bkp access for development system use.
Operation
Nonbit-reversed
Bit-reversed
AT&T Microelectronics
25
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Register Operation
This section describes the register settings which control or display various operating conditions in the DSP32C
digital signal processor. Table 19 and Table 20 show the settings for the ioc and dauc registers. In Table 19,
internal refers to signals generated by the DSP32C; external refers to signals generated for the DSP32C by an
external device. The ioc register is cleared on reset.
Input/Output Control (ioc) Register
Table 19. Input/Output Control (ioc) Register
Bit
Field
Bit(s)
0
1
3, 2
4
5
7, 6
8
9
26
20
19
18
DSZ
O24
CKI
17
16 15—13
OUT IN
DMA
12
11 10
9
8
SAN
OLEN
AOL
AOC
7
6
ILEN
5
4
AIL
AIC
3
2
1
SLEN BC
0
ASY
Field
ASY
Description
If 0, SY is external. If 1, SY is internal. When generated internally, SY = {ICK, OCK} ÷ 256,
512, or 1024, based on ioc[1] (BC) and ioc[3—2] (SLEN).
BC
If 0, ICK is used to derive the internal load and SY signals. If 1, OCK is used to derive the
internal load and SY signals.
SLEN These bits select the frequency ratio of the on-chip load signal to the on-chip SY signal.
The possible ratios are listed below:
Bit 3
Bit 2 Ratio
0
0
32
0
1
8
1
0
16
1
1
32
AIC If 0, ICK is external. If 1, ICK is generated internally with a frequency of CKI ÷ 8 or
CKI ÷ 24, based on ioc[18] (CKI).
AIL If 0, ILD is external. If 1, ILD is generated internally with a frequency of ICK ÷ 32 or
OCK ÷ 32, based on ioc[1] (BC).
ILEN These bits specify the length of the serial input data.
Bit 7
Bit 6
Input Length
0
0
32 bits (prior to ILD)
0
1
8 bits (after ILD)
1
0
16 bits (after ILD)
1
1
32 bits (after ILD)
AOC If 0, OCK is external. If 1, OCK is internally generated with a frequency of CKI ÷ 8 or
CKI ÷ 24, based on ioc[18] (CKI).
AOL If 0, OLD is external. If 1, OLD is internally generated with a frequency of ICK ÷ 32 or
OCK ÷ 32, based on ioc[1] (BC).
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Register Operation (continued)
Input/Output Control (ioc) Register (continued)
Table 19. Input/Output Control (ioc) Register (continued)
Bit
Field
Bit(s)
11, 10
12
15—13
16
17
18
19
20
20
DSZ
19
18
O24 CKI
17
16 15—13
OUT IN
DMA
12
11 10
9
8
SAN
OLEN
AOL
AOC
7
6
ILEN
5
4
AIL
AIC
3
2
1
SLEN BC
0
ASY
Field
Description
OLEN These bits, in conjunction with ioc[19] (O24), specify the length of the serial output data.
Bit 19 Bit 11 Bit 10 Output Length
0
0
0
32 bits (no OSE is generated)
0
0
1
8 bits
0
1
0
16 bits
0
1
1
32 bits
1
0
0
24 bits
1
0
1
Reserved
1
1
x
Reserved
SAN If 0, clear sanity bit. If 1, set sanity bit.
DMA These bits control serial direct memory accesses (DMA).
Bit 15 Bit 14 Bit 13
0
0
0
No DMA
0
0
1
Input DMA when IBF is high
0
1
0
Output DMA when OBE is high
0
1
1
Input DMA when IBF is high and output DMA when OBE is high
1
0
0
Input and output DMA when IBF and OBE are high
1
0
1
Input and output DMA when IBF is high
1
1
0
Input and output DMA when OBE is high
1
1
1
Input and output DMA when either IBF or OBE is high
IN
If 0, the LSB is received first during serial inputs. If 1, the MSB is received first during serial inputs.
OUT If 0, the LSB is transmitted first during serial outputs. If 1, the MSB is transmitted first during serial outputs (cannot be used with 24-bit output length).
CKI If 0, the internal bit-clock frequency is CKI ÷ 8. If 1, the internal bit-clock frequency is
CKI ÷ 24.
O24 See OLEN, bits 11 and 10, for the use of this bit.
DSZ If 0, the data size of input and output DMA is 32 bits. If 1, the data size of input DMA is
determined by the ILEN field and the data size of output DMA is determined by the OLEN
and O24 fields. (24-bit is performed as 32-bit.)
AT&T Microelectronics
27
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Register Operation (continued)
DAU Control (dauc) Register
Table 20. DAU Control (dauc) Register
Bit
Field
Bit(s)
4—0
4
3
2
1
0
DAUC
Field
Description
DAUC This register controls the type conversions performed on input and output data. The
permissible combinations are shown below:
xx0x0 — µ-law input conversion
xx0x1 — A-law input conversion
x0x0x — µ-law output conversion
x0x1x — A-law output conversion
xx1xx — Linear byte input conversion
x1xxx — Linear byte output conversion
1xxxx — Truncate on float-to-integer conversions
0xxxx — Round on float-to-integer conversions (default)
Choosing the linear byte input and/or output mode will override the corresponding
µ-law/A-law setting.
Note: x = don't care.
28
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Register Operation (continued)
Parallel I/O Register Selection
The parallel I/O interface provides a processor address bus (PAB0—PAB3) to select access to the various PIO
registers. Table 21 shows the register selections possible. Table 22 through Table 25 display the PIO registers.
All PIO registers may be read or written by the external device, except esr, which is read-only, and the pcw,
which is only accessible by the DSP32C. Bit 9 of the parallel I/O control register (pcr[9]) is used to configure an
8-bit or 16-bit parallel interface. pcr[1] provides a DSP32-compatible means of accessing the pir register.
pcr[9] = 1 and pcr[1] = 0 should not be used together.
Table 21. PIO Register Selection
PAB3—
PAB0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DSP32-Compatible Mode
pcr[9] = 0, pcr[1] = 0
par(l) — low byte
par(h) — high byte
pdr(l) — low byte
pdr(h) — high byte
emr(l) — low byte
emr(h) — high byte
esr
pcr(l) — low byte
pir(h) — high byte
pir(h) — high byte
pir(h) — high byte
pir(h) — high byte
pir(h) — high byte
pir(h) — high byte
pir(h) — high byte
pir(h) — high byte
Register Selected
DSP32C 8-Bit Mode
pcr[9] = 0, pcr[1] = 1
par(l) — low byte
par(h) — high byte
pdr(l) — low byte
pdr(h) — high byte
emr(l) — low byte
emr(h) — high byte
esr
pcr(l) — low byte
pir(l) — low byte
pir(h) — high byte
pcr(h) — high byte
pare
pdr2(l) — low byte
pdr2(h) — high byte
Reserved
Reserved
DSP32C 16-Bit Mode
pcr[9] = 1, pcr[1] = 1
par
Reserved
pdr
Reserved
emr
Reserved
esr
pcr
pir
Reserved
Reserved*
pare
pdr2
Reserved
Reserved
Reserved
* pcr(h) accessible for development system use.
AT&T Microelectronics
29
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Register Operation (continued)
Parallel I/O Control Register (pcr)
The PIO control register (pcr) is a 16-bit register used by an external device to control transfer modes with the
DSP32C device.
Table 22. Parallel I/O Control Register (pcr)
Bit
Field
Bit(s)
0
1
2
3
4
5
6
7
8
9
10
11—15
15—11 10
RES
FLG
9
PIO16
8
7
6
DMA32 RES PIFs
5
PDFs
4
AUTO
3
DMA
2
ENI
1
REGMAP
0
RESET
Field
Description
RESET If 0, halt. If 1, run. A zero-to-one transition initiates a reset sequence.
REGMAP Selects between the possible PAB-to-register mappings. (See Table 21.)
ENI
If 0, disables setting (1) and clearing (0) of the PIF pin due to reading or writing of the
pir. If 1, enables setting (1) and clearing (0) of the PIF pin due to reading or writing of
the pir.
DMA
If 0, PIO DMA is disabled. If 1, PIO DMA is enabled.
AUTO
If 0, par is not autoincremented on DMA. If 1, par is autoincremented on DMA.
PDFs
pdr status (read only). Set (1) when pdr is written by the DSP32C or an external device. Cleared (0) when pdr is read by the DSP32C or an external device.
PIFs
pir status (read only). Set (1) when pir is written by the DSP32C or an external device. Cleared (0) when pir is read by the DSP32C or an external device.
RES
Reserved.
DMA32 If 0, DMA transfers are 16 bits (pdr). If 1, DMA transfers are 32 bits (pdr and pdr2).
PIO16
If 0, the PIO interface is 8 bits. If 1, the interface is 16 bits.
FLG
If 0, the PDF and PIF changes on the leading edge of reads. If 1, the PDF and PIF
changes on the trailing edge of reads.
RES
Reserved.
Notes:
A reset sequence clears the contents of the pcr, except pcr[0] which is set. To achieve a setting other than the default, the pcr must be written again after the reset.
When configuring the DSP32C PIO for 16-bit transfers, since reset clears (0) pcr[1], the PIO is initialized in the DSP32-compatible mode.
pcr(h) is not accessible in this mode. To access pcr(h), an external device must first write a logic 1 to pcr[1] (REGMAP). This places the PIO
in the DSP32C 8-bit mode. pcr(h) may now be written (PAB3—PAB0 = 1010) to change the DMA32, PIO16, and FLG bits.
30
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Register Operation (continued)
Error Source Register (esr)
The 8-bit error source register (esr) is a read-only register which is readable only by the external system. The
register, which is cleared after a read operation, stores the error condition status.
Table 23. Error Source Register (esr)
Bit
Field
Bit
0
1
2
3
4
5
Field
RES
NAN
WPIR
RES
OUE
ADER
6
LOS
7
LOSY
7
LOSY
6
LOS
5
ADER
4
OUE
3
RES
2
WPIR
1
NAN
0
RES
Description
Reserved.
If set (1), IEEE-to-DSP32 conversion detected a NaN.
If set (1), the pir was written.
Reserved.
If set (1), DAU overflow or underflow occurred.
Addressing error. If set (1), an attempt was made to access a float variable or an integer
variable with an address that was not a multiple of four or two, respectively.
Loss of sanity. If set (1), sanity bit in the ioc register is set (1), and SY changes state
from high to low.
Loss of sync. If set (1), loss of external synchronization.
AT&T Microelectronics
31
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Register Operation (continued)
Error Mask Register (emr)
The 16-bit error mask register (emr) can be read or written by the external device and is divided into two halves.
Bits 0, 2, and 3 and bits 8, 10, and 11 are reserved. When the emr is read, these bits are all read as logic one.
emr[1] and emr[4—7], when set (1), mask the corresponding error condition in the esr for signaling an external
device. Similarly, emr[9] and emr[12—15], when set (1), mask the corresponding error condition in the esr (i.e.,
bit 9 of the emr corresponds to bit 1 of the esr) for halting the DSP32C. When the DSP32C is reset, all emr bits
are set (1).
Table 24. Error Mask Register (emr)
Bit
15
Field
Bits
0—7
8—15
32
14
13
12 11 10
Halt Mask
9
8
7
6 5 4 3 2 1
PIF Notification Mask
0
Field
Description
PIF
Each bit in the field is set (1) to mask each corresponding esr bit from signaling the
Notification external device (via the PIF pin) when an error source is detected. If a bit in this field
Mask
is cleared (0), the corresponding esr bit is unmasked to allow the external device to be
signaled if the error is detected.
emr
esr
Error Source
0
0
Reserved
1
1
NaN — Not a Number (IEEE-to-DSP32C)
2
2
Reserved
3
3
Reserved
4
4
OUE — DAU Overflow/Underflow Occurred
5
5
ADER — Addressing Error
6
6
LOS — Loss of Sanity
7
7
LOSY — Loss of External Sync
Halt Mask Each bit in the field is set (1) to mask each corresponding esr bit from halting the
DSP32C when an error source is detected. If a bit in this field is cleared (0), the corresponding esr bit is unmasked to allow the DSP32C to be halted if the error was detected.
emr
esr
Error Source
8
0
Reserved
9
1
NaN — Not a Number (IEEE-to-DSP32C)
10
2
Reserved
11
3
Reserved
12
4
OUE — DAU Overflow/Underflow Occurred
13
5
ADER — Addressing Error
14
6
LOS — Loss of Sanity
15
7
LOSY — Loss of External Sync
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Register Operation (continued)
Processor Control Word (pcw) Register
Table 25. Processor Control Word (pcw) Register
Bit
Field
15
14
Bit(s)
0
Field
WB
1
WA
3, 2
MEMB
5, 4
MEMA
6
PIOPL
7
PIOPH
8
MGN
9
PEND
15—10
INTER
13 12
INTER
11
10
9
8
7
PEND MGN PIOPH
6
5 4 3 2
1
PIOPL MEMA MEMB WA
0
WB
Description
If 0, disable wait-state generator for external memory partition B. If 1, enable waitstate generator for external memory partition B.
If 0, disable wait-state generator for external memory partition A. If 1, enable waitstate generator for external memory partition A.
These bits select the number of wait-states that will be generated for the external
memory in partition B.
00 — 1 wait-state*
01 — 2 wait-states
10 — 3 wait-states
11 — 2 or more wait-states (controlled by SRDYN signal)
These bits select the number of wait-states that will be generated for the external
memory in partition A.
00 — 1 wait-state*
01 — 2 wait-states
10 — 3 wait-states
11 — 2 or more wait-states (controlled by SRDYN signal)
If 0, PIOP3—PIOP0 are inputs. If 1, PIOP3—PIOP0 are outputs when
pcr[9](PIO16) = 0.
If 0, PIOP7—PIOP4 are inputs. If 1, PIOP7—PIOP4 are outputs when
pcr[9](PIO16) = 0.
If 0, the MGN pin acts as a memory output enable signal. If 1, the MGN pin is used
by the bus arbitration protocol to indicate that an external memory access is pending.
If pcw[8](MGN) = 0, this bit is not used. If pcw[8] = 1, the logical value of this bit is
ORed with an internal signal that indicates an external access is pending. It is then
inverted to produce the signal at the MGN pin (i.e., if pcw[8](MGN) = 1 and
pcw[9](PEND) = 1, then the pin MGN = 0).
Each bit in this field corresponds to one of the six sources for an interrupt. A value of
1 in a position enables the corresponding interrupt source; a value of 0 disables the
source.
Bit
Interrupt
Source
10
INTREQ2
Interrupt 2 pin
11
OBE
Serial output buffer empty
12
IBF
Serial input buffer full
13
PDE
Parallel data empty (output)
14
PDF
Parallel data full (input)
15
INTREQ1
Interrupt 1 pin
* 1 wait-state = one period of CKI = 12.5 ns at maximum clock frequency.
AT&T Microelectronics
33
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Pin Information
13
12
11
10
9
8
7
ORIENTATION
PIN
6
5
4
3
2
1
N
M
L
K
J
H
G
F
E
D
C
B
A
5-3616(C)
Figure 4. 133-Pin Square CPGA (DSP32C-R3) Diagram (Bottom View)
21
145
2 1 164
144
22
PIN #1
IDENTIFIER
42
124
62
104
63
83
103
5-3617(C)
Figure 5. 164-Pin BQFP Package (DSP32C-F3) Diagram (Top View)
34
AT&T Microelectronics
Data Sheet
June 1995
Pin Information
AT&T DSP32C Digital Signal Processor
with External Memory Interface
(continued)
Pins by Functional Group Order
Table 26. DSP32C Pin Descriptions
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
(BQFP)
108
110
111
112
114
115
118
120
123
122
124
127
128
130
131
132
126
119
116
107
100
106
152
153
154
156
157
158
160
161
162
164
2
5
Pin
(CPGA)
D13
D12
C13
C12
B13
B12
A13
A12
B11
A11
B10
A10
A9
A8
B6
C7
B8
C8
C9
C10
D10
E10
A2
A1
B3
B2
B1
C2
C1
D3
D2
D1
E2
E1
Symbol
Type*
AB00
AB01
AB02
AB03
AB04
AB05
AB06
AB07
AB08
AB09
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
DB00
DB01
DB02
DB03
DB04
DB05
DB06
DB07
DB08
DB09
DB10
DB11
O(3)
I/O(3)
Name/Description
External Memory Address Bus — Bit 0.
External Memory Address Bus — Bit 1.
External Memory Address Bus — Bit 2.
External Memory Address Bus — Bit 3.
External Memory Address Bus — Bit 4.
External Memory Address Bus — Bit 5.
External Memory Address Bus — Bit 6.
External Memory Address Bus — Bit 7.
External Memory Address Bus — Bit 8.
External Memory Address Bus — Bit 9.
External Memory Address Bus — Bit 10.
External Memory Address Bus — Bit 11.
External Memory Address Bus — Bit 12.
External Memory Address Bus — Bit 13.
External Memory Address Bus — Bit 14.
External Memory Address Bus — Bit 15.
External Memory Address Bus — Bit 16.
External Memory Address Bus — Bit 17.
External Memory Address Bus — Bit 18.
External Memory Address Bus — Bit 19.
External Memory Address Bus — Bit 20.
External Memory Address Bus — Bit 21.
External Memory Data Bus — Bit 0.
External Memory Data Bus — Bit 1.
External Memory Data Bus — Bit 2.
External Memory Data Bus — Bit 3.
External Memory Data Bus — Bit 4.
External Memory Data Bus — Bit 5.
External Memory Data Bus — Bit 6.
External Memory Data Bus — Bit 7.
External Memory Data Bus — Bit 8.
External Memory Data Bus — Bit 9.
External Memory Data Bus — Bit 10.
External Memory Data Bus — Bit 11.
* I = input; O = output; (3) = 3-state, P = power.
† PAB3 is labeled PACK in the DSP32.
‡ PIF is labeled PINT in the DSP32.
AT&T Microelectronics
35
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Pin Information
Data Sheet
June 1995
(continued)
Pins by Functional Group Order (continued)
Table 26. DSP32C Pin Descriptions (continued)
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
(BQFP)
3
6
7
9
10
11
13
14
15
27
25
29
31
32
33
37
36
35
39
40
104
Pin
(CPGA)
F3
F2
F1
G2
G1
H3
H2
H1
J2
J1
K3
K2
K1
L2
L1
M3
M2
M1
N2
N1
—
Symbol
Type*
DB12
DB13
DB14
DB15
DB16
DB17
DB18
DB19
DB20
DB21
DB22
DB23
DB24
DB25
DB26
DB27
DB28
DB29
DB30
DB31
EAPN
I/O(3)
101
99
148
E12
E13
E4
MMD0
MMD1
MMD2
I
134
135
138
140
A7
A6
A5
A4
MSN0
MSN1
MSN2
MSN3
O(3)
O(3)
Name/Description
External Memory Data Bus — Bit 12.
External Memory Data Bus — Bit 13.
External Memory Data Bus — Bit 14.
External Memory Data Bus — Bit 15.
External Memory Data Bus — Bit 16.
External Memory Data Bus — Bit 17.
External Memory Data Bus — Bit 18.
External Memory Data Bus — Bit 19.
External Memory Data Bus — Bit 20.
External Memory Data Bus — Bit 21.
External Memory Data Bus — Bit 22.
External Memory Data Bus — Bit 23.
External Memory Data Bus — Bit 24.
External Memory Data Bus — Bit 25.
External Memory Data Bus — Bit 26.
External Memory Data Bus — Bit 27.
External Memory Data Bus — Bit 28.
External Memory Data Bus — Bit 29.
External Memory Data Bus — Bit 30.
External Memory Data Bus — Bit 31.
External Access Pending (Active-Low). Indicates that the
DSP32C has an external access pending but does not have ownership of its bus.
Memory Mode — Bit 0.
Memory Mode — Bit 1.
Memory Mode — Bit 2.
MMD0 and MMD1 select the address location of memory resources
(see Memory Configuration).
Memory Select — Bit 0 (Active-Low).
Memory Select — Bit 1 (Active-Low).
Memory Select — Bit 2 (Active-Low).
Memory Select — Bit 3 (Active-Low).
MSN0—MSN3 (Active-low) select individual bytes 0, 1, 2, or 3 of
memory addressed by the external memory address bus.
* I = input; O = output; (3) = 3-state, P = power.
† PAB3 is labeled PACK in the DSP32.
‡ PIF is labeled PINT in the DSP32.
36
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Pin Information
(continued)
Pins by Functional Group Order (continued)
Table 26. DSP32C Pin Descriptions (continued)
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
(BQFP)
142
Pin
(CPGA)
A3
Symbol
Type*
Name/Description
MGN/
EAPN
O(3)
139
136
B4
C6
MWN
ASN
O(3)
O(3)
143
C5
DSN
O(3)
144
C4
CYCLEIN
O(3)
150
D4
RWN
O(3)
149
F4
SRDYN
I
28
L6
BREQN
I
19
K5
BRACKN
O(3)
24
L5
INTREQ1
I
23
L4
INTREQ2
I
18
K4
IACK1
O(3)
17
J4
IACK2
O(3)
82
80
79
78
76
K13
K12
K11
L13
L12
PDB00
PDB01
PDB02
PDB03
PDB04
I/O(3)
Memory Output Enable/External Access Pending (Active-Low).
When pcw[8] = 0, MGN indicates that memory output should be
placed on the external memory data bus. When pcw[8] = 1, EAPN
indicates that the DSP32C has an external access pending but does
not have ownership of its bus.
Memory Write (Active-Low). Controls data writes to memory.
Address Strobe (Active-Low). Indicates a valid address on the address bus.
Data Strobe (Active-Low). During a read transaction, DSN indicates that data may be placed on the data bus. During a write transaction, DSN indicates that valid data is present on the data bus.
Cycle Initiate (Active-Low). Indicates the beginning of a valid external memory transaction.
Read/Write. If HIGH, memory transaction is a read operation, and, if
LOW, memory transaction is a write operation.
Synchronous Ready (Active-Low). Indicates to the DSP32C that
the memory transaction may be completed.
Bus Request (Active-Low). When asserted, the DSP32C places
data, address, and control signals in the high-impedance state.
Bus Request Acknowledge (Active-Low). Indicates that the
DSP32C has relinquished its address, data, and control lines, and
that the external processor may access the external memory of the
DSP32C.
Interrupt Request 1 (Active-Low). Higher-priority external interrupt.
Maskable in the pcw register.
Interrupt Request 2 (Active-Low). Lower-priority external interrupt.
Maskable in the pcw register.
Interrupt Acknowledge 1. Indicates the servicing of interrupt request 1.
Interrupt Acknowledge 2. Indicates the servicing of interrupt request 2.
Parallel Data Bus — Bit 0.
Parallel Data Bus — Bit 1.
Parallel Data Bus — Bit 2.
Parallel Data Bus — Bit 3.
Parallel Data Bus — Bit 4.
* I = input; O = output; (3) = 3-state, P = power.
† PAB3 is labeled PACK in the DSP32.
‡ PIF is labeled PINT in the DSP32.
AT&T Microelectronics
37
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Pin Information
Data Sheet
June 1995
(continued)
Pins by Functional Group Order (continued)
Table 26. DSP32C Pin Descriptions (continued)
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
(BQFP)
75
74
72
66
Pin
(CPGA)
M13
M12
M11
J10
Symbol
Type*
I/O(3)
J13
PDB05
PDB06
PDB07
PDB08/
PIOP0
PDB09/
PIOP1
PDB10/
PIOP2
PDB11/
PIOP3
PDB12/
PIOP4
PDB13/
PIOP5
PDB14/
PIOP6
PDB15/
PIOP7
PAB0
PAB1
PAB2
PAB3
(PACK)†
PEN
67
K10
68
L10
61
N11
60
M10
59
L9
53
L8
52
L7
89
91
92
84
H13
G12
G13
J12
85
87
H12
PGN
I
88
H11
PWN
I
70
N12
PIF
(PINT)‡
O(3)
71
N13
PDF
O(3)
I/O(3)
Name/Description
Parallel Data Bus — Bit 5.
Parallel Data Bus — Bit 6.
Parallel Data Bus — Bit 7.
Parallel Data Bus — Bit 8/PIO Port — Bit 0.
Parallel Data Bus — Bit 9/PIO Port — Bit 1.
Parallel Data Bus — Bit 10/PIO Port — Bit 2.
Parallel Data Bus — Bit 11/PIO Port — Bit 3.
Parallel Data Bus — Bit 12/PIO Port — Bit 4.
Parallel Data Bus — Bit 13/PIO Port — Bit 5.
Parallel Data Bus — Bit 14/PIO Port — Bit 6.
Parallel Data Bus — Bit 15/PIO Port — Bit 7.
I
I
Processor Address Bus — Bit 0.
Processor Address Bus — Bit 1.
Processor Address Bus — Bit 2.
Processor Address Bus — Bit 3.
PAB0—PAB3 are decoded to select the appropriate PIO register.
Processor Interface Enable (Active-Low). When active, PEN allows a read or a write of the PIO data bus (PDB).
Processor Read Enable (Active-Low). Allows an external microprocessor to read data from the selected PIO register.
Processor Write Enable (Active-Low). When active, enables onchip registers to be written by an external microprocessor.
Parallel Interrupt Full. Interrupt to µP. PIF is set when a nonmasked error occurs, or when the DSP32C or an external microprocessor writes to pir, and pcr[2] is set; PIF is cleared when esr or pir
is read by the µP, or pir is read by the DSP32C.
Parallel Data Full. Set when pdr is written by the DSP32C or an external microprocessor; cleared when pdr is read by the DSP32C or
an external microprocessor.
* I = input; O = output; (3) = 3-state, P = power.
† PAB3 is labeled PACK in the DSP32.
‡ PIF is labeled PINT in the DSP32.
38
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Pin Information
(continued)
Pins by Functional Group Order (continued)
Table 26. DSP32C Pin Descriptions (continued)
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
(BQFP)
57
47
Pin
(CPGA)
N10
N6
Symbol
Type*
Name/Description
DI
IBF
I
O(3)
56
N9
ICK
I/O(3)
55
N8
ILD
I/O(3)
43
M4
DO
O(3)
45
N5
OBE
O(3)
51
M8
OCK
I/O(3)
49
N7
OLD
I/O(3)
44
N4
OSE
O(3)
41
N3
OEN
I
48
M6
SY
I/O(3)
Data Input. Serial input PCM data.
Input Buffer Full. Indicates state of input buffer (ibuf). IBF is
cleared when ibuf is loaded onto the data bus by the DSP32C.
Input Clock. Clock for serial PCM input data. In internal mode,
ICK is an output; in external mode, ICK is an input, depending on
the ioc register.
Input Load. Clock for loading input buffer from serial-to-parallel
converter. In internal mode, ILD is an output; in external mode,
ILD is an input, depending on the ioc register.
Data Output. Serial output PCM data. 3-stated when OEN is
set.
Output Buffer Empty. Indicates the state of serial PCM output
buffer (obuf). OBE is cleared when obuf is written by the
DSP32C.
Output Clock. Clock for serial PCM output data. In internal
mode, OCK is an output; in external mode, OCK is an input, depending on the ioc register.
Output Load. Clock for loading parallel-to-serial converter from
obuf. In internal mode, OLD is an output; in external mode, OLD
is an input, depending on the ioc register.
Output Shift Register Empty. Indicates end of serial output
transmission. OSE is the complement of OLD delayed by the
number of bits in the transmission, as set by the ioc register.
Output Enable (Active-Low). Enables DO for output. When
high, DO is 3-stated.
Synchronization. Internal mode (Output)—DSP32C provides
frame sync. External mode (Input)—frame sync is provided to
the DSP32C. (May also be used as a general-purpose status pin
when configured in external mode.)
* I = input; O = output; (3) = 3-state, P = power.
† PAB3 is labeled PACK in the DSP32.
‡ PIF is labeled PINT in the DSP32.
AT&T Microelectronics
39
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Pin Information
Data Sheet
June 1995
(continued)
Pins by Functional Group Order (continued)
Table 26. DSP32C Pin Descriptions (continued)
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
(BQFP)
96
93
Pin
(CPGA)
D11
F11
Symbol
Type*
Name/Description
CKI
CKO
I
O(3)
95
F12
RESTN
I
97
F13
ZN
I(R)
8, 16, 26,
34, 42, 50,
58, 69, 77,
86, 94,
105, 113,
121, 129,
137, 147,
155, 163
4, 12, 22,
30, 38, 46,
54, 65, 73,
81, 90, 98,
109, 117,
125, 133,
141, 151,
159
B7, E3,
E11, J3,
J11, M7
V DD
P
Clock In. System clock.
Clock Out. Buffered clock at the same frequency as CKI.
Synchronizes external devices to the DSP32C.
Reset (Active-Low). Controls the DSP32C run/halt state. A low
level causes entry into the halt state. The low-to-high transition
causes the reset sequence. Reset sequence stores pc in r14;
clears pc, ioc, esr; and sets emr to mask all errors. The pcr
register bits, except pcr[0], are cleared; pcr[0] is set. CAU and
DAU condition flags and the dauc register are not affected by reset. The pcw register is set to generate two or more wait-states
(depending on SRDYN signal) for external memory.
3-State (Active-Low). When active, all DSP32C output pins are
3-stated. When not connected, ZN is inactive. Used for poweron reset.
+5 V.
B5, B9,
C3, C11,
D5, D9,
G3, G11,
K9, L3,
L11, M5,
M9
V SS
P
Ground.
* I = input; O = output; (3) = 3-state, P = power.
† PAB3 is labeled PACK in the DSP32.
‡ PIF is labeled PINT in the DSP32.
40
AT&T Microelectronics
Data Sheet
June 1995
Pin Information
AT&T DSP32C Digital Signal Processor
with External Memory Interface
(continued)
Pins by Numerical Order
Table 27. DSP32C Pin Descriptions—CPGA Package
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
C1
C2
C3
C4
C5
C6
Symbol
DB01
DB00
MGN/
EAPN
MSN3
MSN2
MSN1
MSN0
AB13
AB12
AB11
AB09
AB07
AB06
DB04
DB03
DB02
MWN
V SS
AB14
V DD
AB16
V SS
AB10
AB08
AB05
AB04
DB06
DB05
V SS
CYCLEIN
DSN
ASN
Type*
I/O(3)
I/O(3)
O(3)
Name
External Memory Data Bus — Bit 1.
External Memory Data Bus — Bit 0.
Memory Output Enable/External Access Pending.
O(3)
O(3)
O(3)
O(3)
O(3)
O(3)
O(3)
O(3)
O(3)
O(3)
I/O(3)
I/O(3)
I/O(3)
O(3)
P
O(3)
P
O(3)
P
O(3)
O(3)
O(3)
O(3)
I/O(3)
I/O(3)
P
O(3)
O(3)
O(3)
Memory Select — Bit 3.
Memory Select — Bit 2.
Memory Select — Bit 1.
Memory Select — Bit 0.
External Memory Address Bus — Bit 13.
External Memory Address Bus — Bit 12.
External Memory Address Bus — Bit 11.
External Memory Address Bus — Bit 9.
External Memory Address Bus — Bit 7.
External Memory Address Bus — Bit 6.
External Memory Data Bus — Bit 4.
External Memory Data Bus — Bit 3.
External Memory Data Bus — Bit 2.
Memory Write.
Ground.
External Memory Address Bus — Bit 14.
+5 V.
External Memory Address Bus — Bit 16.
Ground.
External Memory Address Bus — Bit 10.
External Memory Address Bus — Bit 8.
External Memory Address Bus — Bit 5.
External Memory Address Bus — Bit 4.
External Memory Data Bus — Bit 6.
External Memory Data Bus — Bit 5.
Ground.
Cycle Initiate.
Data Strobe.
Address Strobe.
* I = input; O = output; P = power; (3) = 3-state; (R) = on-chip pull-up.
† PAB3 is labeled PACK in the DSP32.
‡ PIF is labeled PINT in the DSP32.
AT&T Microelectronics
41
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Pin Information
Data Sheet
June 1995
(continued)
Pins by Numerical Order (continued)
Table 27. DSP32C Pin Descriptions—CPGA Package (continued)
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
C7
C8
C9
C10
C11
C12
C13
D1
D2
D3
D4
D5
D9
D10
D11
D12
D13
E1
E2
E3
E4
E10
E11
E12
E13
F1
F2
F3
F4
F11
F12
F13
G1
G2
Symbol
AB15
AB17
AB18
AB19
V SS
AB03
AB02
DB09
DB08
DB07
RWN
V SS
V SS
AB20
CKI
AB01
AB00
DB11
DB10
V DD
MMD2
AB21
V DD
MMD0
MMD1
DB14
DB13
DB12
SRDYN
CKO
RESTN
ZN
DB16
DB15
Type*
O(3)
O(3)
O(3)
O(3)
P
O(3)
O(3)
I/O(3)
I/O(3)
I/O(3)
O(3)
P
P
O(3)
I
O(3)
O(3)
I/O(3)
I/O(3)
P
I
O(3)
P
I
I
I/O(3)
I/O(3)
I/O(3)
I
O(3)
I
I(R)
I/O(3)
I/O(3)
Name
External Memory Address Bus — Bit 15.
External Memory Address Bus — Bit 17.
External Memory Address Bus — Bit 18.
External Memory Address Bus — Bit 19.
Ground.
External Memory Address Bus — Bit 3.
External Memory Address Bus — Bit 2.
External Memory Data Bus — Bit 9.
External Memory Data Bus — Bit 8.
External Memory Data Bus — Bit 7.
Read/Write.
Ground.
Ground.
External Memory Address Bus — Bit 20.
Clock In.
External Memory Address Bus — Bit 1.
External Memory Address Bus — Bit 0.
External Memory Data Bus — Bit 11.
External Memory Data Bus — Bit 10.
+5 V.
Memory Mode — Bit 2.
External Memory Address Bus — Bit 21.
+5 V.
Memory Mode — Bit 0.
Memory Mode — Bit 1.
External Memory Data Bus — Bit 14.
External Memory Data Bus — Bit 13.
External Memory Data Bus — Bit 12.
Synchronous Ready.
Clock Out.
Reset.
3-state.
External Memory Data Bus — Bit 16.
External Memory Data Bus — Bit 15.
* I = input; O = output; P = power; (3) = 3-state; (R) = on-chip pull-up.
† PAB3 is labeled PACK in the DSP32.
‡ PIF is labeled PINT in the DSP32.
42
AT&T Microelectronics
Data Sheet
June 1995
Pin Information
AT&T DSP32C Digital Signal Processor
with External Memory Interface
(continued)
Pins by Numerical Order (continued)
Table 27. DSP32C Pin Descriptions—CPGA Package (continued)
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
G3
G11
G12
G13
H1
H2
H3
H11
H12
H13
J1
J2
J3
J4
J10
J11
J12
J13
K1
K2
K3
K4
K5
K9
K10
K11
K12
K13
L1
L2
L3
L4
Symbol
V SS
V SS
PAB1
PAB2
DB19
DB18
DB17
PWN
PGN
PAB0
DB21
DB20
V DD
IACK2
PDB08/
PIOP0
V DD
PAB3
(PACK)†
PEN
DB24
DB23
DB22
IACK1
BRACKN
V SS
PDB09/
PIOP1
PDB02
PDB01
PDB00
DB26
DB25
V SS
INTREQ2
Type*
P
P
I
I
I/O(3)
I/O(3)
I/O(3)
I
I
I
I/O(3)
I/O(3)
P
O(3)
I/O(3)
P
I
Name
Ground.
Ground.
Processor Address Bus — Bit 1.
Processor Address Bus — Bit 2.
External Memory Data Bus — Bit 19.
External Memory Data Bus — Bit 18.
External Memory Data Bus — Bit 17.
Processor Write Enable.
Processor Read Enable.
Processor Address Bus — Bit 0.
External Memory Data Bus — Bit 21.
External Memory Data Bus — Bit 20.
+5 V.
Interrupt Acknowledge 2.
Parallel Data Bus — Bit 8/PIO Port — Bit 0.
+5 V.
Processor Address Bus — Bit 3.
I
I/O(3)
I/O(3)
I/O(3)
O(3)
O(3)
P
I/O(3)
Processor Interface Enable.
External Memory Data Bus — Bit 24.
External Memory Data Bus — Bit 23.
External Memory Data Bus — Bit 22.
Interrupt Acknowledge 1.
Bus Request Acknowledge.
Ground.
Parallel Data Bus — Bit 9/PIO Port — Bit 1.
I/O(3)
I/O(3)
I/O(3)
I/O(3)
I/O(3)
P
I
Parallel Data Bus — Bit 2.
Parallel Data Bus — Bit 1.
Parallel Data Bus — Bit 0.
External Memory Data Bus — Bit 26.
External Memory Data Bus — Bit 25.
Ground.
Interrupt Request 2.
* I = input; O = output; P = power; (3) = 3-state; (R) = on-chip pull-up.
† PAB3 is labeled PACK in the DSP32.
‡ PIF is labeled PINT in the DSP32.
AT&T Microelectronics
43
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Pin Information
Data Sheet
June 1995
(continued)
Pins by Numerical Order (continued)
Table 27. DSP32C Pin Descriptions—CPGA Package (continued)
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
L5
L6
L7
L8
L9
L10
L11
L12
L13
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
N1
N2
N3
N4
N5
N6
N7
N8
Symbol
INTREQ1
BREQN
PDB15/
PIOP7
PDB14/
PIOP6
PDB13/
PIOP5
PDB10/
PIOP2
V SS
PDB04
PDB03
DB29
DB28
DB27
DO
V SS
SY
V DD
OCK
V SS
PDB12/
PIOP4
PDB07
PDB06
PDB05
DB31
DB30
OEN
OSE
OBE
IBF
OLD
ILD
Type*
I
I
I/O(3)
Name
Interrupt Request 1.
Bus Request.
Parallel Data Bus — Bit 15/PIO Port — Bit 7.
I/O(3)
Parallel Data Bus — Bit 14/PIO Port — Bit 6.
I/O(3)
Parallel Data Bus — Bit 13/PIO Port — Bit 5.
I/O(3)
Parallel Data Bus — Bit 10/PIO Port — Bit 2.
P
I/O(3)
I/O(3)
I/O(3)
I/O(3)
I/O(3)
O(3)
P
I/O(3)
P
I/O(3)
P
I/O(3)
Ground.
Parallel Data Bus — Bit 4.
Parallel Data Bus — Bit 3.
External Memory Data Bus — Bit 29.
External Memory Data Bus — Bit 28.
External Memory Data Bus — Bit 27.
Data Output.
Ground.
Synchronization.
+5 V.
Output Clock.
Ground.
Parallel Data Bus — Bit 12/PIO Port — Bit 4.
I/O(3)
I/O(3)
I/O(3)
I/O(3)
I/O(3)
I
O(3)
O(3)
O(3)
I/O(3)
I/O(3)
Parallel Data Bus — Bit 7.
Parallel Data Bus — Bit 6.
Parallel Data Bus — Bit 5.
External Memory Data Bus — Bit 31.
External Memory Data Bus — Bit 30.
Output Enable.
Output Shift Register Empty.
Output Buffer Empty.
Input Buffer Full.
Output Load.
Input Load.
* I = input; O = output; P = power; (3) = 3-state; (R) = on-chip pull-up.
† PAB3 is labeled PACK in the DSP32.
‡ PIF is labeled PINT in the DSP32.
44
AT&T Microelectronics
Data Sheet
June 1995
Pin Information
AT&T DSP32C Digital Signal Processor
with External Memory Interface
(continued)
Pins by Numerical Order (continued)
Table 27. DSP32C Pin Descriptions—CPGA Package (continued)
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
N9
N10
N11
N12
N13
Symbol
ICK
DI
PDB11/
PIOP3
PIF
(PINT)‡
PDF
Type*
I/O(3)
I
I/O(3)
Name
Input Clock.
Data Input.
Parallel Data Bus — Bit 11/PIO Port — Bit 3.
O(3)
Parallel Input Full.
O(3)
Parallel Data Full.
* I = input; O = output; P = power; (3) = 3-state; (R) = on-chip pull-up.
† PAB3 is labeled PACK in the DSP32.
‡ PIF is labeled PINT in the DSP32.
Table 28. DSP32C Pin Descriptions—BQFP Package
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Symbol
—
DB10
DB12
V SS
DB11
DB13
DB14
V DD
DB15
DB16
DB17
V SS
DB18
DB19
DB20
V DD
IACK2
IACK1
BRACKN
—
—
Type*
NC
I/O(3)
I/O(3)
P
I/O(3)
I/O(3)
I/O(3)
P
I/O(3)
I/O(3)
I/O(3)
P
I/O(3)
I/O(3)
I/O(3)
P
O(3)
O(3)
O(3)
NC
NC
Name
—
External Memory Data Bus — Bit 10.
External Memory Data Bus — Bit 12.
Ground.
External Memory Data Bus — Bit 11.
External Memory Data Bus — Bit 13.
External Memory Data Bus — Bit 14.
+5 V.
External Memory Data Bus — Bit 15.
External Memory Data Bus — Bit 16.
External Memory Data Bus — Bit 17.
Ground.
External Memory Data Bus — Bit 18.
External Memory Data Bus — Bit 19.
External Memory Data Bus — Bit 20.
+5 V.
Interrupt Acknowledge 2.
Interrupt Acknowledge 1.
Bus Request Acknowledge.
—
—
* I = input; O = output; P = power; NC = no connection; (3) = 3-state; (R) = on-chip pull-up.
† PIF is labeled PINT in the DSP32.
‡ PAB3 is labeled PACK in the DSP32.
AT&T Microelectronics
45
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Pin Information
Data Sheet
June 1995
(continued)
Pins by Numerical Order (continued)
Table 28. DSP32C Pin Descriptions—BQFP Package (continued)
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Symbol
V SS
INTREQ2
INTREQ1
DB22
V DD
DB21
BREQN
DB23
V SS
DB24
DB25
DB26
V DD
DB29
DB28
DB27
V SS
DB30
DB31
OEN
V DD
DO
OSE
OBE
V SS
IBF
SY
OLD
V DD
OCK
PDB15/
PIOP7
PDB14/
PIOP6
Type*
P
I
I
I/O(3)
P
I/O(3)
I
I/O(3)
P
I/O(3)
I/O(3)
I/O(3)
P
I/O(3)
I/O(3)
I/O(3)
P
I/O(3)
I/O(3)
I
P
O(3)
O(3)
O(3)
P
O(3)
I/O(3)
I/O(3)
P
I/O(3)
I/O(3)
Name
Ground.
Interrupt Request 2.
Interrupt Request 1.
External Memory Data Bus — Bit 22.
+5 V.
External Memory Data Bus — Bit 21.
Bus Request.
External Memory Data Bus — Bit 23.
Ground.
External Memory Data Bus — Bit 24.
External Memory Data Bus — Bit 25.
External Memory Data Bus — Bit 26.
+5 V.
External Memory Data Bus — Bit 29.
External Memory Data Bus — Bit 28.
External Memory Data Bus — Bit 27.
Ground.
External Memory Data Bus — Bit 30.
External Memory Data Bus — Bit 31.
Output Enable.
+5 V.
Data Output.
Output Shift Register Empty.
Output Buffer Empty.
Ground.
Input Buffer Full.
Synchronization.
Output Load.
+5 V.
Output Clock.
Parallel Data Bus — Bit 15/PIO Port — Bit 7.
I/O(3)
Parallel Data Bus — Bit 14/PIO Port — Bit 6.
* I = input; O = output; P = power; NC = no connection; (3) = 3-state; (R) = on-chip pull-up.
† PIF is labeled PINT in the DSP32.
‡ PAB3 is labeled PACK in the DSP32.
46
AT&T Microelectronics
Data Sheet
June 1995
Pin Information
AT&T DSP32C Digital Signal Processor
with External Memory Interface
(continued)
Pins by Numerical Order (continued)
Table 28. DSP32C Pin Descriptions—BQFP Package (continued)
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Symbol
V SS
ILD
ICK
DI
V DD
PDB13/
PIOP5
PDB12/
PIOP4
PDB11/
PIOP3
—
—
—
V SS
PDB08/
PIOP0
PDB09/
PIOP1
PDB10/
PIOP2
V DD
PIF
(PINT)†
PDF
PDB07
V SS
PDB06
PDB05
PDB04
V DD
PDB03
PDB02
PDB01
V SS
Type*
P
I/O(3)
I/O(3)
I
P
I/O(3)
Name
Ground.
Input Load.
Input Clock.
Data Input.
+5 V.
Parallel Data Bus — Bit 13/PIO Port — Bit 5.
I/O(3)
Parallel Data Bus — Bit 12/PIO Port — Bit 4.
I/O(3)
Parallel Data Bus — Bit 11/PIO Port — Bit 3.
NC
NC
NC
P
I/O(3)
—
—
—
Ground.
Parallel Data Bus — Bit 8/PIO Port — Bit 0.
I/O(3)
Parallel Data Bus — Bit 9/PIO Port — Bit 1.
I/O(3)
Parallel Data Bus — Bit 10/PIO Port — Bit 2.
P
O(3)
+5 V.
Parallel Interrupt Full.
O(3)
I/O(3)
P
I/O(3)
I/O(3)
I/O(3)
P
I/O(3)
I/O(3)
I/O(3)
P
Parallel Data Full.
Parallel Data Bus — Bit 7.
Ground.
Parallel Data Bus — Bit 6.
Parallel Data Bus — Bit 5.
Parallel Data Bus — Bit 4.
+5 V.
Parallel Data Bus — Bit 3.
Parallel Data Bus — Bit 2.
Parallel Data Bus — Bit 1.
Ground.
* I = input; O = output; P = power; NC = no connection; (3) = 3-state; (R) = on-chip pull-up.
† PIF is labeled PINT in the DSP32.
‡ PAB3 is labeled PACK in the DSP32.
AT&T Microelectronics
47
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Pin Information
Data Sheet
June 1995
(continued)
Pins by Numerical Order (continued)
Table 28. DSP32C Pin Descriptions—BQFP Package (continued)
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
Symbol
PDB00
—
PAB3
(PACK)‡
PEN
V DD
PGN
PWN
PAB0
V SS
PAB1
PAB2
CKO
V DD
RESTN
CKI
ZN
V SS
MMD1
AB20
MMD0
—
—
EAPN
V DD
AB21
AB19
AB00
V SS
AB01
AB02
AB03
V DD
AB04
Type*
I/O(3)
NC
I
I
P
I
I
I
P
I
I
O(3)
P
I
I
I(R)
P
I
O(3)
I
NC
NC
O(3)
P
O(3)
O(3)
O(3)
P
O(3)
O(3)
O(3)
P
O(3)
Name
Parallel Data Bus — Bit 0.
—
Processor Address Bus — Bit 3.
Processor Interface Enable.
+5 V.
Processor Read Enable.
Processor Write Enable.
Processor Address Bus — Bit 0.
Ground.
Processor Address Bus — Bit 1.
Processor Address Bus — Bit 2.
Clock Out.
+5 V.
Reset.
Clock In.
3-State.
Ground.
Memory Mode — Bit 1.
External Memory Address Bus — Bit 20.
Memory Mode — Bit 0.
—
—
External Access Pending.
+5 V.
External Memory Address Bus — Bit 21.
External Memory Address Bus — Bit 19.
External Memory Address Bus — Bit 0.
Ground.
External Memory Address Bus — Bit 1.
External Memory Address Bus — Bit 2.
External Memory Address Bus — Bit 3.
+5 V.
External Memory Address Bus — Bit 4.
* I = input; O = output; P = power; NC = no connection; (3) = 3-state; (R) = on-chip pull-up.
† PIF is labeled PINT in the DSP32.
‡ PAB3 is labeled PACK in the DSP32.
48
AT&T Microelectronics
Data Sheet
June 1995
Pin Information
AT&T DSP32C Digital Signal Processor
with External Memory Interface
(continued)
Pins by Numerical Order (continued)
Table 28. DSP32C Pin Descriptions—BQFP Package (continued)
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
Symbol
AB05
AB18
V SS
AB06
AB17
AB07
V DD
AB09
AB08
AB10
V SS
AB16
AB11
AB12
V DD
AB13
AB14
AB15
V SS
MSN0
MSN1
ASN
V DD
MSN2
MWN
MSN3
V SS
MGN
DSN
CYCLEIN
—
—
V DD
MMD2
Type*
O(3)
O(3)
P
O(3)
O(3)
O(3)
P
O(3)
O(3)
O(3)
P
O(3)
O(3)
O(3)
P
O(3)
O(3)
O(3)
P
O(3)
O(3)
O(3)
P
O(3)
O(3)
O(3)
P
O(3)
O(3)
O(3)
NC
NC
P
I
Name
External Memory Address Bus — Bit 5.
External Memory Address Bus — Bit 18.
Ground.
External Memory Address Bus — Bit 6.
External Memory Address Bus — Bit 17.
External Memory Address Bus — Bit 7.
+5 V.
External Memory Address Bus — Bit 9.
External Memory Address Bus — Bit 8.
External Memory Address Bus — Bit 10.
Ground.
External Memory Address Bus — Bit 16.
External Memory Address Bus — Bit 11.
External Memory Address Bus — Bit 12.
+5 V.
External Memory Address Bus — Bit 13.
External Memory Address Bus — Bit 14.
External Memory Address Bus — Bit 15.
Ground.
Memory Select — Bit 0.
Memory Select — Bit 1.
Address Strobe.
+5 V.
Memory Select — Bit 2.
Memory Write.
Memory Select — Bit 3.
Ground.
Memory Output Enable/External Access Pending.
Data Strobe.
Cycle Initiate.
—
—
+5 V.
Memory Mode — Bit 2.
* I = input; O = output; P = power; NC = no connection; (3) = 3-state; (R) = on-chip pull-up.
† PIF is labeled PINT in the DSP32.
‡ PAB3 is labeled PACK in the DSP32.
AT&T Microelectronics
49
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Pin Information
Data Sheet
June 1995
(continued)
Pins by Numerical Order (continued)
Table 28. DSP32C Pin Descriptions—BQFP Package (continued)
Please refer to the AT&T DSP32C Information Manual for a complete description of each pin.
Pin
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
Symbol
SRDYN
RWN
V SS
DB00
DB01
DB02
V DD
DB03
DB04
DB05
V SS
DB06
DB07
DB08
V DD
DB09
Type*
I
O(3)
P
I/O(3)
I/O(3)
I/O(3)
P
I/O(3)
I/O(3)
I/O(3)
P
I/O(3)
I/O(3)
I/O(3)
P
I/O(3)
Name
Synchronous Ready.
Read/Write.
Ground.
External Memory Data Bus — Bit 0.
External Memory Data Bus — Bit 1.
External Memory Data Bus — Bit 2.
+5 V.
External Memory Data Bus — Bit 3.
External Memory Data Bus — Bit 4.
External Memory Data Bus — Bit 5.
Ground.
External Memory Data Bus — Bit 6.
External Memory Data Bus — Bit 7.
External Memory Data Bus — Bit 8.
+5 V.
External Memory Data Bus — Bit 9.
* I = input; O = output; P = power; NC = no connection; (3) = 3-state; (R) = on-chip pull-up.
† PIF is labeled PINT in the DSP32.
‡ PAB3 is labeled PACK in the DSP32.
50
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Device Requirements and Characteristics
Absolute Maximum Ratings
Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to Absolute Maximum Ratings for
extended periods can adversely affect device reliability.
Table 29. Absolute Maximum Ratings
Parameter
Voltage Range on Any Pin with Respect to Ground
Power Dissipation
Storage Temperature
External Lead Bonding and Soldering Temperature
Min
–0.5
—
–65
—
Max
6.0
1.7
150
300
Unit
V
W
°C
°C
Warning: All CMOS devices are prone to latch-up if excessive current is injected to/from the substrate.
To prevent latch-up at powerup, no input pin should be subjected to input voltages greater than
V IL, or less than VSS – 0.5 V before VDD is applied. After powerup, input should not be greater
than V DD + 0.5 V or less than VSS – 0.5 V.
Handling Precautions
All MOS devices must be handled with certain precautions to avoid damage due to the accumulation of static
charge. Although input protection circuitry has been incorporated into the devices to minimize the effect
of this static buildup, proper precautions should be taken to avoid exposure to electrostatic discharge
during handling and mounting. AT&T employs a human-body model for ESD susceptibility testing. Since the
failure voltage of electronic devices is dependent on the current and voltage and, hence, the resistance and capacitance, it is important that standard values be employed to establish a reference by which to compare test
data. Values of 100 pF and 1500 Ω are the most common and are the values used in the AT&T human-body
model test circuit. The breakdown voltage for the DSP32C is greater than 2000 V*, according to the human-body
model. ESD data for the charged-device model is available on request.
* The value of 2000 V for the breakdown voltage is subject to change.
AT&T Microelectronics
51
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Device Requirements and Characteristics (continued)
Temperature Class Definitions
Table 30. Temperature Class Definitions
Temperature
Class
Commercial
Industrial
Ambient Temperature TA (°C)
Min
0
–40
Max
70
85
Recommended Operating Conditions
Table 31. Recommended Operating Conditions
Device
Speed
Package
Temperature
Class
50 ns
133-Pin CPGA
164-Pin BQFP
133-Pin CPGA
133-Pin CPGA
164-Pin BQFP
133-Pin CPGA
133-Pin CPGA
164-Pin BQFP
133-Pin CPGA
164-Pin BQFP
Commercial
Commercial
Industrial
Commercial
Commercial
Industrial
Commercial
Commercial
Industrial
Industrial
60 ns
80 ns
Device Code
DSP32C-R35---050
DSP32C-F35---050
DSP32C-R35---050-I
DSP32C-R35---060
DSP32C-F35---060
DSP32C-R35---060-I
DSP32C-R35---080
DSP32C-F35---080
DSP32C-R35---080-I
DSP32C-F35---080-I
Supply Voltage V DD (V)
Min
4.75
4.75
4.75
4.75
4.75
4.75
4.5
4.5
4.75
4.75
Max
5.25
5.25
5.25
5.25
5.25
5.25
5.5
5.5
5.25
5.25
Package Thermal Considerations
The recommended operating temperature specified above is based on the maximum power, package type, and
maximum junction temperature. The following equation describes the relationship between these parameters.
For certain applications, the maximum power may be less than the worst-case value and the following relationship
can be used to determine the maximum ambient temperature allowed.
TA = TJ − P × ΘJA
Maximum Junction Temperature (T J) in 133-Pin CPGA................................................................................ +125 °C
133-Pin CPGA Maximum Thermal Resistance in Still-Air-Ambient ( ΘJA )..................................................... 25 °C/W
Maximum Junction Temperature (T J) in 164-Pin BQFP ................................................................................ +125 °C
164-Pin BQFP Maximum Thermal Resistance in Still-Air-Ambient ( ΘJA ) ..................................................... 37 °C/W
52
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Electrical Characteristics
The parameters below are valid for the following conditions:
Commercial temperature class device:
TA = 0 °C to 70 °C; VSS = 0 V; CLOAD = 50 pF.
Industrial temperature class device:
TA = –40 °C to +85 °C; VSS = 0 V; CLOAD = 50 pF.
Parameter
Input Voltage: All Pins Except PAB3—PAB0, PEN, PGN, PWN, OCK,
ICK, SY*
Low
High (commercial temperature class device)
High (industrial temperature class device)
Input Voltage: Pins PAB3—PAB0, PEN, PGN, PWN, OCK, ICK, SY*
Low
High (commercial temperature class device)
High (industrial temperature class device)
Output Low Voltage
Low (IOL = 2 mA)
Low (IOL = 5 µA)
Output High Voltage
High (IOH = –2 mA)
High (IOH = –5 µA)
Input Leakage: All Inputs Except ZN
Low (VIL = 0 V) Low
High (VIH = 5.5 V) High
Input Leakage: ZN† Pin
Low (VIL = 0 V) Low
High (VIH = 5.5 V) High
Output Offset Current
Low (VOL = 0 V)
High (VOH = 5.5 V)
Input, Output, I/O Capacitance
Power Supply Current‡
Instruction Cycle Time = 50 ns; tCKILCKIL = 12.5 ns
Instruction Cycle Time = 60 ns; tCKILCKIL = 15 ns
Instruction Cycle Time = 80 ns; tCKILCKIL = 20 ns
Power Dissipation§
Instruction Cycle Time = 50 ns; tCKILCKIL = 12.5 ns
Instruction Cycle Time = 60 ns; tCKILCKIL = 15 ns
Instruction Cycle Time = 80 ns; tCKILCKIL = 20 ns
Sym
Min
Max
Unit
V IL
—
0.8
V
V IH
V IH
2.0
2.2
—
—
V
V
V IL
V IH
V IH
—
2.4
2.7
0.8
—
—
V
V
V
V OL
V OL
—
—
0.4
0.2
V
V
V OH
V OH
V DD – 0.7
V DD – 0.2
—
—
V
V
IIL
IIH
–5
—
—
5
µA
µA
IIL
IIH
–500
—
—
5
µA
µA
IOZL
IOZH
CI
–10
—
—
—
10
10
µA
µA
pF
IDD
IDD
IDD
—
—
—
306
255
225
mA
mA
mA
PD
PD
PD
—
—
—
1.7
1.4
1.25
W
W
W
* The ICK, OCK, and SY pins have Schmitt triggers with hysteresis in the range of 0.5 V to 0.8 V.
† This pin has a pull-up device.
‡ Current in the input buffers is highly dependent on the input voltage level. At full CMOS levels, essentially no dc current is drawn, but for
levels near the threshold of 1.4 V, high and unstable levels of current may flow. There are 72 inputs to the chip (19 input-only and 53 input/
output pins). If all inputs are connected to a dc voltage around 1.4 V, an additional current in the range of 150 mA can be drawn. This current can be almost totally eliminated by setting the input pins to CMOS voltage levels (VDD or VSS ). Therefore, all unused inputs should be
tied inactive to V DD or VSS and all unused I/O pins should be tied inactive through a 10 kΩ resistor to VDD or VSS.
§ The power dissipation listed is for output loads = 70 pF. Total power dissipation can be calculated on the basis of the application by adding
C × VDD 2 × f for each output, where C is the load capacitance and f is the output frequency.
AT&T Microelectronics
53
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Timing Requirements and Characteristics
The characteristics listed are valid under the following conditions:
Commercial temperature class device:
TA = 0 °C to 70 °C; VSS = 0 V; CLOAD = 50 pF.
Industrial temperature class device:
TA = –40 °C to +85 °C; VSS = 0 V; CLOAD = 50 pF.
Output characteristics can be derated as a function of load capacitance (CL).
All outputs except PDBs:
PDB outputs:
dT/dCL ≤ 0.04 ns/pF for 0 ≤ CL ≤ 100 pF
dT/dCL ≤ 0.11 ns/pF for 0 ≤ C L ≤ 200 pF
Test conditions for inputs:
Test conditions for outputs:
Rise and fall times of 4 ns or less
CLOAD = 50 pF
Timing reference level for setup times is
V IM = 1.5 V
Timing reference level for delay times is
V OM = 1.5 V
Timing reference levels for hold times:
V IH = 2.0 V, VIL = 0.8 V
Timing reference levels for hold times:
V OH = 2.4 V, VOL = 0.4 V
CKI and CKO Timing
Table 32. CKI and CKO Timing (See Figure 6.)
Abbreviated
Reference
t1
t2
t3
t4
t5
t6
t6a
t6b
t7
IEEE
Symbol
tCKILCKIL
tCKILCKIH
tCKIHCKIL
tCKIRISE
tCKIFALL
tCKILCKOL
tCKOFALL
tCKORISE
tCKIHCKOH
Parameter
Clock In Period
Clock In Low
Clock In High
Clock In Rise Time
Clock In Fall Time
CKI Low to CKO Low
Clock Out Fall Time
Clock Out Rise Time
CKI High to CKO High
50 ns
Min
Max
12.5
500*
5.7
—
5.7
—
—
3
—
3
—
5
—
3
—
3
—
5
60 ns
Min
Max
15
500*
6.8
—
6.8
—
—
3.5
—
3.5
—
6
—
3.5
—
3.5
—
6
80 ns
Min
Max
20
500*
9
—
9
—
—
4
—
4
—
8
—
4
—
4
—
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The internal RAM contents are retained if CKI drops to DC, but the device is not guaranteed to function properly with CKI below 500 ns.
54
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Timing Requirements and Characteristics (continued)
External Memory Interface (EMI) Timing
Table 33. Definition of Timing Characteristics for External Memory Interface (See Figures 7 and 8.)
Abbreviated
Reference
t8
t8a
t10
t10a
t11
t12
t13
t13a
t14
t14a
t14b
t15
t15a
t15b
t16
t17
t17b
t17c
t17d
t18
t20
t20a
t20b
t20c
t21
t21a
t21c
t21e
t21f
t22
t22a
t22b
t22c
t22d
t23
t23a
IEEE
Symbol
tCKOLABV
tCKOLABX
tCKOLRWNV
tCKOLRWNX
tCKOLCYCNL
tCKOLCYCNH
tABVASNL
tCKOHASNL
tASNLASNH
tCKOLASNH
tASNHABX
tABVDSNH
tCKOLDSNL
tCKOLDSNH
tDSNLDSNH
tMGNLMGNH
tMGNHMGNL
tCKOHMGNL
tCKOLMGNH
tDSNHABX
tDSNHRWNX
tDSNHDBE
tMGNHDBE
tRWNLDBE
tDBVDSNH
tDSNHDBZ
tCKOLDBZ
tCKOLDBV
tCKOLDBE
tDBVMWNH
tMWNLMWNH
tCKOHMWNL
tMWNHABX
tCKOHMWNH
tABVMGNL
tABVMWNL
Parameter
CKO Low to Address Valid*
Address Hold After CKO Low*
CKO Low to Read-Write Valid
Read-Write Hold After CKO Low
CKO Low to Cycle Initiate Low
CKO Low to Cycle Initiate High
Address Valid to Address Strobe Low*
CKO High to Address Strobe Low
Address Strobe Width
CKO Low to Address Strobe High
Address Hold After Address Strobe High*
Data Strobe High After Address Valid*
CKO Low to Data Strobe Low
CKO Low to Data Strobe High
Data Strobe Width
Read Data Strobe Width
Read Strobe High to Read Strobe Low
CKO High to Read Strobe Low
CKO Low to Read Strobe High
Address Hold After Data Strobe High*
Read-Write Hold After Data Strobe High
Data Strobe High to Data Bus Low-Z
Read Strobe High to Data Bus Low-Z
Read-Write Low to Data Bus Low-Z
Data Bus Valid to Data Strobe High
Data Strobe High to Data Bus Hi-Z
Data Bus Hi-Z After CKO Low
CKO Low to Data Bus Valid
Data Bus Low-Z After CKO Low
Data Bus Valid to Write Strobe High
Write Strobe Width
CKO High to Write Strobe Low
Address Hold After Write Strobe High*
CKO High to Write Strobe High
Read Strobe Low After Address Valid*
Write Strobe Low After Address Valid*
* Timing of MSN0—MSN3 is the same as the address bus.
AT&T Microelectronics
55
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Timing Requirements and Characteristics (continued)
External Memory Interface (EMI) Timing (continued)
Table 33. Definition of Timing Characteristics for External Memory Interface (continued)
(see Figures 7 and 8.)
Abbreviated
Reference
t24
t24a
t24b
IEEE
Symbol
tABVDSNL
tMWNHDBZ
tASNHDBZ
Parameter
Data Strobe Low After Address Valid*
Data Bus Hi-Z After Write Strobe High
Data Bus Hi-Z After Address Strobe High
* Timing of MSN0—MSN3 is the same as the address bus.
Table 34. Timing Characteristics for External Memory Interface (See Figures 7 and 8.)
Abbreviated
Reference
t8†
t8a†
t10
t10a
t11
t12
t13†
t13a
t14
t14a
t14b†
t15†
t15a
t15b
t16
t17
t17b
t17c
t17d
t18†
t20
t20a
t20b
IEEE
50 ns*
Symbol
Min
Max
tCKOLABV
0
5
tCKOLABX
0
—
tCKOLRWNV
0
5
tCKOLRWNX
0
—
tCKOLCYCNL
0
4
tCKOLCYCNH
0
4
tABVASNL
0.5T – 1 0.5T + 3
tCKOHASNL
0
4
tASNLASNH 1.5T – 2 +
—
NT
tCKOLASNH
0
3
tASNHABX
0
—
tABVDSNH
2T – 3 +
—
NT
tCKOLDSNL
0
3
tCKOLDSNH
0
3
tDSNLDSNH
T–1+
—
NT
tMGNLMGNH 1.5T – 2
—
+ NT
tMGNHMGNL 0.5T – 1
—
tCKOHMGNL
0
5
tCKOLMGNH
0
5
tDSNHABX
0
—
tDSNHRWNX
0
—
tDSNHDBE
T
—
tMGNHDBE
T–2
—
60 ns*
80 ns*
Min
Max
Min
Max
0
6
0
8
0
—
0
—
0
6
0
8
0
—
0
—
0
5
0
6
0
5
0
6
0.5T – 1 0.5T + 3 0.5T – 3 0.5T + 3
0
4
0
5
1.5T – 2
—
1.5T – 2 +
—
+ NT
NT
0
4
0
5
0
—
0
—
2T – 3 +
—
2T – 5 +
—
NT
NT
0
4
0
5
0
4
0
5
T–1+
—
T–2+
—
NT
NT
1.5T – 2
—
1.5T – 4
—
+ NT
+ NT
0.5T – 1
—
0.5T – 2
—
0
5
0
6
0
5
0
6
0
—
0
—
0
—
0
—
T
—
T–1
—
T–2
—
T–4
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* T = tCKILCKIL; N = number of wait-states; NT is the product of N and T.
† Timing of MSN0—MSN3 is the same as the address bus.
56
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Timing Requirements and Characteristics (continued)
External Memory Interface (EMI) Timing (continued)
Table 34. Timing Characteristics for External Memory Interface (continued) (See Figures 7 and 8.)
Abbreviated
Reference
t20c
t21
IEEE
Symbol
tRWNLDBE
tDBVDSNH
t21a
t21c
t21e
t21f
t22
tDSNHDBZ
tCKOLDBZ
tCKOLDBV
tCKOLDBE
tDBVMWNH
t22a
t22b
t22c
t22d
t23
t23a
t24
t24a
t24b
tMWNLMWNH
tCKOHMWNL
tMWNHABX
tCKOHMWNH
tABVMGNL
tABVMWNL
tABVDSNL
tMWNHDBZ
tASNHDBZ
50 ns*
Min
T–1
T–3+
NT
—
0
0
0
0.5T – 2
+ NT
T + NT
0
0.5T – 2
0
0.5T – 2
0.5T – 2
T–2
0.5T – 2
–1
60 ns*
Max
—
—
2
—
4
—
—
—
4
—
3
—
—
—
0.5T + 2
2
Min
T–1
T–3+
NT
—
0
0
0
0.5T – 2
+ NT
T + NT
0
0.5T – 3
0
0.5T – 3
0.5T – 3
T–3
0.5T – 2
–1
80 ns*
Max
—
—
2
—
5
—
—
—
5
—
4
—
—
—
0.5T + 3
2
Min
T–2
T–5+
NT
—
0
0
0
0.5T – 2
+ NT
T + NT
0
0.5T – 4
0
0.5T – 4
0.5T – 4
T–4
0.5T – 2
–1
Unit
Max
—
—
ns
ns
2
—
8
—
—
ns
ns
ns
ns
ns
—
7
—
6
—
—
—
0.5T + 4
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
* T = tCKILCKIL; N = number of wait-states; NT is the product of N and T.
† Timing of MSN0—MSN3 is the same as the address bus.
AT&T Microelectronics
57
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Timing Requirements and Characteristics (continued)
External Memory Interface (EMI) Timing (continued)
Table 35. Definition of Timing Requirements for External Memory Interface (See Figures 7 and 8.)
Abbreviated
Reference
t25
t26
t27a
t27c
t27d
t27m
t28a
t28c
t28d
t28m
t29
t29a
t29d
t29m
IEEE
Symbol
tSRDYNLCKOH
tCKOHSRDYNH
tDBINASNH
tDBINVCKOL
tDBINVDSNH
tDBINVMGNH
tASNHDBX
tCKOLDBX
tDSNHDBX
tMGNHDBX
tABVDBINV
tASNLDBINV
tDSNLDBINV
tMGNLDBINV
Parameter
SRDYN Setup to CKO High
SRDYN Hold After CKO High
DATA in Setup to Address Strobe High
DATA in Setup to CKO Low
DATA in Setup to Data Strobe High
DATA in Setup to Read Strobe High
DATA in Hold After Address Strobe High
DATA in Hold After CKO Low
DATA in Hold After Data Strobe High
DATA in Hold After Read Strobe High
Address Valid to DATA in Valid*
Address Strobe Low to DATA in Valid
Data Strobe Low to DATA in Valid
Read Strobe Low to DATA in Valid
* Timing of MSN0—MSN3 is the same as the address bus.
Table 36. Timing Requirements for External Memory Interface (See Figures 7 and 8.)
Abbreviated
Reference
t25
t26
t27a
t27c
t27d
t27m
t28a
t28c
t28d
t28m
t29†
t29a
t29d
t29m
50 ns
Min
4
0
6
3
6
8
0
0
0
0
—
—
—
—
Max*
—
—
—
—
—
—
—
—
—
—
2T – 7 + NT
0.5T – 5 + NT
T – 5 + NT
1.5T – 7 + NT
60 ns
Min
5
0
7
4
7
9
0
0
0
0
—
—
—
—
Max*
—
—
—
—
—
—
—
—
—
—
2T – 8 + NT
0.5T – 6 + NT
T – 6 + NT
1.5T – 8 + NT
80 ns
Min
6
0
8
5
8
10
0
0
0
0
—
—
—
—
Unit
Max*
—
—
—
—
—
—
—
—
—
—
2T – 10 + NT
1.5T – 8 + NT
T – 8 + NT
1.5T – 10 + NT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* T = tCKILCKIL; N = number of wait-states; NT is the product of N and T.
† Timing of MSN0—MSN3 is the same as the address bus.
58
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Timing Requirements and Characteristics (continued)
Serial I/O (SIO) Timing
Note: Serial I/O is fully static; however, the maximum clock period (input and output) is tested only to the values
stated in Table 37 and Table 38.
Table 37. Timing Requirements and Characteristics for Serial Input (See Figure 9.)
Abbreviated
Reference
t31
t32
t33
t34
t35
t36
t37
t38
t39
t40
IEEE
Symbol
tICKLICKL
tICKLICKH
tICKHICKL
tILDHICKH
tICKHILDX
tILDLICKH
tICKHILDX
tDIVICKH
tICKHDIX
tICKHIBFH
Parameter
Clock Period
Clock Low Time
Clock High Time
Load High Setup
Load High Hold
Load Low Setup
Load Low Hold
Data Setup
Data Hold
Input Buffer Delay
50 ns
Min
Max
25
1000
11
—
11
—
5
—
0
—
5
—
0
—
5
—
0
—
—
12
60 ns
Min
Max
30
1000
13
—
13
—
6
—
0
—
6
—
0
—
6
—
0
—
—
14
80 ns
Min
Max
40
1000
18
—
18
—
8
—
0
—
8
—
0
—
8
—
0
—
—
23
Unit
60 ns
Min
Max
30
1000
13
—
13
—
6
—
0
—
6
—
0
—
80 ns
Min
Max
40
1000
18
—
18
—
8
—
0
—
8
—
0
—
Unit
60 ns
Min
Max
—
14
2
—
—
14
80 ns
Min
Max
—
23
2
—
—
23
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 38. Timing Requirements for Serial Output (See Figure 10.)
Abbreviated
Reference
t41
t42
t43
t44
t45
t46
t47
IEEE
Symbol
tOCKLOCKL
tOCKLOCKH
tOCKHOCKL
tOLDHOCKH
tOCKHOLDX
tOLDLOCKH
tOCKHOLDX
Parameter
Clock Period
Clock Low Time
Clock High Time
Load High Setup
Load High Hold
Load Low Setup
Load Low Hold
50 ns
Min
Max
25
1000
11
—
11
—
5
—
0
—
5
—
0
—
ns
ns
ns
ns
ns
ns
ns
Table 39. Timing Characteristics for Serial Output (See Figure 10.)
Abbreviated
Reference
t48
t49
t50
IEEE
Symbol
tOCKHDOV
tOCKHDOX
tOCKHOBEH
t51
tOCKHOSEH
t52
t53
tOENLDOE
tOENHDOZ
AT&T Microelectronics
Parameter
Data Delay
Data Hold
Output Buffer
Empty Delay
Output Shift
Register Delay
Enable Delay
Disable Delay
50 ns
Min
Max
—
12
2
—
—
12
ns
ns
ns
—
12
—
14
—
23
ns
—
—
12
12
—
—
14
14
—
—
23
23
ns
ns
59
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Timing Requirements and Characteristics (continued)
Serial I/O (SIO) Timing (continued)
Note: Serial I/O is fully static; however, the maximum clock period (input and output) is tested only to the values
stated in Table 37 and Table 38.
Table 40. Timing Requirements for Serial Clock Generation (See Figure 11.)
Abbreviated
Reference
t54
t55
t56
t57
IEEE
Symbol
tSYHICKH
tSYHOCKH
tICKHSYX
tOCKHSYX
tSYLICKH
tSYLOCKH
tICKHSYX
tOCKHSYX
Parameter*
SY High Setup
50 ns
Min
Max
8
—
60 ns
Min
Max
8
—
80 ns
Min
Max
8
—
Unit
ns
SY High Hold
0
—
0
—
0
—
ns
SY Low Setup
8
—
8
—
8
—
ns
SY Low Hold
0
—
0
—
0
—
ns
* ICK or OCK is selected by ioc[1] (BC).
Table 41. Timing Characteristics for Serial Clock Generation (See Figure 11.)
Abbreviated
Reference
t58
t59
t60
t61†
t62†
t63†
IEEE
Symbol
tICKHSYL
tOCKHSYL
tICKHILDL
tOCKHOLDL
tSYLILDL
tSYLOLDL
tICKHICKH
tOCKHOCKH
tICKLICKH
tOCKLOCKH
tICKHICKL
tOCKHOCKL
Parameter*
Internal SY Delay
Internal Load
Delay
Internal Load/SY
Delay
Clock Period
Clock Low Time
Clock High Time
50 ns
Min
Max
—
12
60 ns
Min
Max
—
14
80 ns
Min
Max
—
23
Unit
ns
—
12
—
14
—
23
ns
—
12
—
14
—
23
ns
300/
100
135/
35
135/
35
—
360/
120
165/
45
165/
45
—
480/
160
220/
60
220/
60
—
ns
—
ns
—
ns
—
—
—
—
* ICK or OCK is selected by ioc[1] (BC).
† Depends on the value of the internal clock, determined by ioc[18] (CKI). Either CKI ÷ 8 or CKI ÷ 24.
60
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Timing Requirements and Characteristics (continued)
Parallel I/O (PIO) Timing
Table 42. Timing Requirements for PIO Read Cycle (See Figure 12.)
Abbreviated
Reference
t64
t65
t70a
t76g
IEEE
Symbol
tPAVPRL
tPRHPAX
tPRLPRH
tPRWHPRWL
Parameter
50 ns
Min*
Max
5
—
0
—
2T
—
2T
—
Address Setup
Address Hold
Read Pulse
PIO Idle†
60 ns
Min*
Max
6
—
0
—
2T
—
2T
—
80 ns
Min*
Max
8
—
0
—
2T
—
2T
—
Unit
ns
ns
ns
ns
* T = tCKILCKIL.
† A minimum 2T interval is required for the start of the read or write cycle following the end of the previous read or write cycle.
Table 43. Timing Characteristics for PIO Read Cycle (See Figure 12.)
Abbreviated
Reference
t66
t67
IEEE
Symbol
tPRLPDV
tPRHPDZ
Parameter
Access from Read
Data Hold from Read
50 ns
Min*
Max
—
17
2
7
60 ns
Min*
Max
—
20
2
8
80 ns
Min*
Max
—
30
2
10
Unit
60 ns
Min*
Max
6
—
0
—
2T
—
15
—
0
—
2T
—
80 ns
Min*
Max
8
—
0
—
2T
—
20
—
0
—
2T
—
Unit
ns
ns
Table 44. Timing Requirements for PIO Write Cycle (See Figure 13.)
Abbreviated
Reference
t68
t69
t70
t71
t72
t76g
IEEE
Symbol
tPAVPWL
tPWHPAX
tPWLPWH
tPDVPWH
tPWHPDX
tPRWHPRWL
Parameter
Address Setup
Address Hold
Write Pulse
Data Setup
Data Hold
PIO Idle†
50 ns
Min*
Max
5
—
0
—
2T
—
10
—
0
—
2T
—
ns
ns
ns
ns
ns
ns
* T = tCKILCKIL.
† A minimum 2T interval is required for the start of the read or write cycle following the end of the previous read or write cycle.
Table 45. Timing Characteristics for PDF and PIF (See Figure 12 and Figure 13.)
Abbreviated
Reference
t73
t73a
t74
t75
t76a
t76
IEEE
Symbol
tPWHPDFH
tPWHPIFH
tPRLPDFL
tPRLPIFL
tPRHPDFL
tPRHPIFL
Parameter
PDF Write Delay
PIF Write Delay
PDF Read Delay
PIF Read Delay
PDF Read Delay
PIF Read Delay
50 ns
Min
Max*
—
T + 15
—
T + 15
—
15
—
15
—
T + 15
—
T + 15
60 ns
Min
Max*
—
T + 18
—
T + 18
—
18
—
18
—
T + 18
—
T + 18
80 ns
Min
Max*
—
T + 25
—
T + 25
—
28
—
28
—
T + 25
—
T + 25
Unit
ns
ns
ns
ns
ns
ns
* T = tCKILCKIL.
AT&T Microelectronics
61
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Timing Requirements and Characteristics (continued)
Parallel I/O (PIO) Timing (continued)
Table 46. Timing Requirements and Characteristics for PIOP (See Figure 14.)
Abbreviated
Reference
t76b
t76c
IEEE
Symbol
tPIOPVCKOL
tCKOLPIOPX
Parameter
PIOP Setup
PIOP Hold
50 ns
Min*
Max
7
—
0
—
60 ns
Min*
Max
8
—
0
—
80 ns
Min*
Max
10
—
0
—
Unit
80 ns
Min*
Max
5
—
—
35
Unit
ns
ns
Table 47. Timing Requirements and Characteristics for PIOP (See Figure 14.)
Abbreviated
Reference
t76d
t76e
IEEE
Symbol
tCKOHPIOPX
tCKOHPIOPV
Parameter
PIOP Output Hold
PIOP Output Delay
Reset and Interrupt Timing
The following terms describe reset:
Reset state — The DSP32C is in the reset state when
the internal reset signal is asserted, initializing the internal states of the chip. This state is entered when:
Power-on reset is detected, or
ZN and RESTN pins are low, or
A 0-to-1 transition is detected on RESTN, or
A 0-to-1 transition is detected on pcr[0] (only if
RESTN = 1).
Powerup reset — Powerup reset occurs during the
first eight clock cycles after power has been applied
(VDD ≥ 3 V). On-chip circuitry detects powerup and
puts the chip in the reset state.
Reset sequence — The reset sequence is the execution of the internally generated instructions call 0 (r14)
followed by nop. The reset sequence always follows
the reset state.
Halt mode — The DSP32C is executing internally
generated nops during the halt mode. PIO DMA remains active.
50 ns
Min*
Max
4
—
—
15
60 ns
Min*
Max
4
—
—
20
ns
ns
At this time, the logic levels of RESTN and ZN (both
are active-low) control the DSP32C's operation:
ZN
0
x*
1
RESTN
0
1
0
Description
Remain in the reset state.
Perform reset sequence then run.
Perform reset sequence then halt.
* x denotes don't care.
Reset and halt operation. While in the run mode, the
DSP32C can be placed in other modes by asserting
the RESTN and ZN pins or by using the pcr register.
To enter the halt mode, assert RESTN or write
pcr[0] = 0. Note that RESTN has priority over pcr[0].
To bring the chip out of the halt mode, deassert
RESTN or write pcr[0] = 1. This initiates a reset state
followed by the reset sequence followed by the run
mode.
To enter the reset state immediately, assert ZN and
RESTN. Subsequent operations are the same as on
powerup.
To enter the halt mode using only the RESTN signal
(see Figure 18):
1. Assert RESTN.
Run mode — The DSP32C is fetching and executing
instructions.
2. Deassert RESTN. The reset state is performed,
followed by the reset sequence.
Powerup reset sequences. On powerup of the
DSP32C, on-chip circuitry puts the device in the reset
state for the first eight clock cycles.
3. Assert RESTN, again, within 10 clock cycles. The
DSP32C enters the halt mode without executing
any instructions.
62
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Timing Requirements and Characteristics (continued)
Reset and Interrupt Timing (continued)
Table 48. Definition of Timing Requirements and Characteristics for Interrupts and Reset
(see Figure 15, Figure 18, and Figure 19)
Abbreviated
Reference
t77
t78
t79
t79a
t79b
t79c
t80
IEEE
Symbol
tINTREQLINTREQH
tIACKHINTREQH
tRESTNLRESTNH
tPUSV
tRESTNHZNH
tHALT
tCKOLIACKH
Parameter
INTREQ Assertion to Guarantee Interrupt Is Recognized
Interrupt Acknowledge to Request Deassertion
RESTN Assertion to Guarantee Reset
Powerup to RESTN and ZN Valid
RESTN High to ZN High
RESTN High to RESTN Low (enter halt after reset)
Interrupt Acknowledge Asserted with Respect to CKO
Table 49. Timing Requirements and Characteristics for Interrupts and Reset
(see Figure 15, Figure 18, and Figure 19)
Abbreviated
Reference
t77
t78
t79
t79a
t79b
t79c
t80
50 ns*
Min
Max
4T + 6
—
—
2T
4T – 6
—
0
4T – 10
—
8T †
—
10T
—
7
60 ns*
Min
Max
4T + 8
—
—
2T
4T – 8
—
0
4T – 10
—
8T †
—
10T
—
8
80 ns*
Min
Max
4T + 10
—
—
2T
4T – 10
—
0
4T – 10
—
8T †
—
10T
—
10
Unit
ns
ns
ns
ns
ns
ns
ns
* T = tCKILCKIL.
† ZN may be asserted at any time. This maximum specification permits correct DSP32C operation.
Assertion of ZN for longer than 8T keeps all DSP32C outputs in a high-impedance state.
AT&T Microelectronics
63
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Timing Requirements and Characteristics (continued)
Bus Request Timing
Table 50. Definition of Timing Requirements and Characteristics for Bus Request
(See Figure 16 and Figure 17.)
Abbreviated
Reference
t81
t82
t83
t84
t85
t86
t87
t88
t89
t90
IEEE
Symbol
tBREQNLCKOL
tCKOLCKOH
tCKOHBRACKNL
tBRACKNLABZ
tBREQNHCKOL
tCKOLCKOH
tCKOHBRACKNH
tBRACKNHABV
tCKOLMGNL
tCKOLMGNH
Parameter
BREQN Setup Time to CKO Low
Synchronous Bus Request Interval
BRACKN Delay After CKO High
BRACKN Asserted to EMI High Impedance
BREQN Setup Time to CKO Low
Synchronous Bus Request Deassertion Interval
BRACKN Delay After CKO High
BRACKN Deasserted to EMI Signals Active
MGN/EAPN Asserted After CKO Low
MGN/EAPN Deasserted After CKO Low
Table 51. Timing Requirements and Characteristics for Bus Request
(See Figure 16 and Figure 17.)
Abbreviated
Reference
t81
t82
t83
t84
t85
t86
t87
t88
t89
t90
50 ns*
Min
6
2.5T
—
—
6
1.5T
—
0
—
—
Max
—
3.5T + NT
6
0
—
—
6
—
6
6
60 ns*
Min
7
2.5T
—
—
7
1.5T
—
0
—
—
Max
—
3.5T + NT
7
0
—
—
7
—
7
7
80 ns*
Min
8
2.5T
—
—
8
1.5T
—
0
—
—
Max
—
3.5T + NT
8
0
—
—
8
—
8
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* T = tCKILCKIL; N = number of wait-states in external memory transaction; NT is the product of N and T.
64
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Timing Diagrams
t1
t2
t3
VIH–
CKI VIM (1.5 V)–
VILO (0.5 V)–
t5
t4
t7
t6
VOH–
CKO VOM (1.5 V)–
VOL–
t6b
t6a
5-3622(C)
Figure 6. Clock In and Clock Out
EXTERNAL WRITE
CKO
EXTERNAL READ
*
VOM
EXTERNAL WRITE
*
EXTERNAL READ
*
EXTERNAL READ
*
INTERNAL
*
*
AB[21:00] VOM– VOH–
VOL–
t8a
t8
t14b
t18
MSN[3:0] VOM– VOH–
VOL–
t10
RWN
t20
t10a
VOM–
t14a
t13a
ASN
VOM–
CYCLEIN
VOM–
t13
t11
t28d
t16
VOM–
VOM–
t24
t21
t22a
t23a
t22d
t27m
t20a
t23
t22
t17b
VOM–
t20c
t21e
VOH–
VOL–
HI-Z
OUTPUT
ACTIVE
HI-Z
t29m
t29
t20b
t24b
t21c
t21f
DB[31:00]
t27d
t29d
t17
t17c
t17d
MGN
t28a
t27a
t15
t15a
t22b
MWN
t29a
t12
t15b
DSN
t14
t27c
t28c
DATA
IN
HI-Z
t28m
t21a
t24a
OUTPUT
ACTIVE
HI-Z
DATA
IN
HI-Z
DATA
IN
5-3623(C)
* Additional clock periods are added here for memory waits.
Figure 7. External Memory Transactions (No Wait-States from External Memory)
AT&T Microelectronics
65
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Timing Diagrams (continued)
EXTERNAL WRITE
WAIT
CKO
WAIT
WAIT
WAIT
WAIT
WAIT
VOM–
AB[21:00] VOM–VOH–
VOL–
t8a
t22c
t8
MSN[3:0] VOM–VOH–
VOL–
t10
RWN
INTERNAL
MEMORY
TRANSACTION
EXTERNAL READ
t14b
t10a
VOM–
t14a
t13a
ASN
VOM–
t11
CYCLEIN
t12
VOM–
t15a
t15b
DSN
VOM–
t22b
MWN
t22d
VOM–
t17c
MGN
DB[31:00]
VOM–
VOH–
VOL– HI-Z
t21e
t21f
t21c
t28c
t24b
OUTPUT ACTIVE
t25
t26
SRDYN
t17d
t27c
t25
HI-Z
t25
t26
t26
DATA
IN
t26
t25
VIM–
5-3624(C)
Note: SRDYN assertion is not necessary for wait-states programmed with pcw[MEMA]/pcw[MEMB] = 00, 01, or 10 and
pcw[WA]/pcw[WB] = 1.
Figure 8. External Memory Transactions (Wait-States from External Memory)
66
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Timing Diagrams (continued)
t31
t32
t33
VIH–
ICK VIM (1.5 V)–
t34
t37
t35
t36
VIH–
VIM–
VIL–
ILD
t38
VIH–
DI
t39
b0
VIL–
bn – 1
t40
IBF
VOM–
5-3625(C)
Figure 9. Serial Input Timing
t41
t42
OCK
VIM–
t44
OLD
t43
t45
t46
t47
VIH–
VIM–
VIL–
t48
VOH–
DO
t49
b0
bn – 1
VOL–
t50
OBE VOM–
t51
OSE VOM–
t53
t52
OEN
VIM–
5-3626(C)
Figure 10. Serial Output Timing
AT&T Microelectronics
67
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Timing Diagrams (continued)
ICK, OCK
VIM–
t55
t56
t54
SY
t57
VIH–
VIM–
VIL–
t60
ILD, OLD
VOM–
A. External SY, ICK/OCK, Internal ILD/OLD
ICK, OCK
VIM–
t58
SY
VOM–
t59
ILD, OLD
VOM–
B. Internal SY, ILD/OLD, External ICK/OCK
ICK,
VOM (1.5 V)–
OCK
t63
t62
t61
C. Internal ICK/OCK
5-3627(C)
Figure 11. I/O Clock Generation Timing
68
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Timing Diagrams (continued)
VIH–
PAB
VIL–
t64
READ
(PEN + PGN)
t65
t70a
READ
OR
WRITE
VIM–
t76g
t66
PDB
t67
VOH–
DATA OUT
VOL–
t74
PDF1
VOM–
t75
PIF2 VOM–
t76a
PDF3 VOM–
t76
PIF4 VOM–
5-3628(C)
1. PDF changes at the beginning of a read transaction when pcr[10] = 0. PDF changes only when pdr(h) (8-bit mode) or pdr (16-bit
mode) is read. Reading pdr(l), pdr2(l), or pdr2(h) (8-bit mode), or reading pdr2 (16-bit mode) does not affect the PDF flag.
2. PIF changes at the beginning of a read transaction if pcr[10] = 0. If PIF high was caused by the loading of the pir register, PIF changes
when pir(h) (8-bit mode) is read, or pir(w) (16-bit mode) is read and pcr[2] (ENI) is set (1).
3. PDF changes at the end of a read transaction if pcr[10] = 1. (See Note 1 for a description of PDF logic.)
4. PIF changes at the end of a read transaction if pcr[10] = 1. (See Note 2 for a description of PIF logic.) PIF also changes when the esr
register is read (if PIF high was caused by an unmasked error).
Figure 12. PIO Timing — Read Cycle
AT&T Microelectronics
69
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Timing Diagrams (continued)
PAB
VIH–
VIL–
t68
WRITE
VIM–
(PEN + PWN)
(PGN NOT ASSERTED)
PDB
t69
READ
OR
WRITE
t70
t71
VIH–
t76g
t72
DATA IN
VIL–
t73
PDF* VOM–
t73a
PIF† VOM–
5-3629(C)
*
PDF changes only when pdr(h) (8-bit mode) or pdr (16-bit mode) is written. Writing pdr(l), pdr2(l), pdr2(h) (8-bit mode), or writing
pdr2 (16-bit mode) does not affect the PDF flag.
†
If pcr[2] (ENI) is set (1), PIF changes when pir(h) (8-bit mode) or pir (16-bit mode) is written.
Figure 13. PIO Timing — Write Cycle (PGN High)
70
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Timing Diagrams (continued)
4 CKO CYCLES
CKO
VOM–
t76b
PIOP*
INPUT
VIH–
VIL–
t76c
DATA IN
t76e
t76d
PIOP
OUTPUT
VOH–
DATA OUT
VOL–
DATA
OUT
5-3630(C)
Note: The PIOP inputs are intended to sense slowly changing events. The DSP32C samples PIOP inputs once every four cycles of CKO;
the value of PIOP read reflects the PIOP when sampled by a DSP32C instruction that reads the PIOP register.
Figure 14. PIOP Timing
8-Bit PIO
When the DSP32C PIO is configured as an 8-bit port, the upper 8 bits of PDB can be configured by pcw[7—6] to
be two 4-bit input or output registers. The upper 8 bits of PDB are referred to as PIOP0—PIOP7.
When either PIOP0—PIOP3 or PIOP4—PIOP7 is configured as an input, the PIOP register can be read by the
DSP32C, at most, once every four cycles of CKO.
When either PIOP0—PIOP3 or PIOP4—PIOP7 is configured as an output, the corresponding bits of PDB change
only when the DSP32C program writes a different value to the corresponding bit in PIOP, or if pcw[6] (PIOPL) or
pcw[7] (PIOPH) is cleared. This may occur, at most, once every four cycles of CKO. (When pcw[6] or pcw[7] is
cleared, the corresponding bits of PDB become inputs, but the contents of the PIOP registers remain unchanged.)
AT&T Microelectronics
71
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Timing Diagrams (continued)
t77
INTREQ1,
INTREQ2
VIM–
t78
IACK1,
IACK2
VOM–
t80
CKO
VOM–
5-3631(C)
Figure 15. Interrupt Timing
CKO
VOM–
t81
BREQN
VIM–
BRACKN
VOM–
t82
t83
t84
AS, MSN, ASN, MWN,
DSN, RWN, CYCLEIN,
DB, MGN, (pcw[8] = 0)
5-3632(C)
Figure 16. Bus Request Assertion Timing
72
AT&T Microelectronics
Data Sheet
June 1995
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Timing Diagrams (continued)
CKO VOM–
t85
t86
BREQN VIM–
t87
BRACKN VOM–
t90
t89
EAPN/MGN
VOM–
(pcw[8] = 1)
CYCLEIN
VOH–
VOL–
t88
AB[21:00], MSN
VOH–
PENDING TRANSACTION STARTS
VOL–
DB[31:00], ASN, DSN, RWN, VOH–
MWN, MGN, (pcw[8] = 0)
VOL–
5-3633(C)
Figure 17. Bus Request Deassertion Timing
t79
RESTN
VIM–
ZN
VIH–
t79c
RESET
SEQUENCE
HALT
5-3634(C)
Figure 18. Reset and Enter Halt
VDD 3 V–
t79a
RESTN VIM–
RESET
STATE
RESET SEQUENCE
t79b
ZN VIM–
RUN
MODE
5-3635(C)
Figure 19. Power-On Reset Requirements
AT&T Microelectronics
73
AT&T DSP32C Digital Signal Processor
with External Memory Interface
Data Sheet
June 1995
Outline Diagrams
133-Pin CPGA Package (all dimensions are in inches)
PACKAGE
IDENTIFIER
1
A
A1 INDEX
POSITION
0.02 x 45° REF
TYP 4 CORNERS
0.115
0.162 ± 0.016
0.308
0.170
0.040
Ø 0.016
AT TIP
TYP ALL PINS
0.018 + 0.002 DIA TYP
– 0.001
1.36 SQ.
12 SPACES @ 0.100 ± 1.200
(TOLERANCE NONCUMULATIVE)
0.08 TYP
N
M
L
K
J
ORIENTATION
PIN
H
G
F
E
D
C
B
A
PIN GRID
COORDINATES
(REF ONLY)
1
2
3
4
5
6
7
8
9
10
11
12
13
+ 0.010
0.050 – 0.003 DIA TYP
4 CORNER STANDOFFS
PIN A1
INDEX MARK
5-3636(C)
74
AT&T Microelectronics
Data Sheet
June 1995
Outlines Diagrams
AT&T DSP32C Digital Signal Processor
with External Memory Interface
(continued)
164-Pin BQFP Package (all dimensions are in inches)
1.270/1.290 SQ.
1.140/1.160 SQ.
21
1 164
145
144
22
PIN #1
IDENTIFIER
0.130/0.150
62
104
0°—8°
0.020/0.040
0.036/0.046
103
63
DETAIL A
DETAIL A
0.180
MAX
0.025 TYP
0.008/0.014
SEATING PLANE
0.004 A
–A–
5-2195(C)
AT&T Microelectronics
75
For additional information, contact your AT&T Account Manager or the following:
U.S.A.: AT&T Microelectronics, 555 Union Boulevard, Room 21Q-133BA, Allentown, PA 18103
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC: AT&T Microelectronics Asia/Pacific, 14 Science Park Drive, #03-02A/04 The Maxwell, Singapore 0511
Tel. (65) 778-8833, FAX (65) 777-7495
JAPAN: AT&T Microelectronics, AT&T Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3-5421-1600, FAX (81) 3-5421-1700
For data requests in Europe:
AT&T DATALINE: Tel. (44) 1734 324 299, FAX (44) 1734 328 148
For technical inquiries in Europe:
CENTRAL EUROPE: (49) 89 95086 0 (Munich), NORTHERN EUROPE: (44) 1344 487 111 (Bracknell UK),
FRANCE: (33) 1 47 67 47 67 (Paris), SOUTHERN EUROPE: (39) 2 6601 1800 (Milan) or (34) 1 807 1700 (Madrid)
AT&T reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any
patent accompany the sale of any such product(s) or information.
Copyright © 1995 AT&T
All Rights Reserved
Printed in U.S.A.
June 1995
DS94-084DCON
RT
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