GPL169256A - Generalplus

GPL169256A - Generalplus
GPL169256A
16-bit LCD Controller with 2368 Dots
Driver
Dec. 19, 2013
Version 1.4
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice.
TECHNOLOGY INC. is believed to be accurate and reliable.
Information provided by GENERALPLUS
However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order.
No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPL169256A
Table of Contents
PAGE
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 3
2. BLOCK DIAGRAM ...................................................................................................................................................................................... 3
3. FEATURES .................................................................................................................................................................................................. 3
4. APPLICATION FIELD.................................................................................................................................................................................. 3
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 4
5.1. PAD ASSIGNMENT .................................................................................................................................................................................. 6
6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 7
6.1. CPU ..................................................................................................................................................................................................... 7
6.2. MEMORY ............................................................................................................................................................................................... 7
6.3. REGULATOR .......................................................................................................................................................................................... 7
6.4. PLL, CLOCK, POWER MODE................................................................................................................................................................... 7
6.5. POWER SAVING MODE ........................................................................................................................................................................... 7
6.6. LCD CONTROLLER ................................................................................................................................................................................ 8
6.7. LOW VOLTAGE DETECTION AND LOW VOLTAGE RESET............................................................................................................................. 8
6.8. INTERRUPT ............................................................................................................................................................................................ 8
6.9. I/O ........................................................................................................................................................................................................ 8
6.10. ADC (ANALOG TO DIGITAL CONVERTER)................................................................................................................................................. 9
6.11. DAC ..................................................................................................................................................................................................... 9
6.12. TIMER/COUNTER ................................................................................................................................................................................... 9
6.13. POWER SAVING, WAKEUP AND WATCHDOG ............................................................................................................................................ 10
6.14. UART ................................................................................................................................................................................................. 10
6.15. SERIAL PERIPHERAL INTERFACE(SPI)....................................................................................................................................................11
6.16. AUDIO ALGORITHM ................................................................................................................................................................................11
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 12
7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 12
7.2. DC CHARACTERISTICS (TA = 25℃) ...................................................................................................................................................... 12
8. APPLICATION CIRCUITS ......................................................................................................................................................................... 14
8.1. APPLICATION CIRCUIT - (1) ................................................................................................................................................................... 14
9. PACKAGE/ORDERING INFORMATION ................................................................................................................................................... 15
9.1. ORDERING INFORMATION ..................................................................................................................................................................... 15
10. DISCLAIMER............................................................................................................................................................................................. 16
11. REVISION HISTORY ................................................................................................................................................................................. 17
© Generalplus Technology Inc.
Proprietary & Confidential
2
Dec. 19, 2013
Version: 1.4
GPL169256A
16-BIT LCD CONTROLLER WITH 2368 DOTS DRIVER
1. GENERAL DESCRIPTION
3. FEATURES
The GPL169256A, a 16-bit architecture LCD controller product,
„ Built-in 16-bit μ’nSP 1.3 microprocessor
carries the SUNPLUS’s newest 16-bit microprocessor, μ’nSP
─ 256K-word ROM
(pronounced as micro-n-SP) and also has LCD driver built-in.
─ 4K-word SRAM
The high processing speed assures the μ’nSP™ is capable of
─ 592-word SRAM for LCD frame buffer
handling complex digital signal processes easily and rapidly.
─ CPU clock: Max. 48MHz
The
─ 18 INT sources can be selected as IRQ or FIQ
GPL169256A is applicable to digital sound processing application.
In addition, Liquid Crystal Display (LCD) capability strengthens the
GPL169256A to be used in variety of visual applications.
„ Three power saving modes:
The
Standby mode/Halt mode/Wait mode
memory capacity includes 4K-word SRAM for system and
Max. 5μA @ 3.6V in standby mode
592-word SRAM for LCD frame buffer and 256K-word ROM.
Max. 30μA @ 3.6V in halt mode(without LCD display)
The
GPL169256A provides single-chip solution with built-in driver to
Max. 180μA @ 3.6V in halt mode(with mono LCD display)
support maximum resolution up to 32x74.
Max. 2mA @3.6V in wait mode
Other features include
8 programmable multi-functional I/Os, three 16-bit timers/counters,
„ Programmable LCD driver
─ Up to 74 segments, up to 32 commons, maximum 2368 dots
32768Hz Real Time Clock, Low Voltage Reset/Detection and
many others.
Unused commons and segments can be set as I/O
─ 1/3~1/7 bias, 1/4, 1/6, 1/8,1/12, 1/16, 1/18, 1/32 duty
─ Adjustable LCD voltage (32 level)
2. BLOCK DIAGRAM
─ 592 words dedicated LCD RAM
─ Selectable black/white or 16-gray display
ICECLK
ICESDA
16-bit
u'nSP
and
ICE
controller
VCOIN
X32I
X32O
PLL
4KW
SRAM
256KW
ROM
CPU
Clock
RTC
„ Built-in 12-bit ADC with AGC
592W
SRAM
LCD Controller
Driver
„ Asynchronous serial interface (UART)
COM0~3
SEG0~47
„ Supports SPI interface
Memory
Controller
„ Three 16-bit timers/counters
„ Two-channel 16-bit DAC audio outputs
SPI
„ Maximum up to 37 general I/Os (8 dedicate I/Os, 29 shared
Timer/Counter
USBON
ROSC
GPIO
UART/IrDA
AUDA
AUDB
with commons/segments)
IOA[7:0]
IOB[2:0]
„ Key wakeup/interrupt function
IOC[15:0]
IOD[9:0]
DAC
„ PLL feature for system clock
„ 32768Hz Real Time Clock (RTC)
ADINA
12-bit ADC
ADINB
„ Low voltage reset and low voltage detection
LVD/LVR
WatchDog
„ Watchdog, system bus/address error reset
Int. Controller
„ Software-based audio processing
NOTE: PB[2:0] shared with VMIC/ADINA/ADINB; PC[15:0] shared with
COM[31:16]; PD[9:0] shared with COM[73:64]
4. APPLICATION FIELD
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„
Advanced educational toys or ELAs
„
Handheld LCD game with sound synthesizer
Dec. 19, 2013
Version: 1.4
GPL169256A
5. SIGNAL DESCRIPTIONS
Mnemonic
SEG[15:0]
Pin No.
Type
155-140
O
Description
LCD driver segment output
Can be shared with key scan port
SEG[63:16]
33-2, 171-156
O
LCD driver segment output
SEG[73:64]
43-34
O
LCD driver segment output
SEG[73:64] also shared pins with PD[9:0]
COM[31:0]
51-82
O
LCD driver common output
COM[31:16] also shared pins with PC[15:0]
IOA[7:0]
83-86, 127-130
I/O
IOA[7:0]: bi-directional I/O ports
IOA[7:0] can be software programmed to wakeup I/O pins and key strobe inputs
IOA[7] can be selected as Timer clock input or external interrupt input
IOA[6] can be selected as Timer input/output of CCP function
IOA[5:4] can be selected as UART RX/TX pins
IOA[3:1] can be selected as SPI interface signals SCK/SDO/SDI
RESETB
136
I
X6MON
139
I
External reset pin
This pin will control the ON/OFF of the 6MHz crystal and must be connected as
VDD or GND.
ICECLK
138
I
ICESDA
137
I/O
ICE data pin should be connected to ground if not in development mode.
AUDA
93
O
Audio DAC output
AUDB
96
O
Audio DAC output
X32I
123
I
32768Hz crystal input
X32O
124
O
32768Hz crystal output
TEST
135
I
Test pin
CAP1P, CAP1N
108, 109
P
LCD voltage generation.
Charge pump capacitor interconnection pins.
CAP2P, CAP2N
111, 110
P
LCD voltage generation.
Charge pump capacitor interconnection pins.
112
P
LCD voltage generation
VPP
ICE clock input pin should be connected to ground if not in development mode.
VLCD
113
P
VLCD highest voltage
V1
117
P
LCD bias voltage
V2
116
P
LCD bias voltage
V3
115
P
LCD bias voltage
V4
VDDIO_33
VSSIO
114
P
LCD bias voltage
50, 172
P
Power supply voltage input
1, 49
P
Ground reference
VDDANA_33
119
P
Power supply voltage input for analog circuit
VSSANA
118
P
Ground reference for analog circuit
VDDAUD_33
92
P
Power supply voltage input for DAC
VSSAUD
95
P
Ground reference for DAC
VDDREG_55
120
P
Power supply voltage input for core
VSSREG
122
P
Ground reference for core
VDDO_33
121
O
AVREF_DAC
94
MICP
102
A
Microphone differential input (positive)
MICN
101
A
Microphone differential input (negative)
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Regulator output voltage for core
DAC reference voltage pin
4
Dec. 19, 2013
Version: 1.4
GPL169256A
Mnemonic
Pin No.
Type
107
I/O
VMIC
Description
Output VDDADC when microphone enabled or used as GPIO.
VMIC also shared pins with PB[2]
st
MICOUT
100
A
Microphone 1 amplifier output
OPI
99
A
Microphone 2 amplifier input
AGC
98
A
AGC control pin
nd
VADREF
103
A
ADC reference pin
ADINA
104
A/I
ADC input
ADINB
105
A/I
ADINA also shared pins with PB[1]
ADC input
ADINB also shared pins with PB[0]
VDDADC_33
106
P
Power supply voltage input for ADC
VSSADC
97
P
Ground reference for ADC
X6MI
126
I
6MHz crystal input or RC filter connection for PLL
X6MO
125
O
6MHz crystal output
VDD_33
131
P
Power supply voltage input
NC
44-48, 87-91,
Non-used pin for user
132-134
Legend: I = Input, O = Output, P = Power
Total 172pins
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Dec. 19, 2013
Version: 1.4
GPL169256A
5.1. Pad Assignment
Note1: To ensure IC functions properly, please bond all of VDD and VSS pins.
Note2: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible.
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Dec. 19, 2013
Version: 1.4
GPL169256A
6. FUNCTIONAL DESCRIPTIONS
6.1. CPU
6.4.1.1. System clock
The GPL169256A is equipped with a 16-bit μ’nSP™, the newest
Basically, the system clock is provided by PLL to determine the
16-bit
system clock frequency.
microprocessor
micro-n-SP.
by
SUNPLUS
and
pronounced
as
The clock source could be selected
either from 6MHz crystal or 32KHz crystal.
Eight registers are involved in μ’nSP™: R1 ~ R4
(General-purpose registers), PC (Program Counter), SP (Stack
clock is around 6MHz after reset.
Pointer), Base Pointer (BP) and SR (Segment Register).
adjusted to desired CPU clock by software.
The
The default CPU
The CPU clock can be
new version of μ’nSP™ 1.3 contains four secondary registers and
6.4.1.2. 32768Hz RTC
supports many DSP functions and bit-operation instructions.
The RTC, Real Time Clock, is normally used in watch, clock or
The interrupts include three FIQs (Fast Interrupt Request) and
other time related products.
A 2Hz-RTC (0.5 seconds) function is
eight IRQs (Interrupt Request), plus one software-interrupt,
featured in GPL169256A.
The RTC is to compute timing and
BREAK.
wake CPU up whenever RTC occurs.
Moreover, a high performance hardware multiplier with
The timing can be traced
capability of FIR filter is also built in to reduce software
by number of RTC occurrences.
multiplication loading.
supports 32768Hz oscillator in strong mode and auto mode.
Besides, nested IRQ is also supported.
In addition, GPL169256A
In
strong mode, 32768Hz OSC always runs at the highest power
consumption.
Phase Lock Loop
32768Hz X'tal
System Clock generator
S2
S1
the first 7.5 seconds and switches back to weak mode
CPU Clock
(PLL)
S0
System clock frequency selection
automatically to save powers.
6M/5.997MHz(default)
12M/11.993MHz
18M/17.990MHz
24M/23.986MHz
30M/29.983MHz
36M/35.979MHz
42M/41.976MHz
48M/47.972MHz
6.5. Power Saving Mode
The GPL169256A features three power saving modes: WAIT
mode, HALT mode, and STANDBY mode.
6.2. Memory
The GPL169256A contains 4KW SRAM and 592W dual-port
SRAM dedicated to support LCD display.
In auto mode, however, it runs in strong mode for
The frame buffer is
Wait
Halt
Standby
CPU
OFF
OFF
OFF
PLL
ON
OFF
OFF
RTC
ON
ON
OFF
6.5.1. Wait mode
able to support maximum 32x74 16-gray display.
In WAIT mode, only CPU is disabled.
6.3. Regulator
active to keep LCD display function.
After GPL169256A is
awakened from wait mode, CPU will continue to execute the
There is a built-in regulator that provides approximate 3V core
power from 3-battery power system.
The PLL and RTC are still
program from previous state.
The regulator could also be
code-optioned to mark-off in 2-battery applications.
6.5.2. Halt mode
6.4. PLL, Clock, Power Mode
In HALT mode, both CPU and PLL are OFF and only RTC is
6.4.1. PLL (Phase Lock Loop)
keeping active.
There are two PLLs built-in in GPL169256A to provide the system
clock.
The 6MHz crystal or boost-up from 32768Hz clock could
6.5.3. Standby mode
be selected to provide the clock source of fast PLL to generate
48MHz clock.
After GPL169256A is awakened form Halt mode,
the CPU will execute the program from reset state.
While in STANDY mode, all modules are OFF to keep at the
The slow PLL is to generate the 5.997MHz clock
lowest power consumption.
from 32768Hz crystal and could be the clock source of the fast
In such mode, RAM and I/Os remain
in the previous states till CPU being awakened.
PLL.
The wakeup
sources in GPL169256A can be IOA/IOB/IOC/IOD.
After
GPL169256A is awakened from standby mode, the CPU will
execute the program from reset state.
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Dec. 19, 2013
Version: 1.4
GPL169256A
6.6. LCD Controller
32768HZ
The GPL169256A contains a powerful LCD controller, which can
support up to 16 gray levels for monochrome STN.
With built-in
VDD
LCD driver function, GPL169256A provides a single-chip solution,
2.4V
Tw
which supports maximum resolution up to 32x74 with 16 gray
levels.
RESET
6.6.1. LCD Voltage Generation
Reset
Tw=32768HZ x 4 cycle
To achieve highly integrated circuit and save external components
as possible, the GPL169256A has built-in charge pump circuit and
operational amplifiers to generate LCD’s bias voltages VLCD, V4,
V3, V2 and V1.
approx. to 8V.
6.8. Interrupt
The charge pump circuit can generate VPP
The GPL169256A has 18 interrupt sources.
With VPP as power source, an operational
amplifier is further to provide LCD panel’s power supply, VLCD.
The level of VLCD can be adjusted by software.
Request) or IRQ (Interrupt Request) individually.
It is suggested
FIQ is higher than IRQ.
that VLCD must be higher than VDD by 0.7V, otherwise, abnormal
IRQ7 ~ IRQ0.
6.7.1. Low Voltage Detection (LVD)
There are four LVD levels to be selected: 2.2V,
2.4V, 2.6V and 2.8V.
Those levels can be programmed via
As an example, suppose LVD is given to 2.8V.
When the voltage drops below 2.8V, the b15 of 0x7009 is read as
In such state, program is designed to handle this
situation.
6.7.2. Low Voltage Reset (LVR)
In addition to LVD, the GPL169256A offers another important
feature, Low Voltage Reset (LVR).
2.4V.
The level of LVR voltage is
The LVR detects whether the power input of regulator is
below the voltage.
IRQ7 is the lowest priority interrupt.
Interrupt Source
The Low Voltage Detection (LVD) reports the circumstance of
HIGH.
When IRQ and FIQ happen
simultaneous, IRQ has the lower priority than FIQ and so do the
6.7. Low Voltage Detection and Low Voltage Reset
0x7009 (W).
The priority of
FIQ is the high-priority interrupt while
IRQ is the low-priority one.
operation will occur.
present voltage.
Some of the
interrupt sources could be programmed as FIQ (Fast Interrupt
With the LVR function, a reset signal is
Interrupt Group
Priority
Audio ChannelA
FIQ/IRQ0
Highest
Audio ChannelB
FIQ/IRQ0
Highest
EXT1
FIQ/IRQ2
High
DMA
FIQ/IRQ3
High
UART
FIQ/IRQ3
High
SPI
FIQ/IRQ3
High
TimerC
FIQ/IRQ4
High
TimerB
FIQ/IRQ4
High
TimerA
FIQ/IRQ4
High
LCD Frame Pulse
FIQ/IRQ5
High
Key Change
FIQ/IRQ5
High
LVD
FIQ/IRQ6
High
generated to reset system when the operating voltage drops
Schedule
IRQ6
Low
below predetermined voltage for four consecutive clock cycles.
Time Base C
IRQ6
Low
Without LVR, the CPU becomes unstable and malfunctions when
Time Base B
IRQ7
Lowest
the operating voltage drops below 2.4V.
Time Base A
IRQ7
Lowest
all functions to the initial operational (stable) states when the
Alarm
IRQ7
Lowest
voltage drops below 2.4V.
RTC
IRQ7
Lowest
Using LVR, it will reset
A LVR timing diagram is given as
follows:
6.9. I/O
Maximum four I/O ports are provided in GPL169256A: IOA, IOB,
IOC and IOD.
In addition to regular IO function, all I/Os are
shared with special function pins.
The following diagram is an I/O
schematic.
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Version: 1.4
GPL169256A
Buffer(R)
Port_Data(W)
Register
Port_Buffer(W)
Clock of Source A
Clock of Source B
Clock of Source C
SYSCLK/2
2048Hz
SYSCLK/2
SYSCLK/256
1024Hz
SYSCLK/256
32768Hz
256Hz
32768Hz
8192Hz
TMBB
8192Hz
4096Hz
TMBA
4096Hz
pull high
Pin pad
Control
logic
Port_DIR(R/W)
pull low
Port_ATTR(R/W)
1
0
1
TimerB overflow
1
0
EXTA
0
EXTA
PWM service rate
-
PWM service rate
Data(R)
Although data can be written into the same register through
Port_Data and Port_Buffer, they can be read from different places,
TimerA and TimerB can operate in timer mode, counter mode,
Buffer (R) and Data (R).
capture mode, compare mode and PWM mode.
key wakeup capability.
The IOA is software programmable for
TimerC can
operate in timer mode and counter mode.
To activate key wakeup function, latch
data on PORT_IOA_RL and enable the key wakeup function.
Wakeup is triggered when the IOA state is different from at the
6.12.1. Timer mode
time latched.
Initially, write a value of N into a timer and select a desired clock
source, timer will start counting from N, N+1, N+2…, through FFFF.
6.10. ADC (Analog to Digital Converter)
An INT (TimerA/TimerB/TimerC) signal is generated at the next
The GPL169256A has built-in three 12-bit A/Ds (Analog to Digital
clock after reaching “FFFF” and the INT signal is transmitted to
Converter) channels; one is the microphone input channel and two
INT controller for further processing.
are line-in channels.
reloaded into timer and start all over again.
The function of an A/D converter is to
At the same time, N will be
The clock source A is
convert analog quality signal, e.g. a voltage, into a digital word.
a high frequency source and clock source B is a low frequency
Or convert from an input source which can be line-in from
source.
ADINA/ADINB or microphone input through amplifier and AGC
variety of speed to TimerA.
controller.
gating.
The MIC amplifier circuit is capable of reducing
The combination of clock source A and B provides a
A “1” represents pass signal and not
In contrast, “0” indicates deactivating timer.
common mode noise by transmitting signals through MIC’s fully
differential input.
6.12.2. Counter mode
Moreover, an external resistor can be applied to
adjust microphone gain and time of AGC operating.
needs to select source of line-in before converting.
The AD
The EXTA is the external clock source (shared with IOA[7]).
The ADC
The
external clock source can be divided by 1, 4 or 16 pre-scaler
chooses internal power (=AVDD) as top reference voltage.
divider and capable of selecting clock edge.
6.11. DAC
6.12.3. Capture mode
The GPL169256A imposes two 16-bit DACs and therefore
In capture mode, the content of timer/counter is stored in register
superior sound effect can be generated with less distortion.
at the selected edge of pins CCP (special function of IOA[6]) by
the selected rate.
6.12. Timer/Counter
This could be used to detect the pulse width of
CCP.
The GPL169256A has three 16-bit timers/counters: TimerA,
TimerB and TimerC.
6.12.4. Comparison mode
The clock source of TimerA comes from the
combination of clock source A and clock source B.
TimerC, the clock source is given from source C.
In TimerB and
In comparison mode, CCP will be programmed as output
When timer
automatically.
The initial value is loaded from pre-load register
overflows, an INT signal is sent to CPU to generate a time-out
and after count to the pre-set value, hardware will set or clear
signal.
CCP or leave it unaffected.
When timer/counter overflows, initial
value will not be reloaded but interrupt flag will be generated.
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GPL169256A
6.12.5. PWM mode
SYSTEM
RESET
In PWM mode, the operation is similar to comparison mode except
that the initial value will reloaded whenever timer/counter overflow
is.
Write
5xx5
to
$700C
Generally, the clock source A and C are fast clock sources and
source B comes from RTC system (32768Hz).
Therefore, clock
Wait
Normal
source B can be utilized as a punctual counter for time count, e.g.,
Wakeup
the 2Hz clock can be used for real time counting.
6.12.6. Timebase
Halt
Timebase, generated by 32768Hz, is a combination of frequency
selections.
Write
AxxA
to
$700E
Write
5xxA
to
$700D
Standby
The outputs of timebase module are named TMBA,
TMBB, and TMBC.
TMBA and TMBB can be clock source for
TimerA (clock source B).
Wakeup
The TMBA and TMBB are the sources
Wakeup
CPU
Reset
for Interrupt (IRQ7) whereas TMBC is the source for interrupt
(IRQ6).
TMBC
TMBB
Note1: When GPL169256A enters Wait mode, any interrupt will awake
TMB1
128Hz
8Hz
Reserved
256Hz
16Hz
1Hz
512Hz
32Hz
2Hz
1024Hz
64Hz
4Hz
Default: 128Hz
Default: 8Hz
Default: 2Hz
GPL169256A.
After GPL169256A is awoken, CPU continues to
execute next instruction.
Note2: When GPL169256A enters Halt or Standby mode, any interrupt will
awake GPL169256A.
After GPL169256A is awoken, CPU will be
reset to initial state.
6.13.2. Watchdog
The purpose of watchdog is to monitor if the system operates
6.13. Power saving, Wakeup and Watchdog
normally.
6.13.1. Power saving and Wakeup
cleared.
1).
Wakeup:
If
any
interrupt
happens,
GPL169256A
will be executed all over again.
disabled by software.
is
The watchdog function can be
In GPL169256A, the clear period can be
programmed from 62.5ms to 2 seconds (default).
awakened.
3).
As a result, system
or CPU will be reset according to register setting and the program
After reset, IC starts
running until a power saving signal occurs.
2).
If watchdog is not cleared, CPU assumes the program
has been running in an abnormal condition.
Power saving: In GPL169256A, CPU has three power saving
mode, Wait/Halt/Standby mode.
Within a certain period of time, watchdog must be
If watchdog is
cleared within the given time period, the system or CPU will not be
The following diagram shows the three conditions:
reset.
To
clear
watchdog,
Port_Watchdog_Clear(W).
simply
write
“Axx5(h)”
to
The watchdog function remains
enabled during wait mode and halt mode where the 32768Hz is
still turned on.
6.14. UART
The UART module provides a full-duplex standard interface that is
able to communicate with other devices.
With this interface,
GPL169256A can transmit and receive simultaneously.
maximum baud-rate can be up to 115200bps.
The
This function can
be accomplished by using IOA and Interrupt (UART IRQ).
The
Rx and Tx of UART are shared with IOA[5] and IOA[4].
The
UART has two 16-byte FIFOs to store transmitted and received
data.
The UART status register will indicate status when the
FIFOs are empty, half-full or full.
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GPL169256A
start
bit
D0
D1
D2
1-bit Start
D3
D4
D5
D6
8-bit data
D7
parity
bit
stop
bit
can be enabled/disable;
also even/odd check
1-bit Stop
6.15. Serial Peripheral Interface (SPI)
6.16. Audio Algorithm
The SPI interface is a master/slave interface that enables
The following speech types can be used in GPL169256A: PCM,
synchronous serial communication with peripherals.
Two 16-byte
LOG
FIFOs are used for transmitting and receiving data.
Four modes
SACM_S480,
with programmable phase and polarity of master clock are also
SACM_S880,
supported.
SACM_DVR1600, SACM_DVR4800, and SACM_DVR3200.
PCM,
SACM_A1600,
SACM_1601,
SACM_S200,
SACM_S530,
SACM_S720,
SACM_S320,
SACM_DVR1800,
SACM_DVR520,
For
melody synthesis, the GPL169256A provides a SACM_MS01 (FM
synthesizer) and SACM_MS02 wave-table synthesizer.
© Generalplus Technology Inc.
Proprietary & Confidential
11
Dec. 19, 2013
Version: 1.4
GPL169256A
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
Symbol
Ratings
VDD
< 3.6V
Input Voltage Range
VIN
-0.5V to VDD + 0.5V
Operating Temperature
TA
0℃ to +70℃
TSTO
-50℃ to +150℃
DC Supply Voltage
Storage Temperature
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device.
For normal operational conditions
see AC/DC Electrical Characteristics.
7.2. DC Characteristics (TA = 25℃)
Characteristics
Operating Voltage
Symbol
Limit
Min.
Typ.
Max.
VDD
2.4
-
3.6
VDDREG_55
2.4
-
5.5
Unit
V
Test Condition
All VDD pins except VDDREG_55
VDD = 3.6V, FOSC = 47.9232MHz,
Operating Current
IOP
-
40
-
mA
The wait cycle of internal ROM is 1
($704c.b3~b0)
VDD = 3.6V, 32K X’tal ON,
The wait cycle of internal ROM is 1
Wait Current
IWAIT1
-
-
2
mA
($704c.b3~b0), clock source OSC
1MHz.
LCD ON, no LCD panel, PLL ON
Halt Current
IHALT1
-
-
30
μA
Halt Current
IHALT2
-
-
180
μA
ISTB
-
-
3.0
-
6.0
3.19
-
6.6
V
VDD = 3.0V, 1/6 bias, no load
3.48
-
7.2
V
VDD = 3.0V, 1/7 bias, no load
Standby Current
LCD Driver Voltage
B
VLCD
5
10
μA
VDD = 3.6V, 32K X’tal & RTC ON
VDD = 3.6V, 32K X’tal & RTC ON,
mono LCD ON
VDD = 3.6V, all off, disable regulator
VDD = 3.6V, all off, enable regulator
VDD = 3.0V, 1/5 bias, no load
Input High Level
VIH
0.7 VDD
-
-
V
VDD = 3.0V
Input Low Level
VIL
-
-
0.3 VDD
V
VDD = 3.0V
Output High Current
IOH2
-2.0
-
-
mA
Output Low Current
IOL2
-2.0
-
-
mA
RPL
-
100
-
KΩ
RPH
-
100
-
KΩ
Input Pull-Low Resistor
(IOA)
Input Pull-High Resistor
(IOA)
© Generalplus Technology Inc.
Proprietary & Confidential
12
VDD = 3.0V, VOH = 2.4V
IOA[7:0]
VDD = 3.0V, VOL = 0.8V
IOA[7:0]
VDD = 3.0V
VIN = 3.0V
VDD = 3.0V
VIN = VSS
Dec. 19, 2013
Version: 1.4
GPL169256A
7.2.1. PLL Characteristics (TA = 25℃, VDD=3.0V, 6MHz crystal disable)
Characteristics
Symbol
VCO Operating Frequency
Fvco
Input Reference Clock Freq.
Fref
Limit
Min.
Typ.
Max.
11.993
-
95.945
Unit
MHz
-
32768
-
Hz
5.997
-
47.972
MHz
Start-up Time
-
-
5
ms
Lock-in Time
-
-
5
ms
Jitter (cycle-cycle)
-
1.5
-
%
Duty Cycle
-
50
-
%
Output Clock Freq.
Test Condition
7.2.2. ADC Characteristics (TA = 25℃, VDD=3.0V)
Characteristics
Symbol
ADC Resolution
RESO
Signal-to-noise Ratio
SINDR
+distortion
ADC Input Voltage
INL(Integral Non-linearity)
DNL(Differential Non-linearity)
@fin=1KHz
VIN
INL
DNL
No Missing Code
AD Conversion Rate
FCONV
Limit
Unit
Min.
Typ.
Max.
-
-
12
Bits
-
-
57
dB
VSS
-
VDD
V
-
±4.0
-
LSB
-
±0.8
-
LSB
10
11
-
Bits
-
-
FCPU/512
KHz
Test Condition
7.2.3. DAC Characteristics (TA = 25℃, VDD=3.0V)
Characteristics
Symbol
Limit
Typ.
Resolution
-
16
-
Bits
Input Data Sampling Freq.
-
-
192
KHz
Output Range
Max.
Unit
Min.
0.2
-
0.8
Vdd
125
-
-
ohm
THD+N at FS
-
0.1(-60dB)
-
%
Dynamic Range
-
80
-
dB
Output Loading
RLOAD
Test Condition
7.2.4. OSC Characteristics (TA = 25℃, VDD=3.0V)
Characteristics
Output Clock Frequency
Duty Cycle
Start-up Time
© Generalplus Technology Inc.
Proprietary & Confidential
Symbol
CLK32768
Limit
Unit
Min.
Typ.
Max.
-
32768
-
Hz
40
-
50
%
-
-
13
10000x
T32768
Test Condition
μs
Dec. 19, 2013
Version: 1.4
GPL169256A
8. APPLICATION CIRCUITS
8.1. Application Circuit - (1)
Note*1: These capacitor values are for design guidance only. We recommend user select the ESR < 35K as well as CL1=CL=20~30pF(including PCB
parasitic loading). Note that the environment humidity may affect the equivalent resistances on the two end points. To avoid the humidity effect, we
recommend user to apply 20pF(assume PCB parasitic loading is 6pF) on XI and XO. Note that a larger CL capacitance will cause a longer time for XTAL to
oscillate.
Note*2: These capacitor values are for design guidance only. The ratio of capacitance of CVPP to the capacitance of CAP1 and CAP2 is recommended to be
ten or more.
© Generalplus Technology Inc.
Proprietary & Confidential
14
Dec. 19, 2013
Version: 1.4
GPL169256A
9. PACKAGE/ORDERING INFORMATION
9.1. Ordering Information
Product Number
Package Type
GPL169256A-NnnV-C
Chip form
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
© Generalplus Technology Inc.
Proprietary & Confidential
15
Dec. 19, 2013
Version: 1.4
GPL169256A
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only.
GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement.
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE.
the specifications and prices at any time without notice.
Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders.
applications.
FURTHERMORE, GENERALPLUS MAKES NO
GENERALPLUS reserves the right to halt production or alter
Products described herein are intended for use in normal commercial
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications.
Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
Proprietary & Confidential
16
Dec. 19, 2013
Version: 1.4
GPL169256A
11. REVISION HISTORY
Date
Revision #
Description
DEC 19, 2013
1.4
Modify 8.1. Application Circuit.
14
SEP 16, 2013
1.3
Modify 8.1. Application Circuit.
14
OCT. 11, 2012
1.2
Modify 8.1. Application Circuit.
14
JUL. 29, 2010
1.1
Modify 8.1. Application Circuit and add notes.
15
1. Add description about ICECLK & ICESDA pin.
5
AUG. 20, 2009
1.0
nd
2. Add 2 ISTB condition on DC characteristics table.
13
Original
18
B
MAR. 13, 2008
0.1
© Generalplus Technology Inc.
Proprietary & Confidential
Page
17
Dec. 19, 2013
Version: 1.4
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