HMP8320VCS - Harris Semiconductor

HMP8320VCS - Harris Semiconductor
HMP8320VCS
S E M I C O N D U C T O R
ADVANCE INFORMATION
Video Conference Solution Chip Set
June 1997
Features
Description
• Fully Compliant with ITU-T H.320
The HMP8320VCS (Video Conference Solution) chip set is
fully compliant with the ITU-T H.320 Teleconferencing standard and designed to run with a host processor. The VCS
chip set consists of four Harris ICs: the video codec
(HMP8364); the audio link processor (HMP8201), the
NTSC/PAL video decoder (HMP8112) and an optional
NTSC/PAL video encoder (HMP8156). The H.320 (ISDN)
VCS chip set supports up to 30 frames per second of CIF
(Common Interface Format) or QCIF (Quarter CIF) video,
high quality audio, acoustic echo cancellation (AEC) and
advanced features such as document and applications sharing. To significantly reduce design investment of a video conference solution, Harris offers a complete VCS tool set that
includes a Manufacturer's Development Kit (MDK), Software
Development Kit (SDK) and Software License (SWL). This
tool set (reference design, application software, firmware
and license) allows the ability to design and produce a H.320
desk-top-video conference product within months.
• Multiplexes Video, Audio and User Data to ITU-T H.221
• Encodes and Decodes Video to ITU-T H.261 CIF up to
30 FPS or QCIF at 30 FPS
• Encodes and Decodes Audio to ITU-T G.711, G.722 or
G.728
• Adaptive Full Duplex Wide Band (7kHz) Echo Canceller
• Video Input from any Composite NTSC or PAL Camera
or VCR
• Y/C Video Input also Supported
• Standard MVIP and IOM-2 Interfaces to ISDN Board
• Basic Rate Interface ISDN is Supported
• Restricted Mode Line Rates are Supported (12 KBPS)
Applications
Ordering Information
• ITU H.320 Video Conferencing Systems
PART NUMBER
HMP8320VCS
TEMP.
RANGE (oC)
0 to 70
PACKAGE
NA
PKG.
NO.
NA
Block Diagram
COMPOSITE
VIDEO
NTSC/PAL
DECODER
HMP8112
Y BUS
CbCr BUS
H.261 VIDEO
CODEC
HMP8364
I/O BUS
MA BUS
I2C
BUS
FROM AUDIO
CODEC
DRAM
OPTIONAL
MD BUS
CV
BUS
EEPROM
UV
BUS
NTSC/PAL
ENCODER
HMP8156
COMPOSITE
VIDEO
I/O
BUS
I/O BUS
AUDIO LINK
PROCESSOR
HMP8201
SA BUS
SRAM
SD BUS
TELECOM BUS
PCI BUS
FIGURE 1. VIDEO CONFERENCING H.320 REFERENCE DESIGN WITH HARRIS CHIP SET
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
File Number
4348
HMP8320VCS
1.0 Introduction
2.0 Video Conferencing System Processes
The major component of the Video Conferencing Chip Set are:
2.1 Audio Link Processor (HMP8201)
1. NTSC/PAL Video Decoder (Harris P/N HMP8112)
The Harris Audio Link Processor (ALP) combines high
performance audio processing with a PCI bus interface to
support implementation of ITU H.320 Video Conferencing
using the Harris Video Conferencing Chip Set. The ALP
provides a complete solution for the audio layer of ITU
H.320. The audio processing includes full duplex
implementations of ITU G.711, G.722 and G.728 audio
compression. In addition, acoustic echo cancellation is
included to enable the use of a “hands free” speaker phone
type interface.
2. Video CODEC (Harris P/N HMP8364)
3. Audio Link Processor (Harris P/N HMP8201)
4. Optional NTSC/PAL Video Encoder (Harris P/N HMP8156)
The inputs to this system are the local analog audio, the
local composite video, and the remote H.221 via the Telecom Bus connected to an ISDN MODEM. The analog monophonic audio input is to the Audio CODEC from a line or
microphone source. The local video input is to the Video
Decoder from a local video camera.
In addition to audio processing the ALP provides a PCI
interface to manage data flows between the host and the
Harris Video Conferencing chip set. The PCI interface supports control and data flows between the host system and
the H.261 Video CODEC, the Audio CODEC, the Video
Decoder, and the ISDN MODEM. As shown in the block diagram (Figure 1), these data flows are routed to the various
ICs via an I2C Bus, an 8-bit general purpose IO Bus, a telecom interface supporting the MVIP or IOM2 standards, and
buses for compressed and uncompressed video. A top level
block diagram of the ALP is shown in Figure 2. For further
details see the Audio Link Processor data sheet (HMP8201).
The outputs are the remote audio out of the Audio CODEC
and the processed remote video for display. The processed
video may be passed to the HOST Memory or the Graphics
Card via the PCI Bus. A second option is to pass the processed video via an NTSC/PAL Video Encoder to a monitor
that accept composite analog video. A third method is possible but not recommended. This method is to pass the processed video to the local Graphics Card via the VMI Bus.
This third method is inferior to passing the processed video
over the PCI Bus.
The HOST processor is responsible for performing the following tasks:
2.2 Video CODEC (HMP8364)
1. Initializing the Video Conferencing System.
The Harris H.261 Video CODEC is a single-chip, high performance integrated circuit that simultaneously encodes and
decodes full-motion video at 30 frames per second and fullresolution CIF Video conforming to the ITU H.261 Video
Conferencing Standard. This device is designed for highly
integrated teleconferencing services and real-time multimedia applications.
2. Initializing the ISDN MODEM.
3. Performing the H.221 processing.
The following two sections discusses the data busses (data
paths) of the H.320 reference design and the processes carried out in the chip set.
DIGITAL
VIDEO BUS
CONTROL
AND STATUS
DIGITAL
VIDEO BUS
INTERFACE
I2C
BUS
INTERFACE
BUS INTERFACE COMPONENT
CLOCK
GENERATOR
TELECOM
TRANSCEIVER
INTERFACE
AUDIO CODEC
REFERENCE/CLOCK
TELECOMM
BUS
COMPRESSED
VIDEO
CONTROL AND STATUS
COMPRESSED ANNEX D
STREAM, DIGITAL AUDIO
COMPRESSED
VIDEO I/O BUS
INTERFACE
PCI
BUS
INTERFACE
I/O
BUS
INTERFACE
TIMER
HOST
PROCESSOR
INTERFACE
PCI BUS
HOST AND GUI DATA
FIGURE 2. ALP TOP LEVEL BLOCK DIAGRAM
2
EXTERNAL
SRAM
DUAL
PROGRAMMABLE
DIGITAL
SIGNAL
PROCESSOR
CORES
HMP8320VCS
3.0 Video Conferencing System Data
Busses
The HMP8364 tightly couples to the HMP8112 Video
Decoder or a digital video source which produces 8-bit or
16-bit Standard 4:2:2 BT.601 Video from either PAL or
NTSC sources. It properly scales the incoming video to CIF
or QCIF format with the 4:2:0 pixel siting defined in ITU
H.261. Inter-picture prediction is augmented by full motion
compensation and spatial filtering. Entropy coding is
performed on the compressed signal. Annex D is also
supported. Video is output in various modes for design
flexibility.
3.1 SRAM Interface (SA and SD Bus)
This bus is a standard parallel bus for passing data between
the SRAM and the Audio Link Processor (ALP). The bus has
a 16-bit bidirectional data bus (SD), 17-bit address bus (SA)
with read (SRD) and write (SWR) signals.
Assumptions: 40MHz bus cycle, 40pF load, 3.3V with 5V
tolerance.
2.3 Video Decoder (HMP8112A)
3.2 IO Bus (IOB)
The HMP8112 is a high quality, digital video, color decoder
with internal A/D converters. The A/D function includes a 3:1
analog input multiplexer, Sync Tip AGC, Black clamping and
two 8-bit A/D Converters. The high quality A/D converters
minimize pixel jitter and crosstalk.
The Audio Link Processor (ALP) is the master of this parallel
bus. This bus provides a means of passing data between the
Audio Link Processor, the Audio CODEC, and the Video
CODEC or any other parallel bus device. The interface has
an 8-bit bi-directional data bus (IOD[7:0]) and an 8-bit
address bus (IOA[7:0]) with read (IORD) and write (IOWR)
signals. Slaves devices (the video and audio CODEC)
request servicing by means of the signals ADRQ, CDRQ
and PDRQ.
The decoder function is compatible with NTSC M, PAL B, D,
G, H, I, M, N and special combination PAL N video standards. Both composite (CVBS) and S-Video (Y/C) input formats are supported. A two line comb filter plus a user
selectable Chrominance trap filter provide high quality Y/C
separation. Various adjustments are available to optimize
the image such as Brightness, Contrast, Saturation, Hue and
Sharpness controls. Video synchronization is achieved with
a 4xfSC chroma burst lock PLL for color demodulation and
line lock PLL for correct pixel alignment. A chrominance subsampling 4:2:2 scheme is provided to reduce chrominance
bandwidth.
3.3 Compressed Video (CV) Bus
The CV Bus transfers local compressed video (CVL) from
the Video Codec to the ALP and remote compressed video
(CVR) from the ALP to the Video CODEC.
Compressed Video Bus is a synchronous serial bus. Serial
data is clocked out of the ALP on the rising edge of the compression video clock (CVCLK) and into the ALP on the falling
edge of this clock. The serial data into the ALP is the local
compressed video (CVL) and the serial data out of the ALP
is the remote compressed video (CVR). The ALP also produces two data valid signals, the compressed video gate
local (CVGTL) and the compressed video gate remote
(CVGTR). When the ALP asserts CVGTL signal, latches in
the Video CODEC are enabled to clock out the CVL serial
data on the falling edge of the CVCLK signal. Correspondingly, when the ALP asserts CVGTR signal, latches in the
Video CODEC are enabled to clock in the CVR serial data
on the rising edge of the CVCLK signal.
The HMP8112 is ideally suited as the analog video interface
to VCRs and cameras in any multimedia or video system.
The high quality Y/C separation, user flexibility and integrated phase locked loops are ideal for use with today’s powerful compression processors. The HMP8112 operates from
a single 5V supply and is TTL/CMOS compatible.
2.4 NTSC/PAL Video Encoder
The HMP8156 NTSC and PAL encoder is designed for use
in systems requiring the generation of high quality NTSC
and PAL video from digital image data.
YCbCr or RGB digital video data drive the P0-P23 inputs.
Overlay inputs are processed and the data is 2x upsampled. The Y data is optionally lowpass filtered to 5MHz and
drives the Y analog output. Cb and Cr are each lowpass filtered to 1.3MHz, quadrature modulated, and summed. The
result drives the C analog output. The digital Y and C data
are also added together and drive the two composite analog outputs.
3.4 Uncompressed Video (UV) Bus
The UV Bus transfers uncompressed video data (UV[7:0])
from the Video CODEC to the ALP. The alternate fields can
be local and remote video or local only or remote only.
The UV Bus is a synchronous parallel data bus, using the
on board system clock (27MHz) as the synchronizing clock.
The 8-bit parallel uncompressed video data (UV[7:0]) is
clocked out of the Video CODEC on the rising edge of
SYSCLK. Data clocked out of the Video CODEC on one
rising edge of SYSCLK is clock into the ALP on the next
rising edge of SYSCLK. Vertical Sync signal (VSYNC)
should pulse high at least one SYSCLK prior to the first
data byte of a new video field and at least one SYSCLK
following the last byte of the previous video field. An active
high on the Uncompressed Video Ready signal (UVRDY)
indicates that data present on UV[7:0] is valid. The sense
The YCbCr data may also be converted to RGB data to drive
the DACs, allowing support for the European SCART connector.
The DACs can drive doubly-terminated (37.5Ω) lines, and
run at a 2x oversampling rate to simplify the analog output
filter requirements.
3
HMP8320VCS
3.7 Y Bus and CbCr Bus (Video CODEC Local Video In
Interface)
of the Video Field signal (FIELD) indicates whether an even
or odd video field is currently being transferred (0 = even,
1 = odd). The state of this input is held constant through
out the duration of the field transfer.
This bus provides a means of passing local video (luma and
chroma data) from the NTSC/PAL Decoder to the Video
CODEC. The luma data is passed over an 8-bit Y Bus
(YIN[7:0]). The chroma data is also passed over an 8-bit
CbCr Bus (CbCr[7:0]), sometimes called the C Bus. The
data transfer is synchronous with the PIXCLK signal. The
luma data and the chroma data are clocked out of the
NTSC/PAL Decoder on one rising edge of PIXCLK and into
the Video CODEC on the next rising edge.
Note that all of the signal except SYSCLK are output of the
Video CODEC.
3.5 TELECOM Bus (MVIP or IOM-2 Interface)
This bus is a serial synchronous bus used for transferring
H.221 data between the ALP and the ISDN MODEM. This
interface is compatible with ISDN MODEMs using either
MVIP (Multi Vendor Integration Protocol) in the US or IOM-2
type interface in Europe and elsewhere.
Vertical sync (VSYNC) and horizontal sync (HSYNC) signals
are also inputs to the Video CODEC from the video decoder.
In systems using the MVIP interface the Serial Data Clock
(DCL) would be tied to the C2 output on the ISDN MODEM
which is a 2.048MHz clock synchronous to the bit rate. In
systems using the IOM-2 MODEM interface, the DCL signal
would be tied to the DCL output which is synchronous to
twice the bit rate and is programmable from 512kHz to
6176kHz. The serial Data Input (DI) is the serial data into the
ALP from ISDN MODEM and is synchronous to DCL. The
serial Data Output (DO) is the serial data from the ALP into
ISDN MODEM and is synchronous to DCL. Frame Sync. is
an 8kHz clock indicating the start of a frame. This output
also serves as the audio sample rate reference to the audio
CODEC. Data Output Enable is asserted active high during
an outgoing data transmission.
The DATAVLD is a data valid signal for each byte of video
data, YIN[7:0] and CBCR[7:0], transferred and the signal
ACTIVE is asserted for an entire video line of data.
3.6 I2C Interface
3.8 PCI Interface
The Inter-integrated Circuit Bus (I2C or IIC Bus) is a two wire
bidirectional serial bus providing communications between
the ALP (Bus Master) and three on-board devices (Bus
Slave Devices), the Audio Codec, the NTSC/PAL Decoder,
the ISDN Modem daughter board and a serial EEPROM.
The Peripheral Component Interconnect (PCI) Bus is a high
performance, 32-bit bus with multiplexed address and data
lines (see HMP8201 data sheet). The PCI Bus is the interconnect between the Harris Video Conferencing Chip Set
Design (the ALP), the GUI Card, and the Host Processor/Memory System. A copy of the full PCI Local Bus Specification may be obtained by contacting the office of the PCI
Special Interest Group (PCI SIG).
The FIELD input to the Video CODEC identifies the odd and
even fields (1 = even field, 0 = odd field) for CCIR input
video. This input changes state only during the vertical
blanking interval when there is no active lines.
Note that polarities required by the Video CODEC for the
signals VSYNC, HSYNC, DATAVLD, ACTIVE, and FIELD are
programmable.
For further information see the H.261 Video CODEC data
sheet (HMP8364).
The I2C Bus was developed and patented by Philips Semiconductor Corporation. A copy of the I2C Bus Specification
may be obtained by contacting the Philips Semiconductor
Corporation.
All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
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S E M I C O N D U C TO R
4
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