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1
TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
TPS2549-Q1 Automotive USB Charging Port Controller and Power Switch With Cable
Compensation
1 Features
1
• AEC-Q100 Qualified With the Following Results:
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C5
• 4.5-V to 6.5-V Operating Range
• 47-mΩ (typ.) High-Side MOSFET
• 3.2-A Maximum Continuous Output Current
• ±5% CS Output for Cable Compensation
• CDP Mode per USB Battery Charging
Specification 1.2
• Automatic DCP Modes Selection:
– Shorted Mode per BC1.2 and YD/T 1591-2009
– 2.7-V Divider 3 Mode
– 1.2-V Mode
• D+ and D– Client Mode for System Update
• D+ and D– Short-to-V
BUS
Protection
• D+ and D– ±8-kV Contact and ±15-kV Air
Discharge ESD Rating (IEC 61000-4-2)
• –40°C to 125°C Junction Operating Temperature
• 16-Pin QFN (3-mm × 3-mm) Package
2 Applications
• Automotive USB Ports (Host and Hubs)
• Automotive Infotainment System
3 Description
The TPS2549-Q1 device is a USB charging port controller and power switch with a current-sense output that is able to control an upstream supply. This allows it to maintain 5 V at the USB port even with heavy
PART NUMBER
Device Information
PACKAGE BODY SIZE (NOM)
TPS2549-Q1 WQFN (16) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
Simplified Schematic
V
(BAT)
4.5 V to 6.5 V 0.1 µF
R
(CABLE1)
Voltage
Regulator
5 V
LMR14030
LM53603-Q1
LM25117-Q1
TPS54340-Q1
FB
GND
R
(FA)
R
(FB)
R
(G)
C
(COMP)
R
(FAULT)
R
(STATUS)
FAULT
STATUS
Power S witch EN
Mode Select I/O heavy charging currents. This is important in systems with long USB cables where significant voltage drops can occur while fast-charging portable devices.
The TP2549-Q1 47-mΩ power switch has two selectable, programmable current limits that support port power management by providing a lower current limit that can be used when adjacent ports are experiencing heavy loads. This is important in systems with multiple ports and an upstream supply unable to provide full current to all ports simultaneously.
The DCP_Auto scheme detects and selects the proper D+ and D– settings to communicate with the attached device, so that it can fast-charge at full current. The integrated CDP detection enables up to
1.5-A fast charging of most portable devices with simultaneous data communication.
The unique client-mode feature allows software updates to client devices, but avoids power conflicts by turning off the internal power switch while keeping the data line connection.
Additionally, the TPS2549-Q1 device integrates shortto-V
BUS protection for D+ and D– to prevent damage when D+ and/or D– unexpectedly short to V
BUS
. To save space in the application, the TPS2549-Q1 device also integrates ESD protection to pass
IEC61000-4-2 without external circuitry on D+ and
D–.
IN
OUT
TPS2549-Q1
FAULT
STATUS
DM_IN
DP_IN
GND
CS
EN
CTL1
CTL2
CTL3
ILIM_LO
ILIM_HI
DM_OUT
DP_OUT
C
(OUT)
To Host
Controller
R_HI
R
(CABLE2)
R_LO
Copyright © 2016, Texas Instruments Incorporated
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
www.ti.com
1
Features ..................................................................
2
Applications ...........................................................
3
Description .............................................................
4
Revision History.....................................................
5
Pin Configuration and Functions .........................
6
Specifications.........................................................
6.1
Absolute Maximum Ratings ......................................
6.2
ESD Ratings..............................................................
6.3
Recommended Operating Conditions .......................
6.4
Thermal Information ..................................................
6.5
Electrical Characteristics...........................................
6.6
Switching Characteristics ..........................................
6.7
Typical Characteristics ..............................................
7
Parameter Measurement Information ................
8
Detailed Description ............................................
8.1
Overview .................................................................
8.2
Functional Block Diagram .......................................
Table of Contents
8.3
Feature Description.................................................
8.4
Device Functional Modes........................................
9
Application and Implementation ........................
9.1
Application Information............................................
9.2
Typical Application .................................................
10
Power Supply Recommendations .....................
11
Layout...................................................................
11.1
Layout Guidelines .................................................
11.2
Layout Example ....................................................
12
Device and Documentation Support .................
12.1
Documentation Support ........................................
12.2
Receiving Notification of Documentation Updates
12.3
Community Resources..........................................
12.4
Trademarks ...........................................................
12.5
Electrostatic Discharge Caution ............................
12.6
Glossary ................................................................
13 Mechanical, Packaging, and Orderable
Information ...........................................................
4 Revision History
Changes from Revision A (October 2015) to Revision B Page
• Changed maximum outlput current to 3.2 A...........................................................................................................................
• Changed maximum output current in Recommended Operating Conditions .........................................................................
• Changed minimum current-set resistance in Recommended Operating Conditions ............................................................
• Added a row to the CURRENT LIMIT section in Electrical Characteristics ..........................................................................
• Added a row to the CABLE COMPENSATION section of Electircal Characteristics .............................................................
• Added Receiving Notification of Documentation Updates section .......................................................................................
Changes from Original (October 2015) to Revision A Page
• Device status changed from PRE_PROD to PRODUCTION.................................................................................................
2
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Copyright © 2015–2016, Texas Instruments Incorporated
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5 Pin Configuration and Functions
RTE Package
16-Pin WQFN
Top View
TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
IN 1
DM_OUT 2
DP_OUT 3
CS 4
Thermal
Pad
12 OUT
11 DM_IN
10 DP_IN
9 STATUS
Pin Functions
PIN
TYPE
(1)
DESCRIPTION
NAME NO.
CS 4 O
Provide sink current proportional to output current. For cable compensation, connect to the feedback divider of the up-stream voltage regulator.
CTL1
CTL2
CTL3
DM_IN
DM_OUT
DP_IN
DP_OUT
EN
FAULT
GND
ILIM_HI
ILIM_LO
IN
OUT
STATUS
Thermal pad
6
7
8
11
2
10
3
5
13
14
16
15
1
12
9
—
I
I
I
I/O
I/O
I/O
I/O
I
O
—
I
I
PWR
PWR
O
—
Logic-level control inputs for controlling the charging mode and the signal switches; (see
). These pins tie directly to IN or GND without a pullup or pulldown resistor.
D– data line to downstream connector
D– data line to upstream USB host controller
D+ data line to downstream connector
D+ data line to upstream USB host controller
Logic-level control input for turning the power switch and the signal switches on/off. When
EN is low, the device is disabled, the signal and power switches are OFF.
Active-low open-drain output, asserted during overtemperature, overcurrent, and DP_IN and
DM_IN overvoltage conditions. See
Ground connection; should be connected externally to the thermal pad.
Connect external resistor to ground to set the high current-limit threshold.
Connect external resistor to ground to set the low current-limit threshold and the loaddetection current threshold.
Input supply voltage; connect a 0.1 µF or greater ceramic capacitor from IN to GND as close to the IC as possible.
Power-switch output
Active-low open-drain output, asserted when the load exceeds the load-detection threshold
Thermal pad on bottom of package. The thermal pad is internally connected to GND and is used to heat-sink the device to the circuit board. Connect the thermal pad to the GND plane.
(1) I = Input, O = Output, I/O = Input and output, PWR = Power
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links:
TPS2549-Q1
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TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
6 Specifications
www.ti.com
6.1 Absolute Maximum Ratings
Voltages are with respect to GND unless otherwise noted
(1)
MIN MAX UNIT
Voltage range
CS, CTL1, CTL2, CTL3, EN, FAULT, ILIM_HI,
ILIM_LO, IN, OUT, STATUS
DM_IN, DM_OUT, DP_IN, DP_OUT
IN to OUT
–0.3
–0.3
–7
7
5.7
7
V
V
V
I
(SRC)
Continuous current in SDP,
CDP or client mode
Continuous current in BC1.2
DCP mode
Continuous output current
Continuous output source current
DP_IN to DP_OUT or DM_IN to DM_OUT
DP_IN to DM_IN
OUT
ILIM_HI, ILIM_LO
–100
–35
100
35
Internally limited
Internally limited mA mA
A
A
I
(SNK)
T
J
T stg
Continuous output sink current
Operating junction temperature
Storage temperature
FAULT, STATUS
CS
25
Internally limited
–40 Internally limited
–65 150 mA
A
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
Charged-device model (CDM), per AEC Q100-011
IEC
(4)
IEC61000-4-2 contact discharge, DP_IN and DM_IN
IEC61000-4-2 air discharge, DP_IN and DM_IN
VALUE
±2,000
(2)
±750
(3)
±8,000
±15,000
UNIT
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) The passing level per AEC-Q100 Classification H2.
(3) The passing level per AEC-Q100 Classification C5
(4) Surges per IEC61000-4-2, 1999 applied between DP_IN/DM_IN and output ground of the TPS2549Q1EVM-729 ( SLVUAK6 ) evaluation module.
6.3 Recommended Operating Conditions
Voltages are with respect to GND unless otherwise noted.
V
(IN)
Supply voltage
Input voltage
IN
CTL1, CTL2, CTL3, EN
DM_IN, DM_OUT, DP_IN, DP_OUT
OUT (–40°C ≤ T
A
≤ 85°C)
DP_IN to DP_OUT or DM_IN to DM_OUT
MIN
4.5
0
0
–30
NOM MAX UNIT
6.5
V
6.5
3.6
3.2
V
V
A
30 mA
I
(OUT)
R
(ILIM_xx)
T
J
Output continuous current
Continuous current in SDP, CDP or client mode
Continuous current in BC1.2 DCP mode
Continuous output sink current
Current limit-set resistors
Operating junction temperature
DP_IN to DM_IN
FAULT, STATUS
–15
14.7
–40
15
10
1000
125 mA mA k Ω
°C
4
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Copyright © 2015–2016, Texas Instruments Incorporated
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TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
6.4 Thermal Information
R
θJA
R
θJC(top)
R
θJB
ψ
JT
ψ
JB
R
θJC(bot)
THERMAL METRIC
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
(1)
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
TPS2549-Q1
RTE (WQFN)
16 PINS
44.9
53.3
17.6
1
17.6
4.1
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953 .
6.5 Electrical Characteristics
Unless otherwise noted, –40°C
R
(STATUS)
= 10 kΩ, R
(ILIM_HI)
≤ T
J
≤ 125°C and 4.5 V ≤ V
= 19.1 kΩ, R
(ILIM_LO)
(IN)
≤ 6.5 V, V
(EN)
= V
(IN)
, V
(CTL1)
= V
(CTL2)
= V
(CTL3)
= V
(IN)
. R
(FAULT)
= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND.
=
MIN TYP MAX UNIT PARAMETER
r
OUT – POWER SWITCH
DS(on)
On-resistance
(1)
TEST CONDITIONS
I lkg(OUT)
OUT - DISCHARGE
Reverse leakage current on
OUT pin
R
(DCHG)
OUT discharge resistance
EN, CTL1, CTL2, CTL3 INPUTS
T
J
= 25°C
–40°C ≤ T
J
≤ 85°C
–40°C ≤T
J
≤ 125°C
V
OUT
= 6.5 V, V measure I
(OUT)
IN
= V
EN
= 0 V, –40°C
≤ T
J
≤ 85°C,
Input pin rising logic threshold voltage
Input pin falling logic threshold voltage
Hysteresis
(2)
Input current Pin voltage = 0 V or 6.5 V
CURRENT LIMIT
I
OS
OUT short-circuit current limit
R
(ILIM_LO)
= 210 kΩ
R
(ILIM_LO)
= 80.6 kΩ
R
(ILIM_LO)
= 23.2 kΩ
R
(ILIM_HI)
= 20 kΩ
R
(ILIM_HI)
= 19.1 kΩ
R
(ILIM_HI)
= 15.4 kΩ
R
(ILIM_HI)
= 14.7 kΩ
R
(ILIM_HI) shorted to GND
SUPPLY CURRENT
I
(IN_OFF)
I
(IN_ON)
Disabled IN supply current V
(EN)
= 0 V, V
(OUT)
= 0 V, –40°C ≤ T
J
≤ 85°C
Enabled IN supply current V
(CTL)1
= V
(CTL2)
= V
(CTL3)
= V
(IN)
V
(CTL1)
= V
(CTL2)
= 0 V, V
(CTL3)
= V
(IN)
V
(CTL2)
= V
(IN)
, V
(CTL1)
= V
(CTL3)
= 0 V
V
(CTL1)
= V
(IN)
, V
(CTL2)
= V
(CTL3)
= 0 V
400
1
0.85
–1
205
600
2145
2500
2620
3255
3411
5500
47
47
47
500
1.35
1.15
200
255
660
2300
2670
2800
3470
3637
7000
0.1
220
226
150
115
57 mΩ
72
80
2 µA
630
2
1.65
Ω
V
V mV
1 µA
305 mA
720
2455
2840
2975
3685
3862
8000
5 µA
300 µA
300
220
190
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account separately.
(2) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.
Copyright © 2015–2016, Texas Instruments Incorporated
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Electrical Characteristics (continued)
Unless otherwise noted, –40°C
R
(STATUS)
= 10 kΩ, R
(ILIM_HI)
≤ T
J
≤ 125°C and 4.5 V ≤ V
= 19.1 kΩ, R voltages are with respect to GND.
(ILIM_LO)
(IN)
≤ 6.5 V, V
(EN)
= V
(IN)
, V
(CTL1)
= V
(CTL2)
= V
(CTL3)
= V
(IN)
. R
(FAULT)
= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All
=
MIN TYP MAX UNIT PARAMETER
UNDERVOLTAGE LOCKOUT, IN
V
(UVLO)
IN rising UVLO threshold voltage
Hysteresis
(3)
FAULT
Output low voltage
Off-state leakage
T
J
= 25°C
TEST CONDITIONS
I
(FAULT)
= 1 mA
V
(FAULT)
= 6.5 V
STATUS
Output low voltage
Off-state leakage
THERMAL SHUTDOWN
T
(OTSD2)
Thermal shutdown threshold
T
(OTSD1)
Thermal shutdown threshold in current-limit
Hysteresis
(3)
LOAD DETECT (V
CTL1
= V
CTL2
= V
CTL3
= V
IN
)
I
(LD)
I
OUT load detection threshold
Hysteresis
(3)
I
(STATUS)
V
R
(STATUS)
(ILIM_LO)
= 1 mA
= 6.5 V
= 80.6 k Ω, rising load current
DP_IN AND DM_IN SHORT-TO-V
BUS
PROTECTION
V
(OV)
Overvoltage protection trip threshold
Hysteresis
(3)
DP_IN and DM_IN rising
R
(DCHG_Data)
Discharge resistance after
OVP
V
(DP_IN)
= V
(DM_IN)
= 5 V
I
CABLE COMPENSATION
(CS)
Sink current Load = 3.2 A, 2.5 V ≤ V
(CS)
≤ 6.5 V
Load = 3 A, 2.5 V
≤ V
(CS)
≤ 6.5 V
Load = 2.4 A, 2.5 V ≤ V
(CS)
≤ 6.5 V
Load = 2.1 A, 2.5 V ≤ V
(CS)
≤ 6.5 V
Load = 1 A, 2.5 V ≤ V
(CS)
≤ 6.5 V
3.9
155
135
630
3.7
160
228
214
171
149
70
4.1
100
20
700
50
3.9
100
210
240
225
180
158
75
4.3
4.15
V mV
100 mV
2 µA
100 mV
2 µA
°C
°C
°C
770 mA mA
V mV
240 k Ω
252 µA
236
189
166
80
(3) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.
6
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TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
Electrical Characteristics (continued)
Unless otherwise noted, –40°C
R
(STATUS)
= 10 kΩ, R
(ILIM_HI)
≤ T
J
≤ 125°C and 4.5 V ≤ V
= 19.1 kΩ, R voltages are with respect to GND.
(ILIM_LO)
(IN)
≤ 6.5 V, V
(EN)
= V
(IN)
, V
(CTL1)
= V
(CTL2)
= V
(CTL3)
= V
(IN)
. R
(FAULT)
= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All
=
MIN TYP MAX UNIT PARAMETER
HIGH-BANDWIDTH ANALOG SWITCH
R
(HS_ON)
|ΔR
(HS_ON)
|
DP and DM switch onresistance
Switch resistance mismatch between DP and DM channels
C
C
(IO_OFF)
(IO_ON)
DP/DM switch off-state capacitance
(4)
DP/DM switch on-state capacitance
(4)
Off-state isolation
(4)
On-state cross-channel isolation
(4)
I lkg(OFF)
BW
Off-state leakage current,
DP_OUT and DM_OUT
Bandwidth (–3 dB)
(4)
CHARGING DOWNSTREAM PORT DETECT
TEST CONDITIONS
V
(DP_OUT)
30 mA
= V
(DM_OUT)
= 0 V, I
(DP_IN)
= I
(DM_IN)
=
V
(DP_OUT)
–15 mA
= V
(DM_OUT)
= 2.4 V, I
(DP_IN)
= I
(DM_IN)
=
V
(DP_OUT)
30 mA
= V
(DM_OUT)
= 0 V, I
(DP_IN)
= I
(DM_IN)
=
V
(DP_OUT)
–15 mA
= V
(DM_OUT)
= 2.4 V, I
(DP_IN)
= I
(DM_IN)
=
V
EN
V
V
= V
R
EN
(L)
= 0 V, V
(DP_IN)
Vac = 0.03 V
(DP_IN)
= V
(DM_OUT)
= 50 Ω
(DM_IN)
= 0 V, V
(DP_IN)
= 0 V
= 0.3 V,
Vac = 0.03 V
PP
, f = 1 MHz
V
EN
= 0 V, f = 250 MHz f = 250 MHz
PP
= V
= V
(DM_IN)
, f = 1 MHz
(DM_IN)
= 0.3 V,
= 3.6 V, V
(DP_OUT)
V
V
(DM_SRC)
(DAT_REF)
R
(DPM_SHORT)
DM_IN CDP output voltage V
(DP_IN)
= 0.6 V, –250 µA < I
(DM_IN)
< 0 µA
DP_IN rising lower window threshold for V
DM_SRC activation
Hysteresis
(4)
V
(LGC_SRC)
DP_IN rising upper window threshold for VDM_SRC de-activation
Hysteresis
(4)
V
(LGC_SRC_HYS)
I
(DP_SINK)
BC1.2 DCP MODE
DP_IN sink current
DP_IN and DM_IN shorting resistance
V
(DP_IN)
= 0.6 V
DIVIDER3 MODE
V
(DP_DIV3)
V
(DM_DIV3)
R
(DP_DIV3)
R
(DM_DIV3)
1.2-V MODE
V
(DP_1.2V)
V
(DM_1.2V)
R
(DP_1.2V)
R
(DM_1.2V)
DP_IN output voltage
DM_IN output voltage
DP_IN output impedance
DM_IN output impedance I
(DM_IN)
= –5 µA
DP_IN output voltage
DM_IN output voltage
DP_IN output impedance
I
(DP_IN)
= –5 µA
I
(DP_IN)
= –5 µA
DM_IN output impedance I
(DM_IN
= –5 µA
0.5
0.36
0.8
40
2.57
2.57
24
24
1.12
1.12
84
84
2
2.9
0.05
0.05
6.7
10
27
23
0.1
925
0.6
50
100
75
125
1.2
1.2
100
100
2.7
2.7
30
30
4
6
0.15
0.15
200
Ω
Ω pF pF dB dB
1.5
µA
0.7
0.4
0.88
MHz
V
V mV
V mV
100 µA
Ω
2.84
2.84
V
V
36 kΩ
36 kΩ
1.26
1.26
V
V
126 kΩ
126
(4) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.
Copyright © 2015–2016, Texas Instruments Incorporated
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TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
www.ti.com
6.6 Switching Characteristics
Unless otherwise noted –40°C
R(
STATUS)
= 10 kΩ, R
(ILIM_HI)
≤ T
J
≤ 125°C and 4.5 V ≤ V
(IN)
= 19.1 kΩ, R
(ILIM_LO)
≤ 6.5 V, V
(EN)
= V
(IN)
, V
(CTL1)
= V
(CTL2)
= V
(CTL3)
= V
(IN)
. R
(FAULT)
=
= 80.6 kΩ. Positive current is into pins. Typical value is at 25°C. All voltages are with respect to GND.
t t t t t t t t t t r t f t on t off
(DCHG_L)
(DCHG_S)
(IOS) t
(OC_OUT_FAULT) pd
(SK)
(LD_SET)
(LD_RESET)
(OV_D)
(OV_D_FAULT)
PARAMETER
OUT voltage rise time
OUT voltage fall time
OUT voltage turnon time
TEST CONDITIONS
V
(IN)
= 5 V, C
(L)
= 1 µF, R
and
)
(L)
= 100 Ω (see
V
(IN)
= 5 V, C
(L)
= 1 µF, R
and
(L)
= 100 Ω (see
OUT voltage turnoff time
Long OUT discharge hold time (SDP, CDP, or client mode to DCP_Auto)
Short OUT discharge hold time (DCP_Auto to SDP,
CDP, or client mode)
Time V
Time V
(OUT)
(OUT)
< 0.7 V (see
< 0.7 V (see
)
)
OUT short-circuit response time
(1)
V
(IN)
= 5 V, R
(SHORT)
= 50 mΩ (see
OUT FAULT deglitch time Bidirectional deglitch applicable to current limit condition only (no deglitch assertion for OTSD)
V
(IN)
= 5 V Analog switch propagation delay
(1)
Analog switch skew between opposite transitions of the same port
(t
PHL
– t
PLH
)
(1)
Load-detect set time
V
(IN)
= 5 V
Load-detect reset time
DP_IN and DM_IN overvoltage protection response time
DP_IN and DM_IN FAULT degltich time
V
(IN)
= 5 V (See
V
(IN)
= 5 V (See
V
(OUT)
= 5 V (See
V
(OUT)
= 5 V (See
MIN
0.7
0.2
1.1
186
5.5
120
1.8
11
TYP
1.14
0.35
4.15
1.8
2
320
2
8
0.14
0.02
210
3
2
16
MAX UNIT
2 ms
0.6
6 ms ms
3
2.9
ms s
450
11.5
280
4.2
23 ms
µs ms ns ns ms s
µs ms
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.
6.7 Typical Characteristics
70
65
60
55
50
45
40
35
30
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D001
V
IN
= 5 V
Figure 1. Power Switch On-Resistance vs Temperature
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D002
V
IN
= 5 V
Figure 2. Reverse Leakage Current vs Temperature
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Typical Characteristics (continued)
550
540
V
(IN)
= 4.5 V
V
(IN)
= 5 V
V
(IN)
= 6.5 V
530
520
510
500
490
480
470
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D003
A
8
6
4
2
0
14
Figure 3. OUT Discharge Resistance vs Temperature
12
V
(IN)
= 4.5 V
V
(IN)
= 5 V
V
(IN)
= 6.5 V
10
-2
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D005
CTL1 = 1 CTL2 = 1 CTL3 = 1
Figure 5. Disabled IN Supply Current vs Temperature
290
270
V
(IN)
= 4.5 V
V
(IN)
= 5 V
V
(IN)
= 6.5 V
250
230
210
190
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D007
CTL1 = 0 CTL2 = 0 CTL3 = 1
Figure 7. Enabled IN Supply Current – DCP_Auto (001) vs
Temperature
TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
240
220
200
4000
3500
3000
2500
2000
1500
1000
500
R
(ILIM_LO)
R
(ILIM_LO)
= 210 k
:
= 80.6 k
:
R
(ILIM_HI)
R
(ILIM_HI)
= 20 k
:
= 19.1 k :
R
(ILIM_HI)
= 15.4 k :
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D004
V
IN
= 5 V
Figure 4. OUT Short-Circuit Current Limit vs Temperature
280
260
V
(IN)
= 4.5 V
V
(IN)
= 5 V
V
(IN)
= 6.5 V
180
160
140
180
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D006
CTL1 = 1 CTL2 = 1 CTL3 = 1
220
Figure 6. Enabled IN Supply Current – CDP (111) vs
Temperature
200
V
(IN)
= 4.5 V
V
(IN)
= 5 V
V
(IN)
= 6.5 V
120
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D008
CTL1 = 0 CTL2 = 1 CTL3 = 0
Figure 8. Enabled IN Supply Current – SDP (010) vs
Temperature
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Typical Characteristics (continued)
180
160
140
120
100
V
(IN)
= 4.5 V
V
(IN)
= 5 V
V
(IN)
= 6.5 V
80
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D009
CTL1 = 1 CTL2 = 0 CTL3 = 0
Figure 9. Enabled IN Supply Current – Client Mode (100) vs
Temperature
4.2
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720
710
700
690
680
670
660
650
I
(LD)
, OUT Rising Load-Detect Threshold
I
OS
, OUT Short-Circuit Current
640
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D010
R
(ILIM_LO)
= 80.6 kΩ
Figure 10. I
OUT
Rising Load-Detect Threshold and OUT
Short-Circuit Current Limit vs Temperature
4.2
4.1
4.1
4 4
3.9
3.8
3.7
3.6
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D011
V
IN
= 5 V
Figure 11. DP_IN Overvoltage Protection Threshold vs
Temperature
250
3.9
3.8
3.7
3.6
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D012
V
IN
= 5 V
Figure 12. DM_IN Overvoltage Protection Threshold vs
Temperature
250
200
150
100
50
I
(OUT)
= 1 A
I
(OUT)
= 2.1 A
I
(OUT)
= 2.4 A
I
(OUT)
= 3 A
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D013
V
IN
= 5 V V
CS
= 2. 5 V
Figure 13. I
CS vs Temperature
200
150
100
50
0
2.5
3 3.5
I
(OUT
) = 1 A
I
(OUT)
= 2.1 A
4 4.5
CS Voltage (V)
5
I
(OUT)
= 2.4 A
I
(OUT)
= 3 A
5.5
6 6.5
D014
V
IN
= 6.5 V
Figure 14. I
CS vs V
CS
Voltage
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Typical Characteristics (continued)
TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
Figure 15. Data Transmission Characteristics vs Frequency
Figure 16. Off-State Data-Switch Isolation vs Frequency
Figure 17. On-State Cross-Channel Isolation vs Frequency
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Typical Characteristics (continued)
Forcing a page break between ImageMatrices
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Figure 18. Eye Diagram Using USB Compliance Test
Pattern, Bypassing the TPS2549-Q1 Data Switch
V
(EN)
5 V/div
Figure 19. Eye Diagram Using USB Compliance Test
Pattern, Through the TPS2549-Q1 Data Switch
V
(EN)
5 V/div
V
(OUT)
2.
5 V/div
I
(IN)
0.
5 A/div
R
(LOAD)
= 5 Ω C
(LOAD)
= 150 µF
Figure 20. Turnon Response
t = 1 ms/div
V
(EN)
5 V/div
V
( FAULT )
5 V/div
I
(IN)
R
(ILIM_HI)
= 80.6 kΩ t = 2 ms/div
Figure 22. Enable Into Short
R
(LOAD)
= 5 Ω C
(LOAD)
= 150 µF
V
(OUT)
I
(IN)
Figure 21. Turnoff Response
t = 1 ms/div
V
(EN)
5 V/div
V
( FAULT )
5 V/div
I
(IN)
1 A/div
R
(ILIM_HI)
= 19.1 kΩ t = 4 ms/div
Figure 23. Enable Into Short – Thermal Cycling
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Typical Characteristics (continued)
V
( FAULT )
5 V/div
V
(OUT)
TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
V
(OUT)
I
(IN)
2 A/div
R
(ILIM_HI)
= 19.1 kΩ t = 4 ms/div
Figure 24. Short-Circuit to Full-Load Recovery
I
(OUT)
10 A/div
R
(SHORT)
= 50 mΩ t = 1 µs/div
Figure 25. Hot-Short Response Time
V
(OUT)
V
(EN)
V
( STATUS )
5 V/div
I
(OUT)
2 A/div
R
(ILIM_HI)
= 19.1 kΩ R
(SHORT)
= 50 mΩ
Figure 26. Hot Short
V
( STATUS )
5 V/div
V
(OUT)
I
(OUT)
0.5 A/div t = 1 ms/div
R
(ILIM_LO)
= 80.6 kΩ t = 100 ms/div
Figure 27. Load-Detection Set Time
V
(DM_IN)
V
(DM_OUT)
I
(OUT)
0.5 A/div
R
(ILIM_LO)
= 80.6 kΩ t = 1 s/div
Figure 28. Load Detection Reset Time
R
(DM_OUT)
= 15 kΩ t = 1 µs/div
Figure 29. DM_IN Short to V
BUS
Response Time
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SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
Typical Characteristics (continued)
V
( FAULT )
5 V/div
www.ti.com
V
( FAULT )
5 V/div
V
(DM_IN)
2.5 V/div
V
(DM_IN)
V
(DM_OUT)
R
(DM_OUT)
= 15 kΩ t = 4 ms/div
Figure 30. DM_IN Short to V
BUS
V
(DM_OUT)
2.5 V/div
R
(DM_OUT)
= 15 kΩ t = 1 µs/div
Figure 31. DM_IN Short-to-V
BUS
Recovery
7 Parameter Measurement Information
OUT
R
(L)
C
(L)
Figure 32. OUT Rise-Fall Test Load Figure
5 V
V
(OU T) t
(DCHG)
0 V
Figure 34. OUT Discharge During Mode Change
90%
V
(OUT) t r t f
10%
Figure 33. Power-On and -Off Timing
V
(EN)
50% 50% t on t off
90%
V
(OUT)
10%
Figure 35. Enable Timing, Active-High Enable
I
OS
I
(OUT) t
(IO S)
Figure 36. Output Short-Circuit Parameters
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8 Detailed Description
TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
8.1 Overview
The TPS2549-Q1 device is a USB charging controller and power switch which integrates D+ and D– short to
V
BUS protection, cable compensation and IEC ESD protection, and is suitable for automotive USB charging and
USB port-protection applications.
The TPS2549-Q1 device integrates a current-limited, power-distribution switch using N-channel MOSFETs for applications where short circuits or heavy capacitive loads can be encountered. The device allows the user to program the current-limit threshold via an external resistor. The device enters constant-current mode when the load exceeds the current limit threshold.
The TPS2549-Q1 device also integrates CDP mode, defined in the BC1.2 specification, to enable up to 1.5-A fast charging of most of portable devices, meanwhile supporting data communication. In addition, the device integrates the DCP-auto feature to enable fast-charging of most portable devices including pads, tablets, and smart phones.
The TPS2549-Q1 device integrates a cable compensation (CS) feature to compensate the voltage drop in long cables and keep the remote USB port output voltage constant.
Additionally, the device integrates an IEC ESD cell to provide ESD protection up to ±8 kV (contact discharge) and ±15 kV (air discharge) per IEC 61000-4-2 on DP_IN and DM_IN, and integrates short-to-V protection on DP_IN and DM_IN to protect the upstream USB transceiver.
BUS overvoltage
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SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
8.2 Functional Block Diagram
IN
Current
Sense
CS
ILIM_HI
ILIM_LO
EN
Charge
Pump
Current
Limit
CS
UVLO
I
(CS)
= I
(OUT)
× 75 µA /A
Driver
Thermal
Sense
OTSD
OC
Disable + UVLO
+ Discharge
8-ms
Deglitch
16-ms
Deglitch
OVP2 OVP1
DM_OUT
DP_OUT
CTL1
CTL2
CTL3
Logic
Control
CDP
Detection
DCP
(Auto-Detection)
Discharge
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OUT
GND
FAULT
DM_IN
DP_IN
STATUS
8.3 Feature Description
8.3.1 FAULT Response
The device features an active-low, open-drain fault output. FAULT goes low when there is a fault condition. Fault detection includes overtemperature, overcurrent, or DP_IN, DM_IN overvoltage. Connect a 10-kΩ pullup resistor from FAULT to IN.
summarizes the conditions that generate a fault and actions taken by the device.
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Feature Description (continued)
EVENT
Overcurrent on V
(OUT)
Table 1. Fault Conditions
CONDITION
I
(OUT)
> I
OS
TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
Overvoltage on the data lines
Overtemperature
DP_IN or DM_IN > 3.9 V
T
J
> OTSD2 in non-current-limited or T
OTSD1 in current-limited mode.
J
>
ACTION
The device regulates switch current at I
OS until thermal cycling occurs. The fault indicator asserts and de-asserts with an 8-ms deglitch (The device does not assert FAULT on overcurrent in SDP1 and DCP1 modes).
The device immediately shuts off the USB data switches. The fault indicator asserts with a 16-ms deglitch, and de-asserts without deglitch.
The device immediately shuts off the internal power switch and the USB data switches.
The fault indicator asserts immediately when the junction temperature exceeds OTSD2 or
OTSD1 while in a current-limiting condition.
The device has a thermal hysteresis of 20°C.
8.3.2 Cable Compensation
When a load draws current through a long or thin wire, there is an IR drop that reduces the voltage delivered to the load. In the vehicle from the voltage regulator 5-V output to the VPD_IN (input voltage of portable device), the total resistance of power switch r
DS(on) and cable resistance causes an IR drop at the PD input.. So the charging current of most portable devices is less than their expected maximum charging current.
5.x
V
(DROP)
V
(OUT)
With Compensation
V
BUS
With Compensation
V
BUS
Without Compensation
0
0.5
I
(OUT)
(A)
1 1.5
2 2.5
3
Figure 37. Voltage Drop
TPS2549-Q1 device detects the load current and generates a proportional sink current that can be used to adjust output voltage of the upstream regulator to compensate the IR drop in the charging path. The gain G sink current proportional to load current is 75 µA/A.
(CS) of the
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SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
R
V
(OUT)
To Regulator OUT
IN
C
(COMP)
(FA)
R
(FB)
FB
R
(G)
To Regulator
Resistor Divider CS
R1 r
DS(on)
R2
OUT
To Load
R
(WIRE)
C
(OUT)
R
(LOAD)
V
BUS
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Figure 38. Cable Compensation Equivalent Circuit
8.3.2.1 Design Procedure
To start the procedure, the total resistance, including power switch r
DS(on) known.
and wire resistance R
(WIRE)
, must to be
1. Choose R
(G) following the voltage-regulator feedback resistor-divider design guideline.
2. Calculate R
(FA)
R
FA
=
(r
DS(on) according to
+
R
(WIRE)
) / G
(CS)
.
(1)
3. Calculate R
(FB)
R
(FB)
=
V
(FB) according to
V
(OUT)
/ R
(G)
-
R
(G)
-
R
(FA )
.
(2)
4. C
(COMP)
× C
(OUT) in parallel with R
(FA)
, then adjust C
(COMP) is needed to stablilize V
(OUT) when C
(OUT) is large. Start with C
(COMP)
≥ 3 × G to optimize the load transient of the voltage regulator output. V
(OUT)
(CS) stability should always be verified in the end application circuit.
8.3.3 D+ and D– Protection
D+ and D– protection consists of ESD and OVP (overvoltage protection). The DP_IN and DM_IN pins integrate an IEC ESD cell to provide ESD protection up to ±15 kV air discharge and ±8 kV contact discharge per IEC
61000-4-2 (See the
section for test conditions). Overvoltage protection (OVP) is provided for shortto-V
BUS conditions in the vehicle harness to prevent damaging the upstream USB transceiver. Short-to-GND protection for D+ and D– is provided by the upstream USB transceiver.
The ESD stress seen at DP_IN and DM_IN is impacted by many external factors like the parasitic resistance and inductance between ESD test points and the DP_IN and DM_IN pins. For air discharge, the temperature and humidity of the environment can cause some difference, so the IEC performance should always be verified in the end-application circuit.
8.3.4 Output and D+ or D– Discharge
To allow a charging port to renegotiate current with a portable device, the TPS2549-Q1 device uses the OUT discharge function. This function turns off the power switch while discharging OUT with a 500Ω resistance, then turns the power switches to back on reassert the OUT voltage.
For DP_IN and DM_IN, when OVP is triggered, the device turns on an internal discharge path with 210Ω resistance. On removal of OVP, this path can discharge the remnant charges to automatically turn on analog switch and turn off this discharge path, thus back into normal mode.
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TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
8.3.5 Port Power Management (PPM)
PPM is the intelligent and dynamic allocation of power. PPM is for systems that have multiple charging ports but cannot power them all simultaneously.
8.3.5.1 Benefits of PPM
The benefits of PPM include the following:
• Delivers better user experience
• Prevents overloading of system power supply
• Allows for dynamic power limits based on system state
• Allows every port to potentially be a high-power charging port
• Allows for smaller power-supply capacity because loading is controlled
8.3.5.2 PPM Details
All ports are allowed to broadcast high-current charging. The current-limit is based on ILIM_HI. The system monitors the STATUS pin to see when high-current loads are present. Once the allowed number of ports asserts
STATUS, the remaining ports are toggled to a non-charging port. The non-charging port current-limit is based on the ILIM_LO setting. The non-charging ports are automatically toggled back to charging ports when a charging port de-asserts STATUS.
STATUS asserts in a charging port when the load current is above ILIM_LO + 40 mA for 210 ms (typical).
STATUS de-asserts in a charging-port when the load current is below ILIM_LO – 10 mA for 3 seconds (typical).
8.3.5.3 Implementing PPM in a System With Two Charging Ports (CDP and SDP1)
shows the implementation of the two charging ports with data communication, each with a TPS2549-
Q1 device and configured in CDP mode. In this example, the 5-V power supply for the two charging ports is rated at less than 3.5 A. Both TPS2549-Q1 devices have ILIM_LO of 1 A and ILIM_HI of 2.4 A. In this implementation, the system can support only one of the two ports at 2.4-A charging current, whereas the other port is set to SDP1 mode and I
(LIMIT) corresponds to 1 A. In SDP1 mode, FAULT does not assert for overcurrent.
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5 V
EN1
FAULT1
100 kW
IN
EN
FAULT
STATUS
TPS2549 -Q1 Port 1
OUT
DM_IN
DP _IN
ILIM _LO
ILIM_HI
CTL1
CTL2
GND
CTL3
R_HI
USB Charging
Port 1
R_LO
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EN2
FAULT2
100 kW
IN
EN
FAULT
STATUS
TPS2549 -Q1 Port 2
OUT
DM_IN
DP_IN
ILIM _LO
ILIM_HI
CTL1
CTL2
GND
CTL3
R_HI
USB Charging
Port 2
R_LO
Copyright © 2016, Texas Instruments Incorporated
Figure 39. PPM With CDP and SDP1
8.3.5.4 Implementing PPM in a System With Two Charging Ports (DCP and DCP1)
shows the implementation of the two charging-only ports, each with a TPS2549-Q1 device and configured in DCP mode. In this example, the 5-V power supply for the two charging ports is rated at less than
3.5 A. Both TPS2549-Q1 devices have ILIM_LO of 1 A and ILIM_HI of 2.4 A. In this implementation, the system can support only one of the two ports at 2.4-A charging current, whereas the other port is set to DCP1 mode and
I
(LIMIT) corresponds to 1 A. In DCP1 mode, FAULT does not assert for overcurrent.
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5 V
EN1
FAULT1
100 kW
TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
IN
EN
FAULT
STATUS
TPS2549 -Q1 Port 1
OUT
DM_IN
DP _IN
ILIM _LO
ILIM_HI
CTL1
CTL2
GND
CTL3
R_HI
USB Charging
Port 1
R_LO
EN2
FAULT2
100 kW
IN
EN
FAULT
STATUS
TPS2549 -Q1 Port 2
OUT
DM_IN
DP_IN
ILIM _LO
ILIM_HI
CTL1
CTL2
GND
CTL3
R_HI
USB Charging
Port 2
R_LO
Copyright © 2016, Texas Instruments Incorporated
Figure 40. PPM With DCP and DCP1
8.3.6 CDP and SDP Auto Switch
The TPS2549-Q1 device is equipped with a CDP and SDP auto-switch feature to support some popular phones in the market. These popular phones do not comply with the BC1.2 specification because they fail to establish a data connection in CDP mode. These phones use primary detection (used to distinguish between an SDP and different types of charging ports) to only identify ports as SDP (data, no charge) or DCP (no data, charge). These phones do not recognize CDP (data, charge) ports. When connected to a CDP port, these phones classify the port as a DCP and only charge the battery. Because the charging ports are configured as CDP, users do not receive the expected data connection.
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D+
D–
V
BUS
V
BUS
Current
Primary Detection
Device never signals connection and enumerates.
Data connection is lost.
Figure 41. CDP and SDP Auto-Switch
To remedy this problem, the TPS2549-Q1 device employs a CDP and SDP auto-switch scheme to ensure these
BC1.2 noncompliant phones establish data connection using the following steps.
1. The TPS2549-Q1 device determines when a noncompliant phone has wrongly classified a CDP port as a
DCP port and has not made a data connection.
2. The TPS2549-Q1 device automatically completes an OUT (V
BUS
SDP.
) discharge and reconfigures the port as an
3. When reconfigured as an SDP, the phone detects a connection to an SDP and establishes a data connection.
4. The TPS2549-Q1 device then switches automatically back to a CDP without doing an OUT (V
BUS
) discharge.
5. The phone continues to operate as if connected to an SDP because OUT (V
BUS port is now ready in CDP if a new device is attached.
) was not interrupted. The
8.3.7 Overcurrent Protection
When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Two possible overload conditions can occur. In the first condition, the output is shorted before the device enables or before the application of V
(IN)
. The TPS2549-Q1 device senses the short and immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload occurs, high currents flow for 2 μs (typical) before the current-limit circuit reacts. The device operates in constant-current mode after the current-limit circuit has responded. Complete shutdown occurs only if the fault is presented long enough to activate overtemperature protection. The device remains off until the junction temperature cools to approximately 20°C and then restarts.
The device continues to cycle on and off until the overcurrent condition is removed.
8.3.8 Undervoltage Lockout
The undervoltage-lockout (UVLO) circuit disables the device until the input voltage reaches the UVLO turnon threshold. Built-in hysteresis prevents unwanted oscillations on the output due to input voltage drop from large current surges.
8.3.9 Thermal Sensing
Two independent thermal-sensing circuits protect the TPS2549-Q1 device if the temperature exceeds recommended operating conditions. These circuits monitor the operating temperature of the power-distribution switch and disable operation. The device operates in constant-current mode during an overcurrent condition, which increases the voltage drop across power switch. The power dissipation in the package is proportional to the voltage drop across the power switch, so the junction temperature rises during an overcurrent condition.
When the device is in a current-limiting condition, the first thermal sensor turns off the power switch when the die
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8.3.10 Current Limit Setting
The TPS2549-Q1 has two independent current-limit settings that are each programmed externally with a resistor.
The ILIM_HI setting is programmed with R programmed with R
(ILIM_LO)
(ILIM_HI) connected between ILIM_HI and GND. The ILIM_LO setting is connected between ILIM_LO and GND. Consult the device truth table (
see when each current limit is used. Both settings have the same relation between the current limit and the programming resistor.
R
(ILIM_LO) is optional and the ILIM_LO pin may be left unconnected if the following conditions are met:
• The TPS2549-Q1 device is configured as DCP(001) or CDP(111).
• Load detection is not used.
The following equation calculates the value of resistor for programming the typical current limit:
I
(OSnom)
(mA)
=
53 762 (V)
R
(ILIM _ xx)
1.0021
(3)
R
(ILIM_xx) corresponds to either R
(ILIM_HI) or R
(ILIM_LO)
, as appropriate.
Many applications require that the current limit meet specific tolerance limits. When designing to these tolerance limits, both the tolerance of the TPS2549-Q1 current limit and the tolerance of the external programming resistor must be taken into account. The following equations approximate the TPS2549-Q1 minimum and maximum current limits to within a few milliamperes and are appropriate for design purposes. The equations do not constitute part of TI’s published device specifications for purposes of TI’s product warranty. These equations assume an ideal—no variation—external programming resistor. To take resistor tolerance into account, first determine the minimum and maximum resistor values based on its tolerance specifications and use these values in the equations. Because of the inverse relation between the current limit and the programming resistor, use the maximum resistor value in the I
(OS_min) equation and the minimum resistor value in the I
(OS_max) equation.
50 409 (V)
I
(OS min)
(mA)
=
R
(ILIM _ xx)
0.9982
-
35
(4)
I
(OS max)
(mA)
=
57 813 (V)
R
(ILIM _ xx)
1.0107
+
41
(5)
4000
3500
3000
2500
2000
1500
1000
500
0
10 20
I
I
I
(OSmin)
(OStyp)
(OSmax)
30 40 50 60 70
Current Limit Resistor (k : )
80 90 100
D019
700
600
500
400
300
I
I
I
(OSmin)
(OStyp)
(OSmax)
200
100
0
100 200 300 400 500 600 700 800 900 1000
Current Limit Resistor (k : )
D020
Figure 42. Current Limit Setting vs Programming Resistor
I
Figure 43. Current Limit Setting vs Programming Resistor
II
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The routing of the traces to the R
(ILIM_xx) resistors should have a sufficiently low resistance so as to not affect the current-limit accuracy. The ground connection for the R
(ILIM_xx) resistors is also very important. The resistors must reference back to the TPS2549-Q1 GND pin. Follow normal board layout practices to ensure that current flow from other parts of the board does not impact the ground potential between the resistors and the TPS2549-Q1
GND pin.
8.4 Device Functional Modes
8.4.1 Device Truth Table (TT)
The device truth table (
) lists all valid combinations for the three control pins (CTL1 through CTL3), and the corresponding charging mode of each pin combination. The TPS2549-Q1 device monitors the CTL inputs and transitions to whichever charging mode it is commanded to go to. For example, if the USB port is a chargingonly port, then the user must set the CTL pins of the TPS2549-Q1 device to correspond to the DCP-auto charging mode. However, when the USB port requires data communication, then the user must set control pins to correspond to the SDP or CDP mode, and so on.
CTL1 CTL2
0
0
0
1
1
1
0
0
1
0
1
1
CTL3
0
1
X
X
0
1
CURRENT
LIMIT
SETTING
Lo
Hi
Lo
NA
Lo
Hi
MODE
DCP1
(1)
Table 2. Truth Table
STATUS
OUTPUT
(ACTIVE-
LOW)
OFF
FAULT
OUTPUT
(ACTIVE-
LOW)
ON
(2)
DCP
(1)
SDP
Client mode
SDP1
(3)
CDP
(3)
ON
OFF
OFF
OFF
ON
ON
ON
OFF
ON
(2)
ON
CS FOR CABLE
COMPENSATION
ON
ON
ON
OFF
ON
ON
NOTES
DCP includes divider 3,
1.2-V mode, and
BC1.2 mode
DCP includes divider 3,
1.2-V mode, and
BC1.2 mode
Standard SDP port
No current limit, power switch disabled, data switch bypassed
Standard SDP port
CDP-SDP auto switch mode
(1) No OUT discharge when changing between 000 and 001
(2) FAULT not asserted on overcurrent
(3) No OUT discharge when changing between 110 and 111
8.4.2 USB Specification Overview
The following overview references various industry standards. TI recommends consulting the most up-to-date standards to ensure the most recent and accurate information. Rechargeable portable equipment requires an external power source to charge batteries. USB ports are a convenient location for charging because of an available 5-V power source. Universally accepted standards are required to ensure host and client-side devices operate together in a system to ensure power-management requirements are met. Traditionally, host ports following the USB-2.0 specification must provide at least 500 mA to downstream client-side devices. Because multiple USB devices can be attached to a single USB port through a bus-powered hub, the client-side device sets the power allotment from the host to ensure the total current draw does not exceed 500 mA. In general, each USB device is granted 100 mA and can request more current in 100-mA unit steps up to 500 mA. The host grants or denies additional current based on the available current. A USB-3.0 host port not only provides higher data rate than a USB-2.0 port but also raises the unit load from 100 mA to 150 mA. Providing a minimum current of 900 mA to downstream client-side devices is required.
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Additionally, the success of USB has made the micro-USB and mini-USB connectors a popular choice for walladapter cables. A micro-USB or mini-USB allows a portable device to charge from both a wall adapter and USB port with only one connector. As USB charging has gained popularity, the 500-mA minimum defined by USB 2.0, or 900 mA for USB 3.0, has become insufficient for many handset and personal media players, which require a higher charging rate. Wall adapters provide much more current than 500 or 900 mA. Several new standards have been introduced defining protocol handshaking methods that allow host and client devices to acknowledge and draw additional current beyond the 500-mA and 900-mA minimum defined by USB 2.0 and USB 3.0, respectively, while still using a single micro-USB or mini-USB input connector.
The TPS2549-Q1 device supports four of the most-common USB-charging schemes found in popular hand-held media and cellular devices.
• USB Battery Charging Specification BC1.2
• Chinese Telecommunications Industry Standard YD/T 1591-2009
• Divider 3 mode
• 1.2-V mode
The BC1.2 specification includes three different port types:
• Standard downstream port (SDP)
• Charging downstream port (CDP)
• Dedicated charging port (DCP)
BC1.2 defines a charging port as a downstream-facing USB port that provides power for charging portable equipment. Under this definition, CDP and DCP are defined as charging ports.
lists the difference between these port types.
PORT TYPE
SDP (USB 2.0)
SDP (USB 3.0)
CDP
DCP
Table 3. Operating Modes Table
SUPPORTS USB2.0 COMMUNICATION
YES
YES
YES
NO
MAXIMUM ALLOWABLE CURRENT
DRAWN BY PORTABLE EQUIPMENT (A)
0.5
0.9
1.5
1.5
8.4.3 Standard Downstream Port (SDP) Mode — USB 2.0 and USB 3.0
An SDP is a traditional USB port that follows USB 2.0 or USB 3.0 protocol. A USB 2.0 SDP supplies a minimum of 500 mA per port and supports USB 2.0 communications. A USB 3.0 SDP supplies a minimum of 900 mA per port and supports USB 3.0 communications. For both types, the host controller must be active to allow charging.
8.4.4 Charging Downstream Port (CDP) Mode
A CDP is a USB port that follows USB BC1.2 and supplies a minimum of 1.5 A per port. A CDP provides power and meets the USB 2.0 requirements for device enumeration. USB-2.0 communication is supported, and the host controller must be active to allow charging. The difference between CDP and SDP is the host-charge handshaking logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device and allows for additional current draw by the client device.
The CDP handshaking process occurs in two steps. During step one, the portable equipment outputs a nominal
0.6-V output on the D+ line and reads the voltage input on the D– line. The portable device detects the connection to an SDP if the voltage is less than the nominal data-detect voltage of 0.3 V. The portable device detects the connection to a CDP if the D– voltage is greater than the nominal data detect voltage of 0.3 V and optionally less than 0.8 V.
The second step is necessary for portable equipment to determine whether the equipment is connected to a CDP or a DCP. The portable device outputs a nominal 0.6-V output on the D– line and reads the voltage input on the
D+ line. The portable device concludes the equipment is connected to a CDP if the data line being read remains less than the nominal data detects voltage of 0.3 V. The portable device concludes it is connected to a DCP if the data line being read is greater than the nominal data detect voltage of 0.3 V.
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8.4.5 Dedicated Charging Port (DCP) Mode
A DCP only provides power and does not support data connection to an upstream port. As shown in the following sections, a DCP is identified by the electrical characteristics of the data lines. The TPS2549-Q1 only emulates one state, DCP-auto state. In the DCP-auto state, the device charge-detection state machine is activated to selectively implement charging schemes involved with the shorted, divider3 and 1.2 v modes. The shorted DCP mode complies with BC1.2 and Chinese Telecommunications Industry Standard YD/T 1591-2009, whereas the divider3 and 1.2 V modes are employed to charge devices that do not comply with the BC1.2 DCP standard.
8.4.5.1 DCP BC1.2 and YD/T 1591-2009
Both standards specify that the D+ and D– data lines must be connected together with a maximum series impedance of 200 Ω, as shown in
.
V
BUS
5 V
D–
200 Ω
(m a x.)
D+
GND
Figure 44. DCP Supporting BC1.2 and YD/T 1591-2009
8.4.5.2 DCP Divider-Charging Scheme
The device supports divider3, as shown in
Figure 45 . In the Divider3 charging scheme the device applies 2.7 V
and 2.7 V to D+ and D– data lines.
V
BUS
5 V
D–
D+
2.7 V
2.7 V
GND
Figure 45. Divider 3 Mode
8.4.5.3 DCP 1.2-V Charging Scheme
The DCP 1.2-V charging scheme is used by some hand-held devices to enable fast charging at 2 A. The
TPS2549-Q1 device supports this scheme in DCP-auto state before the device enters BC1.2 shorted mode. To simulate this charging scheme, the D+ and D– lines are shorted and pulled up to 1.2 V for a fixed duration. Then the device moves to DCP shorted mode as defined in the BC1.2 specification and as shown in
5 V
200 Ω (m a x.)
V
BUS
D–
1.2 V
D+
GND
Figure 46. 1.2-V Mode
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8.4.6 DCP Auto Mode
As previously discussed, the TPS2549-Q1 device integrates an auto-detect state machine that supports all the
DCP charging schemes. The auto-detect state machine starts in the Divider3 scheme. However, if a BC1.2 or
YD/T 1591-2009 compliant device is attached, the TPS2549-Q1 device responds by turning the power switch back on without output discharge and operating in 1.2-V mode briefly before entering BC1.2 DCP mode. Then the auto-detect state machine stays in that mode until the device releases the data line, in which case the autodetect state machine goes back to the Divider3 scheme. When a Divider3-compliant device is attached, the
TPS2549-Q1 device stays in the Divider3 state.
5 V
S1
S2
S3
2.7 V 2.7 V 1.2 V
S4
V
BUS
DM_IN
DP_IN
GND
D–
D+
GND
Divider 3 Mode
S1, S2: ON
S3, S4: OFF
Shorted Mode
S4 ON
S1, S2, S3: OFF
1.2-V Mode
S1, S2: OFF
S3, S4: ON
Figure 47. DCP Auto Mode
8.4.7 Client Mode
The TPS2549-Q1 device integrates client mode as shown in
Figure 48 . The internal power switch is OFF and
only the data analog switch is ON to block OUT power. This mode can be used for some software programming via the USB port.
IN
DP_OUT
DM_OUT
OFF
OUT
DP_IN
DM_IN
Figure 48. Client-Mode Equivalent Circuit
8.4.8 High-Bandwidth Data-Line Switches
The TPS2549-Q1 device passes the D+ and D– data lines through the device to enable monitoring and handshaking while supporting the charging operation. A wide-bandwidth signal switch allows data to pass through the device without corrupting signal integrity. The data-line switches are turned on in any of the CDP,
SDP, or client operating modes. The EN input must be at logic high for the data line switches to be enabled.
NOTE
• While in CDP mode, the data switches are ON, even during CDP handshaking.
• The data line switches are OFF if EN is low, or if in DCP mode. The switches are not automatically turned off if the power switch (IN to OUT) is in current-limit.
• The data switches are only for a USB-2.0 differential pair. In the case of a USB-3.0
host, the super-speed differential pairs must be routed directly to the USB connector without passing through the TPS2549-Q1 device.
• Data switches are OFF during OUT (V
BUS
) discharge.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
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9.1 Application Information
The TPS2549-Q1 device is a USB charging-port controller and power switch with cable compensation. It is typically used for automotive USB port protection and as a USB charging controller. The following design procedure can be used to select components for the TPS2549-Q1 device. This section presents a simplified discussion of how to design cable compensation.
9.2 Typical Application
Automotive USB port charging requires a voltage regulator to convert battery voltage to 5-V V
Because the V
BUS
BUS output.
, D+, and D– pins of a USB port are exposed, there is a need for a protection device that has
V
BUS overcurrent and D+ and D– ESD protection. An additional need is a charging controller with integrated CDP and DCP charging protocols on D+ and D– to support fast charging. A schematic of an application circuit with cable compensation is shown in
. An LMR14030 device is used as the voltage regulator, and the
TPS2549-Q1 device is used as the charging controller with protection features.
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Typical Application (continued)
12 V
TPS2549-Q1
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0.1 µF
60.4 kW
0.018 µF
BOOT
VIN
SW
EN
LMR14030
GND
RT/SYNC
SS
FB
0.75 V
10 µH
V
(DC)
To Portable Device
R
(BUS) 0.1µF
IN
47 mΩ
OUT
2 × 47 µF
V
BUS
TPS2549-Q1
FAULT
DM_IN
DP_IN
R
(GN D)
1.5-m USB Cable
FAULT
STATUS
STATUS
GND
CS
I /O
EN
ILIM_LO
ILIM _HI
CTL1
CTL2
CTL3
DM_OUT
To Host
Controller
20 k W 80.6 k W
DP_OUT
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Figure 49. Typical Application Schematic: USB Port Charging With Cable Compensation
9.2.1 Design Requirements
For this design example, use the following as the input parameters.
DESIGN PARAMETER
Input voltage, V
(IN)
Output voltage, V
(DC)
Total parasitic resistance including TPS2549-Q1 r
DS(on)
Maximum continuous output current, I
(OUT)
Current limit, I
(LIM)
12 V
5 V
420 m Ω
2.4 A
2.5 A to 2.9 A
EXAMPLE VALUE
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9.2.2 Detailed Design Procedure
To begin the design process, a few parameters must be decided upon. The designer needs to know the following:
• Total resistance including power switch r
DS(on)
, cable resistance, and the contact resistance of connectors
• The maximum continuous output current for the charging port. The minimum current-limit setting of TPS2549-
Q1 device must be higher than this current.
• The maximum output current of the upstream dc-dc converter. The maximum current-limit setting of
TPS2549-Q1 device must be lower than this current.
9.2.2.1 Input and Output Capacitance
Input and output capacitance improves the performance of the device; the actual capacitance should be optimized for the particular application. All protection circuits including the TPS2549-Q1 device have the potential for input voltage droop, overshoot, and output-voltage undershoot.
For all applications, TI recommends a 0.1-µF or greater ceramic bypass capacitor between IN and GND, placed as close as possible to the device for the local noise decoupling.
The TPS2549-Q1 device is used for 5-V power rail protection when a hot-short occurs on the output or when plugging in a capacitive load. Due to the limited response time of the upstream power supply, a large load transient can deplete the charge on the output capacitor of the power supply, causing a voltage droop. If the power supply is shared with other loads, ensure that voltage droop from current surges of the other loads do not force the TPS2549-Q1 device into UVLO. Increasing the upstream power supply output capacitor can reduce this droop. Shortening the connection impedance (resistance and inductance) between the TPS2549-Q1 device and the upstream power supply can also help reduce the voltage droop and overshoot on the TPS2549-Q1 input power bus.
Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input voltage in conjunction with input power-bus inductance and input capacitance when the IN terminal is in the highimpedance state (before turnon). Theoretically, the peak voltage is 2 times the applied voltage. The second cause is due to the abrupt reduction of output short-circuit current when the TPS2549-Q1 device turns off and energy stored in the input inductance drives the input voltage high. Applications with large input inductance (for example, connecting the evaluation board to the bench power supply through long cables) may require large input capacitance to prevent the voltage overshoot from exceeding the absolute maximum voltage of the device.
For output capacitance, consider the following three application situations.
The first, output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred and the TPS2549-Q1 has abruptly reduced OUT current. Energy stored in the inductance will drive the
OUT voltage down and potentially negative as it discharges. Applications with large output inductance (such as from a cable) benefit from use of a high-value output capacitor to control the voltage undershoot. Second, for
USB-port application, because the OUT pin is exposed to the air, the application must withstand ESD stress without damage. Because there is no internal IEC ESD cell as on DP_IN and DM_IN, using a low-ESR capacitance can make this pin robust. Third, when plugging in apacitive load such as the input capacitor of any portable device, having a large output capacitance can help reduce the peak current and up-stream power supply output voltage droop. So for TPS2549-Q1 output capacitance, recommended practice is typically adding two 47-µF ceramic capacitors.
9.2.2.2 Cable Compensation Calculation
Based on the known total resistance,
shows the calculation.
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V
(DC)
(V) without load
R
(G)
(k Ω)
R
(total)
( Ω)
G
(CS)
(mA/A)
R
(FA)
(k Ω)
V
(FB)
(V)
R
(FB)
(k Ω)
V
(CS)
(V)
(2)
Maximum I
OS
(A) at 20 kΩ
V
(DC,max) output (V)
(3)
Table 4. Cable Compensation Calculation
CALCULATION EQUATION
(1)
R
(FA)
= R
(total)
/ G
(CS)
CALCULATED VALUE
5
6.8
0.42
0.075
5.6
0.75
32.93
R
(FB)
R
(G)
= [V
(DC)
– R
(FA)
/ (V
(FB)
/ R
(G)
)] –
V
CS
R
(FB)
= (V
(FB)
)
/ R
(G)
) × (R
(G)
+ 4.39
V
(DC,max)
G
(CS,max)
= 5 + I
(OS,max)
× R
(FA)
×
2.84
6.25
ASSEMBLY VALUE
6.8
5.6
33
C
(OUT)
(µF)
C
(COMP)
(nF)
(4)
C
(COMP)
≥ 3 × G
(CS)
× C
(OUT)
≥21.15
2 × 47
22
(1) See
and
.
(2) Ensure that V
CS
(3) Ensure that the maximum dc-dc output voltage is lower than 6.5 V when considering I
(OS,max)
(4) C
COMP exceeds 2.5 V.
and G
(CS,max)
.
impacts load-transient performance, so the output performance should always be verified in the end application circuit.
9.2.2.3 Power Dissipation and Junction Temperature
The low on-resistance of the N-channel MOSFET allows small surface-mount packages to pass large currents. It is good design practice to estimate power dissipation and junction temperature. The following analysis gives an approximation for calculating junction temperature based on the power dissipation in the package. However, it is important to note that thermal analysis is strongly dependent on additional system-level factors. Such factors include air flow, board layout, copper thickness and surface area, and proximity to other devices dissipating power. Good thermal design practice must include all system-level factors in addition to individual component analysis. Begin by determining the r
DS(on) of the N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read r
DS(on) from the typical characteristics graph. Using this value, the power dissipation can be calculated by:
P
D
= r
DS(on)
´
I
OUT
2
(6) where:
P
D
= Total power dissipation (W)
I r
DS(on)
OUT
= Power-switch on-resistance (Ω)
= Maximum current-limit threshold (A)
This step calculates the total power dissipation of the N-channel MOSFET.
Finally, calculate the junction temperature:
T
J
=
P
D
´
R q JA
+
T
A
(7) where:
T
A
= Ambient temperature (°C)
R
θJA
P
D
= Thermal resistance (°C/W)
= Total power dissipation (W)
Compare the calculated junction temperature with the initial estimate. If they are not within a few degrees, repeat the calculation using the refined r
DS(on) from the previous calculation as the new estimate. Two or three iterations are generally sufficient to achieve the desired result. The final junction temperature is highly dependent on thermal resistance R
θJA
, and thermal resistance is highly dependent on the individual package and board layout.
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9.2.3 Application Curves
6.2
6
5.8
5.6
5.4
5.2
5
4.8
0
V
BUS
V
(DC)
0.5
1
I
(LOAD)
(A)
1.5
2
Figure 50. V
(DC) and V
BUS vs I
(LOAD)
Output
2.5
D018
V
(DC) at 5-V Offset
100 mV/div
I
(OUT)
200 mA/div
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V
(DC) at 5-V Offset
100 mV/div t = 20 ms/div
I
(OUT)
200 mA/div
Figure 51. Plugging In a Portable Device, V
(DC)
V
BUS at 5-V Offset
10 mV/div t = 20 ms/div
Figure 52. Unplugging a Portable Device, V
(DC)
I
(OUT)
200 mA/div t = 20 ms/div
Figure 53. Plugging In Portable Device, V
BUS
V
(DC) at 5-V Offset
200 mV/div
I
(OUT)
200 mA/div
V
BUS at 5-V Offset
100 mV/div t = 20 ms/div
Figure 54. Unplugging Portable Device, V
BUS
I
(OUT)
1 A/div t = 200 µs/div
Figure 55. 0.5-A ↔ 2.4-A Load Transient With 100-mA/µs
Slew Rate, V
(DC)
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TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
V
(DC)
1 V/div
V
BUS at 5-V Offset
200 mV/div
I
(OUT)
1 A/div t = 200 µs/div
Figure 56. 0.5-A ↔ 2.4-A Load Transient With 100-mA/µs
Slew Rate, V
BUS
I
(OUT)
2 A/div t = 200 µs/div
Figure 57. V
BUS
Shorted to GND, V
(DC)
10 Power Supply Recommendations
The TPS2549-Q1 device is designed for a supply-voltage range of 4.5 V ≤ V
IN
≤ 6.5 V. If the input supply is located more than a few inches from the device, an input ceramic bypass capacitor higher than 0.1 μF is recommended. The power supply should be rated higher than the TPS2549-Q1 current-limit setting to avoid voltage droops during overcurrent and short-circuit conditions.
11 Layout
11.1 Layout Guidelines
• For the trace routing of DP_IN, DM_IN, DP_OUT, and DM_OUT: Route these traces as micro-strips with nominal differential impedance of 90 Ω. Minimize the use of vias in the high-speed data lines. Keep the reference GND plane devoid from cuts or splits above the differential pairs to prevent impedance discontinuities. For more information, see the High Speed USB Platform Design Guideline from Intel.
• The trace routing from the upstream regulator to the TPS2549-Q1 IN pin should as short as possible to reduce the voltage drop and parasitic inductance.
• The traces routing from the R
ILIM_HI and R
ILIM_LO resistors to the device should be as short as possible to reduce parasitic effects on the current-limit accuracy.
• The thermal pad should be directly connected to the PCB ground plane using a wide and short copper trace.
• The trace routing from the CS pin to the feedback divider of the upstream regulator should not be routed near any noise sources that can capacitively couple to the feedback divider.
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TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
11.2 Layout Example
Top Layer Signal Trace
Top Layer Signal Ground Plane
Bottom Layer Signal Trace
Via to Bottom Layer Signal Ground Plane
Via to Bottom Layer Signal
IN 1
DM_OUT
DP_OUT
2
CS
3
4
16 15 14 13
12
11
10
9
5 6 7 8
OUT
DM_IN
DP_IN
STATUS
Figure 58. TPS2549-Q1 Layout Diagram
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12 Device and Documentation Support
TPS2549-Q1
SLUSCE3B – OCTOBER 2015 – REVISED JULY 2016
12.1 Documentation Support
12.1.1 Related Documentation
High Speed USB Platform Design Guidelines, Intel
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use .
TI E2E™ Online Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
Design Support
TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Jul-2016
PACKAGING INFORMATION
Orderable Device
TPS2549IRTERQ1
Status
(1)
ACTIVE
Package Type Package
Drawing
WQFN RTE
Pins Package
16
Qty
Eco Plan
(2)
3000 Green (RoHS
& no Sb/Br)
Lead/Ball Finish
(6)
CU NIPDAU
MSL Peak Temp
(3)
Level-2-260C-1 YEAR
Op Temp (°C)
-40 to 85 2549Q
Device Marking
(4/5)
TPS2549IRTETQ1 ACTIVE WQFN RTE 16 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
-40 to 85 2549Q
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
5-Jul-2016 www.ti.com
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
www.ti.com
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
5-Jul-2016
*All dimensions are nominal
Device
TPS2549IRTERQ1
TPS2549IRTETQ1
Package
Type
Package
Drawing
WQFN
WQFN
RTE
RTE
Pins
16
16
SPQ
3000
250
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
330.0
12.4
180.0
12.4
A0
(mm)
3.3
3.3
B0
(mm)
3.3
3.3
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
www.ti.com
PACKAGE MATERIALS INFORMATION
5-Jul-2016
*All dimensions are nominal
Device
TPS2549IRTERQ1
TPS2549IRTETQ1
Package Type Package Drawing Pins
WQFN
WQFN
RTE
RTE
16
16
SPQ
3000
250
Length (mm) Width (mm) Height (mm)
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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