19-0324; Rev 2; 12/97 1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection ____________________________Features ♦ 900MHz Bandwidth The MAX3262 has complementary loss-of-signal outputs for interfacing with open-fiber-control (OFC) circuitry. These outputs can be programmed to assert with input levels between 9mVp-p and 48mVp-p. LOS hysteresis for any programmed level is nominally 3.0dB, preserving a balance between noise immunity and dynamic range. ♦ Single +5V Power Supply ♦ 48dB Maximum Gain ♦ Chatter-Free LOS ♦ Programmable LOS Threshold ♦ Fully Differential Architecture _______________Ordering Information ________________________Applications 1062Mbps Fibre Channel PART TEMP. RANGE MAX3262CAG 0°C to +70°C (TA) PIN-PACKAGE 24 SSOP MAX3262C/D 0°C to +100°C (TJ) Dice* *Dice are designed to operate over this range but are tested and guaranteed only at TA = +25°C. 622Mbps SONET Pin Configuration appears at end of data sheet. ____________________________________________________Typical Operating Circuit CAZ CZP CZN FILTER DIN+ CIN MAX3260 INPUT DINVCC DOUT+ RECEIVER WITH PECL TERMINATIONS DOUT- (50Ω TO VCC - 2V) OUTPUT MAX3262 CIN GND ENB LOS VCC LOSB 50Ω +5V +5V GND DIV2 VLOS C1 0.01µF VCCA VCCB VCCC VCCD VCCE +5V R 4.7k R 4.7k LOS LOSB +5V C1 0.01µF +5V R1 R2 ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. MAX3262 ________________General Description The MAX3262 limiting amplifier with its high gain and wide bandwidth is ideal for use as a post amplifier in fiber-optic receivers with data rates up to 1Gbps. The amplifier’s gain can be adjusted between 33dB and 48dB. At maximum gain, signals as small as 6mVp-p can be amplified to drive devices with PECL inputs. MAX3262 1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection ABSOLUTE MAXIMUM RATINGS Power Supply, VCC - VEE ......................................................6.0V Input Voltage, DIN+, DIN- .....................................................6.0V CZN, CZP, ENB, VLOS, DIV2, LOS+, LOS-.....-0.3V, VCC + 0.3V DOUT+, DOUT- (with 50Ω load) .......................2.5V, VCC + 0.3V Continuous Power Dissipation (TA = +70°C) SSOP (derate 10mW/°C above +70°C) ....................500mW°C Junction Operating Temperature ......................-55°C to +150°C Storage Temperature Range .............................-55°C to +175°C Processing Temperature (Die).........................................+400°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +5V, RLOAD = 50Ω to VCC - 2V (equivalent), TA = 0°C to +70°C. Typical values are at VCC = 5V and TA = +25°C.) PARAMETER SYMBOL Power-Supply Current IVCC Enable Input Current IENB VLOS Input Current ILOS CONDITIONS MIN TYP No output load UNITS 60 mA 150 µA 120 Common-Mode Output Voltage VCC = 5.0V LOS+, LOS- Output Low Voltage IOUT = -1.0mA DIV2 Short-Circuit Current DIV2 = 0V 3.5 3.7 µA 3.8 V 0.5 V 0.5 Differential Output Offset, DOUT+ to DOUTInput Bias Voltage MAX VDIN 2.5 mA ±35 mV 3.0 V MAX UNITS AC ELECTRICAL CHARACTERISTICS (VCC = +5V, RLOAD = 50Ω to 3V, AC parameters are not tested, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Power-Supply Rejection Ratio PSRR Input referred, 55MHz LOS Release Time, Minimum Input tOFFL (Note 1) LOS Release Time, Maximum Input tOFFH (Note 2) LOS Assert Time tONL (Note 1) Input Voltage Range VID Peak-to-peak LOS Sensitivity Range VSR Differential inputs, peak-to-peak LOS Hysteresis HYS VLOS = 5V, Pattern 27 - 1PRBS Differential Input Noise Vn Pulse-Width Distortion PWD Output Edge Speed tR, tF Output Voltage Amplitude VOUT Small-Signal Bandwidth BW MIN TYP 35 0.020 0.2 0.5 µs 0.5 µs 0.5 µs 0.006 1.8 V MAX3262C/D 9 48 MAX3262CAG 10 48 1.5 VLOS = 5V, DIV2 = GND (Note 3) 3.0 5.0 80 1Gbps, 8mVp-p input VOH - VOL 400 600 MAX3262C/D 800 925 MAX3262CAG 750 810 Note 1: Input is a 200MHz square wave, tR < 300ps, 8mVp-p. Note 2: Input is a 200MHz square wave, tR < 300ps, 1.8Vp-p. Note 3: Input-referred noise = RMS output noise/low-frequency gain. 2 dB _______________________________________________________________________________________ mV dB µV 40 ps 250 ps 730 mV MHz 1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection VCC SUPPLY CURRENT (NO OUTPUT LOAD) vs. TEMPERATURE 45 4.75V 4 3 1 4.5 20 40 60 80 100 400 120 800 1000 FREQUENCY (Mbps) FREQUENCY RESPONSE 55 VLOS = 5V DIV2 = GND 49 GAIN (dB) 3.0 2.0 VLOS = 5V DIV2 OPEN 43 VLOS = 3.4V DIV2 OPEN 37 VLOS = 3.0V DIV2 OPEN 31 1.0 25 0 0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 200 400 600 800 1000 1200 1400 VLOS (V) FREQUENCY (MHz) EYE DIAGRAM LOS OPERATION 1Gbps RLOAD = 50Ω to VCC - 2V (EQUIVALENT) VIN = 250mV, VCC = +5V, DIV2 = GND, VLOS = VCC MAX3262-07 +500mV 600 TEMPERATURE (°C) MAX3262-04 1Gbps DIV2 = 0 1,0 PATTERN PRBS 27-1 4.0 0 LOS HYSTERESIS vs. VLOS 5.0 4.0 5.5 5.0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) HYSTERESIS (dB) 0 1-0 PATTERN 6.0 2 0 40 6.5 MAX3262-05 5.0V 5 K28.5 SEQUENCE (FIBRE CHANNEL IDLE PATTERN) 7.0 MAX3262-06 50 7.5 SENSITIVITY (mVp-p) HYSTERESIS (dB) 5.25V 55 MAX3262-03 7 6 60 8.0 MAX3262-02 1Gbps WITH 1,0 PATTERN 65 SUPPLY CURRENT (mA) LOS SENSITIVITY vs. FREQUENCY 8 MAX3262-01 70 LOS HYSTERESIS vs. TEMPERATURE LOS OUTPUT 100mV/div DATA INPUT VLOS = VCC -500mV 225ps/div 2µs/div _______________________________________________________________________________________ 3 MAX3262 __________________________________________Typical Operating Characteristics (VCC = 5V, TA = +25°C, unless otherwise noted.) MAX3262 1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection _______________________________________________________________Pin Description 4 PIN NAME FUNCTION 1 VCCB Positive supply for internal gain stages 2 VLOS Power detect/LOS level set. Use this input to program the required threshold level for LOS assertion. 3 CZP Offset-correction loop compensation capacitor. This pin should be connected to the CZN pin through a 100nF to 330nF capacitor, which provides the dominant pole for the offset-correction loop. 4 CZN Offset-correction loop compensation capacitor. This pin should be connected to the CZP pin through a 100nF to 330nF capacitor, which provides the dominant pole for the offset-correction loop. 5 VCCA Power supply for the input stage amplifier 6 DIN+ Data Input 7 DIN- Inverting Data Input 8 GND Ground for the input stage amplifier 9 ENB Output Enable. Output gain stage is disabled and LOS circuitry remains functional. 10 DIV2 Input stage gain adjust. Grounding this pin forces the input stage gain to maximum (11dB) for applications where the LOS threshold level will be set for input signals in the 9mVp-p to 20mVp-p range. Leaving this pin open forces the gain of the input stage to be divided by two (6dB) for applications where the LOS threshold level will be set for input signal levels in the 15mVp-p to 48mVp-p range. 11 VTH Comparator threshold voltage for test only. Leave unconnected. 12 VCCE Positive supply for the power detect/LOS circuitry 13 GND Ground for the power detect/LOS circuitry 14 GND Ground for the LOS+/LOS- buffer circuitry 15 VCCD Positive supply for the LOS+/LOS- buffer circuitry 16 LOS- Loss-of-Signal detect. This pin is asserted low when input power drops below the LOS threshold level. 17 LOS+ Loss-of-Signal detect. This pin is asserted high when input power drops below the LOS threshold level. 18 DOUT- Inverting Data Output 19 DOUT+ Data Output 20 GND Substrate Ground 21 VCCC Positive supply for bias generators 22 GND Ground for bias generators 23 VCC Positive supply for output buffers 24 GND Ground for internal gain stages _______________________________________________________________________________________ 1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection MAX3262 CAZ VLOS OFFSET CORRECTION 20k 20k DIN+ DOUT+ 5dB/11dB 0dB to 11dB 10dB 10dB 6dB DIN- DOUTRMS DETECT DIV2 MAX3262 BIAS ENB LOS+ REFERENCE LOS- Figure 1. Functional Diagram _______________ Detailed Description The MAX3262 is an integrated limiting amplifier intended for high-frequency fiber-optic applications. The circuit connects to typical transimpedance amplifiers found within a fiber-optic link. The linear signal output from a transimpedance amplifier can contain significant amounts of noise, and may vary in amplitude over time. The MAX3262 limiting amplifier quantizes the signal, and outputs a voltage-limited waveform over a 48dB input dynamic range. The MAX3262 provides an offset correction function that effectively reduces the offset voltage to negligible levels. In communications systems using NRZ data with a 50% duty cycle, pulse-width distortion present in the signal or generated by the transimpedance amplifier appears as input offset and is partially removed by the offset correction function. An external capacitor is required between CZP and CZN to compensate the offset correction loop, determining the lower 3dB point. Loss-of-Signal Function The MAX3262 incorporates a chatter-free loss-of-signal function, which is used to detect that the input signal has dropped below the level necessary for acceptable bit error rate performance, or to indicate an open-fiber condition. The loss-of-signal function is implemented with a rectifying peak detector, which samples the signal entering the output stage. The output from the peak detector is compared against an internally generated threshold, and is used to assert the LOS+ and LOSoutputs. The loss-of-signal threshold is adjusted by varying the amplifier gain. The MAX3262 is configurable for gains between 33dB and 48dB, allowing LOS thresholds between 9mVp-p and 48mVp-p. Figure 2 shows the LOS threshold as a function of the DIV2 and VLOS pins. The DIV2 pin provides a coarse adjustment of 6dB of gain, while the VLOS pin provides a fine gain adjustment between 0dB and 11dB. _______________________________________________________________________________________ 5 MAX3262 1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection VCC = 5V 45 MAX3262-07 LOS ASSERT LEVEL 50 +5V SENSITIVITY (mVp-p) 40 35 30 RLOS MAX3262 DIV2 OPEN LOS+ LOS OUTPUT WITH DESIRED RISE TIME 25 CLOS 20 LOS BUFFER 15 10 5 DIV2 GROUNDED 0 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 VLOS (V) RLOS ≥ 3.3kΩ Figure 2. MAX3262 Sensitivity vs. VLOS Setting Figure 3. Setting the LOS Time Constant Level-detect hysteresis and a 200ns internal delay ensure chatter-free LOS outputs when the input signal level is close to the LOS threshold. The hysteresis for any programmed loss-of-signal level is nominally 2.5dB. The LOS+ and LOS- outputs are open-collector, Schottky-clamped transistors, that require pull-up resistors for proper operation (Figure 3). The loss-of-signal time constant is set externally with the appropriate pull-up resistor and shunt load capacitance. The ENB pin allows the user to disable the output signal without removing the input signal. CIN should be large enough to not affect the signal quality, but small enough to not affect the LOS assert time. When an open-fiber condition occurs, the input coupling capacitors must discharge below the LOS threshold level before the LOS can assert. The worstcase discharge time would occur with the maximum input signal and the minimum LOS threshold. In this case, the input capacitor must discharge from 0.9V to 4.5mV. The time required for this to occur is: t = (1500)(CIN) In(VMAX / VTHRESH) seconds Example: If the MAX3262 is configured for 6mV sensitivity, CIN = 100pF results in a lower -3dB frequency of 1MHz, and a maximum LOS delay of about 1µs. Wire Bonding Die For reliable operation, the MAX3262 has gold metalization. Connections to the die should be made with gold wire only, using ball bonding techniques. Wedge bonding is not recommended. Bond pad size is 4 mils. __________________ Design Procedure Determining Capacitor Values The MAX3262 inputs must be AC coupled to allow proper operation of the offset correction function. Figure 4 shows the circuit’s input stage. The circuit’s lower -3dB point is determined by the input coupling capacitors. The lower -3dB frequency is 1 / [(2π)(1500Ω)(CIN)] Hz. 6 The offset correction capacitor (CAZ) must be greater than 100nF to ensure stable operation. This capacitor is in series with an internal 40kΩ of resistance. The -3dB point of the offset zeroing circuit is: 1 / [(2π)(CAZ)(40kΩ)] Hz For CAZ = 180nF, the bandwidth of the offset correction circuit is 22Hz. Maxim’s proprietary offset-correction architecture decouples the input coupling time constant from the offset correction time constant. This ensures there is no interaction between these two networks, eliminating an additional source of chatter on LOS. _______________________________________________________________________________________ 1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection VCC MAX3262 Layout and PC Board Design Since the MAX3262 is a high-frequency component, the circuit’s performance can largely be determined by board layout and design. A common problem with high-gain amplifiers is feedback from the large swing outputs to the input via the power supply. Some fiberoptic limiting amplifiers suffer from LOS “chatter.” The act of switching the LOS outputs on or off generates noise on the power supply, which can cause the LOS outputs to chatter. With proper board layout, the MAX3262 ensures chatter-free LOS operation. CIN DIN+ VIN CIN DIN- 1.5k 1.5k The MAX3262 has five ground pins and a substrate connection. All of these should be connected to the circuit board’s ground. Use multiple PCB vias close to the part to connect the grounds. Avoid long, inductive runs, which can degrade MAX3262 performance. The MAX3262’s six VCC supply pins must all be connected. VCCA–VCCE can be collectively decoupled with one capacitor. VCC (pin 23) should be decoupled separately (see the Typical Operating Circuit). Figure 4. MAX3262 Equivalent Input Circuit +5V 82Ω DOUT+ DOUT+ 330Ω 50Ω MAX3262 120Ω MAX3262 +5V ZLOAD >500Ω 82Ω DOUT- DOUT330Ω a) DRIVING A 50Ω LOAD TO GROUND 50Ω 120Ω b) DRIVING A HIGH-IMPEDANCE LOAD Figure 5. Output Termination Techniques _______________________________________________________________________________________ 7 MAX3262 Output Termination The MAX3262 outputs must be terminated with a 50Ω load to (VCC - 2V), or a Thevenin equivalent. Figure 5 shows two possible output termination methods. MAX3262 1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection ___________________Pin Configuration ____________________Chip Topography TOP VIEW VCCB 1 24 GND VLOS 2 23 VCC CZP 3 22 GND CZN 4 VCCA 5 21 VCCC MAX3262 V CC C GND DOUTLOSDOUT+ LOS+ GND V CC D V CC GND 20 GND DIN+ 6 19 DOUT+ DIN- 7 18 DOUT- GND 8 17 LOS+ ENB 9 16 LOS- DIV2 10 15 VCCD VTH 11 14 GND VCCE 12 13 GND SSOP 0.080" (2.032mm) GND GND V CC B V CC E V LOS VTH CZP DIV2 CZN V CC A DIN+ DIN- GND ENB 0.060" (1.524mm) TRANSISTOR COUNT: 200 SUBSTRATE CONNECTED TO GND PIN 17 Maxim makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Maxim assume any liability arising out of the application or use of any product or circuit, and Maxim specifically disclaims any and all liability including, without limitation, consequential or incidental damages. “Typical’’ parameters can and do vary in different applications. All operating parameters, including “typicals”, must be validated for each customer application by customer’s technical experts. Maxim products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Maxim product could create a situation where personal injury or death may occur. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project