nRF52 Product Specification

nRF52 Product Specification
nRF52832 Product Specification v1.1
Key features
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2.4 GHz transceiver
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-96 dBm sensitivity in Bluetooth® low energy mode
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1 Mbps, 2 Mbps supported data rates
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TX power -20 to +4 dBm in 4 dB steps
Single-pin antenna interface
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5.3 mA peak current in TX (0 dBm)
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5.4 mA peak current in RX
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RSSI (1 dB resolution)
ARM® Cortex®-M4 32-bit processor with FPU, 64 MHz
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215 EEMBC CoreMark® score running from flash memory
58 μA/MHz running from flash memory
51.6 μA/MHz running from RAM
Data watchpoint and trace (DWT), embedded trace macrocell (ETM), and
instrumentation trace macrocell (ITM)
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Serial wire debug (SWD)
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Trace port
Flexible power management
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Supply voltage range 1.7 V–3.6 V
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Fully automatic LDO and DC/DC regulator system
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Fast wake-up using 64 MHz internal oscillator
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0.7 μA at 3 V in OFF mode
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1.0 μA at 3 V in OFF mode with 32 kB RAM retention
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1.9 μA at 3 V in ON mode, no RAM retention, wake on RTC
Memory
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512 kB flash/64 kB RAM
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256 kB flash/32 kB RAM
Nordic SoftDevice ready
Support for concurrent multi-protocol
Type 2 near field communication (NFC-A) tag with wakeup-on-field and touchto-pair capabilities
12-bit, 200 ksps ADC - 8 configurable channels with programmable gain
64 level comparator
15 level low power comparator with wakeup from System OFF mode
Temperature sensor
32 general purpose I/O pins
3x 4-channel pulse width modulator (PWM) units with EasyDMA
Digital microphone interface (PDM)
5x 32-bit timers with counter mode
Up to 3x SPI master/slave with EasyDMA
Up to 2x I2C compatible 2-Wire master/slave
I2S with EasyDMA
UART (CTS/RTS) with EasyDMA
Programmable peripheral interconnect (PPI)
Quadrature decoder (QDEC)
AES HW encryption with EasyDMA
Autonomous peripheral operation without CPU intervention using PPI and
EasyDMA
3x real-time counter (RTC)
External system
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Single crystal operation
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On-chip balun (single-ended RF)
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Few external components
Package variants
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QFN48 package, 6 × 6 mm
WLCSP package, 3.0 × 3.2 mm
Applications
Applications
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Internet of Things (IoT)
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Home automation
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Sensor networks
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Building automation
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Industrial
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Retail
Personal area networks
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Health/fitness sensor and monitor devices
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Medical devices
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Key fobs and wrist watches
Interactive entertainment devices
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Remote controls
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Gaming controllers
Beacons
A4WP wireless chargers and devices
Remote control toys
Computer peripherals and I/O devices
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Mouse
Keyboard
Multi-touch trackpad
Gaming
Contents
Contents
1 Revision history................................................................................... 9
2 About this document............................................................................................ 10
2.1 Peripheral naming and abbreviations................................................................................... 10
2.2 Register tables...................................................................................................................... 10
2.3 Registers............................................................................................................................... 11
3 Block diagram........................................................................................................12
4 Pin assignments.................................................................................................... 13
4.1 QFN48 pin assignments....................................................................................................... 13
4.2 WLCSP ball assignments..................................................................................................... 15
4.3 GPIO usage restrictions........................................................................................................17
5 Absolute maximum ratings.................................................................................. 19
6 Recommended operating conditions.................................................................. 20
7 CPU......................................................................................................................... 21
7.1 Floating point interrupt.......................................................................................................... 21
7.2 Electrical specification........................................................................................................... 21
7.3 CPU and support module configuration................................................................................22
8 Memory................................................................................................................... 23
8.1
8.2
8.3
8.4
RAM - Random access memory...........................................................................................23
Flash - Non-volatile memory.................................................................................................24
Memory map......................................................................................................................... 24
Instantiation........................................................................................................................... 24
9 AHB multilayer.......................................................................................................26
9.1 AHB multilayer priorities........................................................................................................26
10 EasyDMA.............................................................................................................. 27
10.1 EasyDMA array list............................................................................................................. 28
11 NVMC — Non-volatile memory controller......................................................... 29
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Writing to Flash...................................................................................................................29
Erasing a page in Flash..................................................................................................... 29
Writing to user information configuration registers (UICR)................................................. 29
Erasing user information configuration registers (UICR).................................................... 29
Erase all.............................................................................................................................. 30
Cache.................................................................................................................................. 30
Registers............................................................................................................................. 30
Electrical specification......................................................................................................... 33
12 BPROT — Block protection................................................................................34
12.1 Registers............................................................................................................................. 34
13 FICR — Factory information configuration registers.......................................43
13.1 Registers............................................................................................................................. 43
14 UICR — User information configuration registers........................................... 54
14.1 Registers............................................................................................................................. 54
15 Peripheral interface............................................................................................. 68
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
Peripheral ID....................................................................................................................... 68
Peripherals with shared ID..................................................................................................68
Peripheral registers............................................................................................................. 69
Bit set and clear..................................................................................................................69
Tasks................................................................................................................................... 69
Events..................................................................................................................................70
Shortcuts............................................................................................................................. 70
Interrupts............................................................................................................................. 70
Page 2
Contents
16 Debug and trace.................................................................................................. 72
16.1
16.2
16.3
16.4
16.5
DAP - Debug Access Port.................................................................................................. 72
CTRL-AP - Control Access Port......................................................................................... 73
Debug interface mode.........................................................................................................74
Real-time debug.................................................................................................................. 74
Trace................................................................................................................................... 75
17 Power and clock management...........................................................................76
17.1 Current consumption scenarios.......................................................................................... 76
18 POWER — Power supply....................................................................................78
18.1 Regulators........................................................................................................................... 78
18.2 System OFF mode..............................................................................................................79
18.3 System ON mode............................................................................................................... 80
18.4 Power supply supervisor.....................................................................................................80
18.5 RAM sections...................................................................................................................... 82
18.6 Reset................................................................................................................................... 82
18.7 Retained registers............................................................................................................... 83
18.8 Reset behavior.................................................................................................................... 83
18.9 Registers............................................................................................................................. 83
18.10 Electrical specification....................................................................................................... 99
19 CLOCK — Clock control...................................................................................101
19.1
19.2
19.3
19.4
HFCLK clock controller..................................................................................................... 101
LFCLK clock controller......................................................................................................103
Registers........................................................................................................................... 105
Electrical specification....................................................................................................... 109
20 GPIO — General purpose input/output........................................................... 111
20.1
20.2
20.3
20.4
Pin configuration............................................................................................................... 111
GPIO located near the RADIO......................................................................................... 113
Registers........................................................................................................................... 113
Electrical specification....................................................................................................... 154
21 GPIOTE — GPIO tasks and events..................................................................157
21.1
21.2
21.3
21.4
21.5
Pin events and tasks........................................................................................................ 157
Port event..........................................................................................................................158
Tasks and events pin configuration.................................................................................. 158
Registers........................................................................................................................... 158
Electrical specification....................................................................................................... 167
22 PPI — Programmable peripheral interconnect............................................... 168
22.1 Pre-programmed channels................................................................................................169
22.2 Registers........................................................................................................................... 169
23 RADIO — 2.4 GHz Radio.................................................................................. 204
23.1 EasyDMA...........................................................................................................................204
23.2 Packet configuration..........................................................................................................205
23.3 Maximum packet length.................................................................................................... 206
23.4 Address configuration........................................................................................................206
23.5 Data whitening.................................................................................................................. 206
23.6 CRC...................................................................................................................................207
23.7 Radio states...................................................................................................................... 208
23.8 Transmit sequence............................................................................................................208
23.9 Receive sequence.............................................................................................................210
23.10 Received Signal Strength Indicator (RSSI).....................................................................211
23.11 Interframe spacing...........................................................................................................211
23.12 Device address match.................................................................................................... 212
23.13 Bit counter....................................................................................................................... 212
23.14 Registers......................................................................................................................... 213
23.15 Electrical specification..................................................................................................... 229
24 TIMER — Timer/counter....................................................................................233
24.1 Capture..............................................................................................................................234
24.2 Compare............................................................................................................................234
Page 3
Contents
24.3
24.4
24.5
24.6
Task delays....................................................................................................................... 234
Task priority.......................................................................................................................234
Registers........................................................................................................................... 234
Electrical specification....................................................................................................... 240
25 RTC — Real-time counter.................................................................................241
25.1 Clock source..................................................................................................................... 241
25.2 Resolution versus overflow and the PRESCALER........................................................... 241
25.3 COUNTER register............................................................................................................242
25.4 Overflow features.............................................................................................................. 242
25.5 TICK event........................................................................................................................ 242
25.6 Event control feature.........................................................................................................243
25.7 Compare feature............................................................................................................... 243
25.8 TASK and EVENT jitter/delay........................................................................................... 245
25.9 Reading the COUNTER register.......................................................................................247
25.10 Registers......................................................................................................................... 247
25.11 Electrical specification..................................................................................................... 253
26 RNG — Random number generator................................................................ 254
26.1
26.2
26.3
26.4
Bias correction.................................................................................................................. 254
Speed................................................................................................................................ 254
Registers........................................................................................................................... 254
Electrical specification....................................................................................................... 256
27 TEMP — Temperature sensor.......................................................................... 257
27.1 Registers........................................................................................................................... 257
27.2 Electrical specification....................................................................................................... 262
28 ECB — AES electronic codebook mode encryption...................................... 263
28.1
28.2
28.3
28.4
28.5
Shared resources.............................................................................................................. 263
EasyDMA...........................................................................................................................263
ECB data structure............................................................................................................263
Registers........................................................................................................................... 264
Electrical specification....................................................................................................... 265
29 CCM — AES CCM mode encryption................................................................266
29.1
29.2
29.3
29.4
29.5
29.6
29.7
29.8
29.9
Shared resources.............................................................................................................. 267
Encryption..........................................................................................................................267
Decryption......................................................................................................................... 267
AES CCM and RADIO concurrent operation.................................................................... 268
Encrypting packets on-the-fly in radio transmit mode.......................................................268
Decrypting packets on-the-fly in radio receive mode........................................................269
CCM data structure...........................................................................................................270
EasyDMA and ERROR event........................................................................................... 271
Registers........................................................................................................................... 271
30 AAR — Accelerated address resolver.............................................................275
30.1 Shared resources.............................................................................................................. 275
30.2 EasyDMA...........................................................................................................................275
30.3 Resolving a resolvable address........................................................................................275
30.4 Use case example for chaining RADIO packet reception with address resolution using
AAR.......................................................................................................................................276
30.5 IRK data structure............................................................................................................. 276
30.6 Registers........................................................................................................................... 277
30.7 Electrical specification....................................................................................................... 279
31 SPIM — Serial peripheral interface master with EasyDMA............................280
31.1
31.2
31.3
31.4
31.5
31.6
31.7
Shared resources.............................................................................................................. 280
EasyDMA...........................................................................................................................281
SPI master transaction sequence..................................................................................... 282
Low power.........................................................................................................................283
Master mode pin configuration......................................................................................... 283
Registers........................................................................................................................... 284
Electrical specification....................................................................................................... 289
Page 4
Contents
32 SPIS — Serial peripheral interface slave with EasyDMA...............................291
32.1
32.2
32.3
32.4
32.5
32.6
Shared resources.............................................................................................................. 291
EasyDMA...........................................................................................................................291
SPI slave operation...........................................................................................................292
Pin configuration............................................................................................................... 293
Registers........................................................................................................................... 294
Electrical specification....................................................................................................... 302
2
33 TWIM — I C compatible two-wire interface master with EasyDMA...............304
33.1
33.2
33.3
33.4
33.5
33.6
33.7
33.8
33.9
Shared resources.............................................................................................................. 305
EasyDMA...........................................................................................................................305
Master write sequence......................................................................................................306
Master read sequence...................................................................................................... 307
Master repeated start sequence....................................................................................... 308
Low power.........................................................................................................................309
Master mode pin configuration......................................................................................... 309
Registers........................................................................................................................... 309
Electrical specification....................................................................................................... 316
2
34 TWIS — I C compatible two-wire interface slave with EasyDMA.................. 318
34.1 Shared resources.............................................................................................................. 320
34.2 EasyDMA...........................................................................................................................320
34.3 TWI slave responding to a read command.......................................................................320
34.4 TWI slave responding to a write command...................................................................... 321
34.5 Master repeated start sequence....................................................................................... 322
34.6 Terminating an ongoing TWI transaction..........................................................................323
34.7 Low power.........................................................................................................................323
34.8 Slave mode pin configuration........................................................................................... 323
34.9 Registers........................................................................................................................... 324
34.10 Electrical specification..................................................................................................... 330
35 UARTE — Universal asynchronous receiver/transmitter with EasyDMA.... 332
35.1 Shared resources.............................................................................................................. 332
35.2 EasyDMA...........................................................................................................................332
35.3 Transmission..................................................................................................................... 333
35.4 Reception.......................................................................................................................... 333
35.5 Error conditions................................................................................................................. 335
35.6 Using the UARTE without flow control............................................................................. 335
35.7 Parity configuration............................................................................................................335
35.8 Low power.........................................................................................................................335
35.9 Pin configuration............................................................................................................... 336
35.10 Registers......................................................................................................................... 336
35.11 Electrical specification..................................................................................................... 344
36 QDEC — Quadrature decoder.......................................................................... 346
36.1
36.2
36.3
36.4
36.5
36.6
36.7
36.8
Sampling and decoding.................................................................................................... 346
LED output........................................................................................................................ 347
Debounce filters................................................................................................................ 347
Accumulators.....................................................................................................................348
Output/input pins............................................................................................................... 348
Pin configuration............................................................................................................... 348
Registers........................................................................................................................... 349
Electrical specification....................................................................................................... 355
37 SAADC — Successive approximation analog-to-digital converter............... 356
37.1
37.2
37.3
37.4
37.5
37.6
37.7
Shared resources.............................................................................................................. 356
Overview............................................................................................................................356
Digital output..................................................................................................................... 357
Analog inputs and channels..............................................................................................358
Operation modes...............................................................................................................358
EasyDMA...........................................................................................................................360
Resistor ladder.................................................................................................................. 361
Page 5
Contents
37.8 Reference.......................................................................................................................... 362
37.9 Acquisition time................................................................................................................. 362
37.10 Limits event monitoring................................................................................................... 363
37.11 Registers......................................................................................................................... 364
37.12 Electrical specification..................................................................................................... 388
37.13 Performance factors........................................................................................................ 390
38 COMP — Comparator........................................................................................391
38.1
38.2
38.3
38.4
38.5
38.6
Shared resources.............................................................................................................. 392
Differential mode............................................................................................................... 392
Single-ended mode........................................................................................................... 393
Pin configuration............................................................................................................... 395
Registers........................................................................................................................... 395
Electrical specification....................................................................................................... 400
39 LPCOMP — Low power comparator................................................................402
39.1
39.2
39.3
39.4
Shared resources.............................................................................................................. 403
Pin configuration............................................................................................................... 403
Registers........................................................................................................................... 404
Electrical specification....................................................................................................... 408
40 WDT — Watchdog timer................................................................................... 409
40.1
40.2
40.3
40.4
40.5
Reload criteria................................................................................................................... 409
Temporarily pausing the watchdog................................................................................... 409
Watchdog reset................................................................................................................. 409
Registers........................................................................................................................... 410
Electrical specification....................................................................................................... 414
41 SWI — Software interrupts...............................................................................415
41.1 Registers........................................................................................................................... 415
42 NFCT — Near field communication tag...........................................................416
42.1 Overview............................................................................................................................416
42.2 Pin configuration............................................................................................................... 418
42.3 EasyDMA...........................................................................................................................418
42.4 Collision resolution............................................................................................................ 419
42.5 Frame timing controller..................................................................................................... 420
42.6 Frame assembler.............................................................................................................. 421
42.7 Frame disassembler..........................................................................................................422
42.8 Antenna interface.............................................................................................................. 423
42.9 NFCT antenna recommendations..................................................................................... 423
42.10 Battery protection............................................................................................................ 423
42.11 References...................................................................................................................... 424
42.12 Registers......................................................................................................................... 424
42.13 Electrical specification..................................................................................................... 435
43 PDM — Pulse density modulation interface................................................... 436
2
43.1
43.2
43.3
43.4
43.5
43.6
43.7
43.8
Master clock generator..................................................................................................... 436
Module operation.............................................................................................................. 436
Decimation filter................................................................................................................ 437
EasyDMA...........................................................................................................................437
Hardware example............................................................................................................ 438
Pin configuration............................................................................................................... 438
Registers........................................................................................................................... 439
Electrical specification....................................................................................................... 443
44 I S — Inter-IC sound interface......................................................................... 445
44.1
44.2
44.3
44.4
44.5
44.6
44.7
Mode..................................................................................................................................445
Transmitting and receiving................................................................................................ 445
Left right clock (LRCK)..................................................................................................... 446
Serial clock (SCK).............................................................................................................446
Master clock (MCK).......................................................................................................... 447
Width, alignment and format.............................................................................................447
EasyDMA...........................................................................................................................449
Page 6
Contents
44.8 Module operation.............................................................................................................. 451
44.9 Pin configuration............................................................................................................... 452
44.10 Registers......................................................................................................................... 453
44.11 Electrical specification..................................................................................................... 460
45 MWU — Memory watch unit.............................................................................461
45.1 Registers........................................................................................................................... 461
46 EGU — Event generator unit............................................................................488
46.1 Registers........................................................................................................................... 488
46.2 Electrical specification....................................................................................................... 494
47 PWM — Pulse width modulation..................................................................... 495
47.1
47.2
47.3
47.4
47.5
47.6
Wave counter.................................................................................................................... 495
Decoder with EasyDMA.................................................................................................... 498
Limitations......................................................................................................................... 503
Pin configuration............................................................................................................... 503
Registers........................................................................................................................... 504
Electrical specification....................................................................................................... 512
48 SPI — Serial peripheral interface master........................................................513
48.1 Functional description....................................................................................................... 513
48.2 Registers........................................................................................................................... 516
48.3 Electrical specification....................................................................................................... 519
2
49 TWI — I C compatible two-wire interface....................................................... 521
49.1
49.2
49.3
49.4
49.5
49.6
49.7
49.8
49.9
Functional description....................................................................................................... 521
Master mode pin configuration......................................................................................... 521
Shared resources.............................................................................................................. 522
Master write sequence......................................................................................................522
Master read sequence...................................................................................................... 523
Master repeated start sequence....................................................................................... 524
Low power.........................................................................................................................525
Registers........................................................................................................................... 525
Electrical specification....................................................................................................... 529
50 UART — Universal asynchronous receiver/transmitter................................. 531
50.1 Functional description....................................................................................................... 531
50.2 Pin configuration............................................................................................................... 531
50.3 Shared resources.............................................................................................................. 532
50.4 Transmission..................................................................................................................... 532
50.5 Reception.......................................................................................................................... 532
50.6 Suspending the UART...................................................................................................... 533
50.7 Error conditions................................................................................................................. 533
50.8 Using the UART without flow control................................................................................534
50.9 Parity configuration............................................................................................................534
50.10 Registers......................................................................................................................... 534
50.11 Electrical specification..................................................................................................... 539
51 Mechanical specifications................................................................................ 540
51.1 QFN48 6 x 6 mm package............................................................................................... 540
51.2 WLCSP package............................................................................................................... 541
52 Ordering information.........................................................................................542
52.1
52.2
52.3
52.4
52.5
IC marking.........................................................................................................................542
Box labels..........................................................................................................................542
Order code........................................................................................................................ 543
Code ranges and values...................................................................................................543
Product options................................................................................................................. 544
53 Reference circuitry............................................................................................ 545
53.1 Schematic QFAA and QFAB QFN48 with internal LDO setup......................................... 545
53.2 Schematic QFAA and QFAB QFN48 with DC/DC regulator setup................................... 546
53.3 Schematic QFAA and QFAB QFN48 with DC/DC regulator and NFC setup.................... 547
53.4 Schematic CIAA WLCSP with internal LDO setup........................................................... 548
53.5 Schematic CIAA WLCSP with DC/DC regulator setup..................................................... 549
Page 7
Contents
53.6 Schematic CIAA WLCSP with DC/DC regulator and NFC setup......................................550
53.7 PCB guidelines..................................................................................................................550
53.8 PCB layout example......................................................................................................... 551
54 Liability disclaimer............................................................................................ 553
54.1 Life support applications................................................................................................... 553
Page 8
1 Revision history
1 Revision history
Date
July 2016
Version
1.1
Description
Added documentation for nRF52832 CIAA WLCSP.
Added or updated the following content:
Cover: Added Key features.
Pin assignments on page 13: Added WLCSP
ball assignments. Moved GPIO usage restrictions
here from GPIO/Notes on usage and restrictions.
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Absolute maximum ratings on page 19: Added
environmental information for WLCSP to the
table.
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Memory on page 23: Added QFAB and CIAA
information to the table.
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FICR — Factory information configuration registers
on page 43: Updated INFO.PACKAGE register.
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UICR: Updated APPROTECT register.
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Debug and trace on page 72: Updated DAP Debug access port.
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POWER — Power supply on page 78: Updated
Pin reset.
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CLOCK — Clock control on page 101: Updated
information on external 32 kHz clock support.
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GPIO — General purpose input/output on page
111: Added GPIO located near the RADIO.
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RADIO — 2.4 GHz Radio on page 204: Updated
Figure 29 and Interframe spacing.
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CCM: Updated SCRATCHPTR register.
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SPIM: Updated Master mode pin configuration.
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UARTE: Added RXDRDY and TXDRDY events.
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NFCT: Updated Electrical specifications.
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PWM — Pulse width modulation on page 495:
Updated SEQ[1].REFRESH register.
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Mechanical specifications on page 540: Added
WLCSP package.
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Ordering information on page 542: Updated
with CIAA and QFAB information.
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Reference circuitry on page 545: QFAB
information added. CIAA WLCSP schematics
added.
First release.
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February 2016
1.0
Page 9
2 About this document
2 About this document
This Product Specification is organized into chapters based on the modules and peripherals that are
available in this IC.
The peripheral descriptions are broken into separate sections that include the following information:
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A detailed functional description of the peripheral.
Register configuration for the peripheral
Electrical specification tables providing the specified limits of the chip when tested under the conditions
defined in the Recommended operating conditions on page 20
2.1 Peripheral naming and abbreviations
Every peripheral has a unique capitalized name or an abbreviation of its name, e.g. TIMER, used for
identification and reference. This name is used in chapter headings and references, and it will appear in the
ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer to identify
the peripheral.
The peripheral instance name, which is different from the peripheral name, is constructed using the
peripheral name followed by a numbered postfix, starting with 0, for example, TIMER0. A postfix is normally
only used if a peripheral can be instantiated more than once. The peripheral instance name is also used in
the CMSIS to identify the peripheral instance.
2.2 Register tables
Individual registers are described using register tables. These tables are built up of two sections. The first
three colored rows describe the position and size of the different fields in the register. The following rows
describe the fields in more detail.
2.2.1 Fields and values
The Id (Field Id) row specifies the bits that belong to the different fields in the register.
A blank space means that the field is reserved and that it is read as undefined, and must be written as ‘0’ to
secure forward compatibility. If a register is divided into more than one field, a unique field name is specified
for each field in the Field column.
If a field has enumerated values, then every value will be identified with a unique value id in the Value Id
column. Single-bit bit fields may, however, omit the Value Id when values can be substituted with a Boolean
type enumerator range, for example, True/False, Disable/Enable, On/Off, and so on.
Values are usually provided as decimal or hexadecimal. Hex values have a '0x' prefix, decimal values have
no prefix.
The Value column can be populated in the following ways:
•
•
•
Individual enumerated values, for example, 1, 3, 9.
Range of values, e.g. [0..4], that is, all values from and including 0 and 4.
Implicit values. If no values are indicated in the Value column, all bit combinations are supported, or
alternatively the field’s translation and limitations are described in the text instead.
If two or more fields are closely related, the Value Id, Value, and Description may be omitted for all but the
first field. Subsequent fields will indicate inheritance with “..”.
When an item is marked with the word Deprecated, it means this is an attribute applied to a feature to
indicate that it should not be used for new designs.
Page 10
2 About this document
2.3 Registers
Table 1: Register Overview
Register
Offset
Description
DUMMY
0x514
Example of a register controlling a dummy feature
2.3.1 DUMMY
Address offset: 0x514
Example of a register controlling a dummy feature
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D
Reset 0x00050002
Id
RW Field
A
RW FIELD_A
B
C
D
0
C C C
B
A A
0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Disabled
0
The example feature is disabled
NormalMode
1
The example feature is enabled in normal mode
ExtendedMode
2
The example feature is enabled along with extra functionality
Disabled
0
The override feature is disabled
Enabled
1
The override feature is enabled
ValidRange
[2..7]
Example of a field with several enumerated values
RW FIELD_B
Example of a deprecated field
RW FIELD_C
Example of a field with a valid range of values
Example of allowed values for this field
RW FIELD_D
Example of a field with no restriction on the values
Page 11
Deprecated
3 Block diagram
3 Block diagram
This block diagram illustrates the overall system. Arrows with white heads indicate signals that share
physical pins with other signals.
RAM7
GPIO
P0
(P0.0 – P0.31)
slave
RAM6
slave
RAM5
slave
slave
RAM4
slave
RAM3
slave
RAM2
slave
TPIU
RAM1
slave
TP
SWCLK
RAM0
slave
nRF52832
SW-DP
slave
slave
slave
master
AHB-AP
AHB TO APB
BRIDGE
FICR
UICR
ETM
slave
AHB
Multi-Layer
CTRL-AP
slave
SWDIO
I-Cache
CPU
Flash
ARM
CORTEX-M4
NVIC
nRESET
NVMC
SysTick
RNG
POWER
RTC [0..2]
TIMER [0..4]
WDT
TEMP
PPI
XC1
XC2
XL1
ECB
CLOCK
master
EasyDMA
master
EasyDMA
XL2
CCM
ANT2
RADIO
EasyDMA
NFC2
NFC1
NFCT
EasyDMA
master
ma s
master
SPIM [0.2]
QDEC
OUT0 – OUT3
PWM[0..3]
master
SDA
SCL
SDA
EasyDMA
RTS
CTS
TXD
RXD
master
master
EasyDMA
CSN
I2S
SPIS [0..2]
MISO
MOSI
SCK
EasyDMA
CLK
DIN
TWIM [0..1]
master
SCL
EasyDMA
UARTE [0]
EasyDMA
MCK
LRCK
SCL
SDOUT
SDIN
master
SAADC
LED
A
B
EasyDMA
TWIS [0.1n]
LPCOMP
MOSI
MISO
master
COMP
EasyDMA
AAR
EasyDMA
master
GPIOTE
AIN0 – AIN7
ter
SCK
APB0
ANT1
master
PDM
EasyDMA
master
Figure 1: Block diagram
Page 12
master
EasyDMA
4 Pin assignments
4 Pin assignments
Here we cover the pin assignments for each variant of the chip.
4.1 QFN48 pin assignments
P0.25
P0.26
P0.27
P0.28/AIN4
P0.29/AIN5
P0.30/AIN6
P0.31/AIN7
NC
VSS
DEC4
DCC
VDD
37
38
39
40
41
42
43
44
46
45
48
47
DEC1
P0.00/XL1
P0.01/XL2
P0.02/AIN0
P0.03/AIN1
P0.04/AIN2
P0.05/AIN3
P0.06
P0.07
P0.08
NFC1/P0.09
NFC2/P0.10
1
36
2
35
3
34
4
33
5
32
nRF5102
N52832
QFN48
QFN48
6
7
8
31
30
29
9
28
10
27
exposed die pad
11
26
12
25
VDD
XC2
XC1
DEC3
DEC2
VSS
ANT
P0.24
P0.23
P0.22
SWDIO
SWDCLK
24
23
22
21
20
19
18
17
16
15
14
13
P0.21/nRESET
P0.20/TRACECLK
P0.19
P0.18/TRACEDATA[0]/SWO
P0.17
P0.16/TRACEDATA[1]
P0.15/TRACEDATA[2]
P0.14/TRACEDATA[3]
P0.13
P0.12
P0.11
VDD
Figure 2: QFN48 pin assignments, top view
Table 2: QFN48 pin assignments
Pin
Name
Type
Description
1
DEC1
Power
0.9 V regulator digital supply decoupling
2
P0.00
Digital I/O
General purpose I/O
XL1
Analog input
Connection for 32.768 kHz crystal (LFXO)
P0.01
Digital I/O
General purpose I/O
XL2
Analog input
Connection for 32.768 kHz crystal (LFXO)
P0.02
Digital I/O
General purpose I/O
AIN0
Analog input
SAADC/COMP/LPCOMP input
P0.03
Digital I/O
General purpose I/O
AIN1
Analog input
SAADC/COMP/LPCOMP input
P0.04
Digital I/O
General purpose I/O
AIN2
Analog input
SAADC/COMP/LPCOMP input
P0.05
Digital I/O
General purpose I/O
Left Side of chip
3
4
5
6
7
AIN3
Analog input
SAADC/COMP/LPCOMP input
8
P0.06
Digital I/O
General purpose I/O
9
P0.07
Digital I/O
General purpose I/O
Page 13
4 Pin assignments
Pin
Name
Type
Description
10
P0.08
Digital I/O
General purpose I/O
11
NFC1
NFC input
NFC antenna connection
P0.09
Digital I/O
General purpose I/O1
NFC2
NFC input
NFC antenna connection
P0.10
Digital I/O
General purpose I/O1
13
VDD
Power
Power supply
14
P0.11
Digital I/O
General purpose I/O
15
P0.12
Digital I/O
General purpose I/O
16
P0.13
Digital I/O
General purpose I/O
17
P0.14
Digital I/O
General purpose I/O
12
Bottom side of chip
TRACEDATA[3]
18
P0.15
Trace port output
Digital I/O
TRACEDATA[2]
19
P0.16
General purpose I/O
Trace port output
Digital I/O
TRACEDATA[1]
General purpose I/O
Trace port output
20
P0.17
Digital I/O
General purpose I/O
21
P0.18
Digital I/O
General purpose I/O
TRACEDATA[0] / SWO
Single wire output
Trace port output
22
P0.19
Digital I/O
General purpose I/O
23
P0.20
Digital I/O
General purpose I/O
TRACECLK
24
P0.21
Trace port clock output
Digital I/O
nRESET
General purpose I/O
Configurable as pin reset
Right Side of chip
25
SWDCLK
Digital input
Serial wire debug clock input for debug
26
SWDIO
Digital I/O
27
P0.22
Digital I/O
General purpose I/O2
28
P0.23
Digital I/O
General purpose I/O2
29
P0.24
Digital I/O
General purpose I/O2
30
ANT
RF
Single-ended radio antenna connection
31
VSS
Power
Ground (Radio supply)
32
DEC2
Power
1.3 V regulator supply decoupling (Radio
33
DEC3
Power
Power supply decoupling
34
XC1
Analog input
Connection for 32 MHz crystal
35
XC2
Analog input
Connection for 32 MHz crystal
36
VDD
Power
Power supply
37
P0.25
Digital I/O
General purpose I/O2
38
P0.26
Digital I/O
General purpose I/O2
39
P0.27
Digital I/O
General purpose I/O2
40
P0.28
Digital I/O
General purpose I/O2
AIN4
Analog input
SAADC/COMP/LPCOMP input
P0.29
Digital I/O
General purpose I/O2
AIN5
Analog input
SAADC/COMP/LPCOMP input
P0.30
Digital I/O
General purpose I/O2
AIN6
Analog input
SAADC/COMP/LPCOMP input
P0.31
Digital I/O
General purpose I/O pin2
AIN7
Analog input
SAADC/COMP/LPCOMP input
and programming
Serial wire debug I/O for debug and
programming
supply)
Top side of chip
41
42
43
Page 14
4 Pin assignments
Pin
Name
44
NC
Type
Description
45
VSS
Power
Ground
46
DEC4
Power
1.3 V regulator supply decoupling
No connect
Leave unconnected
Input from DC/DC regulator
Output from 1.3 V LDO
47
DCC
Power
DC/DC regulator output
48
VDD
Power
Power supply
VSS
Power
Ground pad
Bottom of chip
Die pad
Exposed die pad must be connected
to ground (VSS) for proper device
operation.
4.2 WLCSP ball assignments
1
2
3
4
5
6
7
A
B
C
D
E
F
N52832
CIAAHP
YYWWLL
G
H
Figure 3: WLCSP ball assignments, top view
Table 3: WLCSP ball assignments
Ball
Name
A1
XC2
Analog input
Description
Connection for 32 MHz crystal
A2
DEC2
Power
1.3 V regulator supply decoupling (Radio
A3
P0.28
Digital I/O
General purpose I/O3
AIN4
Analog input
SAADC/COMP/LPCOMP input
P0.29
Digital I/O
General purpose I/O3
AIN5
Analog input
SAADC/COMP/LPCOMP input
P0.30
Digital I/O
General purpose I/O3
AIN6
Analog input
SAADC/COMP/LPCOMP input
DEC4
Power
1.3 V regulator supply decoupling
supply)
A4
A5
A6
Input from DC/DC converter. Output
from 1.3 V LDO
A7
VDD
Power
Power supply
B2
XC1
Analog input
Connection for 32 MHz crystal
B3
P0.25
Digital I/O
General purpose I/O3
1
2
See GPIO located near the radio on page 17 for more information.
See NFC antenna pins on page 17 for more information.
Page 15
4 Pin assignments
Ball
Name
B4
P0.27
Digital I/O
Description
General purpose I/O3
B5
P0.31
Digital I/O
General purpose I/O3
AIN7
Analog input
SAADC/COMP/LPCOMP input
B6
DCC
Power
DC/DC converter output
B7
DEC1
Power
0.9 V regulator digital supply decoupling
C2
DEC3
Power
Power supply decoupling
C3
NC
N/A
Not connected
C4
VSS
Power
Ground
C5
VSS
Power
Ground
C6
P0.02
Digital I/O
General purpose I/O
AIN0
Analog input
SAADC/COMP/LPCOMP input
P0.01
Digital I/O
General purpose I/O
C7
XL2
Analog input
Connection for 32.768 kHz crystal (LFXO)
D1
ANT
RF
Single-ended radio antenna connection
D2
VSS_PA
Power
Ground (Radio supply)
D3
P0.26
Digital I/O
General purpose I/O 3
D6
P0.03
Digital I/O
General purpose I/O
AIN1
Analog input
SAADC/COMP/LPCOMP input
P0.00
Digital I/O
General purpose I/O
D7
XL1
Analog input
Connection for 32.768 kHz crystal (LFXO)
E1
P0.24
Digital I/O
General purpose I/O3
E2
P0.23
Digital I/O
General purpose I/O3
E3
VSS
Power
Ground
E6
P0.04
Digital I/O
General purpose I/O
AIN2
Analog input
SAADC/COMP/LPCOMP input
P0.05
Digital I/O
General purpose I/O
E7
AIN3
Analog input
SAADC/COMP/LPCOMP input
F1
SWDCLK
Digital input
Serial wire debug clock input for debug
F2
P0.22
Digital I/O
General purpose I/O3
F3
P0.19
Digital I/O
General purpose I/O
F4
P0.11
Digital I/O
General purpose I/O
F5
VSS
Power
Ground
F6
P0.07
Digital I/O
General purpose I/O
F7
P0.06
Digital I/O
General purpose I/O
G1
SWDIO
Digital I/O
Serial wire debug I/O for debug and
G2
P0.20
Digital I/O
and programming
programming
TRACECLK
General purpose I/O
Trace port clock output
G3
P0.17
Digital I/O
General purpose I/O
G4
P0.13
Digital I/O
General purpose I/O
G5
NFC2
NFC input
NFC antenna connection
P0.10
Digital I/O
General purpose I/O4
NFC1
NFC input
NFC antenna connection
P0.09
Digital I/O
General purpose I/O4
G7
P0.08
Digital I/O
General purpose I/O
H1
P0.21
Digital I/O
General purpose I/O
G6
nRESET
H2
P0.18
Configurable as pin reset
Digital I/O
TRACEDATA[0]
H3
P0.16
Trace port output
Digital I/O
TRACEDATA[1]
H4
P0.15
General purpose I/O
General purpose I/O
Trace port output
Digital I/O
Page 16
General purpose I/O
4 Pin assignments
Ball
Name
Description
TRACEDATA[2]
H5
P0.14
Trace port output
Digital I/O
TRACEDATA[3]
General purpose I/O
Trace port output
H6
P0.12
Digital I/O
General purpose I/O
H7
VDD
Power
Power supply
4.3 GPIO usage restrictions
4.3.1 GPIO located near the radio
Radio performance parameters, such as sensitivity, may be affected by high frequency digital I/O with large
sink/source current close to the Radio power supply and antenna pins.
Table 4: GPIO recommended usage for QFN48 package on page 17 and Table 5: GPIO recommended
usage for WLCSP package on page 17 identify some GPIO that have recommended usage guidelines to
maximize radio performance in an application.
Table 4: GPIO recommended usage for QFN48 package
Pin
27
28
29
37
38
39
40
41
42
43
GPIO
P0.22
P0.23
P0.24
P0.25
P0.26
P0.27
P0.28
P0.29
P0.30
P0.31
Recommended usage
Low drive, low frequency I/O only.
Table 5: GPIO recommended usage for WLCSP package
Pin
F2
E2
E1
B3
D3
B4
A3
A4
A5
B5
GPIO
P0.22
P0.23
P0.24
P0.25
P0.26
P0.27
P0.28
P0.29
P0.30
P0.31
Recommended usage
Low drive, low frequency I/O only.
4.3.2 NFC antenna pins
Two physical pins can be configured either as NFC antenna pins (factory default), or as GPIOs, as shown
below.
Table 6: GPIO pins used by NFC
NFC pad name
NFC1
NFC2
GPIO
P0.09
P0.10
When configured as NFC antenna pins, the GPIOs on those pins will automatically be set to DISABLE state
and a protection circuit will be enabled preventing the chip from being damaged in the presence of a strong
NFC field. The protection circuit will short the two pins together if voltage difference exceeds approximately 2
V.
3
4
See GPIO located near the radio on page 17 for more information.
See NFC antenna pins on page 17 for more information.
Page 17
4 Pin assignments
For information on how to configure these pins as normal GPIOs, see NFCT — Near field communication tag
on page 416 and UICR — User information configuration registers on page 54. Note that the device will
not be protected against strong NFC field damage if the pins are configured as GPIO and an NFC antenna
is connected to the device. The pins will always be configured as NFC pins during power-on reset until the
configuration is set according to the UICR register.
These two pins will have some limitations when configured as GPIO. The pin capacitance will be higher on
these pins, and there is some current leakage between the two pins if they are driven to different logical
values. To avoid leakage between the pins when configured as GPIO, these GPIOs should always be at the
same logical value whenever entering one of the device power saving modes. See Electrical specification.
Page 18
5 Absolute maximum ratings
5 Absolute maximum ratings
Maximum ratings are the extreme limits to which the chip can be exposed for a limited amount of time
without permanently damaging it. Exposure to absolute maximum ratings for prolonged periods of time may
affect the reliability of the device.
Table 7: Absolute maximum ratings
Supply voltages
VDD
VSS
I/O pin voltage
VI/O, VDD ≤3.6 V
VI/O, VDD >3.6 V
NFC antenna pin current
INFC1/2
Radio
RF input level
Environmental QFN48, 6×6 mm package
Storage temperature
MSL (moisture sensitivity level)
ESD HBM (human body model)
ESD CDM (charged device model)
Environmental WLCSP, 3.0×3.2 mm package
Storage temperature
MSL
ESD HBM
ESD CDM
Flash memory
Endurance
Retention
Min.
Max.
Unit
-0.3
+3.9
0
V
V
-0.3
-0.3
VDD + 0.3 V
3.9 V
V
V
80
mA
10
dBm
+125
2
4
1000
°C
+125
1
2
500
°C
-40
-40
10 000
10 years at 40°C
Page 19
kV
V
kV
V
Write/erase cycles
6 Recommended operating conditions
6 Recommended operating conditions
The operating conditions are the physical parameters that the chip can operate within.
Table 8: Recommended operating conditions
Symbol
VDD
tR_VDD
TA
Parameter
Supply voltage, independent of DCDC enable
Supply rise time (0 V to 1.7 V)
Operating temperature
Notes
Min.
1.7
Nom.
3.0
-40
25
Max.
3.6
60
85
Units
V
ms
°C
Important: The on-chip power-on reset circuitry may not function properly for rise times longer than
the specified maximum.
Page 20
7 CPU
7 CPU
The ARM® Cortex®-M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb®-2
technology) that implements a superset of 16 and 32-bit instructions to maximize code density and
performance.
This processor implements several features that enable energy-efficient arithmetic and high-performance
signal processing including:
•
•
•
•
•
Digital signal processing (DSP) instructions
Single-cycle multiply and accumulate (MAC) instructions
Hardware divide
8 and 16-bit single instruction multiple data (SIMD) instructions
Single-precision floating-point unit (FPU)
The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the
ARM Cortex processor series is implemented and available for the M4 CPU.
Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling
events at configurable priority levels via the Nested Vectored Interrupt Controller (NVIC).
Executing code from flash will have a wait state penalty on the nRF52 Series. An instruction cache can be
enabled to minimize flash wait states when fetching instructions. For more information on cache, see Cache
on page 30. The section Electrical specification on page 21 shows CPU performance parameters
including wait states in different modes, CPU current and efficiency, and processing power and efficiency
based on the CoreMark® benchmark.
7.1 Floating point interrupt
The floating point unit (FPU) may generate exceptions when used due to e.g. overflow or underflow. These
exceptions will trigger the FPU interrupt (see Instantiation on page 24). To clear the IRQ line when an
exception has occurred, the relevant exception bit within the FPSCR register needs to be cleared. For more
information about the FPSCR or other FPU registers, see Cortex-M4 Devices Generic User Guide.
7.2 Electrical specification
7.2.1 CPU performance
The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is
executing the CoreMark™ benchmark. It includes power regulator and clock base currents. All other blocks
are IDLE.
Symbol
Description
Min.
WFLASH
CPU wait states, running from flash, cache disabled
0
Typ.
Max.
2
Units
WFLASHCACHE
CPU wait states, running from flash, cache enabled
0
3
WRAM
CPU wait states, running from RAM
IDDFLASHCACHE
CPU current, running from flash, cache enabled, LDO
7.4
mA
IDDFLASHCACHEDCDC
CPU current, running from flash, cache enabled, DCDC 3V
3.7
mA
IDDFLASH
CPU current, running from flash, cache disabled, LDO
8.0
mA
IDDFLASHDCDC
CPU current, running from flash, cache disabled, DCDC 3V
3.9
mA
IDDRAM
CPU current, running from RAM, LDO
6.7
mA
IDDRAMDCDC
CPU current, running from RAM, DCDC 3V
3.3
mA
IDDFLASH/MHz
CPU efficiency, running from flash, cache enabled, LDO
125
µA/
IDDFLASHDCDC/MHz
CPU efficiency, running from flash, cache enabled, DCDC 3V
58
0
MHz
µA/
MHz
Page 21
7 CPU
Symbol
Description
CMFLASH
CoreMark5, running from flash, cache enabled
Min.
Typ.
215
Max.
Units
CoreMark
CMFLASH/MHz
CoreMark per MHz, running from flash, cache enabled
3.36
CoreMark/
CMFLASH/mA
CoreMark per mA, running from flash, cache enabled, DCDC 3V
58
MHz
CoreMark/
mA
7.3 CPU and support module configuration
The ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on the
device.
Option / Module
Core options
NVIC
PRIORITIES
WIC
Endianness
Bit Banding
DWT
SysTick
Modules
MPU
FPU
DAP
ETM
ITM
TPIU
ETB
FPB
HTM
5
Description
Implemented
Nested Vector Interrupt Controller
Priority bits
Wakeup Interrupt Controller
Memory system endianness
Bit banded memory
Data Watchpoint and Trace
System tick timer
37 vectors
3
NO
Little endian
NO
YES
YES
Memory protection unit
Floating point unit
Debug Access Port
Embedded Trace Macrocell
Instrumentation Trace Macrocell
Trace Port Interface Unit
Embedded Trace Buffer
Flash Patch and Breakpoint Unit
AHB Trace Macrocell
YES
YES
YES
YES
YES
YES
NO
YES
NO
Using IAR v6.50.1.4452 with flags --endian=little --cpu=Cortex-M4 -e --fpu=VFPv4_sp –Ohs --no_size_constraints
Page 22
8 Memory
8 Memory
The nRF52832 contains flash and RAM that can be used for code and data storage.
The amount of RAM and flash will vary depending on variant, see Table 9: Memory variants on page 23.
Table 9: Memory variants
Device name
nRF52832-QFAA
nRF52832-QFAB
nRF52832-CIAA
RAM
64 kB
32 kB
64 kB
Flash
512 kB
256 kB
512 kB
Comments
The CPU and the EasyDMA can access memory via the AHB multilayer interconnect. The CPU is also able
to access peripherals via the AHB multilayer interconnect, as illustrated in Figure 4: Memory layout on page
23.
Data RAM
System
APB
ICODE
AHB
DCODE
AHB multilayer interconnect
Section 0
0x0080 F000
0x2000 E000
0x0080 E000
RAM6
AHB slave
Section 1
0x2000 D000
0x0080 D000
Section 0
0x2000 C000
0x0080 C000
RAM5
AHB slave
Section 1
0x2000 B000
0x0080 B000
Section 0
0x2000 A000
0x0080 A000
RAM4
AHB slave
Section 1
0x2000 9000
0x0080 9000
Section 0
0x2000 8000
0x0080 8000
RAM3
AHB slave
Section 1
0x2000 7000
0x0080 7000
0x2000 6000
0x0080 6000
RAM2
AHB slave
Section 1
0x2000 5000
0x0080 5000
Section 0
0x2000 4000
0x0080 4000
RAM1
AHB slave
Section 1
0x2000 3000
0x0080 3000
Section 0
0x2000 2000
0x0080 2000
RAM0
AHB slave
Section 1
0x2100 1000
0x0080 1000
Section 0
0x2000 0000
0x0080 0000
I-Cache
System bus
ICODE
DCODE
EasyDMA
DMA bus
DMA bus
EasyDMA
Peripheral
Code RAM
ICODE/DCODE
0x2000 F000
Section 0
Page 127
NVMC
ARM Cortex-M4
Peripheral
Section 1
AHB
slave
CPU
RAM7
AHB slave
AHB
slave
AHB2APB
Flash
ICODE/DCODE
0x0007 F000
Page 3..126
0x0000 3000
Page 2
Page 1
Page 0
0x0000 2000
0x0000 1000
Block 7
0x0000 0E00
Block 2..6
0x0000 0400
Block 1
0x0000 0200
Block 0
0x0000 0000
Figure 4: Memory layout
See AHB multilayer on page 26 and EasyDMA on page 27 for more information about the AHB
multilayer interconnect and the EasyDMA.
The same physical RAM is mapped to both the Data RAM region and the Code RAM region. It is up to the
application to partition the RAM within these regions so that one does not corrupt the other.
8.1 RAM - Random access memory
The RAM interface is divided into multiple RAM AHB slaves.
Each RAM AHB slave is connected to two 4-kilobyte RAM sections, see Section 0 and Section 1 in Figure 4:
Memory layout on page 23.
Each of the RAM sections have separate power control for System ON and System OFF mode operation,
which is configured via RAM register (see the POWER — Power supply on page 78).
Page 23
8 Memory
8.2 Flash - Non-volatile memory
The Flash can be read an unlimited number of times by the CPU, but it has restrictions on the number of
times it can be written and erased and also on how it can be written.
Writing to Flash is managed by the Non-volatile memory controller (NVMC), see NVMC — Non-volatile
memory controller on page 29.
The Flash is divided into multiple pages that can be accessed by the CPU via both the ICODE and DCODE
buses as shown in, Figure 4: Memory layout on page 23. Each page is divided into 8 blocks.
8.3 Memory map
The complete memory map is shown in Figure 5: Memory map on page 24. As described in Memory on
page 23, Code RAM and the Data RAM are the same physical RAM.
nRF52832 Address Map
0xE010 0000
0xE0FF 0000
0xE004 2000
0xE004 1000
0xE004 0000
ROM Table
External PPB
ETM
TPIU
0xE004 0000
0xE000 F000
0xE000 E000
0xE000 3000
0xE000 2000
0xE000 1000
0xE000 0000
Reserved
SCS
Reserved
FPB
DWT
ITM
0x2000 0000
0x1000 1000
0x1000 0000
0xFFFF FFFF
Cortex M4 System Address Map
Private Peripheral Bus - External
Private Peripheral Bus - Internal
0x6000 0000
External device
1.0GB
Reserved
AHB peripherals
Reserved
0xA000 0000
0x5000 0000
APB peripherals
Reserved
UICR
Reserved
FICR
External RAM
1.0GB
Peripheral
0.5GB
SRAM
0.5GB
Reserved
0x0081 0000
nRF52832 Address Map
System
Code RAM
0x0080 0000
0x4000 0000
0x4000 0000
Reserved
Reserved
0x0008 0000
Data RAM
Flash
Code
0.5GB
0x2001 0000
0x2000 0000
0x0000 0000
Figure 5: Memory map
8.4 Instantiation
Table 10: Instantiation table
ID
Base Address
Peripheral
Instance
Description
0
0x40000000
CLOCK
CLOCK
Clock control
0
0x40000000
POWER
POWER
Power control
0
0x40000000
BPROT
BPROT
Block Protect
1
0x40001000
RADIO
RADIO
2.4 GHz radio
2
0x40002000
UARTE
UARTE0
Universal Asynchronous Receiver/Transmitter with EasyDMA
2
0x40002000
UART
UART0
Universal Asynchronous Receiver/Transmitter
3
0x40003000
SPIM
SPIM0
SPI master 0
3
0x40003000
SPIS
SPIS0
SPI slave 0
3
0x40003000
TWIM
TWIM0
Two-wire interface master 0
3
0x40003000
TWI
TWI0
Two-wire interface master 0
Deprecated
3
0x40003000
SPI
SPI0
SPI master 0
Deprecated
Page 24
Deprecated
8 Memory
ID
Base Address
Peripheral
Instance
Description
3
0x40003000
TWIS
TWIS0
Two-wire interface slave 0
4
0x40004000
SPIM
SPIM1
SPI master 1
4
0x40004000
TWI
TWI1
Two-wire interface master 1
4
0x40004000
SPIS
SPIS1
SPI slave 1
4
0x40004000
TWIS
TWIS1
Two-wire interface slave 1
4
0x40004000
TWIM
TWIM1
Two-wire interface master 1
4
0x40004000
SPI
SPI1
SPI master 1
5
0x40005000
NFCT
NFCT
Near Field Communication Tag
6
0x40006000
GPIOTE
GPIOTE
GPIO Tasks and Events
7
0x40007000
SAADC
SAADC
Analog to digital converter
8
0x40008000
TIMER
TIMER0
Timer 0
9
0x40009000
TIMER
TIMER1
Timer 1
10
0x4000A000
TIMER
TIMER2
Timer 2
11
0x4000B000
RTC
RTC0
Real-time counter 0
12
0x4000C000
TEMP
TEMP
Temperature sensor
13
0x4000D000
RNG
RNG
Random number generator
14
0x4000E000
ECB
ECB
AES Electronic Code Book (ECB) mode block encryption
15
0x4000F000
CCM
CCM
AES CCM Mode Encryption
15
0x4000F000
AAR
AAR
Acelerated Address Resolver
16
0x40010000
WDT
WDT
Watchdog timer
17
0x40011000
RTC
RTC1
Real-time counter 1
18
0x40012000
QDEC
QDEC
Quadrature decoder
19
0x40013000
LPCOMP
LPCOMP
Low power comparator
19
0x40013000
COMP
COMP
General purpose comparator
20
0x40014000
SWI
SWI0
Software interrupt 0
20
0x40014000
EGU
EGU0
Event Generator Unit 0
21
0x40015000
EGU
EGU1
Event Generator Unit 1
21
0x40015000
SWI
SWI1
Software interrupt 1
22
0x40016000
SWI
SWI2
Software interrupt 2
22
0x40016000
EGU
EGU2
Event Generator Unit 2
23
0x40017000
SWI
SWI3
Software interrupt 3
23
0x40017000
EGU
EGU3
Event Generator Unit 3
24
0x40018000
EGU
EGU4
Event Generator Unit 4
24
0x40018000
SWI
SWI4
Software interrupt 4
25
0x40019000
SWI
SWI5
Software interrupt 5
25
0x40019000
EGU
EGU5
Event Generator Unit 5
26
0x4001A000
TIMER
TIMER3
Timer 3
27
0x4001B000
TIMER
TIMER4
Timer 4
28
0x4001C000
PWM
PWM0
Pulse Width Modulation Unit 0
29
0x4001D000
PDM
PDM
Pulse Density Modulation (Digital Microphone Interface)
30
0x4001E000
NVMC
NVMC
Non-Volatile Memory Controller
31
0x4001F000
PPI
PPI
Programmable Peripheral Interconnect
32
0x40020000
MWU
MWU
Memory Watch Unit
33
0x40021000
PWM
PWM1
Pulse Width Modulation Unit 1
34
0x40022000
PWM
PWM2
Pulse Width Modulation Unit 2
35
0x40023000
SPI
SPI2
SPI master 2
35
0x40023000
SPIS
SPIS2
SPI slave 2
35
0x40023000
SPIM
SPIM2
SPI master 2
36
0x40024000
RTC
RTC2
Real-time counter 2
37
0x40025000
I2S
I2S
Inter-IC Sound Interface
38
0x40026000
FPU
FPU
FPU interrupt
N/A
0x10000000
FICR
FICR
Factory Information Configuration
N/A
0x10001000
UICR
UICR
User Information Configuration
N/A
0x50000000
GPIO
GPIO
General purpose input and output
N/A
0x50000000
GPIO
P0
General purpose input and output
Page 25
Deprecated
Deprecated
Deprecated
Deprecated
9 AHB multilayer
9 AHB multilayer
The CPU and all of the EasyDMAs are AHB bus masters on the AHB multilayer, while the RAM and various
other modules are AHB slaves.
See Block diagram on page 12 for an overview of which peripherals implement EasyDMA.
The CPU has exclusive access to all AHB slaves except for the RAM that can also be accessed by the
EasyDMA.
Access rights to each of the RAM AHB slaves are resolved using the priority of the different bus masters in
the system
See AHB multilayer priorities on page 26 for information about the priority of the different AHB bus
masters in the system. It is possible for two or more bus masters to have the same priority in cases where
it is guaranteed by design that the related masters will never be able to access the same slave at the same
time.
9.1 AHB multilayer priorities
Each master connected to the AHB multilayer is assigned a priority.
Table 11: AHB bus masters
Bus master name
CPU
SPIS1
RADIO
CCM/ECB/AAR
SAADC
UARTE
SERIAL0
SERIAL2
NFCT
I2S
PDM
PWM
Priority
Highest priority
Description
Applies to SPIM1, SPIS1, TWIM1, TWIS1
Applies to SPIM0, SPIS0, TWIM0, TWIS0
Applies to SPIM2, SPIS2
I2S
PDM
Applies to PWM0, PWM1, PWM2
Lowest priority
Page 26
10 EasyDMA
10 EasyDMA
EasyDMA is an easy-to-use direct memory access module that some peripherals implement to gain direct
access to Data RAM.
The EasyDMA is an AHB bus master similar to the CPU and it is connected to the AHB multilayer
interconnect for direct access to the Data RAM. The EasyDMA is not able to access the Flash.
A peripheral can implement multiple EasyDMA instances, for example to provide a dedicated channel for
reading data from RAM into the peripheral at the same time as a second channel is dedicated for writing data
to the RAM from the peripheral. This concept is illustrated in Figure 6: EasyDMA example on page 27
RAM
AHB Multilayer
Peripheral
READER
RAM
RAM
AHB
EasyDMA
WRITER
AHB
Peripheral
Core
EasyDMA
Figure 6: EasyDMA example
An EasyDMA channel is usually exposed to the user in the form illustrated below, but some variations may
occur:
READERBUFFER_SIZE 5
WRITERBUFFER_SIZE 6
uint8_t readerBuffer[READERBUFFER_SIZE]
uint8_t writerBuffer[WRITERBUFFER_SIZE]
__at__ 0x20000000;
__at__ 0x20000005;
// Configuring the READER channel
MYPERIPHERAL->READER.MAXCNT = READERBUFFER_SIZE;
MYPERIPHERAL->READER.PTR = &readerBuffer;
// Configure the WRITER channel
MYPERIPHERAL->WRITER.MAXCNT = WRITEERBUFFER_SIZE;
MYPERIPHERAL->WRITER.PTR = &writerBuffer;
This example shows a peripheral called MYPERIPHERAL that implements two EasyDMA channels, one
for reading, called READER, and one for writing, called WRITER. When the peripheral is started, it is here
assumed that the peripheral will read 5 bytes from the readerBuffer located in RAM at address 0x20000000,
process the data and then write no more than 6 bytes back to the writerBuffer located in RAM at address
0x20000005. The memory layout of these buffers is illustrated in Figure 7: EasyDMA memory layout on page
28.
Page 27
10 EasyDMA
0x20000000
readerBuffer[0]
readerBuffer[1]
readerBuffer[2]
readerBuffer[3]
0x20000004
readerBuffer[4]
writerBuffer[0]
writerBuffer[1]
writerBuffer[2]
0x20000008
writerBuffer[3]
writerBuffer[4]
writerBuffer[5]
Figure 7: EasyDMA memory layout
The EasyDMA channel's MAXCNT register cannot be specified larger than the actual size of the buffer. If,
for example, the WRITER.MAXCNT register is specified larger than the size of the writerBuffer, the WRITER
EasyDMA channel may overflow the writerBuffer.
After the peripheral has completed the EasyDMA transfer, the CPU can read the EasyDMA channel's
AMOUNT register to see how many bytes that were transferred, e.g. it is possible for the CPU to read the
MYPERIPHERAL->WRITER.AMOUNT register to see how many bytes the WRITER wrote to RAM.
10.1 EasyDMA array list
The EasyDMA is able to operate in a mode called array list.
The EasyDMA array list can be represented by the data structure ArrayList_type illustrated in the code
example below.
This data structure includes only a buffer with size equal to READER.MAXCNT. EasyDMA will use the
READER.MAXCNT register to determine when the buffer is full.
This array list does not provide a mechanism to explicitly specify where the next item in the list is located.
Instead, it assumes that the list is organized as a linear array where items are located one after the other in
RAM.
#define BUFFER_SIZE
4
typedef struct ArrayList
{
uint8_t buffer[BUFFER_SIZE];
} ArrayList_type;
ArrayList_type ReaderList[3];
READER.MAXCNT = BUFFER_SIZE;
READER.PTR = &ReaderList;
READER.PTR = &ReaderList
0x20000000 : ReaderList[0]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000004 : ReaderList[1]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000008 : ReaderList[2]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
Figure 8: EasyDMA array list
Page 28
11 NVMC — Non-volatile memory controller
11 NVMC — Non-volatile memory controller
The Non-volatile memory controller (NVMC) is used for writing and erasing the internal Flash memory and
the UICR.
Before a write can be performed, the NVMC must be enabled for writing in CONFIG.WEN. Similarly, before
an erase can be performed, the NVMC must be enabled for erasing in CONFIG.EEN, see CONFIG on page
31. The user must make sure that writing and erasing are not enabled at the same time. Failing to do so
may result in unpredictable behavior.
11.1 Writing to Flash
When writing is enabled, the Flash is written by writing a full 32-bit word to a word-aligned address in the
Flash.
The NVMC is only able to write '0' to bits in the Flash that are erased, that is, set to '1'. It cannot write back a
bit to '1'.
As illustrated in Memory on page 23, the Flash is divided into multiple pages that are further divided into
multiple blocks. The same block in the Flash can only be written nWRITE number of times before an erase
must be performed using ERASEPAGE or ERASEALL. See the memory size and organization in Memory on
page 23 for block size.
Only full 32-bit words can be written to Flash using the NVMC interface. To write less than 32 bits to Flash,
write the data as a word, and set all the bits that should remain unchanged in the word to '1'. Note that the
restriction about the number of writes (see above) still applies in this case.
The time it takes to write a word to the Flash is specified by tWRITE. The CPU is halted while the NVMC is
writing to the Flash.
Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.
11.2 Erasing a page in Flash
When erase is enabled, the Flash can be erased page by page using the ERASEPAGE register.
After erasing a Flash page, all bits in the page are set to '1'. The time it takes to erase a page is specified by
tERASEPAGE. The CPU is halted while the NVMC performs the erase operation.
11.3 Writing to user information configuration registers (UICR)
User information configuration registers (UICR) are written in the same way as Flash. After UICR has been
written, the new UICR configuration will only take effect after a reset.
UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR or
ERASEALL.
The time it takes to write a word to the UICR is specified by tWRITE. The CPU is halted while the NVMC is
writing to the UICR.
11.4 Erasing user information configuration registers (UICR)
When erase is enabled, UICR can be erased using the ERASEUICR register.
After erasing UICR all bits in UICR are set to '1'. The time it takes to erase UICR is specified by tERASEPAGE.
The CPU is halted while the NVMC performs the erase operation.
Page 29
11 NVMC — Non-volatile memory controller
11.5 Erase all
When erase is enabled, the whole Flash and UICR can be erased in one operation by using the ERASEALL
register. ERASEALL will not erase the factory information configuration registers (FICR).
The time it takes to perform an ERASEALL command is specified by tERASEALL The CPU is halted while the
NVMC performs the erase operation.
11.6 Cache
An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC.
See the Memory map in Memory map on page 24 for the location of Flash.
A cache hit is an instruction fetch from the cache, and it has a 0 wait-state delay. The number of wait-states
for a cache miss, where the instruction is not available in the cache and needs to be fetched from Flash,
depends on the processor frequency and is shown in CPU on page 21
Enabling the cache can increase CPU performance and reduce power consumption by reducing the number
of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache will use some
current when enabled. If the reduction in average current due to reduced flash accesses is larger than the
cache power requirement, the average current to execute the program code will reduce.
When disabled, the cache does not use current and does not retain its content.
It is possible to enable cache profiling to analyze the performance of the cache for your program using the
ICACHECNF register. When profiling is enabled, the IHIT and IMISS registers are incremented for every
instruction cache hit or miss respectively. The hit and miss profiling registers do not wrap around after
reaching the maximum value. If the maximum value is reached, consider profiling for a shorter duration to get
correct numbers.
11.7 Registers
Table 12: Instances
Base address
Peripheral
Instance
Description
0x4001E000
NVMC
NVMC
Non-Volatile Memory Controller
Configuration
Table 13: Register Overview
Register
Offset
Description
READY
0x400
Ready flag
CONFIG
0x504
Configuration register
ERASEPAGE
0x508
Register for erasing a page in Code area
ERASEPCR1
0x508
Register for erasing a page in Code area. Equivalent to ERASEPAGE.
ERASEALL
0x50C
Register for erasing all non-volatile user memory
ERASEPCR0
0x510
Register for erasing a page in Code area. Equivalent to ERASEPAGE.
ERASEUICR
0x514
Register for erasing User Information Configuration Registers
ICACHECNF
0x540
I-Code cache configuration register.
IHIT
0x548
I-Code cache hit counter.
IMISS
0x54C
I-Code cache miss counter.
11.7.1 READY
Address offset: 0x400
Ready flag
Page 30
Deprecated
Deprecated
11 NVMC — Non-volatile memory controller
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Busy
0
NVMC is busy (on-going write or erase operation)
Ready
1
NVMC is ready
READY
NVMC is ready or busy
11.7.2 CONFIG
Address offset: 0x504
Configuration register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000000
Id
RW Field
A
RW WEN
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Program memory access mode. It is strongly recommended
to only activate erase and write modes when they are actively
used. Enabling write or erase will invalidate the cache and keep
it invalidated.
Ren
0
Read only access
Wen
1
Write Enabled
Een
2
Erase enabled
11.7.3 ERASEPAGE
Address offset: 0x508
Register for erasing a page in Code area
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ERASEPAGE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Register for starting erase of a page in Code area
The value is the address to the page to be erased. (Addresses of
first word in page). Note that code erase has to be enabled by
CONFIG.EEN before the page can be erased. Attempts to erase
pages that are outside the code area may result in undesirable
behaviour, e.g. the wrong page may be erased.
11.7.4 ERASEPCR1 ( Deprecated )
Address offset: 0x508
Register for erasing a page in Code area. Equivalent to ERASEPAGE.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ERASEPCR1
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Register for erasing a page in Code area. Equivalent to
ERASEPAGE.
11.7.5 ERASEALL
Address offset: 0x50C
Register for erasing all non-volatile user memory
Page 31
11 NVMC — Non-volatile memory controller
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ERASEALL
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Erase all non-volatile memory including UICR registers. Note
that code erase has to be enabled by CONFIG.EEN before the
UICR can be erased.
NoOperation
0
No operation
Erase
1
Start chip erase
11.7.6 ERASEPCR0 ( Deprecated )
Address offset: 0x510
Register for erasing a page in Code area. Equivalent to ERASEPAGE.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ERASEPCR0
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Register for starting erase of a page in Code area. Equivalent to
ERASEPAGE.
11.7.7 ERASEUICR
Address offset: 0x514
Register for erasing User Information Configuration Registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ERASEUICR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Register starting erase of all User Information Configuration
Registers. Note that code erase has to be enabled by
CONFIG.EEN before the UICR can be erased.
NoOperation
0
No operation
Erase
1
Start erase of UICR
11.7.8 ICACHECNF
Address offset: 0x540
I-Code cache configuration register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
Reset 0x00000000
Id
RW Field
A
RW CACHEEN
B
0
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable cache. Invalidates all cache entries.
Enabled
1
Enable cache
Disabled
0
Disable cache profiling
Enabled
1
Enable cache profiling
Cache enable
RW CACHEPROFEN
Cache profiling enable
11.7.9 IHIT
Address offset: 0x548
I-Code cache hit counter.
Page 32
11 NVMC — Non-volatile memory controller
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW HITS
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Number of cache hits
11.7.10 IMISS
Address offset: 0x54C
I-Code cache miss counter.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MISSES
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Number of cache misses
11.8 Electrical specification
11.8.1 Flash programming
Symbol
Description
nWRITE,BLOCK
Amount of writes allowed in a block between erase
Min.
Typ.
Max.
Units
tWRITE
Time to write one word
67.5
338
µs
tERASEPAGE
Time to erase one page
2.05
89.7
ms
tERASEALL
Time to erase all flash
6.72
295.3
ms
Max.
Units
181
11.8.2 Cache size
Symbol
Description
SizeICODE
I-Code cache size
Min.
Typ.
2048
Page 33
Bytes
12 BPROT — Block protection
12 BPROT — Block protection
The mechanism for protecting non-volatile memory can be used to prevent application code from erasing or
writing to protected blocks.
Non-volatile memory can be protected from erases and writes depending on the settings in the CONFIG
registers. One bit in a CONFIG register represents one protected block of 4 kB. There are four CONFIG
registers of 32 bits, which means there are 128 protectable blocks in total.
Important: If an erase or write to a protected block is detected, the CPU will hard fault. If an
ERASEALL operation is attempted from the CPU while any block is protected, it will be blocked and
the CPU will hard fault.
On reset, all the protection bits are cleared. To ensure safe operation, the first task after reset must be to set
the protection bits. The only way of clearing protection bits is by resetting the device from any reset source.
The protection mechanism is turned off when in debug interface mode (a debugger is connected) and the
DISABLEINDEBUG register is set to disable. For more information, see Debug and trace on page 72.
Program Memory
127
126
125
l
31
CONFIG[3]
0
...
2
1
0
0x00000000
l
31
CONFIG[0]
0
Figure 9: Protected regions of program memory
12.1 Registers
Table 14: Instances
Base address
Peripheral
Instance
Description
0x40000000
BPROT
BPROT
Block Protect
Configuration
Table 15: Register Overview
Register
Offset
Description
CONFIG0
0x600
Block protect configuration register 0
CONFIG1
0x604
Block protect configuration register 1
DISABLEINDEBUG
0x608
Disable protection mechanism in debug interface mode
0x60C
Reserved
CONFIG2
0x610
Block protect configuration register 2
CONFIG3
0x614
Block protect configuration register 3
Page 34
12 BPROT — Block protection
12.1.1 CONFIG0
Address offset: 0x600
Block protect configuration register 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW REGION0
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
Value Id
Value
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
I H G F E D C B A
Description
Enable protection for region 0. Write '0' has no effect.
RW REGION1
Enable protection for region 1. Write '0' has no effect.
RW REGION2
Enable protection for region 2. Write '0' has no effect.
RW REGION3
Enable protection for region 3. Write '0' has no effect.
RW REGION4
Enable protection for region 4. Write '0' has no effect.
RW REGION5
Enable protection for region 5. Write '0' has no effect.
RW REGION6
Enable protection for region 6. Write '0' has no effect.
RW REGION7
Enable protection for region 7. Write '0' has no effect.
RW REGION8
Enable protection for region 8. Write '0' has no effect.
RW REGION9
Enable protection for region 9. Write '0' has no effect.
RW REGION10
Enable protection for region 10. Write '0' has no effect.
RW REGION11
Enable protection for region 11. Write '0' has no effect.
RW REGION12
Enable protection for region 12. Write '0' has no effect.
RW REGION13
Enable protection for region 13. Write '0' has no effect.
RW REGION14
Enable protection for region 14. Write '0' has no effect.
RW REGION15
Enable protection for region 15. Write '0' has no effect.
RW REGION16
Enable protection for region 16. Write '0' has no effect.
Protection disabled
Page 35
12 BPROT — Block protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
R
S
T
U
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
RW REGION17
I H G F E D C B A
Enable protection for region 17. Write '0' has no effect.
RW REGION18
Enable protection for region 18. Write '0' has no effect.
RW REGION19
Enable protection for region 19. Write '0' has no effect.
RW REGION20
Enable protection for region 20. Write '0' has no effect.
RW REGION21
Enable protection for region 21. Write '0' has no effect.
RW REGION22
Enable protection for region 22. Write '0' has no effect.
RW REGION23
Enable protection for region 23. Write '0' has no effect.
RW REGION24
Enable protection for region 24. Write '0' has no effect.
RW REGION25
Enable protection for region 25. Write '0' has no effect.
RW REGION26
Enable protection for region 26. Write '0' has no effect.
RW REGION27
Enable protection for region 27. Write '0' has no effect.
RW REGION28
Enable protection for region 28. Write '0' has no effect.
RW REGION29
Enable protection for region 29. Write '0' has no effect.
RW REGION30
Enable protection for region 30. Write '0' has no effect.
RW REGION31
Enable protection for region 31. Write '0' has no effect.
12.1.2 CONFIG1
Address offset: 0x604
Block protect configuration register 1
Page 36
12 BPROT — Block protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW REGION32
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
Value Id
Value
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
I H G F E D C B A
Description
Enable protection for region 32. Write '0' has no effect.
RW REGION33
Enable protection for region 33. Write '0' has no effect.
RW REGION34
Enable protection for region 34. Write '0' has no effect.
RW REGION35
Enable protection for region 35. Write '0' has no effect.
RW REGION36
Enable protection for region 36. Write '0' has no effect.
RW REGION37
Enable protection for region 37. Write '0' has no effect.
RW REGION38
Enable protection for region 38. Write '0' has no effect.
RW REGION39
Enable protection for region 39. Write '0' has no effect.
RW REGION40
Enable protection for region 40. Write '0' has no effect.
RW REGION41
Enable protection for region 41. Write '0' has no effect.
RW REGION42
Enable protection for region 42. Write '0' has no effect.
RW REGION43
Enable protection for region 43. Write '0' has no effect.
RW REGION44
Enable protection for region 44. Write '0' has no effect.
RW REGION45
Enable protection for region 45. Write '0' has no effect.
RW REGION46
Enable protection for region 46. Write '0' has no effect.
RW REGION47
Enable protection for region 47. Write '0' has no effect.
RW REGION48
Enable protection for region 48. Write '0' has no effect.
RW REGION49
Enable protection for region 49. Write '0' has no effect.
RW REGION50
Enable protection for region 50. Write '0' has no effect.
Page 37
12 BPROT — Block protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
T
U
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
RW REGION51
I H G F E D C B A
Enable protection for region 51. Write '0' has no effect.
RW REGION52
Enable protection for region 52. Write '0' has no effect.
RW REGION53
Enable protection for region 53. Write '0' has no effect.
RW REGION54
Enable protection for region 54. Write '0' has no effect.
RW REGION55
Enable protection for region 55. Write '0' has no effect.
RW REGION56
Enable protection for region 56. Write '0' has no effect.
RW REGION57
Enable protection for region 57. Write '0' has no effect.
RW REGION58
Enable protection for region 58. Write '0' has no effect.
RW REGION59
Enable protection for region 59. Write '0' has no effect.
RW REGION60
Enable protection for region 60. Write '0' has no effect.
RW REGION61
Enable protection for region 61. Write '0' has no effect.
RW REGION62
Enable protection for region 62. Write '0' has no effect.
RW REGION63
Enable protection for region 63. Write '0' has no effect.
12.1.3 DISABLEINDEBUG
Address offset: 0x608
Disable protection mechanism in debug interface mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000001
Id
RW Field
A
RW DISABLEINDEBUG
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value
Description
Disable the protection mechanism for NVM regions while
in debug interface mode. This register will only disable the
protection mechanism if the device is in debug interface mode.
Disabled
1
Disable in debug
Page 38
12 BPROT — Block protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000001
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Description
Enabled
0
Enable in debug
12.1.4 CONFIG2
Address offset: 0x610
Block protect configuration register 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW REGION64
B
C
D
E
F
G
H
I
J
K
L
M
N
O
Value Id
Value
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
I H G F E D C B A
Description
Enable protection for region 64. Write '0' has no effect.
RW REGION65
Enable protection for region 65. Write '0' has no effect.
RW REGION66
Enable protection for region 66. Write '0' has no effect.
RW REGION67
Enable protection for region 67. Write '0' has no effect.
RW REGION68
Enable protection for region 68. Write '0' has no effect.
RW REGION69
Enable protection for region 69. Write '0' has no effect.
RW REGION70
Enable protection for region 70. Write '0' has no effect.
RW REGION71
Enable protection for region 71. Write '0' has no effect.
RW REGION72
Enable protection for region 72. Write '0' has no effect.
RW REGION73
Enable protection for region 73. Write '0' has no effect.
RW REGION74
Enable protection for region 74. Write '0' has no effect.
RW REGION75
Enable protection for region 75. Write '0' has no effect.
RW REGION76
Enable protection for region 76. Write '0' has no effect.
RW REGION77
Enable protection for region 77. Write '0' has no effect.
RW REGION78
Enable protection for region 78. Write '0' has no effect.
Protection disabled
Page 39
12 BPROT — Block protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
P
Q
R
S
T
U
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
RW REGION79
I H G F E D C B A
Enable protection for region 79. Write '0' has no effect.
RW REGION80
Enable protection for region 80. Write '0' has no effect.
RW REGION81
Enable protection for region 81. Write '0' has no effect.
RW REGION82
Enable protection for region 82. Write '0' has no effect.
RW REGION83
Enable protection for region 83. Write '0' has no effect.
RW REGION84
Enable protection for region 84. Write '0' has no effect.
RW REGION85
Enable protection for region 85. Write '0' has no effect.
RW REGION86
Enable protection for region 86. Write '0' has no effect.
RW REGION87
Enable protection for region 87. Write '0' has no effect.
RW REGION88
Enable protection for region 88. Write '0' has no effect.
RW REGION89
Enable protection for region 89. Write '0' has no effect.
RW REGION90
Enable protection for region 90. Write '0' has no effect.
RW REGION91
Enable protection for region 91. Write '0' has no effect.
RW REGION92
Enable protection for region 92. Write '0' has no effect.
RW REGION93
Enable protection for region 93. Write '0' has no effect.
RW REGION94
Enable protection for region 94. Write '0' has no effect.
RW REGION95
Enable protection for region 95. Write '0' has no effect.
Page 40
12 BPROT — Block protection
12.1.5 CONFIG3
Address offset: 0x614
Block protect configuration register 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW REGION96
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
Value Id
Value
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
I H G F E D C B A
Description
Enable protection for region 96. Write '0' has no effect.
RW REGION97
Enable protection for region 97. Write '0' has no effect.
RW REGION98
Enable protection for region 98. Write '0' has no effect.
RW REGION99
Enable protection for region 99. Write '0' has no effect.
RW REGION100
Enable protection for region 100. Write '0' has no effect.
RW REGION101
Enable protection for region 101. Write '0' has no effect.
RW REGION102
Enable protection for region 102. Write '0' has no effect.
RW REGION103
Enable protection for region 103. Write '0' has no effect.
RW REGION104
Enable protection for region 104. Write '0' has no effect.
RW REGION105
Enable protection for region 105. Write '0' has no effect.
RW REGION106
Enable protection for region 106. Write '0' has no effect.
RW REGION107
Enable protection for region 107. Write '0' has no effect.
RW REGION108
Enable protection for region 108. Write '0' has no effect.
RW REGION109
Enable protection for region 109. Write '0' has no effect.
RW REGION110
Enable protection for region 110. Write '0' has no effect.
RW REGION111
Enable protection for region 111. Write '0' has no effect.
RW REGION112
Enable protection for region 112. Write '0' has no effect.
Protection disabled
Page 41
12 BPROT — Block protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
R
S
T
U
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
RW REGION113
I H G F E D C B A
Enable protection for region 113. Write '0' has no effect.
RW REGION114
Enable protection for region 114. Write '0' has no effect.
RW REGION115
Enable protection for region 115. Write '0' has no effect.
RW REGION116
Enable protection for region 116. Write '0' has no effect.
RW REGION117
Enable protection for region 117. Write '0' has no effect.
RW REGION118
Enable protection for region 118. Write '0' has no effect.
RW REGION119
Enable protection for region 119. Write '0' has no effect.
RW REGION120
Enable protection for region 120. Write '0' has no effect.
RW REGION121
Enable protection for region 121. Write '0' has no effect.
RW REGION122
Enable protection for region 122. Write '0' has no effect.
RW REGION123
Enable protection for region 123. Write '0' has no effect.
RW REGION124
Enable protection for region 124. Write '0' has no effect.
RW REGION125
Enable protection for region 125. Write '0' has no effect.
RW REGION126
Enable protection for region 126. Write '0' has no effect.
RW REGION127
Enable protection for region 127. Write '0' has no effect.
Page 42
13 FICR — Factory information configuration
registers
13 FICR — Factory information configuration registers
Factory information configuration registers (FICR) are pre-programmed in factory and cannot be erased by
the user. These registers contain chip-specific information and configuration.
13.1 Registers
Table 16: Instances
Base address
Peripheral
Instance
Description
0x10000000
FICR
FICR
Factory Information Configuration
Configuration
Table 17: Register Overview
Register
Offset
Description
CODEPAGESIZE
0x010
Code memory page size
CODESIZE
0x014
Code memory size
DEVICEID[0]
0x060
Device identifier
DEVICEID[1]
0x064
Device identifier
ER[0]
0x080
Encryption Root, word 0
ER[1]
0x084
Encryption Root, word 1
ER[2]
0x088
Encryption Root, word 2
ER[3]
0x08C
Encryption Root, word 3
IR[0]
0x090
Identity Root, word 0
IR[1]
0x094
Identity Root, word 1
IR[2]
0x098
Identity Root, word 2
IR[3]
0x09C
Identity Root, word 3
DEVICEADDRTYPE
0x0A0
Device address type
DEVICEADDR[0]
0x0A4
Device address 0
DEVICEADDR[1]
0x0A8
Device address 1
INFO.PART
0x100
Part code
INFO.VARIANT
0x104
Part Variant, Hardware version and Production configuration
INFO.PACKAGE
0x108
Package option
INFO.RAM
0x10C
RAM variant
INFO.FLASH
0x110
Flash variant
0x114
Reserved
0x118
Reserved
0x11C
Reserved
TEMP.A0
0x404
Slope definition A0.
TEMP.A1
0x408
Slope definition A1.
TEMP.A2
0x40C
Slope definition A2.
TEMP.A3
0x410
Slope definition A3.
TEMP.A4
0x414
Slope definition A4.
TEMP.A5
0x418
Slope definition A5.
TEMP.B0
0x41C
y-intercept B0.
TEMP.B1
0x420
y-intercept B1.
TEMP.B2
0x424
y-intercept B2.
TEMP.B3
0x428
y-intercept B3.
TEMP.B4
0x42C
y-intercept B4.
TEMP.B5
0x430
y-intercept B5.
TEMP.T0
0x434
Segment end T0.
TEMP.T1
0x438
Segment end T1.
TEMP.T2
0x43C
Segment end T2.
TEMP.T3
0x440
Segment end T3.
TEMP.T4
0x444
Segment end T4.
Page 43
13 FICR — Factory information configuration
registers
Register
Offset
Description
NFC.TAGHEADER0
0x450
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFC.TAGHEADER1
0x454
NFC.TAGHEADER2
0x458
NFC.TAGHEADER3
0x45C
NFCID1_2ND_LAST and NFCID1_LAST.
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
13.1.1 CODEPAGESIZE
Address offset: 0x010
Code memory page size
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
CODEPAGESIZE
Code memory page size
13.1.2 CODESIZE
Address offset: 0x014
Code memory size
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
CODESIZE
Code memory size in number of pages
Total code space is: CODEPAGESIZE * CODESIZE
13.1.3 DEVICEID[0]
Address offset: 0x060
Device identifier
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
DEVICEID
64 bit unique device identifier
DEVICEID[0] contains the least significant bits of the device
identifier. DEVICEID[1] contains the most significant bits of the
device identifier.
13.1.4 DEVICEID[1]
Address offset: 0x064
Device identifier
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
DEVICEID
64 bit unique device identifier
Page 44
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
DEVICEID[0] contains the least significant bits of the device
identifier. DEVICEID[1] contains the most significant bits of the
device identifier.
13.1.5 ER[0]
Address offset: 0x080
Encryption Root, word 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
ER
Encryption Root, word n
13.1.6 ER[1]
Address offset: 0x084
Encryption Root, word 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
ER
Encryption Root, word n
13.1.7 ER[2]
Address offset: 0x088
Encryption Root, word 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
ER
Encryption Root, word n
13.1.8 ER[3]
Address offset: 0x08C
Encryption Root, word 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
ER
Encryption Root, word n
13.1.9 IR[0]
Address offset: 0x090
Identity Root, word 0
Page 45
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
IR
Identity Root, word n
13.1.10 IR[1]
Address offset: 0x094
Identity Root, word 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
IR
Identity Root, word n
13.1.11 IR[2]
Address offset: 0x098
Identity Root, word 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
IR
Identity Root, word n
13.1.12 IR[3]
Address offset: 0x09C
Identity Root, word 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
IR
Identity Root, word n
13.1.13 DEVICEADDRTYPE
Address offset: 0x0A0
Device address type
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Description
Public
0
Public address
Random
1
Random address
DEVICEADDRTYPE
Device address type
13.1.14 DEVICEADDR[0]
Address offset: 0x0A4
Device address 0
Page 46
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
DEVICEADDR
48 bit device address
DEVICEADDR[0] contains the least significant bits of the device
address. DEVICEADDR[1] contains the most significant bits of
the device address. Only bits [15:0] of DEVICEADDR[1] are used.
13.1.15 DEVICEADDR[1]
Address offset: 0x0A8
Device address 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
DEVICEADDR
48 bit device address
DEVICEADDR[0] contains the least significant bits of the device
address. DEVICEADDR[1] contains the most significant bits of
the device address. Only bits [15:0] of DEVICEADDR[1] are used.
13.1.16 INFO.PART
Address offset: 0x100
Part code
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00052832
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 1 1 0 0 1 0
Value Id
Value
Description
N52832
0x52832
nRF52832
Unspecified
0xFFFFFFFF
Unspecified
PART
Part code
13.1.17 INFO.VARIANT
Address offset: 0x104
Part Variant, Hardware version and Production configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x41414142
Id
RW Field
A
R
0
Value Id
1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0
Value
Description
VARIANT
Part Variant, Hardware version and Production configuration,
encoded as ASCII
AAAA
0x41414141
AAAA
AAAB
0x41414142
AAAB
AABA
0x41414241
AABA
AABB
0x41414242
AABB
Unspecified
0xFFFFFFFF
Unspecified
13.1.18 INFO.PACKAGE
Address offset: 0x108
Package option
Page 47
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00002000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
QF
0x2000
QFxx - 48-pin QFN
CI
0x2001
CIxx - 7x8 WLCSP 56 balls
Unspecified
0xFFFFFFFF
Unspecified
PACKAGE
Package option
13.1.19 INFO.RAM
Address offset: 0x10C
RAM variant
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000040
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Value Id
Value
Description
K16
0x10
16 kByte RAM
K32
0x20
32 kByte RAM
K64
0x40
64 kByte RAM
Unspecified
0xFFFFFFFF
Unspecified
RAM
RAM variant
13.1.20 INFO.FLASH
Address offset: 0x110
Flash variant
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000200
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
K128
0x80
128 kByte FLASH
K256
0x100
256 kByte FLASH
K512
0x200
512 kByte FLASH
Unspecified
0xFFFFFFFF
Unspecified
FLASH
Flash variant
13.1.21 TEMP.A0
Address offset: 0x404
Slope definition A0.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x00000320
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0
Value
Description
A
A (slope definition) register.
13.1.22 TEMP.A1
Address offset: 0x408
Slope definition A1.
Page 48
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x00000343
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1
Value
Description
A
A (slope definition) register.
13.1.23 TEMP.A2
Address offset: 0x40C
Slope definition A2.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x0000035D
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 1
Value
Description
A
A (slope definition) register.
13.1.24 TEMP.A3
Address offset: 0x410
Slope definition A3.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x00000400
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Value
Description
A
A (slope definition) register.
13.1.25 TEMP.A4
Address offset: 0x414
Slope definition A4.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x00000452
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0
Value
Description
A
A (slope definition) register.
13.1.26 TEMP.A5
Address offset: 0x418
Slope definition A5.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x0000037B
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 1 1
Value
Description
A
A (slope definition) register.
13.1.27 TEMP.B0
Address offset: 0x41C
y-intercept B0.
Page 49
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00003FCC
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0
Value
Description
B
B (y-intercept)
13.1.28 TEMP.B1
Address offset: 0x420
y-intercept B1.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00003F98
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0
Value
Description
B
B (y-intercept)
13.1.29 TEMP.B2
Address offset: 0x424
y-intercept B2.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00003F98
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0
Value
Description
B
B (y-intercept)
13.1.30 TEMP.B3
Address offset: 0x428
y-intercept B3.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00000012
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
Value
Description
B
B (y-intercept)
13.1.31 TEMP.B4
Address offset: 0x42C
y-intercept B4.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x0000004D
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1
Value
Description
B
B (y-intercept)
13.1.32 TEMP.B5
Address offset: 0x430
y-intercept B5.
Page 50
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00003E10
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0
Value
Description
B
B (y-intercept)
13.1.33 TEMP.T0
Address offset: 0x434
Segment end T0.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x000000E2
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0
Value
Description
T
T (segment end)register.
13.1.34 TEMP.T1
Address offset: 0x438
Segment end T1.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
T
T (segment end)register.
13.1.35 TEMP.T2
Address offset: 0x43C
Segment end T2.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000014
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0
Value
Description
T
T (segment end)register.
13.1.36 TEMP.T3
Address offset: 0x440
Segment end T3.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000019
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1
Value
Description
T
T (segment end)register.
13.1.37 TEMP.T4
Address offset: 0x444
Segment end T4.
Page 51
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000050
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0
Value
Description
T
T (segment end)register.
13.1.38 NFC.TAGHEADER0
Address offset: 0x450
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFF5F
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1
Id
RW Field
Value
A
R
MFGID
Description
B
R
UD1
Unique identifier byte 1
C
R
UD2
Unique identifier byte 2
D
R
UD3
Unique identifier byte 3
Default Manufacturer ID: Nordic Semiconductor ASA has ICM
0x5F
13.1.39 NFC.TAGHEADER1
Address offset: 0x454
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
Value
A
R
UD4
Description
Unique identifier byte 4
B
R
UD5
Unique identifier byte 5
C
R
UD6
Unique identifier byte 6
D
R
UD7
Unique identifier byte 7
13.1.40 NFC.TAGHEADER2
Address offset: 0x458
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
Value
A
R
UD8
Description
Unique identifier byte 8
B
R
UD9
Unique identifier byte 9
C
R
UD10
Unique identifier byte 10
D
R
UD11
Unique identifier byte 11
13.1.41 NFC.TAGHEADER3
Address offset: 0x45C
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Page 52
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
Value
A
R
UD12
Description
Unique identifier byte 12
B
R
UD13
Unique identifier byte 13
C
R
UD14
Unique identifier byte 14
D
R
UD15
Unique identifier byte 15
Page 53
14 UICR — User information configuration
registers
14 UICR — User information configuration registers
The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for configuring
user specific settings.
For information on writing UICR registers, see the NVMC — Non-volatile memory controller on page 29 and
Memory on page 23 chapters.
14.1 Registers
Table 18: Instances
Base address
Peripheral
Instance
Description
0x10001000
UICR
UICR
User Information Configuration
Configuration
Table 19: Register Overview
Register
Offset
Description
0x000
Reserved
0x004
Reserved
0x008
Reserved
0x010
Reserved
NRFFW[0]
0x014
Reserved for Nordic firmware design
NRFFW[1]
0x018
Reserved for Nordic firmware design
NRFFW[2]
0x01C
Reserved for Nordic firmware design
NRFFW[3]
0x020
Reserved for Nordic firmware design
NRFFW[4]
0x024
Reserved for Nordic firmware design
NRFFW[5]
0x028
Reserved for Nordic firmware design
NRFFW[6]
0x02C
Reserved for Nordic firmware design
NRFFW[7]
0x030
Reserved for Nordic firmware design
NRFFW[8]
0x034
Reserved for Nordic firmware design
NRFFW[9]
0x038
Reserved for Nordic firmware design
NRFFW[10]
0x03C
Reserved for Nordic firmware design
NRFFW[11]
0x040
Reserved for Nordic firmware design
NRFFW[12]
0x044
Reserved for Nordic firmware design
NRFFW[13]
0x048
Reserved for Nordic firmware design
NRFFW[14]
0x04C
Reserved for Nordic firmware design
NRFHW[0]
0x050
Reserved for Nordic hardware design
NRFHW[1]
0x054
Reserved for Nordic hardware design
NRFHW[2]
0x058
Reserved for Nordic hardware design
NRFHW[3]
0x05C
Reserved for Nordic hardware design
NRFHW[4]
0x060
Reserved for Nordic hardware design
NRFHW[5]
0x064
Reserved for Nordic hardware design
NRFHW[6]
0x068
Reserved for Nordic hardware design
NRFHW[7]
0x06C
Reserved for Nordic hardware design
NRFHW[8]
0x070
Reserved for Nordic hardware design
NRFHW[9]
0x074
Reserved for Nordic hardware design
NRFHW[10]
0x078
Reserved for Nordic hardware design
NRFHW[11]
0x07C
Reserved for Nordic hardware design
CUSTOMER[0]
0x080
Reserved for customer
CUSTOMER[1]
0x084
Reserved for customer
CUSTOMER[2]
0x088
Reserved for customer
CUSTOMER[3]
0x08C
Reserved for customer
CUSTOMER[4]
0x090
Reserved for customer
CUSTOMER[5]
0x094
Reserved for customer
CUSTOMER[6]
0x098
Reserved for customer
Page 54
14 UICR — User information configuration
registers
Register
Offset
Description
CUSTOMER[7]
0x09C
Reserved for customer
CUSTOMER[8]
0x0A0
Reserved for customer
CUSTOMER[9]
0x0A4
Reserved for customer
CUSTOMER[10]
0x0A8
Reserved for customer
CUSTOMER[11]
0x0AC
Reserved for customer
CUSTOMER[12]
0x0B0
Reserved for customer
CUSTOMER[13]
0x0B4
Reserved for customer
CUSTOMER[14]
0x0B8
Reserved for customer
CUSTOMER[15]
0x0BC
Reserved for customer
CUSTOMER[16]
0x0C0
Reserved for customer
CUSTOMER[17]
0x0C4
Reserved for customer
CUSTOMER[18]
0x0C8
Reserved for customer
CUSTOMER[19]
0x0CC
Reserved for customer
CUSTOMER[20]
0x0D0
Reserved for customer
CUSTOMER[21]
0x0D4
Reserved for customer
CUSTOMER[22]
0x0D8
Reserved for customer
CUSTOMER[23]
0x0DC
Reserved for customer
CUSTOMER[24]
0x0E0
Reserved for customer
CUSTOMER[25]
0x0E4
Reserved for customer
CUSTOMER[26]
0x0E8
Reserved for customer
CUSTOMER[27]
0x0EC
Reserved for customer
CUSTOMER[28]
0x0F0
Reserved for customer
CUSTOMER[29]
0x0F4
Reserved for customer
CUSTOMER[30]
0x0F8
Reserved for customer
CUSTOMER[31]
0x0FC
Reserved for customer
PSELRESET[0]
0x200
Mapping of the nRESET function (see POWER chapter for details)
PSELRESET[1]
0x204
Mapping of the nRESET function (see POWER chapter for details)
APPROTECT
0x208
Access Port protection
NFCPINS
0x20C
Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
14.1.1 NRFFW[0]
Address offset: 0x014
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.2 NRFFW[1]
Address offset: 0x018
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.3 NRFFW[2]
Address offset: 0x01C
Reserved for Nordic firmware design
Page 55
14 UICR — User information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.4 NRFFW[3]
Address offset: 0x020
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.5 NRFFW[4]
Address offset: 0x024
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.6 NRFFW[5]
Address offset: 0x028
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.7 NRFFW[6]
Address offset: 0x02C
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.8 NRFFW[7]
Address offset: 0x030
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
Page 56
14 UICR — User information configuration
registers
14.1.9 NRFFW[8]
Address offset: 0x034
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.10 NRFFW[9]
Address offset: 0x038
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.11 NRFFW[10]
Address offset: 0x03C
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.12 NRFFW[11]
Address offset: 0x040
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.13 NRFFW[12]
Address offset: 0x044
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.14 NRFFW[13]
Address offset: 0x048
Reserved for Nordic firmware design
Page 57
14 UICR — User information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.15 NRFFW[14]
Address offset: 0x04C
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.16 NRFHW[0]
Address offset: 0x050
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.17 NRFHW[1]
Address offset: 0x054
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.18 NRFHW[2]
Address offset: 0x058
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.19 NRFHW[3]
Address offset: 0x05C
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
Page 58
14 UICR — User information configuration
registers
14.1.20 NRFHW[4]
Address offset: 0x060
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.21 NRFHW[5]
Address offset: 0x064
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.22 NRFHW[6]
Address offset: 0x068
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.23 NRFHW[7]
Address offset: 0x06C
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.24 NRFHW[8]
Address offset: 0x070
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.25 NRFHW[9]
Address offset: 0x074
Reserved for Nordic hardware design
Page 59
14 UICR — User information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.26 NRFHW[10]
Address offset: 0x078
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.27 NRFHW[11]
Address offset: 0x07C
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.28 CUSTOMER[0]
Address offset: 0x080
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.29 CUSTOMER[1]
Address offset: 0x084
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.30 CUSTOMER[2]
Address offset: 0x088
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
Page 60
14 UICR — User information configuration
registers
14.1.31 CUSTOMER[3]
Address offset: 0x08C
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.32 CUSTOMER[4]
Address offset: 0x090
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.33 CUSTOMER[5]
Address offset: 0x094
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.34 CUSTOMER[6]
Address offset: 0x098
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.35 CUSTOMER[7]
Address offset: 0x09C
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.36 CUSTOMER[8]
Address offset: 0x0A0
Reserved for customer
Page 61
14 UICR — User information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.37 CUSTOMER[9]
Address offset: 0x0A4
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.38 CUSTOMER[10]
Address offset: 0x0A8
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.39 CUSTOMER[11]
Address offset: 0x0AC
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.40 CUSTOMER[12]
Address offset: 0x0B0
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.41 CUSTOMER[13]
Address offset: 0x0B4
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
Page 62
14 UICR — User information configuration
registers
14.1.42 CUSTOMER[14]
Address offset: 0x0B8
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.43 CUSTOMER[15]
Address offset: 0x0BC
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.44 CUSTOMER[16]
Address offset: 0x0C0
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.45 CUSTOMER[17]
Address offset: 0x0C4
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.46 CUSTOMER[18]
Address offset: 0x0C8
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.47 CUSTOMER[19]
Address offset: 0x0CC
Reserved for customer
Page 63
14 UICR — User information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.48 CUSTOMER[20]
Address offset: 0x0D0
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.49 CUSTOMER[21]
Address offset: 0x0D4
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.50 CUSTOMER[22]
Address offset: 0x0D8
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.51 CUSTOMER[23]
Address offset: 0x0DC
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.52 CUSTOMER[24]
Address offset: 0x0E0
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
Page 64
14 UICR — User information configuration
registers
14.1.53 CUSTOMER[25]
Address offset: 0x0E4
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.54 CUSTOMER[26]
Address offset: 0x0E8
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.55 CUSTOMER[27]
Address offset: 0x0EC
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.56 CUSTOMER[28]
Address offset: 0x0F0
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.57 CUSTOMER[29]
Address offset: 0x0F4
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.58 CUSTOMER[30]
Address offset: 0x0F8
Reserved for customer
Page 65
14 UICR — User information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.59 CUSTOMER[31]
Address offset: 0x0FC
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.60 PSELRESET[0]
Address offset: 0x200
Mapping of the nRESET function (see POWER chapter for details)
All PSELRESET registers have to contain the same value for a pin mapping to be valid. If they don't, there
will be no nRESET function exposed on a GPIO, and the device will always start independently of the levels
present on any of the GPIOs.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
21
GPIO number P0.n onto which Reset is exposed
Connection
Disconnected
1
Disconnect
Connected
0
Connect
14.1.61 PSELRESET[1]
Address offset: 0x204
Mapping of the nRESET function (see POWER chapter for details)
All PSELRESET registers have to contain the same value for a pin mapping to be valid. If they don't, there
will be no nRESET function exposed on a GPIO, and the device will always start independently of the levels
present on any of the GPIOs.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
21
GPIO number P0.n onto which Reset is exposed
Connection
Disconnected
1
Disconnect
Connected
0
Connect
14.1.62 APPROTECT
Address offset: 0x208
Access Port protection
Page 66
14 UICR — User information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PALL
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Enable or disable Access Port protection. Any other value than
0xFF being written to this field will enable protection.
See Debug and trace on page 72 for more information.
Disabled
0xFF
Disable
Enabled
0x00
Enable
14.1.63 NFCPINS
Address offset: 0x20C
Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PROTECT
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Description
Disabled
0
Operation as GPIO pins. Same protection as normal GPIO pins
NFC
1
Operation as NFC antenna pins. Configures the protection for
Setting of pins dedicated to NFC functionality
NFC operation
Page 67
15 Peripheral interface
15 Peripheral interface
Peripherals are controlled by the CPU by writing to configuration registers and task registers. Peripheral
events are indicated to the CPU by event registers and interrupts if they are configured for a given event.
Task signal from PPI
Peripheral
TASK
write
k
OR
SHORTS
task
Peripheral
core
event
INTEN
m
EVENT m
IRQ signal to NVIC
Event signal to PPI
Figure 10: Tasks, events, shortcuts, and interrupts
15.1 Peripheral ID
Every peripheral is assigned a fixed block of 0x1000 bytes of address space, which is equal to 1024 x 32 bit
registers.
See Instantiation on page 24 for more information about which peripherals are available and where they are
located in the address map.
There is a direct relationship between the peripheral ID and base address. For example, a peripheral with
base address 0x40000000 is assigned ID=0, a peripheral with base address 0x40001000 is assigned ID=1,
and a peripheral with base address 0x4001F000 is assigned ID=31.
Peripherals may share the same ID, which may impose one or more of the following limitations:
•
•
•
Some peripherals share some registers or other common resources.
Operation is mutually exclusive. Only one of the peripherals can be used at a time.
Switching from one peripheral to another must follow a specific pattern (disable the first, then enable the
second peripheral).
15.2 Peripherals with shared ID
In general, and with the exception of ID 0, peripherals sharing an ID and base address may not be used
simultaneously. The user can only enable one at the time on this specific ID.
When switching between two peripherals that share an ID, the user should do the following to prevent
unwanted behavior:
•
Disable the previously used peripheral
Page 68
15 Peripheral interface
•
•
•
•
Remove any PPI connections set up for the peripheral that is being disabled
Clear all bits in the INTEN register, i.e. INTENCLR = 0xFFFFFFFF.
Explicitly configure the peripheral that you enable and do not rely on configuration values that may be
inherited from the peripheral that was disabled.
Enable the now configured peripheral.
For each of the rows in the following table, the instance ID listed is shared by the peripherals in the same
row.
Table 20: Peripherals sharing an ID
Instance
ID 2 (0x40002000)
ID 3 (0x40003000)
ID 4 (0x40004000)
ID 35 (0x40023000)
ID 15 (0x4000F000)
ID 19 (0x40013000)
ID 20 (0x40014000)
ID 21 (0x40015000)
ID 22 (0x40016000)
ID 23 (0x40017000)
ID 24 (0x40018000)
ID 25 (0x40019000)
UARTE
UART
SPIM
SPIM
SPIM
SPIS
SPIS
SPIS
AAR
CCM
COMP
LPCOMP
SWI
SWI
SWI
SWI
SWI
SWI
EGU
EGU
EGU
EGU
EGU
EGU
SPI
SPI
SPI
TWIM
TWIM
TWIS
TWIS
TWI
TWI
15.3 Peripheral registers
Most peripherals feature an ENABLE register. Unless otherwise specified in the relevant chapter, the
peripheral registers (in particular the PSEL registers) must be configured before enabling the peripheral.
Note that the peripheral must be enabled before tasks and events can be used.
15.4 Bit set and clear
Registers with multiple single-bit bit fields may implement the "set-and-clear" pattern. This pattern enables
firmware to set and clear individual bits in a register without having to perform a read-modify-write operation
on the main register.
This pattern is implemented using three consecutive addresses in the register map where the main register
is followed by a dedicated SET and CLR register in that order.
The SET register is used to set individual bits in the main register while the CLR register is used to clear
individual bits in the main register. Writing a '1' to a bit in the SET or CLR register will set or clear the same
bit in the main register respectively. Writing a '0' to a bit in the SET or CLR register has no effect. Reading
the SET or CLR registers returns the value of the main register.
Restriction: The main register may not be visible and hence not directly accessible in all cases.
15.5 Tasks
Tasks are used to trigger actions in a peripheral, for example, to start a particular behavior. A peripheral can
implement multiple tasks with each task having a separate register in that peripheral's task register group.
A task is triggered when firmware writes a '1' to the task register or when the peripheral itself or another
peripheral toggles the corresponding task signal. See Figure 10: Tasks, events, shortcuts, and interrupts on
page 68.
Page 69
15 Peripheral interface
15.6 Events
Events are used to notify peripherals and the CPU about events that have happened, for example, a state
change in a peripheral. A peripheral may generate multiple events with each event having a separate
register in that peripheral’s event register group.
An event is generated when the peripheral itself toggles the corresponding event signal, and the event
register is updated to reflect that the event has been generated. See Figure 10: Tasks, events, shortcuts,
and interrupts on page 68. An event register is only cleared when firmware writes a '0' to it.
Events can be generated by the peripheral even when the event register is set to '1'.
15.7 Shortcuts
A shortcut is a direct connection between an event and a task within the same peripheral. If a shortcut is
enabled, its associated task is automatically triggered when its associated event is generated.
Using a shortcut is the equivalent to making the same connection outside the peripheral and through the
PPI. However, the propagation delay through the shortcut is usually shorter than the propagation delay
through the PPI.
Shortcuts are predefined, which means their connections cannot be configured by firmware. Each shortcut
can be individually enabled or disabled through the shortcut register, one bit per shortcut, giving a maximum
of 32 shortcuts for each peripheral.
15.8 Interrupts
All peripherals support interrupts. Interrupts are generated by events.
A peripheral only occupies one interrupt, and the interrupt number follows the peripheral ID. For example, the
peripheral with ID=4 is connected to interrupt number 4 in the Nested Vectored Interrupt Controller (NVIC).
Using the INTEN, INTENSET and INTENCLR registers, every event generated by a peripheral can be
configured to generate that peripheral’s interrupt. Multiple events can be enabled to generate interrupts
simultaneously. To resolve the correct interrupt source, the event registers in the event group of peripheral
registers will indicate the source.
Some peripherals implement only INTENSET and INTENCLR, and the INTEN register is not available
on those peripherals. Refer to the individual chapters for details. In all cases, however, reading back the
INTENSET or INTENCLR register returns the same information as in INTEN.
Each event implemented in the peripheral is associated with a specific bit position in the INTEN, INTENSET
and INTENCLR registers.
The relationship between tasks, events, shortcuts, and interrupts is shown in Figure 10: Tasks, events,
shortcuts, and interrupts on page 68.
15.8.1 Interrupt clearing
When clearing an interrupt by writing "0" to an event register, or disabling an interrupt using the INTENCLR
register, it can take up to four CPU clock cycles to take effect. This means that an interrupt may reoccur
immediatelly even if a new event has not come, if the program exits an interrupt handler after the interrupt is
cleared or disabled, but before four clock cycles have passed.
Important: To avoid an interrupt reoccurring before a new event has come, the program should
perform a read from one of the peripheral registers, for example, the event register that has been
cleared, or the INTENCLR register that has been used to disable the interrupt.
This will cause a one to three-cycle delay and ensure the interrupt is cleared before exiting the interrupt
handler. Care should be taken to ensure the compiler does not remove the read operation as an
optimization. If the program can guarantee a four-cycle delay after event clear or interrupt disable another
way, then a read of a register is not required.
Page 70
15 Peripheral interface
Page 71
16 Debug and trace
16 Debug and trace
The debug and trace system offers a flexible and powerful mechanism for non-intrusive debugging.
nRF52832
DAP
SWDCLK
External
Debugger
CTRL-AP
NVMC
SW-DP
SWDIO
APPROTECT.PALL
UICR
DAP bus
interconnect
AHB
AHB-AP
CxxxPWRUPREQ
CxxxPWRUPRACK
POWER
RAM & Flash
CPU
Power
ARM Cortex-M4
TRACECLK
Trace
TRACEDATA[0] / SWO
APB/AHB
ETM
Peripherals
TRACEDATA[1]
TRACEDATA[2]
TPIU
TRACEDATA[3]
Trace
ITM
Figure 11: Debug and trace overview
The main features of the debug and trace system are:
•
•
Two-pin Serial Wire Debug (SWD) interface
Flash Patch and Breakpoint Unit (FPB) supports:
•
• Two literal comparators
• Six instruction comparators
Data Watchpoint and Trace Unit (DWT)
•
•
•
• Four comparators
Instrumentation Trace Macrocell (ITM)
Embedded Trace Macrocell (ETM)
Trace Port Interface Unit (TPIU)
•
•
4-bit parallel trace of ITM and ETM trace data
Serial Wire Output (SWO) trace of ITM data
16.1 DAP - Debug Access Port
An external debugger can access the device via the DAP.
The DAP implements a standard ARM® CoreSight™ Serial Wire Debug Port (SW-DP).
The SW-DP implements the Serial Wire Debug protocol (SWD) that is a two-pin serial interface, see
SWDCLK and SWDIO in Figure 11: Debug and trace overview on page 72.
In addition to the default access port in the CPU (AHB-AP), the DAP includes a custom Control Access Port
(CTRL-AP). The CTRL-AP is described in more detail in CTRL-AP - Control Access Port on page 73.
Important:
•
•
The SWDIO line has an internal pull-up resistor.
The SWDCLK line has an internal pull-down resistor.
Page 72
16 Debug and trace
16.2 CTRL-AP - Control Access Port
The Control Access Port (CTRL-AP) is a custom access port that enables control of the device even if the
other access ports in the DAP are being disabled by the access port protection.
Access port protection blocks the debugger from read and write access to all CPU registers and memorymapped addresses. See the UICR register APPROTECT on page 66 for more information about enabling
access port protection.
This access port enables the following features:
•
•
Soft reset, see Reset on page 82 for more information
Disable access port protection
Access port protection can only be disabled by issuing an ERASEALL command via CTRL-AP. This
command will erase the Flash, UICR, and RAM.
16.2.1 Registers
Table 21: Register Overview
Register
Offset
Description
RESET
0x000
Soft reset triggered through CTRL-AP
ERASEALL
0x004
Erase all
ERASEALLSTATUS
0x008
Status register for the ERASEALL operation
APPROTECTSTATUS
0x00C
Status register for access port protection
IDR
0x0FC
CTRL-AP Identification Register, IDR
RESET
Address offset: 0x000
Soft reset triggered through CTRL-AP
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW RESET
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Soft reset triggered through CTRL-AP. See Reset Behaviour in
POWER chapter for more details.
NoReset
0
Reset is not active
Reset
1
Reset is active. Device is held in reset
ERASEALL
Address offset: 0x004
Erase all
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
W
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NoOperation
0
No operation
Erase
1
Erase all FLASH and RAM
ERASEALL
Erase all FLASH and RAM
ERASEALLSTATUS
Address offset: 0x008
Status register for the ERASEALL operation
Page 73
16 Debug and trace
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Ready
0
ERASEALL is ready
Busy
1
ERASEALL is busy (on-going)
ERASEALLSTATUS
Status register for the ERASEALL operation
APPROTECTSTATUS
Address offset: 0x00C
Status register for access port protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
0
Access port protection enabled
Disabled
1
Access port protection not enabled
APPROTECTSTATUS
Status register for access port protection
IDR
Address offset: 0x0FC
CTRL-AP Identification Register, IDR
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E
E E E D D D D C C C C C C C B B B B
Reset 0x02880000
0
0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
R
APID
B
R
CLASS
Value Id
Value
A A A A A A A A
Description
AP Identification
Access Port (AP) class
NotDefined
0x0
No defined class
MEMAP
0x8
Memory Access Port
C
R
JEP106ID
JEDEC JEP106 identity code
D
R
JEP106CONT
JEDEC JEP106 continuation code
E
R
REVISION
Revision
16.3 Debug interface mode
Before the external debugger can access the CPU's access port (AHB-AP) or the Control Access Port
(CTRL-AP), the debugger must first request the device to power up via CxxxPWRUPREQ in the SWJ-DP.
As long as the debugger is requesting power via CxxxPWRUPREQ, the device will be in debug interface
mode. If the debugger is not requesting power via CxxxPWRUPREQ, the device will be in normal mode.
Some peripherals will behave differently in debug interface mode compared to normal mode. These
differences are described in more detail in the chapters of the peripherals that are affected.
When a debug session is over, the external debugger must make sure to put the device back into normal
mode since the overall power consumption will be higher in debug interface mode compared to normal
mode.
For details on how to use the debug capabilities please read the debug documentation of your IDE.
If the device is in System OFF when power is requested via CxxxPWRUPREQ, the system will wake up and
the DIF flag in RESETREAS on page 85 will be set.
16.4 Real-time debug
The nRF52832 supports real-time debugging.
Page 74
16 Debug and trace
Real-time debugging will allow interrupts to execute to completion in real time when breakpoints are set
in Thread mode or lower priority interrupts. This enables the developer to set a breakpoint and singlestep through their code without a failure of the real-time event-driven threads running at higher priority. For
example, this enables the device to continue to service the high-priority interrupts of an external controller or
sensor without failure or loss of state synchronization while the developer steps through code in a low-priority
thread.
16.5 Trace
The device supports ETM and ITM trace.
Trace data from the ETM and the ITM is sent to an external debugger via a 4-bit wide parallel trace port
(TPIU), see TRACEDATA[0] through TRACEDATA[3] and TRACECLK in Figure 11: Debug and trace
overview on page 72.
In addition to parallel trace, the TPIU supports serial trace via the Serial Wire Output (SWO) trace protocol.
Parallel and serial trace cannot be used at the same time.
ETM trace is only supported in parallel trace mode while ITM trace is supported in both parallel and serial
trace modes.
For details on how to use the trace capabilities, please read the debug documentation of your IDE.
TPIU's trace pins are multiplexed with GPIOs, and SWO and TRACEDATA[0] use the same GPIO, see Pin
assignments on page 13 for more information.
Trace speed is configured in the TRACECONFIG on page 108 register.
The speed of the trace pins depends on the DRIVE setting of the GPIOs that the trace pins are multiplexed
with, see PIN_CNF[14] on page 142, PIN_CNF[15] on page 143, PIN_CNF[16] on page 144,
PIN_CNF[18] on page 145 and PIN_CNF[20] on page 146. Only S0S1 and H0H1 drives are suitable
for debugging. S0S1 is the default DRIVE at reset. If parallel or serial trace port signals are not fast enough
in the debugging conditions, all GPIOs in use for tracing should be set to high drive (H0H1). The user shall
make sure that these GPIOs' DRIVE is not overwritten by software during the debugging session.
16.5.1 Electrical specification
Trace port
Symbol
Description
Min.
Tcyc
Clock period, as defined by ARM (See ARM Infocenter,
62.5
Embedded Trace Macrocell Architecture Specification, Trace
Port Physical Interface, Timing specifications)
Page 75
Typ.
Max.
Units
500
ns
17 Power and clock management
17 Power and clock management
Power and clock management in nRF52832 is optimized for ultra-low power applications.
The core of the power and clock management system is the Power Management Unit (PMU) illustrated in
Figure 12: Power Management Unit on page 76.
MCU
CPU
External
Power sources
Internal
voltage
regulators
PMU
Memory
External
crystals
Internal
oscillators
Peripheral
Figure 12: Power Management Unit
The user application is not required to actively control power and clock, since the PMU is able to
automatically detect which resources are required by the different components in the system at any given
time. The PMU will continuously optimize the system based on this information to achieve the lowest power
consumption possible without user interaction.
17.1 Current consumption scenarios
As the system is being constantly tuned by the PMU, estimating the energy consumption of an application
can be challenging if the designer is not able to do measurements on the hardware directly. See Electrical
specification on page 76 for application scenarios showing average current drawn from the VDD supply.
Each scenario specifies a set of active operations and conditions applying to the given scenario. Table 22:
Current consumption scenarios, common conditions on page 76 shows the conditions used for a scenario
unless otherwise is stated in the scenario description.
Table 22: Current consumption scenarios, common conditions
Condition
VDD
Temperature
CPU
Peripherals
Clock
Regulator
Value
3V
25°C
WFI/WFE sleep
All idle
Not running
DCDC
17.1.1 Electrical specification
Current consumption: Radio
Symbol
Description
IRADIO_TX0
0 dBm TX @ 1 Mb/s Bluetooth Low Energy mode, Clock = HFXO
Min.
Typ.
7.1
Max.
Units
mA
IRADIO_TX1
-40 dBm TX @ 1 Mb/s Bluetooth Low Energy mode, Clock =
4.1
mA
6.5
mA
HFXO
IRADIO_RX0
Radio RX @ 1 Mb/s Bluetooth Low Energy mode, Clock = HFXO
Page 76
17 Power and clock management
Current consumption: Radio protocol configurations
Symbol
Description
IS0
CPU running CoreMark from Flash, Radio 0 dBm TX @ 1 Mb/s
Min.
Typ.
Max.
Units
9.6
mA
9.0
mA
Bluetooth Low Energy mode, Clock = HFXO, Cache enabled
IS1
CPU running CoreMark from Flash, Radio RX @ 1 Mb/s
Bluetooth Low Energy mode, Clock = HFXO, Cache enabled
Current consumption: Ultra-low power
Symbol
Description
ION_RAMOFF_EVENT
System ON, No RAM retention, Wake on any event
Min.
1.2
µA
ION_RAMON_EVENT
System ON, Full RAM retention, Wake on any event
1.5
µA
ION_RAMOFF_RTC
System ON, No RAM retention, Wake on RTC
1.9
µA
IOFF_RAMOFF_RESET
System OFF, No RAM retention, Wake on reset
0.7
µA
IOFF_RAMOFF_GPIO
System OFF, No RAM retention, Wake on GPIO
1.2
µA
IOFF_RAMOFF_LPCOMP
System OFF, No RAM retention, Wake on LPCOMP
1.9
µA
IOFF_RAMOFF_NFC
System OFF, No RAM retention, Wake on NFC field
0.7
µA
IOFF_RAMON_RESET
System OFF, Full RAM retention, Wake on reset
1.0
µA
Page 77
Typ.
Max.
Units
18 POWER — Power supply
18 POWER — Power supply
This device has the following power supply features:
•
•
•
•
•
•
•
On-chip LDO and DC/DC regulators
Global System ON/OFF modes
Individual RAM section power control for all system modes
Analog or digital pin wakeup from System OFF
Supervisor HW to manage power on reset, brownout, and power fail
Auto-controlled refresh modes for LDO and DC/DC regulators to maximize efficiency
Automatic switching between LDO and DC/DC regulator based on load to maximize efficiency
Note: Two additional external passive components are required to use the DC/DC regulator.
18.1 Regulators
The following internal power regulator alternatives are supported:
•
•
Internal LDO regulator
Internal DC/DC regulator
The LDO is the default regulator.
The DC/DC regulator can be used as an alternative to the LDO regulator and is enabled through the
DCDCEN on page 88 register. Using the DC/DC regulator will reduce current consumption compared to
when using the LDO regulator, but the DC/DC regulator requires an external LC filter to be connected, as
shown in Figure 14: DC/DC regulator setup on page 79.
POWER
DCDCEN
REG
Supply
LDO
1.3V System power
VDD
DC/DC
DCC
Figure 13: LDO regulator setup
Page 78
DEC4
GND
18 POWER — Power supply
POWER
DCDCEN
REG
Supply
LDO
1.3V System power
VDD
DC/DC
DCC
DEC4
GND
Figure 14: DC/DC regulator setup
18.2 System OFF mode
System OFF is the deepest power saving mode the system can enter. In this mode, the system’s core
functionality is powered down and all ongoing tasks are terminated.
The device can be put into System OFF mode using the POWER register interface. When in System OFF
mode, the device can be woken up through one of the following signals:
1.
2.
3.
4.
The DETECT signal, optionally generated by the GPIO peripheral
The ANADETECT signal, optionally generated by the LPCOMP module
The SENSE signal, optionally generated by the NFC module to “wake-on-field”
A reset
When the system wakes up from System OFF mode, it gets reset. For more details, see Reset behavior on
page 83.
One or more RAM sections can be retained in System OFF mode depending on the settings in the
RAM[n].POWER registers.
RAM[n].POWER are retained registers, see Reset behavior. Note that these registers are usually overwritten
by the startup code provided with the nRF application examples.
Before entering System OFF mode, the user must make sure that all on-going EasyDMA transactions have
been completed. This is usually accomplished by making sure that the EasyDMA enabled peripheral is not
active when entering System OFF.
18.2.1 Emulated System OFF mode
If the device is in debug interface mode, System OFF will be emulated to secure that all required resources
needed for debugging are available during System OFF.
See Debug and trace on page 72 for more information. Required resources needed for debugging include
the following key components: Debug and trace on page 72, CLOCK — Clock control on page 101,
POWER — Power supply on page 78, NVMC — Non-volatile memory controller on page 29, CPU, Flash,
and RAM. Since the CPU is kept on in an emulated System OFF mode, it is recommended to add an infinite
loop directly after entering System OFF, to prevent the CPU from executing code that normally should not be
executed.
Page 79
18 POWER — Power supply
18.3 System ON mode
System ON is the default state after power-on reset. In System ON, all functional blocks such as the CPU or
peripherals, can be in IDLE or RUN mode, depending on the configuration set by the software and the state
of the application executing.
Register RESETREAS on page 85 provides information about the source that caused the wakeup or
reset.
The system can switch on and off the appropriate internal power sources, depending on how much power is
needed at any given time. The power requirement of a peripheral is directly related to its activity level, and
the activity level of a peripheral is usually raised and lowered when specific tasks are triggered or events are
generated.
18.3.1 Sub power modes
In System ON mode, when both the CPU and all the peripherals are in IDLE mode, the system can reside in
one of the two sub power modes.
The sub power modes are:
•
•
Constant latency
Low power
In constant latency mode the CPU wakeup latency and the PPI task response will be constant and kept at
a minimum. This is secured by forcing a set of base resources on while in sleep. The advantage of having
a constant and predictable latency will be at the cost of having increased power consumption. The constant
latency mode is selected by triggering the CONSTLAT task.
In low power mode the automatic power management system, described in System ON mode on page
80, ensures the most efficient supply option is chosen to save the most power. The advantage of having
the lowest power possible will be at the cost of having varying CPU wakeup latency and PPI task response.
The low power mode is selected by triggering the LOWPWR task.
When the system enters System ON mode, it will, by default, reside in the low power sub-power mode.
18.4 Power supply supervisor
The power supply supervisor initializes the system at power-on and provides an early warning of impending
power failure.
In addition, the power supply supervisor puts the system in a reset state if the supply voltage is too low for
safe operation (brownout). The power supply supervisor is illustrated in Figure 15: Power supply supervisor
on page 81.
Page 80
18 POWER — Power supply
VDD
C
Power on reset
R
VBOR
POFCON
Brownout reset
1.7V
...........
MUX
POFWARN
Vpof
2.8V
Figure 15: Power supply supervisor
18.4.1 Power-fail comparator
The power-fail comparator (POF) can provide the CPU with an early warning of impending power failure. It
will not reset the system, but give the CPU time to prepare for an orderly power-down.
The comparator features a hysteresis of VHYST, as illustrated in Figure 16: Power-fail comparator (BOR =
Brownout reset) on page 81. The threshold VPOF is set in register POFCON on page 86. If the POF
is enabled and the supply voltage falls below VPOF, the POFWARN event will be generated. This event will
also be generated if the supply voltage is already below VPOF at the time the POF is enabled, or if VPOF is reconfigured to a level above the supply voltage.
If power-fail warning is enabled and the supply voltage is below VPOF the power-fail comparator will prevent
the NVMC from performing write operations to the NVM. See NVMC — Non-volatile memory controller on
page 29 for more information about the NVMC.
VDD
VPOF+VHYST
VPOF
1.7V
POFWARN
POFWARN
MCU
t
BOR
Figure 16: Power-fail comparator (BOR = Brownout reset)
To save power, the power-fail comparator is not active in System OFF or in System ON when HFCLK is not
running.
Page 81
18 POWER — Power supply
18.5 RAM sections
RAM section power control is used for retention in System OFF mode and for powering down unused
sections in System ON mode.
Each RAM section can power up and down independently in both System ON and System OFF mode. See
chapter Memory on page 23 for more information on RAM sections.
18.6 Reset
There are multiple sources that may trigger a reset.
After a reset has occurred, register RESETREAS can be read to determine which source generated the
reset.
18.6.1 Power-on reset
The power-on reset generator initializes the system at power-on.
The system is held in reset state until the supply has reached the minimum operating voltage and the internal
voltage regulators have started.
A step increase in supply voltage of 300 mV or more, with rise time of 300 ms or less, within the valid supply
range, may result in a system reset.
18.6.2 Pin reset
A pin reset is generated when the physical reset pin on the device is asserted.
Pin reset is configured via the PSELRESET[0] and PSELRESET[1] registers.
Note: Pin reset is not available on all pins.
18.6.3 Wakeup from System OFF mode reset
The device is reset when it wakes up from System OFF mode.
The DAP is not reset following a wake up from System OFF mode if the device is in debug interface mode.
Refer to chapter Debug and trace on page 72 for more information.
18.6.4 Soft reset
A soft reset is generated when the SYSRESETREQ bit of the Application Interrupt and Reset Control
Register (AIRCR register) in the ARM® core is set.
Refer to ARM documentation for more details.
A soft reset can also be generated via the RESET on page 73 register in the CTRL-AP.
18.6.5 Watchdog reset
A Watchdog reset is generated when the watchdog times out.
Refer to chapter WDT — Watchdog timer on page 409 for more information.
18.6.6 Brown-out reset
The brown-out reset generator puts the system in reset state if the supply voltage drops below the brownout
reset (BOR) threshold.
Refer to section Power fail comparator on page 99 for more information.
Page 82
18 POWER — Power supply
18.7 Retained registers
A retained register is a register that will retain its value in System OFF mode and through a reset, depending
on reset source. See individual peripheral chapters for information of which registers are retained for the
various peripherals.
18.8 Reset behavior
Reset source
6
CPU lockup
Soft reset
Wakeup from System OFF mode
reset
Watchdog reset 9
Pin reset
Brownout reset
Power on reset
Reset target
CPU
Peripherals
GPIO
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Debuga
SWJ-DP
RAM
x7
x8
x
x
x
x
x
x
x
x
x
x
WDT
Retained
registers
x
x
x
x
x
x
x
x
RESETREAS
x
x
Note: The RAM is never reset, but depending on reset source, RAM content may be corrupted.
18.9 Registers
Table 23: Instances
Base address
Peripheral
Instance
Description
0x40000000
POWER
POWER
Power control
Configuration
Table 24: Register Overview
Register
Offset
Description
TASKS_CONSTLAT
0x078
Enable constant latency mode
TASKS_LOWPWR
0x07C
Enable low power mode (variable latency)
EVENTS_POFWARN
0x108
Power failure warning
EVENTS_SLEEPENTER
0x114
CPU entered WFI/WFE sleep
EVENTS_SLEEPEXIT
0x118
CPU exited WFI/WFE sleep
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
RESETREAS
0x400
Reset reason
RAMSTATUS
0x428
RAM status register
SYSTEMOFF
0x500
System OFF register
POFCON
0x510
Power failure comparator configuration
GPREGRET
0x51C
General purpose retention register
GPREGRET2
0x520
General purpose retention register
RAMON
0x524
RAM on/off register (this register is retained)
Deprecated
RAMONB
0x554
RAM on/off register (this register is retained)
Deprecated
DCDCEN
0x578
DC/DC enable register
RAM[0].POWER
0x900
RAM0 power control register
a
6
7
8
9
Deprecated
All debug components excluding SWJ-DP. See Debug and trace on page 72 chapter for more
information about the different debug components in the system.
Reset from CPU lockup is disabled if the device is in debug interface mode. CPU lockup is not possible in System
OFF.
The Debug components will not be reset if the device is in debug interface mode.
RAM is not reset on wakeup from OFF mode, but depending on settings in the RAM register parts, or the whole
RAM, may not be retained after the device has entered System OFF mode.
Watchdog reset is not available in System OFF.
Page 83
18 POWER — Power supply
Register
Offset
Description
RAM[0].POWERSET
0x904
RAM0 power control set register
RAM[0].POWERCLR
0x908
RAM0 power control clear register
RAM[1].POWER
0x910
RAM1 power control register
RAM[1].POWERSET
0x914
RAM1 power control set register
RAM[1].POWERCLR
0x918
RAM1 power control clear register
RAM[2].POWER
0x920
RAM2 power control register
RAM[2].POWERSET
0x924
RAM2 power control set register
RAM[2].POWERCLR
0x928
RAM2 power control clear register
RAM[3].POWER
0x930
RAM3 power control register
RAM[3].POWERSET
0x934
RAM3 power control set register
RAM[3].POWERCLR
0x938
RAM3 power control clear register
RAM[4].POWER
0x940
RAM4 power control register
RAM[4].POWERSET
0x944
RAM4 power control set register
RAM[4].POWERCLR
0x948
RAM4 power control clear register
RAM[5].POWER
0x950
RAM5 power control register
RAM[5].POWERSET
0x954
RAM5 power control set register
RAM[5].POWERCLR
0x958
RAM5 power control clear register
RAM[6].POWER
0x960
RAM6 power control register
RAM[6].POWERSET
0x964
RAM6 power control set register
RAM[6].POWERCLR
0x968
RAM6 power control clear register
RAM[7].POWER
0x970
RAM7 power control register
RAM[7].POWERSET
0x974
RAM7 power control set register
RAM[7].POWERCLR
0x978
RAM7 power control clear register
18.9.1 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B
Reset 0x00000000
Id
RW Field
A
RW POFWARN
0
Value Id
Value
Description
Write '1' to Enable interrupt for POFWARN event
See EVENTS_POFWARN
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SLEEPENTER
Write '1' to Enable interrupt for SLEEPENTER event
See EVENTS_SLEEPENTER
C
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SLEEPEXIT
Write '1' to Enable interrupt for SLEEPEXIT event
See EVENTS_SLEEPEXIT
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
18.9.2 INTENCLR
Address offset: 0x308
Disable interrupt
Page 84
18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B
Reset 0x00000000
Id
RW Field
A
RW POFWARN
0
Value Id
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for POFWARN event
See EVENTS_POFWARN
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SLEEPENTER
Write '1' to Disable interrupt for SLEEPENTER event
See EVENTS_SLEEPENTER
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SLEEPEXIT
Write '1' to Disable interrupt for SLEEPEXIT event
See EVENTS_SLEEPEXIT
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
18.9.3 RESETREAS
Address offset: 0x400
Reset reason
Unless cleared, the RESETREAS register will be cumulative. A field is cleared by writing '1' to it. If none of
the reset sources are flagged, this indicates that the chip was reset from the on-chip reset generator, which
will indicate a power-on-reset or a brownout reset.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G F E
Reset 0x00000000
Id
RW Field
A
RW RESETPIN
B
C
D
E
0
Value Id
Value
Description
NotDetected
0
Not detected
Detected
1
Detected
NotDetected
0
Not detected
Detected
1
Detected
NotDetected
0
Not detected
Detected
1
Detected
NotDetected
0
Not detected
Detected
1
Detected
Reset from pin-reset detected
RW DOG
Reset from watchdog detected
RW SREQ
Reset from soft reset detected
RW LOCKUP
Reset from CPU lock-up detected
RW OFF
Reset due to wake up from System OFF mode when wakeup is
triggered from DETECT signal from GPIO
F
NotDetected
0
Not detected
Detected
1
Detected
RW LPCOMP
Reset due to wake up from System OFF mode when wakeup is
triggered from ANADETECT signal from LPCOMP
G
D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NotDetected
0
Not detected
Detected
1
Detected
RW DIF
Reset due to wake up from System OFF mode when wakeup is
triggered from entering into debug interface mode
NotDetected
0
Not detected
Detected
1
Detected
Page 85
18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G F E
Reset 0x00000000
Id
RW Field
H
RW NFC
0
Value Id
D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Reset due to wake up from System OFF mode by NFC field
detect
NotDetected
0
Not detected
Detected
1
Detected
18.9.4 RAMSTATUS ( Deprecated )
Address offset: 0x428
RAM status register
Since this register is deprecated the following substitutions have been made: RAM block 0 is equivalent to
a block comprising RAM0.S0 and RAM1.S0, RAM block 1 is equivalent to a block comprising RAM2.S0 and
RAM3.S0, RAM block 2 is equivalent to a block comprising RAM4.S0 and RAM5.S0 and RAM block 3 is
equivalent to a block comprising RAM6.S0 and RAM7.S0. A RAM block field will indicate ON as long as any
of the RAM sections associated with a block are on.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C B A
Reset 0x00000000
Id
RW Field
A
R
B
C
D
R
R
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RAMBLOCK0
RAM block 0 is on or off/powering up
RAMBLOCK1
RAM block 1 is on or off/powering up
RAMBLOCK2
RAM block 2 is on or off/powering up
RAMBLOCK3
RAM block 3 is on or off/powering up
18.9.5 SYSTEMOFF
Address offset: 0x500
System OFF register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
W
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Enter
1
Description
SYSTEMOFF
Enable System OFF mode
Enable System OFF mode
18.9.6 POFCON
Address offset: 0x510
Power failure comparator configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B B B B A
Reset 0x00000000
Id
RW Field
A
RW POF
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Disabled
0
Description
Enable or disable power failure comparator
Disable
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18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B B B B A
Reset 0x00000000
Id
B
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Enable
V17
4
Set threshold to 1.7 V
V18
5
Set threshold to 1.8 V
V19
6
Set threshold to 1.9 V
V20
7
Set threshold to 2.0 V
V21
8
Set threshold to 2.1 V
V22
9
Set threshold to 2.2 V
V23
10
Set threshold to 2.3 V
V24
11
Set threshold to 2.4 V
V25
12
Set threshold to 2.5 V
V26
13
Set threshold to 2.6 V
V27
14
Set threshold to 2.7 V
V28
15
Set threshold to 2.8 V
RW THRESHOLD
Power failure comparator threshold setting
18.9.7 GPREGRET
Address offset: 0x51C
General purpose retention register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW GPREGRET
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
General purpose retention register
This register is a retained register
18.9.8 GPREGRET2
Address offset: 0x520
General purpose retention register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW GPREGRET
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
General purpose retention register
This register is a retained register
18.9.9 RAMON ( Deprecated )
Address offset: 0x524
RAM on/off register (this register is retained)
Since this register is deprecated the following substitutions have been made: RAM block 0 is equivalent to
a block comprising RAM0.S0 and RAM0.S1 and RAM block 1 is equivalent to a block comprising RAM1.S0
and RAM1.S1. For new designs it is recommended to use the POWER.RAM-0.POWER and its sibling
registers instead.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x00000003
Id
RW Field
A
RW ONRAM0
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Value Id
Value
RAM0Off
0
Description
Keep RAM block 0 on or off in system ON Mode
Off
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18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x00000003
Id
B
C
D
RW Field
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Value Id
Value
Description
RAM0On
1
On
RAM1Off
0
Off
RAM1On
1
On
RAM0Off
0
Off
RAM0On
1
On
RAM1Off
0
Off
RAM1On
1
On
RW ONRAM1
Keep RAM block 1 on or off in system ON Mode
RW OFFRAM0
Keep retention on RAM block 0 when RAM block is switched off
RW OFFRAM1
Keep retention on RAM block 1 when RAM block is switched off
18.9.10 RAMONB ( Deprecated )
Address offset: 0x554
RAM on/off register (this register is retained)
Since this register is deprecated the following substitutions have been made: RAM block 2 is equivalent to
a block comprising RAM2.S0 and RAM2.S1 and RAM block 3 is equivalent to a block comprising RAM3.S0
and RAM3.S1. For new designs it is recommended to use the POWER.RAM-0.POWER and its sibling
registers instead.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x00000003
Id
RW Field
A
RW ONRAM2
B
C
D
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Value Id
Value
Description
RAM2Off
0
Off
RAM2On
1
On
RAM3Off
0
Off
RAM3On
1
On
RAM2Off
0
Off
RAM2On
1
On
RAM3Off
0
Off
RAM3On
1
On
Keep RAM block 2 on or off in system ON Mode
RW ONRAM3
Keep RAM block 3 on or off in system ON Mode
RW OFFRAM2
Keep retention on RAM block 2 when RAM block is switched off
RW OFFRAM3
Keep retention on RAM block 3 when RAM block is switched off
18.9.11 DCDCEN
Address offset: 0x578
DC/DC enable register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW DCDCEN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Enable or disable DC/DC converter
18.9.12 RAM[0].POWER
Address offset: 0x900
RAM0 power control register
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18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
18.9.13 RAM[0].POWERSET
Address offset: 0x904
RAM0 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM0 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM0 on or off in System ON mode
On
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
D
W
1
On
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
1
On
18.9.14 RAM[0].POWERCLR
Address offset: 0x908
RAM0 power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Off
1
Description
S0POWER
Keep RAM section S0 of RAM0 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM0 on or off in System ON mode
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18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
C
RW Field
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Description
Off
1
Off
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
1
Off
18.9.15 RAM[1].POWER
Address offset: 0x910
RAM1 power control register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
18.9.16 RAM[1].POWERSET
Address offset: 0x914
RAM1 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM1 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM1 on or off in System ON mode
On
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
On
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18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
D
W
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
1
On
18.9.17 RAM[1].POWERCLR
Address offset: 0x918
RAM1 power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Off
1
Off
1
Description
S0POWER
Keep RAM section S0 of RAM1 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM1 on or off in System ON mode
Off
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
1
Off
18.9.18 RAM[2].POWER
Address offset: 0x920
RAM2 power control register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
Page 91
18 POWER — Power supply
18.9.19 RAM[2].POWERSET
Address offset: 0x924
RAM2 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM2 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM2 on or off in System ON mode
On
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
D
W
1
On
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
1
On
18.9.20 RAM[2].POWERCLR
Address offset: 0x928
RAM2 power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Off
1
Off
1
Description
S0POWER
Keep RAM section S0 of RAM2 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM2 on or off in System ON mode
Off
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
1
Off
18.9.21 RAM[3].POWER
Address offset: 0x930
RAM3 power control register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
Page 92
18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
18.9.22 RAM[3].POWERSET
Address offset: 0x934
RAM3 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM3 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM3 on or off in System ON mode
On
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
D
W
1
On
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
1
On
18.9.23 RAM[3].POWERCLR
Address offset: 0x938
RAM3 power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
Value Id
Value
Off
1
Off
1
Description
S0POWER
Keep RAM section S0 of RAM3 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM3 on or off in System ON mode
Off
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
Off
Page 93
18 POWER — Power supply
18.9.24 RAM[4].POWER
Address offset: 0x940
RAM4 power control register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
18.9.25 RAM[4].POWERSET
Address offset: 0x944
RAM4 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM4 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM4 on or off in System ON mode
On
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
D
W
1
On
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
On
18.9.26 RAM[4].POWERCLR
Address offset: 0x948
RAM4 power control clear register
When read, this register will return the value of the POWER register.
Page 94
18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Off
1
Off
1
Description
S0POWER
Keep RAM section S0 of RAM4 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM4 on or off in System ON mode
Off
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
1
Off
18.9.27 RAM[5].POWER
Address offset: 0x950
RAM5 power control register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
18.9.28 RAM[5].POWERSET
Address offset: 0x954
RAM5 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM5 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM5 on or off in System ON mode
On
Page 95
18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
C
W
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
D
W
1
On
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
1
On
18.9.29 RAM[5].POWERCLR
Address offset: 0x958
RAM5 power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Off
1
Off
1
Description
S0POWER
Keep RAM section S0 of RAM5 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM5 on or off in System ON mode
Off
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
1
Off
18.9.30 RAM[6].POWER
Address offset: 0x960
RAM6 power control register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
Off
Page 96
18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Description
On
1
On
18.9.31 RAM[6].POWERSET
Address offset: 0x964
RAM6 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM6 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM6 on or off in System ON mode
On
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
D
W
1
On
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
1
On
18.9.32 RAM[6].POWERCLR
Address offset: 0x968
RAM6 power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Off
1
Off
1
Description
S0POWER
Keep RAM section S0 of RAM6 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM6 on or off in System ON mode
Off
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
1
Off
18.9.33 RAM[7].POWER
Address offset: 0x970
RAM7 power control register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
Page 97
18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
18.9.34 RAM[7].POWERSET
Address offset: 0x974
RAM7 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM7 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM7 on or off in System ON mode
On
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
D
W
1
On
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
1
On
18.9.35 RAM[7].POWERCLR
Address offset: 0x978
RAM7 power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Off
1
Off
1
Description
S0POWER
Keep RAM section S0 of RAM7 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM7 on or off in System ON mode
Off
Page 98
18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
C
W
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
1
Off
18.10 Electrical specification
18.10.1 Current consumption, sleep
Symbol
Description
IOFF
System OFF current, no RAM retention
Min.
Typ.
0.7
Max.
Units
µA
ION
System ON base current, no RAM retention
1.2
µA
IRAM
Additional RAM retention current per 4 KB RAM section
20
nA
18.10.2 Device startup times
Symbol
Description
tPOR
Time in Power on Reset after VDD reaches 1.7 V for all supply
Min.
Typ.
Max.
Units
voltages and temperatures. Dependent on supply rise time. 10
tPOR,10us
VDD rise time 10us
1
ms
tPOR,10ms
VDD rise time 10ms
9
ms
tPOR,60ms
VDD rise time 60ms
23
ms
tPINR
If a GPIO pin is configured as reset, the maximum time taken
to pull up the pin and release reset after power on reset.
Dependent on the pin capacitive load (C)11: t=5RC, R = 13kOhm
tPINR,500nF
C = 500nF
32.5
ms
tPINR,10uF
C = 10uF
650
ms
tR2ON
Time from reset to ON (CPU execute)
tR2ON,NOTCONF
If reset pin not configured
tPOR
ms
tR2ON,CONF
If reset pin configured
tPOR +
ms
tPINR
tOFF2ON
Time from OFF to CPU execute
16.5
µs
tIDLE2CPU
Time from IDLE to CPU execute
3.0
µs
tEVTSET,CL1
Time from HW event to PPI event in Constant Latency System
0.0625
µs
0.0625
µs
ON mode
tEVTSET,CL0
Time from HW event to PPI event in Low Power System ON
mode
18.10.3 Power fail comparator
Symbol
Description
IPOF
Current consumption when enabled12
Min.
VPOF
Nominal power level warning thresholds (falling supply voltage).
Typ.
Max.
<4
1.7
Units
µA
2.8
V
±5
%
Levels are configurable between Min. and Max. in 100mV
increments.
VPOFTOL
10
11
12
Threshold voltage tolerance
±1
A step increase in supply voltage of 300 mV or more, with rise time of 300 ms or less, within the valid supply
range, may result in a system reset.
To decrease maximum time a device could hold in reset, a strong external pullup resistor can be used.
To save power, POF will not operate nor consume in System OFF, or while HFCLK is not running, even if left
enabled by software
Page 99
18 POWER — Power supply
Symbol
Description
VPOFHYST
Threshold voltage hysteresis
Min.
Typ.
Max.
VBOR,OFF
Brown out reset voltage range SYSTEM OFF mode
1.2
1.7
V
VBOR,ON
Brown out reset voltage range SYSTEM ON mode
1.5
1.7
V
50
Page 100
Units
mV
19 CLOCK — Clock control
19 CLOCK — Clock control
The clock control system can source the system clocks from a range of internal or external high and low
frequency oscillators and distribute them to modules based upon a module’s individual requirements. Clock
distribution is automated and grouped independently by module to limit current consumption in unused
branches of the clock tree.
Listed here are the main features for CLOCK:
•
•
•
•
•
•
•
64 MHz on-chip oscillator
64 MHz crystal oscillator, using external 32 MHz crystal
32.768 kHz +/-250 ppm RC oscillator
32.768 kHz crystal oscillator, using external 32.768 kHz crystal
32.768 kHz oscillator synthesized from 64 MHz oscillator
Firmware (FW) override control of oscillator activity for low latency start up
Automatic oscillator and clock control, and distribution for ultra-low power
HFCLKSTART
HFCLKSTOP
LFCLKSTART
LFCLKSTOP
CLOCK
HFINT
Internal oscillator
PCLK1M
PCLK16M
XC1
PCLK32M
HFCLK
Clock control
HFXO
Crystal oscillator
32 MHz
HCLK64M
XC2
LFRC
RC oscillator
CAL
SYNT
XL1
LFXO
Crystal oscillator
32.768 kHz
LFCLK
Clock control
PCLK32KI
XL2
HFCLKSTARTED
LFCLKSTARTED
Figure 17: Clock control
19.1 HFCLK clock controller
The HFCLK clock controller provides the following clocks to the system.
•
•
•
•
HCLK64M: 64 MHz CPU clock
PCLK1M: 1 MHz peripheral clock
PCLK16M: 16 MHz peripheral clock
PCLK32M: 32 MHz peripheral clock
The HFCLK controller supports the following high frequency clock (HFCLK) sources:
•
•
64 MHz internal oscillator (HFINT)
64 MHz crystal oscillator (HFXO)
For illustration, see Figure 17: Clock control on page 101.
Page 101
19 CLOCK — Clock control
When the system requests one or more clocks from the HFCLK controller, the HFCLK controller will
automatically provide them. If the system does not request any clocks provided by the HFCLK controller, the
controller will enter a power saving mode.
These clocks are only available when the system is in ON mode. When the system enters ON mode, the
internal oscillator (HFINT) clock source will automatically start to be able to provide the required HFCLK
clock(s) for the system.
The HFINT will be used when HFCLK is requested and HFXO has not been started. The HFXO is started by
triggering the HFCLKSTART task and stopped using the HFCLKSTOP task. A HFCLKSTARTED event will
be generated when the HFXO has started and its frequency is stable.
The HFXO must be running to use the RADIO, NFC module or the calibration mechanism associated with
the 32.768 kHz RC oscillator.
19.1.1 64 MHz crystal oscillator (HFXO)
The 64 MHz crystal oscillator (HFXO) is controlled by a 32 MHz external crystal
The crystal oscillator is designed for use with an AT-cut quartz crystal in parallel resonant mode. To achieve
correct oscillation frequency, the load capacitance must match the specification in the crystal data sheet.
Figure 18: Circuit diagram of the 64 MHz crystal oscillator on page 102 shows how the 32 MHz crystal is
connected to the 64 MHz crystal oscillator.
XC1
XC2
C1
C2
32 MHz
crystal
Figure 18: Circuit diagram of the 64 MHz crystal oscillator
The load capacitance (CL) is the total capacitance seen by the crystal across its terminals and is given by:
C1 and C2 are ceramic SMD capacitors connected between each crystal terminal and ground. For more
information, see Reference circuitry on page 545. Cpcb1 and Cpcb2 are stray capacitances on the PCB. Cpin
is the pin input capacitance on the XC1 and XC2 pins. See table 64 MHz crystal oscillator (HFXO) on page
109. The load capacitors C1 and C2 should have the same value.
For reliable operation, the crystal load capacitance, shunt capacitance, equivalent series resistance, and
drive level must comply with the specifications in table 64 MHz crystal oscillator (HFXO) on page 109. It is
recommended to use a crystal with lower than maximum load capacitance and/or shunt capacitance. A low
load capacitance will reduce both start up time and current consumption.
Page 102
19 CLOCK — Clock control
19.2 LFCLK clock controller
The system supports several low frequency clock sources.
As illustrated in Figure 17: Clock control on page 101, the system supports the following low frequency
clock sources:
•
•
•
32.768 kHz RC oscillator (LFRC)
32.768 kHz crystal oscillator (LFXO)
32.768 kHz synthesized from HFCLK (LFSYNT)
The LFCLK clock is started by first selecting the preferred clock source in register LFCLKSRC on page
108 and then triggering the LFCLKSTART task. If the LFXO is selected as the clock source, the LFCLK
will initially start running from the 32.768 kHz LFRC while the LFXO is starting up and automatically switch to
using the LFXO once this oscillator is running. The LFCLKSTARTED event will be generated when the LFXO
has been started.
The LFCLK clock is stopped by triggering the LFCLKSTOP task.
It is not allowed to write to register LFCLKSRC on page 108 when the LFCLK is running.
A LFCLKSTOP task will stop the LFCLK oscillator. However, the LFCLKSTOP task can only be triggered
after the STATE field in register LFCLKSTAT on page 107 indicates a 'LFCLK running' state.
The LFCLK clock controller and all of the LFCLK clock sources are always switched off when in OFF mode.
19.2.1 32.768 kHz RC oscillator (LFRC)
The default source of the low frequency clock (LFCLK) is the 32.768 kHz RC oscillator (LFRC).
The LFRC frequency will be affected by variation in temperature. The LFRC oscillator can be calibrated to
improve accuracy by using the HFXO as a reference oscillator during calibration. See Table 32.768 kHz RC
oscillator (LFRC) on page 109 for details on the default and calibrated accuracy of the LFRC oscillator.
The LFRC oscillator does not require additional external components.
19.2.2 Calibrating the 32.768 kHz RC oscillator
After the 32.768 kHz RC oscillator is started and running, it can be calibrated by triggering the CAL task. In
this case, the HFCLK will be temporarily switched on and used as a reference.
A DONE event will be generated when calibration has finished. The calibration mechanism will only work as
long as HFCLK is generated from the HFCLK crystal oscillator, it is therefore necessary to explicitly start this
crystal oscillator before calibration can be started, see HFCLKSTART task.
19.2.3 Calibration timer
The calibration timer can be used to time the calibration interval of the 32.768 kHz RC oscillator.
The calibration timer is started by triggering the CTSTART task and stopped by triggering the CTSTOP task.
The calibration timer will always start counting down from the value specified in CTIV and generate a CTTO
timeout event when it reaches 0. The Calibration timer will stop by itself when it reaches 0.
CTSTART
CTSTOP
Calibration
timer
CTIV
CTTO
Figure 19: Calibration timer
Due to limitations in the calibration timer, only one task related to calibration, that is, CAL, CTSTART and
CTSTOP, can be triggered for every period of LFCLK.
Page 103
19 CLOCK — Clock control
19.2.4 32.768 kHz crystal oscillator (LFXO)
For higher LFCLK accuracy (when better than +/- 250 ppm accuracy is required), the low frequency crystal
oscillator (LFXO) must be used.
The following external clock sources are supported:
•
•
Low swing clock signal applied to the XL1 pin. The XL2 pin shall then be grounded.
Rail-to-rail clock signal applied to the XL1 pin. The XL2 pin shall then be grounded or left unconnected.
The LFCLKSRC on page 108 register controls the clock source, and its allowed swing. The truth table for
various situations is as follows:
Table 25: LFCLKSRC configuration depending on clock source
SRC
0
0
0
1
1
1
1
2
2
2
EXTERNAL
0
0
1
0
1
1
0
0
0
1
BYPASS
0
1
X
0
0
1
1
0
1
X
Comment
Normal operation, RC is source
DO NOT USE
DO NOT USE
Normal XTAL operation
Apply external low swing signal to XL1, ground XL2
Apply external full swing signal to XL1, leave XL2 grounded or unconnected
DO NOT USE
Normal operation, synth is source
DO NOT USE
DO NOT USE
To achieve correct oscillation frequency, the load capacitance must match the specification in the crystal
data sheet. Figure 20: Circuit diagram of the 32.768 kHz crystal oscillator on page 104 shows the LFXO
circuitry.
XL1
XL2
C1
C2
32.768 kHz
crystal
Figure 20: Circuit diagram of the 32.768 kHz crystal oscillator
The load capacitance (CL) is the total capacitance seen by the crystal across its terminals and is given by:
C1 and C2 are ceramic SMD capacitors connected between each crystal terminal and ground. Cpcb1 and
Cpcb2 are stray capacitances on the PCB. Cpin is the pin input capacitance on the XC1 and XC2 pins (see
32.768 kHz crystal oscillator (LFXO) on page 109). The load capacitors C1 and C2 should have the same
value.
For more information, see Reference circuitry on page 545.
Page 104
19 CLOCK — Clock control
19.2.5 32.768 kHz synthesized from HFCLK (LFSYNT)
LFCLK can also be synthesized from the HFCLK clock source. The accuracy of LFCLK will then be the
accuracy of the HFCLK.
Using the LFSYNT clock avoids the requirement for a 32.768 kHz crystal, but increases average power
consumption as the HFCLK will need to be requested in the system.
19.3 Registers
Table 26: Instances
Base address
Peripheral
Instance
Description
0x40000000
CLOCK
CLOCK
Clock control
Configuration
Table 27: Register Overview
Register
Offset
Description
TASKS_HFCLKSTART
0x000
Start HFCLK crystal oscillator
TASKS_HFCLKSTOP
0x004
Stop HFCLK crystal oscillator
TASKS_LFCLKSTART
0x008
Start LFCLK source
TASKS_LFCLKSTOP
0x00C
Stop LFCLK source
TASKS_CAL
0x010
Start calibration of LFRC oscillator
TASKS_CTSTART
0x014
Start calibration timer
TASKS_CTSTOP
0x018
Stop calibration timer
EVENTS_HFCLKSTARTED 0x100
HFCLK oscillator started
EVENTS_LFCLKSTARTED 0x104
LFCLK started
EVENTS_DONE
0x10C
Calibration of LFCLK RC oscillator complete event
EVENTS_CTTO
0x110
Calibration timer timeout
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
HFCLKRUN
0x408
Status indicating that HFCLKSTART task has been triggered
HFCLKSTAT
0x40C
HFCLK status
LFCLKRUN
0x414
Status indicating that LFCLKSTART task has been triggered
LFCLKSTAT
0x418
LFCLK status
LFCLKSRCCOPY
0x41C
Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
LFCLKSRC
0x518
Clock source for the LFCLK
CTIV
0x538
Calibration timer interval
TRACECONFIG
0x55C
Clocking options for the Trace Port debug interface
Retained
19.3.1 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x00000000
Id
RW Field
A
RW HFCLKSTARTED
0
Value Id
Value
Description
Write '1' to Enable interrupt for HFCLKSTARTED event
See EVENTS_HFCLKSTARTED
B
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW LFCLKSTARTED
Write '1' to Enable interrupt for LFCLKSTARTED event
See EVENTS_LFCLKSTARTED
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Page 105
19 CLOCK — Clock control
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x00000000
Id
RW Field
C
RW DONE
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for DONE event
See EVENTS_DONE
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CTTO
Write '1' to Enable interrupt for CTTO event
See EVENTS_CTTO
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
19.3.2 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x00000000
Id
RW Field
A
RW HFCLKSTARTED
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for HFCLKSTARTED event
See EVENTS_HFCLKSTARTED
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW LFCLKSTARTED
Write '1' to Disable interrupt for LFCLKSTARTED event
See EVENTS_LFCLKSTARTED
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DONE
Write '1' to Disable interrupt for DONE event
See EVENTS_DONE
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CTTO
Write '1' to Disable interrupt for CTTO event
See EVENTS_CTTO
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
19.3.3 HFCLKRUN
Address offset: 0x408
Status indicating that HFCLKSTART task has been triggered
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NotTriggered
0
Task not triggered
Triggered
1
Task triggered
STATUS
HFCLKSTART task triggered or not
Page 106
19 CLOCK — Clock control
19.3.4 HFCLKSTAT
Address offset: 0x40C
HFCLK status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
Reset 0x00000000
Id
RW Field
A
R
B
R
0
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
RC
0
64 MHz internal oscillator (HFINT)
Xtal
1
64 MHz crystal oscillator (HFXO)
NotRunning
0
HFCLK not running
Running
1
HFCLK running
SRC
Source of HFCLK
STATE
HFCLK state
19.3.5 LFCLKRUN
Address offset: 0x414
Status indicating that LFCLKSTART task has been triggered
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NotTriggered
0
Task not triggered
Triggered
1
Task triggered
STATUS
LFCLKSTART task triggered or not
19.3.6 LFCLKSTAT
Address offset: 0x418
LFCLK status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
Reset 0x00000000
Id
RW Field
A
R
B
R
0
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
RC
0
32.768 kHz RC oscillator
Xtal
1
32.768 kHz crystal oscillator
Synth
2
32.768 kHz synthesized from HFCLK
NotRunning
0
LFCLK not running
Running
1
LFCLK running
SRC
Source of LFCLK
STATE
LFCLK state
19.3.7 LFCLKSRCCOPY
Address offset: 0x41C
Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
RC
0
32.768 kHz RC oscillator
Xtal
1
32.768 kHz crystal oscillator
Synth
2
32.768 kHz synthesized from HFCLK
SRC
Clock source
Page 107
19 CLOCK — Clock control
19.3.8 LFCLKSRC
Address offset: 0x518
Clock source for the LFCLK
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B
Reset 0x00000000
Id
RW Field
A
RW SRC
B
0
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
RC
0
32.768 kHz RC oscillator
Xtal
1
32.768 kHz crystal oscillator
Synth
2
32.768 kHz synthesized from HFCLK
Clock source
RW BYPASS
Enable or disable bypass of LFCLK crystal oscillator with external
clock source
C
Disabled
0
Disable (use with Xtal or low-swing external source)
Enabled
1
Enable (use with rail-to-rail external source)
Disabled
0
Disable external source (use with Xtal)
Enabled
1
Enable use of external source instead of Xtal (SRC needs to be
RW EXTERNAL
Enable or disable external source for LFCLK
set to Xtal)
19.3.9 CTIV ( Retained )
Address offset: 0x538
This register is a retained register
Calibration timer interval
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CTIV
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Calibration timer interval in multiple of 0.25 seconds. Range:
0.25 seconds to 31.75 seconds.
19.3.10 TRACECONFIG
Address offset: 0x55C
Clocking options for the Trace Port debug interface
This register is a retained register. Reset behavior is the same as debug components.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B B
Reset 0x00000000
Id
RW Field
A
RW TRACEPORTSPEED
0
Value Id
Value
Description
Speed of Trace Port clock. Note that the TRACECLK pin will
output this clock divided by two.
B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
32MHz
0
32 MHz Trace Port clock (TRACECLK = 16 MHz)
16MHz
1
16 MHz Trace Port clock (TRACECLK = 8 MHz)
8MHz
2
8 MHz Trace Port clock (TRACECLK = 4 MHz)
4MHz
3
4 MHz Trace Port clock (TRACECLK = 2 MHz)
GPIO
0
GPIOs multiplexed onto all trace-pins
Serial
1
SWO multiplexed onto P0.18, GPIO multiplexed onto other
Parallel
2
RW TRACEMUX
Pin multiplexing of trace signals.
trace pins
TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18,
P0.16, P0.15 and P0.14.
Page 108
19 CLOCK — Clock control
19.4 Electrical specification
19.4.1 64 MHz internal oscillator (HFINT)
Symbol
Description
fNOM_HFINT
Nominal output frequency
Min.
Typ.
64
Max.
Units
fTOL_HFINT
Frequency tolerance
<±1.5
IHFINT
Run current
60
µA
ISTART_HFINT
Average startup current
I_HFINT
µA
tSTART_HFINT
Startup time
3
us
MHz
<±6
%
19.4.2 64 MHz crystal oscillator (HFXO)
Symbol
Description
fNOM_HFXO
Nominal output frequency
Min.
Typ.
64
fXTAL_HFXO
External crystal frequency
32
fTOL_HFXO
Frequency tolerance requirement for 2.4 GHz proprietary radio
Max.
Units
MHz
MHz
±60
ppm
±40
ppm
applications
fTOL_HFXO_BLE
Frequency tolerance requirement, Bluetooth low energy
applications
CL_HFXO
Load capacitance
12
pF
C0_HFXO
Shunt capacitance
7
pF
RS_HFXO_7PF
Equivalent series resistance C0 = 7 pF
60
ohm
RS_HFXO_5PF
Equivalent series resistance C0 = 5 pF
80
ohm
RS_HFXO_3PF
Equivalent series resistance C0 = 3 pF
100
ohm
PD_HFXO
Drive level
100
uW
CPIN_HFXO
Input capacitance XC1 and XC2
4
pF
ISTBY_X32M
Core standby current13
50
µA
IHFXO
Run current
250
µA
ISTART_HFXO
Average startup current, first 1 ms
0.4
mA
tSTART_HFXO
Startup time
0.36
ms
19.4.3 32.768 kHz RC oscillator (LFRC)
Symbol
Description
fNOM_LFRC
Nominal frequency
Min.
Typ.
Max.
fTOL_LFRC
Frequency tolerance
±2
%
fTOL_CAL_LFRC
Frequency tolerance for LFRC after calibration14
±250
ppm
ILFRC
Run current for 32.768 kHz RC oscillator
0.6
1
µA
tSTART_LFRC
Startup time for 32.768 kHz RC oscillator
600
32.768
Units
kHz
us
19.4.4 32.768 kHz crystal oscillator (LFXO)
Symbol
Description
fNOM_LFXO
Crystal frequency
fTOL_LFXO_BLE
Frequency tolerance requirement for BLE stack
±250
ppm
fTOL_LFXO_ANT
Frequency tolerance requirement for ANT stack
±50
ppm
CL_LFXO
Load capacitance
12.5
pF
C0_LFXO
Shunt capacitance
2
pF
RS_LFXO
Equivalent series resistance
100
kohm
PD_LFXO
Drive level
1
uW
Cpin
Input capacitance on XL1 and XL2 pads
4
pF
ILFXO
Run current for 32.768 kHz crystal oscillator
0.25
µA
13
14
Min.
Typ.
Max.
32.768
Current drawn if HFXO is forced on through for instance using the low latency power mode.
Constant temperature within ±0.5 °C and calibration performed at least every 8 seconds
Page 109
Units
kHz
19 CLOCK — Clock control
Symbol
Description
tSTART_LFXO
Startup time for 32.768 kHz crystal oscillator
Min.
VAMP_IN_XO_LOW
Peak to peak amplitude for external low swing clock. Input
Typ.
Max.
0.25
200
Units
s
1000
mV
Max.
Units
signal must not swing outside supply rails.
19.4.5 32.768 kHz synthesized from HFCLK (LFSYNT)
Symbol
Description
fNOM_LFSYNT
Nominal frequency
32.768
kHz
fTOL_LFSYNT
Frequency tolerance in addition to HFLCK tolerance15
8
ppm
ILFSYNT
Run current for synthesized 32.768 kHz
100
µA
tSTART_LFSYNT
Startup time for synthesized 32.768 kHz
100
us
15
Min.
Typ.
Frequency tolerance will be derived from the HFCLK source clock plus the LFSYNT tolerance
Page 110
20 GPIO — General purpose input/output
20 GPIO — General purpose input/output
The general purpose input/output (GPIO) is organized as one port with up to 32 I/Os (dependent on
package) enabling access and control of up to 32 pins through one port. Each GPIO can be accessed
individually.
GPIO has the following user-configurable features:
•
•
•
•
•
•
•
•
•
•
Up to 32 GPIO
8 GPIO with Analog channels for SAADC, COMP or LPCOMP inputs
Configurable output drive strength
Internal pull-up and pull-down resistors
Wake-up from high or low level triggers on all pins
Trigger interrupt on state changes on any pin
All pins can be used by the PPI task/event system
One or more GPIO outputs can be controlled through PPI and GPIOTE channels
All pins can be individually mapped to interface blocks for layout flexibility
GPIO state changes captured on SENSE signal can be stored by LATCH register
The GPIO Port peripheral implements up to 32 pins, PIN0 through PIN31. Each of these pins can be
individually configured in the PIN_CNF[n] registers (n=0..31).
The following parameters can be configured through these registers:
•
•
•
•
•
•
Direction
Drive strength
Enabling of pull-up and pull-down resistors
Pin sensing
Input buffer disconnect
Analog input (for selected pins)
The PIN_CNF registers are retained registers. See POWER — Power supply on page 78 chapter for more
information about retained registers.
20.1 Pin configuration
Pins can be individually configured, through the SENSE field in the PIN_CNF[n] register, to detect either a
high level or a low level on their input.
When the correct level is detected on any such configured pin, the sense mechanism will set the DETECT
signal high. Each pin has a separate DETECT signal, and the default behaviour, as defined by the
DETECTMODE register, is that the DETECT signal from all pins in the GPIO Port are combined into
a common DETECT signal that is routed throughout the system, which then can be utilized by other
peripherals, see Figure 21: GPIO Port and the GPIO pin details on page 112. This mechanism is functional
in both ON and OFF mode.
Page 111
20 GPIO — General purpose input/output
LDETECT
PIN0
ANAEN
DETECTMODE
DETECT
GPIO Port
DIR_OVERRIDE
PIN[0].CNF.DRIVE
OUT_OVERRIDE
LATCH
PIN0
OUT
PIN[0].OUT
PIN0.DETECT
PIN[0].IN
PIN[0].CNF
PIN[0].CNF.DIR
Sense
PIN1.DETECT
PIN[0].CNF.SENSE
PIN0
PIN[0].OUT
O
..
PIN[0].CNF.PULL
PIN[0].CNF.INPUT
PIN31.DETECT
PIN[0].IN
I
PIN31
IN
PIN31
PIN[31].OUT
PIN[31].IN
PIN[31].CNF
INPUT_OVERRIDE
ANAIN
O: output buffer
I: input buffer
Figure 21: GPIO Port and the GPIO pin details
Figure 21: GPIO Port and the GPIO pin details on page 112 illustrates the GPIO port containing 32
individual pins, where PIN0 is illustrated in more detail as a reference. All the signals on the left side of the
illustration are used by other peripherals in the system, and therefore, are not directly available to the CPU.
Make sure that a pin is in a level that cannot trigger the sense mechanism before enabling it. Detect will
go high immediately if the sense condition configured in the PIN_CNF registers is met when the sense
mechanism is enabled. This will trigger a PORT event if the DETECT signal was low before enabling the
sense mechanism. See GPIOTE — GPIO tasks and events on page 157.
See the following peripherals for more information about how the DETECT signal is used:
•
•
POWER: uses the DETECT signal to exit from System OFF.
GPIOTE: uses the DETECT signal to generate the PORT event.
When a pin's PINx.DETECT signal goes high, a flag will be set in the LATCH register, e.g. when the
PIN0.DETECT signal goes high, bit 0 in the LATCH register will be set to '1'.
The LATCH register will only be cleared if the CPU explicitly clears it by writing a '1' to the bit that shall be
cleared, i.e. the LATCH register will not be affected by a PINx.DETECT signal being set low.
If the CPU performs a clear operation on a bit in the LATCH register when the associated PINx.DETECT
signal is high, the bit in the LATCH register will not be cleared.
The LDETECT signal will be set high when one or more bits in the LATCH register are '1'. The LDETECT
signal will be set low when all bits in the LATCH register are successfully cleared to '0'.
If one or more bits in the LATCH register are '1' after the CPU has performed a clear operation on the
LATCH registers, a rising edge will be generated on the LDETECT signal, this is illustrated in Figure 22:
DETECT signal behavior on page 113.
Important: The CPU can read the LATCH register at any time to check if a SENSE condition has
been met on one or more of the the GPIO pins even if that condition is no longer met at the time the
CPU queries the LATCH register. This mechanism will work even if the LDETECT signal is not used
as the DETECT signal.
The LDETECT signal is by default not connected to the GPIO port's DETECT signal, but via the
DETECTMODE register it is possible to change the behaviour of the GPIO port's DETECT signal from the
default behaviour described above to instead be derived directly from the LDETECT signal, see Figure 21:
GPIO Port and the GPIO pin details on page 112. Figure 22: DETECT signal behavior on page 113
illustrates the DETECT signals behaviour for these two alternatives.
Page 112
20 GPIO — General purpose input/output
PIN31.DETECT
PIN1.DETECT
PIN0.DETECT
DETECT
(Default mode)
LATCH.31
LATCH.1
LATCH.0
3
4
LATCH = (1 << 31)
LATCH = (1<<1)
2
LATCH = (1<<0)
1
LATCH = (1<<1)
CPU
DETECT
(LDETECT mode)
Figure 22: DETECT signal behavior
The input buffer of a GPIO pin can be disconnected from the pin to enable power savings when the pin is
not used as an input, see Figure 21: GPIO Port and the GPIO pin details on page 112. Inputs must be
connected in order to get a valid input value in the IN register and for the sense mechanism to get access to
the pin.
Other peripherals in the system can attach themselves to GPIO pins and override their output value and
configuration, or read their analog or digital input value, see Figure 21: GPIO Port and the GPIO pin details
on page 112.
Selected pins also support analog input signals, see ANAIN in Figure 21: GPIO Port and the GPIO pin
details on page 112. The assignment of the analog pins can be found in Pin assignments on page 13.
Important: When a pin is configured as digital input, care has been taken in the nRF52832 design
to minimize increased current consumption when the input voltage is between VIL and VIH. However,
it is a good practice to ensure that the external circuitry does not drive that pin to levels between VIL
and VIH for a long period of time.
20.2 GPIO located near the RADIO
Radio performance parameters, such as sensitivity, may be affected by high frequency digital I/O with large
sink/source current close to the radio power supply and antenna pins.
Refer to Pin assignments on page 13 for recommended usage guidelines to maximize radio performance in
an application.
20.3 Registers
Table 28: Instances
Base address
Peripheral
Instance
Description
0x50000000
GPIO
GPIO
General purpose input and output
0x50000000
GPIO
P0
General purpose input and output
Page 113
Configuration
Deprecated
20 GPIO — General purpose input/output
Table 29: Register Overview
Register
Offset
Description
OUT
0x504
Write GPIO port
OUTSET
0x508
Set individual bits in GPIO port
OUTCLR
0x50C
Clear individual bits in GPIO port
IN
0x510
Read GPIO port
DIR
0x514
Direction of GPIO pins
DIRSET
0x518
DIR set register
DIRCLR
0x51C
DIR clear register
LATCH
0x520
Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE
DETECTMODE
0x524
Select between default DETECT signal behaviour and LDETECT mode
PIN_CNF[0]
0x700
Configuration of GPIO pins
PIN_CNF[1]
0x704
Configuration of GPIO pins
PIN_CNF[2]
0x708
Configuration of GPIO pins
PIN_CNF[3]
0x70C
Configuration of GPIO pins
PIN_CNF[4]
0x710
Configuration of GPIO pins
PIN_CNF[5]
0x714
Configuration of GPIO pins
PIN_CNF[6]
0x718
Configuration of GPIO pins
PIN_CNF[7]
0x71C
Configuration of GPIO pins
PIN_CNF[8]
0x720
Configuration of GPIO pins
PIN_CNF[9]
0x724
Configuration of GPIO pins
PIN_CNF[10]
0x728
Configuration of GPIO pins
PIN_CNF[11]
0x72C
Configuration of GPIO pins
PIN_CNF[12]
0x730
Configuration of GPIO pins
PIN_CNF[13]
0x734
Configuration of GPIO pins
PIN_CNF[14]
0x738
Configuration of GPIO pins
PIN_CNF[15]
0x73C
Configuration of GPIO pins
PIN_CNF[16]
0x740
Configuration of GPIO pins
PIN_CNF[17]
0x744
Configuration of GPIO pins
PIN_CNF[18]
0x748
Configuration of GPIO pins
PIN_CNF[19]
0x74C
Configuration of GPIO pins
PIN_CNF[20]
0x750
Configuration of GPIO pins
PIN_CNF[21]
0x754
Configuration of GPIO pins
PIN_CNF[22]
0x758
Configuration of GPIO pins
PIN_CNF[23]
0x75C
Configuration of GPIO pins
PIN_CNF[24]
0x760
Configuration of GPIO pins
PIN_CNF[25]
0x764
Configuration of GPIO pins
PIN_CNF[26]
0x768
Configuration of GPIO pins
PIN_CNF[27]
0x76C
Configuration of GPIO pins
PIN_CNF[28]
0x770
Configuration of GPIO pins
PIN_CNF[29]
0x774
Configuration of GPIO pins
PIN_CNF[30]
0x778
Configuration of GPIO pins
PIN_CNF[31]
0x77C
Configuration of GPIO pins
registers
20.3.1 OUT
Address offset: 0x504
Write GPIO port
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW PIN0
B
Value Id
Value
Description
Low
0
Pin driver is low
High
1
Pin driver is high
Pin 0
RW PIN1
Pin 1
Page 114
I H G F E D C B A
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
RW Field
Value Id
Value
Description
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
RW PIN2
Pin 2
RW PIN3
Pin 3
RW PIN4
Pin 4
RW PIN5
Pin 5
RW PIN6
Pin 6
RW PIN7
Pin 7
RW PIN8
Pin 8
RW PIN9
Pin 9
RW PIN10
Pin 10
RW PIN11
Pin 11
RW PIN12
Pin 12
RW PIN13
Pin 13
RW PIN14
Pin 14
RW PIN15
Pin 15
RW PIN16
Pin 16
RW PIN17
Pin 17
RW PIN18
Pin 18
RW PIN19
Pin 19
Pin driver is low
Page 115
I H G F E D C B A
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
U
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
Low
0
Pin driver is low
High
1
Pin driver is high
RW PIN20
I H G F E D C B A
Pin 20
RW PIN21
Pin 21
RW PIN22
Pin 22
RW PIN23
Pin 23
RW PIN24
Pin 24
RW PIN25
Pin 25
RW PIN26
Pin 26
RW PIN27
Pin 27
RW PIN28
Pin 28
RW PIN29
Pin 29
RW PIN30
Pin 30
RW PIN31
Pin 31
20.3.2 OUTSET
Address offset: 0x508
Set individual bits in GPIO port
Read: reads value of OUT register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW PIN0
B
I H G F E D C B A
Value Id
Value
Description
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Pin 0
RW PIN1
Pin 1
Read: pin driver is low
Page 116
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
C
D
E
F
G
H
I
J
K
L
M
N
O
P
RW Field
I H G F E D C B A
Value Id
Value
Description
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
RW PIN2
Pin 2
RW PIN3
Pin 3
RW PIN4
Pin 4
RW PIN5
Pin 5
RW PIN6
Pin 6
RW PIN7
Pin 7
RW PIN8
Pin 8
RW PIN9
Pin 9
RW PIN10
Pin 10
RW PIN11
Pin 11
RW PIN12
Pin 12
RW PIN13
Pin 13
RW PIN14
Pin 14
RW PIN15
Pin 15
Page 117
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
Q
R
S
T
U
V
W
X
Y
Z
a
b
c
RW Field
I H G F E D C B A
Value Id
Value
Description
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
RW PIN16
Pin 16
RW PIN17
Pin 17
RW PIN18
Pin 18
RW PIN19
Pin 19
RW PIN20
Pin 20
RW PIN21
Pin 21
RW PIN22
Pin 22
RW PIN23
Pin 23
RW PIN24
Pin 24
RW PIN25
Pin 25
RW PIN26
Pin 26
RW PIN27
Pin 27
RW PIN28
Pin 28
Page 118
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
d
RW PIN29
e
f
I H G F E D C B A
Value Id
Value
Description
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Set
1
Write: writing a '1' sets the pin high; writing a '0' has no effect
Pin 29
RW PIN30
Pin 30
RW PIN31
Pin 31
20.3.3 OUTCLR
Address offset: 0x50C
Clear individual bits in GPIO port
Read: reads value of OUT register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW PIN0
B
C
D
E
F
G
H
I H G F E D C B A
Value Id
Value
Description
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Pin 0
RW PIN1
Pin 1
RW PIN2
Pin 2
RW PIN3
Pin 3
RW PIN4
Pin 4
RW PIN5
Pin 5
RW PIN6
Pin 6
RW PIN7
Pin 7
Page 119
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
RW Field
I H G F E D C B A
Value Id
Value
Description
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
RW PIN8
Pin 8
RW PIN9
Pin 9
RW PIN10
Pin 10
RW PIN11
Pin 11
RW PIN12
Pin 12
RW PIN13
Pin 13
RW PIN14
Pin 14
RW PIN15
Pin 15
RW PIN16
Pin 16
RW PIN17
Pin 17
RW PIN18
Pin 18
RW PIN19
Pin 19
RW PIN20
Pin 20
RW PIN21
Pin 21
Read: pin driver is low
Page 120
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
W
X
Y
Z
a
b
c
d
e
f
RW Field
I H G F E D C B A
Value Id
Value
Description
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
Low
0
Read: pin driver is low
High
1
Read: pin driver is high
Clear
1
Write: writing a '1' sets the pin low; writing a '0' has no effect
RW PIN22
Pin 22
RW PIN23
Pin 23
RW PIN24
Pin 24
RW PIN25
Pin 25
RW PIN26
Pin 26
RW PIN27
Pin 27
RW PIN28
Pin 28
RW PIN29
Pin 29
RW PIN30
Pin 30
RW PIN31
Pin 31
20.3.4 IN
Address offset: 0x510
Read GPIO port
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
R
Value Id
Value
Description
Low
0
Pin input is low
High
1
Pin input is high
PIN0
Pin 0
Page 121
I H G F E D C B A
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
B
R
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Value Id
Value
Description
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
PIN1
Pin 1
PIN2
Pin 2
PIN3
Pin 3
PIN4
Pin 4
PIN5
Pin 5
PIN6
Pin 6
PIN7
Pin 7
PIN8
Pin 8
PIN9
Pin 9
PIN10
Pin 10
PIN11
Pin 11
PIN12
Pin 12
PIN13
Pin 13
PIN14
Pin 14
PIN15
Pin 15
PIN16
Pin 16
PIN17
Pin 17
PIN18
Pin 18
PIN19
Pin 19
Page 122
I H G F E D C B A
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
U
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
R
R
R
R
R
R
R
R
R
R
R
R
Value Id
Value
Description
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
Low
0
Pin input is low
High
1
Pin input is high
PIN20
I H G F E D C B A
Pin 20
PIN21
Pin 21
PIN22
Pin 22
PIN23
Pin 23
PIN24
Pin 24
PIN25
Pin 25
PIN26
Pin 26
PIN27
Pin 27
PIN28
Pin 28
PIN29
Pin 29
PIN30
Pin 30
PIN31
Pin 31
20.3.5 DIR
Address offset: 0x514
Direction of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW PIN0
B
C
Value Id
Value
Description
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Pin 0
RW PIN1
Pin 1
RW PIN2
Pin 2
Page 123
I H G F E D C B A
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
RW Field
Value Id
Value
Description
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
RW PIN3
Pin 3
RW PIN4
Pin 4
RW PIN5
Pin 5
RW PIN6
Pin 6
RW PIN7
Pin 7
RW PIN8
Pin 8
RW PIN9
Pin 9
RW PIN10
Pin 10
RW PIN11
Pin 11
RW PIN12
Pin 12
RW PIN13
Pin 13
RW PIN14
Pin 14
RW PIN15
Pin 15
RW PIN16
Pin 16
RW PIN17
Pin 17
RW PIN18
Pin 18
RW PIN19
Pin 19
RW PIN20
Pin 20
Pin set as input
Page 124
I H G F E D C B A
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
Input
0
Pin set as input
Output
1
Pin set as output
RW PIN21
I H G F E D C B A
Pin 21
RW PIN22
Pin 22
RW PIN23
Pin 23
RW PIN24
Pin 24
RW PIN25
Pin 25
RW PIN26
Pin 26
RW PIN27
Pin 27
RW PIN28
Pin 28
RW PIN29
Pin 29
RW PIN30
Pin 30
RW PIN31
Pin 31
20.3.6 DIRSET
Address offset: 0x518
DIR set register
Read: reads value of DIR register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW PIN0
B
C
I H G F E D C B A
Value Id
Value
Description
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Set as output pin 0
RW PIN1
Set as output pin 1
RW PIN2
Set as output pin 2
Page 125
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
D
E
F
G
H
I
J
K
L
M
N
O
P
RW Field
I H G F E D C B A
Value Id
Value
Description
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
RW PIN3
Set as output pin 3
RW PIN4
Set as output pin 4
RW PIN5
Set as output pin 5
RW PIN6
Set as output pin 6
RW PIN7
Set as output pin 7
RW PIN8
Set as output pin 8
RW PIN9
Set as output pin 9
RW PIN10
Set as output pin 10
RW PIN11
Set as output pin 11
RW PIN12
Set as output pin 12
RW PIN13
Set as output pin 13
RW PIN14
Set as output pin 14
RW PIN15
Set as output pin 15
Page 126
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
Q
RW PIN16
R
S
T
U
V
W
X
Y
Z
a
b
c
d
I H G F E D C B A
Value Id
Value
Description
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set as output pin 16
RW PIN17
Set as output pin 17
RW PIN18
Set as output pin 18
RW PIN19
Set as output pin 19
RW PIN20
Set as output pin 20
RW PIN21
Set as output pin 21
RW PIN22
Set as output pin 22
RW PIN23
Set as output pin 23
RW PIN24
Set as output pin 24
RW PIN25
Set as output pin 25
RW PIN26
Set as output pin 26
RW PIN27
Set as output pin 27
RW PIN28
Set as output pin 28
RW PIN29
Set as output pin 29
Page 127
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
e
f
RW Field
I H G F E D C B A
Value Id
Value
Description
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Set
1
Write: writing a '1' sets pin to output; writing a '0' has no effect
RW PIN30
Set as output pin 30
RW PIN31
Set as output pin 31
20.3.7 DIRCLR
Address offset: 0x51C
DIR clear register
Read: reads value of DIR register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW PIN0
B
C
D
E
F
G
H
I
I H G F E D C B A
Value Id
Value
Description
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Set as input pin 0
RW PIN1
Set as input pin 1
RW PIN2
Set as input pin 2
RW PIN3
Set as input pin 3
RW PIN4
Set as input pin 4
RW PIN5
Set as input pin 5
RW PIN6
Set as input pin 6
RW PIN7
Set as input pin 7
RW PIN8
Set as input pin 8
Read: pin set as input
Page 128
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
RW Field
I H G F E D C B A
Value Id
Value
Description
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
RW PIN9
Set as input pin 9
RW PIN10
Set as input pin 10
RW PIN11
Set as input pin 11
RW PIN12
Set as input pin 12
RW PIN13
Set as input pin 13
RW PIN14
Set as input pin 14
RW PIN15
Set as input pin 15
RW PIN16
Set as input pin 16
RW PIN17
Set as input pin 17
RW PIN18
Set as input pin 18
RW PIN19
Set as input pin 19
RW PIN20
Set as input pin 20
RW PIN21
Set as input pin 21
RW PIN22
Set as input pin 22
Page 129
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
X
Y
Z
a
b
c
d
e
f
RW Field
I H G F E D C B A
Value Id
Value
Description
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
Input
0
Read: pin set as input
Output
1
Read: pin set as output
Clear
1
Write: writing a '1' sets pin to input; writing a '0' has no effect
RW PIN23
Set as input pin 23
RW PIN24
Set as input pin 24
RW PIN25
Set as input pin 25
RW PIN26
Set as input pin 26
RW PIN27
Set as input pin 27
RW PIN28
Set as input pin 28
RW PIN29
Set as input pin 29
RW PIN30
Set as input pin 30
RW PIN31
Set as input pin 31
20.3.8 LATCH
Address offset: 0x520
Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW PIN0
Value Id
Value
I H G F E D C B A
Description
Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE
register. Write '1' to clear.
B
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN1
Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE
register. Write '1' to clear.
Page 130
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
C
RW Field
Value Id
Value
Description
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN2
I H G F E D C B A
Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE
register. Write '1' to clear.
D
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN3
Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE
register. Write '1' to clear.
E
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN4
Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE
register. Write '1' to clear.
F
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN5
Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE
register. Write '1' to clear.
G
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN6
Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE
register. Write '1' to clear.
H
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN7
Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE
register. Write '1' to clear.
I
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN8
Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE
register. Write '1' to clear.
J
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN9
Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE
register. Write '1' to clear.
K
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN10
Status on whether PIN10 has met criteria set in
PIN_CNF10.SENSE register. Write '1' to clear.
L
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN11
Status on whether PIN11 has met criteria set in
PIN_CNF11.SENSE register. Write '1' to clear.
M
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN12
Status on whether PIN12 has met criteria set in
PIN_CNF12.SENSE register. Write '1' to clear.
N
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN13
Status on whether PIN13 has met criteria set in
PIN_CNF13.SENSE register. Write '1' to clear.
O
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN14
Status on whether PIN14 has met criteria set in
PIN_CNF14.SENSE register. Write '1' to clear.
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
Page 131
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
P
RW PIN15
Value Id
Value
Description
Status on whether PIN15 has met criteria set in
PIN_CNF15.SENSE register. Write '1' to clear.
Q
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN16
Status on whether PIN16 has met criteria set in
PIN_CNF16.SENSE register. Write '1' to clear.
R
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN17
Status on whether PIN17 has met criteria set in
PIN_CNF17.SENSE register. Write '1' to clear.
S
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN18
Status on whether PIN18 has met criteria set in
PIN_CNF18.SENSE register. Write '1' to clear.
T
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN19
Status on whether PIN19 has met criteria set in
PIN_CNF19.SENSE register. Write '1' to clear.
U
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN20
Status on whether PIN20 has met criteria set in
PIN_CNF20.SENSE register. Write '1' to clear.
V
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN21
Status on whether PIN21 has met criteria set in
PIN_CNF21.SENSE register. Write '1' to clear.
W
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN22
Status on whether PIN22 has met criteria set in
PIN_CNF22.SENSE register. Write '1' to clear.
X
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN23
Status on whether PIN23 has met criteria set in
PIN_CNF23.SENSE register. Write '1' to clear.
Y
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN24
Status on whether PIN24 has met criteria set in
PIN_CNF24.SENSE register. Write '1' to clear.
Z
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN25
Status on whether PIN25 has met criteria set in
PIN_CNF25.SENSE register. Write '1' to clear.
a
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN26
Status on whether PIN26 has met criteria set in
PIN_CNF26.SENSE register. Write '1' to clear.
b
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN27
Status on whether PIN27 has met criteria set in
PIN_CNF27.SENSE register. Write '1' to clear.
c
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN28
Status on whether PIN28 has met criteria set in
PIN_CNF28.SENSE register. Write '1' to clear.
NotLatched
0
Criteria has not been met
Page 132
I H G F E D C B A
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
d
RW Field
Value Id
Value
Description
Latched
1
Criteria has been met
RW PIN29
I H G F E D C B A
Status on whether PIN29 has met criteria set in
PIN_CNF29.SENSE register. Write '1' to clear.
e
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN30
Status on whether PIN30 has met criteria set in
PIN_CNF30.SENSE register. Write '1' to clear.
f
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
RW PIN31
Status on whether PIN31 has met criteria set in
PIN_CNF31.SENSE register. Write '1' to clear.
NotLatched
0
Criteria has not been met
Latched
1
Criteria has been met
20.3.9 DETECTMODE
Address offset: 0x524
Select between default DETECT signal behaviour and LDETECT mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW DETECTMODE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Select between default DETECT signal behaviour and LDETECT
mode
Default
0
DETECT directly connected to PIN DETECT signals
LDETECT
1
Use the latched LDETECT behaviour
20.3.10 PIN_CNF[0]
Address offset: 0x700
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Page 133
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
D0H1
5
Disconnect '0', high drive '1' (normally used for wired-or
S0D1
6
H0D1
7
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.11 PIN_CNF[1]
Address offset: 0x704
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.12 PIN_CNF[2]
Address offset: 0x708
Configuration of GPIO pins
Page 134
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.13 PIN_CNF[3]
Address offset: 0x70C
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Page 135
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
D0H1
5
Disconnect '0', high drive '1' (normally used for wired-or
S0D1
6
H0D1
7
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.14 PIN_CNF[4]
Address offset: 0x710
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.15 PIN_CNF[5]
Address offset: 0x714
Configuration of GPIO pins
Page 136
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.16 PIN_CNF[6]
Address offset: 0x718
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Page 137
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
D0H1
5
Disconnect '0', high drive '1' (normally used for wired-or
S0D1
6
H0D1
7
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.17 PIN_CNF[7]
Address offset: 0x71C
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.18 PIN_CNF[8]
Address offset: 0x720
Configuration of GPIO pins
Page 138
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.19 PIN_CNF[9]
Address offset: 0x724
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Page 139
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
D0H1
5
Disconnect '0', high drive '1' (normally used for wired-or
S0D1
6
H0D1
7
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.20 PIN_CNF[10]
Address offset: 0x728
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.21 PIN_CNF[11]
Address offset: 0x72C
Configuration of GPIO pins
Page 140
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.22 PIN_CNF[12]
Address offset: 0x730
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Page 141
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
D0H1
5
Disconnect '0', high drive '1' (normally used for wired-or
S0D1
6
H0D1
7
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.23 PIN_CNF[13]
Address offset: 0x734
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.24 PIN_CNF[14]
Address offset: 0x738
Configuration of GPIO pins
Page 142
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.25 PIN_CNF[15]
Address offset: 0x73C
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Page 143
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
D0H1
5
Disconnect '0', high drive '1' (normally used for wired-or
S0D1
6
H0D1
7
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.26 PIN_CNF[16]
Address offset: 0x740
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.27 PIN_CNF[17]
Address offset: 0x744
Configuration of GPIO pins
Page 144
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.28 PIN_CNF[18]
Address offset: 0x748
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Page 145
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
D0H1
5
Disconnect '0', high drive '1' (normally used for wired-or
S0D1
6
H0D1
7
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.29 PIN_CNF[19]
Address offset: 0x74C
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.30 PIN_CNF[20]
Address offset: 0x750
Configuration of GPIO pins
Page 146
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.31 PIN_CNF[21]
Address offset: 0x754
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Page 147
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
D0H1
5
Disconnect '0', high drive '1' (normally used for wired-or
S0D1
6
H0D1
7
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.32 PIN_CNF[22]
Address offset: 0x758
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.33 PIN_CNF[23]
Address offset: 0x75C
Configuration of GPIO pins
Page 148
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.34 PIN_CNF[24]
Address offset: 0x760
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Page 149
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
D0H1
5
Disconnect '0', high drive '1' (normally used for wired-or
S0D1
6
H0D1
7
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.35 PIN_CNF[25]
Address offset: 0x764
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.36 PIN_CNF[26]
Address offset: 0x768
Configuration of GPIO pins
Page 150
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.37 PIN_CNF[27]
Address offset: 0x76C
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Page 151
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
D0H1
5
Disconnect '0', high drive '1' (normally used for wired-or
S0D1
6
H0D1
7
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.38 PIN_CNF[28]
Address offset: 0x770
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.39 PIN_CNF[29]
Address offset: 0x774
Configuration of GPIO pins
Page 152
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.40 PIN_CNF[30]
Address offset: 0x778
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Page 153
20 GPIO — General purpose input/output
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
0
RW Field
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
D0H1
5
Disconnect '0', high drive '1' (normally used for wired-or
S0D1
6
H0D1
7
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.3.41 PIN_CNF[31]
Address offset: 0x77C
Configuration of GPIO pins
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E
Reset 0x00000002
Id
RW Field
A
RW DIR
B
C
D
0
D D D
C C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Input
0
Configure pin as an input pin
Output
1
Configure pin as an output pin
Connect
0
Connect input buffer
Disconnect
1
Disconnect input buffer
Disabled
0
No pull
Pulldown
1
Pull down on pin
Pullup
3
Pull up on pin
S0S1
0
Standard '0', standard '1'
H0S1
1
High drive '0', standard '1'
S0H1
2
Standard '0', high drive '1'
H0H1
3
High drive '0', high 'drive '1''
D0S1
4
Disconnect '0' standard '1' (normally used for wired-or
D0H1
5
S0D1
6
H0D1
7
Pin direction. Same physical register as DIR register
RW INPUT
Connect or disconnect input buffer
RW PULL
Pull configuration
RW DRIVE
Drive configuration
connections)
Disconnect '0', high drive '1' (normally used for wired-or
connections)
Standard '0'. disconnect '1' (normally used for wired-and
connections)
High drive '0', disconnect '1' (normally used for wired-and
connections)
E
RW SENSE
Pin sensing mechanism
Disabled
0
Disabled
High
2
Sense for high level
Low
3
Sense for low level
20.4 Electrical specification
20.4.1 GPIO Electrical Specification
Symbol
Description
Min.
VIH
Input high voltage
0.7 x VDD
Page 154
Typ.
Max.
Units
VDD
V
20 GPIO — General purpose input/output
Symbol
Description
Min.
VIL
Input low voltage
VSS
Typ.
Max.
0.3 x VDD V
VOH,SD
Output high voltage, standard drive, 0.5 mA, VDD ≥1.7
VDD-0.4
VDD
V
VOH,HDH
Output high voltage, high drive, 5 mA, VDD >= 2.7 V
VDD-0.4
VDD
V
VOH,HDL
Output high voltage, high drive, 3 mA, VDD >= 1.7 V
VDD-0.4
VDD
V
VOL,SD
Output low voltage, standard drive, 0.5 mA, VDD ≥1.7
VSS
VSS+0.4
V
VOL,HDH
Output low voltage, high drive, 5 mA, VDD >= 2.7 V
VSS
VSS+0.4
V
VOL,HDL
Output low voltage, high drive, 3 mA, VDD >= 1.7 V
VSS
VSS+0.4
V
IOL,SD
Current at VSS+0.4 V, output set low, standard drive, VDD ≥1.7
1
2
4
mA
IOL,HDH
Current at VSS+0.4 V, output set low, high drive, VDD >= 2.7 V
6
10
15
mA
IOL,HDL
Current at VSS+0.4 V, output set low, high drive, VDD >= 1.7 V
3
IOH,SD
Current at VDD-0.4 V, output set high, standard drive, VDD ≥1.7
1
2
4
mA
IOH,HDH
Current at VDD-0.4 V, output set high, high drive, VDD >= 2.7 V
6
9
14
mA
IOH,HDL
Current at VDD-0.4 V, output set high, high drive, VDD >= 1.7 V
3
tRF,15pF
Rise/fall time, low drive mode, 10-90%, 15 pF load1
9
ns
tRF,25pF
Rise/fall time, low drive mode, 10-90%, 25 pF load1
13
ns
tRF,50pF
Rise/fall time, low drive mode, 10-90%, 50 pF load1
25
ns
tHRF,15pF
Rise/Fall time, high drive mode, 10-90%, 15 pF load1
4
ns
tHRF,25pF
Rise/Fall time, high drive mode, 10-90%, 25 pF load1
5
ns
tHRF,50pF
Rise/Fall time, high drive mode, 10-90%, 50 pF load1
8
RPU
Pull-up resistance
11
13
16
kΩ
RPD
Pull-down resistance
11
13
16
kΩ
CPAD
Pad capacitance
3
CPAD_NFC
Pad capacitance on NFC pads
4
INFC_LEAK
Leakage current between NFC pads when driven to different
2
mA
mA
ns
pF
pF
10
states
The current drawn from the battery when GPIO is active as an output is calculated as follows:
IGPIO=VDD Cload f
Cload being the load capacitance and “f” is the switching frequency.
7.00
6.00
Pad current [mA]
5.00
4.00
3.00
2.00
1.00
0.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
Pad voltage [V]
Figure 23: GPIO drive strength vs Voltage, standard drive, VDD = 3.0 V
1
Rise and fall times based on simulations
Page 155
3.50
Units
µA
20 GPIO — General purpose input/output
30.00
Pad current [mA]
25.00
20.00
15.00
10.00
5.00
0.00
0
0.5
1
1.5
2
2.5
3
3.5
Pad voltage [V]
Figure 24: GPIO drive strength vs Voltage, high drive, VDD = 3.0 V
9.00
8.00
Pad current [mA]
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
2.8
3
3.2
3.4
3.6
55
65
75
VDD [V]
Figure 25: Max sink current vs Voltage, standard drive
35.00
30.00
Pad current [mA]
25.00
20.00
15.00
10.00
5.00
0.00
1.6
1.8
2
2.2
2.4
2.6
VDD [V]
Figure 26: Max sink current vs Voltage, high drive
Rise time
Fall time
17.00
Rise/Fall time [ns]
16.00
15.00
14.00
13.00
12.00
11.00
10.00
-25
-15
-5
5
15
25
35
45
Temperature [°C]
Figure 27: Rise and fall time vs Temperature, 10%-90%, 25pF load capacitance, VDD = 3.0 V
Page 156
21 GPIOTE — GPIO tasks and events
21 GPIOTE — GPIO tasks and events
The GPIO tasks and events (GPIOTE) module provides functionality for accessing GPIO pins using tasks
and events. Each GPIOTE channel can be assigned to one pin.
A GPIOTE block enables GPIOs to generate events on pin state change which can be used to carry out
tasks through the PPI system. A GPIO can also be driven to change state on system events using the PPI
system. Low power detection of pin state changes is possible when in System ON or System OFF.
Table 30: GPIOTE properties
Instance
GPIOTE
Number of GPIOTE channels
8
Up to three tasks can be used in each GPIOTE channel for performing write operations to a pin. Two tasks
are fixed (SET and CLR), and one (OUT) is configurable to perform following operations:
•
•
•
Set
Clear
Toggle
An event can be generated in each GPIOTE channel from one of the following input conditions:
•
•
•
Rising edge
Falling edge
Any change
21.1 Pin events and tasks
The GPIOTE module has a number of tasks and events that can be configured to operate on individual
GPIO pins.
The tasks (SET[n], CLR[n] and OUT[n]) can be used for writing to individual pins, and the events (IN[n]) can
be generated from changes occurring at the inputs of individual pins.
The SET task will set the pin selected in CONFIG[n].PSEL to high.
The CLR task will set the pin low.
The effect of the OUT task on the pin is configurable in CONFIG[n].POLARITY , and can either set the pin
high, set it low, or toggle it.
The tasks and events are configured using the CONFIG[n] registers. Every set of SET, CLR and OUT[n]
tasks and IN[n] events has one CONFIG[n] register associated with it.
As long as a SET[n], CLR[n] and OUT[n] task or an IN[n] event is configured to control a pin n, the pin's
output value will only be updated by the GPIOTE module. The pin's output value as specified in the GPIO will
therefore be ignored as long as the pin is controlled by GPIOTE. Attempting to write a pin as a normal GPIO
pin will have no effect. When the GPIOTE is disconnected from a pin, see MODE field in CONFIG[n] register,
the associated pin will get the output and configuration values specified in the GPIO module.
When conflicting tasks are triggered simultaneously (i.e. during the same clock cycle) in one channel, the
precedence of the tasks will be as described in Table 31: Task priorities on page 157.
Table 31: Task priorities
Priority
1
2
3
Task
OUT
CLR
SET
Page 157
21 GPIOTE — GPIO tasks and events
When setting the CONFIG[n] registers, MODE=Disabled does not have the same effect as MODE=Task and
POLARITY=None. In the latter case, a CLR or SET task occurring at the exact same time as OUT will end
up with no change on the pin, according to the priorities described in the table above.
When a GPIOTE channel is configured to operate on a pin as a task, the initial value of that pin is configured
in the OUTINIT field of CONFIG[n].
21.2 Port event
PORT is an event that can be generated from multiple input pins using the GPIO DETECT signal.
The event will be generated on the rising edge of the DETECT signal. See GPIO — General purpose input/
output on page 111 for more information about the DETECT signal.
Putting the system into System ON IDLE while DETECT is high will not cause DETECT to wake the system
up again. Make sure to clear all DETECT sources before entering sleep. If the LATCH register is used as a
source, if any bit in LATCH is still high after clearing all or part of the register (for instance due to one of the
PINx.DETECT signal still high), a new rising edge will be generated on DETECT, see Pin configuration on
page 111.
Trying to put the system to System OFF while DETECT is high will cause a wakeup from System OFF reset.
This feature is always enabled although the peripheral itself appears to be IDLE, that is, no clocks or other
power intensive infrastructure have to be requested to keep this feature enabled. This feature can therefore
be used to wake up the CPU from a WFI or WFE type sleep in System ON with all peripherals and the CPU
idle, that is, lowest power consumption in System ON mode.
In order to prevent spurious interrupts from the PORT event while configuring the sources, the user
shall first disable interrupts on the PORT event (through INTENCLR.PORT), then configure the sources
(PIN_CNF[n].SENSE), clear any potential event that could have occurred during configuration (write '1' to
EVENTS_PORT), and finally enable interrupts (through INTENSET.PORT).
21.3 Tasks and events pin configuration
Each GPIOTE channel is associated with one physical GPIO pin through the CONFIG.PSEL field.
When Event mode is selected in CONFIG.MODE, the pin specified by CONFIG.PSEL will be configured as
an input, overriding the DIR setting in GPIO. Similarly, when Task mode is selected in CONFIG.MODE, the
pin specified by CONFIG.PSEL will be configured as an output overriding the DIR setting and OUT value
in GPIO. When Disabled is selected in CONFIG.MODE, the pin specified by CONFIG.PSEL will use its
configuration from the PIN[n].CNF registers in GPIO.
Only one GPIOTE channel can be assigned to one physical pin. Failing to do so may result in unpredictable
behavior.
21.4 Registers
Table 32: Instances
Base address
Peripheral
Instance
Description
0x40006000
GPIOTE
GPIOTE
GPIO Tasks and Events
Configuration
Table 33: Register Overview
Register
Offset
Description
TASKS_OUT[0]
0x000
Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in
TASKS_OUT[1]
0x004
CONFIG[0].POLARITY.
Task for writing to pin specified in CONFIG[1].PSEL. Action on pin is configured in
CONFIG[1].POLARITY.
Page 158
21 GPIOTE — GPIO tasks and events
Register
Offset
Description
TASKS_OUT[2]
0x008
Task for writing to pin specified in CONFIG[2].PSEL. Action on pin is configured in
TASKS_OUT[3]
0x00C
TASKS_OUT[4]
0x010
TASKS_OUT[5]
0x014
TASKS_OUT[6]
0x018
TASKS_OUT[7]
0x01C
TASKS_SET[0]
0x030
Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high.
TASKS_SET[1]
0x034
Task for writing to pin specified in CONFIG[1].PSEL. Action on pin is to set it high.
TASKS_SET[2]
0x038
Task for writing to pin specified in CONFIG[2].PSEL. Action on pin is to set it high.
TASKS_SET[3]
0x03C
Task for writing to pin specified in CONFIG[3].PSEL. Action on pin is to set it high.
TASKS_SET[4]
0x040
Task for writing to pin specified in CONFIG[4].PSEL. Action on pin is to set it high.
TASKS_SET[5]
0x044
Task for writing to pin specified in CONFIG[5].PSEL. Action on pin is to set it high.
TASKS_SET[6]
0x048
Task for writing to pin specified in CONFIG[6].PSEL. Action on pin is to set it high.
TASKS_SET[7]
0x04C
Task for writing to pin specified in CONFIG[7].PSEL. Action on pin is to set it high.
TASKS_CLR[0]
0x060
Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low.
TASKS_CLR[1]
0x064
Task for writing to pin specified in CONFIG[1].PSEL. Action on pin is to set it low.
TASKS_CLR[2]
0x068
Task for writing to pin specified in CONFIG[2].PSEL. Action on pin is to set it low.
TASKS_CLR[3]
0x06C
Task for writing to pin specified in CONFIG[3].PSEL. Action on pin is to set it low.
TASKS_CLR[4]
0x070
Task for writing to pin specified in CONFIG[4].PSEL. Action on pin is to set it low.
TASKS_CLR[5]
0x074
Task for writing to pin specified in CONFIG[5].PSEL. Action on pin is to set it low.
TASKS_CLR[6]
0x078
Task for writing to pin specified in CONFIG[6].PSEL. Action on pin is to set it low.
TASKS_CLR[7]
0x07C
Task for writing to pin specified in CONFIG[7].PSEL. Action on pin is to set it low.
EVENTS_IN[0]
0x100
Event generated from pin specified in CONFIG[0].PSEL
EVENTS_IN[1]
0x104
Event generated from pin specified in CONFIG[1].PSEL
EVENTS_IN[2]
0x108
Event generated from pin specified in CONFIG[2].PSEL
EVENTS_IN[3]
0x10C
Event generated from pin specified in CONFIG[3].PSEL
EVENTS_IN[4]
0x110
Event generated from pin specified in CONFIG[4].PSEL
EVENTS_IN[5]
0x114
Event generated from pin specified in CONFIG[5].PSEL
EVENTS_IN[6]
0x118
Event generated from pin specified in CONFIG[6].PSEL
EVENTS_IN[7]
0x11C
Event generated from pin specified in CONFIG[7].PSEL
EVENTS_PORT
0x17C
Event generated from multiple input GPIO pins with SENSE mechanism enabled
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
CONFIG[0]
0x510
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
CONFIG[1]
0x514
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
CONFIG[2]
0x518
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
CONFIG[3]
0x51C
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
CONFIG[4]
0x520
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
CONFIG[5]
0x524
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
CONFIG[6]
0x528
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
CONFIG[7]
0x52C
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
CONFIG[2].POLARITY.
Task for writing to pin specified in CONFIG[3].PSEL. Action on pin is configured in
CONFIG[3].POLARITY.
Task for writing to pin specified in CONFIG[4].PSEL. Action on pin is configured in
CONFIG[4].POLARITY.
Task for writing to pin specified in CONFIG[5].PSEL. Action on pin is configured in
CONFIG[5].POLARITY.
Task for writing to pin specified in CONFIG[6].PSEL. Action on pin is configured in
CONFIG[6].POLARITY.
Task for writing to pin specified in CONFIG[7].PSEL. Action on pin is configured in
CONFIG[7].POLARITY.
21.4.1 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
I
H G F E D C B A
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW IN0
Value Id
Value
Description
Write '1' to Enable interrupt for IN[0] event
Page 159
21 GPIOTE — GPIO tasks and events
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
I
H G F E D C B A
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_IN[0]
B
RW IN1
Write '1' to Enable interrupt for IN[1] event
See EVENTS_IN[1]
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW IN2
Write '1' to Enable interrupt for IN[2] event
See EVENTS_IN[2]
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW IN3
Write '1' to Enable interrupt for IN[3] event
See EVENTS_IN[3]
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW IN4
Write '1' to Enable interrupt for IN[4] event
See EVENTS_IN[4]
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW IN5
Write '1' to Enable interrupt for IN[5] event
See EVENTS_IN[5]
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW IN6
Write '1' to Enable interrupt for IN[6] event
See EVENTS_IN[6]
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW IN7
Write '1' to Enable interrupt for IN[7] event
See EVENTS_IN[7]
I
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PORT
Write '1' to Enable interrupt for PORT event
See EVENTS_PORT
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
21.4.2 INTENCLR
Address offset: 0x308
Disable interrupt
Page 160
21 GPIOTE — GPIO tasks and events
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
I
H G F E D C B A
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW IN0
Value Id
Value
Description
Write '1' to Disable interrupt for IN[0] event
See EVENTS_IN[0]
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW IN1
Write '1' to Disable interrupt for IN[1] event
See EVENTS_IN[1]
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW IN2
Write '1' to Disable interrupt for IN[2] event
See EVENTS_IN[2]
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW IN3
Write '1' to Disable interrupt for IN[3] event
See EVENTS_IN[3]
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW IN4
Write '1' to Disable interrupt for IN[4] event
See EVENTS_IN[4]
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW IN5
Write '1' to Disable interrupt for IN[5] event
See EVENTS_IN[5]
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW IN6
Write '1' to Disable interrupt for IN[6] event
See EVENTS_IN[6]
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW IN7
Write '1' to Disable interrupt for IN[7] event
See EVENTS_IN[7]
I
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PORT
Write '1' to Disable interrupt for PORT event
See EVENTS_PORT
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
21.4.3 CONFIG[0]
Address offset: 0x510
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
Page 161
21 GPIOTE — GPIO tasks and events
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D
Reset 0x00000000
Id
RW Field
A
RW MODE
0
C C
B B B B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Disabled
0
Event
1
Description
Mode
Disabled. Pin specified by PSEL will not be acquired by the
GPIOTE module.
Event mode
The pin specified by PSEL will be configured as an input and the
IN[n] event will be generated if operation specified in POLARITY
occurs on the pin.
Task
3
Task mode
The GPIO specified by PSEL will be configured as an output and
triggering the SET[n], CLR[n] or OUT[n] task will perform the
operation specified by POLARITY on the pin. When enabled as a
task the GPIOTE module will acquire the pin and the pin can no
longer be written as a regular output pin from the GPIO module.
B
RW PSEL
C
RW POLARITY
[0..31]
GPIO number associated with SET[n], CLR[n] and OUT[n] tasks
and IN[n] event
When In task mode: Operation to be performed on output
when OUT[n] task is triggered. When In event mode: Operation
on input that shall trigger IN[n] event.
None
0
LoToHi
1
HiToLo
2
Toggle
3
Task mode: No effect on pin from OUT[n] task. Event mode: no
IN[n] event generated on pin activity.
Task mode: Set pin from OUT[n] task. Event mode: Generate
IN[n] event when rising edge on pin.
Task mode: Clear pin from OUT[n] task. Event mode: Generate
IN[n] event when falling edge on pin.
Task mode: Toggle pin from OUT[n]. Event mode: Generate
IN[n] when any change on pin.
D
RW OUTINIT
When in task mode: Initial value of the output when the GPIOTE
channel is configured. When in event mode: No effect.
Low
0
Task mode: Initial value of pin before task triggering is low
High
1
Task mode: Initial value of pin before task triggering is high
21.4.4 CONFIG[1]
Address offset: 0x514
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D
Reset 0x00000000
Id
RW Field
A
RW MODE
0
C C
B B B B B
Value Id
Value
Disabled
0
Event
1
Description
Mode
Disabled. Pin specified by PSEL will not be acquired by the
GPIOTE module.
Event mode
The pin specified by PSEL will be configured as an input and the
IN[n] event will be generated if operation specified in POLARITY
occurs on the pin.
Task
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3
Task mode
The GPIO specified by PSEL will be configured as an output and
triggering the SET[n], CLR[n] or OUT[n] task will perform the
operation specified by POLARITY on the pin. When enabled as a
task the GPIOTE module will acquire the pin and the pin can no
longer be written as a regular output pin from the GPIO module.
Page 162
21 GPIOTE — GPIO tasks and events
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D
Reset 0x00000000
Id
RW Field
B
RW PSEL
C
RW POLARITY
0
Value Id
C C
B B B B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..31]
GPIO number associated with SET[n], CLR[n] and OUT[n] tasks
and IN[n] event
When In task mode: Operation to be performed on output
when OUT[n] task is triggered. When In event mode: Operation
on input that shall trigger IN[n] event.
None
0
LoToHi
1
HiToLo
2
Toggle
3
Task mode: No effect on pin from OUT[n] task. Event mode: no
IN[n] event generated on pin activity.
Task mode: Set pin from OUT[n] task. Event mode: Generate
IN[n] event when rising edge on pin.
Task mode: Clear pin from OUT[n] task. Event mode: Generate
IN[n] event when falling edge on pin.
Task mode: Toggle pin from OUT[n]. Event mode: Generate
IN[n] when any change on pin.
D
RW OUTINIT
When in task mode: Initial value of the output when the GPIOTE
channel is configured. When in event mode: No effect.
Low
0
Task mode: Initial value of pin before task triggering is low
High
1
Task mode: Initial value of pin before task triggering is high
21.4.5 CONFIG[2]
Address offset: 0x518
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D
Reset 0x00000000
Id
RW Field
A
RW MODE
0
C C
B B B B B
Value Id
Value
Disabled
0
Event
1
Description
Mode
Disabled. Pin specified by PSEL will not be acquired by the
GPIOTE module.
Event mode
The pin specified by PSEL will be configured as an input and the
IN[n] event will be generated if operation specified in POLARITY
occurs on the pin.
Task
3
Task mode
The GPIO specified by PSEL will be configured as an output and
triggering the SET[n], CLR[n] or OUT[n] task will perform the
operation specified by POLARITY on the pin. When enabled as a
task the GPIOTE module will acquire the pin and the pin can no
longer be written as a regular output pin from the GPIO module.
B
RW PSEL
C
RW POLARITY
[0..31]
GPIO number associated with SET[n], CLR[n] and OUT[n] tasks
and IN[n] event
When In task mode: Operation to be performed on output
when OUT[n] task is triggered. When In event mode: Operation
on input that shall trigger IN[n] event.
None
0
LoToHi
1
HiToLo
2
Toggle
3
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Task mode: No effect on pin from OUT[n] task. Event mode: no
IN[n] event generated on pin activity.
Task mode: Set pin from OUT[n] task. Event mode: Generate
IN[n] event when rising edge on pin.
Task mode: Clear pin from OUT[n] task. Event mode: Generate
IN[n] event when falling edge on pin.
Task mode: Toggle pin from OUT[n]. Event mode: Generate
IN[n] when any change on pin.
Page 163
21 GPIOTE — GPIO tasks and events
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D
Reset 0x00000000
Id
RW Field
D
RW OUTINIT
0
Value Id
C C
B B B B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
When in task mode: Initial value of the output when the GPIOTE
channel is configured. When in event mode: No effect.
Low
0
Task mode: Initial value of pin before task triggering is low
High
1
Task mode: Initial value of pin before task triggering is high
21.4.6 CONFIG[3]
Address offset: 0x51C
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D
Reset 0x00000000
Id
RW Field
A
RW MODE
0
C C
B B B B B
Value Id
Value
Disabled
0
Event
1
Description
Mode
Disabled. Pin specified by PSEL will not be acquired by the
GPIOTE module.
Event mode
The pin specified by PSEL will be configured as an input and the
IN[n] event will be generated if operation specified in POLARITY
occurs on the pin.
Task
3
Task mode
The GPIO specified by PSEL will be configured as an output and
triggering the SET[n], CLR[n] or OUT[n] task will perform the
operation specified by POLARITY on the pin. When enabled as a
task the GPIOTE module will acquire the pin and the pin can no
longer be written as a regular output pin from the GPIO module.
B
RW PSEL
C
RW POLARITY
[0..31]
GPIO number associated with SET[n], CLR[n] and OUT[n] tasks
and IN[n] event
When In task mode: Operation to be performed on output
when OUT[n] task is triggered. When In event mode: Operation
on input that shall trigger IN[n] event.
None
0
LoToHi
1
HiToLo
2
Toggle
3
Task mode: No effect on pin from OUT[n] task. Event mode: no
IN[n] event generated on pin activity.
Task mode: Set pin from OUT[n] task. Event mode: Generate
IN[n] event when rising edge on pin.
Task mode: Clear pin from OUT[n] task. Event mode: Generate
IN[n] event when falling edge on pin.
Task mode: Toggle pin from OUT[n]. Event mode: Generate
IN[n] when any change on pin.
D
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RW OUTINIT
When in task mode: Initial value of the output when the GPIOTE
channel is configured. When in event mode: No effect.
Low
0
Task mode: Initial value of pin before task triggering is low
High
1
Task mode: Initial value of pin before task triggering is high
21.4.7 CONFIG[4]
Address offset: 0x520
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
Page 164
21 GPIOTE — GPIO tasks and events
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D
Reset 0x00000000
Id
RW Field
A
RW MODE
0
C C
B B B B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Disabled
0
Event
1
Description
Mode
Disabled. Pin specified by PSEL will not be acquired by the
GPIOTE module.
Event mode
The pin specified by PSEL will be configured as an input and the
IN[n] event will be generated if operation specified in POLARITY
occurs on the pin.
Task
3
Task mode
The GPIO specified by PSEL will be configured as an output and
triggering the SET[n], CLR[n] or OUT[n] task will perform the
operation specified by POLARITY on the pin. When enabled as a
task the GPIOTE module will acquire the pin and the pin can no
longer be written as a regular output pin from the GPIO module.
B
RW PSEL
C
RW POLARITY
[0..31]
GPIO number associated with SET[n], CLR[n] and OUT[n] tasks
and IN[n] event
When In task mode: Operation to be performed on output
when OUT[n] task is triggered. When In event mode: Operation
on input that shall trigger IN[n] event.
None
0
LoToHi
1
HiToLo
2
Toggle
3
Task mode: No effect on pin from OUT[n] task. Event mode: no
IN[n] event generated on pin activity.
Task mode: Set pin from OUT[n] task. Event mode: Generate
IN[n] event when rising edge on pin.
Task mode: Clear pin from OUT[n] task. Event mode: Generate
IN[n] event when falling edge on pin.
Task mode: Toggle pin from OUT[n]. Event mode: Generate
IN[n] when any change on pin.
D
RW OUTINIT
When in task mode: Initial value of the output when the GPIOTE
channel is configured. When in event mode: No effect.
Low
0
Task mode: Initial value of pin before task triggering is low
High
1
Task mode: Initial value of pin before task triggering is high
21.4.8 CONFIG[5]
Address offset: 0x524
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D
Reset 0x00000000
Id
RW Field
A
RW MODE
0
C C
B B B B B
Value Id
Value
Disabled
0
Event
1
Description
Mode
Disabled. Pin specified by PSEL will not be acquired by the
GPIOTE module.
Event mode
The pin specified by PSEL will be configured as an input and the
IN[n] event will be generated if operation specified in POLARITY
occurs on the pin.
Task
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3
Task mode
The GPIO specified by PSEL will be configured as an output and
triggering the SET[n], CLR[n] or OUT[n] task will perform the
operation specified by POLARITY on the pin. When enabled as a
task the GPIOTE module will acquire the pin and the pin can no
longer be written as a regular output pin from the GPIO module.
Page 165
21 GPIOTE — GPIO tasks and events
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D
Reset 0x00000000
Id
RW Field
B
RW PSEL
C
RW POLARITY
0
Value Id
C C
B B B B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..31]
GPIO number associated with SET[n], CLR[n] and OUT[n] tasks
and IN[n] event
When In task mode: Operation to be performed on output
when OUT[n] task is triggered. When In event mode: Operation
on input that shall trigger IN[n] event.
None
0
LoToHi
1
HiToLo
2
Toggle
3
Task mode: No effect on pin from OUT[n] task. Event mode: no
IN[n] event generated on pin activity.
Task mode: Set pin from OUT[n] task. Event mode: Generate
IN[n] event when rising edge on pin.
Task mode: Clear pin from OUT[n] task. Event mode: Generate
IN[n] event when falling edge on pin.
Task mode: Toggle pin from OUT[n]. Event mode: Generate
IN[n] when any change on pin.
D
RW OUTINIT
When in task mode: Initial value of the output when the GPIOTE
channel is configured. When in event mode: No effect.
Low
0
Task mode: Initial value of pin before task triggering is low
High
1
Task mode: Initial value of pin before task triggering is high
21.4.9 CONFIG[6]
Address offset: 0x528
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D
Reset 0x00000000
Id
RW Field
A
RW MODE
0
C C
B B B B B
Value Id
Value
Disabled
0
Event
1
Description
Mode
Disabled. Pin specified by PSEL will not be acquired by the
GPIOTE module.
Event mode
The pin specified by PSEL will be configured as an input and the
IN[n] event will be generated if operation specified in POLARITY
occurs on the pin.
Task
3
Task mode
The GPIO specified by PSEL will be configured as an output and
triggering the SET[n], CLR[n] or OUT[n] task will perform the
operation specified by POLARITY on the pin. When enabled as a
task the GPIOTE module will acquire the pin and the pin can no
longer be written as a regular output pin from the GPIO module.
B
RW PSEL
C
RW POLARITY
[0..31]
GPIO number associated with SET[n], CLR[n] and OUT[n] tasks
and IN[n] event
When In task mode: Operation to be performed on output
when OUT[n] task is triggered. When In event mode: Operation
on input that shall trigger IN[n] event.
None
0
LoToHi
1
HiToLo
2
Toggle
3
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Task mode: No effect on pin from OUT[n] task. Event mode: no
IN[n] event generated on pin activity.
Task mode: Set pin from OUT[n] task. Event mode: Generate
IN[n] event when rising edge on pin.
Task mode: Clear pin from OUT[n] task. Event mode: Generate
IN[n] event when falling edge on pin.
Task mode: Toggle pin from OUT[n]. Event mode: Generate
IN[n] when any change on pin.
Page 166
21 GPIOTE — GPIO tasks and events
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D
Reset 0x00000000
Id
RW Field
D
RW OUTINIT
0
Value Id
C C
B B B B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
When in task mode: Initial value of the output when the GPIOTE
channel is configured. When in event mode: No effect.
Low
0
Task mode: Initial value of pin before task triggering is low
High
1
Task mode: Initial value of pin before task triggering is high
21.4.10 CONFIG[7]
Address offset: 0x52C
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D
Reset 0x00000000
Id
RW Field
A
RW MODE
0
C C
B B B B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Disabled
0
Event
1
Description
Mode
Disabled. Pin specified by PSEL will not be acquired by the
GPIOTE module.
Event mode
The pin specified by PSEL will be configured as an input and the
IN[n] event will be generated if operation specified in POLARITY
occurs on the pin.
Task
3
Task mode
The GPIO specified by PSEL will be configured as an output and
triggering the SET[n], CLR[n] or OUT[n] task will perform the
operation specified by POLARITY on the pin. When enabled as a
task the GPIOTE module will acquire the pin and the pin can no
longer be written as a regular output pin from the GPIO module.
B
RW PSEL
C
RW POLARITY
[0..31]
GPIO number associated with SET[n], CLR[n] and OUT[n] tasks
and IN[n] event
When In task mode: Operation to be performed on output
when OUT[n] task is triggered. When In event mode: Operation
on input that shall trigger IN[n] event.
None
0
LoToHi
1
HiToLo
2
Toggle
3
Task mode: No effect on pin from OUT[n] task. Event mode: no
IN[n] event generated on pin activity.
Task mode: Set pin from OUT[n] task. Event mode: Generate
IN[n] event when rising edge on pin.
Task mode: Clear pin from OUT[n] task. Event mode: Generate
IN[n] event when falling edge on pin.
Task mode: Toggle pin from OUT[n]. Event mode: Generate
IN[n] when any change on pin.
D
RW OUTINIT
When in task mode: Initial value of the output when the GPIOTE
channel is configured. When in event mode: No effect.
Low
0
Task mode: Initial value of pin before task triggering is low
High
1
Task mode: Initial value of pin before task triggering is high
21.5 Electrical specification
21.5.1 GPIOTE Electrical Specification
Symbol
Description
IGPIOTE,IN
Run current with 1 or more GPIOTE active channels in Input
Min.
mode
Page 167
Typ.
Max.
Units
0.1
0.5
µA
22 PPI — Programmable peripheral interconnect
22 PPI — Programmable peripheral interconnect
The Programmable peripheral interconnect (PPI) enables peripherals to interact autonomously with each
other using tasks and events independent of the CPU. The PPI allows precise synchronization between
peripherals when real-time application constraints exist and eliminates the need for CPU activity to
implement behavior which can be predefined using PPI.
CH[1].EEP
CH[0].EEP
Peripheral 1
Peripheral 2
CH[n].EEP
Event 1
Event 2
Event 1
Event 2
Event 3
0
0
0
1
1
1
n
n
n
CHEN
CHG[0] ... CHG[m]
16MHz
Task 1
Task 1
Task 2
Task 3
CH[0].TEP
Peripheral 1
Peripheral 2
FORK[0].TEP
Figure 28: PPI block diagram
The PPI system has, in addition to the fully programmable peripheral interconnections, a set of channels
where the event end point (EEP) and task end points (TEP) are fixed in hardware. These fixed channels
can be individually enabled, disabled, or added to PPI channel groups in the same way as ordinary PPI
channels.
Table 34: Configurable and fixed PPI channels
Instance
PPI
PPI (fixed)
Channel
0-19
20-31
Number of channels
20
12
Number of groups
6
The PPI provides a mechanism to automatically trigger a task in one peripheral as a result of an event
occurring in another peripheral. A task is connected to an event through a PPI channel. The PPI channel
is composed of three end point registers, one EEP and two TEPs. A peripheral task is connected to a TEP
using the address of the task register associated with the task. Similarly, a peripheral event is connected to
an EEP using the address of the event register associated with the event.
On each PPI channel, the signals are synchronized to the 16 MHz clock, to avoid any internal violation of
setup and hold timings. As a consequence, events that are synchronous to the 16 MHz clock will be delayed
by one clock period, while other asynchronous events will be delayed by up to one 16 MHz clock period.
Page 168
22 PPI — Programmable peripheral interconnect
Each TEP implements a fork mechanism that enables a second task to be triggered at the same time as
the task specified in the TEP is triggered. This second task is configured in the task end point register in the
FORK registers groups, e.g. FORK.TEP[0] is associated with PPI channel CH[0].
There are two ways of enabling and disabling PPI channels:
•
•
Enable or disable PPI channels individually using the CHEN, CHENSET, and CHENCLR registers.
Enable or disable PPI channels in PPI channel groups through the groups’ ENABLE and DISABLE tasks.
Prior to these tasks being triggered, the PPI channel group must be configured to define which PPI
channels belongs to which groups.
Note that when a channel belongs to two groups m and n, and CHG[m].EN and CHG[n].DIS occur
simultaneously (m and n can be equal or different), EN on that channel has priority.
PPI tasks (for example, CHG[0].EN) can be triggered through the PPI like any other task, which means
they can be hooked up to a PPI channel as a TEP. One event can trigger multiple tasks by using multiple
channels and one task can be triggered by multiple events in the same way.
22.1 Pre-programmed channels
Some of the PPI channels are pre-programmed. These channels cannot be configured by the CPU, but can
be added to groups and enabled and disabled like the general purpose PPI channels. The FORK TEP for
these channels are still programmable and can be used by the application.
For a list of pre-programmed PPI channels, see the table below.
Table 35: Pre-programmed channels
Channel
20
21
22
23
24
25
26
27
28
29
30
31
EEP
TIMER0->EVENTS_COMPARE[0]
TIMER0->EVENTS_COMPARE[0]
TIMER0->EVENTS_COMPARE[1]
RADIO->EVENTS_BCMATCH
RADIO->EVENTS_READY
RADIO->EVENTS_ADDRESS
RADIO->EVENTS_ADDRESS
RADIO->EVENTS_END
RTC0->EVENTS_COMPARE[0]
RTC0->EVENTS_COMPARE[0]
RTC0->EVENTS_COMPARE[0]
RTC0->EVENTS_COMPARE[0]
TEP
RADIO->TASKS_TXEN
RADIO->TASKS_RXEN
RADIO->TASKS_DISABLE
AAR->TASKS_START
CCM->TASKS_KSGEN
CCM->TASKS_CRYPT
TIMER0->TASKS_CAPTURE[1]
TIMER0->TASKS_CAPTURE[2]
RADIO->TASKS_TXEN
RADIO->TASKS_RXEN
TIMER0->TASKS_CLEAR
TIMER0->TASKS_START
22.2 Registers
Table 36: Instances
Base address
Peripheral
Instance
Description
0x4001F000
PPI
PPI
Programmable Peripheral Interconnect
Table 37: Register Overview
Register
Offset
Description
TASKS_CHG[0].EN
0x000
Enable channel group 0
TASKS_CHG[0].DIS
0x004
Disable channel group 0
TASKS_CHG[1].EN
0x008
Enable channel group 1
TASKS_CHG[1].DIS
0x00C
Disable channel group 1
TASKS_CHG[2].EN
0x010
Enable channel group 2
TASKS_CHG[2].DIS
0x014
Disable channel group 2
TASKS_CHG[3].EN
0x018
Enable channel group 3
TASKS_CHG[3].DIS
0x01C
Disable channel group 3
TASKS_CHG[4].EN
0x020
Enable channel group 4
TASKS_CHG[4].DIS
0x024
Disable channel group 4
TASKS_CHG[5].EN
0x028
Enable channel group 5
TASKS_CHG[5].DIS
0x02C
Disable channel group 5
Page 169
Configuration
22 PPI — Programmable peripheral interconnect
Register
Offset
Description
CHEN
0x500
Channel enable register
CHENSET
0x504
Channel enable set register
CHENCLR
0x508
Channel enable clear register
CH[0].EEP
0x510
Channel 0 event end-point
CH[0].TEP
0x514
Channel 0 task end-point
CH[1].EEP
0x518
Channel 1 event end-point
CH[1].TEP
0x51C
Channel 1 task end-point
CH[2].EEP
0x520
Channel 2 event end-point
CH[2].TEP
0x524
Channel 2 task end-point
CH[3].EEP
0x528
Channel 3 event end-point
CH[3].TEP
0x52C
Channel 3 task end-point
CH[4].EEP
0x530
Channel 4 event end-point
CH[4].TEP
0x534
Channel 4 task end-point
CH[5].EEP
0x538
Channel 5 event end-point
CH[5].TEP
0x53C
Channel 5 task end-point
CH[6].EEP
0x540
Channel 6 event end-point
CH[6].TEP
0x544
Channel 6 task end-point
CH[7].EEP
0x548
Channel 7 event end-point
CH[7].TEP
0x54C
Channel 7 task end-point
CH[8].EEP
0x550
Channel 8 event end-point
CH[8].TEP
0x554
Channel 8 task end-point
CH[9].EEP
0x558
Channel 9 event end-point
CH[9].TEP
0x55C
Channel 9 task end-point
CH[10].EEP
0x560
Channel 10 event end-point
CH[10].TEP
0x564
Channel 10 task end-point
CH[11].EEP
0x568
Channel 11 event end-point
CH[11].TEP
0x56C
Channel 11 task end-point
CH[12].EEP
0x570
Channel 12 event end-point
CH[12].TEP
0x574
Channel 12 task end-point
CH[13].EEP
0x578
Channel 13 event end-point
CH[13].TEP
0x57C
Channel 13 task end-point
CH[14].EEP
0x580
Channel 14 event end-point
CH[14].TEP
0x584
Channel 14 task end-point
CH[15].EEP
0x588
Channel 15 event end-point
CH[15].TEP
0x58C
Channel 15 task end-point
CH[16].EEP
0x590
Channel 16 event end-point
CH[16].TEP
0x594
Channel 16 task end-point
CH[17].EEP
0x598
Channel 17 event end-point
CH[17].TEP
0x59C
Channel 17 task end-point
CH[18].EEP
0x5A0
Channel 18 event end-point
CH[18].TEP
0x5A4
Channel 18 task end-point
CH[19].EEP
0x5A8
Channel 19 event end-point
CH[19].TEP
0x5AC
Channel 19 task end-point
CHG[0]
0x800
Channel group 0
CHG[1]
0x804
Channel group 1
CHG[2]
0x808
Channel group 2
CHG[3]
0x80C
Channel group 3
CHG[4]
0x810
Channel group 4
CHG[5]
0x814
Channel group 5
FORK[0].TEP
0x910
Channel 0 task end-point
FORK[1].TEP
0x914
Channel 1 task end-point
FORK[2].TEP
0x918
Channel 2 task end-point
FORK[3].TEP
0x91C
Channel 3 task end-point
FORK[4].TEP
0x920
Channel 4 task end-point
FORK[5].TEP
0x924
Channel 5 task end-point
FORK[6].TEP
0x928
Channel 6 task end-point
FORK[7].TEP
0x92C
Channel 7 task end-point
FORK[8].TEP
0x930
Channel 8 task end-point
Page 170
22 PPI — Programmable peripheral interconnect
Register
Offset
Description
FORK[9].TEP
0x934
Channel 9 task end-point
FORK[10].TEP
0x938
Channel 10 task end-point
FORK[11].TEP
0x93C
Channel 11 task end-point
FORK[12].TEP
0x940
Channel 12 task end-point
FORK[13].TEP
0x944
Channel 13 task end-point
FORK[14].TEP
0x948
Channel 14 task end-point
FORK[15].TEP
0x94C
Channel 15 task end-point
FORK[16].TEP
0x950
Channel 16 task end-point
FORK[17].TEP
0x954
Channel 17 task end-point
FORK[18].TEP
0x958
Channel 18 task end-point
FORK[19].TEP
0x95C
Channel 19 task end-point
FORK[20].TEP
0x960
Channel 20 task end-point
FORK[21].TEP
0x964
Channel 21 task end-point
FORK[22].TEP
0x968
Channel 22 task end-point
FORK[23].TEP
0x96C
Channel 23 task end-point
FORK[24].TEP
0x970
Channel 24 task end-point
FORK[25].TEP
0x974
Channel 25 task end-point
FORK[26].TEP
0x978
Channel 26 task end-point
FORK[27].TEP
0x97C
Channel 27 task end-point
FORK[28].TEP
0x980
Channel 28 task end-point
FORK[29].TEP
0x984
Channel 29 task end-point
FORK[30].TEP
0x988
Channel 30 task end-point
FORK[31].TEP
0x98C
Channel 31 task end-point
22.2.1 CHEN
Address offset: 0x500
Channel enable register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW CH0
B
C
D
E
F
G
H
I
Value Id
Value
Description
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Enable or disable channel 0
RW CH1
Enable or disable channel 1
RW CH2
Enable or disable channel 2
RW CH3
Enable or disable channel 3
RW CH4
Enable or disable channel 4
RW CH5
Enable or disable channel 5
RW CH6
Enable or disable channel 6
RW CH7
Enable or disable channel 7
RW CH8
Enable or disable channel 8
Page 171
I H G F E D C B A
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
a
RW Field
Value Id
Value
Description
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
RW CH9
Enable or disable channel 9
RW CH10
Enable or disable channel 10
RW CH11
Enable or disable channel 11
RW CH12
Enable or disable channel 12
RW CH13
Enable or disable channel 13
RW CH14
Enable or disable channel 14
RW CH15
Enable or disable channel 15
RW CH16
Enable or disable channel 16
RW CH17
Enable or disable channel 17
RW CH18
Enable or disable channel 18
RW CH19
Enable or disable channel 19
RW CH20
Enable or disable channel 20
RW CH21
Enable or disable channel 21
RW CH22
Enable or disable channel 22
RW CH23
Enable or disable channel 23
RW CH24
Enable or disable channel 24
RW CH25
Enable or disable channel 25
RW CH26
Enable or disable channel 26
Disable channel
Page 172
I H G F E D C B A
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
b
c
d
e
f
RW Field
Value Id
Value
Description
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
Disabled
0
Disable channel
Enabled
1
Enable channel
RW CH27
I H G F E D C B A
Enable or disable channel 27
RW CH28
Enable or disable channel 28
RW CH29
Enable or disable channel 29
RW CH30
Enable or disable channel 30
RW CH31
Enable or disable channel 31
22.2.2 CHENSET
Address offset: 0x504
Channel enable set register
Read: reads value of CH{i} field in CHEN register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW CH0
B
C
D
E
F
G
Value Id
Value
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
I H G F E D C B A
Description
Channel 0 enable set register. Writing '0' has no effect
RW CH1
Channel 1 enable set register. Writing '0' has no effect
RW CH2
Channel 2 enable set register. Writing '0' has no effect
RW CH3
Channel 3 enable set register. Writing '0' has no effect
RW CH4
Channel 4 enable set register. Writing '0' has no effect
RW CH5
Channel 5 enable set register. Writing '0' has no effect
RW CH6
Channel 6 enable set register. Writing '0' has no effect
Page 173
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
RW Field
Value Id
Value
Description
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
RW CH7
I H G F E D C B A
Channel 7 enable set register. Writing '0' has no effect
RW CH8
Channel 8 enable set register. Writing '0' has no effect
RW CH9
Channel 9 enable set register. Writing '0' has no effect
RW CH10
Channel 10 enable set register. Writing '0' has no effect
RW CH11
Channel 11 enable set register. Writing '0' has no effect
RW CH12
Channel 12 enable set register. Writing '0' has no effect
RW CH13
Channel 13 enable set register. Writing '0' has no effect
RW CH14
Channel 14 enable set register. Writing '0' has no effect
RW CH15
Channel 15 enable set register. Writing '0' has no effect
RW CH16
Channel 16 enable set register. Writing '0' has no effect
RW CH17
Channel 17 enable set register. Writing '0' has no effect
RW CH18
Channel 18 enable set register. Writing '0' has no effect
RW CH19
Channel 19 enable set register. Writing '0' has no effect
RW CH20
Channel 20 enable set register. Writing '0' has no effect
Read: channel disabled
Page 174
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
RW CH21
I H G F E D C B A
Channel 21 enable set register. Writing '0' has no effect
RW CH22
Channel 22 enable set register. Writing '0' has no effect
RW CH23
Channel 23 enable set register. Writing '0' has no effect
RW CH24
Channel 24 enable set register. Writing '0' has no effect
RW CH25
Channel 25 enable set register. Writing '0' has no effect
RW CH26
Channel 26 enable set register. Writing '0' has no effect
RW CH27
Channel 27 enable set register. Writing '0' has no effect
RW CH28
Channel 28 enable set register. Writing '0' has no effect
RW CH29
Channel 29 enable set register. Writing '0' has no effect
RW CH30
Channel 30 enable set register. Writing '0' has no effect
RW CH31
Channel 31 enable set register. Writing '0' has no effect
22.2.3 CHENCLR
Address offset: 0x508
Channel enable clear register
Read: reads value of CH{i} field in CHEN register.
Page 175
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW CH0
B
C
D
E
F
G
H
I
J
K
L
M
N
Value Id
Value
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
I H G F E D C B A
Description
Channel 0 enable clear register. Writing '0' has no effect
RW CH1
Channel 1 enable clear register. Writing '0' has no effect
RW CH2
Channel 2 enable clear register. Writing '0' has no effect
RW CH3
Channel 3 enable clear register. Writing '0' has no effect
RW CH4
Channel 4 enable clear register. Writing '0' has no effect
RW CH5
Channel 5 enable clear register. Writing '0' has no effect
RW CH6
Channel 6 enable clear register. Writing '0' has no effect
RW CH7
Channel 7 enable clear register. Writing '0' has no effect
RW CH8
Channel 8 enable clear register. Writing '0' has no effect
RW CH9
Channel 9 enable clear register. Writing '0' has no effect
RW CH10
Channel 10 enable clear register. Writing '0' has no effect
RW CH11
Channel 11 enable clear register. Writing '0' has no effect
RW CH12
Channel 12 enable clear register. Writing '0' has no effect
RW CH13
Channel 13 enable clear register. Writing '0' has no effect
Page 176
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
O
P
Q
R
S
T
U
V
W
X
Y
Z
a
b
RW Field
Value Id
Value
Description
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
RW CH14
I H G F E D C B A
Channel 14 enable clear register. Writing '0' has no effect
RW CH15
Channel 15 enable clear register. Writing '0' has no effect
RW CH16
Channel 16 enable clear register. Writing '0' has no effect
RW CH17
Channel 17 enable clear register. Writing '0' has no effect
RW CH18
Channel 18 enable clear register. Writing '0' has no effect
RW CH19
Channel 19 enable clear register. Writing '0' has no effect
RW CH20
Channel 20 enable clear register. Writing '0' has no effect
RW CH21
Channel 21 enable clear register. Writing '0' has no effect
RW CH22
Channel 22 enable clear register. Writing '0' has no effect
RW CH23
Channel 23 enable clear register. Writing '0' has no effect
RW CH24
Channel 24 enable clear register. Writing '0' has no effect
RW CH25
Channel 25 enable clear register. Writing '0' has no effect
RW CH26
Channel 26 enable clear register. Writing '0' has no effect
RW CH27
Channel 27 enable clear register. Writing '0' has no effect
Read: channel disabled
Page 177
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
c
d
e
f
RW Field
Value Id
Value
Description
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
RW CH28
I H G F E D C B A
Channel 28 enable clear register. Writing '0' has no effect
RW CH29
Channel 29 enable clear register. Writing '0' has no effect
RW CH30
Channel 30 enable clear register. Writing '0' has no effect
RW CH31
Channel 31 enable clear register. Writing '0' has no effect
22.2.4 CH[0].EEP
Address offset: 0x510
Channel 0 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.5 CH[0].TEP
Address offset: 0x514
Channel 0 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.6 CH[1].EEP
Address offset: 0x518
Channel 1 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
Page 178
22 PPI — Programmable peripheral interconnect
22.2.7 CH[1].TEP
Address offset: 0x51C
Channel 1 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.8 CH[2].EEP
Address offset: 0x520
Channel 2 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.9 CH[2].TEP
Address offset: 0x524
Channel 2 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.10 CH[3].EEP
Address offset: 0x528
Channel 3 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.11 CH[3].TEP
Address offset: 0x52C
Channel 3 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
Page 179
22 PPI — Programmable peripheral interconnect
22.2.12 CH[4].EEP
Address offset: 0x530
Channel 4 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.13 CH[4].TEP
Address offset: 0x534
Channel 4 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.14 CH[5].EEP
Address offset: 0x538
Channel 5 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.15 CH[5].TEP
Address offset: 0x53C
Channel 5 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.16 CH[6].EEP
Address offset: 0x540
Channel 6 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
Page 180
22 PPI — Programmable peripheral interconnect
22.2.17 CH[6].TEP
Address offset: 0x544
Channel 6 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.18 CH[7].EEP
Address offset: 0x548
Channel 7 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.19 CH[7].TEP
Address offset: 0x54C
Channel 7 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.20 CH[8].EEP
Address offset: 0x550
Channel 8 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.21 CH[8].TEP
Address offset: 0x554
Channel 8 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
Page 181
22 PPI — Programmable peripheral interconnect
22.2.22 CH[9].EEP
Address offset: 0x558
Channel 9 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.23 CH[9].TEP
Address offset: 0x55C
Channel 9 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.24 CH[10].EEP
Address offset: 0x560
Channel 10 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.25 CH[10].TEP
Address offset: 0x564
Channel 10 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.26 CH[11].EEP
Address offset: 0x568
Channel 11 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
Page 182
22 PPI — Programmable peripheral interconnect
22.2.27 CH[11].TEP
Address offset: 0x56C
Channel 11 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.28 CH[12].EEP
Address offset: 0x570
Channel 12 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.29 CH[12].TEP
Address offset: 0x574
Channel 12 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.30 CH[13].EEP
Address offset: 0x578
Channel 13 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.31 CH[13].TEP
Address offset: 0x57C
Channel 13 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
Page 183
22 PPI — Programmable peripheral interconnect
22.2.32 CH[14].EEP
Address offset: 0x580
Channel 14 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.33 CH[14].TEP
Address offset: 0x584
Channel 14 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.34 CH[15].EEP
Address offset: 0x588
Channel 15 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.35 CH[15].TEP
Address offset: 0x58C
Channel 15 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.36 CH[16].EEP
Address offset: 0x590
Channel 16 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
Page 184
22 PPI — Programmable peripheral interconnect
22.2.37 CH[16].TEP
Address offset: 0x594
Channel 16 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.38 CH[17].EEP
Address offset: 0x598
Channel 17 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.39 CH[17].TEP
Address offset: 0x59C
Channel 17 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.40 CH[18].EEP
Address offset: 0x5A0
Channel 18 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.41 CH[18].TEP
Address offset: 0x5A4
Channel 18 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
Page 185
22 PPI — Programmable peripheral interconnect
22.2.42 CH[19].EEP
Address offset: 0x5A8
Channel 19 event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW EEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
22.2.43 CH[19].TEP
Address offset: 0x5AC
Channel 19 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
22.2.44 CHG[0]
Address offset: 0x800
Channel group 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW CH0
B
C
D
E
F
G
H
I
Value Id
Value
Description
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Include or exclude channel 0
RW CH1
Include or exclude channel 1
RW CH2
Include or exclude channel 2
RW CH3
Include or exclude channel 3
RW CH4
Include or exclude channel 4
RW CH5
Include or exclude channel 5
RW CH6
Include or exclude channel 6
RW CH7
Include or exclude channel 7
RW CH8
Include or exclude channel 8
Exclude
Page 186
I H G F E D C B A
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
a
RW Field
Value Id
Value
Description
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
RW CH9
Include or exclude channel 9
RW CH10
Include or exclude channel 10
RW CH11
Include or exclude channel 11
RW CH12
Include or exclude channel 12
RW CH13
Include or exclude channel 13
RW CH14
Include or exclude channel 14
RW CH15
Include or exclude channel 15
RW CH16
Include or exclude channel 16
RW CH17
Include or exclude channel 17
RW CH18
Include or exclude channel 18
RW CH19
Include or exclude channel 19
RW CH20
Include or exclude channel 20
RW CH21
Include or exclude channel 21
RW CH22
Include or exclude channel 22
RW CH23
Include or exclude channel 23
RW CH24
Include or exclude channel 24
RW CH25
Include or exclude channel 25
RW CH26
Include or exclude channel 26
Page 187
I H G F E D C B A
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
b
RW CH27
c
d
e
f
Value Id
Value
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
I H G F E D C B A
Description
Include or exclude channel 27
RW CH28
Include or exclude channel 28
RW CH29
Include or exclude channel 29
RW CH30
Include or exclude channel 30
RW CH31
Include or exclude channel 31
22.2.45 CHG[1]
Address offset: 0x804
Channel group 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW CH0
B
C
D
E
F
G
H
I
J
Value Id
Value
Description
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Include or exclude channel 0
RW CH1
Include or exclude channel 1
RW CH2
Include or exclude channel 2
RW CH3
Include or exclude channel 3
RW CH4
Include or exclude channel 4
RW CH5
Include or exclude channel 5
RW CH6
Include or exclude channel 6
RW CH7
Include or exclude channel 7
RW CH8
Include or exclude channel 8
RW CH9
Include or exclude channel 9
Page 188
I H G F E D C B A
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
K
RW CH10
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
a
b
c
Value Id
Value
Description
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Include or exclude channel 10
RW CH11
Include or exclude channel 11
RW CH12
Include or exclude channel 12
RW CH13
Include or exclude channel 13
RW CH14
Include or exclude channel 14
RW CH15
Include or exclude channel 15
RW CH16
Include or exclude channel 16
RW CH17
Include or exclude channel 17
RW CH18
Include or exclude channel 18
RW CH19
Include or exclude channel 19
RW CH20
Include or exclude channel 20
RW CH21
Include or exclude channel 21
RW CH22
Include or exclude channel 22
RW CH23
Include or exclude channel 23
RW CH24
Include or exclude channel 24
RW CH25
Include or exclude channel 25
RW CH26
Include or exclude channel 26
RW CH27
Include or exclude channel 27
RW CH28
Include or exclude channel 28
Page 189
I H G F E D C B A
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
d
e
f
RW Field
Value Id
Value
Description
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
RW CH29
I H G F E D C B A
Include or exclude channel 29
RW CH30
Include or exclude channel 30
RW CH31
Include or exclude channel 31
22.2.46 CHG[2]
Address offset: 0x808
Channel group 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW CH0
B
C
D
E
F
G
H
I
J
K
L
Value Id
Value
Description
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Include or exclude channel 0
RW CH1
Include or exclude channel 1
RW CH2
Include or exclude channel 2
RW CH3
Include or exclude channel 3
RW CH4
Include or exclude channel 4
RW CH5
Include or exclude channel 5
RW CH6
Include or exclude channel 6
RW CH7
Include or exclude channel 7
RW CH8
Include or exclude channel 8
RW CH9
Include or exclude channel 9
RW CH10
Include or exclude channel 10
RW CH11
Include or exclude channel 11
Page 190
I H G F E D C B A
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
a
b
c
d
RW Field
Value Id
Value
Description
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
RW CH12
Include or exclude channel 12
RW CH13
Include or exclude channel 13
RW CH14
Include or exclude channel 14
RW CH15
Include or exclude channel 15
RW CH16
Include or exclude channel 16
RW CH17
Include or exclude channel 17
RW CH18
Include or exclude channel 18
RW CH19
Include or exclude channel 19
RW CH20
Include or exclude channel 20
RW CH21
Include or exclude channel 21
RW CH22
Include or exclude channel 22
RW CH23
Include or exclude channel 23
RW CH24
Include or exclude channel 24
RW CH25
Include or exclude channel 25
RW CH26
Include or exclude channel 26
RW CH27
Include or exclude channel 27
RW CH28
Include or exclude channel 28
RW CH29
Include or exclude channel 29
Exclude
Page 191
I H G F E D C B A
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
e
f
RW Field
Value Id
Value
Description
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
RW CH30
I H G F E D C B A
Include or exclude channel 30
RW CH31
Include or exclude channel 31
22.2.47 CHG[3]
Address offset: 0x80C
Channel group 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW CH0
B
C
D
E
F
G
H
I
J
K
L
M
Value Id
Value
Description
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Include or exclude channel 0
RW CH1
Include or exclude channel 1
RW CH2
Include or exclude channel 2
RW CH3
Include or exclude channel 3
RW CH4
Include or exclude channel 4
RW CH5
Include or exclude channel 5
RW CH6
Include or exclude channel 6
RW CH7
Include or exclude channel 7
RW CH8
Include or exclude channel 8
RW CH9
Include or exclude channel 9
RW CH10
Include or exclude channel 10
RW CH11
Include or exclude channel 11
RW CH12
Include or exclude channel 12
Exclude
Page 192
I H G F E D C B A
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
a
b
c
d
e
RW Field
Value Id
Value
Description
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
RW CH13
Include or exclude channel 13
RW CH14
Include or exclude channel 14
RW CH15
Include or exclude channel 15
RW CH16
Include or exclude channel 16
RW CH17
Include or exclude channel 17
RW CH18
Include or exclude channel 18
RW CH19
Include or exclude channel 19
RW CH20
Include or exclude channel 20
RW CH21
Include or exclude channel 21
RW CH22
Include or exclude channel 22
RW CH23
Include or exclude channel 23
RW CH24
Include or exclude channel 24
RW CH25
Include or exclude channel 25
RW CH26
Include or exclude channel 26
RW CH27
Include or exclude channel 27
RW CH28
Include or exclude channel 28
RW CH29
Include or exclude channel 29
RW CH30
Include or exclude channel 30
Page 193
I H G F E D C B A
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
f
RW CH31
Value Id
Value
Excluded
0
Exclude
Included
1
Include
I H G F E D C B A
Description
Include or exclude channel 31
22.2.48 CHG[4]
Address offset: 0x810
Channel group 4
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW CH0
B
C
D
E
F
G
H
I
J
K
L
M
N
Value Id
Value
Description
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Include or exclude channel 0
RW CH1
Include or exclude channel 1
RW CH2
Include or exclude channel 2
RW CH3
Include or exclude channel 3
RW CH4
Include or exclude channel 4
RW CH5
Include or exclude channel 5
RW CH6
Include or exclude channel 6
RW CH7
Include or exclude channel 7
RW CH8
Include or exclude channel 8
RW CH9
Include or exclude channel 9
RW CH10
Include or exclude channel 10
RW CH11
Include or exclude channel 11
RW CH12
Include or exclude channel 12
RW CH13
Include or exclude channel 13
Page 194
I H G F E D C B A
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
O
RW CH14
P
Q
R
S
T
U
V
W
X
Y
Z
a
b
c
d
e
f
Value Id
Value
Description
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Include or exclude channel 14
RW CH15
Include or exclude channel 15
RW CH16
Include or exclude channel 16
RW CH17
Include or exclude channel 17
RW CH18
Include or exclude channel 18
RW CH19
Include or exclude channel 19
RW CH20
Include or exclude channel 20
RW CH21
Include or exclude channel 21
RW CH22
Include or exclude channel 22
RW CH23
Include or exclude channel 23
RW CH24
Include or exclude channel 24
RW CH25
Include or exclude channel 25
RW CH26
Include or exclude channel 26
RW CH27
Include or exclude channel 27
RW CH28
Include or exclude channel 28
RW CH29
Include or exclude channel 29
RW CH30
Include or exclude channel 30
RW CH31
Include or exclude channel 31
Page 195
I H G F E D C B A
22 PPI — Programmable peripheral interconnect
22.2.49 CHG[5]
Address offset: 0x814
Channel group 5
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW CH0
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
Value Id
Value
Description
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Include or exclude channel 0
RW CH1
Include or exclude channel 1
RW CH2
Include or exclude channel 2
RW CH3
Include or exclude channel 3
RW CH4
Include or exclude channel 4
RW CH5
Include or exclude channel 5
RW CH6
Include or exclude channel 6
RW CH7
Include or exclude channel 7
RW CH8
Include or exclude channel 8
RW CH9
Include or exclude channel 9
RW CH10
Include or exclude channel 10
RW CH11
Include or exclude channel 11
RW CH12
Include or exclude channel 12
RW CH13
Include or exclude channel 13
RW CH14
Include or exclude channel 14
RW CH15
Include or exclude channel 15
RW CH16
Include or exclude channel 16
Exclude
Page 196
I H G F E D C B A
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
R
S
T
U
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
Excluded
0
Exclude
Included
1
Include
RW CH17
Include or exclude channel 17
RW CH18
Include or exclude channel 18
RW CH19
Include or exclude channel 19
RW CH20
Include or exclude channel 20
RW CH21
Include or exclude channel 21
RW CH22
Include or exclude channel 22
RW CH23
Include or exclude channel 23
RW CH24
Include or exclude channel 24
RW CH25
Include or exclude channel 25
RW CH26
Include or exclude channel 26
RW CH27
Include or exclude channel 27
RW CH28
Include or exclude channel 28
RW CH29
Include or exclude channel 29
RW CH30
Include or exclude channel 30
RW CH31
Include or exclude channel 31
22.2.50 FORK[0].TEP
Address offset: 0x910
Channel 0 task end-point
Page 197
I H G F E D C B A
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.51 FORK[1].TEP
Address offset: 0x914
Channel 1 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.52 FORK[2].TEP
Address offset: 0x918
Channel 2 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.53 FORK[3].TEP
Address offset: 0x91C
Channel 3 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.54 FORK[4].TEP
Address offset: 0x920
Channel 4 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.55 FORK[5].TEP
Address offset: 0x924
Channel 5 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
Page 198
22 PPI — Programmable peripheral interconnect
22.2.56 FORK[6].TEP
Address offset: 0x928
Channel 6 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.57 FORK[7].TEP
Address offset: 0x92C
Channel 7 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.58 FORK[8].TEP
Address offset: 0x930
Channel 8 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.59 FORK[9].TEP
Address offset: 0x934
Channel 9 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.60 FORK[10].TEP
Address offset: 0x938
Channel 10 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.61 FORK[11].TEP
Address offset: 0x93C
Channel 11 task end-point
Page 199
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.62 FORK[12].TEP
Address offset: 0x940
Channel 12 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.63 FORK[13].TEP
Address offset: 0x944
Channel 13 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.64 FORK[14].TEP
Address offset: 0x948
Channel 14 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.65 FORK[15].TEP
Address offset: 0x94C
Channel 15 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.66 FORK[16].TEP
Address offset: 0x950
Channel 16 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
Page 200
22 PPI — Programmable peripheral interconnect
22.2.67 FORK[17].TEP
Address offset: 0x954
Channel 17 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.68 FORK[18].TEP
Address offset: 0x958
Channel 18 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.69 FORK[19].TEP
Address offset: 0x95C
Channel 19 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.70 FORK[20].TEP
Address offset: 0x960
Channel 20 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.71 FORK[21].TEP
Address offset: 0x964
Channel 21 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.72 FORK[22].TEP
Address offset: 0x968
Channel 22 task end-point
Page 201
22 PPI — Programmable peripheral interconnect
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.73 FORK[23].TEP
Address offset: 0x96C
Channel 23 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.74 FORK[24].TEP
Address offset: 0x970
Channel 24 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.75 FORK[25].TEP
Address offset: 0x974
Channel 25 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.76 FORK[26].TEP
Address offset: 0x978
Channel 26 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.77 FORK[27].TEP
Address offset: 0x97C
Channel 27 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
Page 202
22 PPI — Programmable peripheral interconnect
22.2.78 FORK[28].TEP
Address offset: 0x980
Channel 28 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.79 FORK[29].TEP
Address offset: 0x984
Channel 29 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.80 FORK[30].TEP
Address offset: 0x988
Channel 30 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
22.2.81 FORK[31].TEP
Address offset: 0x98C
Channel 31 task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TEP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to task register
Page 203
23 RADIO — 2.4 GHz Radio
23 RADIO — 2.4 GHz Radio
The RADIO contains a 2.4 GHz radio receiver and a 2.4 GHz radio transmitter that is compatible with
Nordic's proprietary 1 Mbps and 2 Mbps radio modes in addition to 1 Mbps Bluetooth® low energy mode.
EasyDMA in combination with an automated packet assembler and packet disassembler, and an automated
CRC generator and CRC checker, makes it very easy to configure and use the RADIO. See Figure 29:
RADIO block diagram on page 204 for details.
RAM
RADIO
PACKETPTR
Device
Address
match
Packet synch
S0
CRC
Packet
disassembler
L
RSSI
Address
match
Dewhitening
2.4 GHz
Receiver
S1
Payload
EasyDMA
IFS
control unit
Bit counter
S0
ANT1
L
Packet
assembler
S1
Payload
CRC
Whitening
2.4 GHz
Transmitter
MAXLEN
Figure 29: RADIO block diagram
The RADIO includes a Device Address Match unit and an interframe spacing control unit that can be
utilized to simplify address white listing and interframe spacing respectively, in Bluetooth Smart and similar
applications.
The RADIO also includes a Received Signal Strength Indicator (RSSI) and a bit counter. The bit counter
generates events when a preconfigured number of bits have been sent or received by the RADIO.
23.1 EasyDMA
The RADIO use EasyDMA for reading and writing of data packets from and to the RAM without CPU
involvement.
As illustrated in Figure 29: RADIO block diagram on page 204, the RADIO's EasyDMA utilizes the same
PACKETPTR for receiving and transmitting packets. The CPU should reconfigure this pointer every time
before the RADIO is started via the START task.
The structure of a radio packet is described in detail in Packet configuration on page 205. The data that
is stored in Data RAM and transported by EasyDMA consists of S0, LENGTH, S1, the payload itself, and a
static add-on sent immediately after the payload.
The size of each of the above elements in the frame is configurable (see Packet configuration on page
205), and the space occupied in RAM depends on these settings. A size of zero is possible for any of the
fields, it is up to the user to make sure that the resulting frame complies with the RF protocol chosen.
For the field sizes defined in bits, the occupation in RAM will always be rounded up to the next full byte size
(for instance 3 bit length will allocate 1 byte in RAM, 9 bit length will allocate 2 bytes, etc.).
In addition, the S0INCL field in PCNF0 determines if S0 is present in RAM at all if its length is zero. If
present, one byte is allocated in RAM.
Page 204
23 RADIO — 2.4 GHz Radio
The size of S0 is configured through the S0LEN field in PCNF0. The size of LENGTH is configured through
the LFLEN field in PCNF0. The size of S1 is configured through the S1LEN field in PCNF0. The size of the
payload is configured through the value in RAM corresponding to the LENGTH field. The size of the static
add-on to the payload is configured through the STATLEN field in PCNF1.
The MAXLEN field in the PCNF1 register configures the maximum packet payload plus add-on size in
number of bytes that can be transmitted or received by the RADIO. This feature can be used to ensure that
the RADIO does not overwrite, or read beyond, the RAM assigned to the packet payload. This means that
if the packet payload length defined by PCNF1.STATLEN and the LENGTH field in the packet specifies a
packet larger than MAXLEN, the payload will be truncated at MAXLEN.
Note that MAXLEN includes the payload and the add-on, but excludes the size occupied by the S0, LENGTH
and S1 fields. This has to be taken into account when allocating RAM.
If the payload plus add-on length is specified larger than MAXLEN, the RADIO will still transmit or receive in
the same way as before except the payload is now truncated to MAXLEN. The packet's LENGTH field will
not be altered when the payload is truncated. The RADIO will calculate CRC as if the packet length is equal
to MAXLEN.
If the PACKETPTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault
or RAM corruption. See Memory on page 23 for more information about the different memory regions.
The DISABLED event indicates that the EasyDMA has finished accessing the RAM.
23.2 Packet configuration
A Radio packet contains the following fields: PREAMBLE, ADDRESS, S0, LENGTH, S1, PAYLOAD and
CRC.
See Figure 30: On-air packet layout on page 205. Not shown in the figure is the static payload add-on (the
length of which is defined in STATLEN, and which is 0 bytes long in a standard BLE packet), and would be
sent between PAYLOAD and CRC. The Radio sends the different fields in the packet in the order they are
illustrated below, from left to right. The preamble will be sent least significant bit first on-air.
BASE
PREFIX
S0
LENGTH
S1
LSByte
MSBit
PREAMBLE
LSBit
LSBit
LSBit
0x55 1 0 1 0 1 0 1 0 1
0xAA 0 1 0 1 0 1 0 1 0
PAYLOAD
LSByte
CRC
MSByte
ADDRESS
Figure 30: On-air packet layout
For all modes that can be specified in the MODE register, the PREAMBLE is one byte long. If the first bit of
the ADDRESS is 0 the preamble will be set to 0xAA otherwise the PREAMBLE will be set to 0x55.
Radio packets are stored in memory inside instances of a radio packet data structure as illustrated in
Figure 31: In-RAM representation of radio packet, S0, LENGTH and S1 are optional on page 205. The
PREAMBLE, ADDRESS and CRC fields are omitted in this data structure.
S0
0
LENGTH
S1
PAYLOAD
LSByte
n
Figure 31: In-RAM representation of radio packet, S0, LENGTH and S1 are optional
The byte ordering on air is always Least Significant Byte First for the ADDRESS and PAYLOAD fields and
Most Significant Byte First for the CRC field. The ADDRESS fields are always transmitted and received least
significant bit first on-air. The CRC field is always transmitted and received Most Significant Bit first. The bit-
Page 205
23 RADIO — 2.4 GHz Radio
endian, i.e. which order the bits are sent and received in, of the S0, LENGTH, S1 and PAYLOAD fields can
be configured via the ENDIAN in PCNF1.
The S0INCL field in PCNF0 determines if S0 is present in RAM at all if its length is zero. If present, one byte
is allocated in RAM.
The sizes of the S0, LENGTH and S1 fields can be individually configured via S0LEN, LFLEN and S1LEN in
PCNF0 respectively. If any of these fields are configured to be less than 8 bit long the, the least significant
bits of the fields, as seen from the RAM representation, are used.
If S0, LENGTH or S1 are specified with zero length their fields will be omitted in memory, otherwise each
field will be represented as a separate byte, regardless of the number of bits in their on-air counterpart.
23.3 Maximum packet length
Independent of the configuration of MAXLEN, the combined length of S0, LENGTH, S1 and PAYLOAD
cannot exceed 258 bytes.
23.4 Address configuration
The on-air radio ADDRESS field is composed of two parts, the base address field and the address prefix
field.
The size of the base address field is configurable via BALEN in PCNF1. The base address is truncated from
LSByte if the BALEN is less than 4. See Table 38: Definition of logical addresses on page 206.
The on-air addresses are defined in the BASEn and PREFIXn registers, and it is only when writing these
registers the user will have to relate to actual on-air addresses. For other radio address registers such as the
TXADDRESS, RXADDRESSES and RXMATCH registers, logical radio addresses ranging from 0 to 7 are
being used. The relationship between the on-air radio addresses and the logical addresses is described in
Table 38: Definition of logical addresses on page 206.
Table 38: Definition of logical addresses
Logical address
0
1
2
3
4
5
6
7
Base address
BASE0
BASE1
BASE1
BASE1
BASE1
BASE1
BASE1
BASE1
Prefix byte
PREFIX0.AP0
PREFIX0.AP1
PREFIX0.AP2
PREFIX0.AP3
PREFIX1.AP4
PREFIX1.AP5
PREFIX1.AP6
PREFIX1.AP7
23.5 Data whitening
The RADIO is able to do packet whitening and de-whitening.
See WHITEEN in PCNF1 register for how to enable whitening. When enabled, whitening and de-whitening
will be handled by the RADIO automatically as packets are sent and received.
7
4
The whitening word is generated using polynomial g(D) = D + D + 1, which then is XORed with the data
packet that is to be whitened, or de-whitened. See the figure below.
Page 206
23 RADIO — 2.4 GHz Radio
D0
D4
D7
Data out
+
Position
0
1
2
+
3
4
5
6
Data in
Figure 32: Data whitening and de-whitening
Whitening and de-whitening will be performed over the whole packet (except for the preamble and the
address field).
The linear feedback shift register, illustrated in Figure 32: Data whitening and de-whitening on page 207
can be initialised via the DATAWHITEIV register.
23.6 CRC
The CRC generator in the RADIO calculates the CRC over the whole packet excluding the preamble. If
desirable, the address field can be excluded from the CRC calculation as well
See CRCCNF register for more information.
The CRC polynomial is configurable as illustrated in Figure 33: CRC generation of an n bit CRC on page
0
1
207 where bit 0 in the CRCPOLY register corresponds to X and bit 1 corresponds to X etc. See
CRCPOLY for more information.
Xn-1
Xn
X2
X1
X0
Packet
(Clocked in serially)
+
+
+
bn
+
+
b0
Figure 33: CRC generation of an n bit CRC
As illustrated in Figure 33: CRC generation of an n bit CRC on page 207, the CRC is calculated by feeding
the packet serially through the CRC generator. Before the packet is clocked through the CRC generator, the
CRC generator's latches b0 through bn will be initialized with a predefined value specified in the CRCINIT
register. When the whole packet is clocked through the CRC generator, latches b0 through bn will hold the
resulting CRC. This value will be used by the RADIO during both transmission and reception but it is not
available to be read by the CPU at any time. A received CRC can however be read by the CPU via the
RXCRC register independent of whether or not it has passed the CRC check.
The length (n) of the CRC is configurable, see CRCCNF for more information.
After the whole packet including the CRC has been received, the RADIO will generate a CRCOK event if no
CRC errors were detected, or alternatively generate a CRCERROR event if CRC errors were detected.
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23 RADIO — 2.4 GHz Radio
The status of the CRC check can be read from the CRCSTATUS register after a packet has been received.
23.7 Radio states
The RADIO can enter a number of states.
The RADIO can enter the states described the table below. An overview state diagram for the RADIO is
illustrated in Figure 34: Radio states on page 208. This figure shows how the tasks and events relate to
the RADIO's operation. The RADIO does not prevent a task from being triggered from the wrong state. If a
task is triggered from the wrong state, for example if the RXEN task is triggered from the RXDISABLE state,
this may lead to incorrect behaviour. As illustrated in Figure 34: Radio states on page 208, the PAYLOAD
event is always generated even if the payload is zero.
Table 39: RADIO state diagram
State
DISABLED
RXRU
RXIDLE
RX
TXRU
TXIDLE
TX
RXDISABLE
TXDISABLE
Description
No operations are going on inside the radio and the power consumption is at a minimum
The radio is ramping up and preparing for reception
The radio is ready for reception to start
Reception has been started and the addresses enabled in the RXADDRESSES register are being monitored
The radio is ramping up and preparing for transmission
The radio is ready for transmission to start
The radio is transmitting a packet
The radio is disabling the receiver
The radio is disabling the transmitter
DISABLE
Address sent / ADDRESS
START
TXDISABLE
TXRU
/ DISABLED
Ramp-up
complete
/ READY
TXIDLE
TX
STOP
Packet sent / END
TXEN
Payload sent [payload length >=0]
/ PAYLOAD
DISABLED
/ DISABLED
RXDISABLE
RXEN
RXRU
Packet received / END
Ramp-up
complete
/ READY
Address received [Address match]
/ ADDRESS
START
RXIDLE
RX
STOP
Payload received [payload length >=0]
/ PAYLOAD
DISABLE
Figure 34: Radio states
23.8 Transmit sequence
Before the RADIO is able to transmit a packet, it must first ramp-up in TX mode.
See TXRU in Figure 34: Radio states on page 208 and Figure 35: Transmit sequence on page 209.
A TXRU ramp-up sequence is initiated when the TXEN task is triggered. After the radio has successfully
ramped up it will generate the READY event indicating that a packet transmission can be initiate. A packet
transmission is initiated by triggering the START task. As illustrated in Figure 34: Radio states on page 208
the START task can first be triggered after the RADIO has entered into the TXIDLE state.
Figure 35: Transmit sequence on page 209 illustrates a single packet transmission where the CPU
manually triggers the different tasks needed to control the flow of the RADIO, i.e. no shortcuts are used. If
shortcuts are not used, a certain amount of delay caused by CPU execution is expected between READY
and START, and between END and DISABLE. As illustrated in Figure 35: Transmit sequence on page 209
Page 208
23 RADIO — 2.4 GHz Radio
TX
PAYLOAD
CRC
ADDRESS
S0 L S1
(carrier)
2
DISABLE
3
START
1
TXEN
Lifeline
READY
A
TXDISABLE
END
P
(carrier)
TXIDLE
DISABLED
TXIDLE
Transmitter
TXRU
PAYLOAD
State
the RADIO will by default transmit '1's between READY and START, and between END and DISABLED.
What is transmitted can be programmed through the DTX field in the MODECNF0 register.
Figure 35: Transmit sequence
TX
S0 L S1
PAYLOAD
PAYLOAD
CRC
(carrier)
DISABLED
A
TXDISABLE
1
DISABLE
2
START
TXEN
Lifeline
READY
P
ADDRESS
Transmitter
TXRU
END
State
A slightly modified version of the transmit sequence from Figure 35: Transmit sequence on page 209 is
illustrated in Figure 36: Transmit sequence using shortcuts to avoid delays on page 209 where the RADIO
is configured to use shortcuts between READY and START, and between END and DISABLE, which means
that no delay is introduced.
Figure 36: Transmit sequence using shortcuts to avoid delays
The RADIO is able to send multiple packets one after the other without having to disable and re-enable the
RADIO between packets, this is illustrated in Figure 37: Transmission of multiple packets on page 210.
Page 209
PAYLOAD
CRC
(carrier)
P
A
S0 L S1
PAYLOAD
(carrier)
START
TXEN
3
DISABLE
2
START
1
CRC
DISABLED
PAYLOAD
PAYLOAD
S0 L S1
TXDISABLE
TX
ADDRESS
A
ADDRESS
Lifeline
READY
P
TXIDLE
END
TX
Transmitter
TXRU
END
State
23 RADIO — 2.4 GHz Radio
Figure 37: Transmission of multiple packets
23.9 Receive sequence
Before the RADIO is able to receive a packet, it must first ramp up in RX mode
See RXRU in Figure 34: Radio states on page 208 and Figure 38: Receive sequence on page 210.
An RXRU ramp-up sequence is initiated when the RXEN task is triggered. After the radio has successfully
ramped up it will generate the READY event indicating that a packet reception can be initiated. A packet
reception is initiated by triggering the START task. As illustrated in Figure 34: Radio states on page 208
the START task can, first be triggered after the RADIO has entered into the RXIDLE state.
RX
S0 L S1
2
PAYLOAD
RXDISABLE
CRC
DISABLED
A
ADDRESS
P
DISABLE
3
START
1
RXEN
Lifeline
READY
’X’
RXIDLE
END
RXIDLE
Reception
RXRU
PAYLOAD
State
Figure 38: Receive sequence on page 210 illustrates a single packet reception where the CPU manually
triggers the different tasks needed to control the flow of the RADIO, i.e. no shortcuts are used. If shortcuts
are not used, a certain amount of delay, caused by CPU execution, is expected between READY and
START, and between END and DISABLE. As illustrated Figure 38: Receive sequence on page 210 the
RADIO will be listening and possibly receiving undefined data, illustrated with an 'X', from START and until a
packet with valid preamble (P) is received.
Figure 38: Receive sequence
A slightly modified version of the receive sequence from Figure 38: Receive sequence on page 210 is
illustrated in Figure 39: Receive sequence using shortcuts to avoid delays on page 211 where the the
RADIO is configured to use shortcuts between READY and START, and between END and DISABLE, which
means that no delay is introduced.
Page 210
RX
A
PAYLOAD
ADDRESS
Lifeline
S0 L S1
CRC
DISABLED
P
READY
’X’
RXDISABLE
PAYLOAD
Reception
RXRU
END
State
23 RADIO — 2.4 GHz Radio
1
DISABLE
RXEN
START
2
Figure 39: Receive sequence using shortcuts to avoid delays
’X’ P
A
S0 L S1
PAYLOAD
CRC
DISABLED
CRC
END
PAYLOAD
ADDRESS
S0 L S1
RXDISABLE
RX
END
A
START
3
DISABLE
2
START
1
RXEN
Lifeline
READY
’X’ P
RXIDLE
PAYLOAD
RX
ADDRESS
Receiver
RXRU
PAYLOAD
State
The RADIO is able to receive multiple packets one after the other without having to disable and re-enable
the RADIO between packets, this is illustrated Figure 40: Reception of multiple packets on page 211.
Figure 40: Reception of multiple packets
23.10 Received Signal Strength Indicator (RSSI)
The radio implements a mechanism for measuring the power in the received radio signal. This feature is
called Received Signal Strength Indicator (RSSI).
Sampling of the received signal strength is started by using the RSSISTART task. The sample can be read
from the RSSISAMPLE register.
The sample period of the RSSI is defined by RSSIPERIOD, see the device product specification for details.
The RSSI sample will hold the average received signal strength during this sample period.
For the RSSI sample to be valid the radio has to be enabled in receive mode (RXEN task) and the reception
has to be started (READY event followed by START task).
23.11 Interframe spacing
Interframe spacing is the time interval between two consecutive packets.
It is defined as the time, in micro seconds, from the end of the last bit of the previous packet received and
to the start of the first bit of the subsequent packet that is transmitted. The RADIO is able to enforce this
Page 211
23 RADIO — 2.4 GHz Radio
interval as specified in the TIFS register as long as TIFS is not specified to be shorter than the RADIO’s turnaround time, i.e. the time needed to switch off the receiver, and switch back on the transmitter.
TIFS is only enforced if END_DISABLE and DISABLED_TXEN or END_DISABLE and DISABLED_RXEN
shortcuts are enabled. TIFS is only qualified for use in BLE_1MBIT mode, and default ramp-up mode.
23.12 Device address match
The device address match feature is tailored for address white listing in a Bluetooth Smart and similar
implementations.
This feature enables on-the-fly device address matching while receiving a packet on air. This feature only
works in receive mode and as long as RADIO is configured for little endian, see PCNF1.ENDIAN.
The Device Address match unit assumes that the 48 first bits of the payload is the device address and that
bit number 6 in S0 is the TxAdd bit. See the Bluetooth Core Specification for more information about device
addresses, TxAdd and whitelisting.
The RADIO is able to listen for eight different device addresses at the same time. These addresses are
specified in a DAB/DAP register pair, one pair per address, in addition to a TxAdd bit configured in the
DACNF register. The DAB register specifies the 32 least significant bits of the device address, while the DAP
register specifies the 16 most significant bits of the device address.
Each of the device addresses can be individually included or excluded from the matching mechanism. This is
configured in the DACNF register.
23.13 Bit counter
The RADIO implements a simple counter that can be configured to generate an event after a specific number
of bits have been transmitted or received.
By using shortcuts, this counter can be started from different events generated by the RADIO and hence
count relative to these.
The bit counter is started by triggering the BCSTART task, and stopped by triggering the BCSTOP task.
A BCMATCH event will be generated when the bit counter has counted the number of bits specified in the
BCC register. The bit counter will continue to count bits until the DISABLED event is generated or until the
BCSTOP task is triggered. The CPU can therefore, after a BCMATCH event, reconfigure the BCC value for
new BCMATCH events within the same packet.
The bit counter can only be started after the RADIO has received the ADDRESS event.
The bit counter will stop and reset on BCSTOP, STOP, END and DISABLE tasks.
The figure below illustrates how the bit counter can be used to generate a BCMATCH event in the beginning
of the packet payload, and again generate a second BCMATCH event after sending 2 bytes (16 bits) of the
payload.
Page 212
RX
DISABLED
CRC
3
DISABLE
BCC = 12 + 16
BCSTART
START
BCMATCH
BCMATCH
READY
2
BCC = 12
2
PAYLOAD
1
RXEN
1
S0 L S1
PAYLOAD
Lifeline
This example
assumes that the
combined length
of S0, Length (L)
and S1 is 12
bits.
A
ADDRESS
Reception
0
’X’ P
RXDISABLE
END
RXRU
BCSTOP
State
23 RADIO — 2.4 GHz Radio
Figure 41: Bit counter example
23.14 Registers
Table 40: Instances
Base address
Peripheral
Instance
Description
0x40001000
RADIO
RADIO
2.4 GHz radio
Configuration
Table 41: Register Overview
Register
Offset
Description
TASKS_TXEN
0x000
Enable RADIO in TX mode
TASKS_RXEN
0x004
Enable RADIO in RX mode
TASKS_START
0x008
Start RADIO
TASKS_STOP
0x00C
Stop RADIO
TASKS_DISABLE
0x010
Disable RADIO
TASKS_RSSISTART
0x014
Start the RSSI and take one single sample of the receive signal strength.
TASKS_RSSISTOP
0x018
Stop the RSSI measurement
TASKS_BCSTART
0x01C
Start the bit counter
TASKS_BCSTOP
0x020
Stop the bit counter
EVENTS_READY
0x100
RADIO has ramped up and is ready to be started
EVENTS_ADDRESS
0x104
Address sent or received
EVENTS_PAYLOAD
0x108
Packet payload sent or received
EVENTS_END
0x10C
Packet sent or received
EVENTS_DISABLED
0x110
RADIO has been disabled
EVENTS_DEVMATCH
0x114
A device address match occurred on the last received packet
EVENTS_DEVMISS
0x118
No device address match occurred on the last received packet
EVENTS_RSSIEND
0x11C
Sampling of receive signal strength complete.
EVENTS_BCMATCH
0x128
Bit counter reached bit count value.
EVENTS_CRCOK
0x130
Packet received with CRC ok
EVENTS_CRCERROR
0x134
Packet received with CRC error
SHORTS
0x200
Shortcut register
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
CRCSTATUS
0x400
CRC status
RXMATCH
0x408
Received address
RXCRC
0x40C
CRC field of previously received packet
Page 213
23 RADIO — 2.4 GHz Radio
Register
Offset
Description
DAI
0x410
Device address match index
PACKETPTR
0x504
Packet pointer
FREQUENCY
0x508
Frequency
TXPOWER
0x50C
Output power
MODE
0x510
Data rate and modulation
PCNF0
0x514
Packet configuration register 0
PCNF1
0x518
Packet configuration register 1
BASE0
0x51C
Base address 0
BASE1
0x520
Base address 1
PREFIX0
0x524
Prefixes bytes for logical addresses 0-3
PREFIX1
0x528
Prefixes bytes for logical addresses 4-7
TXADDRESS
0x52C
Transmit address select
RXADDRESSES
0x530
Receive address select
CRCCNF
0x534
CRC configuration
CRCPOLY
0x538
CRC polynomial
CRCINIT
0x53C
CRC initial value
0x540
Reserved
TIFS
0x544
Inter Frame Spacing in us
RSSISAMPLE
0x548
RSSI sample
STATE
0x550
Current radio state
DATAWHITEIV
0x554
Data whitening initial value
BCC
0x560
Bit counter compare
DAB[0]
0x600
Device address base segment 0
DAB[1]
0x604
Device address base segment 1
DAB[2]
0x608
Device address base segment 2
DAB[3]
0x60C
Device address base segment 3
DAB[4]
0x610
Device address base segment 4
DAB[5]
0x614
Device address base segment 5
DAB[6]
0x618
Device address base segment 6
DAB[7]
0x61C
Device address base segment 7
DAP[0]
0x620
Device address prefix 0
DAP[1]
0x624
Device address prefix 1
DAP[2]
0x628
Device address prefix 2
DAP[3]
0x62C
Device address prefix 3
DAP[4]
0x630
Device address prefix 4
DAP[5]
0x634
Device address prefix 5
DAP[6]
0x638
Device address prefix 6
DAP[7]
0x63C
Device address prefix 7
DACNF
0x640
Device address match configuration
MODECNF0
0x650
Radio mode configuration register 0
POWER
0xFFC
Peripheral power control
23.14.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H
Reset 0x00000000
Id
RW Field
A
RW READY_START
0
Value Id
Value
Description
Shortcut between READY event and START task
See EVENTS_READY and TASKS_START
B
G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW END_DISABLE
Shortcut between END event and DISABLE task
See EVENTS_END and TASKS_DISABLE
Page 214
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H
Reset 0x00000000
Id
C
RW Field
0
G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW DISABLED_TXEN
Shortcut between DISABLED event and TXEN task
See EVENTS_DISABLED and TASKS_TXEN
D
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW DISABLED_RXEN
Shortcut between DISABLED event and RXEN task
See EVENTS_DISABLED and TASKS_RXEN
E
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW ADDRESS_RSSISTART
Shortcut between ADDRESS event and RSSISTART task
See EVENTS_ADDRESS and TASKS_RSSISTART
F
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW END_START
Shortcut between END event and START task
See EVENTS_END and TASKS_START
G
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW ADDRESS_BCSTART
Shortcut between ADDRESS event and BCSTART task
See EVENTS_ADDRESS and TASKS_BCSTART
H
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW DISABLED_RSSISTOP
Shortcut between DISABLED event and RSSISTOP task
See EVENTS_DISABLED and TASKS_RSSISTOP
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
23.14.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
I
Value
Description
Write '1' to Enable interrupt for READY event
See EVENTS_READY
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ADDRESS
Write '1' to Enable interrupt for ADDRESS event
See EVENTS_ADDRESS
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PAYLOAD
Write '1' to Enable interrupt for PAYLOAD event
See EVENTS_PAYLOAD
D
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW END
Write '1' to Enable interrupt for END event
Page 215
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K
Reset 0x00000000
Id
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_END
E
RW DISABLED
Write '1' to Enable interrupt for DISABLED event
See EVENTS_DISABLED
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DEVMATCH
Write '1' to Enable interrupt for DEVMATCH event
See EVENTS_DEVMATCH
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DEVMISS
Write '1' to Enable interrupt for DEVMISS event
See EVENTS_DEVMISS
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RSSIEND
Write '1' to Enable interrupt for RSSIEND event
See EVENTS_RSSIEND
I
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW BCMATCH
Write '1' to Enable interrupt for BCMATCH event
See EVENTS_BCMATCH
K
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CRCOK
Write '1' to Enable interrupt for CRCOK event
See EVENTS_CRCOK
L
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CRCERROR
Write '1' to Enable interrupt for CRCERROR event
See EVENTS_CRCERROR
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
23.14.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
I
Value
Description
Write '1' to Disable interrupt for READY event
See EVENTS_READY
Clear
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Disable
Page 216
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K
Reset 0x00000000
Id
B
RW Field
0
I
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ADDRESS
Write '1' to Disable interrupt for ADDRESS event
See EVENTS_ADDRESS
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PAYLOAD
Write '1' to Disable interrupt for PAYLOAD event
See EVENTS_PAYLOAD
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW END
Write '1' to Disable interrupt for END event
See EVENTS_END
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DISABLED
Write '1' to Disable interrupt for DISABLED event
See EVENTS_DISABLED
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DEVMATCH
Write '1' to Disable interrupt for DEVMATCH event
See EVENTS_DEVMATCH
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DEVMISS
Write '1' to Disable interrupt for DEVMISS event
See EVENTS_DEVMISS
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RSSIEND
Write '1' to Disable interrupt for RSSIEND event
See EVENTS_RSSIEND
I
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW BCMATCH
Write '1' to Disable interrupt for BCMATCH event
See EVENTS_BCMATCH
K
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CRCOK
Write '1' to Disable interrupt for CRCOK event
See EVENTS_CRCOK
L
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CRCERROR
Write '1' to Disable interrupt for CRCERROR event
See EVENTS_CRCERROR
Clear
1
Disable
Disabled
0
Read: Disabled
Page 217
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K
Reset 0x00000000
Id
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Read: Enabled
23.14.4 CRCSTATUS
Address offset: 0x400
CRC status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
CRCError
0
Packet received with CRC error
CRCOk
1
Packet received with CRC ok
CRCSTATUS
CRC status of packet received
23.14.5 RXMATCH
Address offset: 0x408
Received address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
RXMATCH
Received address
Logical address of which previous packet was received
23.14.6 RXCRC
Address offset: 0x40C
CRC field of previously received packet
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
RXCRC
CRC field of previously received packet
CRC field of previously received packet
23.14.7 DAI
Address offset: 0x410
Device address match index
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
DAI
Device address match index
Index (n) of device address, see DAB[n] and DAP[n], that got an
address match.
23.14.8 PACKETPTR
Address offset: 0x504
Page 218
23 RADIO — 2.4 GHz Radio
Packet pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PACKETPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Packet pointer
Packet address to be used for the next transmission or
reception. When transmitting, the packet pointed to by this
address will be transmitted and when receiving, the received
packet will be written to this address. This address is a byte
aligned ram address.
23.14.9 FREQUENCY
Address offset: 0x508
Frequency
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
Reset 0x00000002
Id
RW Field
A
RW FREQUENCY
B
RW MAP
0
Value Id
A A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value
Description
[0..100]
Radio channel frequency
Frequency = 2400 + FREQUENCY (MHz).
Channel map selection.
Default
0
Low
1
Channel map between 2400 MHZ .. 2500 MHz
Frequency = 2400 + FREQUENCY (MHz)
Channel map between 2360 MHZ .. 2460 MHz
Frequency = 2360 + FREQUENCY (MHz)
23.14.10 TXPOWER
Address offset: 0x50C
Output power
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TXPOWER
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
RADIO output power.
Output power in number of dBm, i.e. if the value -20 is specified
the output power will be set to -20dBm.
Pos4dBm
0x04
+4 dBm
Pos3dBm
0x03
+3 dBm
0dBm
0x00
0 dBm
Neg4dBm
0xFC
-4 dBm
Neg8dBm
0xF8
-8 dBm
Neg12dBm
0xF4
-12 dBm
Neg16dBm
0xF0
-16 dBm
Neg20dBm
0xEC
-20 dBm
Neg30dBm
0xD8
-40 dBm
Neg40dBm
0xD8
-40 dBm
23.14.11 MODE
Address offset: 0x510
Data rate and modulation
Page 219
Deprecated
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW MODE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Radio data rate and modulation setting. The radio supports
Frequency-shift Keying (FSK) modulation.
Nrf_1Mbit
0
1 Mbit/s Nordic proprietary radio mode
Nrf_2Mbit
1
2 Mbit/s Nordic proprietary radio mode
Nrf_250Kbit
2
250 kbit/s Nordic proprietary radio mode
Ble_1Mbit
3
1 Mbit/s Bluetooth Low Energy
Deprecated
23.14.12 PCNF0
Address offset: 0x514
Packet configuration register 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00000000
0
Id
RW Field
A
RW LFLEN
Length on air of LENGTH field in number of bits.
C
RW S0LEN
Length on air of S0 field in number of bytes.
E
RW S1LEN
Length on air of S1 field in number of bits.
F
RW S1INCL
G
Value Id
F E E E E
C
A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Include or exclude S1 field in RAM
Automatic
0
Include S1 field in RAM only if S1LEN > 0
Include
1
Always include S1 field in RAM independent of S1LEN
8bit
0
8-bit preamble
16bit
1
16-bit preamble
RW PLEN
Length of preamble on air. Decision point: TASKS_START task
23.14.13 PCNF1
Address offset: 0x518
Packet configuration register 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E D
Reset 0x00000000
Id
RW Field
A
RW MAXLEN
0
Value Id
C C C B B B B B B B B A A A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..255]
Maximum length of packet payload. If the packet payload is
larger than MAXLEN, the radio will truncate the payload to
MAXLEN.
B
RW STATLEN
[0..255]
Static length in number of bytes
The static length parameter is added to the total length of the
payload when sending and receiving packets, e.g. if the static
length is set to N the radio will receive or send N bytes more
than what is defined in the LENGTH field of the packet.
C
RW BALEN
[2..4]
Base address length in number of bytes
The address field is composed of the base address and the one
byte long address prefix, e.g. set BALEN=2 to get a total address
of 3 bytes.
D
RW ENDIAN
On air endianness of packet, this applies to the S0, LENGTH, S1
and the PAYLOAD fields.
E
Little
0
Least Significant bit on air first
Big
1
Most significant bit on air first
Disabled
0
Disable
Enabled
1
Enable
RW WHITEEN
Enable or disable packet whitening
Page 220
23 RADIO — 2.4 GHz Radio
23.14.14 BASE0
Address offset: 0x51C
Base address 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW BASE0
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Base address 0
Radio base address 0.
23.14.15 BASE1
Address offset: 0x520
Base address 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW BASE1
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Base address 1
Radio base address 1.
23.14.16 PREFIX0
Address offset: 0x524
Prefixes bytes for logical addresses 0-3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0x00000000
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
Value
A
RW AP0
Description
Address prefix 0.
B
RW AP1
Address prefix 1.
C
RW AP2
Address prefix 2.
D
RW AP3
Address prefix 3.
23.14.17 PREFIX1
Address offset: 0x528
Prefixes bytes for logical addresses 4-7
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0x00000000
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
Value
A
RW AP4
Description
Address prefix 4.
B
RW AP5
Address prefix 5.
C
RW AP6
Address prefix 6.
D
RW AP7
Address prefix 7.
23.14.18 TXADDRESS
Address offset: 0x52C
Transmit address select
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23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
RW TXADDRESS
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Transmit address select
Logical address to be used when transmitting a packet.
23.14.19 RXADDRESSES
Address offset: 0x530
Receive address select
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G F E D C B A
Reset 0x00000000
Id
RW Field
A
RW ADDR0
B
C
D
E
F
G
H
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Enable or disable reception on logical address 0.
RW ADDR1
Enable or disable reception on logical address 1.
RW ADDR2
Enable or disable reception on logical address 2.
RW ADDR3
Enable or disable reception on logical address 3.
RW ADDR4
Enable or disable reception on logical address 4.
RW ADDR5
Enable or disable reception on logical address 5.
RW ADDR6
Enable or disable reception on logical address 6.
RW ADDR7
Enable or disable reception on logical address 7.
23.14.20 CRCCNF
Address offset: 0x534
CRC configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
Reset 0x00000000
Id
RW Field
A
RW LEN
B
0
Value Id
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[1..3]
CRC length in number of bytes.
Disabled
0
CRC length is zero and CRC calculation is disabled
One
1
CRC length is one byte and CRC calculation is enabled
Two
2
CRC length is two bytes and CRC calculation is enabled
Three
3
CRC length is three bytes and CRC calculation is enabled
Include
0
CRC calculation includes address field
Skip
1
CRC calculation does not include address field. The CRC
RW SKIPADDR
Include or exclude packet address field out of CRC calculation.
calculation will start at the first byte after the address.
Page 222
23 RADIO — 2.4 GHz Radio
23.14.21 CRCPOLY
Address offset: 0x538
CRC polynomial
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CRCPOLY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
CRC polynomial
Each term in the CRC polynomial is mapped to a bit in this
register which index corresponds to the term's exponent. The
least significant term/bit is hard-wired internally to 1, and bit
number 0 of the register content is ignored by the hardware.
The following example is for an 8 bit CRC polynomial: x8 + x7 +
x3 + x2 + 1 = 1 1000 1101 .
23.14.22 CRCINIT
Address offset: 0x53C
CRC initial value
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CRCINIT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
CRC initial value
Initial value for CRC calculation.
23.14.23 TIFS
Address offset: 0x544
Inter Frame Spacing in us
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TIFS
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Inter Frame Spacing in us
Inter frame space is the time interval between two consecutive
packets. It is defined as the time, in micro seconds, from the
end of the last bit of the previous packet to the start of the first
bit of the subsequent packet.
23.14.24 RSSISAMPLE
Address offset: 0x548
RSSI sample
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
RSSISAMPLE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..127]
RSSI sample
RSSI sample result. The value of this register is read as a positive
value while the actual received signal strength is a negative
value. Actual received signal strength is therefore as follows:
received signal strength = -A dBm
Page 223
23 RADIO — 2.4 GHz Radio
23.14.25 STATE
Address offset: 0x550
Current radio state
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
RADIO is in the Disabled state
RxRu
1
RADIO is in the RXRU state
RxIdle
2
RADIO is in the RXIDLE state
Rx
3
RADIO is in the RX state
RxDisable
4
RADIO is in the RXDISABLED state
TxRu
9
RADIO is in the TXRU state
TxIdle
10
RADIO is in the TXIDLE state
Tx
11
RADIO is in the TX state
TxDisable
12
RADIO is in the TXDISABLED state
STATE
Current radio state
23.14.26 DATAWHITEIV
Address offset: 0x554
Data whitening initial value
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A
Reset 0x00000040
Id
RW Field
A
RW DATAWHITEIV
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Value
Description
Data whitening initial value. Bit 6 is hard-wired to '1', writing '0'
to it has no effect, and it will always be read back and used by
the device as '1'.
Bit 0 corresponds to Position 6 of the LSFR, Bit 1 to Position 5,
etc.
23.14.27 BCC
Address offset: 0x560
Bit counter compare
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW BCC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Bit counter compare
Bit counter compare register
23.14.28 DAB[0]
Address offset: 0x600
Device address base segment 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 0
Page 224
23 RADIO — 2.4 GHz Radio
23.14.29 DAB[1]
Address offset: 0x604
Device address base segment 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 1
23.14.30 DAB[2]
Address offset: 0x608
Device address base segment 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 2
23.14.31 DAB[3]
Address offset: 0x60C
Device address base segment 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 3
23.14.32 DAB[4]
Address offset: 0x610
Device address base segment 4
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 4
23.14.33 DAB[5]
Address offset: 0x614
Device address base segment 5
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 5
23.14.34 DAB[6]
Address offset: 0x618
Device address base segment 6
Page 225
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 6
23.14.35 DAB[7]
Address offset: 0x61C
Device address base segment 7
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 7
23.14.36 DAP[0]
Address offset: 0x620
Device address prefix 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 0
23.14.37 DAP[1]
Address offset: 0x624
Device address prefix 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 1
23.14.38 DAP[2]
Address offset: 0x628
Device address prefix 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 2
23.14.39 DAP[3]
Address offset: 0x62C
Device address prefix 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 3
Page 226
23 RADIO — 2.4 GHz Radio
23.14.40 DAP[4]
Address offset: 0x630
Device address prefix 4
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 4
23.14.41 DAP[5]
Address offset: 0x634
Device address prefix 5
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 5
23.14.42 DAP[6]
Address offset: 0x638
Device address prefix 6
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 6
23.14.43 DAP[7]
Address offset: 0x63C
Device address prefix 7
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 7
23.14.44 DACNF
Address offset: 0x640
Device address match configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
P O N M L K J
Reset 0x00000000
Id
RW Field
A
RW ENA0
0
Value Id
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable device address matching using device address
0
B
Disabled
0
Disabled
Enabled
1
Enabled
RW ENA1
Enable or disable device address matching using device address
1
Disabled
0
Disabled
Page 227
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
P O N M L K J
Reset 0x00000000
Id
C
RW Field
0
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Enabled
RW ENA2
Enable or disable device address matching using device address
2
D
Disabled
0
Disabled
Enabled
1
Enabled
RW ENA3
Enable or disable device address matching using device address
3
E
Disabled
0
Disabled
Enabled
1
Enabled
RW ENA4
Enable or disable device address matching using device address
4
F
Disabled
0
Disabled
Enabled
1
Enabled
RW ENA5
Enable or disable device address matching using device address
5
G
Disabled
0
Disabled
Enabled
1
Enabled
RW ENA6
Enable or disable device address matching using device address
6
H
Disabled
0
Disabled
Enabled
1
Enabled
RW ENA7
Enable or disable device address matching using device address
7
Disabled
0
Disabled
Enabled
1
Enabled
I
RW TXADD0
TxAdd for device address 0
J
RW TXADD1
TxAdd for device address 1
K
RW TXADD2
TxAdd for device address 2
L
RW TXADD3
TxAdd for device address 3
M
RW TXADD4
TxAdd for device address 4
N
RW TXADD5
TxAdd for device address 5
O
RW TXADD6
TxAdd for device address 6
P
RW TXADD7
TxAdd for device address 7
23.14.45 MODECNF0
Address offset: 0x650
Radio mode configuration register 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C C
Reset 0x00000200
Id
RW Field
A
RW RU
0
Value Id
Value
Default
0
Fast
1
Description
Radio ramp-up time
Default ramp-up time (tRXEN), compatible with firmware
written for nRF51
Fast ramp-up (tRXEN,FAST), see electrical specification for more
information
C
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
RW DTX
Default TX value
Specifies what the RADIO will transmit when it is not started, i.e.
between:
RADIO.EVENTS_READY and RADIO.TASKS_START
RADIO.EVENTS_END and RADIO.TASKS_START
Page 228
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C C
Reset 0x00000200
Id
0
RW Field
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
B1
0
Transmit '1'
B0
1
Transmit '0'
Center
2
Transmit center frequency
RADIO.EVENTS_END and RADIO.EVENTS_DISABLED
When tuning the crystal for centre frequency, the RADIO must
be set in DTX = Center mode to be able to achieve the expected
accuracy.
23.14.46 POWER
Address offset: 0xFFC
Peripheral power control
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000001
Id
RW Field
A
RW POWER
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value
Description
Peripheral power control. The peripheral and its registers will be
reset to its initial state by switching the peripheral off and then
back on again.
Disabled
0
Peripheral is powered off
Enabled
1
Peripheral is powered on
23.15 Electrical specification
23.15.1 General Radio Characteristics
Symbol
Description
Min.
fOP
Operating frequencies
2360
Typ.
fPLL,PROG,RES
PLL programming resolution
2
kHz
fPLL,CH,SP
PLL channel spacing
1
MHz
fDELTA,1M
Frequency deviation @ 1 Msps
±170
kHz
fDELTA,BLE,1M
Frequency deviation @ BLE 1Msps
±250
kHz
fDELTA,2M
Frequency deviation @ 2 Msps
±320
fskSPS
On-the-air data rate
1
Max.
Units
2500
MHz
kHz
2
Msps
Max.
Units
23.15.2 Radio current consumption (Transmitter)
Symbol
Description
ITX,PLUS4dBM,DCDC
TX only run current (DCDC, 3V) PRF =+4 dBm
Min.
7.5
mA
ITX,PLUS4dBM
TX only run current PRF = +4 dBm
16.6
mA
ITX,0dBM,DCDC
TX only run current (DCDC, 3V)PRF = 0dBm
5.3
mA
ITX,0dBM
TX only run current PRF = 0dBm
11.6
mA
ITX,MINUS4dBM,DCDC
TX only run current DCDC, 3V PRF = -4dBm
4.2
mA
ITX,MINUS4dBM
TX only run current PRF = -4 dBm
9.3
mA
ITX,MINUS8dBM,DCDC
TX only run current DCDC, 3V PRF = -8 dBm
3.8
mA
ITX,MINUS8dBM
TX only run current PRF = -8 dBm
8.4
mA
ITX,MINUS12dBM,DCDC
TX only run current DCDC, 3V PRF = -12 dBm
3.5
mA
ITX,MINUS12dBM
TX only run current PRF = -12 dBm
7.7
mA
ITX,MINUS16dBM,DCDC
TX only run current DCDC, 3V PRF = -16 dBm
3.3
mA
ITX,MINUS16dBM
TX only run current PRF = -16 dBm
7.3
mA
ITX,MINUS20dBM,DCDC
TX only run current DCDC, 3V PRF = -20 dBm
3.2
mA
ITX,MINUS20dBM
TX only run current PRF = -20 dBm
7.0
mA
ITX,MINUS40dBM,DCDC
TX only run current DCDC, 3V PRF = -40 dBm
2.7
mA
Page 229
Typ.
23 RADIO — 2.4 GHz Radio
Symbol
Description
ITX,MINUS40dBM
TX only run current PRF = -40 dBm
Min.
Typ.
5.9
Max.
Units
mA
ISTART,TX,DCDC
TX start-up current DCDC, 3V, PRF = 4 dBm
4.0
mA
ISTART,TX
TX start-up current, PRF = 4 dBm
8.8
mA
23.15.3 Radio current consumption (Receiver)
Symbol
Description
IRX,1M,DCDC
RX only run current (DCDC, 3V) 1Msps / 1Msps BLE
Min.
Typ.
5.4
Max.
Units
mA
IRX,1M
RX only run current 1Msps / 1Msps BLE
11.7
mA
IRX,2M,DCDC
RX only run current (DCDC, 3V) 2Msps
5.8
mA
IRX,2M
RX only run current 2Msps
12.9
mA
ISTART,RX,1M,DCDC
RX start-up current (DCDC 3V) 1Msps / 1Msps BLE
3.5
mA
ISTART,RX,1M
RX start-up current 1Msps / 1Msps BLE
7.5
mA
23.15.4 Transmitter specification
Symbol
Description
Typ.
Max.
Units
PRF
Maximum output power
Min.
4
6
dBm
PRFC
RF power control range
24
PRFCR
RF power accuracy
PRF1,1
1st Adjacent Channel Transmit Power 1 MHz (1 Msps)
-25
dBc
PRF2,1
2nd Adjacent Channel Transmit Power 2 MHz (1 Msps)
-50
dBc
PRF1,2
1st Adjacent Channel Transmit Power 2 MHz (2 Msps)
-25
dBc
PRF2,2
2nd Adjacent Channel Transmit Power 4 MHz (2 Msps)
-50
dBc
dB
±4
dB
23.15.5 Receiver operation
Symbol
Description
PRX,MAX
Maximum received signal strength at < 0.1% PER
Min.
Typ.
0
Max.
Units
dBm
PSENS,IT,1M
Sensitivity, 1Msps nRF mode16
-93
dBm
PSENS,IT,SP,1M,BLE
Sensitivity, 1Msps BLE ideal transmitter, <=37 bytes BER=1E-317
-96
dBm
PSENS,IT,LP,1M,BLE
Sensitivity, 1Msps BLE ideal transmitter >=128 bytes BER=1E-4
-95
dBm
-89
dBm
18
PSENS,IT,2M
Sensitivity, 2Msps nRF mode19
23.15.6 RX selectivity
20
RX selectivity with equal modulation on interfering signal
Symbol
Description
C/I1M,co-channel
1Msps mode, Co-Channel interference
9
dB
C/I1M,-1MHz
1 Msps mode, Adjacent (-1 MHz) interference
-2
dB
C/I1M,+1MHz
1 Msps mode, Adjacent (+1 MHz) interference
-10
dB
C/I1M,-2MHz
1 Msps mode, Adjacent (-2 MHz) interference
-19
dB
C/I1M,+2MHz
1 Msps mode, Adjacent (+2 MHz) interference
-42
dB
C/I1M,-3MHz
1 Msps mode, Adjacent (-3 MHz) interference
-38
dB
C/I1M,+3MHz
1 Msps mode, Adjacent (+3 MHz) interference
-48
dB
C/I1M,±6MHz
1 Msps mode, Adjacent (≥6 MHz) interference
-50
dB
C/I1MBLE,co-channel
1 Msps BLE mode, Co-Channel interference
6
dB
16
17
18
19
20
Min.
Typ.
Max.
Units
Typical sensitivity applies when ADDR0 is used for receiver address correlation. When ADDR[1...7] are used for
receiver address correlation, the typical sensitivity for this mode is degraded by 3dB.
As defined in the Bluetooth Core Specification v4.0 Volume 6: Core System Package (Low Energy Controller
Volume)
Equivalent BER limit < 10E-04
Typical sensitivity applies when ADDR0 is used for receiver address correlation. When ADDR[1...7] are used for
receiver address correlation, the typical sensitivity for this mode is degraded by 3dB.
Wanted signal level at PIN = -67 dBm. One interferer is used, having equal modulation as the wanted
signal. The input power of the interferer where the sensitivity equals BER = 0.1% is presented
Page 230
23 RADIO — 2.4 GHz Radio
Symbol
Description
C/I1MBLE,-1MHz
1 Msps BLE mode, Adjacent (-1 MHz) interference
Min.
Typ.
-2
Max.
Units
dB
C/I1MBLE,+1MHz
1 Msps BLE mode, Adjacent (+1 MHz) interference
-9
dB
C/I1MBLE,-2MHz
1 Msps BLE mode, Adjacent (-2 MHz) interference
-22
dB
C/I1MBLE,+2MHz
1 Msps BLE mode, Adjacent (+2 MHz) interference
-46
dB
C/I1MBLE,>3MHz
1 Msps BLE mode, Adjacent (≥3 MHz) interference
-50
dB
C/I1MBLE,image
Image frequency Interference
-22
dB
C/I1MBLE,image,1MHz
Adjacent (1 MHz) interference to in-band image frequency
-35
dB
C/I2M,co-channel
2Msps mode, Co-Channel interference
10
dB
C/I2M,-2MHz
2 Msps mode, Adjacent (-2 MHz) interference
6
dB
C/I2M,+2MHz
2 Msps mode, Adjacent (+2 MHz) interference
-14
dB
C/I2M,-4MHz
2 Msps mode, Adjacent (-4 MHz) interference
-20
dB
C/I2M,+4MHz
2 Msps mode, Adjacent (+4 MHz) interference
-44
dB
C/I2M,-6MHz
2 Msps mode, Adjacent (-6 MHz) interference
-42
dB
C/I2M,+6MHz
2 Msps mode, Adjacent (+6 MHz) interference
-47
dB
C/I2M,≥12MHz
2 Msps mode, Adjacent (≥12 MHz) interference
-52
dB
23.15.7 RX intermodulation
21
RX intermodulation
Symbol
Description
PIMD,1M
IMD performance, 1 Msps, 3rd, 4th, and 5th offset channel
Min.
Typ.
-33
Max.
Units
dBm
PIMD,1M,BLE
IMD performance, BLE 1 Msps, 3rd, 4th, and 5th offset channel
-30
dBm
PIMD,2M
IMD performance, 2 Msps, 3rd, 4th, and 5th offset channel
-33
dBm
23.15.8 Radio timing
Symbol
Description
tTXEN
Time between TXEN task and READY event after channel
Min.
Typ.
Max.
Units
140
us
40
us
6
us
4
us
140
us
40
us
20
us
0
us
FREQUENCY configured
tTXEN,FAST
Time between TXEN task and READY event after channel
FREQUENCY configured (Fast Mode)
tTXDISABLE
Time between DISABLE task and DISABLED event when the
radio was in TX and mode is set to 1Msps
tTXDISABLE,2M
Time between DISABLE task and DISABLED event when the
radio was in TX and mode is set to 2Msps
tRXEN
Time between the RXEN task and READY event after channel
FREQUENCY configured in default mode
tRXEN,FAST
Time between the RXEN task and READY event after channel
FREQUENCY configured in fast mode
tSWITCH
The minimum time taken to switch from RX to TX or TX to RX
(channel FREQUENCY unchanged)
tRXDISABLE
Time between DISABLE task and DISABLED event when the
radio was in RX
tTXCHAIN
TX chain delay
0.6
us
tRXCHAIN
RX chain delay
9.4
us
tRXCHAIN,2M
RX chain delay in 2Msps mode
5
us
23.15.9 Received Signal Strength Indicator (RSSI) specifications
Symbol
Description
RSSIACC
RSSI Accuracy Valid range -90 to -20 dBm
±2
dB
RSSIRESOLUTION
RSSI resolution
1
dB
RSSIPERIOD
Sample period
8
us
21
Min.
Typ.
Max.
Units
Wanted signal level at PIN = -64 dBm. Two interferers with equal input power are used. The interferer
closest in frequency is not modulated, the other interferer is modulated equal with the wanted signal.
The input power of the interferers where the sensitivity equals BER = 0.1% is presented.
Page 231
23 RADIO — 2.4 GHz Radio
23.15.10 Jitter
Symbol
Description
tDISABLEDJITTER
Jitter on DISABLED event relative to END event when shortcut
Min.
Typ.
Max.
Units
0.25
us
0.25
us
between END and DISABLE is enabled.
tREADYJITTER
Jitter on READY event relative to TXEN and RXEN task.
23.15.11 Delay when disabling the RADIO
Symbol
Description
tTXDISABLE,1M
Disable delay from TX.
Min.
Typ.
Max.
Units
6
us
0
us
Delay between DISABLE and DISABLED for MODE = Nrf_1Mbit
and MODE = Ble_1Mbit
tRXDISABLE,1M
Disable delay from RX.
Delay between DISABLE and DISABLED for MODE = Nrf_1Mbit
and MODE = Ble_1Mbit
Page 232
24 TIMER — Timer/counter
24 TIMER — Timer/counter
The TIMER can operate in two modes: timer and counter.
CLEAR
CAPTURE[0..n]
STOP
START
COUNT
TIMER
TIMER Core
Increment
BITMODE
Counter
PCLK1M
Prescaler
PCLK16M
fTIMER
PRESCALER
CC[0..n]
MODE
COMPARE[0..n]
Figure 42: Block schematic for timer/counter
The timer/counter runs on the high-frequency clock source (HFCLK) and includes a four-bit (1/2X) prescaler
that can divide the timer input clock from the HFCLK controller. Clock source selection between PCLK16M
and PCLK1M is automatic according to TIMER base frequency set by the prescaler. The TIMER base
frequency is always given as 16 MHz divided by the prescaler value.
The PPI system allows a TIMER event to trigger a task of any other system peripheral of the device. The
PPI system also enables the TIMER task/event features to generate periodic output and PWM signals to any
GPIO. The number of input/outputs used at the same time is limited by the number of GPIOTE channels.
The TIMER can operate in two modes, Timer mode and Counter mode. In both modes, the TIMER is started
by triggering the START task, and stopped by triggering the STOP task. After the timer is stopped the timer
can resume timing/counting by triggering the START task again. When timing/counting is resumed, the timer
will continue from the value it had prior to being stopped.
In Timer mode, the TIMER's internal Counter register is incremented by one for every tick of the timer
frequency fTIMER as illustrated in Figure 42: Block schematic for timer/counter on page 233. The timer
frequency is derived from PCLK16M as shown below, using the values specified in the PRESCALER
register:
fTIMER = 16 MHz / (2PRESCALER)
When fTIMER <= 1 MHz the TIMER will use PCLK1M instead of PCLK16M for reduced power consumption.
In counter mode, the TIMER's internal Counter register is incremented by one each time the COUNT task
is triggered, that is, the timer frequency and the prescaler are not utilized in counter mode. Similarly, the
COUNT task has no effect in Timer mode.
The TIMER's maximum value is configured by changing the bit-width of the timer in the BITMODE on page
238 register.
PRESCALER on page 238 and the BITMODE on page 238 must only be updated when the timer
is stopped. If these registers are updated while the TIMER is started then this may result in unpredictable
behavior.
Page 233
24 TIMER — Timer/counter
When the timer is incremented beyond its maximum value the Counter register will overflow and the TIMER
will automatically start over from zero.
The Counter register can be cleared, that is, its internal value set to zero explicitly, by triggering the CLEAR
task.
The TIMER implements multiple capture/compare registers.
Independent of prescaler setting the accuracy of the TIMER is equivalent to one tick of the timer frequency
fTIMER as illustrated in Figure 42: Block schematic for timer/counter on page 233.
24.1 Capture
The TIMER implements one capture task for every available capture/compare register.
Every time the CAPTURE[n] task is triggered, the Counter value is copied to the CC[n] register.
24.2 Compare
The TIMER implements one COMPARE event for every available capture/compare register.
A COMPARE event is generated when the Counter is incremented and then becomes equal to the value
specified in one of the capture compare registers. When the Counter value becomes equal to the value
specified in a capture compare register CC[n], the corresponding compare event COMPARE[n] is generated.
BITMODE on page 238 specifies how many bits of the Counter register and the capture/compare register
that are used when the comparison is performed. Other bits will be ignored.
24.3 Task delays
After the TIMER is started, the CLEAR task, COUNT task and the STOP task will guarantee to take effect
within one clock cycle of the PCLK16M.
24.4 Task priority
If the START task and the STOP task are triggered at the same time, that is, within the same period of
PCLK16M, the STOP task will be prioritized.
24.5 Registers
Table 42: Instances
Base address
Peripheral
Instance
Description
Configuration
0x40008000
TIMER
TIMER0
Timer 0
This timer instance has 4 CC registers
0x40009000
TIMER
TIMER1
Timer 1
0x4000A000
TIMER
TIMER2
Timer 2
0x4001A000
TIMER
TIMER3
Timer 3
0x4001B000
TIMER
TIMER4
Timer 4
(CC[0..3])
This timer instance has 4 CC registers
(CC[0..3])
This timer instance has 4 CC registers
(CC[0..3])
This timer instance has 6 CC registers
(CC[0..5])
This timer instance has 6 CC registers
(CC[0..5])
Table 43: Register Overview
Register
Offset
Description
TASKS_START
0x000
Start Timer
Page 234
24 TIMER — Timer/counter
Register
Offset
Description
TASKS_STOP
0x004
Stop Timer
TASKS_COUNT
0x008
Increment Timer (Counter mode only)
TASKS_CLEAR
0x00C
Clear time
TASKS_SHUTDOWN
0x010
Shut down timer
TASKS_CAPTURE[0]
0x040
Capture Timer value to CC[0] register
TASKS_CAPTURE[1]
0x044
Capture Timer value to CC[1] register
TASKS_CAPTURE[2]
0x048
Capture Timer value to CC[2] register
TASKS_CAPTURE[3]
0x04C
Capture Timer value to CC[3] register
TASKS_CAPTURE[4]
0x050
Capture Timer value to CC[4] register
TASKS_CAPTURE[5]
0x054
Capture Timer value to CC[5] register
EVENTS_COMPARE[0]
0x140
Compare event on CC[0] match
EVENTS_COMPARE[1]
0x144
Compare event on CC[1] match
EVENTS_COMPARE[2]
0x148
Compare event on CC[2] match
EVENTS_COMPARE[3]
0x14C
Compare event on CC[3] match
EVENTS_COMPARE[4]
0x150
Compare event on CC[4] match
EVENTS_COMPARE[5]
0x154
Compare event on CC[5] match
SHORTS
0x200
Shortcut register
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
MODE
0x504
Timer mode selection
BITMODE
0x508
Configure the number of bits used by the TIMER
PRESCALER
0x510
Timer prescaler register
CC[0]
0x540
Capture/Compare register 0
CC[1]
0x544
Capture/Compare register 1
CC[2]
0x548
Capture/Compare register 2
CC[3]
0x54C
Capture/Compare register 3
CC[4]
0x550
Capture/Compare register 4
CC[5]
0x554
Capture/Compare register 5
Deprecated
24.5.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW COMPARE0_CLEAR
0
Value Id
I H G
Value
Description
Shortcut between COMPARE[0] event and CLEAR task
See EVENTS_COMPARE[0] and TASKS_CLEAR
B
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW COMPARE1_CLEAR
Shortcut between COMPARE[1] event and CLEAR task
See EVENTS_COMPARE[1] and TASKS_CLEAR
C
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW COMPARE2_CLEAR
Shortcut between COMPARE[2] event and CLEAR task
See EVENTS_COMPARE[2] and TASKS_CLEAR
D
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW COMPARE3_CLEAR
Shortcut between COMPARE[3] event and CLEAR task
See EVENTS_COMPARE[3] and TASKS_CLEAR
E
F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW COMPARE4_CLEAR
Shortcut between COMPARE[4] event and CLEAR task
See EVENTS_COMPARE[4] and TASKS_CLEAR
Page 235
24 TIMER — Timer/counter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
F
RW Field
0
I H G
F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW COMPARE5_CLEAR
Shortcut between COMPARE[5] event and CLEAR task
See EVENTS_COMPARE[5] and TASKS_CLEAR
G
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW COMPARE0_STOP
Shortcut between COMPARE[0] event and STOP task
See EVENTS_COMPARE[0] and TASKS_STOP
H
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW COMPARE1_STOP
Shortcut between COMPARE[1] event and STOP task
See EVENTS_COMPARE[1] and TASKS_STOP
I
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW COMPARE2_STOP
Shortcut between COMPARE[2] event and STOP task
See EVENTS_COMPARE[2] and TASKS_STOP
J
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW COMPARE3_STOP
Shortcut between COMPARE[3] event and STOP task
See EVENTS_COMPARE[3] and TASKS_STOP
K
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW COMPARE4_STOP
Shortcut between COMPARE[4] event and STOP task
See EVENTS_COMPARE[4] and TASKS_STOP
L
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW COMPARE5_STOP
Shortcut between COMPARE[5] event and STOP task
See EVENTS_COMPARE[5] and TASKS_STOP
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
24.5.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F E D C B A
Reset 0x00000000
Id
RW Field
A
RW COMPARE0
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for COMPARE[0] event
See EVENTS_COMPARE[0]
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE1
Write '1' to Enable interrupt for COMPARE[1] event
See EVENTS_COMPARE[1]
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE2
Write '1' to Enable interrupt for COMPARE[2] event
Page 236
24 TIMER — Timer/counter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F E D C B A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_COMPARE[2]
D
RW COMPARE3
Write '1' to Enable interrupt for COMPARE[3] event
See EVENTS_COMPARE[3]
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE4
Write '1' to Enable interrupt for COMPARE[4] event
See EVENTS_COMPARE[4]
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE5
Write '1' to Enable interrupt for COMPARE[5] event
See EVENTS_COMPARE[5]
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
24.5.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F E D C B A
Reset 0x00000000
Id
RW Field
A
RW COMPARE0
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for COMPARE[0] event
See EVENTS_COMPARE[0]
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE1
Write '1' to Disable interrupt for COMPARE[1] event
See EVENTS_COMPARE[1]
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE2
Write '1' to Disable interrupt for COMPARE[2] event
See EVENTS_COMPARE[2]
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE3
Write '1' to Disable interrupt for COMPARE[3] event
See EVENTS_COMPARE[3]
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE4
Write '1' to Disable interrupt for COMPARE[4] event
See EVENTS_COMPARE[4]
Clear
1
Disable
Page 237
24 TIMER — Timer/counter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F E D C B A
Reset 0x00000000
Id
F
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE5
Write '1' to Disable interrupt for COMPARE[5] event
See EVENTS_COMPARE[5]
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
24.5.4 MODE
Address offset: 0x504
Timer mode selection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000000
Id
RW Field
A
RW MODE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Timer
0
Select Timer mode
Counter
1
Select Counter mode
LowPowerCounter
2
Select Low Power Counter mode
Timer mode
Deprecated
24.5.5 BITMODE
Address offset: 0x508
Configure the number of bits used by the TIMER
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000000
Id
RW Field
A
RW BITMODE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
16Bit
0
16 bit timer bit width
08Bit
1
8 bit timer bit width
24Bit
2
24 bit timer bit width
32Bit
3
32 bit timer bit width
Timer bit width
24.5.6 PRESCALER
Address offset: 0x510
Timer prescaler register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000004
Id
RW Field
A
RW PRESCALER
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Value
Description
[0..9]
Prescaler value
24.5.7 CC[0]
Address offset: 0x540
Capture/Compare register 0
Page 238
24 TIMER — Timer/counter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Capture/Compare value
Only the number of bits indicated by BITMODE will be used by
the TIMER.
24.5.8 CC[1]
Address offset: 0x544
Capture/Compare register 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Capture/Compare value
Only the number of bits indicated by BITMODE will be used by
the TIMER.
24.5.9 CC[2]
Address offset: 0x548
Capture/Compare register 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Capture/Compare value
Only the number of bits indicated by BITMODE will be used by
the TIMER.
24.5.10 CC[3]
Address offset: 0x54C
Capture/Compare register 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Capture/Compare value
Only the number of bits indicated by BITMODE will be used by
the TIMER.
24.5.11 CC[4]
Address offset: 0x550
Capture/Compare register 4
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Capture/Compare value
Page 239
24 TIMER — Timer/counter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
0
RW Field
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Only the number of bits indicated by BITMODE will be used by
the TIMER.
24.5.12 CC[5]
Address offset: 0x554
Capture/Compare register 5
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Capture/Compare value
Only the number of bits indicated by BITMODE will be used by
the TIMER.
24.6 Electrical specification
24.6.1 Timers Electrical Specification
Symbol
Description
Min.
Typ.
Max.
Units
ITIMER_1M
Run current with 1 MHz clock input (PCLK1M)
3
5
8
µA
ITIMER_16M
Run current with 16 MHz clock input (PCLK16M)
50
70
120
µA
tTIMER,START
Time from START task is given until timer starts counting
Page 240
0.25
µs
25 RTC — Real-time counter
25 RTC — Real-time counter
The Real-time counter (RTC) module provides a generic, low power timer on the low-frequency clock source
(LFCLK).
32.768 kHz
START
STOP
CLEAR
TRIGOVRFLW
task
PRESCALER
event
TICK
event
OVRFLW
event
COMPARE[0..N]
COUNTER
task
RTC
task
task
CC[0:3]
Figure 43: RTC block schematic
The RTC module features a 24-bit COUNTER, a 12-bit (1/X) prescaler, capture/compare registers, and a tick
event generator for low power, tickless RTOS implementation.
25.1 Clock source
The RTC will run off the LFCLK.
The COUNTER resolution will therefore be 30.517 µs. Depending on the source, the RTC is able to run while
the HFCLK is OFF and PCLK16M is not available.
The software has to explicitely start LFCLK before using the RTC.
See CLOCK — Clock control on page 101 for more information about clock sources.
25.2 Resolution versus overflow and the PRESCALER
Counter increment frequency:
fRTC [kHz] = 32.768 / (PRESCALER + 1 )
The PRESCALER register is read/write when the RTC is stopped. The PRESCALER register is read-only
once the RTC is STARTed. Writing to the PRESCALER register when the RTC is started has no effect.
The PRESCALER is restarted on START, CLEAR and TRIGOVRFLW, that is, the prescaler value is latched
to an internal register (<<PRESC>>) on these tasks.
Examples:
1. Desired COUNTER frequency 100 Hz (10 ms counter period)
PRESCALER = round(32.768 kHz / 100 Hz) - 1 = 327
fRTC = 99.9 Hz
Page 241
25 RTC — Real-time counter
10009.576 µs counter period
2. Desired COUNTER frequency 8 Hz (125 ms counter period)
PRESCALER = round(32.768 kHz / 8 Hz) – 1 = 4095
fRTC = 8 Hz
125 ms counter period
Table 44: RTC resolution versus overflow
Prescaler
0
28-1
212-1
Counter resolution
30.517 μs
7812.5 μs
125 ms
Overflow
512 seconds
131072 seconds
582.542 hours
25.3 COUNTER register
The COUNTER increments on LFCLK when the internal PRESCALER register (<<PRESC>>) is 0x00.
<<PRESC>> is reloaded from the PRESCALER register. If enabled, the TICK event occurs on each
increment of the COUNTER. The TICK event is disabled by default.
SysClk
LFClk
TICK
PRESC
<<PRESC>>
COUNTER
0x000
0x000
0x000
0x000
0x000
0x000000
0x000001
0x000002
0x000003
0x000
0x001
Figure 44: Timing diagram - COUNTER_PRESCALER_0
SysClk
LFClk
TICK
PRESC
<<PRESC>>
COUNTER
0x001
0x000
0x001
0x000000
0x000001
Figure 45: Timing diagram - COUNTER_PRESCALER_1
25.4 Overflow features
The TRIGOVRFLW task sets the COUNTER value to 0xFFFFF0 to allow SW test of the overflow condition.
OVRFLW occurs when COUNTER overflows from 0xFFFFFF to 0.
Important: The OVRFLW event is disabled by default.
25.5 TICK event
The TICK event enables low power "tick-less" RTOS implementation as it optionally provides a regular
interrupt source for a RTOS without the need to use the ARM® SysTick feature.
Page 242
25 RTC — Real-time counter
Using the RTC TICK event rather than the SysTick allows the CPU to be powered down while still keeping
RTOS scheduling active.
Important: The TICK event is disabled by default.
25.6 Event control feature
To optimize RTC power consumption, events in the RTC can be individually disabled to prevent PCLK16M
and HFCLK being requested when those events are triggered. This is managed using the EVTEN register.
For example, if the TICK event is not required for an application, this event should be disabled as it is
frequently occurring and may increase power consumption if HFCLK otherwise could be powered down for
long durations.
This means that the RTC implements a slightly different task and event system compared to the standard
system described in Peripheral interface on page 68. The RTC task and event system is illustrated in Figure
46: Tasks, events and interrupts in the RTC on page 243.
Task signal from PPI
RTC
write
TASK
OR
task
RTC
core
event
EVTEN
m
INTEN
m
EVENT m
IRQ signal to NVIC
Event signal to PPI
Figure 46: Tasks, events and interrupts in the RTC
25.7 Compare feature
There are a number of Compare registers.
For more information, see Registers on page 247.
When setting a compare register, the following behavior of the RTC compare event should be noted:
•
If a CC register value is 0 when a CLEAR task is set, this will not trigger a COMPARE event.
Page 243
25 RTC — Real-time counter
SysClk
LFClk
PRESC
0x000
COUNTER
X
0x000000
CLEAR
CC[0]
0x000000
COMPARE[0]
•
0
Figure 47: Timing diagram - COMPARE_CLEAR
If a CC register is N and the COUNTER value is N when the START task is set, this will not trigger a
COMPARE event.
SysClk
LFClk
PRESC
0x000
COUNTER
N-1
N
N+1
START
•
CC[0]
N
COMPARE[0]
0
Figure 48: Timing diagram - COMPARE_START
COMPARE occurs when a CC register is N and the COUNTER value transitions from N-1 to N.
SysClk
LFClk
PRESC
COUNTER
0x000
N-2
N-1
CC[0]
COMPARE[0]
•
N
N+1
N
0
1
Figure 49: Timing diagram - COMPARE
If the COUNTER is N, writing N+2 to a CC register is guaranteed to trigger a COMPARE event at N+2.
Page 244
25 RTC — Real-time counter
SysClk
LFClk
PRESC
COUNTER
0x000
N-1
N
N+1
N+2
> 62.5 ns
CC[0]
X
N+2
COMPARE[0]
•
0
1
Figure 50: Timing diagram - COMPARE_N+2
If the COUNTER is N, writing N or N+1 to a CC register may not trigger a COMPARE event.
SysClk
LFClk
PRESC
COUNTER
0x000
N-2
N-1
N+1
>= 0
CC[0]
X
N+1
COMPARE[0]
•
N
0
Figure 51: Timing diagram - COMPARE_N+1
If the COUNTER is N and the current CC register value is N+1 or N+2 when a new CC value is written,
a match may trigger on the previous CC value before the new value takes effect. If the current CC value
greater than N+2 when the new value is written, there will be no event due to the old value.
SysClk
LFClk
PRESC
COUNTER
CC[0]
0x000
N-2
N-1
N
N+1
>= 0
N
COMPARE[0]
X
0
1
Figure 52: Timing diagram - COMPARE_N-1
25.8 TASK and EVENT jitter/delay
Jitter or delay in the RTC is due to the peripheral clock being a low frequency clock (LFCLK) which is not
synchronous to the faster PCLK16M.
Registers in the peripheral interface, part of the PCLK16M domain, have a set of mirrored registers in the
LFCLK domain. For example, the COUNTER value accessible from the CPU is in the PCLK16M domain
and is latched on read from an internal register called COUNTER in the LFCLK domain. COUNTER is the
register which is actually modified each time the RTC ticks. These registers must be synchronised between
clock domains (PCLK16M and LFCLK).
The following is a summary of the jitter introduced on tasks and events. Figures illustrating jitter follow.
Page 245
25 RTC — Real-time counter
Table 45: RTC jitter magnitudes on tasks
Task
CLEAR, STOP, START, TRIGOVRFLOW
Delay
+15 to 46 μs
Table 46: RTC jitter magnitudes on events
Operation/Function
START to COUNTER increment
COMPARE to COMPARE 22
Jitter
+/- 15 μs
+/- 62.5 ns
1. CLEAR and STOP (and TRIGOVRFLW; not shown) will be delayed as long as it takes for the peripheral
to clock a falling edge and rising of the LFCLK. This is between 15.2585 µs and 45.7755 µs – rounded to
15 µs and 46 µs for the remainder of the section.
SysClk
CLEAR
LFClk
PRESC
COUNTER
CLEARa
0x000
X
X+1
0x000000
0x000001
0 or more SysClk after
<= ~46 us
>= ~15 us
1 or more SysClk before
CLEARb
Figure 53: Timing diagram - DELAY_CLEAR
SysClk
STOP
LFClk
PRESC
COUNTER
STOPa
STOPb
0x000
X
X+1
0 or more SysClk after
<= ~46 us
>= ~15 us
1 or more SysClk before
Figure 54: Timing diagram - DELAY_STOP
2. The START task will start the RTC. Assuming that the LFCLK was previously running and stable, the
first increment of COUNTER (and instance of TICK event) will be typically after 30.5 µs +/-15 µs. In
some cases, in particular if the RTC is STARTed before the LFCLK is running, that timing can be up to
~250 µs. The software should therefore wait for the first TICK if it has to make sure the RTC is running.
Sending a TRIGOVRFLW task sets the COUNTER to a value close to overflow. However, since the
update of COUNTER relies on a stable LFCLK, sending this task while LFCLK is not running will start
LFCLK, but the update will then be delayed by the same amount of time of up to ~250 us. The figures
show the smallest and largest delays to on the START task which appears as a +/-15 µs jitter on the first
COUNTER increment.
22
Assumes RTC runs continuously between these events.
Note: 32.768 kHz clock jitter is additional to the numbers provided above.
Page 246
25 RTC — Real-time counter
SysClk
First tick
LFClk
PRESC
COUNTER
START
0x000
X
X+1
X+2
X+3
>= ~15 us
0 or more SysClk before
Figure 55: Timing diagram - JITTER_STARTSysClk
First tick
LFClk
PRESC
COUNTER
0x000
X
X+1
X+2
<= ~250 us
START
Figure 56: Timing diagram - JITTER_START+
25.9 Reading the COUNTER register
To read the COUNTER register, the internal <<COUNTER>> value is sampled.
To ensure that the <<COUNTER>> is safely sampled (considering an LFCLK transition may occur during
a read), the CPU and core memory bus are halted for three cycles by lowering the core PREADY signal.
The Read takes the CPU 2 cycles in addition resulting in the COUNTER register read taking a fixed five
PCLK16M clock cycles.
SysClk
PREADY
LFClk
<<COUNTER>>
N-1
COUNTER
N
X
N
375.2 ns
COUNTER_READ
Figure 57: Timing diagram - COUNTER_READ
25.10 Registers
Table 47: Instances
Base address
Peripheral
Instance
Description
Configuration
0x4000B000
RTC
RTC0
Real-time counter 0
CC[0..2] implemented, CC[3] not
0x40011000
RTC
RTC1
Real-time counter 1
implemented
Page 247
CC[0..3] implemented
25 RTC — Real-time counter
Base address
Peripheral
Instance
Description
Configuration
0x40024000
RTC
RTC2
Real-time counter 2
CC[0..3] implemented
Table 48: Register Overview
Register
Offset
Description
TASKS_START
0x000
Start RTC COUNTER
TASKS_STOP
0x004
Stop RTC COUNTER
TASKS_CLEAR
0x008
Clear RTC COUNTER
TASKS_TRIGOVRFLW
0x00C
Set COUNTER to 0xFFFFF0
EVENTS_TICK
0x100
Event on COUNTER increment
EVENTS_OVRFLW
0x104
Event on COUNTER overflow
EVENTS_COMPARE[0]
0x140
Compare event on CC[0] match
EVENTS_COMPARE[1]
0x144
Compare event on CC[1] match
EVENTS_COMPARE[2]
0x148
Compare event on CC[2] match
EVENTS_COMPARE[3]
0x14C
Compare event on CC[3] match
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
EVTEN
0x340
Enable or disable event routing
EVTENSET
0x344
Enable event routing
EVTENCLR
0x348
Disable event routing
COUNTER
0x504
Current COUNTER value
PRESCALER
0x508
12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is
CC[0]
0x540
Compare register 0
CC[1]
0x544
Compare register 1
CC[2]
0x548
Compare register 2
CC[3]
0x54C
Compare register 3
stopped
25.10.1 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F E D C
Reset 0x00000000
Id
RW Field
A
RW TICK
0
Value Id
Value
Description
Write '1' to Enable interrupt for TICK event
See EVENTS_TICK
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW OVRFLW
Write '1' to Enable interrupt for OVRFLW event
See EVENTS_OVRFLW
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE0
Write '1' to Enable interrupt for COMPARE[0] event
See EVENTS_COMPARE[0]
D
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE1
Write '1' to Enable interrupt for COMPARE[1] event
See EVENTS_COMPARE[1]
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Page 248
25 RTC — Real-time counter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F E D C
Reset 0x00000000
Id
RW Field
E
RW COMPARE2
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for COMPARE[2] event
See EVENTS_COMPARE[2]
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE3
Write '1' to Enable interrupt for COMPARE[3] event
See EVENTS_COMPARE[3]
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
25.10.2 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F E D C
Reset 0x00000000
Id
RW Field
A
RW TICK
0
Value Id
Value
Description
Write '1' to Disable interrupt for TICK event
See EVENTS_TICK
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW OVRFLW
Write '1' to Disable interrupt for OVRFLW event
See EVENTS_OVRFLW
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE0
Write '1' to Disable interrupt for COMPARE[0] event
See EVENTS_COMPARE[0]
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE1
Write '1' to Disable interrupt for COMPARE[1] event
See EVENTS_COMPARE[1]
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE2
Write '1' to Disable interrupt for COMPARE[2] event
See EVENTS_COMPARE[2]
F
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE3
Write '1' to Disable interrupt for COMPARE[3] event
See EVENTS_COMPARE[3]
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Page 249
25 RTC — Real-time counter
25.10.3 EVTEN
Address offset: 0x340
Enable or disable event routing
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F E D C
Reset 0x00000000
Id
RW Field
A
RW TICK
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable event routing for TICK event
See EVENTS_TICK
B
Disabled
0
Disable
Enabled
1
Enable
RW OVRFLW
Enable or disable event routing for OVRFLW event
See EVENTS_OVRFLW
C
Disabled
0
Disable
Enabled
1
Enable
RW COMPARE0
Enable or disable event routing for COMPARE[0] event
See EVENTS_COMPARE[0]
D
Disabled
0
Disable
Enabled
1
Enable
RW COMPARE1
Enable or disable event routing for COMPARE[1] event
See EVENTS_COMPARE[1]
E
Disabled
0
Disable
Enabled
1
Enable
RW COMPARE2
Enable or disable event routing for COMPARE[2] event
See EVENTS_COMPARE[2]
F
Disabled
0
Disable
Enabled
1
Enable
RW COMPARE3
Enable or disable event routing for COMPARE[3] event
See EVENTS_COMPARE[3]
Disabled
0
Disable
Enabled
1
Enable
25.10.4 EVTENSET
Address offset: 0x344
Enable event routing
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F E D C
Reset 0x00000000
Id
RW Field
A
RW TICK
0
Value Id
Value
Description
Write '1' to Enable event routing for TICK event
See EVENTS_TICK
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW OVRFLW
Write '1' to Enable event routing for OVRFLW event
See EVENTS_OVRFLW
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE0
Write '1' to Enable event routing for COMPARE[0] event
See EVENTS_COMPARE[0]
Set
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Enable
Page 250
25 RTC — Real-time counter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F E D C
Reset 0x00000000
Id
D
RW Field
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE1
Write '1' to Enable event routing for COMPARE[1] event
See EVENTS_COMPARE[1]
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE2
Write '1' to Enable event routing for COMPARE[2] event
See EVENTS_COMPARE[2]
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE3
Write '1' to Enable event routing for COMPARE[3] event
See EVENTS_COMPARE[3]
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
25.10.5 EVTENCLR
Address offset: 0x348
Disable event routing
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F E D C
Reset 0x00000000
Id
RW Field
A
RW TICK
0
Value Id
Value
Description
Write '1' to Disable event routing for TICK event
See EVENTS_TICK
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW OVRFLW
Write '1' to Disable event routing for OVRFLW event
See EVENTS_OVRFLW
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE0
Write '1' to Disable event routing for COMPARE[0] event
See EVENTS_COMPARE[0]
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE1
Write '1' to Disable event routing for COMPARE[1] event
See EVENTS_COMPARE[1]
E
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COMPARE2
Write '1' to Disable event routing for COMPARE[2] event
See EVENTS_COMPARE[2]
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Page 251
25 RTC — Real-time counter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F E D C
Reset 0x00000000
Id
RW Field
F
RW COMPARE3
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable event routing for COMPARE[3] event
See EVENTS_COMPARE[3]
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
25.10.6 COUNTER
Address offset: 0x504
Current COUNTER value
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
COUNTER
Counter value
25.10.7 PRESCALER
Address offset: 0x508
12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PRESCALER
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Prescaler value
25.10.8 CC[0]
Address offset: 0x540
Compare register 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW COMPARE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Compare value
25.10.9 CC[1]
Address offset: 0x544
Compare register 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW COMPARE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Compare value
25.10.10 CC[2]
Address offset: 0x548
Compare register 2
Page 252
25 RTC — Real-time counter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW COMPARE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Compare value
25.10.11 CC[3]
Address offset: 0x54C
Compare register 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW COMPARE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Compare value
25.11 Electrical specification
25.11.1 RTC Electrical Specification
Symbol
Description
IRTC
Run current Real Time Counter (LFCLK source)
Min.
Typ.
0.1
Page 253
Max.
Units
µA
26 RNG — Random number generator
26 RNG — Random number generator
The Random number generator (RNG) generates true non-deterministic random numbers based on internal
thermal noise that are suitable for cryptographic purposes. The RNG does not require a seed value.
START
Random number
generator
STOP
VALRDY
VALUE
Figure 58: Random number generator
The RNG is started by triggering the START task and stopped by triggering the STOP task. When started,
new random numbers are generated continuously and written to the VALUE register when ready. A VALRDY
event is generated for every new random number that is written to the VALUE register. This means that after
a VALRDY event is generated the CPU has the time until the next VALRDY event to read out the random
number from the VALUE register before it is overwritten by a new random number.
26.1 Bias correction
A bias correction algorithm is employed on the internal bit stream to remove any bias toward '1' or '0'. The
bits are then queued into an eight-bit register for parallel readout from the VALUE register.
It is possible to enable bias correction in the CONFIG register. This will result in slower value generation, but
will ensure a statistically uniform distribution of the random values.
26.2 Speed
The time needed to generate one random byte of data is unpredictable, and may vary from one byte to the
next. This is especially true when bias correction is enabled.
26.3 Registers
Table 49: Instances
Base address
Peripheral
Instance
Description
0x4000D000
RNG
RNG
Random number generator
Configuration
Table 50: Register Overview
Register
Offset
Description
TASKS_START
0x000
Task starting the random number generator
TASKS_STOP
0x004
Task stopping the random number generator
EVENTS_VALRDY
0x100
Event being generated for every new random number written to the VALUE register
SHORTS
0x200
Shortcut register
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
CONFIG
0x504
Configuration register
VALUE
0x508
Output random number
26.3.1 SHORTS
Address offset: 0x200
Shortcut register
Page 254
26 RNG — Random number generator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW VALRDY_STOP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between VALRDY event and STOP task
See EVENTS_VALRDY and TASKS_STOP
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
26.3.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW VALRDY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for VALRDY event
See EVENTS_VALRDY
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
26.3.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW VALRDY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for VALRDY event
See EVENTS_VALRDY
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
26.3.4 CONFIG
Address offset: 0x504
Configuration register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW DERCEN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disabled
Enabled
1
Enabled
Bias correction
26.3.5 VALUE
Address offset: 0x508
Output random number
Page 255
26 RNG — Random number generator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
VALUE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..255]
Generated random number
26.4 Electrical specification
26.4.1 RNG Electrical Specification
Symbol
Description
IRNG
Run current, CPU sleeping.
Min.
Typ.
500
Max.
Units
µA
tRNG,START
Time from setting the START task to generation begins. This is
128
µs
30
µs
120
µs
a one-time delay on START signal and does not apply between
samples.
tRNG,RAW
Run time per byte without bias correction. Uniform distribution
of 0 and 1 is not guaranteed.
tRNG,BC
Run time per byte with bias correction. Uniform distribution
of 0 and 1 is guaranteed. Time to generate a byte cannot be
guaranteed.
Page 256
27 TEMP — Temperature sensor
27 TEMP — Temperature sensor
The temperature sensor measures die temperature over the temperature range of the device. Linearity
compensation can be implemented if required by the application.
Listed here are the main features for TEMP:
•
•
Temperature range is greater than or equal to operating temperature of the device
Resolution is 0.25 degrees
TEMP is started by triggering the START task.
When the temperature measurement is completed, a DATARDY event will be generated and the result of the
measurement can be read from the TEMP register.
To achieve the measurement accuracy stated in the electrical specification, the crystal oscillator must be
selected as the HFCLK source, see CLOCK — Clock control on page 101 for more information.
When the temperature measurement is completed, TEMP analog electronics power down to save power.
TEMP only supports one-shot operation, meaning that every TEMP measurement has to be explicitly started
using the START task.
27.1 Registers
Table 51: Instances
Base address
Peripheral
Instance
Description
0x4000C000
TEMP
TEMP
Temperature sensor
Table 52: Register Overview
Register
Offset
Description
TASKS_START
0x000
Start temperature measurement
TASKS_STOP
0x004
Stop temperature measurement
EVENTS_DATARDY
0x100
Temperature measurement complete, data ready
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
TEMP
0x508
Temperature in °C (0.25° steps)
A0
0x520
Slope of 1st piece wise linear function
A1
0x524
Slope of 2nd piece wise linear function
A2
0x528
Slope of 3rd piece wise linear function
A3
0x52C
Slope of 4th piece wise linear function
A4
0x530
Slope of 5th piece wise linear function
A5
0x534
Slope of 6th piece wise linear function
B0
0x540
y-intercept of 1st piece wise linear function
B1
0x544
y-intercept of 2nd piece wise linear function
B2
0x548
y-intercept of 3rd piece wise linear function
B3
0x54C
y-intercept of 4th piece wise linear function
B4
0x550
y-intercept of 5th piece wise linear function
B5
0x554
y-intercept of 6th piece wise linear function
T0
0x560
End point of 1st piece wise linear function
T1
0x564
End point of 2nd piece wise linear function
T2
0x568
End point of 3rd piece wise linear function
T3
0x56C
End point of 4th piece wise linear function
T4
0x570
End point of 5th piece wise linear function
Page 257
Configuration
27 TEMP — Temperature sensor
27.1.1 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW DATARDY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for DATARDY event
See EVENTS_DATARDY
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
27.1.2 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW DATARDY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for DATARDY event
See EVENTS_DATARDY
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
27.1.3 TEMP
Address offset: 0x508
Temperature in °C (0.25° steps)
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
TEMP
Temperature in °C (0.25° steps)
Result of temperature measurement. Die temperature in °C, 2's
complement format, 0.25 °C steps
Decision point: DATARDY
27.1.4 A0
Address offset: 0x520
Slope of 1st piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x00000320
Id
RW Field
A
RW A0
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0
Value
Description
Slope of 1st piece wise linear function
27.1.5 A1
Address offset: 0x524
Page 258
27 TEMP — Temperature sensor
Slope of 2nd piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x00000343
Id
RW Field
A
RW A1
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1
Value
Description
Slope of 2nd piece wise linear function
27.1.6 A2
Address offset: 0x528
Slope of 3rd piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x0000035D
Id
RW Field
A
RW A2
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 1
Value
Description
Slope of 3rd piece wise linear function
27.1.7 A3
Address offset: 0x52C
Slope of 4th piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x00000400
Id
RW Field
A
RW A3
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Value
Description
Slope of 4th piece wise linear function
27.1.8 A4
Address offset: 0x530
Slope of 5th piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x0000047F
Id
RW Field
A
RW A4
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1
Value
Description
Slope of 5th piece wise linear function
27.1.9 A5
Address offset: 0x534
Slope of 6th piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x0000037B
Id
RW Field
A
RW A5
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 1 1
Value
Description
Slope of 6th piece wise linear function
27.1.10 B0
Address offset: 0x540
y-intercept of 1st piece wise linear function
Page 259
27 TEMP — Temperature sensor
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00003FCC
Id
RW Field
A
RW B0
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0
Value
Description
y-intercept of 1st piece wise linear function
27.1.11 B1
Address offset: 0x544
y-intercept of 2nd piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00003F98
Id
RW Field
A
RW B1
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0
Value
Description
y-intercept of 2nd piece wise linear function
27.1.12 B2
Address offset: 0x548
y-intercept of 3rd piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00003F98
Id
RW Field
A
RW B2
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0
Value
Description
y-intercept of 3rd piece wise linear function
27.1.13 B3
Address offset: 0x54C
y-intercept of 4th piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00000012
Id
RW Field
A
RW B3
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
Value
Description
y-intercept of 4th piece wise linear function
27.1.14 B4
Address offset: 0x550
y-intercept of 5th piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x0000006A
Id
RW Field
A
RW B4
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0
Value
Description
y-intercept of 5th piece wise linear function
27.1.15 B5
Address offset: 0x554
y-intercept of 6th piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00003DD0
Id
RW Field
A
RW B5
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 0 1 0 0 0 0
Value
Description
y-intercept of 6th piece wise linear function
Page 260
27 TEMP — Temperature sensor
27.1.16 T0
Address offset: 0x560
End point of 1st piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x000000E2
Id
RW Field
A
RW T0
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0
Value
Description
End point of 1st piece wise linear function
27.1.17 T1
Address offset: 0x564
End point of 2nd piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW T1
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
End point of 2nd piece wise linear function
27.1.18 T2
Address offset: 0x568
End point of 3rd piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000014
Id
RW Field
A
RW T2
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0
Value
Description
End point of 3rd piece wise linear function
27.1.19 T3
Address offset: 0x56C
End point of 4th piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000019
Id
RW Field
A
RW T3
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1
Value
Description
End point of 4th piece wise linear function
27.1.20 T4
Address offset: 0x570
End point of 5th piece wise linear function
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000050
Id
RW Field
A
RW T4
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0
Value
Description
End point of 5th piece wise linear function
Page 261
27 TEMP — Temperature sensor
27.2 Electrical specification
27.2.1 Temperature Sensor Electrical Specification
Symbol
Description
tTEMP
Time required for temperature measurement
Min.
Typ.
Max.
TTEMP,RANGE
Temperature sensor range
-40
85
°C
TTEMP,ACC
Temperature sensor accuracy
-5
5
°C
TTEMP,RES
Temperature sensor resolution
0.25
TTEMP,STB
Sample to sample stability at constant device temperature
+/-0.25
TTEMP,OFFST
Sample offset at 25°C
36
-2.5
Page 262
Units
µs
°C
°C
2.5
°C
28 ECB — AES electronic codebook mode
encryption
28 ECB — AES electronic codebook mode encryption
The AES electronic codebook mode encryption (ECB) can be used for a range of cryptographic functions
like hash generation, digital signatures, and keystream generation for data encryption/decryption. The ECB
encryption block supports 128 bit AES encryption (encryption only, not decryption).
AES ECB operates with EasyDMA access to system Data RAM for in-place operations on cleartext
and ciphertext during encryption. ECB uses the same AES core as the CCM and AAR blocks and is an
asynchronous operation which may not complete if the AES core is busy.
AES ECB features:
•
•
•
•
128 bit AES encryption
Supports standard AES ECB block encryption
Memory pointer support
DMA data transfer
AES ECB performs a 128 bit AES block encrypt. At the STARTECB task, data and key is loaded into
the algorithm by EasyDMA. When output data has been written back to memory, the ENDECB event is
triggered.
AES ECB can be stopped by triggering the STOPECB task.
28.1 Shared resources
The ECB, CCM, and AAR share the same AES module. The ECB will always have lowest priority and if there
is a sharing conflict during encryption, the ECB operation will be aborted and an ERRORECB event will be
generated.
28.2 EasyDMA
The ECB implements an EasyDMA mechanism for reading and writing to the Data RAM. This DMA cannot
access the program memory or any other parts of the memory area except RAM.
If the ECBDATAPTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault
or RAM corruption. See Memory on page 23 for more information about the different memory regions.
The EasyDMA will have finished accessing the Data RAM when the ENDECB or ERRORECB is generated.
28.3 ECB data structure
Input to the block encrypt and output from the block encrypt are stored in the same data structure.
ECBDATAPTR should point to this data structure before STARTECB is initiated.
Table 53: ECB data structure overview
Property
KEY
CLEARTEXT
CIPHERTEXT
Address offset
0
16
32
Description
16 byte AES key
16 byte AES cleartext input block
16 byte AES ciphertext output block
Page 263
28 ECB — AES electronic codebook mode
encryption
28.4 Registers
Table 54: Instances
Base address
Peripheral
Instance
Description
0x4000E000
ECB
ECB
AES Electronic Code Book (ECB) mode
Configuration
block encryption
Table 55: Register Overview
Register
Offset
Description
TASKS_STARTECB
0x000
Start ECB block encrypt
TASKS_STOPECB
0x004
Abort a possible executing ECB operation
EVENTS_ENDECB
0x100
ECB block encrypt complete
EVENTS_ERRORECB
0x104
ECB block encrypt aborted because of a STOPECB task or due to an error
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ECBDATAPTR
0x504
ECB block encrypt memory pointers
28.4.1 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
RW Field
A
RW ENDECB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for ENDECB event
See EVENTS_ENDECB
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERRORECB
Write '1' to Enable interrupt for ERRORECB event
See EVENTS_ERRORECB
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
28.4.2 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
RW Field
A
RW ENDECB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for ENDECB event
See EVENTS_ENDECB
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERRORECB
Write '1' to Disable interrupt for ERRORECB event
See EVENTS_ERRORECB
Clear
1
Disable
Disabled
0
Read: Disabled
Page 264
28 ECB — AES electronic codebook mode
encryption
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
0
RW Field
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Read: Enabled
28.4.3 ECBDATAPTR
Address offset: 0x504
ECB block encrypt memory pointers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0
Id
RW Field
Value Id
A
RW ECBDATAPTR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to the ECB data structure (see Table 1 ECB data
structure overview)
28.5 Electrical specification
28.5.1 ECB Electrical Specification
Symbol
Description
tECB
Run time per 16 byte block in all modes
Min.
Typ.
6
Page 265
Max.
Units
µs
29 CCM — AES CCM mode encryption
29 CCM — AES CCM mode encryption
Cipher block chaining - message authentication code (CCM) mode is an authenticated encryption algorithm
designed to provide both authentication and confidentiality during data transfer. CCM combines counter
mode encryption and CBC-MAC authentication. The CCM terminology "Message authentication code
(MAC)" is called the "Message integrity check (MIC)" in 'Bluetooth terminology and also in this document.
The CCM block generates an encrypted keystream that is applied to input data using the XOR operation
and generates the 4 byte MIC field in one operation. The CCM and radio can be configured to work
synchronously. The CCM will encrypt in time for transmission and decrypt after receiving bytes into memory
from the Radio. All operations can complete within the packet RX or TX time. CCM on this device is
implemented according to Bluetooth requirements and the algorithm as defined in IETF RFC3610, and
depends on the AES-128 block cipher. A description of the CCM algorithm can also be found in NIST Special
Publication 800-38C. The Bluetooth specification describes the configuration of counter mode blocks and
encryption blocks to implement compliant encryption for BLE.
The CCM block uses EasyDMA to load key, counter mode blocks (including the nonce required), and to
read/write plain text and cipher text.
The AES CCM supports three operations: key-stream generation, packet encryption, and packet decryption.
23
All these operations are done in compliance with the Bluetooth specification. A new key-stream must be
generated before a new packet encryption or packet decryption operation can be started.
A key-stream is generated by triggering the KSGEN task. An ENDKSGEN event will be generated when the
new key-stream has been generated. The key-stream will be stored in the AES CCM’s temporary memory
area, specified by the SCRATCHPTR, where it will be used in subsequent encryption and decryption
operations.
Encryption is started by triggering the CRYPT task with the MODE register set to ENCRYPTION. Similarly,
decryption is started by triggering the same task with MODE set to DECRYPTION. An ENDCRYPT event
will be generated when packet encryption is completed as well as when packet decryption is completed, see
Figure 59: Key-stream generation followed by encryption or decryption. The shortcut is optional. on page
266.
key-stream
generation
KSGEN
encryption / decryption
ENDKSGEN
CRYPT
ENDCRYPT
SHORTCUT
Figure 59: Key-stream generation followed by encryption or decryption. The shortcut is optional.
Key-stream generation, packet encryption, and packet decryption operations utilize the configuration
specified in the data structure pointed to by the CNFPTR pointer. It is necessary to configure this pointer and
its underlying data structure, and the MODE register before the KSGEN task is triggered. It is also necessary
to configure the INPTR pointer and the OUTPTR pointer before the CRYPT task is triggered.
If a shortcut is used between ENDKSGEN event and CRYPT task, the INPTR pointer and the OUTPTR
pointer must be configured before the KSGEN task is triggered.
The AES CCM supports different packet lengths, this is configured via the PACKETLENGTH field in the
MODE register.
23
Bluetooth AES CCM 128 bit block encryption, see Bluetooth Core specification Version 4.0.
Page 266
29 CCM — AES CCM mode encryption
29.1 Shared resources
The CCM shares registers and other resources with other peripherals that have the same ID as the CCM.
The user must therefore disable all peripherals that have the same ID as the CCM before the CCM can be
configured and used.
Disabling a peripheral that have the same ID as the CCM will not reset any of the registers that are shared
with the CCM. It is therefore important to configure all relevant CCM registers explicitly to secure that it
operates correctly.
See the Instantiation table in Instantiation on page 24 for details on peripherals and their IDs.
29.2 Encryption
During packet encryption, the AES CCM will read the unencrypted packet located in RAM at the address
specified in the INPTR pointer, encrypt the packet and append a four byte long Message Integrity Check
(MIC) field to the packet.
The AES CCM will also modify the length field of the packet to adjust for the appended MIC field, that is,
add four bytes to the length, and store the resulting packet back into RAM at the address specified in the
OUTPTR pointer, see Figure 60: Encryption on page 267.
Empty packets (length field is set to 0) will not be encrypted but instead moved unmodified through the AES
CCM.
SCRATCHPTR
INPTR
Unencrypted packet
H
L
H
L+4
OUTPTR
RFU
MODE = ENCRYPTION
Encrypted packet
RFU
Scratch area
PL
EPL
AES CCM
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
PL: unencrypted payload
EPL: encrypted payload
CCM data
structure
MIC
CNFPTR
Figure 60: Encryption
29.3 Decryption
During packet decryption, the AES CCM will read the encrypted packet located in RAM at the address
specified in the INPTR pointer, decrypt the packet, authenticate the packet’s MIC field and generate the
appropriate MIC status.
The AES CCM will also modify the length field of the packet to adjust for the MIC field, that is, subtract
four bytes from the length, and then store the decrypted packet into RAM at the address pointed to by the
OUTPTR pointer, see Figure 61: Decryption on page 268.
The CCM is only able to decrypt packets that are at least 5 bytes long, that is, 1 byte or more encrypted
payload (EPL) and 4 bytes of MIC. The CCM will therefore generate a MIC error for packets where the length
field is set to 1, 2, 3 or 4.
Empty packets (length field is set to 0) will not be decrypted but instead moved unmodified through the AES
CCM, these packets will always pass the MIC check.
Page 267
29 CCM — AES CCM mode encryption
SCRATCHPTR
OUTPTR
Unencrypted packet
H
L
INPTR
RFU
MODE = DECRYPTION
Encrypted packet
H
L+4
RFU
Scratch area
PL
EPL
AES CCM
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
PL: unencrypted payload
EPL: encrypted payload
CCM data
structure
MIC
CNFPTR
Figure 61: Decryption
29.4 AES CCM and RADIO concurrent operation
The AES CCM is designed to run in parallel with the RADIO to enable on-the-fly encryption and decryption
of RADIO packets without CPU involvement. To facilitate this, the RADIO has to be configured with specific
settings.
Table 56: Radio configuration settings
Radio parameter
PCNF0.S0LEN
Value
1
PCNF0.LFLEN
5 or 8
PCNF0.S1LEN
3 or 0
PCNF0.S1
Include
MODE
PCNF1.BALEN
CRCCNF.LEN
Ble_1Mbit
3
3
Description
Length of HEADER field in: Table 58: Data structure for unencrypted packet on page 270 and Table
59: Data structure for encrypted packet on page 270.
Length of LENGTH field in: Table 58: Data structure for unencrypted packet on page 270 and Table
59: Data structure for encrypted packet on page 270.
Length of the RFU field in: Table 58: Data structure for unencrypted packet on page 270 and Table
59: Data structure for encrypted packet on page 270. The combined length of LENGTH and RFU
must always be 8 bit.
Always include the S1 field (RFU field) in RAM to secure that the same data structure can be used
for PCNF0.S1LEN = 3 and PCNF0.S1LEN = 0: Table 58: Data structure for unencrypted packet on page
270 and Table 59: Data structure for encrypted packet on page 270.
Data rate. Must match CCM->MODE.DATARATE
Length of address (32 bit)
Length of CRC (24 bit)
29.5 Encrypting packets on-the-fly in radio transmit mode
When the AES CCM is encrypting a packet on-the-fly at the same time as the RADIO is transmitting it, the
RADIO must read the encrypted packet from the same memory location as the AES CCM is writing to.
The OUTPTR pointer in the AES CCM must therefore point to the same memory location as the
PACKETPTR pointer in the RADIO, see Figure 62: Configuration of on-the-fly encryption on page 268.
SCRATCHPTR
INPTR
Unencrypted packet
OUTPTR
&
PACKETPTR
H
L
RFU
MODE = ENCRYPTION
Encrypted packet
H
L+4
RFU
Scratch area
PL
EPL
AES CCM
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
PL: unencrypted payload
EPL: encrypted payload
CCM data
structure
MIC
CNFPTR
To remote
receiver
RADIO
TXEN
Figure 62: Configuration of on-the-fly encryption
In order to match the RADIO’s timing, the KSGEN task must be triggered no later than when the START task
in the RADIO is triggered, in addition the shortcut between the ENDKSGEN event and the CRYPT task must
be enabled. This use-case is illustrated in Figure 63: On-the-fly encryption using a PPI connection on page
269 using a PPI connection between the READY event in the RADIO and the KSGEN task in the AES
CCM.
Page 268
29 CCM — AES CCM mode encryption
SHORTCUT
ENDKSGEN
CRYPT
key-stream
generation
AES CCM
encryption
KSGEN
ENDCRYPT
PPI
READY
RADIO
RU
P
A
H
L
RFU
EPL
MIC
CRC
TXEN
END
READY
RU: Ramp-up of RADIO
P: Preamble
A: Address
START
SHORTCUT
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
EPL: encrypted payload
Figure 63: On-the-fly encryption using a PPI connection
29.6 Decrypting packets on-the-fly in radio receive mode
When the AES CCM is decrypting a packet on-the-fly at the same time as the RADIO is receiving it, the AES
CCM must read the encrypted packet from the same memory location as the RADIO is writing to.
The INPTR pointer in the AES CCM must therefore point to the same memory location as the PACKETPTR
pointer in the RADIO, see Figure 64: Configuration of on-the-fly decryption on page 269.
SCRATCHPTR
OUTPTR
Unencrypted packet
INPTR
&
PACKETPTR
H
L
H
L+4
RFU
AES CCM
MODE = DECRYPTION
Encrypted packet
RFU
Scratch area
PL
EPL
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
PL: unencrypted payload
EPL: encrypted payload
CCM data
structure
MIC
CNFPTR
From remote
transmitter
RADIO
RXEN
Figure 64: Configuration of on-the-fly decryption
In order to match the RADIO’s timing, the KSGEN task must be triggered no later than when the START task
in the RADIO is triggered. In addition, the CRYPT task must be triggered no earlier than when the ADDRESS
event is generated by the RADIO.
If the CRYPT task is triggered exactly at the same time as the ADDRESS event is generated by the RADIO,
the AES CCM will guarantee that the decryption is completed no later than when the END event in the
RADIO is generated.
This use-case is illustrated in Figure 65: On-the-fly decryption using a PPI connection between the READY
event in the RADIO and the KSGEN task in the AES CCM on page 270 using a PPI connection between
the ADDRESS event in the RADIO and the CRYPT task in the AES CCM. The KSGEN task is triggered from
the READY event in the RADIO through a PPI connection.
Page 269
29 CCM — AES CCM mode encryption
key-stream
generation
AES CCM
KSGEN
decryption
CRYPT
ENDKSGEN
ENDCRYPT
PPI
PPI
READY
RADIO
ADDRESS
RU
P
A
H
L
RFU
EPL
MIC
RXEN
CRC
END
READY
RU: Ramp-up of RADIO
P: Preamble
A: Address
START
SHORTCUT
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
EPL: encrypted payload
: RADIO receiving noise
Figure 65: On-the-fly decryption using a PPI connection between the READY event in the RADIO and
the KSGEN task in the AES CCM
29.7 CCM data structure
The CCM data structure is located in Data RAM at the memory location specified by the CNFPTR pointer
register.
Table 57: CCM data structure overview
Property
Address offset
Description
KEY
0
16 byte AES key
PKTCTR
16
Octet0 (LSO) of packet counter
17
Octet1 of packet counter
18
Octet2 of packet counter
19
Octet3 of packet counter
20
Bit 6 – Bit 0: Octet4 (7 most significant bits of packet counter, with Bit 6 being the most significant
bit) Bit7: Ignored
IV
21
Ignored
22
Ignored
23
Ignored
24
Bit 0: Direction bit Bit 7 – Bit 1: Zero padded
25
8 byte initialization vector (IV) Octet0 (LSO) of IV, Octet1 of IV, … , Octet7 (MSO) of IV
The NONCE vector (as specified by the Bluetooth Core Specification) will be generated by hardware based
on the information specified in the CCM data structure from Table 57: CCM data structure overview on page
270 .
Table 58: Data structure for unencrypted packet
Property
Address offset
Description
HEADER
0
Packet Header
LENGTH
1
Number of bytes in unencrypted payload
RFU
2
Reserved Future Use
PAYLOAD
3
Unencrypted payload
Table 59: Data structure for encrypted packet
Property
Address offset
Description
HEADER
0
Packet Header
LENGTH
1
Number of bytes in encrypted payload including length of MIC
Important: LENGTH will be 0 for empty packets since the MIC is not added to empty
packets
RFU
2
Reserved Future Use
PAYLOAD
3
Encrypted payload
MIC
3 + payload length
ENCRYPT: 4 bytes encrypted MIC
Page 270
29 CCM — AES CCM mode encryption
Property
Address offset
Description
Important: MIC is not added to empty packets
29.8 EasyDMA and ERROR event
The CCM implements an EasyDMA mechanism for reading and writing to the RAM.
In some scenarios where the CPU and other DMA enabled peripherals are accessing the RAM at the same
time, the CCM DMA could experience some bus conflicts which may also result in an error during encryption.
If this happens, the ERROR event will be generated.
The EasyDMA will have finished accessing the RAM when the ENDKSGEN and ENDCRYPT events are
generated.
If the CNFPTR, SCRATCHPTR, INPTR and the OUTPTR are not pointing to the Data RAM region,
an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 23 for more
information about the different memory regions.
29.9 Registers
Table 60: Instances
Base address
Peripheral
Instance
Description
0x4000F000
CCM
CCM
AES CCM Mode Encryption
Configuration
Table 61: Register Overview
Register
Offset
Description
TASKS_KSGEN
0x000
Start generation of key-stream. This operation will stop by itself when completed.
TASKS_CRYPT
0x004
Start encryption/decryption. This operation will stop by itself when completed.
TASKS_STOP
0x008
Stop encryption/decryption
EVENTS_ENDKSGEN
0x100
Key-stream generation complete
EVENTS_ENDCRYPT
0x104
Encrypt/decrypt complete
EVENTS_ERROR
0x108
CCM error event
SHORTS
0x200
Shortcut register
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
MICSTATUS
0x400
MIC check result
ENABLE
0x500
Enable
MODE
0x504
Operation mode
CNFPTR
0x508
Pointer to data structure holding AES key and NONCE vector
INPTR
0x50C
Input pointer
OUTPTR
0x510
Output pointer
SCRATCHPTR
0x514
Pointer to data area used for temporary storage
29.9.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ENDKSGEN_CRYPT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between ENDKSGEN event and CRYPT task
See EVENTS_ENDKSGEN and TASKS_CRYPT
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
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29 CCM — AES CCM mode encryption
29.9.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW ENDKSGEN
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for ENDKSGEN event
See EVENTS_ENDKSGEN
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDCRYPT
Write '1' to Enable interrupt for ENDCRYPT event
See EVENTS_ENDCRYPT
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Enable interrupt for ERROR event
See EVENTS_ERROR
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
29.9.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW ENDKSGEN
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for ENDKSGEN event
See EVENTS_ENDKSGEN
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDCRYPT
Write '1' to Disable interrupt for ENDCRYPT event
See EVENTS_ENDCRYPT
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Disable interrupt for ERROR event
See EVENTS_ERROR
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
29.9.4 MICSTATUS
Address offset: 0x400
MIC check result
Page 272
29 CCM — AES CCM mode encryption
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
MICSTATUS
The result of the MIC check performed during the previous
decryption operation
CheckFailed
0
MIC check failed
CheckPassed
1
MIC check passed
29.9.5 ENABLE
Address offset: 0x500
Enable
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
2
Enable
Enable or disable CCM
29.9.6 MODE
Address offset: 0x504
Operation mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
Reset 0x00000001
Id
RW Field
A
RW MODE
B
C
0
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Description
Encryption
0
AES CCM packet encryption mode
Decryption
1
AES CCM packet decryption mode
1Mbit
0
In synch with 1 Mbit data rate
2Mbit
1
In synch with 2 Mbit data rate
Default
0
Default length. Effective length of LENGTH field is 5-bit
Extended
1
Extended length. Effective length of LENGTH field is 8-bit
The mode of operation to be used
RW DATARATE
Data rate that the CCM shall run in synch with
RW LENGTH
Packet length configuration
29.9.7 CNFPTR
Address offset: 0x508
Pointer to data structure holding AES key and NONCE vector
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CNFPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to the data structure holding the AES key and the CCM
NONCE vector (see Table 1 CCM data structure overview)
29.9.8 INPTR
Address offset: 0x50C
Input pointer
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29 CCM — AES CCM mode encryption
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW INPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Input pointer
29.9.9 OUTPTR
Address offset: 0x510
Output pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW OUTPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Output pointer
29.9.10 SCRATCHPTR
Address offset: 0x514
Pointer to data area used for temporary storage
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW SCRATCHPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to a scratch data area used for temporary storage
during key-stream generation, MIC generation and encryption/
decryption.
The scratch area is used for temporary storage of data during
key-stream generation and encryption.
A space of 43 bytes, or (16 + MAXPACKETSIZE) bytes, whatever
is largest, must be reserved in RAM.
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30 AAR — Accelerated address resolver
30 AAR — Accelerated address resolver
Accelerated address resolver is a cryptographic support function for implementing the "Resolvable Private
Address Resolution Procedure" described in the Bluetooth Core specification v4.0. "Resolvable private
address generation" should be achieved using ECB and is not supported by AAR.
The procedure allows two devices that share a secret key to generate and resolve a hash based on their
device address. The AAR block enables real-time address resolution on incoming packets when configured
as described in this chapter. This allows real-time packet filtering (whitelisting) using a list of known shared
keys (Identity Resolving Keys (IRK) in Bluetooth).
30.1 Shared resources
The AAR shares registers and other resources with the peripherals that have the same ID as the AAR.
The user must therefore disable all peripherals that have the same ID as the AAR before the AAR can be
configured and used.
Disabling a peripheral that have the same ID as the AAR will not reset any of the registers that are shared
with the AAR. It is therefore important to configure all relevant AAR registers explicitly to secure that it
operates correctly.
See the Instantiation table in Instantiation on page 24 for details on peripherals and their IDs.
30.2 EasyDMA
The AAR implements EasyDMA for reading and writing to the RAM. The EasyDMA will have finished
accessing the RAM when the END, RESOLVED, and NOTRESOLVED events are generated.
If the IRKPTR, ADDRPTR and the SCRATCHPTR is not pointing to the Data RAM region, an EasyDMA
transfer may result in a HardFault or RAM corruption. See Memory on page 23 for more information about
the different memory regions.
30.3 Resolving a resolvable address
As per Bluetooth specification, a private resolvable address is composed of six bytes.
LSB
MSB
random
hash
(24-bit)
10
prand
(24-bit)
Figure 66: Resolvable address
To resolve an address the ADDRPTR register must point to the start of packet. The resolver is started by
triggering the START task. A RESOLVED event is generated when the AAR manages to resolve the address
using one of the Identity Resolving Keys (IRK) found in the IRK data structure. The AAR will use the IRK
specified in the register IRK0 to IRK15 starting from IRK0. How many to be used is specified by the NIRK
register. The AAR module will generate a NOTRESOLVED event if it is not able to resolve the address using
the specified list of IRKs.
The AAR will go through the list of available IRKs in the IRK data structure and for each IRK try to resolve
the address according to the Resolvable Private Address Resolution Procedure described in the Bluetooth
24
Specification . The time it takes to resolve an address may vary depending on where in the list the
24
Bluetooth Specification Version 4.0 [Vol 3] chapter 10.8.2.3.
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30 AAR — Accelerated address resolver
resolvable address is located. The resolution time will also be affected by RAM accesses performed by other
peripherals and the CPU. See the Electrical specifications for more information about resolution time.
The AAR will only do a comparison of the received address to those programmed in the module. And not
check what type of address it actually is.
The AAR will stop as soon as it has managed to resolve the address, or after trying to resolve the address
using NIRK number of IRKs from the IRK data structure. The AAR will generate an END event after it has
stopped.
SCRATCHPTR
ADDR: resolvable address
START
Scratch area
ADDRPTR
RESOLVED
AAR
S0
L
S1
IRK data
structure
ADDR
IRKPTR
Figure 67: Address resolution with packet preloaded into RAM
30.4 Use case example for chaining RADIO packet reception with
address resolution using AAR
The AAR may be started as soon as the 6 bytes required by the AAR have been received by the RADIO and
stored in RAM. The ADDRPTR pointer must point to the start of packet.
SCRATCHPTR
S0: S0 field of RADIO (optional)
L: Length field of RADIO (optional)
S1: S1 field of RADIO (optional)
ADDR: resolvable address
START
PACKETPTR
ADDRPTR
Scratch area
RESOLVED
AAR
S0
L
S1
IRK data
structure
ADDR
IRKPTR
From remote
transmitter
RADIO
RXEN
Figure 68: Address resolution with packet loaded into RAM by the RADIO
30.5 IRK data structure
The IRK data structure is located in RAM at the memory location specified by the CNFPTR pointer register.
Table 62: IRK data structure overview
Property
IRK0
IRK1
..
IRK15
Address offset
0
16
..
240
Description
IRK number 0 (16 - byte)
IRK number 1 (16 - byte)
..
IRK number 15 (16 - byte)
Page 276
30 AAR — Accelerated address resolver
30.6 Registers
Table 63: Instances
Base address
Peripheral
Instance
Description
0x4000F000
AAR
AAR
Acelerated Address Resolver
Configuration
Table 64: Register Overview
Register
Offset
Description
TASKS_START
0x000
Start resolving addresses based on IRKs specified in the IRK data structure
TASKS_STOP
0x008
Stop resolving addresses
EVENTS_END
0x100
Address resolution procedure complete
EVENTS_RESOLVED
0x104
Address resolved
EVENTS_NOTRESOLVED 0x108
Address not resolved
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
STATUS
0x400
Resolution status
ENABLE
0x500
Enable AAR
NIRK
0x504
Number of IRKs
IRKPTR
0x508
Pointer to IRK data structure
ADDRPTR
0x510
Pointer to the resolvable address
SCRATCHPTR
0x514
Pointer to data area used for temporary storage
30.6.1 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW END
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for END event
See EVENTS_END
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RESOLVED
Write '1' to Enable interrupt for RESOLVED event
See EVENTS_RESOLVED
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW NOTRESOLVED
Write '1' to Enable interrupt for NOTRESOLVED event
See EVENTS_NOTRESOLVED
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
30.6.2 INTENCLR
Address offset: 0x308
Disable interrupt
Page 277
30 AAR — Accelerated address resolver
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW END
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for END event
See EVENTS_END
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RESOLVED
Write '1' to Disable interrupt for RESOLVED event
See EVENTS_RESOLVED
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW NOTRESOLVED
Write '1' to Disable interrupt for NOTRESOLVED event
See EVENTS_NOTRESOLVED
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
30.6.3 STATUS
Address offset: 0x400
Resolution status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
STATUS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..15]
The IRK that was used last time an address was resolved
30.6.4 ENABLE
Address offset: 0x500
Enable AAR
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
3
Enable
Enable or disable AAR
30.6.5 NIRK
Address offset: 0x504
Number of IRKs
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000001
Id
RW Field
A
RW NIRK
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value
Description
[1..16]
Number of Identity root keys available in the IRK data structure
30.6.6 IRKPTR
Address offset: 0x508
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30 AAR — Accelerated address resolver
Pointer to IRK data structure
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW IRKPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to the IRK data structure
30.6.7 ADDRPTR
Address offset: 0x510
Pointer to the resolvable address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ADDRPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to the resolvable address (6-bytes)
30.6.8 SCRATCHPTR
Address offset: 0x514
Pointer to data area used for temporary storage
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0
Id
RW Field
Value Id
A
RW SCRATCHPTR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to a scratch data area used for temporary storage
during resolution.A space of minimum 3 bytes must be
reserved.
30.7 Electrical specification
30.7.1 AAR Electrical Specification
Symbol
Description
tAAR,8
Time for address resolution of 8 IRKs
Min.
Typ.
48
Page 279
Max.
Units
µs
31 SPIM — Serial peripheral interface master with
EasyDMA
31 SPIM — Serial peripheral interface master with
EasyDMA
The SPI master can communicate with multiple slaves using individual chip select signals for each of the
slave devices attached to a bus.
Listed here are the main features for the SPIM
STOP
Three SPIM instances
SPI mode 0-3
EasyDMA direct transfer to/from RAM for both SPI Slave and SPI Master
Individual selection of IO pin for each SPI signal
START
•
•
•
•
SPIM
GPIO
RAM
PSEL.MOSI
TXD.PTR
buffer[0]
buffer[1]
MOSI
Pin
SCK
Pin
TXD+1
TXD buffer
EasyDMA
buffer[TXD.MAXCNT-1]
PSEL.SCK
buffer[0]
buffer[1]
MISO
Pin
RXD-1
EasyDMA
PSEL.MISO
RXD.PTR
RXD buffer
ENDRX
ENDTX
STARTED
buffer[RXD.MAXCNT-1]
Figure 69: SPIM — SPI master with EasyDMA
The SPIM does not implement support for chip select directly. Therefore, the CPU must use available GPIOs
to select the correct slave and control this independently of the SPI master. The SPIM supports SPI modes 0
through 3. The CONFIG register allows setting CPOL and CPHA appropriately.
Table 65: SPI modes
Mode
Clock polarity
CPOL
SPI_MODE00 (Leading)
SPI_MODE10 (Leading)
SPI_MODE21 (Trailing)
SPI_MODE31 (Trailing)
Clock phase
CPHA
0 (Active High)
1 (Active Low)
0 (Active High)
1 (Active Low)
31.1 Shared resources
The SPI shares registers and other resources with other peripherals that have the same ID as the SPI.
Therefore, the user must disable all peripherals that have the same ID as the SPI before the SPI can be
configured and used.
Page 280
31 SPIM — Serial peripheral interface master with
EasyDMA
Disabling a peripheral that has the same ID as the SPI will not reset any of the registers that are shared with
the SPI. It is therefore important to configure all relevant SPI registers explicitly to secure that it operates
correctly.
See the Instantiation table in Instantiation on page 24 for details on peripherals and their IDs.
31.2 EasyDMA
The SPI master implements EasyDMA for reading and writing of data packets from and to the DATA RAM
without CPU involvement.
The RXD.PTR and TXD.PTR point to the RXD buffer (receive buffer) and TXD buffer (transmit buffer)
respectively, see Figure 69: SPIM — SPI master with EasyDMA on page 280. RXD.MAXCNT and
TXD.MAXCNT specify the maximum number of bytes allocated to the buffers.
The SPI master will automatically stop transmitting after TXD.MAXCNT bytes have been transmitted and
RXD.MAXCNT bytes have been received. If TXD.MAXCNT is larger than RXD.MAXCNT, the superfluous
received bytes will be ignored. If RXD.MAXCNT is larger than TXD.MAXCNT, the remaining transmitted
bytes will contain the value defined in the ORC register.
If the RXD.PTR and the TXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result
in a HardFault or RAM corruption. See Memory on page 23 for more information about the different memory
regions.
The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next
transmission immediately after having received the STARTED event.
The ENDRX/ENDTX event indicate that EasyDMA has finished accessing respectively the RX/TX buffer in
RAM. The END event gets generated when both RX and TX are finished accessing the buffers in RAM.
31.2.1 EasyDMA list
EasyDMA supports one list type.
The supported list type is:
•
Array list
EasyDMA array list
The EasyDMA array list can be represented by the data structure ArrayList_type.
For illustration, see the code example below. This data structure includes only a buffer with size equal
to Channel.MAXCNT. EasyDMA will use the Channel.MAXCNT register to determine when the buffer
is full. Replace 'Channel' by the specific data channel you want to use, for instance 'NRF_SPIM->RXD',
'NRF_SPIM->TXD', 'NRF_TWIM->RXD', etc.
The Channel.MAXCNT register cannot be specified larger than the actual size of the buffer. If
Channel.MAXCNT is specified larger than the size of the buffer, the EasyDMA channel may overflow the
buffer.
This array list does not provide a mechanism to explicitly specify where the next item in the list is located.
Instead, it assumes that the list is organized as a linear array where items are located one after the other in
RAM.
#define BUFFER_SIZE
4
typedef struct ArrayList
{
uint8_t buffer[BUFFER_SIZE];
} ArrayList_type;
ArrayList_type MyArrayList[3];
Page 281
31 SPIM — Serial peripheral interface master with
EasyDMA
//replace 'Channel' below by the specific data channel you want to use,
//
for instance 'NRF_SPIM->RXD', 'NRF_TWIM->RXD', etc.
Channel.MAXCNT = BUFFER_SIZE;
Channel.PTR = &MyArrayList;
Channel.PTR = &MyArrayList
Note: addresses are
assuming that
sizeof(buffer[n]) is one byte
0x20000000 : MyArrayList[0]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000004 : MyArrayList[1]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000008 : MyArrayList[2]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
Figure 70: EasyDMA array list
31.3 SPI master transaction sequence
An SPI master transaction consists of a sequence started by the START task followed by a number of
events, and finally the STOP task.
An SPI master transaction is started by triggering the START task. The ENDTX event will be generated
when the transmitter has transmitted all bytes in the TXD buffer as specified in the TXD.MAXCNT register.
The ENDRX event will be generated when the receiver has filled the RXD buffer, i.e. received the last
possible byte as specified in the RXD.MAXCNT register.
Following a START task, the SPI master will generate an END event when both ENDRX and ENDTX have
been generated.
The SPI master is stopped by triggering the STOP task. A STOPPED event is generated when the SPI
master has stopped.
If the ENDRX event has not already been generated when the SPI master has come to a stop, the SPI
master will generate the ENDRX event explicitly even though the RX buffer is not full.
If the ENDTX event has not already been generated when the SPI master has come to a stop, the SPI
master will generate the ENDTX event explicitly even though all bytes in the TXD buffer, as specified in the
TXD.MAXCNT register, have not been transmitted.
The SPI master is a synchronous interface, and for every byte that is sent, a different byte will be received at
the same time; this is illustrated in Figure 71: SPI master transaction on page 283.
Page 282
31 SPIM — Serial peripheral interface master with
EasyDMA
CSN
SCK
MOSI
0
1
2
n
ORC
ORC
MISO
A
B
C
m-2
m-1
m
ENDRX
ENDTX
CPU
1
2
START
Figure 71: SPI master transaction
31.4 Low power
When putting the system in low power and the peripheral is not needed, lowest possible power consumption
is achieved by stopping, and then disabling the peripheral.
The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent,
software shall wait until the STOPPED event was received as a response before disabling the peripheral
through the ENABLE register.
31.5 Master mode pin configuration
The SCK, MOSI, and MISO signals associated with the SPI master are mapped to physical pins according to
the configuration specified in the PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers respectively.
The PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and their configurations are only used as long as
the SPI master is enabled, and retained only as long as the device is in ON mode. PSEL.SCK, PSEL.MOSI
and PSEL.MISO must only be configured when the SPI master is disabled.
To secure correct behavior in the SPI, the pins used by the SPI must be configured in the GPIO peripheral
as described in Table 66: GPIO configuration on page 283 prior to enabling the SPI. This configuration
must be retained in the GPIO for the selected IOs as long as the SPI is enabled.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behavior.
Table 66: GPIO configuration
SPI master signal
SCK
MOSI
MISO
SPI master pin
As specified in PSEL.SCK
As specified in PSEL.MOSI
As specified in PSEL.MISO
Direction
Output
Output
Input
Output value
Same as CONFIG.CPOL
0
Not applicable
Page 283
Comments
31 SPIM — Serial peripheral interface master with
EasyDMA
31.6 Registers
Table 67: Instances
Base address
Peripheral
Instance
Description
0x40003000
SPIM
SPIM0
SPI master 0
0x40004000
SPIM
SPIM1
SPI master 1
0x40023000
SPIM
SPIM2
SPI master 2
Configuration
Table 68: Register Overview
Register
Offset
Description
TASKS_START
0x010
Start SPI transaction
TASKS_STOP
0x014
Stop SPI transaction
TASKS_SUSPEND
0x01C
Suspend SPI transaction
TASKS_RESUME
0x020
Resume SPI transaction
EVENTS_STOPPED
0x104
SPI transaction has stopped
EVENTS_ENDRX
0x110
End of RXD buffer reached
EVENTS_END
0x118
End of RXD buffer and TXD buffer reached
EVENTS_ENDTX
0x120
End of TXD buffer reached
EVENTS_STARTED
0x14C
Transaction started
SHORTS
0x200
Shortcut register
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ENABLE
0x500
Enable SPIM
PSEL.SCK
0x508
Pin select for SCK
PSEL.MOSI
0x50C
Pin select for MOSI signal
PSEL.MISO
0x510
Pin select for MISO signal
FREQUENCY
0x524
SPI frequency
RXD.PTR
0x534
Data pointer
RXD.MAXCNT
0x538
Maximum number of bytes in receive buffer
RXD.AMOUNT
0x53C
Number of bytes transferred in the last transaction
RXD.LIST
0x540
EasyDMA list type
TXD.PTR
0x544
Data pointer
TXD.MAXCNT
0x548
Maximum number of bytes in transmit buffer
TXD.AMOUNT
0x54C
Number of bytes transferred in the last transaction
TXD.LIST
0x550
EasyDMA list type
CONFIG
0x554
Configuration register
ORC
0x5C0
Over-read character. Character clocked out in case and over-read of the TXD buffer.
31.6.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW END_START
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between END event and START task
See EVENTS_END and TASKS_START
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
31.6.2 INTENSET
Address offset: 0x304
Enable interrupt
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31 SPIM — Serial peripheral interface master with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
D
C
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for STOPPED event
See EVENTS_STOPPED
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDRX
Write '1' to Enable interrupt for ENDRX event
See EVENTS_ENDRX
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW END
Write '1' to Enable interrupt for END event
See EVENTS_END
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDTX
Write '1' to Enable interrupt for ENDTX event
See EVENTS_ENDTX
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STARTED
Write '1' to Enable interrupt for STARTED event
See EVENTS_STARTED
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
31.6.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
Value
Description
Write '1' to Disable interrupt for STOPPED event
See EVENTS_STOPPED
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDRX
Write '1' to Disable interrupt for ENDRX event
See EVENTS_ENDRX
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW END
Write '1' to Disable interrupt for END event
See EVENTS_END
D
D
C
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDTX
Write '1' to Disable interrupt for ENDTX event
See EVENTS_ENDTX
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31 SPIM — Serial peripheral interface master with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E
Reset 0x00000000
Id
E
RW Field
0
D
C
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STARTED
Write '1' to Disable interrupt for STARTED event
See EVENTS_STARTED
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
31.6.4 ENABLE
Address offset: 0x500
Enable SPIM
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable SPIM
Enabled
7
Enable SPIM
Enable or disable SPIM
31.6.5 PSEL.SCK
Address offset: 0x508
Pin select for SCK
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
31.6.6 PSEL.MOSI
Address offset: 0x50C
Pin select for MOSI signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
31.6.7 PSEL.MISO
Address offset: 0x510
Pin select for MISO signal
Page 286
31 SPIM — Serial peripheral interface master with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
31.6.8 FREQUENCY
Address offset: 0x524
SPI frequency
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x04000000
Id
RW Field
A
RW FREQUENCY
0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
K125
0x02000000
125 kbps
K250
0x04000000
250 kbps
K500
0x08000000
500 kbps
M1
0x10000000
1 Mbps
M2
0x20000000
2 Mbps
M4
0x40000000
4 Mbps
M8
0x80000000
8 Mbps
SPI master data rate
31.6.9 RXD.PTR
Address offset: 0x534
Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Data pointer
31.6.10 RXD.MAXCNT
Address offset: 0x538
Maximum number of bytes in receive buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in receive buffer
31.6.11 RXD.AMOUNT
Address offset: 0x53C
Number of bytes transferred in the last transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last transaction
Page 287
31 SPIM — Serial peripheral interface master with
EasyDMA
31.6.12 RXD.LIST
Address offset: 0x540
EasyDMA list type
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
RW LIST
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable EasyDMA list
ArrayList
1
Use array list
List type
31.6.13 TXD.PTR
Address offset: 0x544
Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Data pointer
31.6.14 TXD.MAXCNT
Address offset: 0x548
Maximum number of bytes in transmit buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in transmit buffer
31.6.15 TXD.AMOUNT
Address offset: 0x54C
Number of bytes transferred in the last transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last transaction
31.6.16 TXD.LIST
Address offset: 0x550
EasyDMA list type
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
RW LIST
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable EasyDMA list
ArrayList
1
Use array list
List type
Page 288
31 SPIM — Serial peripheral interface master with
EasyDMA
31.6.17 CONFIG
Address offset: 0x554
Configuration register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW ORDER
B
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
MsbFirst
0
Most significant bit shifted out first
LsbFirst
1
Least significant bit shifted out first
Leading
0
Trailing
1
Bit order
RW CPHA
Serial clock (SCK) phase
Sample on leading edge of clock, shift serial data on trailing
edge
Sample on trailing edge of clock, shift serial data on leading
edge
C
RW CPOL
Serial clock (SCK) polarity
ActiveHigh
0
Active high
ActiveLow
1
Active low
31.6.18 ORC
Address offset: 0x5C0
Over-read character. Character clocked out in case and over-read of the TXD buffer.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ORC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Over-read character. Character clocked out in case and overread of the TXD buffer.
31.7 Electrical specification
31.7.1 SPIM master interface
Symbol
Description
fSPIM
Bit rates for SPIM25
Min.
Typ.
Max.
Units
826
ISPIM,2Mbps
Run current for SPIM, 2 Mbps
50
Mbps
µA
ISPIM,8Mbps
Run current for SPIM, 8 Mbps
50
µA
ISPIM,IDLE
Idle current for SPIM (STARTed, no CSN activity)
1
µA
tSPIM,START,LP
Time from START task to transmission started, low power mode
tSPIM,START,CL
µs
+
tSTART_HFINT
tSPIM,START,CL
Time from START task to transmission started, constant latency
1
µs
mode
31.7.2 Serial Peripheral Interface Master (SPIM) electrical specifications
Symbol
Description
tSPIM,CSCK,8Mbps
SCK period at 8Mbps
125
ns
tSPIM,CSCK,4Mbps
SCK period at 4Mbps
250
ns
tSPIM,CSCK,2Mbps
SCK period at 2Mbps
500
ns
25
26
Min.
Typ.
Max.
Higher bit rates may require GPIOs to be set as High Drive, see GPIO chapter for more details.
The actual maximum data rate depends on the slave's CLK to MISO and MOSI setup and hold timings.
Page 289
Units
31 SPIM — Serial peripheral interface master with
EasyDMA
Symbol
Description
tSPIM,RSCK,LD
SCK rise time, low drivea
Min.
Typ.
Max.
tRF,25pF
tSPIM,RSCK,HD
SCK rise time, high drivea
tHRF,25pF
tSPIM,FSCK,LD
SCK fall time, low drivea
tRF,25pF
tSPIM,FSCK,HD
SCK fall time, high drivea
tSPIM,WHSCK
SCK high timea
tSPIM,WLSCK
SCK low timea
tSPIM,SUMI
MISO to CLK edge setup time
19
tSPIM,HMI
CLK edge to MISO hold time
18
tSPIM,VMO
CLK edge to MOSI valid
tSPIM,HMO
MOSI hold time after CLK edge
Units
tHRF,25pF
(0.5*tCSCK)
– tRSCK
(0.5*tCSCK)
– tFSCK
ns
ns
59
20
ns
tCSCK
SCK (out)
CPOL=0
CPHA=0
tWHSCK
tWLSCK
CPOL=1
CPHA=0
tRSCK
tFSCK
CPOL=0
CPHA=1
CPOL=1
CPHA=1
tSUMI
MISO (in)
tHMI
MSb
tVMO
MOSI (out)
MSb
a
LSb
tHMO
LSb
Figure 72: SPIM timing diagram
At 25pF load, including GPIO pin capacitance, see GPIO spec.
Page 290
ns
32 SPIS — Serial peripheral interface slave with
EasyDMA
32 SPIS — Serial peripheral interface slave with
EasyDMA
SPI slave (SPIS) is implemented with EasyDMA support for ultra low power serial communication from an
external SPI master. EasyDMA in conjunction with hardware-based semaphore mechanisms removes all
real-time requirements associated with controlling the SPI slave from a low priority CPU execution context.
PSEL.CSN
PSEL.MISO
PSEL.MOSI
PSEL.SCK
SPIS
CSN
MOSI
MISO
ACQUIRE
SPI slave tranceiver
RELEASE
Semaphore
ACQUIRED
END
DEF
OVERREAD
OVERFLOW
TXD.PTR
EasyDMA
EasyDMA
RXD.PTR
RAM
TXD
RXD
TXD+1
RXD+1
TXD+2
RXD+2
TXD+n
RXD+n
Figure 73: SPI slave
The SPIS supports SPI modes 0 through 3. The CONFIG register allows setting CPOL and CPHA
appropriately.
Table 69: SPI modes
Mode
SPI_MODE0
SPI_MODE1
SPI_MODE2
SPI_MODE3
Clock polarity
CPOL
0 (Leading)
0 (Leading)
1 (Trailing)
1 (Trailing)
Clock phase
CPHA
0 (Active High)
1 (Active Low)
0 (Active High)
1 (Active Low)
32.1 Shared resources
The SPI slave shares registers and other resources with other peripherals that have the same ID as the SPI
slave. Therefore, you must disable all peripherals that have the same ID as the SPI slave before the SPI
slave can be configured and used.
Disabling a peripheral that has the same ID as the SPI slave will not reset any of the registers that are
shared with the SPI slave. It is important to configure all relevant SPI slave registers explicitly to secure that
it operates correctly.
The Instantiation table in Instantiation on page 24 shows which peripherals have the same ID as the SPI
slave.
32.2 EasyDMA
The SPI slave implements EasyDMA for reading and writing to and from the RAM. The END event indicates
that EasyDMA has finished accessing the buffer in RAM.
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32 SPIS — Serial peripheral interface slave with
EasyDMA
If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result
in a HardFault or RAM corruption. See Memory on page 23 for more information about the different memory
regions.
32.3 SPI slave operation
SPI slave uses two memory pointers, RXD.PTR and TXD.PTR, that point to the RXD buffer (receive
buffer) and TXD buffer (transmit buffer) respectively. Since these buffers are located in RAM, which can be
accessed by both the SPI slave and the CPU, a hardware based semaphore mechanism is implemented to
enable safe sharing.
See Figure 74: SPI transaction when shortcut between END and ACQUIRE is enabled on page 293.
Before the CPU can safely update the RXD.PTR and TXD.PTR pointers it must first acquire the SPI
semaphore. The CPU can acquire the semaphore by triggering the ACQUIRE task and then receiving
the ACQUIRED event. When the CPU has updated the RXD.PTR and TXD.PTR pointers the CPU must
release the semaphore before the SPI slave will be able to acquire it. The CPU releases the semaphore by
triggering the RELEASE task. This is illustrated in Figure 74: SPI transaction when shortcut between END
and ACQUIRE is enabled on page 293. Triggering the RELEASE task when the semaphore is not granted
to the CPU will have no effect.
The semaphore mechanism does not, at any time, prevent the CPU from performing read or write access
to the RXD.PTR register, the TXD.PTR registers, or the RAM that these pointers are pointing to. The
semaphore is only telling when these can be updated by the CPU so that safe sharing is achieved.
The semaphore is by default assigned to the CPU after the SPI slave is enabled. No ACQUIRED event will
be generated for this initial semaphore handover. An ACQUIRED event will be generated immediately if the
ACQUIRE task is triggered while the semaphore is assigned to the CPU.
The SPI slave will try to acquire the semaphore when CSN goes low. If the SPI slave does not manage to
acquire the semaphore at this point, the transaction will be ignored. This means that all incoming data on
MOSI will be discarded, and the DEF (default) character will be clocked out on the MISO line throughout
the whole transaction. This will also be the case even if the semaphore is released by the CPU during the
transaction. In case of a race condition where the CPU and the SPI slave try to acquire the semaphore at
the same time, as illustrated in lifeline item 2 in Figure 74: SPI transaction when shortcut between END and
ACQUIRE is enabled on page 293, the semaphore will be granted to the CPU.
If the SPI slave acquires the semaphore, the transaction will be granted. The incoming data on MOSI will be
stored in the RXD buffer and the data in the TXD buffer will be clocked out on MISO.
When a granted transaction is completed and CSN goes high, the SPI slave will automatically release the
semaphore and generate the END event.
As long as the semaphore is available the SPI slave can be granted multiple transactions one after the
other. If the CPU is not able to reconfigure the TXD.PTR and RXD.PTR between granted transactions, the
same TX data will be clocked out and the RX buffers will be overwritten. To prevent this from happening,
the END_ACQUIRE shortcut can be used. With this shortcut enabled the semaphore will be handed over to
the CPU automatically after the granted transaction has completed, giving the CPU the ability to update the
TXPTR and RXPTR between every granted transaction.
If the CPU tries to acquire the semaphore while it is assigned to the SPI slave, an immediate handover
will not be granted. However, the semaphore will be handed over to the CPU as soon as the SPI slave
has released the semaphore after the granted transaction is completed. If the END_ACQUIRE shortcut is
enabled and the CPU has triggered the ACQUIRE task during a granted transaction, only one ACQUIRE
request will be served following the END event.
The MAXRX register specifies the maximum number of bytes the SPI slave can receive in one granted
transaction. If the SPI slave receives more than MAXRX number of bytes, an OVERFLOW will be indicated
in the STATUS register and the incoming bytes will be discarded.
The MAXTX parameter specifies the maximum number of bytes the SPI slave can transmit in one granted
transaction. If the SPI slave is forced to transmit more than MAXTX number of bytes, an OVERREAD will be
indicated in the STATUS register and the ORC character will be clocked out.
Page 292
32 SPIS — Serial peripheral interface slave with
EasyDMA
The RXD.AMOUNT and TXD.AMOUNT registers are updated when a granted transaction is completed.
The TXD.AMOUNT register indicates how many bytes were read from the TX buffer in the last transaction,
that is, ORC (over-read) characters are not included in this number. Similarly, the RXD.AMOUNT register
indicates how many bytes were written into the RX buffer in the last transaction.
The ENDRX event is generated when the RX buffer has been filled.
Transaction status
SPI master can use the DEF
character to stop the transaction as
soon as possible if the transaction is
not granted.
Ignored
Granted
MOSI
0
1
2
0
1
2
DEF
DEF
DEF
DEF
A
B
C
Free
SPIS
CPU
CPU
4
3
ACQUIRE
ACQUIRE
2
RELEASE
ACQUIRE
1
RELEASE
Lifeline
CPUPENDING
END
&
ACQUIRED
Free
ACQUIRED
CPU
ACQUIRED
Semaphore assignment
0
MISO
SCK
CSN
Ignored
Figure 74: SPI transaction when shortcut between END and ACQUIRE is enabled
32.4 Pin configuration
The CSN, SCK, MOSI, and MISO signals associated with the SPI slave are mapped to physical pins
according to the configuration specified in the PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO
registers respectively. If the CONNECT field of any of these registers is set to Disconnected, the associated
SPI slave signal will not be connected to any physical pins.
The PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and their configurations are only used
as long as the SPI slave is enabled, and retained only as long as the device is in System ON mode, see
POWER — Power supply on page 78 chapter for more information about power modes. When the peripheral
is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field
and PIN_CNF[n] register. PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO must only be configured
when the SPI slave is disabled.
To secure correct behavior in the SPI slave, the pins used by the SPI slave must be configured in the GPIO
peripheral as described in Table 70: GPIO configuration before enabling peripheral on page 294 before
enabling the SPI slave. This is to secure that the pins used by the SPI slave are driven correctly if the SPI
Page 293
32 SPIS — Serial peripheral interface slave with
EasyDMA
slave itself is temporarily disabled, or if the device temporarily enters System OFF. This configuration must
be retained in the GPIO for the selected I/Os as long as the SPI slave is to be recognized by an external SPI
master.
The MISO line is set in high impedance as long as the SPI slave is not selected with CSN.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behavior.
Table 70: GPIO configuration before enabling peripheral
SPI signal
CSN
SCK
MOSI
MISO
SPI pin
As specified in PSEL.CSN
As specified in PSEL.SCK
As specified in PSEL.MOSI
As specified in PSEL.MISO
Direction
Input
Input
Input
Input
Output value
Not applicable
Not applicable
Not applicable
Not applicable
Comment
Emulates that the SPI slave is not selected.
32.5 Registers
Table 71: Instances
Base address
Peripheral
Instance
Description
0x40003000
SPIS
SPIS0
SPI slave 0
0x40004000
SPIS
SPIS1
SPI slave 1
0x40023000
SPIS
SPIS2
SPI slave 2
Configuration
Table 72: Register Overview
Register
Offset
Description
TASKS_ACQUIRE
0x024
Acquire SPI semaphore
TASKS_RELEASE
0x028
Release SPI semaphore, enabling the SPI slave to acquire it
EVENTS_END
0x104
Granted transaction completed
EVENTS_ENDRX
0x110
End of RXD buffer reached
EVENTS_ACQUIRED
0x128
Semaphore acquired
SHORTS
0x200
Shortcut register
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
SEMSTAT
0x400
Semaphore status register
STATUS
0x440
Status from last transaction
ENABLE
0x500
Enable SPI slave
PSELSCK
0x508
Pin select for SCK
Deprecated
PSELMISO
0x50C
Pin select for MISO
Deprecated
PSELMOSI
0x510
Pin select for MOSI
Deprecated
PSELCSN
0x514
Pin select for CSN
Deprecated
PSEL.SCK
0x508
Pin select for SCK
PSEL.MISO
0x50C
Pin select for MISO signal
PSEL.MOSI
0x510
Pin select for MOSI signal
PSEL.CSN
0x514
Pin select for CSN signal
RXDPTR
0x534
RXD data pointer
Deprecated
MAXRX
0x538
Maximum number of bytes in receive buffer
Deprecated
AMOUNTRX
0x53C
Number of bytes received in last granted transaction
Deprecated
RXD.PTR
0x534
RXD data pointer
RXD.MAXCNT
0x538
Maximum number of bytes in receive buffer
RXD.AMOUNT
0x53C
Number of bytes received in last granted transaction
TXDPTR
0x544
TXD data pointer
Deprecated
MAXTX
0x548
Maximum number of bytes in transmit buffer
Deprecated
AMOUNTTX
0x54C
Number of bytes transmitted in last granted transaction
Deprecated
TXD.PTR
0x544
TXD data pointer
TXD.MAXCNT
0x548
Maximum number of bytes in transmit buffer
TXD.AMOUNT
0x54C
Number of bytes transmitted in last granted transaction
CONFIG
0x554
Configuration register
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32 SPIS — Serial peripheral interface slave with
EasyDMA
Register
Offset
Description
DEF
0x55C
Default character. Character clocked out in case of an ignored transaction.
ORC
0x5C0
Over-read character
32.5.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW END_ACQUIRE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between END event and ACQUIRE task
See EVENTS_END and TASKS_ACQUIRE
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
32.5.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
Reset 0x00000000
Id
RW Field
A
RW END
0
Value Id
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for END event
See EVENTS_END
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDRX
Write '1' to Enable interrupt for ENDRX event
See EVENTS_ENDRX
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ACQUIRED
Write '1' to Enable interrupt for ACQUIRED event
See EVENTS_ACQUIRED
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
32.5.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
Reset 0x00000000
Id
RW Field
A
RW END
0
Value Id
Value
Description
Write '1' to Disable interrupt for END event
See EVENTS_END
B
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDRX
Write '1' to Disable interrupt for ENDRX event
Page 295
32 SPIS — Serial peripheral interface slave with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
Reset 0x00000000
Id
RW Field
0
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_ENDRX
C
RW ACQUIRED
Write '1' to Disable interrupt for ACQUIRED event
See EVENTS_ACQUIRED
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
32.5.4 SEMSTAT
Address offset: 0x400
Semaphore status register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000001
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Description
Free
0
Semaphore is free
CPU
1
Semaphore is assigned to CPU
SPIS
2
Semaphore is assigned to SPI slave
CPUPending
3
Semaphore is assigned to SPI but a handover to the CPU is
SEMSTAT
Semaphore status
pending
32.5.5 STATUS
Address offset: 0x440
Status from last transaction
Individual bits are cleared by writing a '1' to the bits that shall be cleared
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
RW Field
A
RW OVERREAD
B
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NotPresent
0
Read: error not present
Present
1
Read: error present
Clear
1
Write: clear error on writing '1'
NotPresent
0
Read: error not present
Present
1
Read: error present
Clear
1
Write: clear error on writing '1'
TX buffer over-read detected, and prevented
RW OVERFLOW
RX buffer overflow detected, and prevented
32.5.6 ENABLE
Address offset: 0x500
Enable SPI slave
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable SPI slave
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32 SPIS — Serial peripheral interface slave with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable SPI slave
Enabled
2
Enable SPI slave
32.5.7 PSELSCK ( Deprecated )
Address offset: 0x508
Pin select for SCK
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PSELSCK
1
Value Id
Disconnected
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
[0..31]
Pin number configuration for SPI SCK signal
0xFFFFFFFF
Disconnect
32.5.8 PSELMISO ( Deprecated )
Address offset: 0x50C
Pin select for MISO
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PSELMISO
1
Value Id
Disconnected
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
[0..31]
Pin number configuration for SPI MISO signal
0xFFFFFFFF
Disconnect
32.5.9 PSELMOSI ( Deprecated )
Address offset: 0x510
Pin select for MOSI
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PSELMOSI
1
Value Id
Disconnected
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
[0..31]
Pin number configuration for SPI MOSI signal
0xFFFFFFFF
Disconnect
32.5.10 PSELCSN ( Deprecated )
Address offset: 0x514
Pin select for CSN
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PSELCSN
1
Value Id
Disconnected
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
[0..31]
Pin number configuration for SPI CSN signal
0xFFFFFFFF
Disconnect
32.5.11 PSEL.SCK
Address offset: 0x508
Pin select for SCK
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32 SPIS — Serial peripheral interface slave with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
32.5.12 PSEL.MISO
Address offset: 0x50C
Pin select for MISO signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
32.5.13 PSEL.MOSI
Address offset: 0x510
Pin select for MOSI signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
32.5.14 PSEL.CSN
Address offset: 0x514
Pin select for CSN signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
32.5.15 RXDPTR ( Deprecated )
Address offset: 0x534
RXD data pointer
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32 SPIS — Serial peripheral interface slave with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW RXDPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
RXD data pointer
32.5.16 MAXRX ( Deprecated )
Address offset: 0x538
Maximum number of bytes in receive buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXRX
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in receive buffer
32.5.17 AMOUNTRX ( Deprecated )
Address offset: 0x53C
Number of bytes received in last granted transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNTRX
Number of bytes received in the last granted transaction
32.5.18 RXD.PTR
Address offset: 0x534
RXD data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
RXD data pointer
32.5.19 RXD.MAXCNT
Address offset: 0x538
Maximum number of bytes in receive buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in receive buffer
32.5.20 RXD.AMOUNT
Address offset: 0x53C
Number of bytes received in last granted transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes received in the last granted transaction
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32 SPIS — Serial peripheral interface slave with
EasyDMA
32.5.21 TXDPTR ( Deprecated )
Address offset: 0x544
TXD data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TXDPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
TXD data pointer
32.5.22 MAXTX ( Deprecated )
Address offset: 0x548
Maximum number of bytes in transmit buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXTX
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in transmit buffer
32.5.23 AMOUNTTX ( Deprecated )
Address offset: 0x54C
Number of bytes transmitted in last granted transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNTTX
Number of bytes transmitted in last granted transaction
32.5.24 TXD.PTR
Address offset: 0x544
TXD data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
TXD data pointer
32.5.25 TXD.MAXCNT
Address offset: 0x548
Maximum number of bytes in transmit buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in transmit buffer
32.5.26 TXD.AMOUNT
Address offset: 0x54C
Number of bytes transmitted in last granted transaction
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32 SPIS — Serial peripheral interface slave with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transmitted in last granted transaction
32.5.27 CONFIG
Address offset: 0x554
Configuration register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW ORDER
B
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
MsbFirst
0
Most significant bit shifted out first
LsbFirst
1
Least significant bit shifted out first
Leading
0
Trailing
1
Bit order
RW CPHA
Serial clock (SCK) phase
Sample on leading edge of clock, shift serial data on trailing
edge
Sample on trailing edge of clock, shift serial data on leading
edge
C
RW CPOL
Serial clock (SCK) polarity
ActiveHigh
0
Active high
ActiveLow
1
Active low
32.5.28 DEF
Address offset: 0x55C
Default character. Character clocked out in case of an ignored transaction.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DEF
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Default character. Character clocked out in case of an ignored
transaction.
32.5.29 ORC
Address offset: 0x5C0
Over-read character
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ORC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Over-read character. Character clocked out after an over-read
of the transmit buffer.
Page 301
32 SPIS — Serial peripheral interface slave with
EasyDMA
32.6 Electrical specification
32.6.1 SPIS slave interface electrical specifications
Symbol
Description
fSPIS
Bit rates for SPIS27
Min.
Typ.
Max.
Units
828
ISPIS,2Mbps
Run current for SPIS, 2 Mbps
45
Mbps
µA
ISPIS,8Mbps
Run current for SPIS, 8 Mbps
45
µA
ISPIS,IDLE
Idle current for SPIS (STARTed, no CSN activity)
1
µA
tSPIS,LP,START
Time from RELEASE task to ready to receive/transmit (CSN
tSPIS,CL,START
µs
active), Low power mode
+
tSTART_HFINT
tSPIS,CL,START
Time from RELEASE task to receive/transmit (CSN active),
0.125
µs
Constant latency mode
32.6.2 Serial Peripheral Interface Slave (SPIS) timing specifications
Symbol
Description
tSPIS,CSCKIN,8Mbps
SCK input period at 8Mbps
Min.
Typ.
125
Max.
Units
ns
tSPIS,CSCKIN,4Mbps
SCK input period at 4Mbps
250
ns
tSPIS,CSCKIN,2Mbps
SCK input period at 2Mbps
500
tSPIS,RFSCKIN
SCK input rise/fall time
tSPIS,WHSCKIN
SCK input high time
30
ns
tSPIS,WLSCKIN
SCK input low time
30
ns
tSPIS,SUCSN,LP
CSN to CLK setup time, Low power mode
tSPIS,SUCSN,CL
ns
ns
30
ns
+
tSTART_HFINT
tSPIS,SUCSN,CL
CSN to CLK setup time, Constant latency mode
1000
tSPIS,HCSN
CLK to CSN hold time
2000
ns
tSPIS,ASO
CSN to MISO drivena
1000
ns
tSPIS,DISSO
CSN to MISO disableda
68
ns
tSPIS,CWH
CSN inactive time
tSPIS,VSO
CLK edge to MISO valid
tSPIS,HSO
MISO hold time after CLK edge
1829
ns
tSPIS,SUSI
MOSI to CLK edge setup time
59
ns
tSPIS,HSI
CLK edge to MOSI hold time
20
ns
ns
300
ns
19
ns
CSN (in)
SCK (in)
tSUCSN
CPOL=0
CPHA=0
tCSCKIN
tWHSCKIN
tWLSCKIN
CPOL=1
CPHA=0
tASO
tHSO
tDISSO
MSb
tSUSI
MOSI (in)
tCWH
tRSCKIN
tFSCKIN
tVSO
MISO (out)
tHCSN
LSb
tHSI
MSb
LSb
Figure 75: SPIS timing diagram
27
28
a
29
Higher bit rates may require GPIOs to be set as High Drive, see GPIO chapter for more details.
The actual maximum data rate depends on the master's CLK to MISO and MOSI setup and hold timings.
At 25pF load, including GPIO capacitance, see GPIO spec.
This is to ensure compatibility to SPI masters sampling MISO on the same edge as MOSI is output
Page 302
32 SPIS — Serial peripheral interface slave with
EasyDMA
Master
Slave
CSN (in)
SCK
CPOL=0
CPHA=0
tSUCSN
tCSCK
tWHSCK
tWLSCK
CPOL=1
CPHA=0
tHCSN
tRSCK
tFSCK
CPOL=0
CPHA=1
CPOL=1
CPHA=1
tSUMI
tASO
MISO (in)
MISO (out)
tHMI
tVSO
tDISSO
MSb
LSb
tVMO
tHSI
tSUSI
MOSI (out)
MOSI (in)
tHSO
tHMO
MSb
LSb
Figure 76: Common SPIM and SPIS timing diagram
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33 TWIM — I C compatible two-wire interface
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33 TWIM — I C compatible two-wire interface master
with EasyDMA
TWI master with EasyDMA (TWIM) is a two-wire half-duplex master which can communicate with multiple
slave devices connected to the same bus
Listed here are the main features for TWIM:
•
•
•
•
2
I C compatible
100 kbps, 250 kbps, or 400 kbps
Support for clock stretching
EasyDMA
The two-wire interface can communicate with a bi-directional wired-AND bus with two lines (SCL, SDA).
The protocol makes it possible to interconnect up to 127 individually addressable devices. TWIM is not
compatible with CBUS.
STOP
RESUME
SUSPEND
STARTTX
STARTRX
The GPIOs used for each two-wire interface line can be chosen from any GPIO on the device and are
independently configurable. This enables great flexibility in device pinout and efficient use of board space
and signal routing.
TWIM
GPIO
RAM
PSEL.SDA
TXD.PTR
buffer[0]
buffer[1]
SDA
Pin
SCL
Pin
TXD+1
EasyDMA
buffer[TXD.MAXCNT-1]
RXD-1
EasyDMA
buffer[0]
TXD buffer
buffer[1]
RXD buffer
PSEL.SCK
RXD.PTR
STOPPED
ERROR
SUSPENDED
LASTTX
LASTRX
TXSTARTED
RXSTARTED
buffer[RXD.MAXCNT-1]
Figure 77: TWI master with EasyDMA
A typical TWI setup consists of one master and one or more slaves. For an example, see Figure 78: A typical
TWI setup comprising one master and three slaves on page 305. This TWIM is only able to operate as a
single master on the TWI bus. Multi-master bus configuration is not supported.
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33 TWIM — I C compatible two-wire interface
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VDD
VDD
TWI master
(TWIM)
SDA
SCL
R
R
TWI slave
(EEPROM)
TWI slave
(Sensor)
TWI slave
Address = b1011001
Address = b1011000
Address = b1011011
SCL
SDA
SCL
SDA
SCL
SDA
Figure 78: A typical TWI setup comprising one master and three slaves
This TWI master supports clock stretching performed by the slaves. The TWI master is started by triggering
the STARTTX or STARTRX tasks, and stopped by triggering the STOP task. The TWI master will generate a
STOPPED event when it has stopped following a STOP task.
The TWI master cannot get stopped while it is suspended, so the STOP task has to be issued after the TWI
master has been resumed.
After the TWI master is started, the STARTTX task or the STARTRX task should not be triggered again
before the TWI master has stopped, i.e. following a LASTRX, LASTTX or STOPPED event.
If a NACK is clocked in from the slave, the TWI master will generate an ERROR event.
33.1 Shared resources
The TWI master shares registers and other resources with other peripherals that have the same ID as the
TWI master. Therefore, you must disable all peripherals that have the same ID as the TWI master before the
TWI master can be configured and used.
Disabling a peripheral that has the same ID as the TWI master will not reset any of the registers that are
shared with the TWI master. It is therefore important to configure all relevant registers explicitly to secure that
the TWI master operates correctly.
The Instantiation table in Instantiation on page 24 shows which peripherals have the same ID as the TWI.
33.2 EasyDMA
The TWI master implements EasyDMA for reading and writing to and from the RAM.
If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result
in a HardFault or RAM corruption. See Memory on page 23 for more information about the different memory
regions.
The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next RX/
TX transmission immediately after having received the RXSTARTED/TXSTARTED event.
The STOPPED event indicates that EasyDMA has finished accessing the buffer in RAM.
33.2.1 EasyDMA list
EasyDMA supports one list type.
The supported list type is:
•
Array list
EasyDMA array list
The EasyDMA array list can be represented by the data structure ArrayList_type.
For illustration, see the code example below. This data structure includes only a buffer with size equal
to Channel.MAXCNT. EasyDMA will use the Channel.MAXCNT register to determine when the buffer
is full. Replace 'Channel' by the specific data channel you want to use, for instance 'NRF_SPIM->RXD',
'NRF_SPIM->TXD', 'NRF_TWIM->RXD', etc.
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33 TWIM — I C compatible two-wire interface
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The Channel.MAXCNT register cannot be specified larger than the actual size of the buffer. If
Channel.MAXCNT is specified larger than the size of the buffer, the EasyDMA channel may overflow the
buffer.
This array list does not provide a mechanism to explicitly specify where the next item in the list is located.
Instead, it assumes that the list is organized as a linear array where items are located one after the other in
RAM.
#define BUFFER_SIZE
4
typedef struct ArrayList
{
uint8_t buffer[BUFFER_SIZE];
} ArrayList_type;
ArrayList_type MyArrayList[3];
//replace 'Channel' below by the specific data channel you want to use,
//
for instance 'NRF_SPIM->RXD', 'NRF_TWIM->RXD', etc.
Channel.MAXCNT = BUFFER_SIZE;
Channel.PTR = &MyArrayList;
Channel.PTR = &MyArrayList
Note: addresses are
assuming that
sizeof(buffer[n]) is one byte
0x20000000 : MyArrayList[0]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000004 : MyArrayList[1]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000008 : MyArrayList[2]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
Figure 79: EasyDMA array list
33.3 Master write sequence
A TWI master write sequence is started by triggering the STARTTX task. After the STARTTX task has
been triggered, the TWI master will generate a start condition on the TWI bus, followed by clocking out the
address and the READ/WRITE bit set to 0 (WRITE=0, READ=1).
The address must match the address of the slave device that the master wants to write to. The READ/
WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK=1) generated by the slave.
After receiving the ACK bit, the TWI master will clock out the data bytes found in the transmit buffer located
in RAM at the address specified in the TXD.PTR register. Each byte clocked out from the master will be
followed by an ACK/NACK bit clocked in from the slave.
A typical TWI master write sequence is illustrated in Figure 80: TWI master writing data to a slave on page
307. Occurrence 2 in the figure illustrates clock stretching performed by the TWI master following a
SUSPEND task.
A SUSPENDED event indicates that the SUSPEND task has taken effect; this event can be used to
synchronize the software.
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33 TWIM — I C compatible two-wire interface
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STOPPED
4
STOP
RESUME
3
SUSPEND
STARTTX
TXD.MAXCNT = N+1
LASTTX
SUSPENDED
TWI
CPU Lifeline
2
N
ACK
1
N-1
STOP
2
ACK
Stretch
ACK
1
ACK
0
ACK
ACK
WRITE
START
ADDR
Figure 80: TWI master writing data to a slave
The TWI master will generate a LASTTX event when it starts to transmit the last byte, this is illustrated in
Figure 80: TWI master writing data to a slave on page 307
The TWI master is stopped by triggering the STOP task, this task should be triggered during the
transmission of the last byte to secure that the TWI will stop as fast as possible after sending the last byte. It
is safe to use the shortcut between LASTTX and STOP to accomplish this.
Note that the TWI master does not stop by itself when the whole RAM buffer has been sent, or when an error
occurs. The STOP task must be issued, through the use of a local or PPI shortcut, or in software as part of
the error handler.
The TWI master cannot get stopped while it is suspended, so the STOP task has to be issued after the TWI
master has been resumed.
33.4 Master read sequence
A TWI master read sequence is started by triggering the STARTRX task. After the STARTRX task has been
triggered the TWI master will generate a start condition on the TWI bus, followed by clocking out the address
and the READ/WRITE bit set to 1 (WRITE = 0, READ = 1). The address must match the address of the slave
device that the master wants to read from. The READ/WRITE bit is followed by an ACK/NACK bit (ACK=0 or
NACK = 1) generated by the slave.
After having sent the ACK bit the TWI slave will send data to the master using the clock generated by the
master.
Data received will be stored in RAM at the address specified in the RXD.PTR register. The TWI master will
generate an ACK after all but the last byte received from the slave. The TWI master will generate a NACK
after the last byte received to indicate that the read sequence shall stop.
A typical TWI master read sequence is illustrated in Figure 81: The TWI master reading data from a slave on
page 308. Occurrence 2 in the figure illustrates clock stretching performed by the TWI master following a
SUSPEND task.
A SUSPENDED event indicates that the SUSPEND task has taken effect; this event can be used to
synchronize the software.
The TWI master will generate a LASTRX event when it is ready to receive the last byte, this is illustrated
in Figure 81: The TWI master reading data from a slave on page 308. If RXD.MAXCNT > 1 the LASTRX
event is generated after sending the ACK of the previously received byte. If RXD.MAXCNT = 1 the LASTRX
event is generated after receiving the ACK following the address and READ bit.
The TWI master is stopped by triggering the STOP task, this task must be triggered before the NACK bit
is supposed to be transmitted. The STOP task can be triggered at any time during the reception of the last
byte. It is safe to use the shortcut between LASTRX and STOP to accomplish this.
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33 TWIM — I C compatible two-wire interface
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Note that the TWI master does not stop by itself when the RAM buffer is full, or when an error occurs. The
STOP task must be issued, through the use of a local or PPI shortcut, or in software as part of the error
handler.
The TWI master cannot get stopped while it is suspended, so the STOP task has to be issued after the TWI
master has been resumed.
LASTRX
3
4
STOP
SUSPEND
RESUME
2
STARTRX
RXD.MAXCNT = M+1
CPU Lifeline
1
M
STOPPED
M-1
SUSPENDED
TWI
2
STOP
NACK
Stretch
ACK
1
ACK
ACK
0
ACK
ACK
READ
START
ADDR
Figure 81: The TWI master reading data from a slave
33.5 Master repeated start sequence
A typical repeated start sequence is one in which the TWI master writes two bytes to the slave followed by
reading four bytes from the slave. This example uses shortcuts to perform the simplest type of repeated start
sequence, i.e. one write followed by one read. The same approach can be used to perform a repeated start
sequence where the sequence is read followed by write.
STOPPED
LASTRX
LASTTX
STOP
STARTRX
2
STARTTX
TXD.MAXCNT = 2
RXD.MAXCNT = 4
CPU Lifeline
STOP
1
3
NACK
2
ACK
1
ACK
0
ACK
ADDR
ACK
READ
1
RESTART
ACK
0
ACK
ADDR
ACK
WRITE
START
CPU Lifeline
The figure Figure 82: A repeated start sequence, where the TWI master writes two bytes followed by reading
4 bytes from the slave on page 308 illustrates this:
Figure 82: A repeated start sequence, where the TWI master writes two bytes followed by reading 4
bytes from the slave
If a more complex repeated start sequence is needed and the TWI firmware drive is serviced in a low priority
interrupt it may be necessary to use the SUSPEND task and SUSPENDED event to guarantee that the
correct tasks are generated at the correct time. This is illustrated in Figure 83: A double repeated start
sequence using the SUSPEND task to secure safe operation in low priority interrupts on page 309.
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33 TWIM — I C compatible two-wire interface
master with EasyDMA
STOPPED
LASTTX
5
STOP
STARTTX
RESUME
STARTRX
TXD.MAXCNT = 2
SUSPEND
RXD.MAXCNT = 1
STARTTX
TXD.MAXCNT = 1
LASTRX
SUSPENDED
LASTTX
TWI
CPU Lifeline
4
ACK
3
1
STOP
0
ACK
2
ADDR
ACK
WRITE
1
0
NACK
ADDR
RESTART
Stretch
ACK
READ
0
RESTART
ACK
ACK
WRITE
START
ADDR
Figure 83: A double repeated start sequence using the SUSPEND task to secure safe operation in low
priority interrupts
33.6 Low power
When putting the system in low power and the peripheral is not needed, lowest possible power consumption
is achieved by stopping, and then disabling the peripheral.
The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent,
software shall wait until the STOPPED event was received as a response before disabling the peripheral
through the ENABLE register.
33.7 Master mode pin configuration
The SCL and SDA signals associated with the TWI master are mapped to physical pins according to the
configuration specified in the PSEL.SCL and PSEL.SDA registers respectively.
The PSEL.SCL and PSEL.SDA registers and their configurations are only used as long as the TWI master
is enabled, and retained only as long as the device is in ON mode. When the peripheral is disabled, the pins
will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n]
register. PSEL.SCL, PSEL.SDA must only be configured when the TWI master is disabled.
To secure correct signal levels on the pins used by the TWI master when the system is in OFF mode, and
when the TWI master is disabled, these pins must be configured in the GPIO peripheral as described in
Table 73: GPIO configuration before enabling peripheral on page 309.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behavior.
Table 73: GPIO configuration before enabling peripheral
TWI master signal
SCL
SDA
TWI master pin
As specified in PSEL.SCL
As specified in PSEL.SDA
Direction
Input
Input
Output value
Not applicable
Not applicable
33.8 Registers
Table 74: Instances
Base address
Peripheral
Instance
Description
0x40003000
TWIM
TWIM0
Two-wire interface master 0
0x40004000
TWIM
TWIM1
Two-wire interface master 1
Page 309
Configuration
Drive strength
S0D1
S0D1
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33 TWIM — I C compatible two-wire interface
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Table 75: Register Overview
Register
Offset
Description
TASKS_STARTRX
0x000
Start TWI receive sequence
TASKS_STARTTX
0x008
Start TWI transmit sequence
TASKS_STOP
0x014
Stop TWI transaction. Must be issued while the TWI master is not suspended.
TASKS_SUSPEND
0x01C
Suspend TWI transaction
TASKS_RESUME
0x020
Resume TWI transaction
EVENTS_STOPPED
0x104
TWI stopped
EVENTS_ERROR
0x124
TWI error
EVENTS_SUSPENDED
0x148
Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
EVENTS_RXSTARTED
0x14C
Receive sequence started
EVENTS_TXSTARTED
0x150
Transmit sequence started
EVENTS_LASTRX
0x15C
Byte boundary, starting to receive the last byte
EVENTS_LASTTX
0x160
Byte boundary, starting to transmit the last byte
SHORTS
0x200
Shortcut register
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ERRORSRC
0x4C4
Error source
ENABLE
0x500
Enable TWIM
PSEL.SCL
0x508
Pin select for SCL signal
PSEL.SDA
0x50C
Pin select for SDA signal
FREQUENCY
0x524
TWI frequency
RXD.PTR
0x534
Data pointer
RXD.MAXCNT
0x538
Maximum number of bytes in receive buffer
RXD.AMOUNT
0x53C
Number of bytes transferred in the last transaction
RXD.LIST
0x540
EasyDMA list type
TXD.PTR
0x544
Data pointer
TXD.MAXCNT
0x548
Maximum number of bytes in transmit buffer
TXD.AMOUNT
0x54C
Number of bytes transferred in the last transaction
TXD.LIST
0x550
EasyDMA list type
ADDRESS
0x588
Address used in the TWI transfer
33.8.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F
Reset 0x00000000
Id
RW Field
A
RW LASTTX_STARTRX
0
Value Id
D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between LASTTX event and STARTRX task
See EVENTS_LASTTX and TASKS_STARTRX
B
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW LASTTX_SUSPEND
Shortcut between LASTTX event and SUSPEND task
See EVENTS_LASTTX and TASKS_SUSPEND
C
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW LASTTX_STOP
Shortcut between LASTTX event and STOP task
See EVENTS_LASTTX and TASKS_STOP
D
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW LASTRX_STARTTX
Shortcut between LASTRX event and STARTTX task
See EVENTS_LASTRX and TASKS_STARTTX
Disabled
0
Disable shortcut
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33 TWIM — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F
Reset 0x00000000
Id
F
RW Field
0
D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Enable shortcut
RW LASTRX_STOP
Shortcut between LASTRX event and STOP task
See EVENTS_LASTRX and TASKS_STOP
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
33.8.2 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
J
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
I
H G F
D
Value
Description
Enable or disable interrupt for STOPPED event
See EVENTS_STOPPED
D
Disabled
0
Disable
Enabled
1
Enable
RW ERROR
Enable or disable interrupt for ERROR event
See EVENTS_ERROR
F
Disabled
0
Disable
Enabled
1
Enable
RW SUSPENDED
Enable or disable interrupt for SUSPENDED event
See EVENTS_SUSPENDED
G
Disabled
0
Disable
Enabled
1
Enable
RW RXSTARTED
Enable or disable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
H
Disabled
0
Disable
Enabled
1
Enable
RW TXSTARTED
Enable or disable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
I
Disabled
0
Disable
Enabled
1
Enable
RW LASTRX
Enable or disable interrupt for LASTRX event
See EVENTS_LASTRX
J
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Disabled
0
Disable
Enabled
1
Enable
RW LASTTX
Enable or disable interrupt for LASTTX event
See EVENTS_LASTTX
Disabled
0
Disable
Enabled
1
Enable
33.8.3 INTENSET
Address offset: 0x304
Enable interrupt
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33 TWIM — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
J
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
I
H G F
D
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for STOPPED event
See EVENTS_STOPPED
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Enable interrupt for ERROR event
See EVENTS_ERROR
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SUSPENDED
Write '1' to Enable interrupt for SUSPENDED event
See EVENTS_SUSPENDED
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXSTARTED
Write '1' to Enable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTARTED
Write '1' to Enable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
I
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW LASTRX
Write '1' to Enable interrupt for LASTRX event
See EVENTS_LASTRX
J
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW LASTTX
Write '1' to Enable interrupt for LASTTX event
See EVENTS_LASTTX
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
33.8.4 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
J
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
I
H G F
Value
Description
Write '1' to Disable interrupt for STOPPED event
See EVENTS_STOPPED
D
D
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Disable interrupt for ERROR event
See EVENTS_ERROR
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33 TWIM — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
J
Reset 0x00000000
Id
F
RW Field
0
I
H G F
D
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SUSPENDED
Write '1' to Disable interrupt for SUSPENDED event
See EVENTS_SUSPENDED
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXSTARTED
Write '1' to Disable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTARTED
Write '1' to Disable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
I
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW LASTRX
Write '1' to Disable interrupt for LASTRX event
See EVENTS_LASTRX
J
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW LASTTX
Write '1' to Disable interrupt for LASTTX event
See EVENTS_LASTTX
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
33.8.5 ERRORSRC
Address offset: 0x4C4
Error source
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
RW Field
A
RW ANACK
B
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NotReceived
0
Error did not occur
Received
1
Error occurred
NotReceived
0
Error did not occur
Received
1
Error occurred
NACK received after sending the address (write '1' to clear)
RW DNACK
NACK received after sending a data byte (write '1' to clear)
33.8.6 ENABLE
Address offset: 0x500
Enable TWIM
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33 TWIM — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable TWIM
Enabled
6
Enable TWIM
Enable or disable TWIM
33.8.7 PSEL.SCL
Address offset: 0x508
Pin select for SCL signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
33.8.8 PSEL.SDA
Address offset: 0x50C
Pin select for SDA signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
33.8.9 FREQUENCY
Address offset: 0x524
TWI frequency
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x04000000
Id
RW Field
A
RW FREQUENCY
0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
K100
0x01980000
100 kbps
K250
0x04000000
250 kbps
K400
0x06400000
400 kbps
TWI master clock frequency
33.8.10 RXD.PTR
Address offset: 0x534
Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Data pointer
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33 TWIM — I C compatible two-wire interface
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33.8.11 RXD.MAXCNT
Address offset: 0x538
Maximum number of bytes in receive buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[1..255]
Maximum number of bytes in receive buffer
33.8.12 RXD.AMOUNT
Address offset: 0x53C
Number of bytes transferred in the last transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last transaction. In case of
NACK error, includes the NACK'ed byte.
33.8.13 RXD.LIST
Address offset: 0x540
EasyDMA list type
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
RW LIST
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable EasyDMA list
ArrayList
1
Use array list
List type
33.8.14 TXD.PTR
Address offset: 0x544
Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Data pointer
33.8.15 TXD.MAXCNT
Address offset: 0x548
Maximum number of bytes in transmit buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[1..255]
Maximum number of bytes in transmit buffer
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33 TWIM — I C compatible two-wire interface
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33.8.16 TXD.AMOUNT
Address offset: 0x54C
Number of bytes transferred in the last transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last transaction. In case of
NACK error, includes the NACK'ed byte.
33.8.17 TXD.LIST
Address offset: 0x550
EasyDMA list type
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
RW LIST
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable EasyDMA list
ArrayList
1
Use array list
List type
33.8.18 ADDRESS
Address offset: 0x588
Address used in the TWI transfer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ADDRESS
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Address used in the TWI transfer
33.9 Electrical specification
33.9.1 TWIM interface electrical specifications
Symbol
Description
Min.
fTWIM
Bit rates for TWIM30
100
Typ.
Max.
Units
400
ITWIM,100kbps
Run current for TWIM, 100 kbps
50
kbps
µA
ITWIM,400kbps
Run current for TWIM, 400 kbps
50
µA
tTWIM,START,LP
Time from STARTRX/STARTTX task to transmission started, Low
tTWIM,START,CL
µs
power mode
+
tSTART_HFINT
tTWIM,START,CL
Time from STARTRX/STARTTX task to transmission started,
1.5
µs
Constant latency mode
33.9.2 Two Wire Interface Master (TWIM) timing specifications
Symbol
Description
fTWIM,SCL,100kbps
SCL clock frequency, 100 kbps
100
kHz
fTWIM,SCL,250kbps
SCL clock frequency, 250 kbps
250
kHz
fTWIM,SCL,400kbps
SCL clock frequency, 400 kbps
400
kHz
30
Min.
Typ.
Max.
Units
Higher bit rates or stronger pull-ups may require GPIOs to be set as High Drive, see GPIO chapter for more
details.
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33 TWIM — I C compatible two-wire interface
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Symbol
Description
Min.
tTWIM,SU_DAT
Data setup time before positive edge on SCL – all modes
300
Typ.
Max.
Units
ns
tTWIM,HD_DAT
Data hold time after negative edge on SCL – all modes
500
ns
tTWIM,HD_STA,100kbps
TWIM master hold time for START and repeated START
10000
ns
4000
ns
2500
ns
5000
ns
2000
ns
1250
ns
5800
ns
2700
ns
2100
ns
condition, 100 kbps
tTWIM,HD_STA,250kbps
TWIM master hold time for START and repeated START
condition, 250kbps
tTWIM,HD_STA,400kbps
TWIM master hold time for START and repeated START
condition, 400 kbps
tTWIM,SU_STO,100kbps
TWIM master setup time from SCL high to STOP condition, 100
kbps
tTWIM,SU_STO,250kbps
TWIM master setup time from SCL high to STOP condition, 250
kbps
tTWIM,SU_STO,400kbps
TWIM master setup time from SCL high to STOP condition, 400
kbps
tTWIM,BUF,100kbps
TWIM master bus free time between STOP and START
conditions, 100 kbps
tTWIM,BUF,250kbps
TWIM master bus free time between STOP and START
conditions, 250 kbps
tTWIM,BUF,400kbps
TWIM master bus free time between STOP and START
conditions, 400 kbps
Figure 84: TWIM timing diagram, 1 byte transaction
R [kΩ]
30
100 kbps
25
400 kbps
20
15
13
10
5
0
0
100
200
300
400
500
cap [pF]
Figure 85: Recommended TWIM pullup value vs. line capacitance
•
•
The I2C specification allows a line capacitance of 400 pF at most.
The nRF52832 internal pullup has a fixed value of typ. 13 kOhm, see RPU in the GPIO chapter.
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34 TWIS — I C compatible two-wire interface
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34 TWIS — I C compatible two-wire interface slave with
EasyDMA
2
TWI slave with EasyDMA (TWIS) is compatible with I C operating at 100 kHz and 400 kHz. The TWI
transmitter and receiver implement EasyDMA.
PSELSDA
PSELSCK
PSELSDA
PREPARETX
PREPARERX
RXD
(signal)
STOPPED
TXD
(signal)
SUSPEND
RESUME
EasyDMA
RXD.PTR
EasyDMA
TXD.PTR
WRITE
READ
RAM
RXD
TXD
RXD+1
TXD+1
RXD+2
TXD+2
RXD+n
TXD+n
Figure 86: TWI slave with EasyDMA
A typical TWI setup consists of one master and one or more slaves. For an example, see Figure 87: A typical
TWI setup comprising one master and three slaves on page 318. TWIS is only able to operate with a single
master on the TWI bus.
VDD
VDD
TWI master
SDA
SCL
R
R
TWI slave
(EEPROM)
TWI slave
(Sensor)
Address = b1011001
Address = b1011000
SCL
SDA
SCL
SDA
TWI slave
(TWIS)
Address = b1011011
SCL
SDA
Figure 87: A typical TWI setup comprising one master and three slaves
The TWI slave state machine is illustrated in Figure 88: TWI slave state machine on page 319 and Table
76: TWI slave state machine symbols on page 319 is explaining the different symbols used in the state
machine.
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34 TWIS — I C compatible two-wire interface
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PREPARETX
PREPARERX
ENABLE
/ STOPPED
Unprepare TX,
Unprepare RX
IDLE
STOP
[ READ && (TX prepared) ]
[ WRITE && (RX prepared) ]
Restart sequence
Stop sequence
TX
RX
entry / Unprepare TX
entry / Unprepare RX
entry / TXSTARTED
entry / RXSTARTED
Figure 88: TWI slave state machine
Table 76: TWI slave state machine symbols
Symbol
ENABLE
PREPARETX
STOP
PREPARERX
STOPPED
RXSTARTED
TXSTARTED
TX prepared
RX prepared
Unprepare TX
Unprepare RX
Stop sequence
Restart sequence
Type
Register
Task
Task
Task
Event
Event
Event
Internal
Internal
Internal
Internal
TWI protocol
TWI protocol
Description
The TWI slave has been enabled via the ENABLE register
The TASKS_PREPARETX task has been triggered
The TASKS_STOP task has been triggered
The TASKS_PREPARERX task has been triggered
The EVENTS_STOPPED event was generated
The EVENTS_RXSTARTED event was generated
The EVENTS_TXSTARTED event was generated
Internal flag indicating that a TASKS_PREPARETX task has been triggered. This flag is not visible to the user.
Internal flag indicating that a TASKS_PREPARERX task has been triggered. This flag is not visible to the user.
Clears the internal 'TX prepared' flag until next TASKS_PREPARETX task.
Clears the internal 'RX prepared' flag until next TASKS_PREPARERX task.
A TWI stop sequence was detected
A TWI restart sequence was detected
The TWI slave supports clock stretching performed by the master.
The TWI slave operates in a low power mode while waiting for a TWI master to initiate a transfer. As long as
the TWI slave is not addressed, it will remain in this low power mode.
To secure correct behaviour of the TWI slave, PSEL.SCL, PSEL.SDA, CONFIG and the ADDRESS[n]
registers, must be configured prior to enabling the TWI slave through the ENABLE register. Similarly,
changing these settings must be performed while the TWI slave is disabled. Failing to do so may result in
unpredictable behaviour.
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34 TWIS — I C compatible two-wire interface
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34.1 Shared resources
The TWI slave shares registers and other resources with other peripherals that have the same ID as the TWI
slave.
Therefore, you must disable all peripherals that have the same ID as the TWI slave before the TWI slave can
be configured and used. Disabling a peripheral that has the same ID as the TWI slave will not reset any of
the registers that are shared with the TWI slave. It is therefore important to configure all relevant registers
explicitly to secure that the TWI slave operates correctly.
The Instantiation table in Instantiation on page 24 shows which peripherals have the same ID as the TWI
slave.
34.2 EasyDMA
The TWI slave implements EasyDMA for reading and writing to and from the RAM.
The STOPPED event indicates that EasyDMA has finished accessing the buffer in RAM.
If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result
in a HardFault or RAM corruption. See Memory on page 23 for more information about the different memory
regions.
34.3 TWI slave responding to a read command
Before the TWI slave can respond to a read command the TWI slave must be configured correctly and
enabled via the ENABLE register. When enabled the TWI slave will be in its IDLE state where it will consume
IIDLE .
A read command is started when the TWI master generates a start condition on the TWI bus, followed by
clocking out the address and the READ/WRITE bit set to 1 (WRITE=0, READ=1). The READ/WRITE bit is
followed by an ACK/NACK bit (ACK=0 or NACK=1) response from the TWI slave.
The TWI slave is able to listen for up to two addresses at the same time. Which addresses to listen for is
configured in the ADDRESS registers and the CONFIG register.
The TWI slave will only acknowledge (ACK) the read command if the address presented by the master
matches one of the addresses the slave is configured to listen for. The TWI slave will generate a READ
event when it acknowledges the read command.
The TWI slave is only able to detect a read command from the IDLE state.
The TWI slave will set an internal 'TX prepared' flag when the PREPARETX task is triggered.
When the read command is received the TWI slave will enter the TX state if the internal 'TX prepared' flag is
set.
If the internal 'TX prepared' flag is not set when the read command is received, the TWI slave will stretch the
master's clock until the PREPARETX task is triggered and the internal 'TX prepared' flag is set.
The TWI slave will generate the TXSTARTED event and clear the 'TX prepared' flag ('unprepare TX') when
it enters the TX state. In this state the TWI slave will send the data bytes found in the transmit buffer to the
master using the master's clock. The TWI slave will consume ITX in this mode.
The TWI slave will go back to the IDLE state if the TWI slave receives a restart command when it is in the TX
state.
The TWI slave is stopped when it receives the stop condition from the TWI master. A STOPPED event will
be generated when the transaction has stopped. The TWI slave will clear the 'TX prepared' flag ('unprepare
TX') and go back to the IDLE state when it has stopped.
The transmit buffer is located in RAM at the address specified in the TXD.PTR register. The TWI slave will
only be able to send TXD.MAXCNT bytes from the transmit buffer for each transaction. If the TWI master
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34 TWIS — I C compatible two-wire interface
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forces the slave to send more than TXD.MAXCNT bytes, the slave will send the byte specified in the ORC
register to the master instead. If this happens, an ERROR event will be generated.
The EasyDMA configuration registers, see TXD.PTR etc., are latched when the TXSTARTED event is
generated.
The TWI slave can be forced to stop by triggering the STOP task. A STOPPED event will be generated when
the TWI slave has stopped. The TWI slave will clear the 'TX prepared' flag and go back to the IDLE state
when it has stopped, see also Terminating an ongoing TWI transaction on page 323.
Each byte sent from the slave will be followed by an ACK/NACK bit sent from the master. The TWI master
will generate a NACK following the last byte that it wants to receive to tell the slave to release the bus so
that the TWI master can generate the stop condition. The TXD.AMOUNT register can be queried after a
transaction to see how many bytes were sent.
A typical TWI slave read command response is illustrated in Figure 89: The TWI slave responding to a read
command on page 321. Occurrence 2 in the figure illustrates clock stretching performed by the TWI slave
following a SUSPEND task.
STOPPED
READ
3
4
SUSPEND
RESUME
2
PREPARETX
TXD.MAXCNT >= N+1
TXD.PTR = 0x20000000
TXSTARTED
TWI
CPU Lifeline
N
STOP
N-1
NACK
2
ACK
Stretch
ACK
1
ACK
1
0
ACK
ACK
READ
START
ADDR
Figure 89: The TWI slave responding to a read command
34.4 TWI slave responding to a write command
Before the TWI slave can respond to a write command the TWI slave must be configured correctly and
enabled via the ENABLE register. When enabled the TWI slave will be in its IDLE state where it will consume
IIDLE.
A write command is started when the TWI master generates a start condition on the TWI bus, followed by
clocking out the address and the READ/WRITE bit set to 0 (WRITE=0, READ=1). The READ/WRITE bit is
followed by an ACK/NACK bit (ACK=0 or NACK=1) response from the slave.
The TWI slave is able to listen for up to two addresses at the same time. Which addresses to listen for is
configured in the ADDRESS registers and the CONFIG register.
The TWI slave will only acknowledge (ACK) the write command if the address presented by the master
matches one of the addresses the slave is configured to listen for. The TWI slave will generate a WRITE
event if it acknowledges the write command.
The TWI slave is only able to detect a write command from the IDLE state.
The TWI slave will set an internal 'RX prepared' flag when the PREPARERX task is triggered.
When the write command is received the TWI slave will enter the RX state if the internal 'RX prepared' flag is
set.
If the internal 'RX prepared' flag is not set when the write command is received, the TWI slave will stretch the
master's clock until the PREPARERX task is triggered and the internal 'RX prepared' flag is set.
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34 TWIS — I C compatible two-wire interface
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The TWI slave will generate the RXSTARTED event and clear the internal 'RX prepared' flag ('unprepare
RX') when it enters the RX state. In this state the TWI slave will be able to receive the bytes sent by the TWI
master. The TWI slave will consume IRX in this mode.
The TWI slave will go back to the IDLE state if the TWI slave receives a restart command when it is in the
RX state.
The TWI slave is stopped when it receives the stop condition from the TWI master. A STOPPED event will
be generated when the transaction has stopped. The TWI slave will clear the internal 'RX prepared' flag
('unprepare RX') and go back to the IDLE state when it has stopped.
The receive buffer is located in RAM at the address specified in the TXD.PTR register. The TWI slave will
only be able to receive as many bytes as specified in the RXD.MAXCNT register. If the TWI master tries to
send more bytes to the slave than the slave is able to receive,these bytes will be discarded and the bytes will
be NACKed by the slave. If this happens, an ERROR event will be generated.
The EasyDMA configuration registers, see RXD.PTR etc., are latched when the RXSTARTED event is
generated.
The TWI slave can be forced to stop by triggering the STOP task. A STOPPED event will be generated when
the TWI slave has stopped. The TWI slave will clear the internal 'RX prepared' flag and go back to the IDLE
state when it has stopped, see also Terminating an ongoing TWI transaction on page 323.
The TWI slave will generate an ACK after every byte received from the master. The RXD.AMOUNT register
can be queried after a transaction to see how many bytes were received.
A typical TWI slave write command response is illustrated in Figure 90: The TWI slave responding to a write
command on page 322. Occurrence 2 in the figure illustrates clock stretching performed by the TWI slave
following a SUSPEND task.
M-1
M
STOPPED
2
3
SUSPEND
RESUME
WRITE
PREPARERX
RXD.MAXCNT >= M+1
RXD.PTR = 0x20000000
RXSTARTED
TWI
CPU Lifeline
2
STOP
ACK
Stretch
ACK
1
ACK
ACK
1
0
ACK
ACK
WRITE
START
ADDR
4
Figure 90: The TWI slave responding to a write command
34.5 Master repeated start sequence
An example of a repeated start sequence is one in which the TWI master writes two bytes to the slave
followed by reading four bytes from the slave.
This is illustrated in Figure 91: A repeated start sequence, where the TWI master writes two bytes followed
by reading four bytes from the slave on page 323.
It is here assumed that the receiver does not know in advance what the master wants to read, and that
this information is provided in the first two bytes received in the write part of the repeated start sequence.
To guarantee that the CPU is able to process the received data before the TWI slave starts to reply to the
read command, the SUSPEND task is triggered via a shortcut from the READ event generated when the
read command is received. When the CPU has processed the incoming data and prepared the correct data
response, the CPU will resume the transaction by triggering the RESUME task.
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34 TWIS — I C compatible two-wire interface
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STOPPED
3
RESUME
TXD.MAXCNT = 4
PREPARETX
SUSPEND
TXD.PTR = 0x20000010
PREPARERX
RXD.MAXCNT = 2
RXD.PTR = 0x20000000
TXSTARTED
READ
WRITE
RXSTARTED
TWI
CPU Lifeline
STOP
3
NACK
2
2
ACK
1
1
ACK
0
ACK
ADDR
ACK
READ
1
RESTART
ACK
0
ACK
ACK
WRITE
START
ADDR
Figure 91: A repeated start sequence, where the TWI master writes two bytes followed by reading
four bytes from the slave
34.6 Terminating an ongoing TWI transaction
In some situations, e.g. if the external TWI master is not responding correctly, it may be required to terminate
an ongoing transaction.
This can be achieved by triggering the STOP task. In this situation a STOPPED event will be generated
when the TWI has stopped independent of whether or not a STOP condition has been generated on the TWI
bus. The TWI slave will release the bus when it has stopped and go back to its IDLE state.
34.7 Low power
When putting the system in low power and the peripheral is not needed, lowest possible power consumption
is achieved by stopping, and then disabling the peripheral.
The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent,
software shall wait until the STOPPED event was received as a response before disabling the peripheral
through the ENABLE register.
34.8 Slave mode pin configuration
The SCL and SDA signals associated with the TWI slave are mapped to physical pins according to the
configuration specified in the PSEL.SCL and PSEL.SDA registers respectively.
The PSEL.SCL and PSEL.SDA registers and their configurations are only used as long as the TWI slave is
enabled, and retained only as long as the device is in ON mode. When the peripheral is disabled, the pins
will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n]
register. PSEL.SCL and PSEL.SDA must only be configured when the TWI slave is disabled.
To secure correct signal levels on the pins used by the TWI slave when the system is in OFF mode, and
when the TWI slave is disabled, these pins must be configured in the GPIO peripheral as described in Table
77: GPIO configuration before enabling peripheral on page 323.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behavior.
Table 77: GPIO configuration before enabling peripheral
TWI slave signal
SCL
SDA
TWI slave pin
As specified in PSEL.SCL
As specified in PSEL.SDA
Direction
Input
Input
Page 323
Output value
Not applicable
Not applicable
Drive strength
S0D1
S0D1
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34 TWIS — I C compatible two-wire interface
slave with EasyDMA
34.9 Registers
Table 78: Instances
Base address
Peripheral
Instance
Description
0x40003000
TWIS
TWIS0
Two-wire interface slave 0
Configuration
0x40004000
TWIS
TWIS1
Two-wire interface slave 1
Table 79: Register Overview
Register
Offset
Description
TASKS_STOP
0x014
Stop TWI transaction
TASKS_SUSPEND
0x01C
Suspend TWI transaction
TASKS_RESUME
0x020
Resume TWI transaction
TASKS_PREPARERX
0x030
Prepare the TWI slave to respond to a write command
TASKS_PREPARETX
0x034
Prepare the TWI slave to respond to a read command
EVENTS_STOPPED
0x104
TWI stopped
EVENTS_ERROR
0x124
TWI error
EVENTS_RXSTARTED
0x14C
Receive sequence started
EVENTS_TXSTARTED
0x150
Transmit sequence started
EVENTS_WRITE
0x164
Write command received
EVENTS_READ
0x168
Read command received
SHORTS
0x200
Shortcut register
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ERRORSRC
0x4D0
Error source
MATCH
0x4D4
Status register indicating which address had a match
ENABLE
0x500
Enable TWIS
PSEL.SCL
0x508
Pin select for SCL signal
PSEL.SDA
0x50C
Pin select for SDA signal
RXD.PTR
0x534
RXD Data pointer
RXD.MAXCNT
0x538
Maximum number of bytes in RXD buffer
RXD.AMOUNT
0x53C
Number of bytes transferred in the last RXD transaction
TXD.PTR
0x544
TXD Data pointer
TXD.MAXCNT
0x548
Maximum number of bytes in TXD buffer
TXD.AMOUNT
0x54C
Number of bytes transferred in the last TXD transaction
ADDRESS[0]
0x588
TWI slave address 0
ADDRESS[1]
0x58C
TWI slave address 1
CONFIG
0x594
Configuration register for the address match mechanism
ORC
0x5C0
Over-read character. Character sent out in case of an over-read of the transmit buffer.
34.9.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
RW Field
A
RW WRITE_SUSPEND
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between WRITE event and SUSPEND task
See EVENTS_WRITE and TASKS_SUSPEND
B
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW READ_SUSPEND
Shortcut between READ event and SUSPEND task
See EVENTS_READ and TASKS_SUSPEND
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34 TWIS — I C compatible two-wire interface
slave with EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
34.9.2 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
F E
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for STOPPED event
See EVENTS_STOPPED
B
Disabled
0
Disable
Enabled
1
Enable
RW ERROR
Enable or disable interrupt for ERROR event
See EVENTS_ERROR
E
Disabled
0
Disable
Enabled
1
Enable
RW RXSTARTED
Enable or disable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
F
Disabled
0
Disable
Enabled
1
Enable
RW TXSTARTED
Enable or disable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
G
Disabled
0
Disable
Enabled
1
Enable
RW WRITE
Enable or disable interrupt for WRITE event
See EVENTS_WRITE
H
Disabled
0
Disable
Enabled
1
Enable
RW READ
Enable or disable interrupt for READ event
See EVENTS_READ
Disabled
0
Disable
Enabled
1
Enable
34.9.3 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
F E
Value
Description
Write '1' to Enable interrupt for STOPPED event
See EVENTS_STOPPED
B
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Enable interrupt for ERROR event
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34 TWIS — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G
Reset 0x00000000
Id
RW Field
0
F E
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_ERROR
E
RW RXSTARTED
Write '1' to Enable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTARTED
Write '1' to Enable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW WRITE
Write '1' to Enable interrupt for WRITE event
See EVENTS_WRITE
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW READ
Write '1' to Enable interrupt for READ event
See EVENTS_READ
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
34.9.4 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
F E
B
Value
Description
Write '1' to Disable interrupt for STOPPED event
See EVENTS_STOPPED
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Disable interrupt for ERROR event
See EVENTS_ERROR
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXSTARTED
Write '1' to Disable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTARTED
Write '1' to Disable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
Clear
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Disable
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34 TWIS — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G
Reset 0x00000000
Id
G
RW Field
0
F E
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW WRITE
Write '1' to Disable interrupt for WRITE event
See EVENTS_WRITE
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW READ
Write '1' to Disable interrupt for READ event
See EVENTS_READ
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
34.9.5 ERRORSRC
Address offset: 0x4D0
Error source
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B
Reset 0x00000000
Id
RW Field
A
RW OVERFLOW
B
C
0
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NotDetected
0
Error did not occur
Detected
1
Error occurred
NotReceived
0
Error did not occur
Received
1
Error occurred
NotDetected
0
Error did not occur
Detected
1
Error occurred
RX buffer overflow detected, and prevented
RW DNACK
NACK sent after receiving a data byte
RW OVERREAD
TX buffer over-read detected, and prevented
34.9.6 MATCH
Address offset: 0x4D4
Status register indicating which address had a match
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
MATCH
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..1]
Which of the addresses in {ADDRESS} matched the incoming
address
34.9.7 ENABLE
Address offset: 0x500
Enable TWIS
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Disabled
0
Description
Enable or disable TWIS
Disable TWIS
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34 TWIS — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
9
Enable TWIS
34.9.8 PSEL.SCL
Address offset: 0x508
Pin select for SCL signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
34.9.9 PSEL.SDA
Address offset: 0x50C
Pin select for SDA signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
34.9.10 RXD.PTR
Address offset: 0x534
RXD Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
RXD Data pointer
34.9.11 RXD.MAXCNT
Address offset: 0x538
Maximum number of bytes in RXD buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in RXD buffer
34.9.12 RXD.AMOUNT
Address offset: 0x53C
Number of bytes transferred in the last RXD transaction
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34 TWIS — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last RXD transaction
34.9.13 TXD.PTR
Address offset: 0x544
TXD Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
TXD Data pointer
34.9.14 TXD.MAXCNT
Address offset: 0x548
Maximum number of bytes in TXD buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in TXD buffer
34.9.15 TXD.AMOUNT
Address offset: 0x54C
Number of bytes transferred in the last TXD transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last TXD transaction
34.9.16 ADDRESS[0]
Address offset: 0x588
TWI slave address 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ADDRESS
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
TWI slave address
34.9.17 ADDRESS[1]
Address offset: 0x58C
TWI slave address 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ADDRESS
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
TWI slave address
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34 TWIS — I C compatible two-wire interface
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34.9.18 CONFIG
Address offset: 0x594
Configuration register for the address match mechanism
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000001
Id
RW Field
A
RW ADDRESS0
B
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Description
Disabled
0
Disabled
Enabled
1
Enabled
Disabled
0
Disabled
Enabled
1
Enabled
Enable or disable address matching on ADDRESS[0]
RW ADDRESS1
Enable or disable address matching on ADDRESS[1]
34.9.19 ORC
Address offset: 0x5C0
Over-read character. Character sent out in case of an over-read of the transmit buffer.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ORC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Over-read character. Character sent out in case of an over-read
of the transmit buffer.
34.10 Electrical specification
34.10.1 TWIS slave interface electrical specifications
Symbol
Description
Min.
fTWIS
Bit rates for TWIS31
100
ITWIS,100kbps
Run current for TWIS (Average current to receive and transfer a
Typ.
Max.
Units
400
kbps
45
µA
45
µA
byte to RAM), 100 kbps
ITWIS,400kbps
Run current for TWIS (Average current to receive and transfer a
byte to RAM), 400 kbps
ITWIS,IDLE
Idle current for TWIS
1
µA
tTWIS,START,LP
Time from PREPARERX/PREPARETX task to ready to receive/
tTWIS,START,CL
µs
transmit, Low power mode
+
tSTART_HFINT
tTWIS,START,CL
Time from PREPARERX/PREPARETX task to ready to receive/
1.5
µs
transmit, Constant latency mode
34.10.2 TWIS slave timing specifications
Symbol
Description
fTWIS,SCL,400kbps
SCL clock frequency, 400 kbps
Min.
Typ.
Max.
Units
400
tTWIS,SU_DAT
Data setup time before positive edge on SCL – all modes
300
kHz
ns
tTWIS,HD_DAT
Data hold time after negative edge on SCL – all modes
500
ns
tTWIS,HD_STA,100kbps
TWI slave hold time from for START condition (SDA low to SCL
5200
ns
1300
ns
low), 100 kbps
tTWIS,HD_STA,400kbps
TWI slave hold time from for START condition (SDA low to SCL
low), 400 kbps
31
Higher bit rates or stronger pull-ups may require GPIOs to be set as High Drive, see GPIO chapter for more
details.
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34 TWIS — I C compatible two-wire interface
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Symbol
Description
Min.
tTWIS,SU_STO,100kbps
TWI slave setup time from SCL high to STOP condition, 100 kbps
5200
tTWIS,SU_STO,400kbps
TWI slave setup time from SCL high to STOP condition, 400 kbps
1300
tTWIS,BUF,100kbps
TWI slave bus free time between STOP and START conditions,
Typ.
Max.
Units
ns
ns
4700
ns
1300
ns
100 kbps
tTWIS,BUF,400kbps
TWI slave bus free time between STOP and START conditions,
400 kbps
Figure 92: TWIS timing diagram, 1 byte transaction
Page 331
35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
The Universal asynchronous receiver/transmitter with EasyDMA (UARTE) offers fast, full-duplex,
asynchronous serial communication with built-in flow control (CTS, RTS) support in hardware at a rate up to
1 Mbps, and EasyDMA data transfer from/to RAM.
Listed here are the main features for UARTE:
•
•
•
•
•
•
•
•
Full-duplex operation
Automatic hardware flow control
th
Parity checking and generation for the 9 data bit
EasyDMA
Up to 1 Mbps baudrate
Return to IDLE between transactions supported (when using HW flow control)
One stop bit
Least significant bit (LSB) first
PSELRXD
STARTRX
PSELCTS
RXD
(signal)
STOPRX
PSELRTS
RXD.PTR
TXD.PTR
PSELTXD
TXD
(signal)
STARTTX
STOPTX
SUSPEND
RESUME
RX
FIFO
RXTO
ENDTX
EasyDMA
EasyDMA
ENDRX
CTS
NCTS
RAM
RXD
TXD
RXD+1
TXD+1
RXD+2
TXD+2
RXD+n
TXD+n
Figure 93: UARTE configuration
The GPIOs used for each UART interface can be chosen from any GPIO on the device and are
independently configurable. This enables great flexibility in device pinout and efficient use of board space
and signal routing.
35.1 Shared resources
The UARTE shares registers and other resources with other peripherals that have the same ID as the
UARTE.
Therefore, you must disable all peripherals that have the same ID as the UARTE before the UARTE can be
configured and used. Disabling a peripheral that has the same ID as the UARTE will not reset any of the
registers that are shared with the UARTE. It is therefore important to configure all relevant UARTE registers
explicitly to ensure that it operates correctly.
See the Instantiation table in Instantiation on page 24 for details on peripherals and their IDs.
35.2 EasyDMA
The UARTE implements EasyDMA for reading and writing to and from the RAM.
If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result
in a HardFault or RAM corruption. See Memory on page 23 for more information about the different memory
regions.
Page 332
35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next RX/
TX transmission immediately after having received the RXSTARTED/TXSTARTED event.
The ENDRX/ENDTX event indicates that EasyDMA has finished accessing respectively the RX/TX buffer in
RAM.
35.3 Transmission
The first step of a DMA transmission is storing bytes in the transmit buffer and configuring EasyDMA. This
is achieved by writing the initial address pointer to TXD.PTR, and the number of bytes in the RAM buffer to
TXD.MAXCNT. The UARTE transmission is started by triggering the STARTTX task.
After each byte has been sent over the TXD line, a TXDRDY event will be generated.
When all bytes in the TXD buffer, as specified in the TXD.MAXCNT register, have been transmitted, the
UARTE transmission will end automatically and an ENDTX event will be generated.
A UARTE transmission sequence is stopped by triggering the STOPTX task, a TXSTOPPED event will be
generated when the UARTE transmitter has stopped.
If the ENDTX event has not already been generated when the UARTE transmitter has come to a stop, the
UARTE will generate the ENDTX event explicitly even though all bytes in the TXD buffer, as specified in the
TXD.MAXCNT register, have not been transmitted.
N
2
ENDTX
TXDRDY
TXDRDY
N-1
TXDRDY
N-2
2
TXDRDY
TXDRDY
1
STARTTX
TXD.MAXCNT = N+1
1
TXSTARTED
Lifeline
0
TXDRDY
TXD
CTS
If flow control is enabled, a transmission will be automatically suspended when CTS is deactivated and
resumed when CTS is activated again, as illustrated in Figure 94: UARTE transmission on page 333.
A byte that is in transmission when CTS is deactivated will be fully transmitted before the transmission is
suspended.
Figure 94: UARTE transmission
The UARTE transmitter will be in its lowest activity level, and consume the least amount of energy, when
it is stopped, i.e. before it is started via STARTTX or after it has been stopped via STOPTX and the
TXSTOPPED event has been generated. See POWER — Power supply on page 78 for more information
about power modes.
35.4 Reception
The UARTE receiver is started by triggering the STARTRX task. The UARTE receiver is using EasyDMA to
store incoming data in an RX buffer in RAM.
Page 333
35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
The RX buffer is located at the address specified in the RXD.PTR register. The RXD.PTR register is doublebuffered and it can be updated and prepared for the next STARTRX task immediately after the RXSTARTED
event is generated. The size of the RX buffer is specified in the RXD.MAXCNT register and the UARTE will
generate an ENDRX event when it has filled up the RX buffer, see Figure 95: UARTE reception on page
334.
For each byte received over the RXD line, an RXDRDY event will be generated. This event is likely to occur
before the corresponding data has been transferred to Data RAM.
The RXD.AMOUNT register can be queried following an ENDRX event to see how many new bytes have
been transferred to the RX buffer in RAM since the previous ENDRX event.
Data RAM
1
2
3
4
5
6
7
8
9
10
11
12
-
10
11
0x20000003
0x20000004
0x20000010
0x20000011
0x20000012
0x20000013
0x20000014
0x20000020
0x20000021
0x20000022
0x20000023
0x20000024
12
12
RXSTARTED
RXDRDY
RXD.PTR = 0x20000020
RXD.PTR = 0x20000030
4
STARTRX
3
0x20000001
0x20000002
RXDRDY
11
10
ENDRX
9
RXDRDY
RXSTARTED
9
RXDRDY
8
8
RXDRDY
7
ENDRX
6
7
RXDRDY
6
RXDRDY
5
RXDRDY
4
5
STARTRX
STARTRX
RXD.MAXCNT = 5
RXD.PTR = 0x20000000
4
2
1
ENDRX_STARTRX = 1
3
RXD.PTR = 0x20000010
Lifeline
3
RXDRDY
2
RXSTARTED
RXDRDY
1
2
RXDRDY
RXD
1
RXDRDY
EasyDMA
-
0x20000000
Figure 95: UARTE reception
The UARTE receiver is stopped by triggering the STOPRX task. An RXTO event is generated when the
UARTE has stopped. The UARTE will make sure that an impending ENDRX event will be generated before
the RXTO event is generated. This means that the UARTE will guarantee that no ENDRX event will be
generated after RXTO, unless the UARTE is restarted or a FLUSHRX command is issued after the RXTO
event is generated.
Important: If the ENDRX event has not already been generated when the UARTE receiver has
come to a stop, which implies that all pending content in the RX FIFO has been moved to the RX
buffer, the UARTE will generate the ENDRX event explicitly even though the RX buffer is not full. In
this scenario the ENDRX event will be generated before the RXTO event is generated.
To be able to know how many bytes have actually been received into the RX buffer, the CPU can read the
RXD.AMOUNT register following the ENDRX event or the RXTO event.
The UARTE is able to receive up to four bytes after the STOPRX task has been triggered as long as these
are sent in succession immediately after the RTS signal is deactivated. This is possible because after the
RTS is deactivated the UARTE is able to receive bytes for an extended period equal to the time it takes to
send 4 bytes on the configured baud rate.
After the RXTO event is generated the internal RX FIFO may still contain data, and to move this data to RAM
the FLUSHRX task must be triggered. To make sure that this data does not overwrite data in the RX buffer,
the RX buffer should be emptied or the RXD.PTR should be updated before the FLUSHRX task is triggered.
Page 334
35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
5
6
6
7
Lifeline
2
1
7
8
8
9
9
11, 12, 13, 14
10
10
11
12
13
3
14
ENDRX
4
5
RXTO
3
4
ENDRX
2
3
RXSTARTED
1
2
ENDRX
RXD
1
RXSTARTED
EasyDMA
To make sure that all data in the RX FIFO is moved to the RX buffer, the RXD.MAXCNT register must be set
to RXD.MAXCNT > 4, see Figure 96: UARTE reception with forced stop via STOPRX on page 335. The
UARTE will generate the ENDRX event after completing the FLUSHRX task even if the RX FIFO was empty
or if the RX buffer does not get filled up. To be able to know how many bytes have actually been received
into the RX buffer in this case, the CPU can read the RXD.AMOUNT register following the ENDRX event.
3
4
5
FLUSHRX
STOPRX
ENDRX_STARTRX = 0
STARTRX
RXD.PTR = C
STARTRX
RXD.PTR = B
RXD.PTR = A
RXD.MAXCNT = 5
ENDRX_STARTRX = 1
Timeout
Figure 96: UARTE reception with forced stop via STOPRX
If HW flow control is enabled the RTS signal will be deactivated when the receiver is stopped via the
STOPRX task or when the UARTE is only able to receive four more bytes in its internal RX FIFO.
With flow control disabled, the UARTE will function in the same way as when the flow control is enabled
except that the RTS line will not be used. This means that no signal will be generated when the UARTE has
reached the point where it is only able to receive four more bytes in its internal RX FIFO. Data received when
the internal RX FIFO is filled up, will be lost.
The UARTE receiver will be in its lowest activity level, and consume the least amount of energy, when it is
stopped, i.e. before it is started via STARTRX or after it has been stopped via STOPRX and the RXTO event
has been generated. See POWER — Power supply on page 78 for more information about power modes.
35.5 Error conditions
An ERROR event, in the form of a framing error, will be generated if a valid stop bit is not detected in a
frame. Another ERROR event, in the form of a break condition, will be generated if the RXD line is held
active low for longer than the length of a data frame. Effectively, a framing error is always generated before a
break condition occurs.
An ERROR event will not stop reception. If the error was a parity error, the received byte will still be
transferred into Data RAM, and so will following incoming bytes. If there was a framing error (wrong stop bit),
that specific byte will NOT be stored into Data RAM, but following incoming bytes will.
35.6 Using the UARTE without flow control
If flow control is not enabled, the interface will behave as if the CTS and RTS lines are kept active all the
time.
35.7 Parity configuration
When parity is enabled, the parity will be generated automatically from the even parity of TXD and RXD for
transmission and reception respectively.
35.8 Low power
When putting the system in low power and the peripheral is not needed, lowest possible power consumption
is achieved by stopping, and then disabling the peripheral.
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35 UARTE — Universal asynchronous receiver/
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The STOPTX and STOPRX tasks may not be always needed (the peripheral might already be stopped),
but if STOPTX and/or STOPRX is sent, software shall wait until the TXSTOPPED and/or RXTO event is
received in response, before disabling the peripheral through the ENABLE register.
35.9 Pin configuration
The different signals RXD, CTS (Clear To Send, active low), RTS (Request To Send, active low), and TXD
associated with the UARTE are mapped to physical pins according to the configuration specified in the
PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers respectively.
The PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers and their configurations are only used
as long as the UARTE is enabled, and retained only for the duration the device is in ON mode. PSEL.RXD,
PSEL.RTS, PSEL.RTS and PSEL.TXD must only be configured when the UARTE is disabled.
To secure correct signal levels on the pins by the UARTE when the system is in OFF mode, the pins must be
configured in the GPIO peripheral as described in Table 80: GPIO configuration before enabling peripheral
on page 336.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behavior.
Table 80: GPIO configuration before enabling peripheral
UARTE signal
RXD
CTS
RTS
TXD
UARTE pin
As specified in PSEL.RXD
As specified in PSEL.CTS
As specified in PSEL.RTS
As specified in PSEL.TXD
Direction
Input
Input
Output
Output
Output value
Not applicable
Not applicable
1
1
35.10 Registers
Table 81: Instances
Base address
Peripheral
Instance
Description
0x40002000
UARTE
UARTE0
Universal Asynchronous Receiver/
Configuration
Transmitter with EasyDMA
Table 82: Register Overview
Register
Offset
Description
TASKS_STARTRX
0x000
Start UART receiver
TASKS_STOPRX
0x004
Stop UART receiver
TASKS_STARTTX
0x008
Start UART transmitter
TASKS_STOPTX
0x00C
Stop UART transmitter
TASKS_FLUSHRX
0x02C
Flush RX FIFO into RX buffer
EVENTS_CTS
0x100
CTS is activated (set low). Clear To Send.
EVENTS_NCTS
0x104
CTS is deactivated (set high). Not Clear To Send.
EVENTS_RXDRDY
0x108
Data received in RXD (but potentially not yet transferred to Data RAM)
EVENTS_ENDRX
0x110
Receive buffer is filled up
EVENTS_TXDRDY
0x11C
Data sent from TXD
EVENTS_ENDTX
0x120
Last TX byte transmitted
EVENTS_ERROR
0x124
Error detected
EVENTS_RXTO
0x144
Receiver timeout
EVENTS_RXSTARTED
0x14C
UART receiver has started
EVENTS_TXSTARTED
0x150
UART transmitter has started
EVENTS_TXSTOPPED
0x158
Transmitter stopped
SHORTS
0x200
Shortcut register
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
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35 UARTE — Universal asynchronous receiver/
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Register
Offset
Description
ERRORSRC
0x480
Error source
ENABLE
0x500
Enable UART
PSEL.RTS
0x508
Pin select for RTS signal
PSEL.TXD
0x50C
Pin select for TXD signal
PSEL.CTS
0x510
Pin select for CTS signal
PSEL.RXD
0x514
Pin select for RXD signal
BAUDRATE
0x524
Baud rate. Accuracy depends on the HFCLK source selected.
RXD.PTR
0x534
Data pointer
RXD.MAXCNT
0x538
Maximum number of bytes in receive buffer
RXD.AMOUNT
0x53C
Number of bytes transferred in the last transaction
TXD.PTR
0x544
Data pointer
TXD.MAXCNT
0x548
Maximum number of bytes in transmit buffer
TXD.AMOUNT
0x54C
Number of bytes transferred in the last transaction
CONFIG
0x56C
Configuration of parity and hardware flow control
35.10.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x00000000
Id
RW Field
C
RW ENDRX_STARTRX
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between ENDRX event and STARTRX task
See EVENTS_ENDRX and TASKS_STARTRX
D
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW ENDRX_STOPRX
Shortcut between ENDRX event and STOPRX task
See EVENTS_ENDRX and TASKS_STOPRX
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
35.10.2 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L
Reset 0x00000000
Id
RW Field
A
RW CTS
0
Value Id
J
I
H
Value
Description
Enable or disable interrupt for CTS event
See EVENTS_CTS
B
Disabled
0
Disable
Enabled
1
Enable
RW NCTS
Enable or disable interrupt for NCTS event
See EVENTS_NCTS
C
Disabled
0
Disable
Enabled
1
Enable
RW RXDRDY
Enable or disable interrupt for RXDRDY event
See EVENTS_RXDRDY
D
G F E
D
C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Disabled
0
Disable
Enabled
1
Enable
RW ENDRX
Enable or disable interrupt for ENDRX event
See EVENTS_ENDRX
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35 UARTE — Universal asynchronous receiver/
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L
Reset 0x00000000
Id
E
RW Field
0
J
I
H
G F E
D
C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
RW TXDRDY
Enable or disable interrupt for TXDRDY event
See EVENTS_TXDRDY
F
Disabled
0
Disable
Enabled
1
Enable
RW ENDTX
Enable or disable interrupt for ENDTX event
See EVENTS_ENDTX
G
Disabled
0
Disable
Enabled
1
Enable
RW ERROR
Enable or disable interrupt for ERROR event
See EVENTS_ERROR
H
Disabled
0
Disable
Enabled
1
Enable
RW RXTO
Enable or disable interrupt for RXTO event
See EVENTS_RXTO
I
Disabled
0
Disable
Enabled
1
Enable
RW RXSTARTED
Enable or disable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
J
Disabled
0
Disable
Enabled
1
Enable
RW TXSTARTED
Enable or disable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
L
Disabled
0
Disable
Enabled
1
Enable
RW TXSTOPPED
Enable or disable interrupt for TXSTOPPED event
See EVENTS_TXSTOPPED
Disabled
0
Disable
Enabled
1
Enable
35.10.3 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L
Reset 0x00000000
Id
RW Field
A
RW CTS
0
Value Id
J
I
H
G F E
Value
Description
Write '1' to Enable interrupt for CTS event
See EVENTS_CTS
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW NCTS
Write '1' to Enable interrupt for NCTS event
See EVENTS_NCTS
C
D
C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXDRDY
Write '1' to Enable interrupt for RXDRDY event
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35 UARTE — Universal asynchronous receiver/
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L
Reset 0x00000000
Id
RW Field
0
J
I
H
G F E
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_RXDRDY
D
RW ENDRX
Write '1' to Enable interrupt for ENDRX event
See EVENTS_ENDRX
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXDRDY
Write '1' to Enable interrupt for TXDRDY event
See EVENTS_TXDRDY
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDTX
Write '1' to Enable interrupt for ENDTX event
See EVENTS_ENDTX
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Enable interrupt for ERROR event
See EVENTS_ERROR
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXTO
Write '1' to Enable interrupt for RXTO event
See EVENTS_RXTO
I
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXSTARTED
Write '1' to Enable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
J
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTARTED
Write '1' to Enable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
L
D
C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTOPPED
Write '1' to Enable interrupt for TXSTOPPED event
See EVENTS_TXSTOPPED
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
35.10.4 INTENCLR
Address offset: 0x308
Disable interrupt
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35 UARTE — Universal asynchronous receiver/
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L
Reset 0x00000000
Id
RW Field
A
RW CTS
0
Value Id
J
I
H
G F E
Value
Description
Write '1' to Disable interrupt for CTS event
See EVENTS_CTS
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW NCTS
Write '1' to Disable interrupt for NCTS event
See EVENTS_NCTS
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXDRDY
Write '1' to Disable interrupt for RXDRDY event
See EVENTS_RXDRDY
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDRX
Write '1' to Disable interrupt for ENDRX event
See EVENTS_ENDRX
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXDRDY
Write '1' to Disable interrupt for TXDRDY event
See EVENTS_TXDRDY
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDTX
Write '1' to Disable interrupt for ENDTX event
See EVENTS_ENDTX
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Disable interrupt for ERROR event
See EVENTS_ERROR
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXTO
Write '1' to Disable interrupt for RXTO event
See EVENTS_RXTO
I
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXSTARTED
Write '1' to Disable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
J
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTARTED
Write '1' to Disable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
L
D
C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTOPPED
Write '1' to Disable interrupt for TXSTOPPED event
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35 UARTE — Universal asynchronous receiver/
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L
Reset 0x00000000
Id
RW Field
0
J
I
H
G F E
D
C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_TXSTOPPED
35.10.5 ERRORSRC
Address offset: 0x480
Error source
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C B A
Reset 0x00000000
Id
RW Field
A
RW OVERRUN
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Overrun error
A start bit is received while the previous data still lies in RXD.
(Previous data is lost.)
B
NotPresent
0
Read: error not present
Present
1
Read: error present
RW PARITY
Parity error
A character with bad parity is received, if HW parity check is
enabled.
C
NotPresent
0
Read: error not present
Present
1
Read: error present
RW FRAMING
Framing error occurred
A valid stop bit is not detected on the serial data input after all
bits in a character have been received.
D
NotPresent
0
Read: error not present
Present
1
Read: error present
RW BREAK
Break condition
The serial data input is '0' for longer than the length of a data
frame. (The data frame length is 10 bits without parity bit, and
11 bits with parity bit.).
NotPresent
0
Read: error not present
Present
1
Read: error present
35.10.6 ENABLE
Address offset: 0x500
Enable UART
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable UARTE
Enabled
8
Enable UARTE
Enable or disable UARTE
35.10.7 PSEL.RTS
Address offset: 0x508
Pin select for RTS signal
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35 UARTE — Universal asynchronous receiver/
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
35.10.8 PSEL.TXD
Address offset: 0x50C
Pin select for TXD signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
35.10.9 PSEL.CTS
Address offset: 0x510
Pin select for CTS signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
35.10.10 PSEL.RXD
Address offset: 0x514
Pin select for RXD signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
35.10.11 BAUDRATE
Address offset: 0x524
Baud rate. Accuracy depends on the HFCLK source selected.
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35 UARTE — Universal asynchronous receiver/
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x04000000
Id
RW Field
A
RW BAUDRATE
0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Baud1200
0x0004F000
1200 baud (actual rate: 1205)
Baud2400
0x0009D000
2400 baud (actual rate: 2396)
Baud4800
0x0013B000
4800 baud (actual rate: 4808)
Baud9600
0x00275000
9600 baud (actual rate: 9598)
Baud14400
0x003AF000
14400 baud (actual rate: 14401)
Baud19200
0x004EA000
19200 baud (actual rate: 19208)
Baud28800
0x0075C000
28800 baud (actual rate: 28777)
Baud38400
0x009D0000
38400 baud (actual rate: 38369)
Baud57600
0x00EB0000
57600 baud (actual rate: 57554)
Baud76800
0x013A9000
76800 baud (actual rate: 76923)
Baud115200
0x01D60000
115200 baud (actual rate: 115108)
Baud230400
0x03B00000
230400 baud (actual rate: 231884)
Baud250000
0x04000000
250000 baud
Baud460800
0x07400000
460800 baud (actual rate: 457143)
Baud921600
0x0F000000
921600 baud (actual rate: 941176)
Baud1M
0x10000000
1Mega baud
Baud rate
35.10.12 RXD.PTR
Address offset: 0x534
Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Data pointer
35.10.13 RXD.MAXCNT
Address offset: 0x538
Maximum number of bytes in receive buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in receive buffer
35.10.14 RXD.AMOUNT
Address offset: 0x53C
Number of bytes transferred in the last transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last transaction
35.10.15 TXD.PTR
Address offset: 0x544
Data pointer
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35 UARTE — Universal asynchronous receiver/
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Data pointer
35.10.16 TXD.MAXCNT
Address offset: 0x548
Maximum number of bytes in transmit buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in transmit buffer
35.10.17 TXD.AMOUNT
Address offset: 0x54C
Number of bytes transferred in the last transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last transaction
35.10.18 CONFIG
Address offset: 0x56C
Configuration of parity and hardware flow control
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B B B A
Reset 0x00000000
Id
RW Field
A
RW HWFC
B
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disabled
Enabled
1
Enabled
Excluded
0x0
Exclude parity bit
Included
0x7
Include parity bit
Hardware flow control
RW PARITY
Parity
35.11 Electrical specification
35.11.1 UARTE electrical specification
Symbol
Description
fUARTE
Baud rate for UARTE32.
IUARTE1M
Run current at max baud rate.
55
µA
IUARTE115k
Run current at 115200 bps.
55
µA
IUARTE1k2
Run current at 1200 bps.
55
µA
IUARTE,IDLE
Idle current for UARTE (STARTed, no XXX activity)
1
µA
tUARTE,CTSH
CTS high time
32
Min.
Typ.
Max.
Units
1000
kbps
1
Higher baud rates may require GPIOs to be set as High Drive, see GPIO chapter for more details.
Page 344
µs
35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
Symbol
Description
tUARTE,START,LP
Time from STARTRX/STARTTX task to transmission started, low
Min.
Typ.
tUARTE,START,CL
Max.
power mode
+
Units
µs
tSTART_HFINT
tUARTE,START,CL
Time from STARTRX/STARTTX task to transmission started,
constant latency mode
Page 345
1
µs
36 QDEC — Quadrature decoder
36 QDEC — Quadrature decoder
The Quadrature decoder (QDEC) provides buffered decoding of quadrature-encoded sensor signals. It is
suitable for mechanical and optical sensors.
The sample period and accumulation are configurable to match application requirements. The QDEC
provides the following:
•
•
•
•
Decoding of digital waveform from off-chip quadrature encoder.
Sample accumulation eliminating hard real-time requirements to be enforced on application.
Optional input de-bounce filters.
Optional LED output signal for optical encoders.
ACCREAD
ACCDBLREAD
ACC
ACCDBL
+
+
SAMPLE
Quadrature decoder
IO router
On-chip
Off-chip
Phase A
Phase B
LED
Mechanical to electrical
Mechanical
device
Quadrature Encoder
Figure 97: Quadrature decoder configuration
36.1 Sampling and decoding
The QDEC decodes the output from an incremental motion encoder by sampling the QDEC phase input pins
(A and B).
The off-chip quadrature encoder is an incremental motion encoder outputting two waveforms, phase A and
phase B. The two output waveforms are always 90 degrees out of phase, meaning that one always changes
level before the other. The direction of movement is indicated by which of these two waveforms that changes
level first. Invalid transitions may occur, that is when the two waveforms switch simultaneously. This may
occur if the wheel rotates too fast relative to the sample rate set for the decoder.
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36 QDEC — Quadrature decoder
The QDEC decodes the output from the off-chip encoder by sampling the QDEC phase input pins (A and B)
at a fixed rate as specified in the SAMPLEPER register.
If the SAMPLEPER value needs to be changed, the QDEC shall be stopped using the STOP task.
SAMPLEPER can be then changed upon receiving the STOPPED event, and QDEC can be restarted using
the START task. Failing to do so may result in unpredictable behaviour.
It is good practice to change other registers (LEDPOL, REPORTPER, DBFEN and LEDPRE) only when the
QDEC is stopped.
When started, the decoder continuously samples the two input waveforms and decodes these by comparing
the current sample pair (n) with the previous sample pair (n-1).
The decoding of the sample pairs is described in the table below.
Table 83: Sampled value encoding
Previous
sample pair(n
- 1)
A
B
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
Current
SAMPLE
samples pair(n) register
ACC operation ACCDBL
operation
Description
A
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
No change
Increment
Decrement
No change
Decrement
No change
No change
Increment
Increment
No change
No change
Decrement
No change
Decrement
Increment
No change
No movement
Movement in positive direction
Movement in negative direction
Error: Double transition
Movement in negative direction
No movement
Error: Double transition
Movement in positive direction
Movement in positive direction
Error: Double transition
No movement
Movement in negative direction
Error: Double transition
Movement in negative direction
Movement in positive direction
No movement
B
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-1
2
-1
0
2
1
1
2
0
-1
2
-1
1
0
No change
No change
No change
Increment
No change
No change
Increment
No change
No change
Increment
No change
No change
Increment
No change
No change
No change
36.2 LED output
The LED output follows the sample period, and the LED is switched on a given period before sampling and
switched off immediately after the inputs are sampled. The period the LED is switched on before sampling is
given in the LEDPRE register.
The LED output pin polarity is specified in the LEDPOL register.
For using off-chip mechanical encoders not requiring a LED, the LED output can be disabled by writing
value 'Disconnected' to the CONNECT field of the PSEL.LED register. In this case the QDEC will not acquire
access to a LED output pin and the pin can be used for other purposes by the CPU.
36.3 Debounce filters
Each of the two-phase inputs have digital debounce filters.
When enabled through the DBFEN register, the filter inputs are sampled at a fixed 1 MHz frequency during
the entire sample period (which is specified in the SAMPLEPER register), and the filters require all of the
samples within this sample period to equal before the input signal is accepted and transferred to the output
of the filter.
As a result, only input signal with a steady state longer than twice the period specified in SAMPLEPER are
guaranteed to pass through the filter, and any signal with a steady state shorter than SAMPLEPER will
always be suppressed by the filter. (This is assumed that the frequency during the debounce period never
exceeds 500 kHz (as required by the Nyquist theorem when using a 1 MHz sample frequency).
The LED will always be ON when the debounce filters are enabled, as the inputs in this case will be sampled
continuously.
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36 QDEC — Quadrature decoder
Note that when when the debounce filters are enabled, displacements reported by the QDEC peripheral are
delayed by one SAMPLEPER period.
36.4 Accumulators
The quadrature decoder contains two accumulator registers, ACC and ACCDBL, that accumulate
respectively valid motion sample values and the number of detected invalid samples (double transitions).
The ACC register will accumulate all valid values (1/-1) written to the SAMPLE register. This can be useful
for preventing hard real-time requirements from being enforced on the application. When using the ACC
register the application does not need to read every single sample from the SAMPLE register, but can
instead fetch the ACC register whenever it fits the application. The ACC register will always hold the relative
movement of the external mechanical device since the previous clearing of the ACC register. Sample values
indicating a double transition (2) will not be accumulated in the ACC register.
An ACCOF event will be generated if the ACC receives a SAMPLE value that would cause the register to
overflow or underflow. Any SAMPLE value that would cause an ACC overflow or underflow will be discarded,
but any samples not causing the ACC to overflow or underflow will still be accepted.
The accumulator ACCDBL accumulates the number of detected double transitions since the previous
clearing of the ACCDBL register.
The ACC and ACCDBL registers can be cleared by the READCLRACC and subsequently read using the
ACCREAD and ACCDBLREAD registers.
The ACC register can be separately cleared by the RDCLRACC and subsequently read using the ACCREAD
registers.
The ACCDBL register can be separately cleared by the RDCLRDBL and subsequently read using the
ACCDBLREAD registers.
The REPORTPER register allows automating the capture of several samples before it can send out a
REPORTRDY event in case a non-null displacement has been captured and accumulated, and a DBLRDY
event in case one or more double-displacements have been captured and accumulated. The REPORTPER
field in this register selects after how many samples the accumulators contents are evaluated to send (or not)
REPORTRDY and DBLRDY events.
Using the RDCLRACC task (manually sent upon receiving the event, or using the DBLRDY_RDCLRACC
shortcut), ACCREAD can then be read.
In case at least one double transition has been captured and accumulated, a DBLRDY event is sent. Using
the RDCLRDBL task (manually sent upon receiving the event, or using the DBLRDY_RDCLRDBL shortcut),
ACCDBLREAD can then be read.
36.5 Output/input pins
The QDEC uses a three-pin interface to the off-chip quadrature encoder.
These pins will be acquired when the QDEC is enabled in the ENABLE register. The pins acquired by the
QDEC cannot be written by the CPU, but they can still be read by the CPU.
The pin numbers to be used for the QDEC are selected using the PSEL.n registers.
36.6 Pin configuration
The Phase A, Phase B, and LED signals are mapped to physical pins according to the configuration
specified in the PSEL.A, PSEL.B, and PSEL.LED registers respectively.
If the CONNECT field value 'Disconnected' is specified in any of these registers, the associated signal
will not be connected to any physical pin. The PSEL.A, PSEL.B, and PSEL.LED registers and their
configurations are only used as long as the QDEC is enabled, and retained only as long as the device is in
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36 QDEC — Quadrature decoder
ON mode. When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration
in their respective OUT bit field and PIN_CNF[n] register.
To secure correct behavior in the QDEC, the pins used by the QDEC must be configured in the GPIO
peripheral as described in Table 84: GPIO configuration before enabling peripheral on page 349 before
enabling the QDEC. This configuration must be retained in the GPIO for the selected IOs as long as the
QDEC is enabled.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behavior.
Table 84: GPIO configuration before enabling peripheral
QDEC signal
Phase A
Phase B
LED
QDEC pin
As specified in PSEL.A
As specified in PSEL.B
As specified in PSEL.LED
Direction
Input
Input
Input
Output value
Not applicable
Not applicable
Not applicable
Comment
36.7 Registers
Table 85: Instances
Base address
Peripheral
Instance
Description
0x40012000
QDEC
QDEC
Quadrature decoder
Configuration
Table 86: Register Overview
Register
Offset
Description
TASKS_START
0x000
Task starting the quadrature decoder
TASKS_STOP
0x004
Task stopping the quadrature decoder
TASKS_READCLRACC
0x008
Read and clear ACC and ACCDBL
TASKS_RDCLRACC
0x00C
Read and clear ACC
TASKS_RDCLRDBL
0x010
Read and clear ACCDBL
EVENTS_SAMPLERDY
0x100
Event being generated for every new sample value written to the SAMPLE register
EVENTS_REPORTRDY
0x104
Non-null report ready
EVENTS_ACCOF
0x108
ACC or ACCDBL register overflow
EVENTS_DBLRDY
0x10C
Double displacement(s) detected
EVENTS_STOPPED
0x110
QDEC has been stopped
SHORTS
0x200
Shortcut register
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ENABLE
0x500
Enable the quadrature decoder
LEDPOL
0x504
LED output pin polarity
SAMPLEPER
0x508
Sample period
SAMPLE
0x50C
Motion sample value
REPORTPER
0x510
Number of samples to be taken before REPORTRDY and DBLRDY events can be generated
ACC
0x514
Register accumulating the valid transitions
ACCREAD
0x518
Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task
PSEL.LED
0x51C
Pin select for LED signal
PSEL.A
0x520
Pin select for A signal
PSEL.B
0x524
Pin select for B signal
DBFEN
0x528
Enable input debounce filters
LEDPRE
0x540
Time period the LED is switched ON prior to sampling
ACCDBL
0x544
Register accumulating the number of detected double transitions
ACCDBLREAD
0x548
Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task
36.7.1 SHORTS
Address offset: 0x200
Shortcut register
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36 QDEC — Quadrature decoder
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G F E D C B A
Reset 0x00000000
Id
RW Field
A
RW REPORTRDY_READCLRACC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between REPORTRDY event and READCLRACC task
See EVENTS_REPORTRDY and TASKS_READCLRACC
B
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW SAMPLERDY_STOP
Shortcut between SAMPLERDY event and STOP task
See EVENTS_SAMPLERDY and TASKS_STOP
C
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW REPORTRDY_RDCLRACC
Shortcut between REPORTRDY event and RDCLRACC task
See EVENTS_REPORTRDY and TASKS_RDCLRACC
D
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW REPORTRDY_STOP
Shortcut between REPORTRDY event and STOP task
See EVENTS_REPORTRDY and TASKS_STOP
E
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW DBLRDY_RDCLRDBL
Shortcut between DBLRDY event and RDCLRDBL task
See EVENTS_DBLRDY and TASKS_RDCLRDBL
F
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW DBLRDY_STOP
Shortcut between DBLRDY event and STOP task
See EVENTS_DBLRDY and TASKS_STOP
G
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW SAMPLERDY_READCLRACC
Shortcut between SAMPLERDY event and READCLRACC task
See EVENTS_SAMPLERDY and TASKS_READCLRACC
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
36.7.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E D C B A
Reset 0x00000000
Id
RW Field
A
RW SAMPLERDY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for SAMPLERDY event
See EVENTS_SAMPLERDY
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REPORTRDY
Write '1' to Enable interrupt for REPORTRDY event
See EVENTS_REPORTRDY
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ACCOF
Write '1' to Enable interrupt for ACCOF event
See EVENTS_ACCOF
Set
1
Enable
Page 350
36 QDEC — Quadrature decoder
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E D C B A
Reset 0x00000000
Id
D
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DBLRDY
Write '1' to Enable interrupt for DBLRDY event
See EVENTS_DBLRDY
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Enable interrupt for STOPPED event
See EVENTS_STOPPED
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
36.7.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E D C B A
Reset 0x00000000
Id
RW Field
A
RW SAMPLERDY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for SAMPLERDY event
See EVENTS_SAMPLERDY
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REPORTRDY
Write '1' to Disable interrupt for REPORTRDY event
See EVENTS_REPORTRDY
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ACCOF
Write '1' to Disable interrupt for ACCOF event
See EVENTS_ACCOF
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DBLRDY
Write '1' to Disable interrupt for DBLRDY event
See EVENTS_DBLRDY
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Disable interrupt for STOPPED event
See EVENTS_STOPPED
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
36.7.4 ENABLE
Address offset: 0x500
Enable the quadrature decoder
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36 QDEC — Quadrature decoder
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable the quadrature decoder
When enabled the decoder pins will be active. When disabled
the quadrature decoder pins are not active and can be used as
GPIO .
Disabled
0
Disable
Enabled
1
Enable
36.7.5 LEDPOL
Address offset: 0x504
LED output pin polarity
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW LEDPOL
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
ActiveLow
0
Led active on output pin low
ActiveHigh
1
Led active on output pin high
LED output pin polarity
36.7.6 SAMPLEPER
Address offset: 0x508
Sample period
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW SAMPLEPER
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Sample period. The SAMPLE register will be updated for every
new sample
128us
0
128 us
256us
1
256 us
512us
2
512 us
1024us
3
1024 us
2048us
4
2048 us
4096us
5
4096 us
8192us
6
8192 us
16384us
7
16384 us
32ms
8
32768 us
65ms
9
65536 us
131ms
10
131072 us
36.7.7 SAMPLE
Address offset: 0x50C
Motion sample value
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
SAMPLE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[-1..2]
Last motion sample
Page 352
36 QDEC — Quadrature decoder
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
The value is a 2's complement value, and the sign gives the
direction of the motion. The value '2' indicates a double
transition.
36.7.8 REPORTPER
Address offset: 0x510
Number of samples to be taken before REPORTRDY and DBLRDY events can be generated
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW REPORTPER
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Specifies the number of samples to be accumulated in the ACC
register before the REPORTRDY and DBLRDY events can be
generated
The report period in [us] is given as: RPUS = SP * RP Where
RPUS is the report period in [us/report], SP is the sample period
in [us/sample] specified in SAMPLEPER, and RP is the report
period in [samples/report] specified in REPORTPER .
10Smpl
0
10 samples / report
40Smpl
1
40 samples / report
80Smpl
2
80 samples / report
120Smpl
3
120 samples / report
160Smpl
4
160 samples / report
200Smpl
5
200 samples / report
240Smpl
6
240 samples / report
280Smpl
7
280 samples / report
1Smpl
8
1 sample / report
36.7.9 ACC
Address offset: 0x514
Register accumulating the valid transitions
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
ACC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[-1024..1023]
Register accumulating all valid samples (not double transition)
read from the SAMPLE register
Double transitions ( SAMPLE = 2 ) will not be accumulated in
this register. The value is a 32 bit 2's complement value. If a
sample that would cause this register to overflow or underflow
is received, the sample will be ignored and an overflow event
( ACCOF ) will be generated. The ACC register is cleared by
triggering the READCLRACC or the RDCLRACC task.
36.7.10 ACCREAD
Address offset: 0x518
Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task
Page 353
36 QDEC — Quadrature decoder
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
ACCREAD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[-1024..1023]
Snapshot of the ACC register.
The ACCREAD register is updated when the READCLRACC or
RDCLRACC task is triggered
36.7.11 PSEL.LED
Address offset: 0x51C
Pin select for LED signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
36.7.12 PSEL.A
Address offset: 0x520
Pin select for A signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
36.7.13 PSEL.B
Address offset: 0x524
Pin select for B signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
36.7.14 DBFEN
Address offset: 0x528
Enable input debounce filters
Page 354
36 QDEC — Quadrature decoder
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW DBFEN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Debounce input filters disabled
Enabled
1
Debounce input filters enabled
Enable input debounce filters
36.7.15 LEDPRE
Address offset: 0x540
Time period the LED is switched ON prior to sampling
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A
Reset 0x00000010
Id
RW Field
A
RW LEDPRE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Value
Description
[1..511]
Period in us the LED is switched on prior to sampling
36.7.16 ACCDBL
Address offset: 0x544
Register accumulating the number of detected double transitions
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
ACCDBL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..15]
Register accumulating the number of detected double or illegal
transitions. ( SAMPLE = 2 ).
When this register has reached its maximum value the
accumulation of double / illegal transitions will stop. An
overflow event ( ACCOF ) will be generated if any double or
illegal transitions are detected after the maximum value was
reached. This field is cleared by triggering the READCLRACC or
RDCLRDBL task.
36.7.17 ACCDBLREAD
Address offset: 0x548
Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
ACCDBLREAD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..15]
Snapshot of the ACCDBL register. This field is updated when the
READCLRACC or RDCLRDBL task is triggered.
36.8 Electrical specification
36.8.1 QDEC Electrical Specification
Symbol
Description
IQDEC
Run current
Min.
Typ.
Max.
tSAMPLE
Time between sampling signals from quadrature decoder
128
131072
µs
tLED
Time from LED is turned on to signals are sampled
0
511
µs
5
Page 355
Units
µA
37 SAADC — Successive approximation analogto-digital converter
37 SAADC — Successive approximation analog-todigital converter
The ADC is a differential successive approximation register (SAR) analog-to-digital converter.
Listed here are the main features of SAADC:
•
•
•
•
•
•
•
•
•
•
•
•
8/10/12-bit resolution, 14-bit resolution with oversampling
Up to eight input channels
• One channel per single-ended input and two channels per differential input
• Scan mode can be configured with both single-ended channels and differential channels.
Full scale input range (0 to VDD)
Sampling triggered via a task from software or a PPI channel for full flexibility on sample frequency
source from low power 32.768kHz RTC or more accurate 1/16MHz Timers
One-shot conversion mode to sample a single channel
Scan mode to sample a series of channels in sequence. Sample delay between channels is tack + tconv
which may vary between channels according to user configuration of tack.
Support for direct sample transfer to RAM using EasyDMA
Interrupts on single sample and full buffer events
Samples stored as 16-bit 2’s complement values for differential and single-ended sampling
Continuous sampling without the need of an external timer
Internal resistor string
Limit checking on the fly
37.1 Shared resources
The ADC can coexist with COMP, LPCOMP and other peripherals using one of AIN0-AIN7, provided these
are assigned to different pins.
It is not recommended to select the same analog input pin for both modules.
37.2 Overview
The ADC supports up to eight external analog input channels, depending on package variant. It can be
operated in a one-shot mode with sampling under software control, or a continuous conversion mode with a
programmable sampling rate.
The analog inputs can be configured as eight single-ended inputs, four differential inputs or a combination
of these. Each channel can be configured to select AIN0 to AIN7 pins, or the VDD pin. Channels can be
sampled individually in one-shot or continuous sampling modes, or, using scan mode, multiple channels can
be sampled in sequence. Channels can also be oversampled to improve noise performance.
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37 SAADC — Successive approximation analogto-digital converter
PSEL_A
PSEL_A
PSEL_A
PSEL_A
PSEL_A
PSEL_A
CH[X].CONFIG
PSEL_A
PSEL_A
PSEL_A
PSEL_A
PSEL_A
PSEL_A
CH[X].PSELP
NC
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
VDD
NC
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
VDD
ADC
RAM
MUX
RESULT
P
RESP
RESULT
SAR
core
GAIN
RESULT
EasyDMA
RESULT
RESULT
RESULT
N
RESN
RESULT
RESULT
MUX
RESULT.PTR
START
SAMPLE
VDD
Internal reference
REFSEL
STARTED
END
STOPPED
STOP
CH[X].PSELN
PSEL_A
PSEL_A
PSEL_A
PSEL_A
PSEL_A
PSEL_A
Figure 98: Simplified ADC block diagram
Internally, the ADC is always a differential analog-to-digital converter, but by default it is configured with
single-ended input in the MODE field of the CH[n].CONFIG register. In single-ended mode, the negative
input will be shorted to ground internally.
The assumption in single-ended mode is that the internal ground of the ADC is the same as the external
ground that the measured voltage is referred to. The ADC is thus sensitive to ground bounce on the PCB in
single-ended mode. If this is a concern we recommend using differential measurement.
37.3 Digital output
The output result of the ADC depends on the settings in the CH[n].CONFIG and RESOLUTION registers as
follows:
RESULT = [V(P) – V(N) ] * GAIN/REFERENCE * 2(RESOLUTION
- m)
where
V(P)
is the voltage at input P
V(N)
is the voltage at input N
GAIN
is the selected gain setting
REFERENCE
is the selected reference voltage
and m=0 if CONFIG.MODE=SE, or m=1 if CONFIG.MODE=Diff.
The result generated by the ADC will deviate from the expected due DC errors like offset, gain, differential
non-linearity (DNL), and integral non-linearity (INL). See Electrical specification for details on these
parameters. The result can also vary due to AC errors like non-linearities in the GAIN block, settling errors
due to high source impedance and sampling jitter. For battery measurement the DC errors are most
noticeable.
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37 SAADC — Successive approximation analogto-digital converter
The ADC has a wide selection of gains controlled in the GAIN field of the CH[n].CONFIG register. If
CH[n].CONFIG.REFSEL=0, the input range of the ADC core is nominally ±0.6 V differential and the input
must be scaled accordingly.
The ADC has a temperature dependent offset. If the ADC is to operate over a large temperature range, we
recommend running CALIBRATEOFFSET at regular intervals, a CALIBRATEDONE event will be fired when
the calibration is complete
37.4 Analog inputs and channels
Up to eight analog input channels, CH[n](n=0..7), can be configured.
See Shared resources on page 356 for shared input with comparators.
Any one of the available channels can be enabled for the ADC to operate in one-shot mode. If more than
one CH[n] is configured, the ADC enters scan mode.
An analog input is selected as a positive converter input if CH[n].PSELP is set, setting CH[n].PSELP also
enables the particular channel.
An analog input is selected as a negative converter input if CH[n].PSELN is set. The CH[n].PSELN register
will have no effect unless differential mode is enabled, see MODE field in CH[n].CONFIG register.
If more than one of the CH[n].PSELP registers is set, the device enters scan mode. Input selections in scan
mode are controlled by the CH[n].PSELP and CH[n].PSELN registers, where CH[n].PSELN is only used if
the particular scan channel is specified as differential, see MODE field in CH[n].CONFIG register.
Important: Channels selected for either COMP or LPCOMP cannot be used at the same time for
ADC sampling, though channels not selected for use by these blocks can be used by the ADC.
Table 87: Legal connectivity CH[n] vs. analog input
Channel input
CH[n].PSELP
CH[n].PSELP
CH[n].PSELN
CH[n].PSELN
Source
AIN0…AIN7
VDD
AIN0…AIN7
VDD
Connectivity
Yes(any)
Yes
Yes(any)
Yes
37.5 Operation modes
The ADC input configuration supports one-shot mode, continuous mode and scan mode.
Scan mode and oversampling cannot be combined.
37.5.1 One-shot mode
One-shot operation is configured by enabling only one of the available channels defined by CH[n].PSELP,
CH[n].PSELN, and CH[n].CONFIG registers.
Upon a SAMPLE task, the ADC starts to sample the input voltage. The CH[n].CONFIG.TACQ controls the
acquisition time.
A DONE event signals that one sample has been taken.
In this mode, the RESULTDONE event has the same meaning as DONE when no oversampling takes place.
Note that both events may occur before the actual value has been transferred into RAM by EasyDMA. For
more information, see EasyDMA on page 360.
37.5.2 Continuous mode
Continuous sampling can be achieved by using the internal timer in the ADC, or triggering the SAMPLE task
from one of the general purpose timers through the PPI.
Care shall be taken to ensure that the sample rate fulfils the following criteria, depending on how many
channels are active:
fSAMPLE < 1/[tACQ + tconv]
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37 SAADC — Successive approximation analogto-digital converter
The SAMPLERATE register can be used as a local timer instead of triggering individual SAMPLE tasks.
When SAMPLERATE.MODE is set to Timers, it is sufficient to trigger SAMPLE task only once in order to
start the SAADC and triggering the STOP task will stop sampling. The SAMPLERATE.CC field controls the
sample rate.
The SAMPLERATE timer mode cannot be combined with SCAN mode, and only one channel can be
enabled in this mode.
A DONE event signals that one sample has been taken.
In this mode, the RESULTDONE event has the same meaning as DONE when no oversampling takes place.
Note that both events may occur before the actual value has been transferred into RAM by EasyDMA.
37.5.3 Oversampling
An accumulator in the ADC can be used to average noise on the analog input. In general, oversampling
improves the signal-to-noise ratio (SNR). Oversampling, however, does not improve the integral non-linearity
(INL), or differential non-linearity (DNL).
Oversampling and scan should not be combined, since oversampling and scan will average over input
channels.
The accumulator is controlled in the OVERSAMPLE register. The SAMPLE task must be set 2
number of times before the result is written to RAM. This can be achieved by:
•
•
•
OVERSAMPLE
Configuring a fixed sampling rate using the local timer or a general purpose timer and PPI to trigger a
SAMPLE task
OVERSAMPLE
Triggering SAMPLE 2
times from software
Enabling BURST mode
OVERSAMPLE
CH[n].CONFIG.BURST can be enabled to avoid setting SAMPLE task 2
times. With
OVERSAMPLE
BURST = 1 the ADC will sample the input 2
times as fast as it can (actual timing:
OVERSAMPLE
<(tACQ+tCONV)×2
). Thus, for the user it will just appear like the conversion took a bit longer time,
but other than that, it is similar to one-shot mode. Scan mode can be combined with BURST=1, if burst is
enabled on all channels.
A DONE event signals that one sample has been taken.
In this mode, the RESULTDONE event signals that enough conversions have taken place for an
oversampled result to get transferred into RAM. Note that both events may occur before the actual value has
been transferred into RAM by EasyDMA.
37.5.4 Scan mode
A channel is considered enabled if CH[n].PSELP is set. If more than one channel, CH[n], is enabled, the
ADC enters scan mode.
In scan mode, one SAMPLE task will trigger one conversion per enabled channel. The time it takes to
sample all channels is:
Total time < Sum(CH[x].tACQ+tCONV), x=0..enabled channels
A DONE event signals that one sample has been taken.
In this mode, the RESULTDONE event signals has the same meaning as DONE when no oversampling
takes place. Note that both events may occur before the actual values have been transferred into RAM by
EasyDMA.
Figure 99: Example of RAM placement (even RESULT.MAXCNT), channels 1, 2 and 5 enabled on page
360 provides an example of results placement in Data RAM, with an even RESULT.MAXCNT. In this
example, channels 1, 2 and 5 are enabled, all others are disabled.
Page 359
37 SAADC — Successive approximation analogto-digital converter
31
16 15
0
RESULT.PTR
CH[2] 1st result
CH[1] 1st result
RESULT.PTR + 4
CH[1] 2nd result
CH[5] 1st result
RESULT.PTR + 8
CH[5] 2nd result
CH[2] 2nd result
(…)
RESULT.PTR +
2*(RESULT.MAXCNT – 2)
CH[5] last result
CH[2] last result
Figure 99: Example of RAM placement (even RESULT.MAXCNT), channels 1, 2 and 5 enabled
Figure 100: Example of RAM placement (odd RESULT.MAXCNT), channels 1, 2 and 5 enabled on page
360 provides an example of results placement in Data RAM, with an odd RESULT.MAXCNT. In this
example, channels 1, 2 and 5 are enabled, all others are disabled. The last 32-bit word is populated only with
one 16-bit result.
31
16 15
0
RESULT.PTR
CH[2] 1st result
CH[1] 1st result
RESULT.PTR + 4
CH[1] 2nd result
CH[5] 1st result
RESULT.PTR + 8
CH[5] 2nd result
CH[2] 2nd result
(…)
RESULT.PTR +
2*(RESULT.MAXCNT – 1)
CH[5] last result
Figure 100: Example of RAM placement (odd RESULT.MAXCNT), channels 1, 2 and 5 enabled
37.6 EasyDMA
After configuring RESULT.PTR and RESULT.MAXCNT, the ADC resources are started by triggering the
START task. The ADC is using EasyDMA to store results in a Result buffer in RAM.
The Result buffer is located at the address specified in the RESULT.PTR register. The RESULT.PTR
register is double-buffered and it can be updated and prepared for the next START task immediately after
the STARTED event is generated. The size of the Result buffer is specified in the RESULT.MAXCNT register
and the ADC will generate an END event when it has filled up the Result buffer, see Figure 101: ADC on
page 361. Results are stored in little-endian byte order in Data RAM. Every sample will be sign extended to
16 bit before stored in the Result buffer.
The ADC is stopped by triggering the STOP task. The STOP task will terminate an ongoing sampling. The
ADC will generate a STOPPED event when it has stopped. If the ADC is already stopped when the STOP
task is triggered, the STOPPED event will still be generated.
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37 SAADC — Successive approximation analogto-digital converter
Data RAM
Result 0
Result 1
Result 2
Result 3
0
END
RAM
Sample and convert
0x20000010
0x20000012
0x20000020
0x20000022
RAM
START
SAMPLE
SAMPLE
RESULT.PTR = 0x20000020
START
SAMPLE
3
SAMPLE
RESULT.MAX
CNT
START
END_START = 1
RESULT.PTR = 0x20000000
2
RESULT.PTR = 0x20000010
Lifeline
1
Sample and convert
RAM
0x20000002
END
Sample and convert
RAM
STARTED
Sample and convert
STARTED
ADC
0
0x20000000
Figure 101: ADC
If the RESULT.PTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault
or RAM corruption. See Memory on page 23 for more information about the different memory regions.
The EasyDMA will have finished accessing the RAM when the END or STOPPED event has been
generated.
The RESULT.AMOUNT register can be read following an END event or a STOPPED event to see how many
results have been transferred to the Result buffer in RAM since the START task was triggered.
In Scan mode, the size of the Result buffer must be large enough to have room for a minimum one
result from each of the enabled channels. To secure this, RESULT.MAXCNT must be specified to
RESULT.MAXCNT >= "number of channels enabled". See Scan mode on page 359 for more information
about Scan mode.
37.7 Resistor ladder
The ADC has an internal resistor string for positive and negative input.
See Figure 102: Resistor ladder for positive input (negative input is equivalent, using RESN instead of
RESP) on page 362. The resistors are controlled in the CH[n].CONFIG.RESP and CH[n].CONFIG.RESN
registers.
Page 361
37 SAADC — Successive approximation analogto-digital converter
RESP = Pullup
R
Output
Input
R
RESP = Pulldown
Figure 102: Resistor ladder for positive input (negative input is equivalent, using RESN instead of
RESP)
37.8 Reference
The ADC can use two different references, controlled in the REFSEL field of the CH[n].CONFIG register.
These are:
•
•
Internal reference
VDD as reference
The internal reference results in an input range of ±0.6 V on the ADC core. VDD as reference results in an
input range of ±VDD/4 on the ADC core. The gain block can be used to change the effective input range of
the ADC.
Input range = (+- 0.6 V or +-VDD/4)/Gain
For example, choosing VDD as reference, single ended input (grounded negative input), and a gain of 1/4
the input range will be:
Input range = (VDD/4)/(1/4) = VDD
With internal reference, single ended input (grounded negative input), and a gain of 1/6 the input range will
be:
Input range = (0.6 V)/(1/6) = 3.6 V
The AIN0-AIN7 inputs cannot exceed VDD, or be lower than VSS.
37.9 Acquisition time
To sample the input voltage, the ADC connects a capacitor to the input.
For illustration, see Figure 103: Simplified ADC sample network on page 363. The acquisition time
indicates how long the capacitor is connected, see TACQ field in CH[n].CONFIG register. The required
acquisition time depends on the source (Rsource) resistance. For high source resistance the acquisition time
should be increased, see Table 88: Acquisition time on page 363.
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37 SAADC — Successive approximation analogto-digital converter
ADC
Rsource
TACQ
Figure 103: Simplified ADC sample network
Table 88: Acquisition time
TACQ [µs]
3
5
10
15
20
40
Maximum source resistance [kOhm]
10
40
100
200
400
800
37.10 Limits event monitoring
A channel can be event monitored by configuring limit register CH[n].LIMIT.
If the conversion result is higher than the defined high limit, or lower than the defined low limit, the
appropriate event will get fired.
VIN
CH[n].LIMIT.HIGH
CH[n].LIMIT.LOW
t
EVENTS_CH[n].LIMITL
EVENTS_CH[n].LIMITH
EVENTS_CH[n].LIMITH
EVENTS_CH[n].LIMITH
events
Figure 104: Example of limits monitoring on channel 'n'
Note that when setting the limits, CH[n].LIMIT.HIGH shall always be higher than or equal to
CH[n].LIMIT.LOW . In other words, an event can be fired only when the input signal has been sampled
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37 SAADC — Successive approximation analogto-digital converter
outside of the defined limits. It is not possible to fire an event when the input signal is inside a defined range
by swapping high and low limits.
The comparison to limits always takes place, there is no need to enable it. If comparison is not required on a
channel, the software shall simply ignore the related events. In that situation, the value of the limits registers
is irrelevant, so it does not matter if CH[n].LIMIT.LOW is lower than CH[n].LIMIT.HIGH or not.
37.11 Registers
Table 89: Instances
Base address
Peripheral
Instance
Description
0x40007000
SAADC
SAADC
Analog to digital converter
Configuration
Table 90: Register Overview
Register
Offset
Description
TASKS_START
0x000
Start the ADC and prepare the result buffer in RAM
TASKS_SAMPLE
0x004
Take one ADC sample, if scan is enabled all channels are sampled
TASKS_STOP
0x008
Stop the ADC and terminate any on-going conversion
TASKS_CALIBRATEOFFSET0x00C
Starts offset auto-calibration
EVENTS_STARTED
0x100
The ADC has started
EVENTS_END
0x104
The ADC has filled up the Result buffer
EVENTS_DONE
0x108
A conversion task has been completed. Depending on the mode, multiple conversions might be
EVENTS_RESULTDONE
0x10C
needed for a result to be transferred to RAM.
A result is ready to get transferred to RAM.
EVENTS_CALIBRATEDONE0x110
Calibration is complete
EVENTS_STOPPED
0x114
The ADC has stopped
EVENTS_CH[0].LIMITH
0x118
Last results is equal or above CH[0].LIMIT.HIGH
EVENTS_CH[0].LIMITL
0x11C
Last results is equal or below CH[0].LIMIT.LOW
EVENTS_CH[1].LIMITH
0x120
Last results is equal or above CH[1].LIMIT.HIGH
EVENTS_CH[1].LIMITL
0x124
Last results is equal or below CH[1].LIMIT.LOW
EVENTS_CH[2].LIMITH
0x128
Last results is equal or above CH[2].LIMIT.HIGH
EVENTS_CH[2].LIMITL
0x12C
Last results is equal or below CH[2].LIMIT.LOW
EVENTS_CH[3].LIMITH
0x130
Last results is equal or above CH[3].LIMIT.HIGH
EVENTS_CH[3].LIMITL
0x134
Last results is equal or below CH[3].LIMIT.LOW
EVENTS_CH[4].LIMITH
0x138
Last results is equal or above CH[4].LIMIT.HIGH
EVENTS_CH[4].LIMITL
0x13C
Last results is equal or below CH[4].LIMIT.LOW
EVENTS_CH[5].LIMITH
0x140
Last results is equal or above CH[5].LIMIT.HIGH
EVENTS_CH[5].LIMITL
0x144
Last results is equal or below CH[5].LIMIT.LOW
EVENTS_CH[6].LIMITH
0x148
Last results is equal or above CH[6].LIMIT.HIGH
EVENTS_CH[6].LIMITL
0x14C
Last results is equal or below CH[6].LIMIT.LOW
EVENTS_CH[7].LIMITH
0x150
Last results is equal or above CH[7].LIMIT.HIGH
EVENTS_CH[7].LIMITL
0x154
Last results is equal or below CH[7].LIMIT.LOW
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
STATUS
0x400
Status
ENABLE
0x500
Enable or disable ADC
CH[0].PSELP
0x510
Input positive pin selection for CH[0]
CH[0].PSELN
0x514
Input negative pin selection for CH[0]
CH[0].CONFIG
0x518
Input configuration for CH[0]
CH[0].LIMIT
0x51C
High/low limits for event monitoring a channel
CH[1].PSELP
0x520
Input positive pin selection for CH[1]
CH[1].PSELN
0x524
Input negative pin selection for CH[1]
CH[1].CONFIG
0x528
Input configuration for CH[1]
CH[1].LIMIT
0x52C
High/low limits for event monitoring a channel
CH[2].PSELP
0x530
Input positive pin selection for CH[2]
Page 364
37 SAADC — Successive approximation analogto-digital converter
Register
Offset
Description
CH[2].PSELN
0x534
Input negative pin selection for CH[2]
CH[2].CONFIG
0x538
Input configuration for CH[2]
CH[2].LIMIT
0x53C
High/low limits for event monitoring a channel
CH[3].PSELP
0x540
Input positive pin selection for CH[3]
CH[3].PSELN
0x544
Input negative pin selection for CH[3]
CH[3].CONFIG
0x548
Input configuration for CH[3]
CH[3].LIMIT
0x54C
High/low limits for event monitoring a channel
CH[4].PSELP
0x550
Input positive pin selection for CH[4]
CH[4].PSELN
0x554
Input negative pin selection for CH[4]
CH[4].CONFIG
0x558
Input configuration for CH[4]
CH[4].LIMIT
0x55C
High/low limits for event monitoring a channel
CH[5].PSELP
0x560
Input positive pin selection for CH[5]
CH[5].PSELN
0x564
Input negative pin selection for CH[5]
CH[5].CONFIG
0x568
Input configuration for CH[5]
CH[5].LIMIT
0x56C
High/low limits for event monitoring a channel
CH[6].PSELP
0x570
Input positive pin selection for CH[6]
CH[6].PSELN
0x574
Input negative pin selection for CH[6]
CH[6].CONFIG
0x578
Input configuration for CH[6]
CH[6].LIMIT
0x57C
High/low limits for event monitoring a channel
CH[7].PSELP
0x580
Input positive pin selection for CH[7]
CH[7].PSELN
0x584
Input negative pin selection for CH[7]
CH[7].CONFIG
0x588
Input configuration for CH[7]
CH[7].LIMIT
0x58C
High/low limits for event monitoring a channel
RESOLUTION
0x5F0
Resolution configuration
OVERSAMPLE
0x5F4
Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is
SAMPLERATE
0x5F8
Controls normal or continuous sample rate
RESULT.PTR
0x62C
Data pointer
RESULT.MAXCNT
0x630
Maximum number of buffer words to transfer
RESULT.AMOUNT
0x634
Number of buffer words transferred since last START
applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.
37.11.1 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
RW Field
A
RW STARTED
0
Value Id
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for STARTED event
See EVENTS_STARTED
B
Disabled
0
Disable
Enabled
1
Enable
RW END
Enable or disable interrupt for END event
See EVENTS_END
C
Disabled
0
Disable
Enabled
1
Enable
RW DONE
Enable or disable interrupt for DONE event
See EVENTS_DONE
D
Disabled
0
Disable
Enabled
1
Enable
RW RESULTDONE
Enable or disable interrupt for RESULTDONE event
See EVENTS_RESULTDONE
Disabled
0
Disable
Enabled
1
Enable
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37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
RW Field
E
RW CALIBRATEDONE
0
Value Id
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for CALIBRATEDONE event
See EVENTS_CALIBRATEDONE
F
Disabled
0
Disable
Enabled
1
Enable
RW STOPPED
Enable or disable interrupt for STOPPED event
See EVENTS_STOPPED
G
Disabled
0
Disable
Enabled
1
Enable
RW CH0LIMITH
Enable or disable interrupt for CH[0].LIMITH event
See EVENTS_CH[0].LIMITH
H
Disabled
0
Disable
Enabled
1
Enable
RW CH0LIMITL
Enable or disable interrupt for CH[0].LIMITL event
See EVENTS_CH[0].LIMITL
I
Disabled
0
Disable
Enabled
1
Enable
RW CH1LIMITH
Enable or disable interrupt for CH[1].LIMITH event
See EVENTS_CH[1].LIMITH
J
Disabled
0
Disable
Enabled
1
Enable
RW CH1LIMITL
Enable or disable interrupt for CH[1].LIMITL event
See EVENTS_CH[1].LIMITL
K
Disabled
0
Disable
Enabled
1
Enable
RW CH2LIMITH
Enable or disable interrupt for CH[2].LIMITH event
See EVENTS_CH[2].LIMITH
L
Disabled
0
Disable
Enabled
1
Enable
RW CH2LIMITL
Enable or disable interrupt for CH[2].LIMITL event
See EVENTS_CH[2].LIMITL
M
Disabled
0
Disable
Enabled
1
Enable
RW CH3LIMITH
Enable or disable interrupt for CH[3].LIMITH event
See EVENTS_CH[3].LIMITH
N
Disabled
0
Disable
Enabled
1
Enable
RW CH3LIMITL
Enable or disable interrupt for CH[3].LIMITL event
See EVENTS_CH[3].LIMITL
O
Disabled
0
Disable
Enabled
1
Enable
RW CH4LIMITH
Enable or disable interrupt for CH[4].LIMITH event
See EVENTS_CH[4].LIMITH
P
Disabled
0
Disable
Enabled
1
Enable
RW CH4LIMITL
Enable or disable interrupt for CH[4].LIMITL event
See EVENTS_CH[4].LIMITL
Q
Disabled
0
Disable
Enabled
1
Enable
RW CH5LIMITH
Enable or disable interrupt for CH[5].LIMITH event
See EVENTS_CH[5].LIMITH
Page 366
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
R
RW Field
0
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
RW CH5LIMITL
Enable or disable interrupt for CH[5].LIMITL event
See EVENTS_CH[5].LIMITL
S
Disabled
0
Disable
Enabled
1
Enable
RW CH6LIMITH
Enable or disable interrupt for CH[6].LIMITH event
See EVENTS_CH[6].LIMITH
T
Disabled
0
Disable
Enabled
1
Enable
RW CH6LIMITL
Enable or disable interrupt for CH[6].LIMITL event
See EVENTS_CH[6].LIMITL
U
Disabled
0
Disable
Enabled
1
Enable
RW CH7LIMITH
Enable or disable interrupt for CH[7].LIMITH event
See EVENTS_CH[7].LIMITH
V
Disabled
0
Disable
Enabled
1
Enable
RW CH7LIMITL
Enable or disable interrupt for CH[7].LIMITL event
See EVENTS_CH[7].LIMITL
Disabled
0
Disable
Enabled
1
Enable
37.11.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
RW Field
A
RW STARTED
0
Value Id
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for STARTED event
See EVENTS_STARTED
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW END
Write '1' to Enable interrupt for END event
See EVENTS_END
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DONE
Write '1' to Enable interrupt for DONE event
See EVENTS_DONE
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RESULTDONE
Write '1' to Enable interrupt for RESULTDONE event
See EVENTS_RESULTDONE
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Page 367
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
RW Field
E
RW CALIBRATEDONE
0
Value Id
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for CALIBRATEDONE event
See EVENTS_CALIBRATEDONE
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Enable interrupt for STOPPED event
See EVENTS_STOPPED
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH0LIMITH
Write '1' to Enable interrupt for CH[0].LIMITH event
See EVENTS_CH[0].LIMITH
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH0LIMITL
Write '1' to Enable interrupt for CH[0].LIMITL event
See EVENTS_CH[0].LIMITL
I
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH1LIMITH
Write '1' to Enable interrupt for CH[1].LIMITH event
See EVENTS_CH[1].LIMITH
J
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH1LIMITL
Write '1' to Enable interrupt for CH[1].LIMITL event
See EVENTS_CH[1].LIMITL
K
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH2LIMITH
Write '1' to Enable interrupt for CH[2].LIMITH event
See EVENTS_CH[2].LIMITH
L
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH2LIMITL
Write '1' to Enable interrupt for CH[2].LIMITL event
See EVENTS_CH[2].LIMITL
M
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH3LIMITH
Write '1' to Enable interrupt for CH[3].LIMITH event
See EVENTS_CH[3].LIMITH
N
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH3LIMITL
Write '1' to Enable interrupt for CH[3].LIMITL event
See EVENTS_CH[3].LIMITL
O
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH4LIMITH
Write '1' to Enable interrupt for CH[4].LIMITH event
Page 368
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
RW Field
0
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_CH[4].LIMITH
P
RW CH4LIMITL
Write '1' to Enable interrupt for CH[4].LIMITL event
See EVENTS_CH[4].LIMITL
Q
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH5LIMITH
Write '1' to Enable interrupt for CH[5].LIMITH event
See EVENTS_CH[5].LIMITH
R
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH5LIMITL
Write '1' to Enable interrupt for CH[5].LIMITL event
See EVENTS_CH[5].LIMITL
S
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH6LIMITH
Write '1' to Enable interrupt for CH[6].LIMITH event
See EVENTS_CH[6].LIMITH
T
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH6LIMITL
Write '1' to Enable interrupt for CH[6].LIMITL event
See EVENTS_CH[6].LIMITL
U
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH7LIMITH
Write '1' to Enable interrupt for CH[7].LIMITH event
See EVENTS_CH[7].LIMITH
V
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH7LIMITL
Write '1' to Enable interrupt for CH[7].LIMITL event
See EVENTS_CH[7].LIMITL
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
37.11.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
RW Field
A
RW STARTED
0
Value Id
Value
Description
Write '1' to Disable interrupt for STARTED event
See EVENTS_STARTED
Clear
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Disable
Page 369
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
B
RW Field
0
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW END
Write '1' to Disable interrupt for END event
See EVENTS_END
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DONE
Write '1' to Disable interrupt for DONE event
See EVENTS_DONE
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RESULTDONE
Write '1' to Disable interrupt for RESULTDONE event
See EVENTS_RESULTDONE
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CALIBRATEDONE
Write '1' to Disable interrupt for CALIBRATEDONE event
See EVENTS_CALIBRATEDONE
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Disable interrupt for STOPPED event
See EVENTS_STOPPED
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH0LIMITH
Write '1' to Disable interrupt for CH[0].LIMITH event
See EVENTS_CH[0].LIMITH
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH0LIMITL
Write '1' to Disable interrupt for CH[0].LIMITL event
See EVENTS_CH[0].LIMITL
I
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH1LIMITH
Write '1' to Disable interrupt for CH[1].LIMITH event
See EVENTS_CH[1].LIMITH
J
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH1LIMITL
Write '1' to Disable interrupt for CH[1].LIMITL event
See EVENTS_CH[1].LIMITL
K
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH2LIMITH
Write '1' to Disable interrupt for CH[2].LIMITH event
See EVENTS_CH[2].LIMITH
Clear
1
Disable
Disabled
0
Read: Disabled
Page 370
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
L
RW Field
0
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Read: Enabled
RW CH2LIMITL
Write '1' to Disable interrupt for CH[2].LIMITL event
See EVENTS_CH[2].LIMITL
M
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH3LIMITH
Write '1' to Disable interrupt for CH[3].LIMITH event
See EVENTS_CH[3].LIMITH
N
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH3LIMITL
Write '1' to Disable interrupt for CH[3].LIMITL event
See EVENTS_CH[3].LIMITL
O
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH4LIMITH
Write '1' to Disable interrupt for CH[4].LIMITH event
See EVENTS_CH[4].LIMITH
P
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH4LIMITL
Write '1' to Disable interrupt for CH[4].LIMITL event
See EVENTS_CH[4].LIMITL
Q
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH5LIMITH
Write '1' to Disable interrupt for CH[5].LIMITH event
See EVENTS_CH[5].LIMITH
R
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH5LIMITL
Write '1' to Disable interrupt for CH[5].LIMITL event
See EVENTS_CH[5].LIMITL
S
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH6LIMITH
Write '1' to Disable interrupt for CH[6].LIMITH event
See EVENTS_CH[6].LIMITH
T
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH6LIMITL
Write '1' to Disable interrupt for CH[6].LIMITL event
See EVENTS_CH[6].LIMITL
U
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH7LIMITH
Write '1' to Disable interrupt for CH[7].LIMITH event
See EVENTS_CH[7].LIMITH
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Page 371
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
RW Field
V
RW CH7LIMITL
0
Value Id
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for CH[7].LIMITL event
See EVENTS_CH[7].LIMITL
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
37.11.4 STATUS
Address offset: 0x400
Status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Ready
0
ADC is ready. No on-going conversion.
Busy
1
ADC is busy. Conversion in progress.
STATUS
Status
37.11.5 ENABLE
Address offset: 0x500
Enable or disable ADC
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable ADC
Enabled
1
Enable ADC
Enable or disable ADC
When enabled, the ADC will acquire access to the analog input
pins specified in the CH[n].PSELP and CH[n].PSELN registers.
37.11.6 CH[0].PSELP
Address offset: 0x510
Input positive pin selection for CH[0]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog positive input channel
Page 372
37 SAADC — Successive approximation analogto-digital converter
37.11.7 CH[0].PSELN
Address offset: 0x514
Input negative pin selection for CH[0]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog negative input, enables differential channel
37.11.8 CH[0].CONFIG
Address offset: 0x518
Input configuration for CH[0]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
B
C
D
E
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Internal reference (0.6 V)
VDD1_4
1
VDD/4 as reference
Positive channel resistor control
RW RESN
Negative channel resistor control
RW GAIN
Gain control
RW REFSEL
Reference control
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
Page 373
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
F
RW Field
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
40us
5
40 us
SE
0
Diff
1
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
G
Differential
RW BURST
Enable burst mode
samples as fast as it can, and sends the average to Data RAM.
37.11.9 CH[0].LIMIT
Address offset: 0x51C
High/low limits for event monitoring a channel
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.10 CH[1].PSELP
Address offset: 0x520
Input positive pin selection for CH[1]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog positive input channel
37.11.11 CH[1].PSELN
Address offset: 0x524
Input negative pin selection for CH[1]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
Analog negative input, enables differential channel
Page 374
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
37.11.12 CH[1].CONFIG
Address offset: 0x528
Input configuration for CH[1]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
B
C
D
E
0
F
E E E
D
C C C
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Internal reference (0.6 V)
VDD1_4
1
VDD/4 as reference
Positive channel resistor control
RW RESN
Negative channel resistor control
RW GAIN
Gain control
RW REFSEL
Reference control
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
F
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
SE
0
Diff
1
Disabled
0
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
G
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Differential
RW BURST
Enable burst mode
Burst mode is disabled (normal operation)
Page 375
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
samples as fast as it can, and sends the average to Data RAM.
37.11.13 CH[1].LIMIT
Address offset: 0x52C
High/low limits for event monitoring a channel
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.14 CH[2].PSELP
Address offset: 0x530
Input positive pin selection for CH[2]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog positive input channel
37.11.15 CH[2].PSELN
Address offset: 0x534
Input negative pin selection for CH[2]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
Analog negative input, enables differential channel
Page 376
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
VDD
9
VDD
37.11.16 CH[2].CONFIG
Address offset: 0x538
Input configuration for CH[2]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
B
C
D
E
0
F
E E E
D
C C C
B B
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Internal reference (0.6 V)
VDD1_4
1
VDD/4 as reference
Positive channel resistor control
RW RESN
Negative channel resistor control
RW GAIN
Gain control
RW REFSEL
Reference control
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
F
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
SE
0
Diff
1
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
G
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Differential
RW BURST
Enable burst mode
samples as fast as it can, and sends the average to Data RAM.
37.11.17 CH[2].LIMIT
Address offset: 0x53C
High/low limits for event monitoring a channel
Page 377
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.18 CH[3].PSELP
Address offset: 0x540
Input positive pin selection for CH[3]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog positive input channel
37.11.19 CH[3].PSELN
Address offset: 0x544
Input negative pin selection for CH[3]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog negative input, enables differential channel
37.11.20 CH[3].CONFIG
Address offset: 0x548
Input configuration for CH[3]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
0
Value Id
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Positive channel resistor control
Page 378
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
B
C
D
E
RW Field
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Internal reference (0.6 V)
VDD1_4
1
VDD/4 as reference
RW RESN
Negative channel resistor control
RW GAIN
Gain control
RW REFSEL
Reference control
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
F
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
SE
0
Diff
1
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
G
Differential
RW BURST
Enable burst mode
samples as fast as it can, and sends the average to Data RAM.
37.11.21 CH[3].LIMIT
Address offset: 0x54C
High/low limits for event monitoring a channel
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.22 CH[4].PSELP
Address offset: 0x550
Input positive pin selection for CH[4]
Page 379
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog positive input channel
37.11.23 CH[4].PSELN
Address offset: 0x554
Input negative pin selection for CH[4]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog negative input, enables differential channel
37.11.24 CH[4].CONFIG
Address offset: 0x558
Input configuration for CH[4]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
B
C
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Positive channel resistor control
RW RESN
Negative channel resistor control
RW GAIN
Gain control
Page 380
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
D
E
RW Field
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Internal reference (0.6 V)
VDD1_4
1
VDD/4 as reference
RW REFSEL
Reference control
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
F
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
SE
0
Diff
1
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
G
Differential
RW BURST
Enable burst mode
samples as fast as it can, and sends the average to Data RAM.
37.11.25 CH[4].LIMIT
Address offset: 0x55C
High/low limits for event monitoring a channel
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.26 CH[5].PSELP
Address offset: 0x560
Input positive pin selection for CH[5]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
Analog positive input channel
Page 381
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
37.11.27 CH[5].PSELN
Address offset: 0x564
Input negative pin selection for CH[5]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog negative input, enables differential channel
37.11.28 CH[5].CONFIG
Address offset: 0x568
Input configuration for CH[5]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
B
C
D
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Positive channel resistor control
RW RESN
Negative channel resistor control
RW GAIN
Gain control
RW REFSEL
Reference control
Internal reference (0.6 V)
Page 382
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
E
RW Field
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
VDD1_4
1
VDD/4 as reference
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
F
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
SE
0
Diff
1
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
G
Differential
RW BURST
Enable burst mode
samples as fast as it can, and sends the average to Data RAM.
37.11.29 CH[5].LIMIT
Address offset: 0x56C
High/low limits for event monitoring a channel
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.30 CH[6].PSELP
Address offset: 0x570
Input positive pin selection for CH[6]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog positive input channel
37.11.31 CH[6].PSELN
Address offset: 0x574
Input negative pin selection for CH[6]
Page 383
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog negative input, enables differential channel
37.11.32 CH[6].CONFIG
Address offset: 0x578
Input configuration for CH[6]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
B
C
D
E
0
F
E E E
D
C C C
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Internal reference (0.6 V)
VDD1_4
1
VDD/4 as reference
Positive channel resistor control
RW RESN
Negative channel resistor control
RW GAIN
Gain control
RW REFSEL
Reference control
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
F
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
SE
0
Diff
1
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
Differential
Page 384
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
G
RW BURST
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
Enable burst mode
samples as fast as it can, and sends the average to Data RAM.
37.11.33 CH[6].LIMIT
Address offset: 0x57C
High/low limits for event monitoring a channel
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.34 CH[7].PSELP
Address offset: 0x580
Input positive pin selection for CH[7]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog positive input channel
37.11.35 CH[7].PSELN
Address offset: 0x584
Input negative pin selection for CH[7]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
Analog negative input, enables differential channel
Page 385
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
37.11.36 CH[7].CONFIG
Address offset: 0x588
Input configuration for CH[7]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
B
C
D
E
0
F
E E E
D
C C C
B B
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Internal reference (0.6 V)
VDD1_4
1
VDD/4 as reference
Positive channel resistor control
RW RESN
Negative channel resistor control
RW GAIN
Gain control
RW REFSEL
Reference control
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
F
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
SE
0
Diff
1
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
G
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Differential
RW BURST
Enable burst mode
samples as fast as it can, and sends the average to Data RAM.
37.11.37 CH[7].LIMIT
Address offset: 0x58C
Page 386
37 SAADC — Successive approximation analogto-digital converter
High/low limits for event monitoring a channel
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.38 RESOLUTION
Address offset: 0x5F0
Resolution configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000001
Id
RW Field
A
RW VAL
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value
Description
Set the resolution
8bit
0
8 bit
10bit
1
10 bit
12bit
2
12 bit
14bit
3
14 bit
37.11.39 OVERSAMPLE
Address offset: 0x5F4
Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is
applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW OVERSAMPLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Bypass
0
Bypass oversampling
Over2x
1
Oversample 2x
Over4x
2
Oversample 4x
Over8x
3
Oversample 8x
Over16x
4
Oversample 16x
Over32x
5
Oversample 32x
Over64x
6
Oversample 64x
Over128x
7
Oversample 128x
Over256x
8
Oversample 256x
Oversample control
37.11.40 SAMPLERATE
Address offset: 0x5F8
Controls normal or continuous sample rate
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
Reset 0x00000000
Id
RW Field
A
RW CC
B
RW MODE
0
Value Id
A A A A A A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[80..2047]
Capture and compare value. Sample rate is 16 MHz/CC
Select mode for sample rate control
Task
0
Rate is controlled from SAMPLE task
Timers
1
Rate is controlled from local timer (use CC to control the rate)
Page 387
37 SAADC — Successive approximation analogto-digital converter
37.11.41 RESULT.PTR
Address offset: 0x62C
Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Data pointer
37.11.42 RESULT.MAXCNT
Address offset: 0x630
Maximum number of buffer words to transfer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of buffer words to transfer
37.11.43 RESULT.AMOUNT
Address offset: 0x634
Number of buffer words transferred since last START
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of buffer words transferred since last START. This
register can be read after an END or STOPPED event.
37.12 Electrical specification
37.12.1 SAADC Electrical Specification
Symbol
Description
Min.
Typ.
DNL
Differential non-linearity, 10-bit resolution
-0.95
<1
Max.
Units
LSB
INL
Integral non-linearity, 10-bit resolution
1
LSB
VOS
Differential offset error (calibrated), 10-bit resolution a
+-2
LSB
CEG
Gain error temperature coefficient
0.02
fSAMPLE
Maximum sampling rate
tACQ,10k
Acquisition time (configurable), source Resistance <= 10kOhm
3
µs
tACQ,40k
Acquisition time (configurable), source Resistance <= 40kOhm
5
µs
tACQ,100k
Acquisition time (configurable), source Resistance <= 100kOhm
10
µs
tACQ,200k
Acquisition time (configurable), source Resistance <= 200kOhm
15
µs
tACQ,400k
Acquisition time (configurable), source Resistance <= 400kOhm
20
µs
tACQ,800k
Acquisition time (configurable), source Resistance <= 800kOhm
40
µs
tCONV
Conversion time
<2
µs
IADC,CONV
ADC current during ACQuisition and CONVersion
700
µA
IADC,IDLE
Idle current, when not sampling, excluding clock sources and
<5
µA
%/◦C
200
kHz
regulator base currents33
a
33
Digital output code at zero volt differential input.
When tACQ is 10us or longer, and if DC/DC is active, it will be allowed to work in refresh mode if no other
resource is requiring a high quality power supply from 1V3. If tACQ is smaller than 10us and DC/DC is active,
Page 388
37 SAADC — Successive approximation analogto-digital converter
Symbol
Description
Min.
Max.
Units
EG1/6
Errorb for Gain = 1/6
-3
Typ.
3
%
EG1/4
Errorb for Gain = 1/4
-3
3
%
EG1/2
Errorb for Gain = 1/2
-3
4
%
EG1
Errorb for Gain = 1
-3
4
%
CSAMPLE
Sample and hold capacitance at maximum gain34
2.5
pF
RINPUT
Input resistance
>1
MΩ
ENOB
Effective number of bits, differential mode, 12-bit resolution,
9
Bit
56
dB
70
dBc
160
kΩ
1/1 gain, 3 µs acquisition time, crystal HFCLK, 200 ksps
SNDR
Peak signal to noise and distortion ratio, differential mode, 12bit resolution, 1/1 gain, 3 µs acquisition time, crystal HFCLK, 200
ksps
SFDR
Spurious free dynamic range, differential mode, 12-bit
resolution, 1/1 gain, 3 µs acquisition time, crystal HFCLK, 200
ksps
RLADDER
Ladder resistance
CH[n].CONFIG.RESP
ADC
RLADDER
RSOURCE
PAD
CPAD
PSEL
RINPUT
TACQ
RLADDER
CSAMPLE
CH[n].CONFIG.RESP
Figure 105: Model of SAADC input (one channel)
INL [LSB10b]
Note: SAADC average current calculation for a given application is based on the sample period, conversion
and acquisition time ( tconv and tACQ) and conversion and idle current (IADC,CONV and IADC,IDLE). For example,
sampling at 4kHz gives a sample period of 250µs. The average current consumption would then be:
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0
64 128 192 256 320 384 448 512 576 640 704 768 832 896 960
Output code
Figure 106: ADC INL vs Output Code
b
34
refresh mode will not be allowed, and it will remain in normal mode from the START task to the STOPPED event.
So depending on tACQ and other resources' needs, the appropriate base current needs to be taken into account.
Does not include temperature drift
Maximum gain corresponds to highest capacitance.
Page 389
DNL [LSB10b]
37 SAADC — Successive approximation analogto-digital converter
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0
64 128 192 256 320 384 448 512 576 640 704 768 832 896 960
Output code
Figure 107: ADC DNL vs Output Code
0
12-bit resolution
Differential mode
Internal reference
200kHz sampling frequency
3µs aquisition time
4096 point FFT (EasyDMA)
SNDR = 56.6 dB
ENOB = 9.1 bit
SFDR = 72 dBc
-20
Magnitude [dBFS]
-40
-60
-80
-100
-120
0
10
20
30
40
50
60
70
80
90
100
Frequency [kHz]
Figure 108: FFT of a 2.8 kHz sine at 200 ksps ()
37.13 Performance factors
Clock jitter, affecting sample timing accuracy, and circuit noise can affect ADC performance.
Jitter can be between START tasks or from START task to acquisition. START timer accuracy and startup
times of regulators and references will contribute to variability. Sources of circuit noise may include CPU
activity and the DC/DC regulator. Best ADC performance is achieved using START timing based on the
TIMER module, HFXO clock source, and Constant Latency mode.
Page 390
38 COMP — Comparator
38 COMP — Comparator
The Comparator (COMP) compares the input voltage (VIN+) that is derived from an analog input pin
selected via the PSEL register against a second input voltage (VIN-) that can be derived from multiple
sources depending on operation mode.
Listed here are the main features for COMP:
•
•
Input range from 0 V to VDD
Single-ended mode
•
• Fully flexible hysteresis using a 64-level reference ladder
Differential mode
•
• Configurable 50 mV hysteresis
Reference inputs:
•
•
•
Three operation modes: low power, normal and high-speed
Single-pin capacitive sensor support
Event generation on output changes
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
UP event on VIN- > VIN+
DOWN event on VIN- < VIN+
CROSS event on VIN+ and VIN- crossing
READY event on core and internal reference (if used) ready
AIN0
•
•
•
•
AIN1
•
•
•
VDD
External reference from AIN0 to AIN1 (between 0 V and VDD)
Internal references 1.2 V, 1.8 V and 2.4 V
PSEL
MUX
SAMPLE
STOP
START
ISOURCE
VIN+
+
Comparator
core
MODE
VIN-
HYST
RESULT
Output
0 = BELOW (VIN+ < VIN-)
1 = ABOVE (VIN+ > VIN-)
READY
DOWN
UP
CROSS
Figure 109: Comparator overview
Important: COMP cannot be used (STARTed) at the same time as LPCOMP. Only one comparator
can be used at a time.
The COMP is started by triggering the START task, and stopped by triggering the STOP task. After a start35
up time of tCOMP,START the COMP will generate a READY event to indicate that the comparator is ready
35
See tPROPDLY,LP, tPROPDLY,N, tPROPDLY,HS, ICOMP,LP, ICOMP,N and ICOMP,HS in Electrical parameters for
more information about COMP speed and power characteristics related to these different modes.
Page 391
38 COMP — Comparator
to use and the output of the COMP is correct. When the COMP module is started, events will be generated
every time VIN+ crosses VIN-.
VIN- can be derived directly from AIN0 or AIN1 in differential mode, or VREF in single-ended mode. VUP
and VDOWN thresholds can be set to implement a hysteresis on VIN- using the Reference Ladder. VREF
can be derived from VDD, AIN0, AIN1 or internal 1.2V, 1.8V and 2.4V references.
An upward crossing will generate an UP event and a downward crossing will generate a DOWN event. The
CROSS event will be generated every time there is a crossing, independent of direction.
An optional hysteresis on VIN+ and VIN- can be enabled when the module is used in differential mode
through the HYST register. In single ended mode the two reference ladders (VUP and VDOWN, see Figure
112: Comparator in single-ended mode on page 394) will be used instead of the hysteresis mechanism
configured in HYST.
This hysteresis is in the order of magnitude of 50 mV, and shall prevent noise on the signal to create
unwanted events. See Figure 113: Hysteresis example where VIN+ starts below VUP on page 394 for
illustration of the effect of an active hysteresis on a noisy input signal.
The COMP can be configured to operate in two main operation modes, differential mode and single-ended
mode, see MODE register for more information.
The COMP can, for both main operation modes, operate in different speed and power consumption modes,
see MODE register. High-speed mode will consume more power compared to low-power mode, and lowpower mode will result in slower response time compared to high-speed mode.
The immediate value of the COMP can be sampled to the RESULT register by triggering the SAMPLE task.
A selectable current can be applied (ISOURCE register) on the currently selected AINx line. Enabling the
block creates a feedback path around the comparator, forming a relaxation oscillator. The circuit will sink
current from VIN+ when the comparator output is high, and source current into VIN+ when the comparator
output is low. The frequency of the oscillator is dependent on the capacitance at the analog input pin, the
reference voltages and the value of the current source. In this mode, only a capacitive sensor needs to be
attached between the analog input pin and ground. With a selected current of 10 µA, VUP-VDOWN equal to
1 V, and an external capacity of typically 10 pF, the resulting oscillation frequency is around 500 kHz.
The frequency of the oscillator can be calculated as
f_OSC = I_SOURCE / (2C∙(VUP-VDOWN) )
38.1 Shared resources
The COMP shares analog resources with the SAADC and LPCOMP peripherals.
While it is possible to use SAADC at the same time as COMP or LPCOMP, COMP and LPCOMP are
mutually exclusive: enabling one will automatically disable the other. In addition, when using SAADC and
COMP or LPCOMP simultaneously, it is not possible to select the same analog input pin for both modules.
Important: The COMP peripheral shall not be disabled (by writing to the ENABLE register) before
the peripheral has stopped. Failing to do so may result in unpredictable behaviour.
38.2 Differential mode
In differential mode, the reference input VIN- is derived directly from one of the AINx pins.
In this mode, the impedance on VIN-'s signal path is equal to the impedance on VIN+'s signal path. See
ZCOMPVINP and ZCOMPVINND for more information. In differential mode, the PSEL, MODE and EXTREFSEL
registers must be configured before the COMP is enabled via the ENABLE register. When HYST is turned
on while in this mode, the Output of the comparator (and associated events) will change from ABOVE
to BELOW whenever VIN+ becomes smaller than (VIN- - (VDIFFHYST / 2) ). Similarly, it will change from
BELOW to ABOVE whenever VIN+ becomes larger than (VIN- + (VDIFFHYST / 2) ), as illustrated in Figure
111: Hysteresis enabled in differential mode on page 393.
Page 392
38 COMP — Comparator
PSEL
MUX
EXTREFSEL
MUX
SAMPLE
STOP
START
ISOURCE
AIN1
AIN0
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
Restriction: Depending on the device, not all the analog inputs may be available for each MUX.
VIN+
+
VIN-
Comparator
core
MODE
RESULT
Output
0 = BELOW (VIN+ < VIN-)
1 = ABOVE (VIN+ > VIN-)
READY
DOWN
UP
CROSS
Figure 110: Comparator in differential mode
VIN+
VIN- + (VDIFFHYST / 2)
VIN- - (VDIFFHYST / 2)
t
Output
ABOVE
(VIN+ > (VIN- + VDIFFHYST /2))
BELOW
(VIN+ < (VIN- - VDIFFHYST /2))
ABOVE
(VIN+ > (VIN- + VDIFFHYST /2))
BELOW
Figure 111: Hysteresis enabled in differential mode
38.3 Single-ended mode
In single-ended mode, VIN- is derived from the Reference Ladder.
The Reference Ladder uses the reference voltage VREF to derive two new voltage references, VUP and
VDOWN. VUP and VDOWN are configured via THUP and THDOWN in the TH register. VREF can be
sourced from any of the available references sources as illustrated in Figure 112: Comparator in singleended mode on page 394. This is configured via EXTREFSEL and REFSEL.
When the comparator core detects that VIN+ > VIN-, i.e. ABOVE as per the RESULT register, VIN- will
switch to VDOWN. When VIN- falls below VIN- again, VIN- will be switched back to VUP. By specifying VUP
larger than VDOWN, a hysteresis as illustrated in Figure 113: Hysteresis example where VIN+ starts below
VUP on page 394 and Figure 114: Hysteresis example where VIN+ starts above VUP on page 395 can
be generated. In single-ended mode, the PSEL, MODE, EXTREFSEL, REFSEL and TH registers must be
configured before the COMP is enabled via the ENABLE register.
Restriction: Depending on the device, not all the analog inputs may be available for each MUX.
Writing to the HYST register has no effect in single-ended mode, and the content of this register is ignored.
Page 393
PSEL
MUX
VIN+
+
-
VIN-
EXTREFSEL
MUX
VDD
VUP
0
AREF
MUX
VDOWN
1
Comparator
core
MODE
REFSEL
SAMPLE
STOP
START
ISOURCE
TH
AIN1
AIN0
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
38 COMP — Comparator
Reference
ladder
HYST
RESULT
VREF
MUX
1V2
1V8
2V4
Output
0 = BELOW (VIN+ < VIN-)
1 = ABOVE (VIN+ > VIN-)
READY
DOWN
UP
CROSS
Figure 112: Comparator in single-ended mode
VIN+
VUP
VDOWN
Output
ABOVE (VIN+ > VIN-)
BELOW
VUP
VDOWN
VUP
RESULT
BELOW ( VIN+ < VIN-)
VIN-
t
DOWN
SAMPLE
START
3
2
SAMPLE
1
CPU
ABOVE
UP
READY
BELOW
Figure 113: Hysteresis example where VIN+ starts below VUP
Page 394
38 COMP — Comparator
VIN+
VUP
VDOWN
Output
BELOW ( VIN+ < VIN-)
ABOVE (VIN+ > VIN-)
BELOW
VDOWN
VUP
VDOWN
VUP
BELOW
3
SAMPLE
SAMPLE
2
START
CPU
1
ABOVE
UP
DOWN
READY
ABOVE
DOWN
RESULT
ABOVE (VIN+ > VIN-)
VIN-
t
Figure 114: Hysteresis example where VIN+ starts above VUP
38.4 Pin configuration
The user can use the PSEL register to select one of the analog input pins, AIN0 through AIN7, as input VIN
+.
See Figure 112: Comparator in single-ended mode on page 394. Similarly the user can use the
EXTREFSEL register to select one of the AINx analog input pins as reference input, in case AREF is
selected in REFSEL. The selected analog pins will be acquired by the COMP when it is enabled via the
ENABLE register.
Depending on the device, not all the analog inputs may be available for each MUX. See PSEL and
EXTREFSEL register definition for more information about which analog pins are available on a particular
device.
38.5 Registers
Table 91: Instances
Base address
Peripheral
Instance
Description
0x40013000
COMP
COMP
General purpose comparator
Table 92: Register Overview
Register
Offset
Description
TASKS_START
0x000
Start comparator
TASKS_STOP
0x004
Stop comparator
TASKS_SAMPLE
0x008
Sample comparator value
EVENTS_READY
0x100
COMP is ready and output is valid
EVENTS_DOWN
0x104
Downward crossing
EVENTS_UP
0x108
Upward crossing
EVENTS_CROSS
0x10C
Downward or upward crossing
SHORTS
0x200
Shortcut register
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
Page 395
Configuration
38 COMP — Comparator
Register
Offset
Description
INTENCLR
0x308
Disable interrupt
RESULT
0x400
Compare result
ENABLE
0x500
COMP enable
PSEL
0x504
Pin select
REFSEL
0x508
Reference source select
EXTREFSEL
0x50C
External reference select
TH
0x530
Threshold configuration for hysteresis unit
MODE
0x534
Mode configuration
HYST
0x538
Comparator hysteresis enable
ISOURCE
0x53C
Current source select on analog input
38.5.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E D C B A
Reset 0x00000000
Id
RW Field
A
RW READY_SAMPLE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between READY event and SAMPLE task
See EVENTS_READY and TASKS_SAMPLE
B
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW READY_STOP
Shortcut between READY event and STOP task
See EVENTS_READY and TASKS_STOP
C
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW DOWN_STOP
Shortcut between DOWN event and STOP task
See EVENTS_DOWN and TASKS_STOP
D
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW UP_STOP
Shortcut between UP event and STOP task
See EVENTS_UP and TASKS_STOP
E
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW CROSS_STOP
Shortcut between CROSS event and STOP task
See EVENTS_CROSS and TASKS_STOP
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
38.5.2 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C B A
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for READY event
See EVENTS_READY
B
Disabled
0
Disable
Enabled
1
Enable
RW DOWN
Enable or disable interrupt for DOWN event
See EVENTS_DOWN
Page 396
38 COMP — Comparator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C B A
Reset 0x00000000
Id
C
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
RW UP
Enable or disable interrupt for UP event
See EVENTS_UP
D
Disabled
0
Disable
Enabled
1
Enable
RW CROSS
Enable or disable interrupt for CROSS event
See EVENTS_CROSS
Disabled
0
Disable
Enabled
1
Enable
38.5.3 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C B A
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for READY event
See EVENTS_READY
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DOWN
Write '1' to Enable interrupt for DOWN event
See EVENTS_DOWN
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW UP
Write '1' to Enable interrupt for UP event
See EVENTS_UP
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CROSS
Write '1' to Enable interrupt for CROSS event
See EVENTS_CROSS
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
38.5.4 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C B A
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for READY event
See EVENTS_READY
Clear
1
Disable
Page 397
38 COMP — Comparator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C B A
Reset 0x00000000
Id
B
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DOWN
Write '1' to Disable interrupt for DOWN event
See EVENTS_DOWN
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW UP
Write '1' to Disable interrupt for UP event
See EVENTS_UP
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CROSS
Write '1' to Disable interrupt for CROSS event
See EVENTS_CROSS
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
38.5.5 RESULT
Address offset: 0x400
Compare result
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Below
0
Input voltage is below the threshold (VIN+ < VIN-)
Above
1
Input voltage is above the threshold (VIN+ > VIN-)
RESULT
Result of last compare. Decision point SAMPLE task.
38.5.6 ENABLE
Address offset: 0x500
COMP enable
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
2
Enable
Enable or disable COMP
38.5.7 PSEL
Address offset: 0x504
Pin select
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
RW PSEL
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Analog pin select
Page 398
38 COMP — Comparator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
AnalogInput0
0
AIN0 selected as analog input
AnalogInput1
1
AIN1 selected as analog input
AnalogInput2
2
AIN2 selected as analog input
AnalogInput3
3
AIN3 selected as analog input
AnalogInput4
4
AIN4 selected as analog input
AnalogInput5
5
AIN5 selected as analog input
AnalogInput6
6
AIN6 selected as analog input
AnalogInput7
7
AIN7 selected as analog input
38.5.8 REFSEL
Address offset: 0x508
Reference source select
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000004
Id
RW Field
A
RW REFSEL
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Value Id
Value
Description
Int1V2
0
VREF = internal 1.2 V reference (VDD >= 1.7 V)
Int1V8
1
VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)
Int2V4
2
VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)
VDD
4
VREF = VDD
ARef
7
VREF = AREF (VDD >= VREF >= AREFMIN)
Reference select
38.5.9 EXTREFSEL
Address offset: 0x50C
External reference select
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW EXTREFSEL
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
AnalogReference0
0
Use AIN0 as external analog reference
AnalogReference1
1
Use AIN1 as external analog reference
External analog reference select
38.5.10 TH
Address offset: 0x530
Threshold configuration for hysteresis unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B B B B B B
Reset 0x00000000
0
Value Id
A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
Value
Description
A
RW THDOWN
[63:0]
VDOWN = (THDOWN+1)/64*VREF
B
RW THUP
[63:0]
VUP = (THUP+1)/64*VREF
38.5.11 MODE
Address offset: 0x534
Mode configuration
Page 399
38 COMP — Comparator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
Reset 0x00000000
Id
RW Field
A
RW SP
B
0
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Low
0
Low power mode
Normal
1
Normal mode
High
2
High speed mode
SE
0
Single ended mode
Diff
1
Differential mode
Speed and power mode
RW MAIN
Main operation mode
38.5.12 HYST
Address offset: 0x538
Comparator hysteresis enable
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW HYST
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NoHyst
0
Comparator hysteresis disabled
Hyst50mV
1
Comparator hysteresis enabled
Comparator hysteresis
38.5.13 ISOURCE
Address offset: 0x53C
Current source select on analog input
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000000
Id
RW Field
A
RW ISOURCE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Off
0
Current source disabled
Ien2mA5
1
Current source enabled (+/- 2.5 uA)
Ien5mA
2
Current source enabled (+/- 5 uA)
Ien10mA
3
Current source enabled (+/- 10 uA)
Comparator hysteresis
38.6 Electrical specification
38.6.1 COMP Electrical Specification
Symbol
Description
ICOMP,LP
Core run current in low power mode
Min.
Typ.
2
Max.
Units
µA
ICOMP,N
Core run current in normal mode
5
µA
ICOMP,HS
Core run current in high-speed mode
10
µA
tPROPDLY,LP
Propagation delay, low power modea
0.6
µS
tPROPDLY,N
Propagation delay, normal modea
0.2
µS
tPROPDLY,HS
Propagation delay, high-speed modea
0.1
µS
ISOURCE
Configurable input current provided by the output driven
µA
current source.
ISOURCE,A
2.5
µA
ISOURCE,B
5.0
µA
ISOURCE,C
10.0
µA
a
Propagation delay is with 10mV overdrive.
Page 400
38 COMP — Comparator
Symbol
Description
VDIFFHYST
Optional hysteresis applied to differential input
Min.
VVDD-VREF
Required difference between VDD and a selected VREF, VDD >
Typ.
Max.
30
Units
mV
0.3
V
VREF
IINT_REF
Current used by the internal bandgap reference when selected
13
µA
as source for VREF
tINT_REF,START
Startup time for the internal bandgap reference
EINT_REF
Internal bandgap reference error
50
RLADDER
Reference ladder resistance, ILADDER = VREF / RLADDER
VINPUTOFFSET
Input offset
DNLLADDER
Differential non-linearity of reference ladder
<0.1
LSB
tCOMP,START
Startup time for the comparator core
3
µS
-3
80
µS
3
%
550
-10
kΩ
10
mV
Total comparator run current must be calculated from the ICOMP, IINT_REF, ISOURCE and ILADDER values for a
given reference voltage.
Page 401
39 LPCOMP — Low power comparator
39 LPCOMP — Low power comparator
LPCOMP compares an input voltage against a reference voltage.
Listed here are the main features of LPCOMP:
•
•
•
•
0 - VDD input range
Ultra low power
Eight input options (AIN0 to AIN7)
Reference voltage options:
•
•
• Two external analog reference inputs, or
• 15-level internal reference ladder (VDD/16)
Optional hysteresis enable on input
Wakeup source from OFF mode
In System ON, the LPCOMP can generate separate events on rising and falling edges of a signal, or sample
the current state of the pin as being above or below the selected reference. The block can be configured
to use any of the analog inputs on the device. Additionally, the low power comparator can be used as an
analog wakeup source from System OFF or System ON. The comparator threshold can be programmed to a
range of fractions of the supply voltage.
Restriction: LPCOMP cannot be used (STARTed) at the same time as COMP. Only one comparator
can be used at a time.
EXTREFSEL
tasks
HYST
AREF
MUX
VIN+
+
Comparator
core
VIN-
MUX
ANADETECT
(signal to POWER module)
-
READY
DOWN
CROSS
UP
VDD*1/16
VDD*1/8
VDD*3/16
VDD*2/8
VDD*5/16
VDD*3/8
VDD*7/16
VDD*4/8
VDD*9/16
VDD*5/8
VDD*11/16
VDD*6/8
VDD*13/16
VDD*7/8
VDD*15/16
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
RESULT
SAMPLE
MUX
STOP
AIN1
PSEL
START
AIN0
REFSEL
events
Figure 115: Low power comparator
The wakeup comparator (LPCOMP) compares an input voltage (VIN+), which comes from an analog input
pin selected via the PSEL register against a reference voltage (VIN-) selected via the REFSEL on page
407 and EXTREFSEL registers.
The PSEL, REFSEL, and EXTREFSEL registers must be configured before the LPCOMP is enabled through
the ENABLE register.
The HYST register allows enabling an optional hysteresis in the comparator core. This hysteresis is in
the order of magnitude of 50 mV, and shall prevent noise on the signal to create unwanted events. See
Figure 116: Effect of hysteresis on a noisy input signal on page 403 for illustration of the effect of an active
hysteresis on a noisy input signal. It is disabled by default, and shall be configured before enabling LPCOMP
as well.
The LPCOMP is started by triggering the START task. After a start-up time of tLPCOMP,STARTUP the LPCOMP
will generate a READY event to indicate that the comparator is ready to use and the output of the LPCOMP
is correct. The LPCOMP will generate events every time VIN+ crosses VIN-. More specifically, every time
VIN+ rises above VIN- (upward crossing) an UP event is generated along with a CROSS event. Every time
VIN+ falls below VIN- (downward crossing), a DOWN event is generated along with a CROSS event. When
Page 402
39 LPCOMP — Low power comparator
hysteresis is enabled, the upward crossing level becomes (VIN- + VHYST/2), and the downward crossing
level becomes (VIN- - VHYST/2).
The LPCOMP is stopped by triggering the STOP task.
VIN+
VIN- + VHYST/2
VIN- - VHYST/2
t
Output
ABOVE
(VIN+ > (VIN- + VHYST/2))
BELOW
(VIN+ < (VIN- - VHYST/2))
ABOVE
(VIN+ > (VIN- + VHYST/2))
BELOW
Figure 116: Effect of hysteresis on a noisy input signal
LPCOMP will be operational in both System ON and System OFF mode when it is enabled through the
ENABLE register. See POWER — Power supply on page 78 for more information about power modes. Note
that it is not allowed to go to System OFF when a READY event is pending to be generated.
All LPCOMP registers, including ENABLE, are classified as retained registers when the LPCOMP is enabled.
However, when the device wakes up from System OFF, all LPCOMP registers will be reset.
The LPCOMP can wake up the system from System OFF by asserting the ANADETECT signal. The
ANADETECT signal can be derived from any of the event sources that generate the UP, DOWN and
CROSS events. In case of wakeup from System OFF, no events will be generated, only the ANADETECT
signal. See the ANADETECT register ( ANADETECT on page 407) for more information on how to
configure the ANADETECT signal.
The immediate value of the LPCOMP can be sampled to RESULT on page 406 by triggering the
SAMPLE task.
See RESETREAS on page 85 for more information on how to detect a wakeup from LPCOMP.
39.1 Shared resources
The LPCOMP shares resources with other peripherals.
The LPCOMP shares analog resources with SAADC and COMP. While it is possible to use SAADC at
the same time as COMP or LPCOMP, COMP and LPCOMP are mutually exclusive: enabling one will
automatically disable the other. In addition, when using SAADC and COMP or LPCOMP simultaneously, it is
not possible to select the same analog input pin for both modules.
The LPCOMP peripheral shall not be disabled (by writing to the ENABLE register) before the peripheral has
been stopped. Failing to do so may result in unpredictable behaviour.
39.2 Pin configuration
You can use the LPCOMP.PSEL register to select one of the analog input pins, AIN0 through AIN7, as the
analog input pin for the LPCOMP.
See GPIO — General purpose input/output on page 111 for more information about the pins. Similarly, you
can use EXTREFSEL on page 407 to select one of the analog reference input pins, AIN0 and AIN1, as
input for AREF in case AREF is selected in EXTREFSEL on page 407. The selected analog pins will be
acquired by the LPCOMP when it is enabled through ENABLE on page 406.
Page 403
39 LPCOMP — Low power comparator
39.3 Registers
Table 93: Instances
Base address
Peripheral
Instance
Description
0x40013000
LPCOMP
LPCOMP
Low power comparator
Configuration
Table 94: Register Overview
Register
Offset
Description
TASKS_START
0x000
Start comparator
TASKS_STOP
0x004
Stop comparator
TASKS_SAMPLE
0x008
Sample comparator value
EVENTS_READY
0x100
LPCOMP is ready and output is valid
EVENTS_DOWN
0x104
Downward crossing
EVENTS_UP
0x108
Upward crossing
EVENTS_CROSS
0x10C
Downward or upward crossing
SHORTS
0x200
Shortcut register
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
RESULT
0x400
Compare result
ENABLE
0x500
Enable LPCOMP
PSEL
0x504
Input pin select
REFSEL
0x508
Reference select
EXTREFSEL
0x50C
External reference select
ANADETECT
0x520
Analog detect configuration
HYST
0x538
Comparator hysteresis enable
39.3.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E D C B A
Reset 0x00000000
Id
RW Field
A
RW READY_SAMPLE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between READY event and SAMPLE task
See EVENTS_READY and TASKS_SAMPLE
B
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW READY_STOP
Shortcut between READY event and STOP task
See EVENTS_READY and TASKS_STOP
C
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW DOWN_STOP
Shortcut between DOWN event and STOP task
See EVENTS_DOWN and TASKS_STOP
D
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW UP_STOP
Shortcut between UP event and STOP task
See EVENTS_UP and TASKS_STOP
E
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW CROSS_STOP
Shortcut between CROSS event and STOP task
See EVENTS_CROSS and TASKS_STOP
Disabled
0
Disable shortcut
Page 404
39 LPCOMP — Low power comparator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E D C B A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Enable shortcut
39.3.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C B A
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for READY event
See EVENTS_READY
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DOWN
Write '1' to Enable interrupt for DOWN event
See EVENTS_DOWN
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW UP
Write '1' to Enable interrupt for UP event
See EVENTS_UP
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CROSS
Write '1' to Enable interrupt for CROSS event
See EVENTS_CROSS
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
39.3.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C B A
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for READY event
See EVENTS_READY
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DOWN
Write '1' to Disable interrupt for DOWN event
See EVENTS_DOWN
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW UP
Write '1' to Disable interrupt for UP event
See EVENTS_UP
Page 405
39 LPCOMP — Low power comparator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C B A
Reset 0x00000000
Id
D
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CROSS
Write '1' to Disable interrupt for CROSS event
See EVENTS_CROSS
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
39.3.4 RESULT
Address offset: 0x400
Compare result
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Bellow
0
Input voltage is below the reference threshold (VIN+ < VIN-).
Below
0
Input voltage is below the reference threshold (VIN+ < VIN-).
Above
1
Input voltage is above the reference threshold (VIN+ > VIN-).
RESULT
Result of last compare. Decision point SAMPLE task.
Deprecated
39.3.5 ENABLE
Address offset: 0x500
Enable LPCOMP
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Enable or disable LPCOMP
39.3.6 PSEL
Address offset: 0x504
Input pin select
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
RW PSEL
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
AnalogInput0
0
AIN0 selected as analog input
AnalogInput1
1
AIN1 selected as analog input
AnalogInput2
2
AIN2 selected as analog input
AnalogInput3
3
AIN3 selected as analog input
AnalogInput4
4
AIN4 selected as analog input
AnalogInput5
5
AIN5 selected as analog input
AnalogInput6
6
AIN6 selected as analog input
AnalogInput7
7
AIN7 selected as analog input
Analog pin select
Page 406
39 LPCOMP — Low power comparator
39.3.7 REFSEL
Address offset: 0x508
Reference select
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000004
Id
RW Field
A
RW REFSEL
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Value Id
Value
Description
Ref1_8Vdd
0
VDD * 1/8 selected as reference
Ref2_8Vdd
1
VDD * 2/8 selected as reference
Ref3_8Vdd
2
VDD * 3/8 selected as reference
Ref4_8Vdd
3
VDD * 4/8 selected as reference
Ref5_8Vdd
4
VDD * 5/8 selected as reference
Ref6_8Vdd
5
VDD * 6/8 selected as reference
Ref7_8Vdd
6
VDD * 7/8 selected as reference
ARef
7
External analog reference selected
Ref1_16Vdd
8
VDD * 1/16 selected as reference
Ref3_16Vdd
9
VDD * 3/16 selected as reference
Ref5_16Vdd
10
VDD * 5/16 selected as reference
Ref7_16Vdd
11
VDD * 7/16 selected as reference
Ref9_16Vdd
12
VDD * 9/16 selected as reference
Ref11_16Vdd
13
VDD * 11/16 selected as reference
Ref13_16Vdd
14
VDD * 13/16 selected as reference
Ref15_16Vdd
15
VDD * 15/16 selected as reference
Reference select
39.3.8 EXTREFSEL
Address offset: 0x50C
External reference select
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW EXTREFSEL
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
AnalogReference0
0
Use AIN0 as external analog reference
AnalogReference1
1
Use AIN1 as external analog reference
External analog reference select
39.3.9 ANADETECT
Address offset: 0x520
Analog detect configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000000
Id
RW Field
A
RW ANADETECT
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Cross
0
Up
1
Generate ANADETECT on upward crossing only
Down
2
Generate ANADETECT on downward crossing only
Analog detect configuration
Generate ANADETECT on crossing, both upward crossing and
downward crossing
39.3.10 HYST
Address offset: 0x538
Comparator hysteresis enable
Page 407
39 LPCOMP — Low power comparator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW HYST
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NoHyst
0
Comparator hysteresis disabled
Hyst50mV
1
Comparator hysteresis disabled (typ. 50 mV)
Comparator hysteresis enable
39.4 Electrical specification
39.4.1 LPCOMP Electrical Specification
Symbol
Description
ILPC
Run current for low power comparator
Min.
Typ.
0.5
Max.
Units
µA
tLPCANADET
Time from VIN crossing (>=50mV above threshold) to
5
µs
ANADETECT signal generated.
EREFLADDER
Error in reference ladder threshold voltage
VHYST
Optional hysteresis
-30
30
30
Page 408
mV
mV
40 WDT — Watchdog timer
40 WDT — Watchdog timer
A countdown watchdog timer using the low-frequency clock source (LFCLK) offers configurable and robust
protection against application lock-up.
The watchdog timer is started by triggering the START task.
The watchdog can be paused during long CPU sleep periods for low power applications and when the
debugger has halted the CPU. The watchdog is implemented as a down-counter that generates a TIMEOUT
event when it wraps over after counting down to 0. When the watchdog timer is started through the START
task, the watchdog counter is loaded with the value specified in the CRV register. This counter is also
reloaded with the value specified in the CRV register when a reload request is granted.
The watchdog’s timeout period is given by:
timeout [s] = ( CRV + 1 ) / 32768
When started, the watchdog will automatically force the 32.768 kHz RC oscillator on as long as no other
32.768 kHz clock source is running and generating the 32.768 kHz system clock, see chapter CLOCK —
Clock control on page 101.
40.1 Reload criteria
The watchdog has eight separate reload request registers, which shall be used to request the watchdog to
reload its counter with the value specified in the CRV register. To reload the watchdog counter, the special
value 0x6E524635 needs to be written to all enabled reload registers.
One or more RR registers can be individually enabled through the RREN register.
40.2 Temporarily pausing the watchdog
By default, the watchdog will be active counting down the down-counter while the CPU is sleeping and when
it is halted by the debugger. It is however possible to configure the watchdog to automatically pause while
the CPU is sleeping as well as when it is halted by the debugger.
40.3 Watchdog reset
A TIMEOUT event will automatically lead to a watchdog reset.
See Reset on page 82 for more information about reset sources. If the watchdog is configured to generate
an interrupt on the TIMEOUT event, the watchdog reset will be postponed with two 32.768 kHz clock
cycles after the TIMEOUT event has been generated. Once the TIMEOUT event has been generated, the
impending watchdog reset will always be effectuated.
The watchdog must be configured before it is started. After it is started, the watchdog’s configuration
registers, which comprise registers CRV, RREN, and CONFIG, will be blocked for further configuration.
The watchdog can be reset from several reset sources, see Reset behavior on page 83.
When the device starts running again, after a reset, or waking up from OFF mode, the watchdog
configuration registers will be available for configuration again.
Page 409
40 WDT — Watchdog timer
40.4 Registers
Table 95: Instances
Base address
Peripheral
Instance
Description
0x40010000
WDT
WDT
Watchdog timer
Configuration
Table 96: Register Overview
Register
Offset
Description
TASKS_START
0x000
Start the watchdog
EVENTS_TIMEOUT
0x100
Watchdog timeout
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
RUNSTATUS
0x400
Run status
REQSTATUS
0x404
Request status
CRV
0x504
Counter reload value
RREN
0x508
Enable register for reload request registers
CONFIG
0x50C
Configuration register
RR[0]
0x600
Reload request 0
RR[1]
0x604
Reload request 1
RR[2]
0x608
Reload request 2
RR[3]
0x60C
Reload request 3
RR[4]
0x610
Reload request 4
RR[5]
0x614
Reload request 5
RR[6]
0x618
Reload request 6
RR[7]
0x61C
Reload request 7
40.4.1 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW TIMEOUT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for TIMEOUT event
See EVENTS_TIMEOUT
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
40.4.2 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW TIMEOUT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for TIMEOUT event
See EVENTS_TIMEOUT
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Page 410
40 WDT — Watchdog timer
40.4.3 RUNSTATUS
Address offset: 0x400
Run status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NotRunning
0
Watchdog not running
Running
1
Watchdog is running
RUNSTATUS
Indicates whether or not the watchdog is running
40.4.4 REQSTATUS
Address offset: 0x404
Request status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G F E D C B A
Reset 0x00000001
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
DisabledOrRequested
0
Description
RR0
Request status for RR[0] register
RR[0] register is not enabled, or are already requesting reload
EnabledAndUnrequested 1
B
R
RR[0] register is enabled, and are not yet requesting reload
RR1
Request status for RR[1] register
DisabledOrRequested
0
RR[1] register is not enabled, or are already requesting reload
EnabledAndUnrequested 1
C
R
RR[1] register is enabled, and are not yet requesting reload
RR2
Request status for RR[2] register
DisabledOrRequested
0
RR[2] register is not enabled, or are already requesting reload
EnabledAndUnrequested 1
D
R
RR[2] register is enabled, and are not yet requesting reload
RR3
Request status for RR[3] register
DisabledOrRequested
0
RR[3] register is not enabled, or are already requesting reload
EnabledAndUnrequested 1
E
R
RR[3] register is enabled, and are not yet requesting reload
RR4
Request status for RR[4] register
DisabledOrRequested
0
RR[4] register is not enabled, or are already requesting reload
EnabledAndUnrequested 1
F
R
RR[4] register is enabled, and are not yet requesting reload
RR5
Request status for RR[5] register
DisabledOrRequested
0
RR[5] register is not enabled, or are already requesting reload
EnabledAndUnrequested 1
G
R
RR[5] register is enabled, and are not yet requesting reload
RR6
Request status for RR[6] register
DisabledOrRequested
0
RR[6] register is not enabled, or are already requesting reload
EnabledAndUnrequested 1
H
R
RR[6] register is enabled, and are not yet requesting reload
RR7
Request status for RR[7] register
DisabledOrRequested
0
RR[7] register is not enabled, or are already requesting reload
EnabledAndUnrequested 1
RR[7] register is enabled, and are not yet requesting reload
40.4.5 CRV
Address offset: 0x504
Counter reload value
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CRV
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
[0x0000000F..0xFFFFFFFF]Counter reload value in number of cycles of the 32.768 kHz
clock
Page 411
40 WDT — Watchdog timer
40.4.6 RREN
Address offset: 0x508
Enable register for reload request registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G F E D C B A
Reset 0x00000001
Id
RW Field
A
RW RR0
B
C
D
E
F
G
H
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Description
Disabled
0
Disable RR[0] register
Enabled
1
Enable RR[0] register
Disabled
0
Disable RR[1] register
Enabled
1
Enable RR[1] register
Disabled
0
Disable RR[2] register
Enabled
1
Enable RR[2] register
Disabled
0
Disable RR[3] register
Enabled
1
Enable RR[3] register
Disabled
0
Disable RR[4] register
Enabled
1
Enable RR[4] register
Disabled
0
Disable RR[5] register
Enabled
1
Enable RR[5] register
Disabled
0
Disable RR[6] register
Enabled
1
Enable RR[6] register
Disabled
0
Disable RR[7] register
Enabled
1
Enable RR[7] register
Enable or disable RR[0] register
RW RR1
Enable or disable RR[1] register
RW RR2
Enable or disable RR[2] register
RW RR3
Enable or disable RR[3] register
RW RR4
Enable or disable RR[4] register
RW RR5
Enable or disable RR[5] register
RW RR6
Enable or disable RR[6] register
RW RR7
Enable or disable RR[7] register
40.4.7 CONFIG
Address offset: 0x50C
Configuration register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
Reset 0x00000001
Id
RW Field
A
RW SLEEP
0
Value Id
Value
Description
Configure the watchdog to either be paused, or kept running,
while the CPU is sleeping
C
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Pause
0
Pause watchdog while the CPU is sleeping
Run
1
Keep the watchdog running while the CPU is sleeping
RW HALT
Configure the watchdog to either be paused, or kept running,
while the CPU is halted by the debugger
Pause
0
Pause watchdog while the CPU is halted by the debugger
Run
1
Keep the watchdog running while the CPU is halted by the
debugger
40.4.8 RR[0]
Address offset: 0x600
Reload request 0
Page 412
40 WDT — Watchdog timer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
W
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Reload
0x6E524635
RR
Reload request register
Value to request a reload of the watchdog timer
40.4.9 RR[1]
Address offset: 0x604
Reload request 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
W
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Reload
0x6E524635
RR
Reload request register
Value to request a reload of the watchdog timer
40.4.10 RR[2]
Address offset: 0x608
Reload request 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
W
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Reload
0x6E524635
RR
Reload request register
Value to request a reload of the watchdog timer
40.4.11 RR[3]
Address offset: 0x60C
Reload request 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
W
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Reload
0x6E524635
RR
Reload request register
Value to request a reload of the watchdog timer
40.4.12 RR[4]
Address offset: 0x610
Reload request 4
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
W
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Reload
0x6E524635
RR
Reload request register
40.4.13 RR[5]
Address offset: 0x614
Reload request 5
Page 413
Value to request a reload of the watchdog timer
40 WDT — Watchdog timer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
W
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Reload
0x6E524635
RR
Reload request register
Value to request a reload of the watchdog timer
40.4.14 RR[6]
Address offset: 0x618
Reload request 6
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
W
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Reload
0x6E524635
RR
Reload request register
Value to request a reload of the watchdog timer
40.4.15 RR[7]
Address offset: 0x61C
Reload request 7
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
W
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Reload
0x6E524635
RR
Reload request register
Value to request a reload of the watchdog timer
40.5 Electrical specification
40.5.1 Watchdog Timer Electrical Specification
Symbol
Description
IWDT
Run current for watchdog timer
tWDT
Time out interval
Min.
458 µs
Page 414
Typ.
Max.
Units
0.3
2
µA
36 h
41 SWI — Software interrupts
41 SWI — Software interrupts
A set of interrupts have been reserved for use as software interrupts.
41.1 Registers
Table 97: Instances
Base address
Peripheral
Instance
Description
0x40014000
SWI
SWI0
Software interrupt 0
0x40015000
SWI
SWI1
Software interrupt 1
0x40016000
SWI
SWI2
Software interrupt 2
0x40017000
SWI
SWI3
Software interrupt 3
0x40018000
SWI
SWI4
Software interrupt 4
0x40019000
SWI
SWI5
Software interrupt 5
Page 415
Configuration
42 NFCT — Near field communication tag
42 NFCT — Near field communication tag
The NFCT peripheral (referred to as the 'NFC peripheral' from now on) supports communication signal
interface type A and 106 kbps bit rate from the NFC Forum.
With appropriate software, the NFC peripheral can be used to emulate the listening device NFC-A as
specified by the NFC Forum.
Listed here are the main features for the NFC peripheral:
•
NFC-A listen mode operation
•
•
•
•
• 13.56 MHz input frequency
• Bit rate 106 kbps
Wake-on-field low power field detection (SENSE) mode
Frame assemble and disassemble for the NFC-A frames specified by the NFC Forum
Programmable frame timing controller
Integrated automatic collision resolution, CRC and parity functions
42.1 Overview
The NFC peripheral is an implementation of an NFC Forum compliant listening device NFC-A.
PACKETPTR
MAXLEN
TXD.FRAMECONFIG
Data RAM
D
A
T
A
Frame assemble
SoF, EoF, Parity
and CRC
Easy
DMA
STARTTX
ENABLERXDATA
Collision
resolution
FRAMEDELAYxxx
Frame
disassemble
SoF, EoF, Parity
and CRC
NFCID1_xxx
SENSRES
SELRES
FRAMESTATUS.RX
RXD.FRAMECONFIG
On the Air symbol
coder
13.56 MHz
NFC-A
load modulator
Frame timing
controller
Clock recovery
On the Air symbol
decoder
13.56 MHz
NFC-A
Receiver
Field detector
Figure 117: NFC block diagram
The NFC peripheral contains a 13.56 MHz AM receiver and a 13.56 MHz load modulator compatible with the
NFC-A technology defined in the NFC Forum with 106 kbps data rate.
The received frames will be automatically disassembled and the data part of the frame transferred to RAM.
When transmitting, the frame data will be transferred directly from RAM and transmitted with configurable
frame type and delay timing. The system will be notified by an event whenever a complete frame is received
or sent.
It also supports the collision detection and resolution ("anticollision") as defined by the NFC Forum.
Page 416
42 NFCT — Near field communication tag
Wake-on-field is supported in SENSE mode while the device is either in System OFF or System ON mode.
When the antenna enters an NFC field, an event will be triggered notifying the system to activate the
NFC functionality for incoming frames. In System ON, if the energy detected at the antenna increases
beyond a threshold value, the module will generate a FIELDDETECTED event. The module will generate a
FIELDLOST event when the quality or strength of the field no longer support NFC communication. Please
refer to NFCT Electrical Specification on page 435 for the Low Power Field Detect threshold values.
In system OFF, the NFC Low Power Field Detect function can wake the system up through a reset. The NFC
bit in register RESETREAS on page 85 will be set as cause of the wake-up.
If the system is put into system OFF mode while a field is already present, the NFC Low Power Field Detect
function will wake the system up right away and generate a reset.
Note that as a consequence of reset, NFC is disabled, so the reset handler will have to activate NFC again
and set it up properly.
The HFXO must be running before the NFC peripheral goes into ACTIVATED state. Note that the NFC
peripheral calibration is automatically done on ACTIVATE task. The HFXO can be turned off when the NFC
peripheral goes into SENSE mode. The shortcut FIELDDETECTED_ACTIVATE can be used when the
HFXO is already running while in SENSE mode.
Outgoing data will be collected from RAM with the EasyDMA function and assembled according to the
TXD.FRAMECONFIG register. Incoming data will be disassembled according to the RXD.FRAMECONFIG
register and the data section in the frame will be written to RAM via the EasyDMA function.
The NFC peripheral includes a frame timing controller that can be used to accurately control the inter-frame
delay between the incoming frame and a corresponding outgoing frame. It also includes optional CRC
functionality.
The NFC peripheral has a set of different states. The module can change state by triggering a task, or when
specific operations are finalized. Events and tasks allow software to keep track of and change the current
state.
See Figure 117: NFC block diagram on page 416 and Figure 118: NFC state diagram on page 418 for
more information.
Notes:
•
•
•
•
FIELDLOST event will not be reflected in the state machine (for instance by going back to the DISABLE
state), it is up to software to decide on the actions to take when a field lost occurs.
FIELDLOST event is not generated in SENSE mode.
FIELDDETECTED event is generated only on the transition from FIELDLOST event to energy
detected by the NFC peripheral. So, sending SENSE task while field is still present does not generate
FIELDDETECTED event.
If the FIELDDETECTED event is cleared before sending the ACTIVATE task, then the FIELDDETECTED
event shows up again after sending the ACTIVATE task. The shortcut FIELDDETECTED_ACTIVATE can
be used to avoid this condition.
Page 417
42 NFCT — Near field communication tag
Activated
NFC (OTHER) (See activity)
/COLLISION
GOIDLE
DISABLE
DISABLE
ACTIVATE
IDLERU
/ READY
NFC (ALL_REQ)
/ AUTOCOLRESSTARTED
IDLE
/SELECTED
READY_A
NFC (SENS_REQ)
/ AUTOCOLRESSTARTED
NFC (ALL_REQ)
/ AUTOCOLRESSTARTED
DISABLE
SLEEP_A
SENSE
NFC (SLP_REQ)
GOSLEEP
ACTIVE_A
ENABLERXDATA
SENSE_FIELD
STARTTX
SENSE
RECEIVE
STARTTX
TRANSMIT
/TXFRAMEEND
ACTIVATE
/RXFRAMEEND
/ RXERROR
Figure 118: NFC state diagram
42.2 Pin configuration
NFC uses two pins to connect the antenna.
These pins are shared with GPIOs, and the PROTECT field in the NFCPINS register in UICR defines the
usage of these pins and their protection level against excessive voltages. The content of the NFCPINS
register is reloaded at every reset.
When NFCPINS.PROTECT=NFC, a protection circuit will be enabled on the dedicated pins, preventing the
chip from being damaged in the presence of a strong NFC field. The GPIO function will be disabled on those
pins as well.
When NFCPINS.PROTECT=Disabled, the device will not be protected against strong NFC field damages
caught by a connected NFC antenna, and the NFCT peripheral will not operate as expected, as it will never
leave the DISABLE state.
The pins dedicated to the NFC antenna function will have some limitation when the pins are configured
for normal GPIO operation. The pin capacitance will be higher on those (refer to CPAD_NFC in the GPIO
Electrical Specification on page 154 below), and some increased leakage current between the two pins is
to be expected if they are used in GPIO mode, and are driven to different logical values. To save power the
two pins should always be set to the same logical value whenever entering one of the device power saving
modes. Please refer to INFC_LEAK in GPIO Electrical Specification on page 154 for details.
42.3 EasyDMA
The NFC peripheral implements EasyDMA for reading and writing of data packets from and to the Data RAM
without CPU involvement.
The NFC EasyDMA utilizes one pointer called PACKETPTR for receiving and transmitting packets.
The EasyDMA can either read or write between the NFC peripheral and the RAM, but not at the same time.
The event RXFRAMESTART indicates that the EasyDMA has started writing to the RAM for a receive frame
and the event RXFRAMEND indicates that the EasyDMA has completed writing to the RAM. Similarly, the
event TXFRAMESTART indicates that the EasyDMA has started reading from the RAM for a transmit frame
and the event TXFRAMEND indicates that the EasyDMA has completed reading from the RAM. If a transmit
and a receive operation is issued at the same time, the transmit operation would be prioritized.
Starting a transmit operation while the EasyDMA has already started writing a receive frame to the RAM
will result in unpredictable behavior. Starting an EasyDMA operation whilst there is an ongoing EasyDMA
operation may result in unpredictable behavior. It is recommended to wait for the TXFRAMEEND or
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42 NFCT — Near field communication tag
RXFRAMEND event for the respective ongoing transmit or receive before starting a new receive or transmit
operation.
The MAXLEN register determines the maximum number of bytes that can be read from or written to the
RAM. This feature can be used to secure that the NFC peripheral does not overwrite, or read beyond, the
RAM assigned to a packet. Note that if the RXD.AMOUNT or TXD.AMOUNT register indicates longer data
packets than set in MAXLEN, the frames sent to or received from the physical layer will be incomplete.
In RX, the OVERRUN bit in the FRAMESTATUS.RX register will be set and an RXERROR event will be
triggered in that situation.
Note that RXD.AMOUNT and TXD.AMOUNT define a frame length in bytes and bits excluding SoF, EoF and
parity, but including CRC for RXD.AMOUNT only, make sure to take potential additional bits into account
when setting MAXLEN.
Only sending task ENABLERXDATA ensures that a new value in PACKETPTR pointing to the RX buffer in
Data RAM is taken into account.
If PACKETPTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or
RAM corruption. See Chapter Memory on page 23 for more information about the different memory regions.
The NFC peripherals normally do alternative receive and transmit frames. So, to prepare for the next frame,
the PACKETPTR, MAXLEN, TXD.FRAMECONFIG and TXD.AMOUNT can be updated while the receive
is in progress, and, similarly, the PACKETPTR, MAXLEN and RXD.FRAMECONFIG can be updated while
the transmit is in progress. They can be updated and prepared for the next NFC frame immediately after
the STARTED event of the current frame has been received. Updating the TXD.FRAMECONFIG and
TXD.AMOUNT during the current transmit frame or updating RXD.FRAMECONFIG during current receive
frame may cause unpredictable behaviour.
In accordance with NFC Forum, NFC Digital Protocol Technical Specification, the least a significant bit from
the least significant byte is sent on air first. The bytes are stored in increasing order, starting at the lowest
address in the EasyDMA buffer in RAM.
42.4 Collision resolution
The NFC peripheral implements an automatic collision resolution function as defined by the NFC Forum.
The SENSRES and SELRES registers need to be programmed upfront in order for the collision resolution to
behave correctly. Depending on the NFCIDSIZE field in SENSRES, the following registers also need to be
programmed upfront:
•
•
•
NFCID1_LAST if NFCID1SIZE=NFCID1Single (ID = 4 bytes);
NFCID1_2ND_LAST and NFCID1_LAST if NFCID1SIZE=NFCID1Double (ID = 7 bytes);
NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST if NFCID1SIZE=NFCID1Triple (ID = 10
bytes);
Table 98: NFCID1 byte allocation (top sent first on air) on page 419 explains the position of the ID bytes in
NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST, depending on the ID size, and as compared
to the definition used in the NFC Forum, NFC Digital Protocol Technical Specification.
Table 98: NFCID1 byte allocation (top sent first on air)
NFCID1_Q
NFCID1_R
NFCID1_S
NFCID1_T
NFCID1_U
NFCID1_V
NFCID1_W
NFCID1_X
NFCID1_Y
NFCID1_Z
ID = 4 bytes
ID = 7 bytes
nfcid10
nfcid11
nfcid12
nfcid13
nfcid10
nfcid11
nfcid12
nfcid13
nfcid14
nfcid15
nfcid16
ID = 10 bytes
nfcid10
nfcid11
nfcid12
nfcid13
nfcid14
nfcid15
nfcid16
nfcid17
nfcid18
nfcid19
Automatic collision resolution is enabled by default.
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42 NFCT — Near field communication tag
The hardware implementation can handle the states from IDLE to ACTIVE_A automatically as defined
in the NFC Forum, NFC Activity Technical Specification, and the other states are to be handled by
software. The software keeps track of the state through events. The collision resolution will trigger an
AUTOCOLRESSTARTED event when it has started. Reaching the ACTIVE_A state is indicated by the
SELECTED event.
If collision resolution fails, a COLLISION event is triggered. Note that errors occurring during automatic
collision resolution may also cause ERROR and/or RXERROR events to be generated. Also, other events
may get generated. It is recommended that the software ignores any event except COLLISION, SELECTED
and FIELDLOST during automatic collision resolution. Software shall also make sure that any unwanted
SHORT or PPI shortcut are disabled during automatic collision resolution.
A pre-defined set of registers, NFC.TAGHEADER0..3, containing a valid NFCID1 value, is available in FICR,
and can be used by software to populate the NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST
registers. Refer to the release notes of the NFC stack for more details on the format.
The automatic collision resolution will be restarted, if the packets are received with CRC or parity errors while
in ACTIVE_A state.
The SLP_REQ is automatically handled by the NFC peripheral. However, this results in an ERROR event
(with FRAMEDELAYTIMEOUT cause in ERRORSTATUS) since the SLP_REQ has no response. This error
must be ignored until the SELECTED event is triggered and this error should be cleared by the software
when the SELECTED event is triggered.
42.5 Frame timing controller
The NFC peripheral includes a frame timing controller that continuously keeps track of the number of the
13.56 MHz RF-carrier clock periods since the end of the EoF of the last received frame.
The NFC peripheral can be programmed to send a responding frame within a time window or at an exact
count of RF carrier periods. In case of FRAMEDELAYMODE = Window a STARTTX task triggered before
the frame timing controller counter is equal to FRAMEDELAYMIN will force the transmission to halt until the
counter is equal to FRAMEDELAYMIN. If the counter is within FRAMEDELAYMIN and FRAMEDELAYMAX
when the STARTTX task is triggered, the peripheral will start the transmission straight away. In case of
FRAMEDELAYMODE = ExactVal, a STARTTX task, triggered before the frame delay counter is equal to
FRAMEDELAYMAX, will halt the actual transmission start until the counter is equal to FRAMEDELAYMAX.
In case of FRAMEDELAYMODE = WindowGrid, the behaviour is similar to the FRAMEDELAYMODE =
Window, but the actual transmission between FRAMEDELAYMIN and FRAMEDELAYMAX starts on a bit
grid as defined for NFC-A Listen frames (slot duration of 128 RF carrier periods).
The FRAMEDELAYMIN and FRAMEDELAYMAX values shall only be updated before the STARTTX
task is triggered. Failing to do so may cause unpredictable behaviour. An ERROR event (with
FRAMEDELAYTIMEOUT cause in ERRORSTATUS) will be asserted if the frame timing controller counter
reaches FRAMEDELAYMAX without any STARTTX task triggered. This may happen even when the
response is not required as per NFC Forum, NFC Digital Protocol Technical Specification. Any commands
handled by the automatic collision resolution that don't involve a response being generated may also result in
an ERROR event (with FRAMEDELAYTIMEOUT cause in ERRORSTATUS).
The frame timing controller operation is illustrated in Figure 119: Frame timing controller
(FRAMEDELAYMODE=Window) on page 421. The frame timing controller automatically adjusts the frame
timing counter based on the last received data bit according to NFC-A technology in the NFC Forum, NFC
Digital Protocol Technical Specification.
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42 NFCT — Near field communication tag
Receive
Last data bit
Transmit
EoF
Subcarrier continues in the 3 cases below
Logic ‘0’
Logic ‘1’
20/fc
84/fc
Before Min
FRAMEDELAYMAX
FRAMEDELAYMIN
STARTTX task
SoF
Subcarrier modulation
Between Min and Max
STARTTX task
SoF
Subcarrier modulation
After Max (or missing)
STARTTX task
Subcarrier modulation
ERROR event
Figure 119: Frame timing controller (FRAMEDELAYMODE=Window)
42.6 Frame assembler
The NFC peripheral implements a frame assembler in hardware.
When the NFC peripheral is in the ACTIVE_A state, the software can decide to enter RX or TX mode. For
RX, see Frame disassembler on page 422. For TX, the software must indicate the address of the source
buffer in Data RAM and its size through programming the PACKETPTR and MAXCNT registers respectively,
then issuing a TXSTART task.
MAXCNT must be set so that it matches the size of the frame to be sent.
The STARTED event indicates that the PACKETPTR and MAXCNT registers have been captured by the
frame assembler's EasyDMA.
When asserting the STARTTX task, the frame assembler module will start reading
TXD.AMOUNT.TXDATABYTES bytes (plus one additional byte if TXD.AMOUNT.TXDATABITS > 0) from the
RAM position set by the PACKETPTR.
The NFC peripheral transmits the data as read from RAM, adding framing and the CRC calculated on the fly.
The NFC peripheral will take (8*TXD.AMOUNT.TXDATABYTES + TXD.AMOUNT.TXDATABITS) bits and
assemble a frame according to settings in TXD.FRAMECONFIG. Both short frames, standard frames and
bit oriented SDD frames as specified in the NFC Forum, NFC Digital Protocol Technical Specification can be
assembled by correct setting of the TXD.FRAMECONFIG register.
The bytes will be transmitted on air in the same order as they are read from RAM with a rising bit order
within each byte (least significant bit first). That is, b0 will be transmitted on air before b1, and so on. The
bits read from RAM will be coded into symbols as defined in the NFC Forum, NFC Digital Protocol Technical
Specification.
Important: Some NFC Forum documents, such as NFC Forum, NFC Digital Protocol Technical
Specification, define bit numbering in a byte from b1 (LSB) to b8 (MSB), while most other technical
documents from the NFC Forum, and also the Nordic Semiconductor documentation, traditionally
numbers them from b0 to b7. The present document uses the b0 to b7 numbering scheme. Be aware
of this when comparing with the NFC Forum, NFC Digital Protocol Technical Specification to others.
The frame assembler can be configured in TXD.FRAMECONFIG to add Start of Frame (SoF) symbol,
calculate and add parity bits, and calculate and add CRC to the data read from RAM when assembling
the frame. The total frame will then be longer than what is defined by TXD.AMOUNT.TXDATABYTES and
TXDATABITS. DISCARDMODE will select if the first bits in the first byte read from RAM or the last bits in the
last byte read from RAM will be discarded if TXD.AMOUNT.TXDATABITS are not equal to zero. Note that if
TXD.FRAMECONFIG.PARITY = Parity and TXD.FRAMECONFIG.DISCARDMODE=DiscardStart, a parity bit
will be included after the non-complete first byte. No parity will be added after a non-complete last byte.
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42 NFCT — Near field communication tag
The Frame Assemble operation is illustrated in Figure 120: Frame assemble on page 422 for different
settings in TXD.FRAMECONFIG. All shaded bits fields are added by the frame assembler. Some of these
bits are optional and appearances are configured in TXD.FRAMECONFIG. Please note that the frames
illustrated do not necessarily comply with the NFC specification. The figure is only to illustrate the behavior of
the NFC peripheral.
Data from RAM
Byte 1: PACKETPTR + 0
b0
b1
b2
b3
b4
b5
Byte 2: PACKETPTR + 1
b6
b7
b0
b1
b2
b3
b4
Byte (TXDATABYTES)
b5
b6
b7
b0
b1
b2
b3
b4
Byte (TXDATABYTES + 1)
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
b7
(only if TXDATABITS > 0)
Frame on air
PARITY = Parity, TXDATABITS = 0, CRCMODETX = CRC16TX
Byte 1
Byte 2
SoF
b0
b1
b2
b3
b4
b5
b6
b7
b0
P
b1
b2
Byte (TXDATABYTES)
b3
b4
b5
b6
P
b7
b0
b1
b2
b3
b5
b6
b7
PARITY = Parity, TXDATABITS = 4, CRCMODETX = NoCRCTX, DISCARDMODE = DiscardStart
Byte (TXDATABYTES)
Byte 1
Byte 2
SoF
b4
b5
b6
b7
P
b0
b1
b2
b3
b4
b5
b6
b7
b0
P
b1
b2
b3
b4
b4
b5
b6
CRC 1 (8 bit)
P
b7
P
CRC 2 (8 bit)
P
EoF
Byte (TXDATABYTES + 1)
P
b0
b1
b2
b3
b4
b5
b6
P
b7
EoF
PARITY = Parity, TXDATABITS = 0, CRCMODETX = NoCRCTX
Byte 1
Byte TXDATABYTES
SoF
b0
b1
b2
b3
b4
b5
b6
b7
P
b0
b1
b2
b3
b4
b5
b6
P
b7
EoF
Figure 120: Frame assemble
The accurate timing for transmitting the frame on air is set using the frame timing controller settings.
42.7 Frame disassembler
The NFC peripheral implements a frame disassembler in hardware.
When the NFC peripheral is in the ACTIVE_A state, the software can decide to enter RX or TX mode. For
TX, see Frame assembler on page 421. For RX, the software must indicate the address of the destination
buffer in Data RAM and its size through programming the PACKETPTR and MAXCNT registers respectively,
then issuing a ENABLERXDATA task.
The STARTED event indicates that the PACKETPTR and MAXCNT registers have been captured by the
frame disassembler's EasyDMA.
When an incoming frame starts, the RXFRAMESTART event will get issued and data will be written to the
buffer in Data RAM. The frame disassembler will verify and remove on the fly any parity bits and SoF and
End of Frame (EoF) symbols based on RXD.FRAMECONFIG register configuration. It will, however, verify
and transfer the CRC bytes into RAM, if the CRC is was enabled through RXD.FRAMECONFIG.
When an EoF symbol is detected, the NFC peripheral will assert the RXFRAMEEND event and write the
RXD.AMOUNT register to indicate numbers of received bytes and bits in the data packet. The module does
not interpret the content of the data received from the remote NFC device, except for SoF, EoF, parity and
CRC checking, as described above. The Frame disassemble operation is illustrated in Figure 121: Frame
disassemble illustration on page 422.
Per NFC specification, the time between end of frame to the next start of frame can be as short as 86 µs,
so care must be taken that PACKETPTR and MAXCNT are ready and ENABLERXDATA is issued on time
after the end of previous frame. The use of a PPI shortcut from TXFRAMEEND to ENABLERXDATA is
recommended.
Frame on air
PARITY = Parity, RXDATABITS = 0, CRCMODERX = CRC16RX, RXDATABITS = 0
Byte 1
SoF
b0
b1
Byte 2
b2
b3
b4
b5
b6
b7
P
b0
Byte RXDATABYTES
b1
b2
b3
b4
b5
b6
b7
P
b0
b4
b5
b6
b7
P
b0
PARITY = Parity, CRCMODERX = NoCRCRX, RXDATABITS = 4
Byte 1
Byte 2
SoF
b0
b1
b2
b3
b4
b5
b6
b7
P
b0
b1
b2
b1
b2
b3
b5
b6
b7
P
b5
b6
b7
P
b4
Byte RXDATABYTES
b3
b1
b2
b3
b4
Byte (RXDATABYTES+1)
PARITY = NoParity, CRCMODERX = NoCRCRX, RXDATABITS = 0
Byte 1
Byte 2
SoF
b0
b1
b2
b3
b4
b5
b6
Data to RAM
Byte 1: (PACKETPTR + 0)
b0
b1
b2
b3
b4
b5
b7
b0
b1
b2
b3
b4
b7
b0
b1
b2
b3
b4
b5
b0
b1
b2
b3
EoF
Byte RXDATABYTES
b5
b6
b7
b0
b1
Byte 2: (PACKETPTR + 1)
b6
CRC 1 (8 bit)
b2
b3
b4
b5
b6
b0
b7
Byte RXDATABYTES
b6
b7
b0
b1
b2
b3
b4
b1
b2
b3
b4
b5
b6
b7
EoF
Byte (RXDATABYTES+1)
b5
b6
b7
b0
b1
b2
b3
b4
(only if RXDATABITS > 0)
Figure 121: Frame disassemble illustration
Page 422
b5
b6
b7
P
CRC 2 (8 bit)
P
EoF
42 NFCT — Near field communication tag
42.8 Antenna interface
In ACTIVATED state, an amplitude regulator will adjust the voltage swing on the antenna pins to a value that
is within the Vswing limit.
Refer to NFCT Electrical Specification on page 435.
42.9 NFCT antenna recommendations
The NFCT antenna coil must be connected differential between NFC1 and NFC2 pins of the device.
Two external capacitors should be used to tune the resonance of the antenna circuit to 13.56 MHz.
Cp1
Ctune1
Cint1
NFC1
ANTENNA
Lant
Rin
NFC2
Cp2
Ctune2
Cint2
Figure 122: NFCT antenna recommendations
The required tuning capacitor value is given by the below equations:
An antenna inductance of Lant = 2 µH will give tuning capacitors in the range of 130 pF on each pin. For good
performance, match the total capacitance on NFC1 and NFC2.
42.10 Battery protection
If the antenna is exposed to a strong NFC field, current may flow in the opposite direction on the supply due
to parasitic diodes and ESD structures.
If the battery used does not tolerate return current, a series diode must be placed between the battery and
the device in order to protect the battery.
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42 NFCT — Near field communication tag
42.11 References
NFC Forum, NFC Analog Specification version 1.0, www.nfc-forum.org
NFC Forum, NFC Digital Protocol Technical Specification version 1.1, www.nfc-forum.org
NFC Forum, NFC Activity Technical Specification version 1.1, www.nfc-forum.org
42.12 Registers
Table 99: Instances
Base address
Peripheral
Instance
Description
0x40005000
NFCT
NFCT
Near Field Communication Tag
Configuration
Table 100: Register Overview
Register
Offset
Description
TASKS_ACTIVATE
0x000
Activate NFC peripheral for incoming and outgoing frames, change state to activated
TASKS_DISABLE
0x004
Disable NFC peripheral
TASKS_SENSE
0x008
Enable NFC sense field mode, change state to sense mode
TASKS_STARTTX
0x00C
Start transmission of a outgoing frame, change state to transmit
TASKS_ENABLERXDATA 0x01C
Initializes the EasyDMA for receive.
TASKS_GOIDLE
0x024
Force state machine to IDLE state
TASKS_GOSLEEP
0x028
Force state machine to SLEEP_A state
EVENTS_READY
0x100
The NFC peripheral is ready to receive and send frames
EVENTS_FIELDDETECTED 0x104
Remote NFC field detected
EVENTS_FIELDLOST
Remote NFC field lost
0x108
EVENTS_TXFRAMESTART 0x10C
Marks the start of the first symbol of a transmitted frame
EVENTS_TXFRAMEEND
Marks the end of the last transmitted on-air symbol of a frame
0x110
EVENTS_RXFRAMESTART 0x114
Marks the end of the first symbol of a received frame
EVENTS_RXFRAMEEND 0x118
Received data have been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended
accessing the RX buffer
EVENTS_ERROR
0x11C
NFC error reported. The ERRORSTATUS register contains details on the source of the error.
EVENTS_RXERROR
0x128
NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the
EVENTS_ENDRX
0x12C
RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.
EVENTS_ENDTX
0x130
Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer
error.
EVENTS_AUTOCOLRESSTARTED
0x138
Auto collision resolution process has started
EVENTS_COLLISION
0x148
NFC Auto collision resolution error reported.
EVENTS_SELECTED
0x14C
NFC Auto collision resolution successfully completed
EVENTS_STARTED
0x150
EasyDMA is ready to receive or send frames.
SHORTS
0x200
Shortcut register
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ERRORSTATUS
0x404
NFC Error Status register
FRAMESTATUS.RX
0x40C
Result of last incoming frames
CURRENTLOADCTRL
0x430
Current value driven to the NFC Load Control
FIELDPRESENT
0x43C
Indicates the presence or not of a valid field
FRAMEDELAYMIN
0x504
Minimum frame delay
FRAMEDELAYMAX
0x508
Maximum frame delay
FRAMEDELAYMODE
0x50C
Configuration register for the Frame Delay Timer
PACKETPTR
0x510
Packet pointer for TXD and RXD data storage in Data RAM
MAXLEN
0x514
Size of allocated for TXD and RXD data storage buffer in Data RAM
TXD.FRAMECONFIG
0x518
Configuration of outgoing frames
TXD.AMOUNT
0x51C
Size of outgoing frame
RXD.FRAMECONFIG
0x520
Configuration of incoming frames
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42 NFCT — Near field communication tag
Register
Offset
Description
RXD.AMOUNT
0x524
Size of last incoming frame
NFCID1_LAST
0x590
Last NFCID1 part (4, 7 or 10 bytes ID)
NFCID1_2ND_LAST
0x594
Second last NFCID1 part (7 or 10 bytes ID)
NFCID1_3RD_LAST
0x598
Third last NFCID1 part (10 bytes ID)
SENSRES
0x5A0
NFC-A SENS_RES auto-response settings
SELRES
0x5A4
NFC-A SEL_RES auto-response settings
42.12.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
RW Field
A
RW FIELDDETECTED_ACTIVATE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between FIELDDETECTED event and ACTIVATE task
See EVENTS_FIELDDETECTED and TASKS_ACTIVATE
B
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW FIELDLOST_SENSE
Shortcut between FIELDLOST event and SENSE task
See EVENTS_FIELDLOST and TASKS_SENSE
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
42.12.2 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for READY event
See EVENTS_READY
B
Disabled
0
Disable
Enabled
1
Enable
RW FIELDDETECTED
Enable or disable interrupt for FIELDDETECTED event
See EVENTS_FIELDDETECTED
C
Disabled
0
Disable
Enabled
1
Enable
RW FIELDLOST
Enable or disable interrupt for FIELDLOST event
See EVENTS_FIELDLOST
D
Disabled
0
Disable
Enabled
1
Enable
RW TXFRAMESTART
Enable or disable interrupt for TXFRAMESTART event
See EVENTS_TXFRAMESTART
E
Disabled
0
Disable
Enabled
1
Enable
RW TXFRAMEEND
Enable or disable interrupt for TXFRAMEEND event
See EVENTS_TXFRAMEEND
F
Disabled
0
Disable
Enabled
1
Enable
RW RXFRAMESTART
Enable or disable interrupt for RXFRAMESTART event
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42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
RW Field
0
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
See EVENTS_RXFRAMESTART
G
RW RXFRAMEEND
Enable or disable interrupt for RXFRAMEEND event
See EVENTS_RXFRAMEEND
H
Disabled
0
Disable
Enabled
1
Enable
RW ERROR
Enable or disable interrupt for ERROR event
See EVENTS_ERROR
K
Disabled
0
Disable
Enabled
1
Enable
RW RXERROR
Enable or disable interrupt for RXERROR event
See EVENTS_RXERROR
L
Disabled
0
Disable
Enabled
1
Enable
RW ENDRX
Enable or disable interrupt for ENDRX event
See EVENTS_ENDRX
M
Disabled
0
Disable
Enabled
1
Enable
RW ENDTX
Enable or disable interrupt for ENDTX event
See EVENTS_ENDTX
N
Disabled
0
Disable
Enabled
1
Enable
RW AUTOCOLRESSTARTED
Enable or disable interrupt for AUTOCOLRESSTARTED event
See EVENTS_AUTOCOLRESSTARTED
R
Disabled
0
Disable
Enabled
1
Enable
RW COLLISION
Enable or disable interrupt for COLLISION event
See EVENTS_COLLISION
S
Disabled
0
Disable
Enabled
1
Enable
RW SELECTED
Enable or disable interrupt for SELECTED event
See EVENTS_SELECTED
T
Disabled
0
Disable
Enabled
1
Enable
RW STARTED
Enable or disable interrupt for STARTED event
See EVENTS_STARTED
Disabled
0
Disable
Enabled
1
Enable
42.12.3 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for READY event
See EVENTS_READY
Page 426
42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
B
RW Field
0
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW FIELDDETECTED
Write '1' to Enable interrupt for FIELDDETECTED event
See EVENTS_FIELDDETECTED
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW FIELDLOST
Write '1' to Enable interrupt for FIELDLOST event
See EVENTS_FIELDLOST
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXFRAMESTART
Write '1' to Enable interrupt for TXFRAMESTART event
See EVENTS_TXFRAMESTART
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXFRAMEEND
Write '1' to Enable interrupt for TXFRAMEEND event
See EVENTS_TXFRAMEEND
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXFRAMESTART
Write '1' to Enable interrupt for RXFRAMESTART event
See EVENTS_RXFRAMESTART
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXFRAMEEND
Write '1' to Enable interrupt for RXFRAMEEND event
See EVENTS_RXFRAMEEND
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Enable interrupt for ERROR event
See EVENTS_ERROR
K
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXERROR
Write '1' to Enable interrupt for RXERROR event
See EVENTS_RXERROR
L
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDRX
Write '1' to Enable interrupt for ENDRX event
See EVENTS_ENDRX
M
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDTX
Write '1' to Enable interrupt for ENDTX event
See EVENTS_ENDTX
Set
1
Enable
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42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
N
RW Field
0
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW AUTOCOLRESSTARTED
Write '1' to Enable interrupt for AUTOCOLRESSTARTED event
See EVENTS_AUTOCOLRESSTARTED
R
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COLLISION
Write '1' to Enable interrupt for COLLISION event
See EVENTS_COLLISION
S
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SELECTED
Write '1' to Enable interrupt for SELECTED event
See EVENTS_SELECTED
T
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STARTED
Write '1' to Enable interrupt for STARTED event
See EVENTS_STARTED
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
42.12.4 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for READY event
See EVENTS_READY
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW FIELDDETECTED
Write '1' to Disable interrupt for FIELDDETECTED event
See EVENTS_FIELDDETECTED
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW FIELDLOST
Write '1' to Disable interrupt for FIELDLOST event
See EVENTS_FIELDLOST
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXFRAMESTART
Write '1' to Disable interrupt for TXFRAMESTART event
See EVENTS_TXFRAMESTART
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Page 428
42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
RW Field
E
RW TXFRAMEEND
0
Value Id
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for TXFRAMEEND event
See EVENTS_TXFRAMEEND
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXFRAMESTART
Write '1' to Disable interrupt for RXFRAMESTART event
See EVENTS_RXFRAMESTART
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXFRAMEEND
Write '1' to Disable interrupt for RXFRAMEEND event
See EVENTS_RXFRAMEEND
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Disable interrupt for ERROR event
See EVENTS_ERROR
K
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXERROR
Write '1' to Disable interrupt for RXERROR event
See EVENTS_RXERROR
L
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDRX
Write '1' to Disable interrupt for ENDRX event
See EVENTS_ENDRX
M
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDTX
Write '1' to Disable interrupt for ENDTX event
See EVENTS_ENDTX
N
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW AUTOCOLRESSTARTED
Write '1' to Disable interrupt for AUTOCOLRESSTARTED event
See EVENTS_AUTOCOLRESSTARTED
R
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COLLISION
Write '1' to Disable interrupt for COLLISION event
See EVENTS_COLLISION
S
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SELECTED
Write '1' to Disable interrupt for SELECTED event
See EVENTS_SELECTED
T
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STARTED
Write '1' to Disable interrupt for STARTED event
Page 429
42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
RW Field
0
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_STARTED
42.12.5 ERRORSTATUS
Address offset: 0x404
NFC Error Status register
Write a bit to '1' to clear it. Writing '0' has no effect.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x00000000
0
Value Id
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW FRAMEDELAYTIMEOUT
Value
Description
C
RW NFCFIELDTOOSTRONG
Field level is too high at max load resistance
D
RW NFCFIELDTOOWEAK
Field level is too low at min load resistance
No STARTTX task triggered before expiration of the time set in
FRAMEDELAYMAX
42.12.6 FRAMESTATUS.RX
Address offset: 0x40C
Result of last incoming frames
Write a bit to '1' to clear it. Writing '0' has no effect.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B
Reset 0x00000000
Id
RW Field
A
RW CRCERROR
B
C
0
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
CRCCorrect
0
Valid CRC detected
CRCError
1
CRC received does not match local check
ParityOK
0
Frame received with parity OK
ParityError
1
Frame received with parity error
NoOverrun
0
No overrun detected
Overrun
1
Overrun error
No valid End of Frame detected
RW PARITYSTATUS
Parity status of received frame
RW OVERRUN
Overrun detected
42.12.7 CURRENTLOADCTRL
Address offset: 0x430
Current value driven to the NFC Load Control
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
CURRENTLOADCTRL
Current value driven to the NFC Load Control
42.12.8 FIELDPRESENT
Address offset: 0x43C
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42 NFCT — Near field communication tag
Indicates the presence or not of a valid field
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
FIELDPRESENT
Indicates the presence or not of a valid field. Available only in
the activated state.
B
R
NoField
0
No valid field detected
FieldPresent
1
Valid field detected
NotLocked
0
Not locked to field
Locked
1
Locked to field
LOCKDETECT
Indicates if the low level has locked to the field
42.12.9 FRAMEDELAYMIN
Address offset: 0x504
Minimum frame delay
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000480
Id
RW Field
A
RW FRAMEDELAYMIN
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0
Value
Description
Minimum frame delay in number of 13.56 MHz clocks
42.12.10 FRAMEDELAYMAX
Address offset: 0x508
Maximum frame delay
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00001000
Id
RW Field
A
RW FRAMEDELAYMAX
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum frame delay in number of 13.56 MHz clocks
42.12.11 FRAMEDELAYMODE
Address offset: 0x50C
Configuration register for the Frame Delay Timer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000001
Id
RW Field
A
RW FRAMEDELAYMODE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Description
FreeRun
0
Window
1
ExactVal
2
Frame is transmitted exactly at FRAMEDELAYMAX
WindowGrid
3
Frame is transmitted on a bit grid between FRAMEDELAYMIN
Configuration register for the Frame Delay Timer
Transmission is independent of frame timer and will start when
the STARTTX task is triggered. No timeout.
Frame is transmitted between FRAMEDELAYMIN and
FRAMEDELAYMAX
and FRAMEDELAYMAX
42.12.12 PACKETPTR
Address offset: 0x510
Packet pointer for TXD and RXD data storage in Data RAM
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42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Packet pointer for TXD and RXD data storage in Data RAM. This
address is a byte aligned RAM address.
42.12.13 MAXLEN
Address offset: 0x514
Size of allocated for TXD and RXD data storage buffer in Data RAM
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXLEN
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..257]
Size of allocated for TXD and RXD data storage buffer in Data
RAM
42.12.14 TXD.FRAMECONFIG
Address offset: 0x518
Configuration of outgoing frames
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D
Reset 0x00000017
Id
RW Field
A
RW PARITY
B
C
D
0
C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1
Value Id
Value
Description
NoParity
0
Parity is not added in TX frames
Parity
1
Parity is added TX frames
DiscardEnd
0
Unused bits is discarded at end of frame
DiscardStart
1
Unused bits is discarded at start of frame
NoSoF
0
Start of Frame symbol not added
SoF
1
Start of Frame symbol added
NoCRCTX
0
CRC is not added to the frame
CRC16TX
1
16 bit CRC added to the frame based on all the data read from
Adding parity or not in the frame
RW DISCARDMODE
Discarding unused bits in start or at end of a Frame
RW SOF
Adding SoF or not in TX frames
RW CRCMODETX
CRC mode for outgoing frames
RAM that is used in the frame
42.12.15 TXD.AMOUNT
Address offset: 0x51C
Size of outgoing frame
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B B B B B B B B B A A A
Reset 0x00000000
Id
RW Field
A
RW TXDATABITS
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..7]
Number of bits in the last or first byte read from RAM that shall
be included in the frame (excluding parity bit).
The DISCARDMODE field in FRAMECONFIG.TX selects if unused
bits is discarded at the start or at the end of a frame. A value of
0 data bytes and 0 data bits is invalid.
B
RW TXDATABYTES
[0..257]
Number of complete bytes that shall be included in the frame,
excluding CRC, parity and framing
Page 432
42 NFCT — Near field communication tag
42.12.16 RXD.FRAMECONFIG
Address offset: 0x520
Configuration of incoming frames
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
Reset 0x00000015
Id
RW Field
A
RW PARITY
B
C
0
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1
Value Id
Value
Description
NoParity
0
Parity is not expected in RX frames
Parity
1
Parity is expected in RX frames
NoSoF
0
Start of Frame symbol is not expected in RX frames
SoF
1
Start of Frame symbol is expected in RX frames
NoCRCRX
0
CRC is not expected in RX frames
CRC16RX
1
Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS
Parity expected or not in RX frame
RW SOF
SoF expected or not in RX frames
RW CRCMODERX
CRC mode for incoming frames
updated
42.12.17 RXD.AMOUNT
Address offset: 0x524
Size of last incoming frame
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B B B B B B B B B A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
RXDATABITS
Number of bits in the last byte in the frame, if less than 8
(including CRC, but excluding parity and SoF/EoF framing).
Frames with 0 data bytes and less than 7 data bits are invalid
and are not received properly.
B
R
RXDATABYTES
Number of complete bytes received in the frame (including CRC,
but excluding parity and SoF/EoF framing)
42.12.18 NFCID1_LAST
Address offset: 0x590
Last NFCID1 part (4, 7 or 10 bytes ID)
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0x00006363
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1
Id
RW Field
Value
A
RW NFCID1_Z
Description
NFCID1 byte Z (very last byte sent)
B
RW NFCID1_Y
NFCID1 byte Y
C
RW NFCID1_X
NFCID1 byte X
D
RW NFCID1_W
NFCID1 byte W
42.12.19 NFCID1_2ND_LAST
Address offset: 0x594
Second last NFCID1 part (7 or 10 bytes ID)
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42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0x00000000
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW NFCID1_V
Value
Description
NFCID1 byte V
B
RW NFCID1_U
NFCID1 byte U
C
RW NFCID1_T
NFCID1 byte T
42.12.20 NFCID1_3RD_LAST
Address offset: 0x598
Third last NFCID1 part (10 bytes ID)
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0x00000000
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW NFCID1_S
Value
Description
NFCID1 byte S
B
RW NFCID1_R
NFCID1 byte R
C
RW NFCID1_Q
NFCID1 byte Q
42.12.21 SENSRES
Address offset: 0x5A0
NFC-A SENS_RES auto-response settings
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E E E D D D D C C B A A A A A
Reset 0x00000001
Id
RW Field
A
RW BITFRAMESDD
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value
Description
Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES
response in the NFC Forum, NFC Digital Protocol Technical
Specification
SDD00000
0
SDD pattern 00000
SDD00001
1
SDD pattern 00001
SDD00010
2
SDD pattern 00010
SDD00100
4
SDD pattern 00100
SDD01000
8
SDD pattern 01000
SDD10000
16
SDD pattern 10000
B
RW RFU5
Reserved for future use. Shall be 0.
C
RW NFCIDSIZE
NFCID1 size. This value is used by the Auto collision resolution
engine.
D
NFCID1Single
0
NFCID1 size: single (4 bytes)
NFCID1Double
1
NFCID1 size: double (7 bytes)
NFCID1Triple
2
NFCID1 size: triple (10 bytes)
RW PLATFCONFIG
Tag platform configuration as defined by the b4:b1 of byte 2
in SENS_RES response in the NFC Forum, NFC Digital Protocol
Technical Specification
E
RW RFU74
Reserved for future use. Shall be 0.
42.12.22 SELRES
Address offset: 0x5A4
NFC-A SEL_RES auto-response settings
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42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E D D C C B A A
Reset 0x00000000
Id
RW Field
A
RW RFU10
B
RW CASCADE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Reserved for future use. Shall be 0.
Cascade bit (controlled by hardware, write has no effect)
Complete
0
NFCID1 complete
NotComplete
1
NFCID1 not complete
C
RW RFU43
Reserved for future use. Shall be 0.
D
RW PROTOCOL
Protocol as defined by the b7:b6 of SEL_RES response in the
E
RW RFU7
NFC Forum, NFC Digital Protocol Technical Specification
Reserved for future use. Shall be 0.
42.13 Electrical specification
42.13.1 NFCT Electrical Specification
Symbol
Description
fc
Frequency of operation
Min.
Typ.
Max.
CMI
Carrier modulation index
DR
Data Rate
106
fs
Modulation sub-carrier frequency
fc/16
Vswing
Peak differential Input voltage swing on NFC1 and NFC2
Vsense
Peak differential Field detect threshold level on NFC1-NFC236
1.0
Vp
Isense
Current in SENSE STATE
100
nA
Iactivated
Current in ACTIVATED STATE
480
Rin_min
Minimum input resistance when regulating voltage swing
Rin_max
Maximum input resistance when regulating voltage swing
1.0
Rin_loadmod
Input resistance when load modulating
8
Imax
Maximum input current on NFC pins
13.56
Units
MHz
95
%
kbps
MHz
VDD
Vp
µA
40
Ω
kΩ
22
Ω
80
mA
Max.
Units
500
us
20
us
42.13.2 NFCT Timing Parameters
Symbol
Description
tactivate
Time from task_ACTIVATE in SENSE or DISABLE state to
Min.
Typ.
ACTIVATE_A or IDLE state37
tsense
Time from remote field is present in SENSE mode to
FIELDDETECTED event is asserted
DISABLE
ACTIVATE
SENSE
TASKS
tactivate
tsense
tsense
RF-Carrier
MODES
DISABLE
SENSE_FIELD
IDLERU
Activated
DISABLE
FIELDDETECTED
FIELDLOST
READY
FIELDDETECTED
EVENTS
Figure 123: NFCT timing parameters (Shortcuts for FIELDDETECTED and FIELDLOST are disabled)
36
37
Input is high impedance in sense mode
Does not account for voltage supply and oscillator startup times
Page 435
43 PDM — Pulse density modulation interface
43 PDM — Pulse density modulation interface
The pulse density modulation (PDM) module enables input of pulse density modulated signals from external
audio frontends, for example, digital microphones. The PDM module generates the PDM clock and supports
single-channel or dual-channel (Left and Right) data input. Data is transferred directly to RAM buffers using
EasyDMA.
Listed here are the main features for PDM:
•
•
•
•
Up to two PDM microphones configured as a Left/Right pair using the same data input
16 kHz output sample rate, 16-bit samples
EasyDMA support for sample buffering
HW decimation filters
The PDM module illustrated in Figure 124: PDM module on page 436 is interfacing up to two digital
microphones with the PDM interface. It implements EasyDMA, which relieves real-time requirements
associated with controlling the PDM slave from a low priority CPU execution context. It also includes all
the necessary digital filter elements to produce PCM samples. The PDM module allows continuous audio
streaming.
CLK
Band-pass and
Decimation (left)
PDM to PCM
Band-pass and
Decimation (right)
RAM
PDM to PCM
EasyDMA
Sampling
DIN
Master clock
generator
Figure 124: PDM module
43.1 Master clock generator
The FREQ field in the master clock's PDMCLKCTRL register allows adjusting the PDM clock's frequency.
The master clock generator does not add any jitter to the HFCLK source chosen. It is recommended (but not
mandatory) to use the Xtal as HFCLK source.
43.2 Module operation
By default, bits from the left PDM microphone are sampled on PDM_CLK falling edge, bits for the right are
sampled on the rising edge of PDM_CLK, resulting in two bitstreams. Each bitstream is fed into a digital filter
which converts the PDM stream into 16-bit PCM samples, and filters and down-samples them to reach the
appropriate sample rate.
The EDGE field in the MODE register allows swapping Left and Right, so that Left will be sampled on rising
edge, and Right on falling.
The PDM module uses EasyDMA to store the samples coming out from the filters into one buffer in RAM.
Depending on the mode chosen in the OPERATION field in the MODE register, memory either contains
alternating left and right 16-bit samples (Stereo), or only left 16-bit samples (Mono).
To ensure continuous PDM sampling, it is up to the application to update the EasyDMA destination address
pointer as the previous buffer is filled.
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43 PDM — Pulse density modulation interface
The continuous transfer can be started or stopped by sending the START and STOP tasks. STOP becomes
effective after the current frame has finished transferring, which will generate the STOPPED event. The
STOPPED event indicates that all activity in the module are finished, and that the data is available in RAM
(EasyDMA has finished transferring as well). Attempting to restart before receiving the STOPPED event may
result in unpredictable behaviour.
43.3 Decimation filter
In order to convert the incoming data stream into PCM audio samples, a decimation filter is included in the
PDM interface module.
The input of the filter is the two-channel PDM serial stream (with left channel on clock high, right channel on
clock low), its output is 2 × 16-bit PCM samples at a sample rate 64 times lower than the PDM clock rate.
The filter stage of each channel is followed by a digital volume control, to attenuate or amplify the output
samples in a range of -20 dB to +20 dB around the default (reset) setting, defined by GPDM,default. The gain is
controlled by the GAINL and GAINR registers.
As an example, if the goal is to achieve 2500 RMS output samples (16 bit) with a 1 kHz 90 dBA signal into a
-26 dBFS sensitivity PDM microphone, the user will have to sum the PDM module's default gain ( GPDM,default
) and the gain introduced by the microphone and acoustic path of his implementation (an attenuation would
translate into a negative gain), and adjust GAINL and GAINR by this amount. Assuming that only the PDM
module influences the gain, GAINL and GAINR must be set to -GPDM,default dB to achieve the requirement.
With GPDM,default=3.2 dB, and as GAINL and GAINR are expressed in 0.5 dB steps, the closest value to
program would be 3.0 dB, which can be calculated as:
GAINL = GAINR = (DefaultGain - (2 * 3))
Remember to check that the resulting values programmed into GAINL and GAINR fall within MinGain and
MaxGain.
43.4 EasyDMA
Samples will be written directly to RAM, and EasyDMA must be configured accordingly.
The address pointer for the EasyDMA channel is set in SAMPLE.PTR register. If the destination address set
in SAMPLE.PTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or
RAM corruption. See Memory on page 23 for more information about the different memory regions.
DMA supports Stereo (Left+Right 16-bit samples) and Mono (Left only) data transfer, depending on setting in
the OPERATION field in the MODE register. The samples are stored little endian.
Table 101: DMA sample storage
MODE.OPERATION
Bits per sample
Stereo
Mono
32 (2x16)
16
Result stored per RAM
word
L+R
2xL
Physical RAM allocated
(32 bit words)
ceil(SAMPLE.MAXCNT/2)
ceil(SAMPLE.MAXCNT/2)
Result boundary indexes
in RAM
R0=[31:16]; L0=[15:0]
L1=[31:16]; L0=[15:0]
Note
Default
The destination buffer in RAM consists of one block, the size of which is set in SAMPLE.MAXCNT register.
Format is number of 16-bit samples. The physical RAM allocated is always:
(RAM allocation, in bytes) = SAMPLE.MAXCNT * 2;
(but the mapping of the samples depends on MODE.OPERATION.
If OPERATION=Stereo, RAM will contain a succession of Left and Right samples.
If OPERATION=Mono, RAM will contain a succession of mono samples.
Page 437
43 PDM — Pulse density modulation interface
For a given value of SAMPLE.MAXCNT, the buffer in RAM can contain half the stereo sampling time as
compared to the mono sampling time.
The PDM acquisition can be started by the START task, after the SAMPLE.PTR and SAMPLE.MAXCNT
registers have been written. When starting the module, it will take some time for the filters to start outputting
valid data. Transients from the PDM microphone itself may also occur. The first few samples (typically
around 50) might hence contain invalid values or transients. It is therefore advised to discard the first few
samples after a PDM start.
As soon as the STARTED event is received, the firmware can write the next SAMPLE.PTR value (this
register is double-buffered), to ensure continuous operation.
When the buffer in RAM is filled with samples, an END event is triggered. The firmware can start processing
the data in the buffer. Meanwhile, the PDM module starts acquiring data into the new buffer pointed to by
SAMPLE.PTR, and sends a new STARTED event, so that the firmware can update SAMPLE.PTR to the
next buffer address.
43.5 Hardware example
Connect the microphone clock to CLK, and data to DIN.
Vdd
L/R
nRFxxxxx
CLK
CLK
DATA
DIN
CLK
DIN
Figure 125: Example of a single PDM microphone, wired as left
Vdd
L/R
nRFxxxxx
CLK
CLK
DATA
DIN
CLK
DIN
Figure 126: Example of a single PDM microphone, wired as right
Note that in a single-microphone (mono) configuration, depending on the microphone’s implementation,
either the left or the right channel (sampled at falling or rising CLK edge respectively) will contain reliable
data. If two microphones are used, one of them has to be set as left, the other as right (L/R pin tied high or
to GND on the respective microphone). It is strongly recommended to use two microphones of exactly the
same brand and type so that their timings in left and right operation match.
Vdd
L/R
nRFxxxxx
CLK
CLK
DATA
DIN
Vdd
CLK
L/R
DATA
CLK
DIN
Figure 127: Example of two PDM microphones
43.6 Pin configuration
The CLK and DIN signals associated to the PDM module are mapped to physical pins according to the
configuration specified in the PSEL.CLK and PSEL.DIN registers respectively. If the CONNECT field in
any PSEL register is set to Disconnected, the associated PDM module signal will not be connected to the
required physical pins, and will not operate properly.
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43 PDM — Pulse density modulation interface
The PSEL.CLK and PSEL.DIN registers and their configurations are only used as long as the PDM module
is enabled, and retained only as long as the device is in System ON mode. See POWER — Power supply on
page 78 for more information about power modes. When the peripheral is disabled, the pins will behave as
regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register.
To ensure correct behaviour in the PDM module, the pins used by the PDM module must be configured in
the GPIO peripheral as described in Table 102: GPIO configuration before enabling peripheral on page
439 before enabling the PDM module. This is to ensure that the pins used by the PDM module are driven
correctly if the PDM module itself is temporarily disabled or the device temporarily enters System OFF. This
configuration must be retained in the GPIO for the selected I/Os as long as the PDM module is supposed to
be connected to an external PDM circuit.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behaviour.
Table 102: GPIO configuration before enabling peripheral
PDM signal
CLK
DIN
PDM pin
As specified in PSEL.CLK
As specified in PSEL.DIN
Direction
Output
Input
Output value
0
Not applicable
Comment
43.7 Registers
Table 103: Instances
Base address
Peripheral
Instance
Description
0x4001D000
PDM
PDM
Pulse Density Modulation (Digital
Configuration
Microphone Interface)
Table 104: Register Overview
Register
Offset
Description
TASKS_START
0x000
Starts continuous PDM transfer
TASKS_STOP
0x004
Stops PDM transfer
EVENTS_STARTED
0x100
PDM transfer has started
EVENTS_STOPPED
0x104
PDM transfer has finished
EVENTS_END
0x108
The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ENABLE
0x500
PDM module enable register
PDMCLKCTRL
0x504
PDM clock generator control
MODE
0x508
Defines the routing of the connected PDM microphones' signals
GAINL
0x518
Left output gain adjustment
GAINR
0x51C
Right output gain adjustment
PSEL.CLK
0x540
Pin number configuration for PDM CLK signal
PSEL.DIN
0x544
Pin number configuration for PDM DIN signal
SAMPLE.PTR
0x560
RAM address pointer to write samples to with EasyDMA
SAMPLE.MAXCNT
0x564
Number of samples to allocate memory for in EasyDMA mode
task has been received) to Data RAM
43.7.1 INTEN
Address offset: 0x300
Enable or disable interrupt
Page 439
43 PDM — Pulse density modulation interface
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW STARTED
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for STARTED event
See EVENTS_STARTED
B
Disabled
0
Disable
Enabled
1
Enable
RW STOPPED
Enable or disable interrupt for STOPPED event
See EVENTS_STOPPED
C
Disabled
0
Disable
Enabled
1
Enable
RW END
Enable or disable interrupt for END event
See EVENTS_END
Disabled
0
Disable
Enabled
1
Enable
43.7.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW STARTED
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for STARTED event
See EVENTS_STARTED
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Enable interrupt for STOPPED event
See EVENTS_STOPPED
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW END
Write '1' to Enable interrupt for END event
See EVENTS_END
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
43.7.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW STARTED
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for STARTED event
See EVENTS_STARTED
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Disable interrupt for STOPPED event
Page 440
43 PDM — Pulse density modulation interface
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_STOPPED
C
RW END
Write '1' to Disable interrupt for END event
See EVENTS_END
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
43.7.4 ENABLE
Address offset: 0x500
PDM module enable register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Enable or disable PDM module
43.7.5 PDMCLKCTRL
Address offset: 0x504
PDM clock generator control
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x08400000
Id
RW Field
A
RW FREQ
0
0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
1000K
0x08000000
PDM_CLK = 32 MHz / 32 = 1.000 MHz
Default
0x08400000
PDM_CLK = 32 MHz / 31 = 1.032 MHz
1067K
0x08800000
PDM_CLK = 32 MHz / 30 = 1.067 MHz
PDM_CLK frequency
43.7.6 MODE
Address offset: 0x508
Defines the routing of the connected PDM microphones' signals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
RW Field
A
RW OPERATION
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Stereo
0
Mono
1
Description
Mono or stereo operation
Sample and store one pair (Left + Right) of 16bit samples per
RAM word R=[31:16]; L=[15:0]
Sample and store two successive Left samples (16 bit each) per
RAM word L1=[31:16]; L0=[15:0]
B
RW EDGE
Defines on which PDM_CLK edge Left (or mono) is sampled
LeftFalling
0
Left (or mono) is sampled on falling edge of PDM_CLK
LeftRising
1
Left (or mono) is sampled on rising edge of PDM_CLK
Page 441
43 PDM — Pulse density modulation interface
43.7.7 GAINL
Address offset: 0x518
Left output gain adjustment
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A
Reset 0x00000028
Id
RW Field
A
RW GAINL
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
Value
Description
Left output gain adjustment, in 0.5 dB steps, around the default
module gain (see electrical parameters)
0x00 -20 dB gain adjust
0x01 -19.5 dB gain adjust
(...)
0x27 -0.5 dB gain adjust
0x28 0 dB gain adjust
0x29 +0.5 dB gain adjust
(...)
0x4F +19.5 dB gain adjust
0x50 +20 dB gain adjust
MinGain
0x00
-20dB gain adjustment (minimum)
DefaultGain
0x28
0dB gain adjustment ('2500 RMS' requirement)
MaxGain
0x50
+20dB gain adjustment (maximum)
43.7.8 GAINR
Address offset: 0x51C
Right output gain adjustment
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000028
Id
RW Field
A
RW GAINR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
Value
Description
Right output gain adjustment, in 0.5 dB steps, around the
default module gain (see electrical parameters)
MinGain
0x00
-20dB gain adjustment (minimum)
DefaultGain
0x28
0dB gain adjustment ('2500 RMS' requirement)
MaxGain
0x50
+20dB gain adjustment (maximum)
43.7.9 PSEL.CLK
Address offset: 0x540
Pin number configuration for PDM CLK signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
43.7.10 PSEL.DIN
Address offset: 0x544
Page 442
43 PDM — Pulse density modulation interface
Pin number configuration for PDM DIN signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
43.7.11 SAMPLE.PTR
Address offset: 0x560
RAM address pointer to write samples to with EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0
Id
RW Field
Value Id
A
RW SAMPLEPTR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Address to write PDM samples to over DMA
43.7.12 SAMPLE.MAXCNT
Address offset: 0x564
Number of samples to allocate memory for in EasyDMA mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW BUFFSIZE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..32767]
Length of DMA RAM allocation in number of samples
43.8 Electrical specification
43.8.1 PDM Electrical Specification
Symbol
Description
IPDM,stereo
PDM module active current, stereo operation38
Min.
Typ.
1.4
fPDM,CLK
PDM clock speed
1.032
tPDM,JITTER
Jitter in PDM clock output
TdPDM,CLK
PDM clock duty cycle
tPDM,DATA
Max.
Units
mA
MHz
20
ns
60
%
Decimation filter delay
5
ms
tPDM,cv
Allowed clock edge to data valid
125
ns
tPDM,ci
Allowed (other) clock edge to data invalid
0
ns
tPDM,s
Data setup time at fPDM,CLK=1.024 MHz
65
ns
tPDM,h
Data hold time at fPDM,CLK=1.024 MHz
0
GPDM,default
Default (reset) absolute gain of the PDM module
38
40
50
ns
3.2
Average current including PDM and DMA transfers, excluding clock and power supply base currents
Page 443
dB
43 PDM — Pulse density modulation interface
tPDM,CLK
CLK
tPDM,cv
tPDM,s
DIN (L)
tPDM,cv
tPDM,s tPDM,h=tPDM,ci
DIN(R)
Figure 128: PDM timing diagram
Page 444
tPDM,h=tPDM,ci
2
44 I S — Inter-IC sound interface
2
44 I S — Inter-IC sound interface
2
2
The I S (Inter-IC Sound) module, supports the original two-channel I S format, and left or right-aligned
formats. It implements EasyDMA for sample transfer directly to and from RAM without CPU intervention.
2
The I S peripheral has the following main features:
•
•
•
•
•
•
Master and Slave mode
Simultaneous bi-directional (TX and RX) audio streaming
2
Original I S and left- or right-aligned format
8, 16 and 24-bit sample width
Low-jitter Master Clock generator
Various sample rates
PSEL.MCK
PSEL.LRCK
PSEL.SCK
PSEL.SDIN PSEL.SDOUT
I2S
CONFIG.MCKEN
Master clock
generator
MCK
CONFIG.MCKFREQ
CONFIG.RATIO
Div
CONFIG.FORMAT
Div
CONFIG.MODE
Serial tranceiever
TXD.PTR
RXD.PTR
RXTXD.MAXCNT
EasyDMA
SDOUT
SDIN
SCK
LRCK
CONFIG.ALIGN
RAM
2
Figure 129: I S master
44.1 Mode
2
The I S protocol specification defines two modes of operation, Master and Slave.
2
The I S mode decides which of the two sides (Master or Slave) shall provide the clock signals LRCK and
SCK, and these signals are always supplied by the Master to the Slave.
44.2 Transmitting and receiving
2
The I S module supports both transmission (TX) and reception (RX) of serial data. In both cases the serial
data is shifted synchronously to the clock signals SCK and LRCK.
Page 445
2
44 I S — Inter-IC sound interface
TX data is written to the SDOUT pin on the falling edge of SCK, and RX data is read from the SDIN pin on
the rising edge of SCK. The most significant bit (MSB) is always transmitted first.
TX and RX are available in both Master and Slave modes and can be enabled/disabled independently in the
CONFIG.TXEN on page 455 and CONFIG.RXEN on page 455.
Transmission and/or reception is started by triggering the START task. When started and transmission
is enabled (in CONFIG.TXEN on page 455), the TXPTRUPD event will be generated for every
RXTXD.MAXCNT on page 458 number of transmitted data words (containing one or more samples).
Similarly, when started and reception is enabled (in CONFIG.RXEN on page 455), the RXPTRUPD event
will be generated for every RXTXD.MAXCNT on page 458 received data words.
RXTXD.MAXCNT
Left 0
Right 0
Left 1
RIght 1
Left 2
Right 2
Left 3
A
A
A
A
C
C
C
Right 3
C
Left 4
E
B
B
B
B
D
D
D
D
F
RXPTRUPD
TXPTRUPD
RXPTRUPD
RXPTRUPD
TXPTRUPD
RXD.PTR = H
TXD.PTR = G
RXD.PTR = F
TXD.PTR = E
TXD.PTR = C
RXD.PTR = D
START
TXD.PTR = A
RXD.PTR = B
CPU
TXPTRUPD
LRCK
SCK
SDIN
SDOUT
RXTXD.MAXCNT
Figure 130: Transmitting and receiving. CONFIG.FORMAT = Aligned, CONFIG.SWIDTH = 8Bit,
CONFIG.CHANNELS = Stereo, RXTXD.MAXCNT = 1.
44.3 Left right clock (LRCK)
2
The Left Right Clock (LRCK), often referred to as "word clock", "sample clock" or "word select" in I S
context, is the clock defining the frames in the serial bit streams sent and received on SDOUT and SDIN,
respectively.
In I2S mode, each frame contains one left and right sample pair, with the left sample being transferred during
the low half period of LRCK followed by the right sample being transferred during the high period of LRCK.
In Aligned mode, each frame contains one left and right sample pair, with the left sample being transferred
during the high half period of LRCK followed by the right sample being transferred during the low period of
LRCK.
Consequently, the LRCK frequency is equivalent to the audio sample rate.
When operating in Master mode, the LRCK is generated from the MCK, and the frequency of LRCK is then
given as:
LRCK = MCK / CONFIG.RATIO
LRCK always toggles around the falling edge of the serial clock SCK.
44.4 Serial clock (SCK)
The serial clock (SCK), often referred to as the serial bit clock, pulses once for each data bit being
transferred on the serial data lines SDIN and SDOUT.
Page 446
2
44 I S — Inter-IC sound interface
When operating in Master mode the SCK is generated from the MCK, and the frequency of SCK is then
given as:
SCK = 2 * LRCK * CONFIG.SWIDTH
The falling edge of the SCK falls on the toggling edge of LRCK.
2
When operating in Slave mode SCK is provided by the external I S master.
44.5 Master clock (MCK)
The master clock (MCK) is the clock from which LRCK and SCK are derived when operating in Master mode.
The MCK is generated by an internal MCK generator. This generator always needs to be enabled when in
Master mode, but the generator can also be enabled when in Slave mode. Enabling the generator when in
slave mode can be useful in the case where the external Master is not able to generate its own master clock.
The MCK generator is enabled/disabled in the register CONFIG.MCKEN on page 456, and the generator
is started or stopped by the START or STOP tasks.
In Master mode the LRCK and the SCK frequencies are closely related, as both are derived from MCK and
set indirectly through CONFIG.RATIO on page 456 and CONFIG.SWIDTH on page 457.
When configuring these registers, the user is responsible for fulfilling the following requirements:
1. SCK frequency can never exceed the MCK frequency, which can be formulated as:
CONFIG.RATIO >= 2 * CONFIG.SWIDTH
2. The MCK/LRCK ratio shall be a multiple of 2 * CONFIG.SWIDTH, which can be formulated as:
Integer = (CONFIG.RATIO / (2 * CONFIG.SWIDTH))
2
The MCK signal can be routed to an output pin (specified in PSEL.MCK) to supply external I S devices that
require the MCK to be supplied from the outside.
2
When operating in Slave mode, the I S module does not use the MCK and the MCK generator does not
need to be enabled.
RATIO =
MCK
LRCK
MCK
LRCK
SWIDTH
SCK
Figure 131: Relation between RATIO, MCK and LRCK.
Table 105: Configuration examples
Desired LRCK [Hz]
16000
16000
16000
32000
32000
32000
44100
44100
44100
CONFIG.SWIDTH
16Bit
16Bit
16Bit
16Bit
16Bit
16Bit
16Bit
16Bit
16Bit
CONFIG.RATIO
32X
64X
256X
32X
64X
256X
32X
64X
256X
CONFIG.MCKFREQ
32MDIV63
32MDIV31
32MDIV8
32MDIV31
32MDIV16
32MDIV4
32MDIV23
32MDIV11
32MDIV3
MCK [Hz]
507936.5
1032258.1
4000000.0
1032258.1
2000000.0
8000000.0
1391304.3
2909090.9
10666666.7
LRCK [Hz]
15873.0
16129.0
15625.0
32258.1
31250.0
31250.0
43478.3
45454.5
41666.7
LRCK error [%]
-0.8
0.8
-2.3
0.8
-2.3
-2.3
-1.4
3.1
-5.5
44.6 Width, alignment and format
The CONFIG.SWIDTH register primarily defines the sample width of the data written to memory. In master
mode, it then also sets the amount of bits per frame. In Slave mode it controls padding/trimming if required.
Left, right, transmitted, and received samples always have the same width. The CONFIG.FORMAT register
specifies the position of the data frames with respect to the LRCK edges in both Master and Slave modes.
Page 447
2
44 I S — Inter-IC sound interface
2
When using I S format, the first bit in a half-frame (containing one left or right sample) gets sampled on the
second rising edge of the SCK after a LRCK edge. When using Aligned mode, the first bit in a half-frame
gets sampled on the first rising edge of SCK following a LRCK edge.
For data being received on SDIN the sample value can be either right or left-aligned inside a half-frame, as
specified in CONFIG.ALIGN on page 457. CONFIG.ALIGN on page 457 affects only the decoding of
the incoming samples (SDIN), while the outgoing samples (SDOUT) are always left-aligned (or justified).
When using left-alignment, each half-frame starts with the MSB of the sample value (both for data being sent
on SDOUT and received on SDIN).
When using right-alignment, each half-frame of data being received on SDIN ends with the LSB of the
sample value, while each half-frame of data being sent on SDOUT starts with the MSB of the sample value
(same as for left-alignment).
In Master mode, the size of a half-frame (in number of SCK periods) equals the sample width (in number of
bits), and in this case the alignment setting does not care as each half-frame in any case will start with the
MSB and end with the LSB of the sample value.
In slave mode, however, the sample width does not need to equal the frame size. This means you might
have extra or fewer SCK pulses per half-frame than what the sample width specified in CONFIG.SWIDTH
requires.
In the case where we use left-alignment and the number of SCK pulses per half-frame is higher than the
sample width, the following will apply:
•
•
For data received on SDIN, all bits after the LSB of the sample value will be discarded.
For data sent on SDOUT, all bits after the LSB of the sample value will be 0.
In the case where we use left-alignment and the number of SCK pulses per frame is lower than the sample
width, the following will apply:
•
Data sent and received on SDOUT and SDIN will be truncated with the LSBs being removed first.
In the case where we use right-alignment and the number of SCK pulses per frame is higher than the
sample width, the following will apply:
•
•
For data received on SDIN, all bits before the MSB of the sample value will be discarded.
For data sent on SDOUT, all bits after the LSB of the sample value will be 0 (same behavior as for leftalignment).
In the case where we use right-alignment and the number of SCK pulses per frame is lower than the
sample width, the following will apply:
•
•
Data received on SDIN will be sign-extended to "sample width" number of bits before being written to
memory.
Data sent on SDOUT will be truncated with the LSBs being removed first (same behavior as for leftalignment).
frame
left
LRCK
right
left
SCK
SDIN or SDOUT
2
Figure 132: I S format. CONFIG.SWIDTH equalling half-frame size.
frame
LRCK
left
right
SCK
SDATA
Figure 133: Aligned format. CONFIG.SWIDTH equalling half-frame size.
Page 448
left
2
44 I S — Inter-IC sound interface
44.7 EasyDMA
2
The I S module implements EasyDMA for accessing internal Data RAM without CPU intervention.
The source and destination pointers for the TX and RX data are configured in TXD.PTR on page 458 and
RXD.PTR on page 458. The memory pointed to by these pointers will only be read or written when TX or
RX are enabled in CONFIG.TXEN on page 455 and CONFIG.RXEN on page 455.
The addresses written to the pointer registers TXD.PTR on page 458 and RXD.PTR on page 458 are
double-buffered in hardware, and these double buffers are updated for every RXTXD.MAXCNT on page
458 words (containing one or more samples) read/written from/to memory. The events TXPTRUPD and
RXPTRUPD are generated whenever the TXD.PTR and RXD.PTR are transferred to these double buffers.
If TXD.PTR on page 458 is not pointing to the Data RAM region when transmission is enabled, or
RXD.PTR on page 458 is not pointing to the Data RAM region when reception is enabled, an EasyDMA
transfer may result in a HardFault and/or memory corruption. See Memory on page 23 for more information
about the different memory regions.
2
Due to the nature of I S, where the number of transmitted samples always equals the number of received
samples (at least when both TX and RX are enabled), one common register RXTXD.MAXCNT on page
458 is used for specifying the sizes of these two memory buffers. The size of the buffers is specified in
a number of 32-bit words. Such a 32-bit memory word can either contain four 8-bit samples, two 16-bit
samples or one right-aligned 24-bit sample sign extended to 32 bit.
In stereo mode (decided by CONFIG.CHANNELS), the samples are stored as "left and right sample
pairs" in memory. Figure Figure 134: Memory mapping for 8 bit stereo. CONFIG.SWIDTH = 8Bit,
CONFIG.CHANNELS = Stereo. on page 449, Figure 136: Memory mapping for 16 bit stereo.
CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Stereo. on page 450 and Figure 138: Memory
mapping for 24 bit stereo. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Stereo. on page 450 show
how the samples are mapped to memory in this mode.
In mono mode (left or right channel only), samples for only one single channel are stored in memory. Figure
Figure 135: Memory mapping for 8 bit mono. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Left. on
page 450, Figure 137: Memory mapping for 16 bit mono, left channel only. CONFIG.SWIDTH = 16Bit,
CONFIG.CHANNELS = Left. on page 450 and Figure 139: Memory mapping for 24 bit mono, left channel
only. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Left. on page 451 show how samples are
mapped to memory in this mode.
31
24 23
16 15
8 7
0
x.PTR
Right sample 1
Left sample 1
Right sample 0
Left sample 0
x.PTR + 4
Right sample 3
Left sample 3
Right sample 2
Left sample 2
Left sample
n-1
Right sample
n-1
Right sample
n-2
Left sample
n-2
x.PTR + (n*2) - 4
Figure 134: Memory mapping for 8 bit stereo. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo.
Page 449
2
44 I S — Inter-IC sound interface
31
24 23
16 15
8 7
0
x.PTR
Left sample 3
Left sample 2
Left sample 1
Left sample 0
x.PTR + 4
Left sample 7
Left sample 6
Left sample 5
Left sample 4
Left sample
n-1
Left sample
n-2
Left sample
n-3
Left sample
n-4
x.PTR + n - 4
Figure 135: Memory mapping for 8 bit mono. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Left.
31
16 15
0
x.PTR
Right sample 0
Left sample 0
x.PTR + 4
Right sample 1
Left sample 1
Right sample n - 1
Left sample n - 1
x.PTR + (n*4) - 4
Figure 136: Memory mapping for 16 bit stereo. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS =
Stereo.
31
16 15
0
x.PTR
Left sample 1
Left sample 0
x.PTR + 4
Left sample 3
Left sample 2
Left sample n - 1
Left sample n - 2
x.PTR + (n*2) - 4
Figure 137: Memory mapping for 16 bit mono, left channel only. CONFIG.SWIDTH = 16Bit,
CONFIG.CHANNELS = Left.
31
23
0
x.PTR
Sign ext.
Left sample 0
x.PTR + 4
Sign ext.
Right sample 0
x.PTR + (n*8) - 8
Sign ext.
Left sample n - 1
x.PTR + (n*8) - 4
Sign ext.
Right sample n - 1
Figure 138: Memory mapping for 24 bit stereo. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS =
Stereo.
Page 450
2
44 I S — Inter-IC sound interface
31
23
0
x.PTR
Sign ext.
Left sample 0
x.PTR + 4
Sign ext.
Left sample 1
x.PTR + (n*4) - 4
Sign ext.
Left sample n - 1
Figure 139: Memory mapping for 24 bit mono, left channel only. CONFIG.SWIDTH = 24Bit,
CONFIG.CHANNELS = Left.
44.8 Module operation
2
Described here is a typical operating procedure for the I S module.
2
1. Configure the I S module using the CONFIG registers
// Enable reception
NRF_I2S->CONFIG.RXEN = (I2S_CONFIG_RXEN_RXEN_Enabled <<
I2S_CONFIG_RXEN_RXEN_Pos);
// Enable transmission
NRF_I2S->CONFIG.TXEN = (I2S_CONFIG_TXEN_TXEN_Enabled <<
I2S_CONFIG_TXEN_TXEN_Pos);
// Enable MCK generator
NRF_I2S->CONFIG.MCKEN = (I2S_CONFIG_MCKEN_MCKEN_Enabled <<
I2S_CONFIG_MCKEN_MCKEN_Pos);
// MCKFREQ = 4 MHz
NRF_I2S->CONFIG.MCKFREQ = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 <<
I2S_CONFIG_MCKFREQ_MCKFREQ_Pos;
// Ratio = 256
NRF_I2S->CONFIG.RATIO = I2S_CONFIG_RATIO_RATIO_256X <<
I2S_CONFIG_RATIO_RATIO_Pos;
// MCKFREQ = 4 MHz and Ratio = 256 gives sample rate = 15.625 ks/s
// Sample width = 16 bit
NRF_I2S->CONFIG.SWIDTH = I2S_CONFIG_SWIDTH_SWIDTH_16Bit <<
I2S_CONFIG_SWIDTH_SWIDTH_Pos;
// Alignment = Left
NRF_I2S->CONFIG.ALIGN = I2S_CONFIG_ALIGN_ALIGN_Left <<
I2S_CONFIG_ALIGN_ALIGN_Pos;
// Format = I2S
NRF_I2S->CONFIG.FORMAT = I2S_CONFIG_FORMAT_FORMAT_I2S <<
I2S_CONFIG_FORMAT_FORMAT_Pos;
// Use stereo
NRF_I2S->CONFIG.CHANNELS = I2S_CONFIG_CHANNELS_CHANNELS_Stereo <<
I2S_CONFIG_CHANNELS_CHANNELS_Pos;
2. Map IO pins using the PINSEL registers
// MCK routed to pin 0
NRF_I2S->PSEL.MCK = (0 << I2S_PSEL_MCK_CONNECT_Pos) |
(I2S_PSEL_MCK_CONNECT_Connected <<
I2S_PSEL_MCK_CONNECT_Pos);
// SCK routed to pin 1
NRF_I2S->PSEL.SCK = (1 << I2S_PSEL_SCK_CONNECT_Pos) |
(I2S_PSEL_SCK_CONNECT_Connected <<
I2S_PSEL_SCK_CONNECT_Pos);
// LRCK routed to pin 2
NRF_I2S->PSEL.LRCK = (2 << I2S_PSEL_LRCK_CONNECT_Pos) |
(I2S_PSEL_LRCK_CONNECT_Connected <<
Page 451
2
44 I S — Inter-IC sound interface
I2S_PSEL_LRCK_CONNECT_Pos);
// SDOUT routed to pin 3
NRF_I2S->PSEL.SDOUT = (3 << I2S_PSEL_SDOUT_CONNECT_Pos) |
(I2S_PSEL_SDOUT_CONNECT_Connected <<
I2S_PSEL_SDOUT_CONNECT_Pos);
// SDIN routed on pin 4
NRF_I2S->PSEL.SDIN = (4 << I2S_PSEL_SDIN_CONNECT_Pos) |
(I2S_PSEL_SDIN_CONNECT_Connected <<
I2S_PSEL_SDIN_CONNECT_Pos);
3. Configure TX and RX data pointers using the TXD, RXD and RXTXD registers
NRF_I2S->TXD.PTR = my_tx_buf;
NRF_I2S->RXD.PTR = my_rx_buf;
NRF_I2S->TXD.MAXCNT = MY_BUF_SIZE;
2
4. Enable the I S module using the ENABLE register
NRF_I2S->ENABLE = 1;
5. Start audio streaming using the START task
NRF_I2S->TASKS_START = 1;
6. Handle received and transmitted data when receiving the TXPTRUPD and RXPTRUPD events
if(NRF_I2S->EVENTS_TXPTRUPD != 0)
{
NRF_I2S->TXD.PTR = my_next_tx_buf;
NRF_I2S->EVENTS_TXPTRUPD = 0;
}
if(NRF_I2S->EVENTS_RXPTRUPD != 0)
{
NRF_I2S->RXD.PTR = my_next_rx_buf;
NRF_I2S->EVENTS_RXPTRUPD = 0;
}
44.9 Pin configuration
2
The MCK, SCK, LRCK, SDIN and SDOUT signals associated with the I S module are mapped to physical
pins according to the pin numbers specified in the PSEL.x registers.
2
These pins are acquired whenever the I S module is enabled through the register ENABLE on page 455.
2
When a pin is acquired by the I S module, the direction of the pin (input or output) will be configured
automatically, and any pin direction setting done in the GPIO module will be overridden. The directions for
2
the various I S pins are shown below in Table 106: GPIO configuration before enabling peripheral (master
mode) on page 452 and Table 107: GPIO configuration before enabling peripheral (slave mode) on page
453.
2
To secure correct signal levels on the pins when the system is in OFF mode, and when the I S module is
disabled, these pins must be configured in the GPIO peripheral directly.
Table 106: GPIO configuration before enabling peripheral (master mode)
I2S signal
MCK
LRCK
I2S pin
As specified in PSEL.MCK
As specified in PSEL.LRCK
Direction
Output
Output
Page 452
Output value
0
0
Comment
2
44 I S — Inter-IC sound interface
I2S signal
SCK
SDIN
SDOUT
I2S pin
As specified in PSEL.SCK
As specified in PSEL.SDIN
As specified in PSEL.SDOUT
Direction
Output
Input
Output
Output value
0
Not applicable
0
Comment
Table 107: GPIO configuration before enabling peripheral (slave mode)
I2S signal
MCK
LRCK
SCK
SDIN
SDOUT
I2S pin
As specified in PSEL.MCK
As specified in PSEL.LRCK
As specified in PSEL.SCK
As specified in PSEL.SDIN
As specified in PSEL.SDOUT
Direction
Output
Input
Input
Input
Output
Output value
0
Not applicable
Not applicable
Not applicable
0
Comment
44.10 Registers
Table 108: Instances
Base address
Peripheral
Instance
Description
0x40025000
I2S
I2S
Inter-IC Sound Interface
Configuration
Table 109: Register Overview
Register
Offset
Description
TASKS_START
0x000
Starts continuous I2S transfer. Also starts MCK generator when this is enabled.
TASKS_STOP
0x004
Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED}
EVENTS_RXPTRUPD
0x104
event to be generated.
The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started
and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on
the SDIN pin.
EVENTS_STOPPED
0x108
I2S transfer stopped.
EVENTS_TXPTRUPD
0x114
The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started
and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the
SDOUT pin.
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ENABLE
0x500
Enable I2S module.
CONFIG.MODE
0x504
I2S mode.
CONFIG.RXEN
0x508
Reception (RX) enable.
CONFIG.TXEN
0x50C
Transmission (TX) enable.
CONFIG.MCKEN
0x510
Master clock generator enable.
CONFIG.MCKFREQ
0x514
Master clock generator frequency.
CONFIG.RATIO
0x518
MCK / LRCK ratio.
CONFIG.SWIDTH
0x51C
Sample width.
CONFIG.ALIGN
0x520
Alignment of sample within a frame.
CONFIG.FORMAT
0x524
Frame format.
CONFIG.CHANNELS
0x528
Enable channels.
RXD.PTR
0x538
Receive buffer RAM start address.
TXD.PTR
0x540
Transmit buffer RAM start address.
RXTXD.MAXCNT
0x550
Size of RXD and TXD buffers.
PSEL.MCK
0x560
Pin select for MCK signal.
PSEL.SCK
0x564
Pin select for SCK signal.
PSEL.LRCK
0x568
Pin select for LRCK signal.
PSEL.SDIN
0x56C
Pin select for SDIN signal.
PSEL.SDOUT
0x570
Pin select for SDOUT signal.
44.10.1 INTEN
Address offset: 0x300
Enable or disable interrupt
Page 453
2
44 I S — Inter-IC sound interface
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F
Reset 0x00000000
Id
RW Field
B
RW RXPTRUPD
0
Value Id
C B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for RXPTRUPD event
See EVENTS_RXPTRUPD
C
Disabled
0
Disable
Enabled
1
Enable
RW STOPPED
Enable or disable interrupt for STOPPED event
See EVENTS_STOPPED
F
Disabled
0
Disable
Enabled
1
Enable
RW TXPTRUPD
Enable or disable interrupt for TXPTRUPD event
See EVENTS_TXPTRUPD
Disabled
0
Disable
Enabled
1
Enable
44.10.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F
Reset 0x00000000
Id
RW Field
B
RW RXPTRUPD
0
Value Id
C B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for RXPTRUPD event
See EVENTS_RXPTRUPD
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Enable interrupt for STOPPED event
See EVENTS_STOPPED
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXPTRUPD
Write '1' to Enable interrupt for TXPTRUPD event
See EVENTS_TXPTRUPD
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
44.10.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F
Reset 0x00000000
Id
RW Field
B
RW RXPTRUPD
0
Value Id
Value
Description
Write '1' to Disable interrupt for RXPTRUPD event
See EVENTS_RXPTRUPD
C
C B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Disable interrupt for STOPPED event
Page 454
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44 I S — Inter-IC sound interface
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F
Reset 0x00000000
Id
RW Field
0
C B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_STOPPED
F
RW TXPTRUPD
Write '1' to Disable interrupt for TXPTRUPD event
See EVENTS_TXPTRUPD
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
44.10.4 ENABLE
Address offset: 0x500
Enable I2S module.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Enable I2S module.
44.10.5 CONFIG.MODE
Address offset: 0x504
I2S mode.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW MODE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Master
0
Slave
1
Description
I2S mode.
Master mode. SCK and LRCK generated from internal master
clcok (MCK) and output on pins defined by PSEL.xxx.
Slave mode. SCK and LRCK generated by external master and
received on pins defined by PSEL.xxx
44.10.6 CONFIG.RXEN
Address offset: 0x508
Reception (RX) enable.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW RXEN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Disabled
0
Enabled
1
Description
Reception (RX) enable.
Reception disabled and now data will be written to the RXD.PTR
address.
Reception enabled.
44.10.7 CONFIG.TXEN
Address offset: 0x50C
Page 455
2
44 I S — Inter-IC sound interface
Transmission (TX) enable.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000001
Id
RW Field
A
RW TXEN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Disabled
0
Enabled
1
Description
Transmission (TX) enable.
Transmission disabled and now data will be read from the
RXD.TXD address.
Transmission enabled.
44.10.8 CONFIG.MCKEN
Address offset: 0x510
Master clock generator enable.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000001
Id
RW Field
A
RW MCKEN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Disabled
0
Enabled
1
Description
Master clock generator enable.
Master clock generator disabled and PSEL.MCK not
connected(available as GPIO).
Master clock generator running and MCK output on PSEL.MCK.
44.10.9 CONFIG.MCKFREQ
Address offset: 0x514
Master clock generator frequency.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x20000000
Id
RW Field
A
RW MCKFREQ
0
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
32MDIV2
0x80000000
32 MHz / 2 = 16.0 MHz
32MDIV3
0x50000000
32 MHz / 3 = 10.6666667 MHz
32MDIV4
0x40000000
32 MHz / 4 = 8.0 MHz
32MDIV5
0x30000000
32 MHz / 5 = 6.4 MHz
32MDIV6
0x28000000
32 MHz / 6 = 5.3333333 MHz
32MDIV8
0x20000000
32 MHz / 8 = 4.0 MHz
32MDIV10
0x18000000
32 MHz / 10 = 3.2 MHz
32MDIV11
0x16000000
32 MHz / 11 = 2.9090909 MHz
32MDIV15
0x11000000
32 MHz / 15 = 2.1333333 MHz
32MDIV16
0x10000000
32 MHz / 16 = 2.0 MHz
32MDIV21
0x0C000000
32 MHz / 21 = 1.5238095
32MDIV23
0x0B000000
32 MHz / 23 = 1.3913043 MHz
32MDIV30
0x08800000
32 MHz / 30 = 1.0666667 MHz
32MDIV31
0x08400000
32 MHz / 31 = 1.0322581 MHz
32MDIV32
0x08000000
32 MHz / 32 = 1.0 MHz
32MDIV42
0x06000000
32 MHz / 42 = 0.7619048 MHz
32MDIV63
0x04100000
32 MHz / 63 = 0.5079365 MHz
32MDIV125
0x020C0000
32 MHz / 125 = 0.256 MHz
Master clock generator frequency.
44.10.10 CONFIG.RATIO
Address offset: 0x518
MCK / LRCK ratio.
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2
44 I S — Inter-IC sound interface
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000006
Id
RW Field
A
RW RATIO
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
Value Id
Value
Description
32X
0
LRCK = MCK / 32
48X
1
LRCK = MCK / 48
64X
2
LRCK = MCK / 64
96X
3
LRCK = MCK / 96
128X
4
LRCK = MCK / 128
192X
5
LRCK = MCK / 192
256X
6
LRCK = MCK / 256
384X
7
LRCK = MCK / 384
512X
8
LRCK = MCK / 512
MCK / LRCK ratio.
44.10.11 CONFIG.SWIDTH
Address offset: 0x51C
Sample width.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000001
Id
RW Field
A
RW SWIDTH
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Description
8Bit
0
8 bit.
16Bit
1
16 bit.
24Bit
2
24 bit.
Sample width.
44.10.12 CONFIG.ALIGN
Address offset: 0x520
Alignment of sample within a frame.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ALIGN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Left
0
Left-aligned.
Right
1
Right-aligned.
Alignment of sample within a frame.
44.10.13 CONFIG.FORMAT
Address offset: 0x524
Frame format.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW FORMAT
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
I2S
0
Original I2S format.
Aligned
1
Alternate (left- or right-aligned) format.
Frame format.
44.10.14 CONFIG.CHANNELS
Address offset: 0x528
Enable channels.
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2
44 I S — Inter-IC sound interface
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000000
Id
RW Field
A
RW CHANNELS
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Stereo
0
Stereo.
Left
1
Left only.
Right
2
Right only.
Enable channels.
44.10.15 RXD.PTR
Address offset: 0x538
Receive buffer RAM start address.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Receive buffer Data RAM start address. When receiving, words
containing samples will be written to this address. This address
is a word aligned Data RAM address.
44.10.16 TXD.PTR
Address offset: 0x540
Transmit buffer RAM start address.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Transmit buffer Data RAM start address. When transmitting,
words containing samples will be fetched from this address. This
address is a word aligned Data RAM address.
44.10.17 RXTXD.MAXCNT
Address offset: 0x550
Size of RXD and TXD buffers.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Size of RXD and TXD buffers in number of 32 bit words.
44.10.18 PSEL.MCK
Address offset: 0x560
Pin select for MCK signal.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
Page 458
2
44 I S — Inter-IC sound interface
44.10.19 PSEL.SCK
Address offset: 0x564
Pin select for SCK signal.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
44.10.20 PSEL.LRCK
Address offset: 0x568
Pin select for LRCK signal.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
44.10.21 PSEL.SDIN
Address offset: 0x56C
Pin select for SDIN signal.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
44.10.22 PSEL.SDOUT
Address offset: 0x570
Pin select for SDOUT signal.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
Page 459
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44 I S — Inter-IC sound interface
44.11 Electrical specification
44.11.1 I2S timing specification
Symbol
Description
Min.
tS_SDIN
SDIN setup time before SCK rising
20
Typ.
Max.
Units
ns
tH_SDIN
SDIN hold time after SCK rising
15
ns
tS_SDOUT
SDOUT setup time after SCK falling
40
ns
tH_SDOUT
SDOUT hold time before SCK falling
6
tSCK_LRCK
SCLK falling to LRCK edge
-5
fMCK
ns
0
5
ns
MCK frequency
4000
kHz
fLRCK
LRCK frequency
48
kHz
fSCK
SCK frequency
2000
kHz
DCCK
Clock duty cycle (MCK, LRCK, SCK)
55
%
45
tSCK_LRCK
LRCK
SCK
tS_SDIN
tH_SDIN
SDIN
tH_SDOUT
SDOUT
Figure 140: I2S timing diagram
Page 460
tS_SDOUT
45 MWU — Memory watch unit
45 MWU — Memory watch unit
The Memory watch unit (MWU) can be used to generate events when a memory region is accessed
by the CPU. The MWU can be configured to trigger events for access to Data RAM and Peripheral
memory segments. The MWU allows an application developer to generate memory access events during
development for debugging or during production execution for failure detection and recovery.
Listed here are the main features for MWU:
•
•
•
•
•
Six memory regions, four user-configurable and two fixed regions in peripheral address space
Flexible configuration of regions with START and END addresses
Generate events on CPU read and/or write to a defined region of Data RAM or peripheral memory
address space
Programmable maskable or non-maskable (NMI) interrupt on events
Peripheral interfaces can be watched for read and write access using subregions of the two fixed memory
regions
Table 110: Memory regions
Memory region
REGION[0..3]
PREGION[0]
PREGION[1]
START address
Configurable
0x40000000
0x40020000
END address
Configurable
0x4001FFFF
0x4003FFFF
Each MWU region is defined by a start address and an end address, configured by the START and END
registers respectively. These addresses are byte aligned and inclusive. The END register value has to be
greater or equal to the START register value. Each region is associated with a pair of events that indicate
that either a write access or a read access from the CPU has been detected inside the region.
For regions containing subregions (see below), a set of status registers PERREGION[0..1].SUBSTATWA
and PERREGION[0..1].SUBSTATRA indicate which subregion(s) caused the EVENT_PREGION[0..1].WA
and EVENT_PREGION[0..1].RA respectively.
The MWU is only able to detect memory accesses in the Data RAM and Peripheral memory segments from
the CPU, see Memory on page 23 for more information about the different memory segments. EasyDMA
accesses are not monitored by the MWU. The MWU requires two HCLK cycles to detect and generate the
event.
The peripheral regions, PREGION[0...1], are divided into 32 equally sized subregions, SR[0...31]. All
subregions are excluded in the main region by default, and any can be included by specifying them in the
SUBS register. When a subregion is excluded from the main region, the memory watch mechanism will not
trigger any events when that subregion is accessed.
Subregions in PREGION[0..1] cannot be individually configured for read or write access watch. Watch
configuration is only possible for a region as a whole. The PRGNiRA and PRGNiWA (i=0..1) fields in the
REGIONEN register control watching read and write access.
REGION[0..3] can be individually enabled for read and/or write access watching through their respective
RGNiRA and RGNiWA (i=0..3) fields in the REGIONEN register.
REGIONENSET and REGIONENCLR allow respectively enabling and disabling one or multiple REGIONs or
PREGIONs watching in a single write access.
45.1 Registers
Table 111: Instances
Base address
Peripheral
Instance
Description
0x40020000
MWU
MWU
Memory Watch Unit
Page 461
Configuration
45 MWU — Memory watch unit
Table 112: Register Overview
Register
Offset
Description
EVENTS_REGION[0].WA 0x100
Write access to region 0 detected
EVENTS_REGION[0].RA 0x104
Read access to region 0 detected
EVENTS_REGION[1].WA 0x108
Write access to region 1 detected
EVENTS_REGION[1].RA 0x10C
Read access to region 1 detected
EVENTS_REGION[2].WA 0x110
Write access to region 2 detected
EVENTS_REGION[2].RA 0x114
Read access to region 2 detected
EVENTS_REGION[3].WA 0x118
Write access to region 3 detected
EVENTS_REGION[3].RA 0x11C
Read access to region 3 detected
EVENTS_PREGION[0].WA 0x160
Write access to peripheral region 0 detected
EVENTS_PREGION[0].RA 0x164
Read access to peripheral region 0 detected
EVENTS_PREGION[1].WA 0x168
Write access to peripheral region 1 detected
EVENTS_PREGION[1].RA 0x16C
Read access to peripheral region 1 detected
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
NMIEN
0x320
Enable or disable non-maskable interrupt
NMIENSET
0x324
Enable non-maskable interrupt
NMIENCLR
0x328
Disable non-maskable interrupt
PERREGION[0].SUBSTATWA
0x400
Source of event/interrupt in region 0, write access detected while corresponding subregion was
enabled for watching
PERREGION[0].SUBSTATRA
0x404
Source of event/interrupt in region 0, read access detected while corresponding subregion was
enabled for watching
PERREGION[1].SUBSTATWA
0x408
Source of event/interrupt in region 1, write access detected while corresponding subregion was
enabled for watching
PERREGION[1].SUBSTATRA
0x40C
Source of event/interrupt in region 1, read access detected while corresponding subregion was
enabled for watching
REGIONEN
0x510
Enable/disable regions watch
REGIONENSET
0x514
Enable regions watch
REGIONENCLR
0x518
Disable regions watch
REGION[0].START
0x600
Start address for region 0
REGION[0].END
0x604
End address of region 0
REGION[1].START
0x610
Start address for region 1
REGION[1].END
0x614
End address of region 1
REGION[2].START
0x620
Start address for region 2
REGION[2].END
0x624
End address of region 2
REGION[3].START
0x630
Start address for region 3
REGION[3].END
0x634
End address of region 3
PREGION[0].START
0x6C0
Reserved for future use
PREGION[0].END
0x6C4
Reserved for future use
PREGION[0].SUBS
0x6C8
Subregions of region 0
PREGION[1].START
0x6D0
Reserved for future use
PREGION[1].END
0x6D4
Reserved for future use
PREGION[1].SUBS
0x6D8
Subregions of region 1
45.1.1 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW REGION0WA
0
Value Id
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for REGION[0].WA event
See EVENTS_REGION[0].WA
Disabled
0
Disable
Page 462
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
B
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Enable
RW REGION0RA
Enable or disable interrupt for REGION[0].RA event
See EVENTS_REGION[0].RA
C
Disabled
0
Disable
Enabled
1
Enable
RW REGION1WA
Enable or disable interrupt for REGION[1].WA event
See EVENTS_REGION[1].WA
D
Disabled
0
Disable
Enabled
1
Enable
RW REGION1RA
Enable or disable interrupt for REGION[1].RA event
See EVENTS_REGION[1].RA
E
Disabled
0
Disable
Enabled
1
Enable
RW REGION2WA
Enable or disable interrupt for REGION[2].WA event
See EVENTS_REGION[2].WA
F
Disabled
0
Disable
Enabled
1
Enable
RW REGION2RA
Enable or disable interrupt for REGION[2].RA event
See EVENTS_REGION[2].RA
G
Disabled
0
Disable
Enabled
1
Enable
RW REGION3WA
Enable or disable interrupt for REGION[3].WA event
See EVENTS_REGION[3].WA
H
Disabled
0
Disable
Enabled
1
Enable
RW REGION3RA
Enable or disable interrupt for REGION[3].RA event
See EVENTS_REGION[3].RA
I
Disabled
0
Disable
Enabled
1
Enable
RW PREGION0WA
Enable or disable interrupt for PREGION[0].WA event
See EVENTS_PREGION[0].WA
J
Disabled
0
Disable
Enabled
1
Enable
RW PREGION0RA
Enable or disable interrupt for PREGION[0].RA event
See EVENTS_PREGION[0].RA
K
Disabled
0
Disable
Enabled
1
Enable
RW PREGION1WA
Enable or disable interrupt for PREGION[1].WA event
See EVENTS_PREGION[1].WA
L
Disabled
0
Disable
Enabled
1
Enable
RW PREGION1RA
Enable or disable interrupt for PREGION[1].RA event
See EVENTS_PREGION[1].RA
Disabled
0
Disable
Enabled
1
Enable
45.1.2 INTENSET
Address offset: 0x304
Enable interrupt
Page 463
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW REGION0WA
0
Value Id
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for REGION[0].WA event
See EVENTS_REGION[0].WA
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION0RA
Write '1' to Enable interrupt for REGION[0].RA event
See EVENTS_REGION[0].RA
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1WA
Write '1' to Enable interrupt for REGION[1].WA event
See EVENTS_REGION[1].WA
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1RA
Write '1' to Enable interrupt for REGION[1].RA event
See EVENTS_REGION[1].RA
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2WA
Write '1' to Enable interrupt for REGION[2].WA event
See EVENTS_REGION[2].WA
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2RA
Write '1' to Enable interrupt for REGION[2].RA event
See EVENTS_REGION[2].RA
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION3WA
Write '1' to Enable interrupt for REGION[3].WA event
See EVENTS_REGION[3].WA
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION3RA
Write '1' to Enable interrupt for REGION[3].RA event
See EVENTS_REGION[3].RA
I
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION0WA
Write '1' to Enable interrupt for PREGION[0].WA event
See EVENTS_PREGION[0].WA
J
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION0RA
Write '1' to Enable interrupt for PREGION[0].RA event
See EVENTS_PREGION[0].RA
K
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION1WA
Write '1' to Enable interrupt for PREGION[1].WA event
Page 464
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_PREGION[1].WA
L
RW PREGION1RA
Write '1' to Enable interrupt for PREGION[1].RA event
See EVENTS_PREGION[1].RA
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
45.1.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW REGION0WA
0
Value Id
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for REGION[0].WA event
See EVENTS_REGION[0].WA
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION0RA
Write '1' to Disable interrupt for REGION[0].RA event
See EVENTS_REGION[0].RA
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1WA
Write '1' to Disable interrupt for REGION[1].WA event
See EVENTS_REGION[1].WA
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1RA
Write '1' to Disable interrupt for REGION[1].RA event
See EVENTS_REGION[1].RA
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2WA
Write '1' to Disable interrupt for REGION[2].WA event
See EVENTS_REGION[2].WA
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2RA
Write '1' to Disable interrupt for REGION[2].RA event
See EVENTS_REGION[2].RA
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION3WA
Write '1' to Disable interrupt for REGION[3].WA event
See EVENTS_REGION[3].WA
Clear
1
Disable
Page 465
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
H
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION3RA
Write '1' to Disable interrupt for REGION[3].RA event
See EVENTS_REGION[3].RA
I
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION0WA
Write '1' to Disable interrupt for PREGION[0].WA event
See EVENTS_PREGION[0].WA
J
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION0RA
Write '1' to Disable interrupt for PREGION[0].RA event
See EVENTS_PREGION[0].RA
K
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION1WA
Write '1' to Disable interrupt for PREGION[1].WA event
See EVENTS_PREGION[1].WA
L
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION1RA
Write '1' to Disable interrupt for PREGION[1].RA event
See EVENTS_PREGION[1].RA
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
45.1.4 NMIEN
Address offset: 0x320
Enable or disable non-maskable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW REGION0WA
0
Value Id
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable non-maskable interrupt for REGION[0].WA
event
See EVENTS_REGION[0].WA
B
Disabled
0
Disable
Enabled
1
Enable
RW REGION0RA
Enable or disable non-maskable interrupt for REGION[0].RA
event
See EVENTS_REGION[0].RA
C
Disabled
0
Disable
Enabled
1
Enable
RW REGION1WA
Enable or disable non-maskable interrupt for REGION[1].WA
event
See EVENTS_REGION[1].WA
Disabled
0
Disable
Enabled
1
Enable
Page 466
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
D
RW REGION1RA
0
Value Id
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable non-maskable interrupt for REGION[1].RA
event
See EVENTS_REGION[1].RA
E
Disabled
0
Disable
Enabled
1
Enable
RW REGION2WA
Enable or disable non-maskable interrupt for REGION[2].WA
event
See EVENTS_REGION[2].WA
F
Disabled
0
Disable
Enabled
1
Enable
RW REGION2RA
Enable or disable non-maskable interrupt for REGION[2].RA
event
See EVENTS_REGION[2].RA
G
Disabled
0
Disable
Enabled
1
Enable
RW REGION3WA
Enable or disable non-maskable interrupt for REGION[3].WA
event
See EVENTS_REGION[3].WA
H
Disabled
0
Disable
Enabled
1
Enable
RW REGION3RA
Enable or disable non-maskable interrupt for REGION[3].RA
event
See EVENTS_REGION[3].RA
I
Disabled
0
Disable
Enabled
1
Enable
RW PREGION0WA
Enable or disable non-maskable interrupt for PREGION[0].WA
event
See EVENTS_PREGION[0].WA
J
Disabled
0
Disable
Enabled
1
Enable
RW PREGION0RA
Enable or disable non-maskable interrupt for PREGION[0].RA
event
See EVENTS_PREGION[0].RA
K
Disabled
0
Disable
Enabled
1
Enable
RW PREGION1WA
Enable or disable non-maskable interrupt for PREGION[1].WA
event
See EVENTS_PREGION[1].WA
L
Disabled
0
Disable
Enabled
1
Enable
RW PREGION1RA
Enable or disable non-maskable interrupt for PREGION[1].RA
event
See EVENTS_PREGION[1].RA
Disabled
0
Disable
Enabled
1
Enable
45.1.5 NMIENSET
Address offset: 0x324
Enable non-maskable interrupt
Page 467
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW REGION0WA
0
Value Id
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable non-maskable interrupt for REGION[0].WA
event
See EVENTS_REGION[0].WA
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION0RA
Write '1' to Enable non-maskable interrupt for REGION[0].RA
event
See EVENTS_REGION[0].RA
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1WA
Write '1' to Enable non-maskable interrupt for REGION[1].WA
event
See EVENTS_REGION[1].WA
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1RA
Write '1' to Enable non-maskable interrupt for REGION[1].RA
event
See EVENTS_REGION[1].RA
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2WA
Write '1' to Enable non-maskable interrupt for REGION[2].WA
event
See EVENTS_REGION[2].WA
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2RA
Write '1' to Enable non-maskable interrupt for REGION[2].RA
event
See EVENTS_REGION[2].RA
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION3WA
Write '1' to Enable non-maskable interrupt for REGION[3].WA
event
See EVENTS_REGION[3].WA
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION3RA
Write '1' to Enable non-maskable interrupt for REGION[3].RA
event
See EVENTS_REGION[3].RA
I
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION0WA
Write '1' to Enable non-maskable interrupt for PREGION[0].WA
event
See EVENTS_PREGION[0].WA
Page 468
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
J
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION0RA
Write '1' to Enable non-maskable interrupt for PREGION[0].RA
event
See EVENTS_PREGION[0].RA
K
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION1WA
Write '1' to Enable non-maskable interrupt for PREGION[1].WA
event
See EVENTS_PREGION[1].WA
L
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION1RA
Write '1' to Enable non-maskable interrupt for PREGION[1].RA
event
See EVENTS_PREGION[1].RA
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
45.1.6 NMIENCLR
Address offset: 0x328
Disable non-maskable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW REGION0WA
0
Value Id
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable non-maskable interrupt for REGION[0].WA
event
See EVENTS_REGION[0].WA
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION0RA
Write '1' to Disable non-maskable interrupt for REGION[0].RA
event
See EVENTS_REGION[0].RA
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1WA
Write '1' to Disable non-maskable interrupt for REGION[1].WA
event
See EVENTS_REGION[1].WA
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1RA
Write '1' to Disable non-maskable interrupt for REGION[1].RA
event
See EVENTS_REGION[1].RA
Page 469
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
E
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2WA
Write '1' to Disable non-maskable interrupt for REGION[2].WA
event
See EVENTS_REGION[2].WA
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2RA
Write '1' to Disable non-maskable interrupt for REGION[2].RA
event
See EVENTS_REGION[2].RA
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Re