Chapter 7 Memory and Programmable Logic Outline

Chapter 7 Memory and Programmable Logic Outline
Chapter 7
Memory and
Programmable Logic
7-1
Outline
!
!
!
!
!
!
!
Introduction
Random-Access Memory
Memory Decoding
Error Detection and Correction
Read-Only Memory
Programmable Devices
Sequential Programmable Devices
7-2
1
Mass Memory Elements
!
!
Memory is a collection of binary cells together
with associated circuits needed to transfer
information to or from any desired location
Two primary categories of memory:
!
!
Random access memory (RAM)
Read only memory (ROM)
7-3
Programmable Logic Device
!
The binary information within the device can be
specified in some fashion and then embedded
within the hardware
!
!
Most of them are programmed by breaking the fuses
of unnecessary connections
Four kinds of PLD are introduced
!
!
!
!
Read-only memory (ROM)
Programmable logic array (PLA)
Programmable array logic (PAL)
Field-programmable gate array (FPGA)
7-4
2
Outline
!
!
!
!
!
!
!
Introduction
Random-Access Memory
Memory Decoding
Error Detection and Correction
Read-Only Memory
Combinational Programmable Devices
Sequential Programmable Devices
7-5
Random Access Memory
!
A word is the basic unit that
moves in and out of memory
!
!
The length of a word is often
multiples of a byte (=8 bits)
Memory units are specified
by its number of words
and the number of bits in
each word
!
!
Ex: 1024(words) x 16(bits)
Each word is assigned a
particular address, starting
from 0 up to 2k – 1
(k = number of address lines)
7-6
3
Write and Read Operations
!
Write to RAM
!
!
!
!
Apply the binary address of the desired word
to the address lines
Apply the data bits that must be stored in
memory to the data input lines
Activate the write control
Read from RAM
!
!
Apply the binary address of the desired word
to the address lines
Activate the read control
7-7
Timing Waveforms
!
CPU clock = 50 MHz
!
!
Memory access time
= 50 ns
!
!
cycle time = 20 ns
The time required to
complete a read or write
operation
The control signals
must stay active for at
least 50 ns
!
3 CPU cycles are required
7-8
4
Types of Memories
!
Access mode:
!
!
!
Operating mode:
!
!
!
Random access: any locations can be accessed in any order
Sequential access: accessed only when the requested word
has been reached (ex: hard disk)
Static RAM (SRAM)
Dynamic RAM (DRAM)
Volatile mode:
!
!
Volatile memory: lose stored information when power is
turned off (ex: RAM)
Non-volatile memory: retain its storage after removal of
power (ex: flash, ROM, hard-disk, …)
7-9
SRAM vs. DRAM
!
Static RAM:
!
!
!
!
Use internal latch to store
the binary information
Stored information remains
valid as long as power is on
Shorter read and write cycles
Larger cell area and power
consumption
!
Dynamic RAM:
!
!
!
!
Use a capacitor to store the
binary information
Need periodically refreshing
to hold the stored info.
Longer read and write cycles
Smaller cell area and power
consumption
7-10
5
Outline
!
!
!
!
!
!
!
Introduction
Random-Access Memory
Memory Decoding
Error Detection and Correction
Read-Only Memory
Combinational Programmable Devices
Sequential Programmable Devices
7-11
Memory Construction
A SRAM Cell
Large memory
will require
large decoder
7-12
6
Coincident Decoding
!
Address decoders are often
divided into two parts
!
!
!
!
A two-dimensional scheme
The total number of gates in
decoders can be reduced
Can arrange the
memory cells to a
square shape
EX: 10-bit address
404 = 0110010100
X = 01100 (first five)
Y = 10100 (last five)
7-13
Address Multiplexing
!
Memory address lines often
occupy too much I/O pads
!
!
!
Share the address lines of
X and Y domains
!
!
!
64K = 16 lines
256M = 28 lines
Reduce the number of lines
to a half
An extra register is required
for both domain to store the
address
Two steps to send address
!
!
RAS=0: send row address
CAS=0: send column address
7-14
7
Outline
!
!
!
!
!
!
!
Introduction
Random-Access Memory
Memory Decoding
Error Detection and Correction
Read-Only Memory
Combinational Programmable Devices
Sequential Programmable Devices
7-15
Error Detection & Correction
!
Memory arrays are often very huge
!
!
!
Reliability of memory can be improved by
employing error-detecting and correcting codes
Error-detecting code: only check for the existence
of errors
!
!
May cause occasional errors in data access
Most common scheme is the parity bit
Error-correcting code: check the existence and
locations of errors
!
!
Use multiple parity check bits to generate a syndrome
that can indicate the erroneous bits
Complement the erroneous bits can correct the errors
7-16
8
Hamming Code (1/2)
!
!
k parity bits are added to an n-bit data word
The positions numbered as a power of 2 are
reserved for the parity bits
Ex: original data is 11000100 (8-bit)
⇒ Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
P1 P2 1 P4 1 0 0 P8 0 1 0 0
! P1 = XOR of bits (3,5,7,9,11) = 0
P2 = XOR of bits (3,6,7,10,11) =0
P4 = XOR of bits (5,6,7,12) = 1
P8 = XOR of bits (9,10,11,12) = 1
! The composite word is 001110010100 (12-bit)
!
7-17
Hamming Code (2/2)
!
When the 12 bits are read from memory, the parity
is checked over the same combination of bits
including the parity bit
!
!
C1
C2
C4
C8
=
=
=
=
XOR
XOR
XOR
XOR
of
of
of
of
bits
bits
bits
bits
(1,3,5,7,9,11)
(2,3,6,7,10,11)
(4,5,6,7,12)
(8,9,10,11,12)
(001110010100) " C = C8C4C2C1 = 0000 : no error
(101110010100) " C = C8C4C2C1 = 0001 : bit 1 error
(001100010100) " C = C8C4C2C1 = 0101 : bit 5 error
viewed as a binary number
7-18
9
General Rules of Hamming Code
!
The number of parity bits:
!
!
!
The syndrome C with k bits can
represent 2k – 1 error locations
(0 indicates no error)
2k – 1 ≥ n + k " 2k – 1 – k ≥ n
Number of
Check Bits, k
3
4
5
6
7
Range of
Data Bits, n
2-4
5-11
12-26
27-57
58-120
The members of each parity bit:
!
!
!
C1(P1): have a “1” in bit 1 of their location numbers
1(0001), 3(0011), 5(0101), 7(0111), 9(1001), …
C2(P2): have a “1” in bit 2 of their location numbers
2(0010), 3(0011), 6(0110), 7(0111), 10(1010), …
C: with parity bit; P: without parity bit itself
7-19
Extension of Hamming Code
!
Original Hamming code can detect and correct
only a single error
!
!
Add an extra bit as the parity of total coded word
!
!
!
Multiple errors are not detected
Ex: 001110010100P13 (P13=XOR of bits 1 to 12)
Still single-error correction but double-error detection
Four cases can occur:
!
!
!
!
If
If
If
If
C=0 and P=0, no error occurred
C≠0 and P=1, single error occurred (can be fixed)
C≠0 and P=0, double error occurred (cannot be fixed)
C=0 and P=1, an error occurred in the P13 bit
7-20
10
Outline
!
!
!
!
!
!
!
Introduction
Random-Access Memory
Memory Decoding
Error Detection and Correction
Read-Only Memory
Combinational Programmable Devices
Sequential Programmable Devices
7-21
Read Only Memory
!
A memory device that can permanently keep binary data
!
!
Even when power is turned off and on again
For a 2k x n ROM,
it consists of
!
!
!
!
!
k inputs (address line)
and n outputs (data)
2k words of n-bit each
A k x 2k decoder
(generate all minterms)
n OR gates with 2k inputs
Initially, all inputs of OR gates
and all outputs of the decoder
are fully connected
7-22
11
Programming the ROM
!
!
Each intersection (crosspoint) in the ROM is often
implemented with a fuse
Blow out
unnecessary
connections
according to
the truth table
!
!
!
“1” means
connected
(marked as X)
“0” means unconnected
Cannot recovered after
programmed
7-23
Design Comb. Circuit with ROM
!
!
!
Derive the truth
table of the circuit
Determine minimum
size of ROM
Program the ROM
A2
0
0
0
0
1
1
1
1
Inputs
A1 A0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Outputs
B5 B4 B3 B2
0 0 0 0
0 0 0 0
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 1 0 0
B1 B0
0 0
0 1
0 0
0 1
0 0
0 1
0 0
0 1
Decimal
0
1
4
9
16
25
36
49
3 select lines
= 8 minterms
word
length
=4
7-24
12
Types of ROMs
!
Mask programming
!
!
!
Programmable ROM (PROM)
!
!
!
Contain all fuses at the factory
Program the ROM by burning out the undesired fuses
(irreversible process)
Erasable PROM (EPROM)
!
!
Program the ROM in the semiconductor factory
Economic for large quantity of the same ROM
Can be restructured to the initial state under a special ultraviolet light for a given period of time
Electrically erasable PROM (EEPROM or E2PROM)
!
Like the EPROM except being erased with electrical signals
7-25
Programmable Logic Devices
!
ROM provides full decoding of variables
!
!
For known combinational functions, Programmable
Logic Devices (PLD) are often used
!
!
!
!
Waste hardware if the functions are given
Programmable read-only memory (PROM)
Programmable array logic (PAL)
Programmable logic array (PLA)
For sequential functions, we can use
!
!
!
Sequential (simple) programmable logic device (SPLD)
Complex programmable logic device (CPLD)
most popular
Field programmable gate array (FPGA)
7-26
13
Outline
!
!
!
!
!
!
!
Introduction
Random-Access Memory
Memory Decoding
Error Detection and Correction
Read-Only Memory
Combinational Programmable Devices
Sequential Programmable Devices
7-27
Configurations of Three PLDs
7-28
14
Programmable Logic Array
!
PLA does not provide full decoding
of the variables
!
!
Only generate the terms
you need
The decoder is replaced
by an array of AND gates
that can be programmed
AB’
AC
BC
A’BC’
Product Term
1
2
3
4
Inputs
A B C
1 0 1 - 1
- 1 1
0 1 0
F1 = AB’ + AC + A’BC’
F2 = (AC +BC)’
Generate complemented
outputs (if required)
Outputs
(T) (C)
F1 F2
1
1
1
1
1
-
7-29
Implementation with PLA
!
Example 7-2: implement the two
functions with PLA
F1(A, B, C) = ∑ (0, 1, 2, 4)
F2(A, B, C) = ∑ (0, 5, 6, 7)
!
Goal: minimize the number of
distinct product terms between
two functions
7-30
15
Programmable Array Logic
!
PAL has a fixed OR array and
a programmable AND array
!
!
!
!
Easier to program but not as
flexible as PLA
Each input has a bufferinverter gate
One of the outputs is fed back
as two inputs of the AND gates
Unlike PLA, a product term
cannot be shared among gates
!
Each function can be simplified by
itself without common terms
7-31
Implementation with PAL
w=∑(2,12,13)
x=∑(7,8,9,10,11,12,13,14,15)
y=∑(0,2,3,4,5,6,7,8,10,11,15) z=∑(1,2,8,12,13)
Product
Term
1
2
3
4
5
6
7
8
9
10
11
12
A
1
0
1
0
1
0
AND Inputs
B C D W
1 0 0 1 0 1 1 1 1 - 1 1 0 - 0 - 1
- 0 0 0 0 1 -
Outputs
w = ABC’
+ A’B’CD’
x=A
+ BCD
y = A’B
+ CD
+ B’D’
z=w
+ AC’D’
+ A’B’C’D
7-32
16
Outline
!
!
!
!
!
!
!
Introduction
Random-Access Memory
Memory Decoding
Error Detection and Correction
Read-Only Memory
Combinational Programmable Devices
Sequential Programmable Devices
7-33
Sequential PLD
!
!
The most simple sequential PLD = PLA (PAL) + Flip-Flops
The mostly used
configuration for SPLD
is constructed with
8 to 10 macrocells
as shown right
7-34
17
Complex PLD
!
Complex digital systems often require the connection
of several devices to produce the complex specification
!
!
More economical to use a complex PLD (CPLD)
CPLD is a collection of individual PLDs on a single IC
with programmable interconnection structure
7-35
Field Programmable Gate Array
!
Gate array: a VLSI circuit with some pre-fabricated
gates repeated thousands of times
!
!
A field programmable gate array (FPGA) is a VLSI
circuit that can be programmed in the user’s location
!
!
!
Designers have to provide the desired interconnection
patterns to the manufacturer (factory)
Easier to use and modify
Getting popular for fast and reusable prototyping
There are various implementations for FPGA
!
More introductions are adopted from “Logic and Computer
Design Fundamentals”, 2nd Edition Updated, by M. Morris
Mano and Charles R. Kime, Prentice-Hall, 2001
7-36
18
FPGA Structure (Altera)
7-37
FPGA Structure (Xilinx)
Fig. 6-29:
Xilinx® XC4000™ FPGA Structure
(Adapted with Permission of Xilinx, Inc.)
7-38
19
Store the Programming Info.
!
SRAM technology is
used
!
!
!
Store control values
!
!
!
M = 1-bit SRAM
Loaded from the
PROM after power on
Control pass transistor
Control multiplexer
Store logic functions
!
Store the value of
each minterm in the
truth table
7-39
Xilinx FPGA Routing
!
Fast direct interconnect
!
!
General purpose
interconnect
!
!
!
Adjacent CLBs
CLB – CLB or CLB – IOB
Through switch matrix
Long lines
!
!
!
!
Across whole chip
High fan-out, low skew
Suitable for global signals
(CLK) and buses
2 tri-states per CLB for
busses
7-40
20
Xilinx Switch Matrix
Six pass transistors to control each switch node
The two lines at point 1 are joined together
At point 2, two distinct signal paths pass through one
switch node
!
!
!
7-41
Configurable Logic Block (CLB)
!
Combinational logic via lookup table
!
!
Any function(s) of available inputs
Output registered and/or combinational
7-42
21
Simplified CLB Structure
7-43
Internal Functions of a CLB
!
!
!
!
Two 4-input tables implement two distinct
functions (F ’ and G ’)
F’ and G’ with another control (H1) feed into
a third lookup table (H ’)
Two arbitrary functions of up to four variables
and selected functions of up to nine variables
can be implemented
Properly setting the two MUXes can assign
any pair of F ’, G ’, and H ’ to the two
combinational outputs (X and Y)
7-44
22
Internal Functions of a CLB
!
!
!
!
!
Two D flip-flops directly drive outputs XQ and YQ
Each of the D inputs can be selected from F ’, G ’,
H ’ and input DIN
Two XORs select each flip-flop individually to be
positive or negative edge triggered
Two SR controls select the signal S/R to be an
asynchronous Set or Reset for the flip-flops
Two multiplexers allow the input EC to optionally
act as a clock ENABLE signal for each flip-flop
7-45
I/O Block (IOB)
!
Periphery of identical I/O blocks
!
!
!
!
Input, output, or bidirectional
Registered, latched, or combinational
Three-state output
Programmable output slew rate
7-46
23
Input/Output Mode of an IOB
!
Input
!
!
!
3-state control places
the output buffer into
high impedance
Direct in and/or
registered in
Output
!
!
3-state driver should be
enabled by TS signal
Direct output or
registered output
7-47
Design with FPGA
!
!
!
Using HDL, schematic editor, SM chart or FSM
diagram to capture the design
Simulate and debug the design
Work out detail logic and feed the logic into
CLBs and IOBs
!
!
!
Completed by a CAD tool
Generate bit pattern for programming the
FPGA and download into the internal
configurable memory cells
Test the operations
7-48
24
FPGA Design Flow
logic + layout synthesis
!
Advantages: Fast and reusable prototyping
!
!
!
Can be reprogrammed and reused
Implementation time is very short
Disadvantages: Expensive and high volume
7-49
Download to a FPGA Demo Board
Source: CIC training manual
7-50
25
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising