NJU3610

NJU3610
NJU3610
1bit Delta-Sigma Stereo ADC
General Description
Package
The NJU3610 is the stereo Analog to Digital Convector (ADC) that covers from 8
to 192 kHz sampling frequency. The NJU3610 provides 1bit Delta-Sigma
technology with high accuracy and low power consumption. The analog inputs are
differential signal and stereo 4-1 selectors are provided. The NJU3610 provides two
power-supply 1.8V / 3.3V(typical) or single power-supply 3.3V(typical) application.
Features
NJU3610FR3
1bit Delta-Sigma stereo ADC
64fs over sampling (MCK=256fs, 384fs)
32fs over sampling (MCK=128fs)
Digital Filter
High-pass filter
Stereo 4-1 selectors
Sampling Rate
: 8 to 192kHz
Dynamic Range
: 100dB(typ@3.3V, 96kHz)
S/N
: 100dB(typ@3.3V, 96kHz)
S/(N+D)
: 90dB(typ@3.3V, 48kHz, -1.0dBFS)
Master Clock
: 128fs(8 to 192kHz), 256fs / 384fs(8 to 96kHz)
Power Supply
: Single power supply 3.0 to 3.6V(3.3Vtyp) Built-in regulator using together
: Two power supply 3.0 to 3.6V(Analog, I/O:3.3Vtyp)
1.65 to 2.0V(Digital:1.8Vtyp)
Digital Audio Format
: 24/16bit Left-justified, I2S Master/Slave
Operating Temperature
: -40 to +85°C
Package
: LQFP48-R3 (Pb-Free)
Ver.2009.12.4
-1-
NJU3610
Function Block Diagram
AINLP1
AINLN1
AINLP2
AINLN2
AINLP3
AINLN3
AINLP4
AINLN4
5th Order
Delta-Sigma
Modulator
Lch
4-1
Selector
1bit
PDM
Feedback
1bit DAC Lch
Serial
Audio
Interface
with
Feedback
1bit DAC Rch
High-Pass
Filter
4-1
Selector
5th Order
Delta-Sigma
Modulator
Rch
Rch
Reference
Reference
each Analog
Blocks
SDO
FMT0
FMT1
24bit
PCM
1bit
PDM
Clock(64 or 32Fs)
/ Control Signal
Clock and Timing Control
Power
Power Control
Power
Voltage
Regulator
MCK
MODE0
MODE1
HPF
RESETb
PDNb
AVDD
AVSS
VDD18
VDD33
VSS
VCOM
REFLP
REFLN
REFRP
REFRN
VREGI
VREGO
BCK
LRCK
Decimation
Digital
Filter
Lch
SEL0
SEL1
AINRP1
AINRN1
AINRP2
AINRN2
AINRP3
AINRN3
AINRP4
AINRN4
24bit
PCM
AVDD/AVSS : Analog Power Supply (typ:3.3V)
VDD18 : Digital Logic (typ:1.8V)
VDD33 : Digital I/O (typ:3.3V)
VSS : Digital GND and Regulator GND
Fig. 1 NJU3610 Block Diagram
-2-
Ver. 2009.12.4
NJU3610
AINRP3
AINRN3
AINRP2
AINRN2
AINRP1
AINRN1
AIVSS
AVDD
MODE1
MODE0
RESETb
PDNb
36
35
34
33
32
31
30
29
28
27
26
25
Pin Configuration
AINRN4
37
24
SEL1
AINRP4
38
23
SEL0
REFRP
39
22
FMT1
REFRN
40
21
FMT0
VCOM
41
20
MCK
AVDD
42
19
VDD33
AVSS
43
18
VDD18
TEST
44
17
VSS
REFLN
45
16
HPF
REFLP
46
15
BCK
AINLP4
47
14
LRCK
AINLN4
48
13
SDO
3
4
5
6
7
8
9
10
11
12
AINLN2
AINLP1
AINLN1
AVSS
AVDD
VDD33
VSS
VREGI
VREGO
2
AINLN3
AINLP2
1
AINLP3
NJU3610FR3
Fig.2 NJU3610 Pin Configuration
Ver.2009.12.4
-3-
NJU3610
Pin Description
Table.1 Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Symbol
AINLP3
AINLN3
AINLP2
AINLN2
AINLP1
AINLN1
AVSS
AVDD
VDD33
VSS
VREGI
VREGO
SDO
LRCK
BCK
HPF
VSS
VDD18
VDD33
MCK
FMT0
FMT1
SEL0
SEL1
PDNb
RESETb
MODE0
MODE1
AVDD
AVSS
AINRN1
AINRP1
AINRN2
AINRP2
AINRN3
AINRP3
AINRN4
AINRP4
REFRP
REFRN
VCOM
I/O
AI
AI
AI
AI
AI
AI
AG
AP
DP
DG
RI
RO
DO
DIO
DIO
DI
DG
DL
DP
DI
DI
DI
DI
DI
DI
DI
DI
DI
AP
AG
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AO
AVDD
AVSS
TEST
REFLN
REFLP
AINLP4
AINLN4
AP
AG
AI
AI
AI
AI
AI
* AP : Analog power supply, 3.3V
AO : Analog output
DL : Digital power supply, 1.8V
RI : built-in regulator input
DI : Digital input
DIO : Bi-directional of Digital
-4-
Description
Lch Analog Positive Input 3 Pin
Lch Analog Negative Input 3 Pin
Lch Analog Positive Input 2 Pin
Lch Analog Negative Input 2 Pin
Lch Analog Positive Input 1 Pin
Lch Analog Negative Input 1 Pin
Analog Ground Pin
Analog Power Supply Pin, 3.3V
Digital Power Supply Pin, 3.3V
Digital Ground Pin
Built-in Regulator Input Pin, 3.3V
Built-in Regulator Output Pin, 1.8V (typ)
Audio Serial Data Output Pin
LR Clock
Bit Clock
HPF for Off-set Cancel (“H”: ON, “L”: OFF)
Digital Ground Pin
Digital Power Supply Pin, 1.8V
Digital Power Supply Pin, 3.3V
Master Clock Input Pin
Control Serial Data Format 0 Pin
Control Serial Data Format 1 Pin
Control Input Selector 0 Pin
Control Input Selector 1 Pin
Power Down Mode Pin (”H”: Power up, “L”: Power down)
Reset Pin (“H”: Reset OFF, “L”: Reset ON)
Control Mode 0 Pin
Control Mode 1 Pin
Analog Power Supply Pin, 3.3V
Analog Ground Pin
Rch Analog Negative Input 1 Pin
Rch Analog Positive Input 1 Pin
Rch Analog Negative Input 2 Pin
Rch Analog Positive Input 2 Pin
Rch Analog Negative Input 3 Pin
Rch Analog Positive Input 3 Pin
Rch Analog Negative Input 4 Pin
Rch Analog Positive Input 4 Pin
Rch Voltage Reference Input Pin, AVDD
Rch Voltage Reference Input Pin, GND
Common Voltage Output Pin, AVDD/2
Connected to AVSS with a 10uF electrolytic capacitor.
Analog Power Supply Pin, 3.3V
Analog Ground Pin
Test Pin (Connected to AVSS)
Lch Voltage Reference Input Pin, GND
Lch Voltage Reference Input Pin, AVDD
Lch Analog Positive Input 4 Pin
Lch Analog Negative Input 4 Pin
AG : Analog ground AI : Analog input
DP : Digital power supply, 3.3V
DG : Digital ground and built-in regulator ground
RO : built-in regulator output
DO : Digital output
Ver. 2009.12.4
NJU3610
Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings
Parameter
Analog
Digital
Power supplies
Built-in Regulator
Input
Built-in Regulator
Output
Pin Voltage
(VSS=AVSS=0V=GND, Ta=25°C)
Symbol
AVDD
VDD33
VDD18
VREGI
VREGO
Rating
-0.3 to +4.2
-0.3 to +2.3
-0.3 to +4.2
-0.3 to +2.3
Digital Input
Vx(IN)
-0.3 to +5.5 (VDD33≥3.0V)
-0.3 to +4.2 (VDD33<3.0V)
Digital Output
Vx(OUT)
-0.3 to VDD33 + 0.3
Analog Input
Vx(AIN)
VCOM Output
Vx(VCOM)
Power Dissipation
Units
V
-0.3 to AVDD + 0.3
800
PD
mW
Mounted on two-layer board of based on the JEDEC.
Operating Temperature
TOPR
-40 to +85
°C
Storage Temperature
TSTR
-40 to +125
°C
* AVDD
* VDD33
* VDD18
* VREGI
* VREGO
* VX(IN)
* VX(OUT)
* VX(AIN)
* VX(VCOM)
Note 1)
Note 2)
: 8, 29, 42pin
: 9pin
: 18pin
: 11pin
: 12pin
: 16, 20-28pin, and 14-15pin (set in the state of the input.)
: 13pin, and 14-15pin (set in the state of the output.)
: 1-6, 31-40, 44-48pin
: 41pin
If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using
LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the
electrical characteristics conditions will cause malfunction and poor reliability.
Please do not open the digital input terminal. Moreover, please do not open the digital I/O terminal set
in the state of the input.
Recommended operating conditions
Table 3. Recommended operating conditions
Parameter
Power
Supplies
Symbol
Analog
AVDD *1
VDD33 *1
Digital
VDD18 *2
Built-in Regulator Input
VREGI *3
Recommended operating
conditions
3.0 to 3.6
AVDD33≥VDD33
1.65 to 2.0
(Or, a built-in regulator supplies
the voltage.)
3.0 to VDD33
Units
V
*1 VDD33 is recommended to be turned on from AVDD and simultaneous or AVDD back.
*2 The power up sequence VDD18 is not critical.
*3 When a built-in regulator is used, VREGI is connected with VDD33. When a built-in regulator is not used,
VREGI and VREGO are connected with VSS.
Ver.2009.12.4
-5-
NJU3610
Electric Characteristics
Table 4. Analog Characteristics
Parameter
Condition
Min.
AIN*** Pin
Full-scale voltage level
*1
AVDD x 1.4
(Between differential motions)
fs=48kHz
fs=96kHz
fs=192kHz
fs=48kHz
fs=96kHz
fs=192kHz
fs=48kHz
fs=96kHz
fs=192kHz
85
93
93
-
90
90
90
99
100
100
99
100
100
-
fs=48kHz, 1kHz BPF
-
110
-
dB
fs=48kHz, 1kHz BPF
97
110
-
dB
fs=48kHz
fs=96kHz
fs=192kHz
fs=48kHz
fs=96kHz
fs=192kHz
fs=48kHz
40
40
40
-0.1
100
50
50
58
58
58
-
0.1
S/(N+D)
(-1.0dBFS)
Dynamic Range
(-60dBFS, A-weighted)
S/N
(A-weighted)
Channel Separation
(Between L and R)
Units
Vpp
AIN*** Pin
(During the selection and non-selection)
Max.
AVDD x 0.7
(Differential one side)
Cross Talk
Typ.
Equivalent input impedance
(Selection input terminal)
Input impedance *2
(Non-Selection input terminal)
Gain Mismatch
dB
dB
dB
kOhm
KOhm
dB
(Ta=25°C, AVDD=VDD33=3.3V, VDD18=VREGO, HPF=ON, Input signal=1kHz(AINL*4/AINR*4), BCK=64fs,
MCK=256fs(48/96kHz), 128fs(192kHz), Measurement frequency=20Hz-20kHz at fs=48kHz, 20Hz-40kHz at
fs=96kHz, 20Hz-40kHz at fs=192kHz)
*1 The full-scale voltage level indicates full-scale value (0dBFS) of the analog input voltage. A full-scale voltage is
proportional to the AVDD voltage. The meaning between differential motions is an operation result of the
differential input signal. The input voltage of the terminal is up to AVDD voltage.
*2 The analog input terminal of non-selection does the bias to VCOM by the resistance of this value.
(Ta=25°C, AVDD=VDD33=3.3V, VDD18=1.8V)
Table 5. Power Supply Current
Parameter
3.3V, Power Supply Current: IDD + IDDA
(Not contain a built-in regulator)
1.8V, Power Supply Current: IDDL
(Not contain a built-in regulator)
Power down mode: IDDQ+IDDLQ
(Not contain a built-in regulator)
Built-in regulator Current: IRIN
-6-
Condition
Min.
Typ.
Max.
units
fs=48kHz
fs=96kHz
fs=192kHz
fs=48kHz
fs=96kHz
fs=192kHz
-
7.0
8.0
8.0
2.0
4.0
8.0
12
10
Clock stop
PDNb=Low
-
-
100
µA
VREGI=3.3V
IOUT=0mA
-
50
70
µA
mA
mA
Ver. 2009.12.4
NJU3610
Table 6. Digital DC Characteristics
Parameter
Symbol
(Ta=25°C, VDD33=3.3V, VDD18=1.8V)
Condition
Min.
Typ.
Max.
Units
*1
High-Level Input Voltage
VIH
2.2
-
VDD33
Low-Level Input Voltage
VIL
0
-
0.8
V
High-Level Output Voltage
VOH
IOH=-1mA
VDD33 x 0.8
-
VDD33
V
Low-Level Output Voltage
VOL
IOL=1mA
0
-
VDD33 x 0.2
V
Input Leakage Current
IIN
VIN=VSS, VDD
-10
-
10
µA
V
*1 The digital input terminal and the input digital I/O terminal are 5V tolerant only at VDD33 ratings.
Table 7. Reset AC Characteristics
Parameter
Reset Time
(Ta=25°C, VDD33=3.3V, VDD18=1.8V)
Symbol
Condition
Min.
Typ.
Max.
Units
tRESETb
RESETb
100
-
-
ns
Table 8. Digital Filter Characteristics
Parameter
(Ta=25°C, VDD33=3.3V, VDD18L=1.8V)
Condition
Min.
Typ.
Max.
Units
-3.0dB
-
fs/44100
-
Hz
LPF Pass band
0
-
0.454
fs
LPF Pass band ripple
-
-
±0.005
dB
0.546
-
-
fs
-80
-
-
dB
-
27
-
1/fs
Cut-off frequency
(HPF=High)
LPF Stop band
LPF Stop band attenuation
Group Delay
Ver.2009.12.4
-7-
NJU3610
Table 9. Clock Timing
Parameter
Symbol
(Ta=25°C, VDD33=3.3V, VDD18=1.8V)
Min.
Typ.
Max.
1.024
24.576
MCK Frequency *1
fMCK
2.048
24.576
3.072
36.864
BCK Frequency *2
fSCK
0.256
12.288
LRCK Frequency *2
fLRCK
8.0
192
MCK Pulse Width Low
tMIL
0.475/fMCK
0.5/fMCK
0.525/fMCK
MCK Pulse Width High
tMIH
0.475/fMCK
0.5/fMCK
0.525/fMCK
BCK Pulse Width Low
tSIL
Slave
35
0.5/fMCK
BCK Pulse Width High
tSIH
Slave
35
0.5/fMCK
BCK to LRCK *3
tSLI
Slave
20
LRCK to BCK *3
tLSI
Slave
20
*1 For fs=8 to 192kHz at 128fs mode. For fs=8 to 96kHz at 256fs/384fs mode.
*2 MCK should synchronized with BCK and LRCK. (Not necessary to phase it.)
*3 BCKI rising edge must not occur at the same time as LRCK edge
Condition
128fs
256fs
384fs
Slave
Slave
tMIH
Units
MHz
MHz
kHz
ns
ns
ns
ns
tMIL
MCK
Fig.3 MCK Timing diagram
LRCK
tSIH
tSIL
tSLI
tLSI
BCK
Fig.4 BCK, LRCK Timing Diagram
Table 10. Serial Audio Output Timing
Parameter
symbol
Condition
*1
BCK to LRCK Time
tSLO
CL=25pF
Data Output Delay
tDOD
CL=25pF
*1 It is regulation in Master mode.
(Ta=25°C VDD33=3.3V, VDD18=1.8V)
Min.
Typ.
Max.
-20
20
20
Units
ns
ns
LRCK
tSL
BCK
tDOD
SDO
Fig.5 Serial Audio Output Timing Diagram
-8-
Ver. 2009.12.4
NJU3610
1.
Power-supply, RESET , Power Down
1.1 Power-supply
The power-supply should be used under the recommended condition. The power-on level procedure should
increase monotonously. During the operation, the power-supply should not become out of the recommended
condition.
The large size decoupling capacitor should be implemented near the NJU3610. The analog/digital power line
should be taken from this large capacitor. Also the power-supply terminals should have enough decoupling
capacitors to the terminals.
The REFLP, REFLN, REFRP, REFRN are the reference voltage terminals of the 1bit-feedback-DAC. The REFLP
and REFRP should be connected to AVDD power line. The REFLPN and REFRN should be connected to AVSS line.
These terminals affect the analog performance, so the decoupling capacitor is very important.
The VCOM output is the half of the AVDD voltage level with the voltage-follower buffer. The VCOM voltage
level is the internal reference. The non-selected input terminals are pull-upped to the internal reference via 58k-ohm
resistors. The 10uF capacitor is recommended to improve noise and channel separation performance. This terminal
output is available for the analog reference level of the input circuit.
The NJU3610 provides the internal voltage regulator for internal digital circuit. The VREGI terminal is the input
to the internal regulator. The input to VREGI should be the same voltage as VDD33 input. The output of the
internal voltage regulator is VREGO. If the VREGO output is connected to VDD18, no other 1.8V power-supply is
necessary.
If the internal voltage regulator is used, put the capacitor (around 4.7 to 10uF) between VREGO and VSS.
If the internal voltage regulator is not used, connect both VREGI and VREGO to VSS.
The internal voltage regulator is provided for the NJU3610 circuit, do not use it for the other circuit.
If the VDD33 and AVDD are different power-supply, follow the next power-on procedure.
First power on analog power-supply (AVDD). Next power on digital power-supply (VDD33).
Also it is possible to power on analog and digital power-supply simultaneously.
Power-on Timing Condition: AVDD (before) ≥ VDD33 (same or after)
There is no constraining on VDD18 power-on procedure. Also there is no constraining on power-down procedure
for all power-supplies.
Ver.2009.12.4
-9-
NJU3610
1.2 Digital Input Terminal
All digital input terminals are 5V tolerant under the recommended VDD33 power-on condition. Also BCK and
LRCK that are assigned as input mode are 5V tolerant under the recommended VDD33 power-on condition.
Input/output setting of BCK and LRCK are defined by FMT1 terminal. These terminals are input mode in case of
FMT1 = “Low” and output mode in case of FMT1 = “High”.
During RESETb terminal = ”Low”, BCK and LRCK are input mode regardless of FMT1 condition.
1.3 RESET and Power Down
During RESETb terminal = ”Low”, digital filter and analog integrator are initialized and SDO output is low level.
The internal reference voltage generator is operating during RESETb terminal = ”Low”.
If the terminal setting or clock is changed under ADC operation, RESETb should be initialized again.
In case of PDNb = ”Low”, all analog circuit become power-down mode. The digital filter is operating under PDNb
= ”Low”, but the clock to analog circuit is stopped. If power-down mode is not used, PDNb should be “high”.
After power-on, the next reset procedure should be done at least one time to initialize the NJU3610. RESETb
should be “Low” level and become “High” level again. Changing PDNb from “Low “level to “High” level makes
VCOM reference level generated. The setup time of VCOM-reference-level depends on the attached capacitor.
The procedure to change RESETb level (“Low” to “High”) should be done, after VCOM level becomes stable.
The procedure of SDO audio data output is as following: First RESET is released from “Low” to “High” level.
After RESET release, wait 136±8fs period and SDO generates audio data. But to get the accurate output data, VCOM
reference level should become half of AVDD level.
If the High Pass Filter is used to cancel offset (HPF=”High”), some more time (max. 8192fs) after generating audio
data is necessary to get accurate output data.
In order to power down the NJU3610 completely, PDNb should be “Low” and, also clocks to MCK, BCK and
LRCK should be stopped.
Notice:
The internal regulator does not provide power-down mode. As far as power is supplied to VREG1, it generates
output voltage with consuming power.
- 10 -
Ver. 2009.12.4
NJU3610
2. ADC Function
2.1 Clock and Digital Audio Interface
The NJU3610 requires MCK, BCK and LRCK audio clock. BCK and LRCK can be generated by MCK in Master
mode. MCK, BCK and LRCK are synchronized in Master mode.
In Slave mode, BCK and LRCK are inputted from the outside. In Slave mode, MCK, BCK and LRCK should be
synchronized. But it is not necessary that the phase of these three clocks are synchronized.
MCK frequency should be one of 128fs, 256fs or 384fs. If fs>96KHz, MCK should be 128fs. The ADC operates
with the next frequency. The operate frequency is 64fs in case of fs≦96KHz. The operate frequency is 32fs in case
of fs>96KHz.
Mode0 and mode1 terminals select the MCK frequency and ADC operating frequency.
In case that ADC operating frequency is 32fs, the effective bandwidth is 1/4fs. Between 1/4fs and 1/2fs, ADC
shaping noise exists.
The NJU3610 digital audio format provides Left-justified and I2S 24bit(BCK=64clocks/fs) in Master mode. The
NJU3610 digital audio format provides Left-justified, I2S 16bit (BCK=32clocks/fs) and I2S 24bit(BCK=64clocks/fs)
in Slave mode.
FMT0 and FMT1 terminals select the above digital audio format. When FMT0, FMT1, MODE0 and MODE1 are
changed, RESET should be done again.
MCK, BCK and LRCK frequency is shown in table11. Digital Audio Format and operation mode is shown in table12.
In Master mode, BCK and LRCK terminals generate clocks. BCK output clock is fixed at 64fs in Master mode. In
Slave mode, BCK and LRCK terminals are assigned input.
Table 11.
LRCK(kHz)
MCK, BCK, LRCK (1)
MCK (MHz)
Master: Generation from MCK
Slave: From outside
128fs
256fs
BCK(MHz)
384fs
32fs
Slave only: from outside
64fs
Master: Generation from MCK
Slave: From outside
8
-*2
2.048
3.072
0.256
0.512
16
-*2
4.096
6.144
0.512
1.024
22.05
-*2
5.6448
8.4672
0.7056
1.4112
32
-*2
8.192
12.288
1.024
2.048
44.1
-*2
11.2896
16.9344
1.4112
2.8224
48
-*2
12.288
18.432
1.536
3.072
64
-*2
16.384
24.576
2.048
4.096
88.2
-*2
22.5792
33.8688
2.8224
5.6448
96
-*2
24.576
36.864
3.072
6.144
*1
176.4
22.5792
5.6448
11.2896
192 *1
24.576
6.144
12.288
*1 It is only a setting of “CKMODE[1:0]=10,11”. At this time, frequency bandwidth is up to 1/4fs.
The shaping noise of the ADC is included in the band from 1/4fs to 1/2fs.
*2 Because an effective bandwidth is limited, it is not practicable.
Ver.2009.12.4
- 11 -
NJU3610
CMKODE
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
Table 12. MCK,BCK,LRCK (2)
Master /
A/D
MCK
Slave
mode
(fs)
FMT
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Slave
64fs
256fs
(≦96kHz)
64fs
384fs
(≦96kHz)
32fs
256fs
(>96kHz)
32fs
128fs
(>96kHz)
Master
Slave
Master
Slave
Master
Slave
Master
Left Channel
LRCK
Format
I2S (32 or 64fs)
Left-justified(32 or 64fs)
I2S (64fs)
Left-justified(64fs)
I2S (32 or 64fs)
Left-justified(32 or 64fs)
I2S (64fs)
Left-justified(64fs)
I2S (32 or 64fs)
Left-justified(32 or 64fs)
I2S (64fs)
Left-justified(64fs)
I2S (32 or 64fs)
Left-justified(32 or 64fs)
I2S (64fs)
Left-justified(64fs)
Right Channel
BCK
MSB
SDO
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
23
32 Clocks
Fig.6 Left-justified Data Format 64fs, 24bit Data
Left Channel
LRCK
Right Channel
BCK
MSB
SDO
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
32 Clocks
Fig.7 I2S Data Format 64fs, 24bit Data
Left Channel
LRCK
Right Channel
BCK
MSB
SDO
LSB MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16 Clocks
16 Clocks
Fig.8 Left-justified Data Format 32fs, 16bit Data
Left Channel
LRCK
Right Channel
BCK
MSB
SDO
LSB MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16 Clocks
16 Clocks
2
Fig.9 I S Data Format 32fs, 16bit Data
- 12 -
Ver. 2009.12.4
NJU3610
2.2 High Pass Filter for offset-cancel
The NJU3610 provides High Pass Filter (digital filter) to cancel offset. Normally HPF terminal is set “High”. In
case of HFP=”High”, High Pass Filter is active. The frequency characteristics are shown in table 8. The cutoff
frequency is set at low frequency. But sampling rate changes the cutoff frequency. HFP terminal setting can be
changed during NJU3610 operating. But changing HPF setup makes pop noise that is caused by offset change.
2.3 Analog Input and 4-1 Selector
The NJU3610 provides four differential-stereo-inputs. SEL0 and SEL1 terminals select one of four stereo-input.
After this selector, input signal goes to ADC input. SEL0 and SEL1 combination is shown in table13.
SEL1
SEL0
0
0
1
1
0
1
0
1
Table 13. SEL1, SEL0 combination
Lch
Rch
Non-reversing
Reversing
Non-reversing
Reversing
input
input
input
input
AINLP1
AINLN1
AINRP1
AINRN1
AINLP2
AINLN2
AINRP2
AINRN2
AINLP3
AINLN3
AINRP3
AINRN3
AINLP4
AINLN4
AINRP4
AINRN4
Each differential-signal input should be biased with VCOM reference level. The half of AVDD level is available
instead of VCOM reference level. Input full-scale level (0dBFS) is “AVDDx0.7Vpp”. In differential signal, Input
full-scale level is “AVDDx1.4Vpp”. Maximum available input range is from GND to AVDD with distortion. But in
this case, the distortion occurs. When AMP with high voltage power-supply is used before the ADC, the input level
should not exceed the ADC input range.
SEL0 and SEL1 settings are taken in at MCK rising edge. In case of RESETb=”Low”, AINLP1, AINLN1,
AINRP1 and AINRN1 are selected regardless of SEL0/SEL1 settings. In case that PDNb level is changed from
“high” to “Low”, the latest condition is maintained.
The terminals that are not selected by SEL0/SEL1 are pull-upped by VCOM bias via 58ohm resisters. The analog
input terminals that are not used should be left open or adds the capacitors between terminals and GND. If these
terminals connect directly to power-supply or GND, VCOM fluctuates and the NJU3610 does not operate properly.
The NJU3610 operates with 32fs over sampling at Mode1=”High”. The NJU3610 operates with 64fs over
sampling at Mode1=”Low”. If noise exists around over sampling frequency, the noise folds back. To avoid this
folding back noise, passive RC filter is required.
The example of input buffer circuit is shown in figure10. VCOM output is used for bias level. The J1 selects RCA
or XLR input. The RC-passive-filter is consist of Ra/Rb(220ohm), Ca/Cb(100pF) and Cc(200pF). The cutoff
frequency of RC-passive-filter is 1447KHz.
This input buffer circuit should be implemented to analog input terminals as far as short distance. The layout
pattern should be symmetric.
C1
R2
47μ
VCOM_OUT
BIAS(VDDAx0.5)
R1
RCA
10μ
Ra=220
AIN*N*
BIAS
Ca=100p
C1
Cc=200p
NJU3610
XLR
R2
Cb=100p
R1
47μ
1
2
Rb=220
AIN*P*
3
J1
BIAS
Fig.10 Input buffer example
Ver.2009.12.4
- 13 -
NJU3610
Package dimension
LQFP48-R3 (Pb-Free)
9±0.1
7±0.1
0∼10°
25
24
48
13
7±0.1
37
1
9±0.1
36
0.6±0.1
12
0.22±0.1
1.5±0.1
1.4±0.05
0.5
0.076
0.1±0.05
0.17TYP
モールド底面
Mold
Plating: Sn-Bi
[CAUTION]
The specifications on this data book are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this data book are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 14 -
Ver. 2009.12.4
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