MP7748S - Monolithic Power System

MP7748S - Monolithic Power System
MP7748S
2 x 30W Stereo Single Ended
Or 60W Mono BTL Class D Audio Amplifier
DESCRIPTION
FEATURES
The MP7748S is a Class D Audio Amplifier for
driving stereo speakers in single-ended
configuration or a mono speaker in bridge-tiedload configuration. It is fully integrated audio
amplifier which dramatically reduces solution
size by integrating the following:

200mΩ power MOSFETs

Startup / Shutdown pop elimination

Short circuit protection circuits



The MP7748S is capable of delivering 30W per
channel into 4Ω speaker in single-ended output
structure, or delivering 60W into 8Ω speaker in
bridge-tied-load output structure. MPS Class D
Audio Amplifiers exhibit the high fidelity of a
Class A/B amplifier at high efficiencies. The
circuit is based on the MPS’ proprietary variable
frequency topology that delivers excellent
linearity, fast response time and operates on a
single power supply.
MP7748S
features
programmable
VDD
shutdown voltage for each channel by
controlling the UVP node voltage. The default
VDD shutdown (rising threshold) voltage is 8.4V
if the UVP pin is NC.
The MP7748S is available in TSSOP28Exposed Package.









9.5V to 36V Operation from a Single Supply
±5.5A Peak Current Output
Output Power at 30V and 10%THD:
- Stereo Single Ended: 2 x 30W into 4Ω Load,
- Bridge Tied Load: 60W into 8Ω Load
THD+N = 0.02% at 1W, 8Ω
> 90% Efficiency at 10%THD
Low Noise (160μV with SE configuration,
145μV with BTL configuration)
Switching Frequency Up to 1MHz
Integrated Startup and Shutdown Pop
Elimination Circuit
Programmable UVP
Thermal and Short Circuit Protection
Integrated Power FETs
Available in TSSOP28-Exposed Package
APPLICATIONS






Portable Docking Stations
Surround Sound DVD Systems
Televisions
Flat Panel Monitors
Multimedia Computers
Home Stereo Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
MP7748S Rev. 1.0
www.MonolithicPower.com
10/14/2013
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© 2013 MPS. All Rights Reserved.
1
MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
TYPICAL APPLICATION
CH1
INPUT
CH1
OUTPUT
IN1
SW1
REF1
BST1
TIMER1
PGND1
TIMER2
PGND2
OFF ON
EN1
EN2
MP7748S
UVP1
VDD1
UVP2
VDD2
VDD
AGND1
AGND2
BST2
CH2
OUTPUT
REF2
SW2
CH2
INPUT
IN2
Stereo SE Application Circuit
TIMER1
SW1
TIMER2
BST1
INPUT+
IN1
PGND1
REF1
REF2
INPUT-
OUTPUT
PGND2
IN2
MP7748S
EN1
OFF ON
VDD
V DD1
EN2
V DD2
UVP1
UVP2
BST2
AGND1
SW2
AGND2
Mono BTL Application Circuit
MP7748S Rev. 1.0
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10/14/2013
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© 2013 MPS. All Rights Reserved.
2
MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
ORDERING INFORMATION
Part Number*
MP7748SGF
Package
TSSOP28-EP
Top Marking
MP7748S
* For Tape & Reel, add suffix –Z (e.g. MP7748SGF–Z).
PACKAGE REFERENCE
N/C
PGND1
REF1
PGND1
IN1
SW1
TIMER1
SW1
AGND1
BST1
EN1
VDD1
UVP1
IN2
EXPOSED PAD
ON BACKSIDE
REF2
VDD1
PGND2
PGND2
TIMER2
SW2
AGND2
SW2
EN2
BST2
UVP2
VDD2
N/C
VDD2
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VDD ......................................40V
BS Voltage.................. VSW – 0.3V to VSW + 6.5V
VUVP, VTIMER, VEN............................. -0.3V to +6V
VSW ......................................... -0.3V to VDD + 1V
VREF, VIN ....................................... -0.3V to +34V
AGND to PGND .......................... -0.3V to +0.3V
(2)
Continuous Power Dissipation (TA = +25°C)
………………………………………………..3.9W
Junction Temperature .............................. 150°C
Lead Temperature ................................... 260°C
Storage Temperature ............... -65°C to +150°C
Recommended Operating Conditions
(3)
Thermal Resistance
(4)
θJA
θJC
TSSOP28-EP ......................... 32 ....... 6 .... C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Supply Voltage VDD ......................... 9.5V to 36V
Operating Junct. Temp (TJ) ...... -40°C to +125°C
MP7748S Rev. 1.0
www.MonolithicPower.com
10/14/2013
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© 2013 MPS. All Rights Reserved.
3
MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
ELECTRICAL CHARACTERISTICS (5, 6)
VDD = 24V, VEN = 5V, TA = +25C, unless otherwise noted.
Parameters
Standby Current
Quiescent Current
SW On Resistance
Short Circuit Current
Symbol Condition
IQ
EN Enable Threshold Voltage
EN Enable Input Current
External Undervoltage
Detection
External Undervoltage
Detection Hysteresis Voltage
Thermal Shutdown Trip Point
VEN = 0V,NIN=PIN=Float
SW=Low
Sourcing and Sinking
Sourcing and Sinking
VEN Rising
VEN Falling
Min
4.5
0.4
VEN = 5V
VUVP
Typ
Max
Units
100
3.1
0.2
5.5
1.4
1.0
130
3.5
µA
mA
Ω
A
V
V
6.5
2.0
5
2
VHys
TJ Rising
Thermal Shutdown Hysteresis
2.2
µA
2.4
V
0.3
V
150
C
30
C
Note:
5) The device is not guaranteed to function outside its operating rating.
6) Electrical Characteristics are for the IC only with no external components except bypass capacitors.
MP7748S Rev. 1.0
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10/14/2013
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© 2013 MPS. All Rights Reserved.
4
MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
OPERATING SPECIFICATIONS (7)
Circuit of figure 5, single-ended output configuration, VDD = 30V, Gain=8.25V/V, VEN = 5V, TA =
+25C, unless otherwise noted.
Parameters
Standby Current
Quiescent Current
Power Output
THD+ Noise
Efficiency
Symbol Condition
Min
Power Supply Rejection
Max
Units
VEN = 0V
Switching, no load
f = 1kHz, THD+N = 10%, 4Ω Load
100
22
30
μA
mA
W
f = 1kHz, THD+N = 10%, 8Ω Load
POUT = 1W, f = 1kHz, 4Ω Load
POUT = 1W, f = 1kHz, 8Ω Load
f = 1kHz, POUT = 30W, 4Ω Load
f = 1kHz, POUT = 17W, 8Ω Load
17
0.04
0.02
90
94
20
W
%
%
%
%
kHz
96
160
dB
μV
f = 1kHz
-59
dB
f = 217Hz
-59
dB
Maximum Power Bandwidth
Dynamic Range
Noise Floor
Typ
A-Weighted
VCC=24V,
Gain=8.25V/V,
VRIPPLE=200mVPP
CR=100μF
Circuit of figure 6, bridge-tied-load output configuration, VDD = 30V, Gain=15V/V, VEN = 5V, TA =
+25C, unless otherwise noted.
Parameters
Symbol Condition
Min
Typ
Max
Units
Standby Current
Quiescent Current
VEN = 0V
Switching, no load
100
26
μA
mA
Power Output
f = 1kHz, THD+N = 10%, 8Ω Load
60
W
THD+ Noise
POUT = 1W, f = 1kHz, 8Ω Load
0.02
%
Efficiency
f = 1kHz, POUT = 60W, 8Ω Load
94
%
Maximum Power Bandwidth
20
kHz
Dynamic Range
Noise Floor
103
145
dB
μV
f = 1kHz
-60
dB
f = 217Hz
-60
dB
Power Supply Rejection
A-Weighted
VCC=24V,
Gain=15V/V,
VRIPPLE=200mVPP
Note:
7) Operating Specifications are for the IC in Typical Application circuit.
MP7748S Rev. 1.0
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10/14/2013
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5
MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
PIN FUNCTIONS
Pin #
Name
Description
1, 14
N/C
2
REF1
3
IN1
4
TIMER1
5
AGND1
6
7
8
EN1
UVP1
IN2
9
REF2
10
TIMER2
11
AGND2
12
13
EN2
UVP2
15, 16
VDD2
17
BST2
18, 19
SW2
20, 21
PGND2
22, 23
VDD1
24
BST1
25, 26
SW1
27, 28
PGND1
Power ground for Amplifier 1. Connect PGND1 to PGND2. Connect PGND to AGND at a
single point.
Exposed
Pad
Connect exposed pad to GND plane for proper thermal performance.
Not connected internally
Internal analog reference (VDD/2) for Amplifier 1. For SE configuration, connect a bypass
capacitor from REF1 to AGND (10μF).
Inverting input for amplifier 1.
Internal timer input for Amplifier 1. Connect a capacitor from TIMER1 to AGND (2.2μF) to
set the internal timer for startup pop elimination.
Analog ground for Amplifier 1. Connect AGND1 to AGND2. Connect PGND to AGND at a
single point.
Enable input for Amplifier 1. Drive EN1 high to turn on the Amplifier 1, low to turn it off.
Under-voltage protection reference input for Amplifier 1. Connect UVP1 to UVP2.
Inverting input for amplifier 2.
Internal analog reference (VDD/2) for Amplifier 2. For SE configuration, connect a bypass
capacitor from REF2 to AGND (10μF).
Internal timer input for Amplifier 2. Connect a capacitor from TIMER2 to AGND (2.2uF) to
set the internal timer for startup pop elimination.
Analog ground for Amplifier 2. Connect AGND2 to AGND1. Connect PGND to AGND at a
single point.
Enable input for Amplifier 2. Drive EN2 high to turn on the Amplifier 2, low to turn it off.
Under-voltage protection reference input for Amplifier 2. Connect UVP2 to UVP1.
Power supply input for Amplifier 2. Bypass VDD2 to PGND2 with a 1μF X7R capacitor (in
addition to the main bulk capacitor), placed close to the VDD2 and PGND2 pins.
High-side MOSFET bootstrap input for Amplifier 2. A capacitor from BST2 to SW2 supplies
the gate drive current to the internal high-side MOSFET.
Switched power output for Amplifier 2.
Power ground for Amplifier 2. Connect PGND2 to PGND1. Connect PGND to AGND at a
single point.
Power supply input for Amplifier 1. Bypass VDD1 to PGND1 with a 1μF X7R capacitor (in
addition to the main bulk capacitor), placed close to the VDD1 and PGND1 pins.
High-side MOSFET bootstrap input for Amplifier 1. A capacitor from BST1 to SW1 supplies
the gate drive current to the internal high-side MOSFET.
Switched power output for Amplifier 1.
MP7748S Rev. 1.0
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10/14/2013
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6
MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
TYPICAL PERFORMANCE CURVES
Circuit of Figure 5, single-ended output configuration, VDD=24V, VEN=5V, AV=8.2V/V, TA = +25C,
unless otherwise noted.
MP7748S Rev. 1.0
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10/14/2013
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7
MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
TYPICAL PERFORMANCE CURVES (continued)
Circuit of Figure 5, single-ended output configuration, VDD=24V, VEN=5V, AV=8.2V/V, TA = +25C,
unless otherwise noted.
MP7748S Rev. 1.0
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10/14/2013
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MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
TYPICAL PERFORMANCE CURVES (continued)
Circuit of Figure 5, single-ended output configuration, VDD=24V, VEN=5V, AV=8.2V/V, TA = +25C,
unless otherwise noted.
MP7748S Rev. 1.0
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10/14/2013
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MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
TYPICAL PERFORMANCE CURVES (continued)
Circuit of Figure 5, single-ended output configuration, VDD=24V, VEN=5V, AV=8.2V/V, TA = +25C,
unless otherwise noted.
MP7748S Rev. 1.0
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10/14/2013
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10
MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
TYPICAL PERFORMANCE CURVES (continued)
Circuit of Figure 6, BTL output configuration, VDD=24V, VEN=5V, AV=15V/V, TA = +25C, unless
otherwise noted.
MP7748S Rev. 1.0
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10/14/2013
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MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
TYPICAL PERFORMANCE CURVES (continued)
Circuit of Figure 6, BTL output configuration, VDD=24V, VEN=5V, AV=15V/V, TA = +25C, unless
otherwise noted.
MP7748S Rev. 1.0
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12
MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
TYPICAL PERFORMANCE CURVES (continued)
Circuit of Figure 6, BTL output configuration, VDD=24V, VEN=5V, AV=15V/V, TA = +25C, unless
otherwise noted.
MP7748S Rev. 1.0
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10/14/2013
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MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
BLOCK DIAGRAM
BST1
VDD
REF1
TM
IN1
AAM
Modulator
TIMER1
UVP1
VDD1
Reference
SW1
Control&
Gate Drive
OTP
OCP
External
Under Voltage
Detector
PGND1
EN1
Shutdown
EN2
AGND1
VDD
REF2
IN2
Reference
AAMTM Modulator
BST2
VDD2
Control&
Gate Drive
SW2
TIMER 2
UVP2
External
Under Voltage
Detector
OTP
OCP
PGND2
AGND2
Figure 1—Function Block Diagram
MP7748S Rev. 1.0
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10/14/2013
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MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
OPERATION
The MP7748S is a Class D Audio Amplifier for
driving stereo speakers in single-ended
configuration or a mono speaker in bridge-tiedload configuration. It uses the Monolithic Power
Systems
patented
Analog
Adaptive
ModulationTM to convert the audio input signal
into pulses. These pulses drive an internal highcurrent output stage and, when filtered through
an external inductor-capacitor filter, reproduce
the input signal across the load. Because of the
switching Class D output stage, power
dissipation in the amplifier is drastically reduced
when compared to Class A, B or A/B amplifiers
while maintaining high fidelity and low
distortion.
REF1 and REF2 are the positive inputs of the
two amplifiers. They are set to half the DC
power supply input voltage (VDD/2) by the
internal circuit. The input capacitor CIN couple
the AC signal at the input.
The amplifier voltage gain is set by the
combination of the input resister RIN and the
feedback resistor RFB and is calculated by the
equation:
AV 
R FB
RIN
Where: for Channel 1, RFB=RFB1, RIN=RIN1;
For Channel 2, RFB=RFB2, RIN=RIN2.
The MP7748S includes four high-power
MOSFETs wherein for each channel the output
driver stage uses two 200mΩ N­channel
MOSFETs to deliver the pulses to the LC output
filter which in turn drives the load. To fully
enhance the high-side MOSFET, the gate is
driven to a voltage higher than the source by
the bootstrap capacitor between SW and BS.
While the output is driven low, the bootstrap
capacitor is charged from VDD through an
internal circuit on the MP7748S. The gate of the
high-side MOSFET is driven high from the
voltage at BS, forcing the MOSFET gate to a
voltage higher than VDD and allowing the
MOSFET to fully turn on, reducing power loss in
the amplifier.
Pop Elimination
The MP7748S integrates a source current
function to charge the AC coupling capacitor
COUT1/2 for the SE output configuration and CIN1/2
at the start up moment. The start up source
current slew rate is adjustable by selecting
different capacitance of timer capacitor
CTIMER1/2. The larger the capacitance of the timer
capacitor is, the smaller the start up current
slew rate is. The recommended 1μF timer
capacitor results in a start up current slew rate
of approximately 20mA/350ms which would
help to minimize the turn on pop.
After driving EN pin low, output SW will be set
to high impedance immediately which would
help to eliminate the turn off pop.
Short Circuit/Overload Protection
The MP7748S has internal overload and short
circuit protection. The currents in both the highside and low-side MOSFETs are measured and
if the current exceeds the 5.5A short circuit
current limit, both MOSFETs are turned off. The
MP7748S then restarts with the same power up
sequence that is used for normal starting to
prevent a pop from occurring after a short
circuit condition is removed.
Over-Temperature Shutdown
Thermal monitoring is also integrated into the
MP7748S. If the die temperature rises above
150°C, all switches turn off. The temperature
must fall below 120°C before normal operation
resumes, with the same power-up sequence
used to prevent popping noise.
Enable Function
The MP7748S EN input is an active high enable
control. To enable the MP7748S, drive EN with
a 2.0V or higher voltage. To disable the
amplifier, drive it below 0.4V. While the
MP7748S is disabled, the VDD operating
current is around 100μA and the output driver
MOSFETs are turned off.
MP7748S Rev. 1.0
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15
MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
Programmable UVP
MP7748S integrate programmable UVP
function, which can be used to shutdown the
MP7748S to escape the pop, by controlling the
UVP node voltage. The VDD shutdown voltage
can be flexibly adjusted by the external resistor,
as shown in the figure 2.
VDD
RH
R H_internal
UVP
+
RL_internal
RL
+2.2V
VVDD _ shutdown  2.2 *
(RH  RL )
RL
If the UVP pin is NC, the default VDD shutdown
voltage (rising threshold) is 8.4V since there is
internal voltage divided circuit.
For example, please see the table 1 for
recommended UVP setting for reduce the
power off pop.
Table 1: Recommended RH and RL for proper
UVP setting.
-
AGND
Fig
ure 2—UVP Block Diagram
If external resistor RH and RL is low enough (e.g.
RH, RL < 50kΩ) compared with internal resistor,
the VDD shutdown voltage (rising threshold)
can be calculated by the equation:
VDD
(V)
12
24
36
VDD_shutdown
(V)
8.6
19
26
MP7748S Rev. 1.0
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© 2013 MPS. All Rights Reserved.
RH
RL
15k
39k
56k
5.1k
5.1k
5.1k
16
MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
APPLICATION INFORMATION
Component Selection
The MP7748S uses a minimum number of
external components to complete a stereo SE or
mono BTL Class D audio amplifier. The circuit in
Figure 5 (stereo SE application circuit) and
Figure 6 (mono BLT application circuit) are
optimized for a 30V power supply. This circuit
should be suitable for most applications. Use the
following sections to design custom circuits.
Setting the Voltage Gain
The maximum output-voltage swing is
the power supply. To achieve the
output power, set the gain such
maximum input signal results in the
output voltage swing.
Table 2: Switching Frequency Setting For SE
Output Configuration
VDD Gain RFB RIN
(V) (V/V) (kΩ) (kΩ)
limited by
maximum
that the
maximum
Left
Right
channel
channel
CINT1 FSW1 CINT2 FSW2
(nF) (kHz) (nF) (kHz)
12
10
100
10
1.8
694
1.5
774
12
20
100
4.99
1.8
694
1.5
782
24
10
150
15
2.7
653
2.2
720
24
20
150
7.5
2.7
654
2.2
723
24
30
150
4.99
2.7
657
2.2
723
30
10
150
15
3.3
653
2.7
743
30
20
150
7.5
3.3
654
2.7
745
30
30
150
4.99
3.3
659
2.7
747
VOUT(PK )
36
10
150
15
5.6
588
3..9
665
VIN(PK )
36
20
150
7.5
5.6
590
3.9
667
36
30
150
4.99
5.6
592
3.9
670
For a single-ended (SE) output configuration, the
maximum output voltage VOUT(PK) is VDD/2. For a
bridge-tied-load (BTL) output configuration, the
maximum output voltage VOUT(PK) is VDD. For a
given input signal voltage, where VIN(PK) is the
peak input voltage, the maximum voltage gain is:
A V (MAX) 
switching frequency by using a different timing
capacitor CINT. For details, refer to the Table for
recommended SE output configuration design,
and Table 3 for recommended BTL output
configuration design.
This voltage-gain setting results in the peak
output voltage approaching its maximum for the
maximum input signal. In some cases the
amplifier is allowed to overdrive slightly, allowing
the THD to increase at high power levels, and so
a higher gain than AV (max) is required.
Setting the Switching Frequency
The idle switching frequency (the switching
frequency when no audio input is present) is a
function of several variables: The supply voltage
VDD, the integral capacitor CINT and the feedback
resistor RFB. Lower switching frequencies result
in greater inductor ripple, causing more quiescent
output voltage ripple, and increasing the output
noise
and
distortion.
Higher
switching
frequencies result in greater power loss. The
optimum quiescent switching frequency is
approximately 600kHz. When used to drive
stereo speakers in single-ended configuration,
set right channel to an idle switching frequency
greater than 50kHz plus the left channel’s
Table 3: Switching Frequency Setting for BTL
Output Configuration
VDD Gain RFB RIN
(V) (V/V) (kΩ) (kΩ)
CINT
(nF)
FSW
(kHz)
12
10
100
10
1.0
686
12
20
100
4.99
1.0
693
24
10
150
15
1.0
660
24
20
150
7.5
1.0
669
24
30
150
4.99
1.0
674
30
10
150
15
1.2
670
30
20
150
7.5
1.2
672
30
30
150
4.99
1.2
677
MP7748S Rev. 1.0
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10/14/2013
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MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
Choosing the Output LC Filter
The inductor-capacitor (LC) filter converts the
pulses at SW to the output voltage that drives the
speaker. There are two kinds of LC filter structure
depending on the output configuration.
COUT
LF
SW1/2
CF
RLOAD
Figure 3: SE Filter Configuration
LF1
SW1
CY1
CY2
SW2
CX
RLOAD
LF2
Figure 4: BTL Filter Configuration
Where:
LF  LF1  LF2 ,
CF  CX 
CY1  CY2
,
CY1  CY2
LF1  LF2 ;
CY1  CY2
The characteristic frequency of the LC filter
needs to be high enough to allow high frequency
audio to the output, yet needs to be low enough
to filter out high frequency products of the pulses
from the SW pin. The characteristic frequency of
the LC filter is:
f0 
1
2    LF  CF
The quality factor (Q) of the LC filter is important:
If this is too low, output noise will increase; if this is
too high, then peaking may occur at high
frequencies and reduce the passband flatness.
The circuit Q is set by the load resistance
(speaker resistance, typically 4Ω or 8Ω). Q is
calculated as:
Q
0
is
the
characteristic
frequency
in
radians/second and f0 is in Hz. Use an LC filter
with Q between 0.7 and 1.
The type of inductor and capacitor used in the LC
filter.greatly affects the output ripple and noise.
Use a film capacitor and an inductor with sufficient
power rating to supply the output current to the
load. The inductor must exhibit soft saturation
characteristics: If the inductor exhibits hard
saturation, it should operate well below the
saturation current. Use toroidal cores made of
gapped ferrite, MPP, powdered iron, or similar
materials. If using either an open or shielded
bobbin ferrite core for multi-channel designs,
make sure that the start windings of each inductor
align (all starting toward the SW pin, or all starting
toward the output) to prevent crosstalk or other
channel-to-channel interference.
Output Coupling Capacitor for SE Output
The output AC coupling capacitor—COUT—serves
to pass only the amplified AC signal from the LC
filter to the load and to block DC signals. The
combination of the coupling capacitor, COUT and
the load resistance results in a first-order highpass filter. Select COUT so that the required
minimum frequency passes. The output corner
frequency (-3dB point), fOUT, can be calculated
as:
fOUT 
1
2    R LOAD  C OUT
Set the output corner frequency (f OUT) at or below
the minimum required frequency.
The output coupling capacitor carries the full load
current, so chose a capacitor such that its ripple
current rating is greater than the maximum load
current. Use low-ESR aluminum electrolytic
capacitors for best results.
Input Coupling Capacitor
The input coupling capacitors CIN1 and CIN2 pass
only the AC signal at the input. For a typical
system application, the source input signal
centers around the circuit ground, while the
MP7748S input is at half the power supply
voltage (VDD/2). The input coupling capacitor
transmits the AC signal from the source
RLOAD
RLOAD

0  LF 2  f0  LF
MP7748S Rev. 1.0
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10/14/2013
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MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
to the MP7748S while blocking the DC voltage.
Choose an input coupling capacitor such that
the corner frequency (fIN) is less than the
passband frequency. The corner frequency is
calculated as:
fIN 
1
2    RIN  CIN
Timer capacitor
The start-up source current slew rate is related
to the timing capacitor CTIMER and SW voltage :
The higher SW voltage is, the smaller charge
current slew rate is. The larger the CTIMER
capacitance is, the longer the start-up time is.
Select a CTIMER value larger than 312nF, so the
start-up current slew rate would be small which
helps eliminate the turn-on pop. The
recommended 1μF capacitor CTIMER results in a
start-up current slew rate of approximately
20mA/350ms.
Power Source
For maximum output power, the amplifier circuit
requires a regulated external power source. A
high power-supply voltage can deliver more
power to a given load resistance, but a powersource voltage exceeding the maximum voltage
of 36V can damage the MP7748S. The
MP7748S’s power supply rejection is excellent,
though power-supply noise can pass to the
output, so care must be taken to minimize
power supply noise within the pass-band
frequencies. Bypass the power supply with a
large capacitor (typically aluminum electrolytic)
along with a smaller 1μF ceramic capacitor at
the MP7748S VDD supply pins.
PCB Layout
Circuit layout is critical for optimal performance,
low output distortion, and noise. Duplicate the
EVB layout for best results. For layout changes,
follow these guidelines and use Figure 7 and
Figure 8 as references.
1) Place the following components as close to
the MP7748S as possible:
Bootstrap Capacitors
CBS1 and CBS2 supply the gate drive current to
the internal HS-FET. Place CBS1 as close to
BST1/2 pin and SW1/2 pin as possible.
Likewise, place CBS2 as close to BST2 pin and
SW2 pins as possible.
Power Supply Bypass Capacitors
CBYP1 and CBYP2 carry the transient current for
the switching power stage. To avoid
overstressing the MP7748S and excessive
output noise, place CBYP1 as close to the VDD1
pins and PGND1 pins as possible, and place
CBYP2 as close to the VDD2 pins and PGND2
pins as possible.
Integral Capacitors
CINT sets the amplifier switching frequencies
and are typically on the order of a few nF. Place
the integral capacitor CINT as close to the
corresponding input as possible to reduce
distortion and noise. For example, place CINT1
as close to pins 2 and 3 as possible at SE
output configuration.
Reference Bypass Capacitors for SE Output
When used with SE output, CR1 and CR2 filter
the ½ VDD reference voltages. Place CR1 and
CR2 as close to the IC as possible to improve
power supply rejection and reduce distortion
and noise at the output.
2) The Inductor-Capacitor (LC) filter converts
the pulse train at SW to the output voltage that
drives the speaker. Please keep the filter
capacitor close to the inductor.
3) When laying out the PCB, use two separate
ground planes—analog ground (AGND) and
power ground (PGND)—and connect the two
grounds together at a single point (usually
around the bulk bypass capacitor) to prevent
noise injection into the amplifier input to reduce
distortion.
4) Keep the sensitive feedback signal trace on
the input side and shield the trace with the
AGND plane. Make sure that any traces
carrying the switch node (SW) voltages are
routed far from any input signal traces. If the
trace must run near the SW trace near the
input, shield the input with a ground plane
between the traces. Physically separate each
channel to prevent crosstalk. Make sure that all
inductors used on a single circuit board have
the same orientation.
MP7748S Rev. 1.0
www.MonolithicPower.com
10/14/2013
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19
MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
Route each power supply from the source to
each channel individually, not serially. This
prevents channel-to-channel coupling through
the power supply input.
Electro-Magnetic Interference (EMI)
Considerations
Due to the switching nature of Class D
amplifiers, care must be taken to minimize the
effects of electromagnetic interference from the
amplifier. However, proper component selection
and careful attention to circuit layout can
minimize the effects of the EMI due to the
amplifier switching.
The power inductors are a potential source of
radiated emissions. For the best EMI
performance, use toroidal inductors, since the
magnetic field is well-contained inside the core.
However toroidal inductors can be expensive to
wind. For a more economical solution, use
shielded-gapped–ferrite or shielded-ferritebobbin-core inductors. These inductors typically
do not contain the EM field as well toroidal
inductors, but can achieve a better balance
between good EMI performance with low cost.
The size of high-current loops that carry rapidly
changing currents must be minimized: Make
sure that the VDD bypass capacitors are as
close to the MP7748S as possible.
Nodes that carry rapidly changing voltage, such
as SW, need to be made as small as possible.
If sensitive traces run near a trace connected to
SW, place a ground shield between the traces.
MP7748S Rev. 1.0
www.MonolithicPower.com
10/14/2013
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© 2013 MPS. All Rights Reserved.
20
MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
TYPICAL APPLICATION CIRCUITS
Figure 5—30V VDD Stereo SE Typical Application Circuit
Figure 6—30V VDD mono BTL Typical Application Circuit
MP7748S Rev. 1.0
www.MonolithicPower.com
10/14/2013
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© 2013 MPS. All Rights Reserved.
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MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
AGND
AGND
PGND
CVDDBYP
PGND
C FB1
R FB1
CR1
CINT1
1
NC
PGND1
28
2
REF1
PGND1
27
3
IN1
SW1
26
4
TIMER1
SW1
25
5
AGND1
BST1
24
6
EN1
VDD1
23
7
UVP1
VDD1
22
8
IN2
PGND2
21
9
REF2
PGND2
20
CINT2
MP7748S
10
TIMER2
SW2
19
11
AGND2
SW2
18
12
EN2
BST2
17
13
UVP2
VDD2
16
14
NC
VDD2
15
CR2
CF1
C BYP1
LF1
CBS1
C BYP2
LF2
CBS2
CF2
R FB2
Feedback
signal
C FB2
Top
Bottom
Figure 7—Stereo SE Reference PCB Layout
CFB1
RFB1
CFX1
26
4
TIMER1
SW1
25
5
AGND1
BST1
24
6
EN1
VDD1
23
7
UVP1
VDD1
22
8
IN2
PGND2
21
9
REF2
PGND2
20
MP7748S
10
TIMER2
SW2
19
11
AGND2
SW2
18
12
EN2
BST2
17
13
UVP2
VDD2
16
14
NC
VDD2
15
CBYP1
LF1
CBS1
CF1
SW1
CF3
27
IN1
CBYP2
CF2
28
PGND1
C F1
PGND1
REF1
3
CF3
NC
2
CF2
CINT
1
LF2
CBS2
CFX2
RFB2
Feedback
signal
CFB2
CVDDBYP
CVDDBYP
AGND
PGND
Top
AGND
PGND
Bottom
Figure 8—Mono BTL Reference PCB Layout
MP7748S Rev. 1.0
www.MonolithicPower.com
10/14/2013
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
22
MP7748S –2 X 30W STEREO SE OR 60W MONO BTL CLASS D AUDIO AMPLIFIER
PACKAGE INFORMATION
TSSOP28-EP
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP7748S Rev. 1.0
www.MonolithicPower.com
10/14/2013
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
23
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