DDR3(L) 4GB / 8GB UDIMM
Nanya Technology Corp.
DDR3(L) 4GB/8GB UDIMM
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
DDR3(L) 4Gb C-Die
DDR3(L) 4GB / 8GB UDIMM
Features
 Signal Integrity
 JEDEC DDR3(L) Compliant1
- Configurable DS for system compatibility
- 8n Prefetch Architecture
- Configurable On-Die Termination
- Differential Clock(CK/) and Data Strobe(DQS/)
- ZQ Calibration
- Double-data rate on DQs, DQS and DM
 Signal Synchronization
 Data Integrity
- Write Leveling via MR settings
- Auto Self Refresh (ASR) by DRAM built-in TS
- Read Leveling via MPR
- Auto Refresh and Self Refresh Modes
 Residual Information
 Power Saving Mode
- Partial Array Self Refresh (PASR)
3
- Serial Presence-Detect (SPD) EEPROM
2
- Fly-by I/O topology
- Power Down Mode
- Terminated control, command, and address bus
Options
 Module / DRAM Speed Grade (CL-TRCD-TRP)
 Interface and Power Supply5
4
- PC3(L)-12800 / DDR3(L)-1600 (11-11-11)
- DDR3(SSTL_15): VDD/VDDQ=1.5V(±0.075V)
- PC3(L)-12800 / DDR3(L)-1600 (9-9-9)
- DDR3L(SSTL_135): VDD/VDDQ=1.35V(-0.067/+0.1V)
 Temperature Range (TA)
- 0℃ ~ 65℃
Programmable Functions
 CAS Latency (5/6/7/8/9/10/11/12/13/14)
 Self RefreshTemperature Range(Normal/Extended)
 CAS Write Latency (5/6/7/8/9/10)
 Output Driver Impedance (34/40)
 Additive Latency (0/CL-1/CL-2)
 On-Die Termination of Rtt_Nom(20/30/40/60/120)
 Write Recovery Time (5/6/7/8/10/12/14/16)
 On-Die Termination of Rtt_WR(60/120)
 Burst Type (Sequential/Interleaved)
 Precharge Power Down (slow/fast)
 Burst Length (BL8/BC4/BC4 or 8 on the fly)
Packages / Density Information
Density and Addressing
Lead-free RoHS compliance and Halogen-free
Configuration
Pin
count
(mm)
30
(512Mbx64)
Mechanical
Specifications
DRAM (512Mb x 8)
4GB
PCB
height
MO-269 R/C B
240
8GB
(1024Mbx64)
30
MO-269 R/C B
DIMM
4GB
8GB
Rank Address
 
2 ([1:0])
DRAM Number
8
16
Refresh Count
8K
Bank Address
8 ( BA[2:0] )
Row Address
64K ( A[15:0] )
Column Address
1K ( A[9:0] )
tREFI
tRFC
6
7.8μs
6
260ns
Notes:
1. Based on NTC DDR3 4Gb C-Die component.
2. Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand.
3. Only Support prime DQ’s feedback for each byte lane.
4. The timing specification of high speed bin is backward compatible with low speed bin.
5. SSTL_135 compatible to SSTL_15.
6. Can not violate tREFI or tRFC.
Version 1.2
02/2014
1
NTC has the rights to change any specifications or product without notification.
Nanya Technology Cooperation ©
All Rights Reserved.
DDR3(L) 4GB/8GB UDIMM
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
Fundamental AC Specifications
DDR3(L)-1600 and DDR3(L)-1333
Speed Bins
DDR3(L)-1600
DDR3(L)-1333
11-11-11
9-9-9
10-10-10
Unit
Parameter
Min
Max
Min
Max
Min
Max
tAA
13.75
20
13.5
20
15
20
ns
tRCD
13.75
-
13.5
-
15
-
ns
tRP
13.75
-
13.5
-
15
-
ns
tRC
48.75
-
49.5
-
51
-
ns
tRAS
35
9xtREFI
36
9xtREFI
36
9xtREFI
ns
DDR3(L)-1066 and DDR3(L)-800
DDR3(L)-1066
Speed Bins
Version 1.2
02/2014
7-7-7
DDR3(L)-800
8-8-8
5-5-5
6-6-6
Unit
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
tAA
13.125
20
15
20
12.5
20
15
20
ns
tRCD
13.125
-
15
-
12.5
-
15
-
ns
tRP
13.125
-
15
-
12.5
-
15
-
ns
tRC
50.625
-
52.5
-
50
-
52.5
-
ns
tRAS
37.5
9xtREFI
37.5
9xtREFI
37.5
9xtREFI
37.5
9xtREFI
ns
2
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DDR3(L) 4GB/8GB UDIMM
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
Descriptions
M2F(X)4G64CB88C4(5/7/H)N / M2F(X)8G64CB8HC4(5/9)N are 240-Pin Double Data Rate 3 (DDR3)
Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM), organized as one rank of 512Mx64
(4GB) and two ranks of 1024Mx64 (8GB) high-speed memory array. Modules use eight 512Mx8 (4GB) and
sixteen 512Mx8 (8GB) 78-ball BGA packaged devices. These DIMMs are manufactured using raw cards
developed for broad industry use as reference designs. The use of these common design files minimizes
electrical variation between suppliers.
The DIMM is intended for use in applications operating of 800MHz clock speeds and achieves high-speed data
transfer rates of 12800Mbps. Prior to any access operation, the device  latency and burst/length/operation
type must be programmed into the DIMM by address inputs and I/O inputs using the mode register set
cycle.The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol.
The first 128 bytes of SPD data are programmed and locked during module assembly. The remaining 128
bytes are available for use by the customer.
Version 1.2
02/2014
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All Rights Reserved.
DDR3(L) 4GB/8GB UDIMM
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
Ordering Information
Organization
Part Number
1
Speed
2
Heat Sink
Clock (MHz)
DIMM (Mbps)
DRAM (Mbps)
CL-TRCD-TRP
DDR3 (SSTL_15)
512Mb x 64
(4GB)
1024Mb x 64
(8GB)
M2X4G64CB88C4N-DG
NO
800
PC3-12800
DDR3-1600
9-9-9
M2X4G64CB88C5N-DG
NO
800
PC3-12800
DDR3-1600
9-9-9
M2X4G64CB88C7N-DG
NO
800
PC3-12800
DDR3-1600
9-9-9
M2X4G64CB88CHN-DG
YES
800
PC3-12800
DDR3-1600
9-9-9
M2F4G64CB88C4N-DI
NO
800
PC3-12800
DDR3-1600
11-11-11
M2F4G64CB88C5N-DI
NO
800
PC3-12800
DDR3-1600
11-11-11
M2F4G64CB88C7N-DI
NO
800
PC3-12800
DDR3-1600
11-11-11
M2X8G64CB8HC4N-DG
NO
800
PC3-12800
DDR3-1600
9-9-9
M2X8G64CB8HC5N-DG
NO
800
PC3-12800
DDR3-1600
9-9-9
M2X8G64CB8HC9N-DG
YES
800
PC3-12800
DDR3-1600
9-9-9
M2F8G64CB8HC4N-DI
NO
800
PC3-12800
DDR3-1600
11-11-11
M2F8G64CB8HC5N-DI
NO
800
PC3-12800
DDR3-1600
11-11-11
M2F8G64CB8HC9N-DI
YES
800
PC3-12800
DDR3-1600
11-11-11
NOTE 1 Bit 13 of part number stands for the combination of PCB version with/without heat sink.
NOTE 2 The timing specification of high speed bin is backward compatible with low speed bin.
Version 1.2
02/2014
4
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DDR3(L) 4GB/8GB UDIMM
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
Pin Description
Pin Name
Description
Pin Name
Description
CK[1:0]
Clock Inputs, positive line
SA[2:0]
[1:0]
Clock Inputs, negative line
DQ[63:0]
Data input/output
Clock Enable
DQS[7:0]
Data strobes

Row Address Strobe
[7:0]
Data strobes complement

Column Address Strobe
DM[7:0]
Data Masks

Write Enable

Reset pin
[1:0]
Chip Selects
VDD ,VDDQ
CKE[1:0]
A[9:0], A11,
A[15:13]
Address Inputs
VSS
Core and I/O power
Ground
A10/AP
Address Input/Auto-Precharge
A12/
Address Input/Burst Chop
BA[2:0]
SDRAM Bank Address Inputs
VTT
Termination voltage
ODT[1:0]
Active termination control lines
NC
No Connect
SCL
Serial Presence Detect Clock Input
SDA
Serial Presence Detect Data Input/Output
Version 1.2
02/2014
VREFCA ,VREFDQ
Serial Presence Detect Address Inputs
VDDSPD
5
Input/output Reference
SPD power
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DDR3(L) 4GB/8GB UDIMM
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
4GB(1-Rank) Package Dimensions
FRONT
133.35 +/- 0.15
2.70 Max.
Detail B
Detail A
5.175
30.00 +/-0.15
17.30
9.50
3.0 (x4)
SIDE
47.00
71.00
5.00
1.27 +/-0.10
BACK
2.50
Detail B
4.00
3.80
Detail A
0.80 +/- 0.05
1.00 Pitch
1.50 +/- 0.10
Units: Millimeters
Version 1.2
02/2014
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DDR3(L) 4GB/8GB UDIMM
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
8GB(2-Ranks) Package Dimensions
FRONT
133.35 +/- 0.15
4.00 Max.
Detail B
Detail A
5.175
30.00 +/-0.15
17.30
9.50
3.0 (x4)
SIDE
47.00
71.00
5.00
1.27 +/-0.10
BACK
2.50
Detail B
4.00
3.80
Detail A
0.80 +/- 0.05
1.00 Pitch
1.50 +/- 0.10
Units: Millimeters
Version 1.2
02/2014
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All Rights Reserved.
DDR3(L) 4GB/8GB UDIMM
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
Pin Assignment
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
1
VREFDQ
2
VSS
3
4
Front
Pin
Back
Pin
Front
121
VSS
31
DQ25
122
DQ4
32
VSS
151
VSS
152
DM3
61
A2
62
VDD
DQ0
123
DQ5
33

153
NC
63
DQ1
124
VSS
34
DQS3
154
VSS
5
VSS
125
DM0
6

126
NC
35
36
VSS
155
DQ26
156
7
DQS0
127
VSS
37
DQ27
8
VSS
9
DQ2
128
DQ6
129
DQ7
38
39
10
DQ3
130
VSS
Pin
Back
181
A1
91
DQ41
211
VSS
182
VDD
92
VSS
212
DM5
CK1,NC
183
VDD
93

213
NC
64
,NC
184
CK0
94
DQS5
214
VSS
DQ30
65
VDD
185

95
VSS
215
DQ46
DQ31
66
VDD
186
VDD
96
DQ42
216
DQ47
157
VSS
67
VREFCA
187
NC
97
DQ43
217
VSS
VSS
158
NC
68
NC
188
A0
98
VSS
218
DQ52
NC
159
NC
69
VDD
189
VDD
99
DQ48
219
DQ53
40
NC
160
VSS
70
A10/AP
190
BA1
100
DQ49
220
VSS
11
VSS
131
DQ12
41
VSS
161
NC
71
BA0
191
VDD
101
VSS
221
DM6
12
DQ8
132
DQ13
42

162
NC
72
VDD
192

102

222
NC
13
DQ9
133
VSS
43
NC
163
VSS
73

193

103
DQS6
223
VSS
14
VSS
134
DM1
44
VSS
164
NC
74

194
VDD
104
VSS
224
DQ54
15

135
NC
45
NC
165
NC
75
VDD
195
ODT0
105
DQ50
225
DQ55
16
DQS1
136
VSS
46
NC
166
VSS
76
,NC
196
A13
106
DQ51
226
VSS
17
VSS
137
DQ14
47
VSS
167
NC
77
ODT1,NC
197
VDD
107
VSS
227
DQ60
18
DQ10
138
DQ15
48
NC
168

78
VDD
198
NC
108
DQ56
228
DQ61
19
DQ11
139
VSS
49
NC
169
CKE1/NC
79
NC
199
VSS
109
DQ57
229
VSS
20
VSS
140
DQ20
50
CKE0
170
VDD
80
VSS
200
DQ36
110
VSS
230
DM7
21
DQ16
141
DQ21
51
VDD
171
A15
81
DQ32
201
DQ37
111

231
NC
22
DQ17
142
VSS
52
BA2
172
A14
82
DQ33
202
VSS
112
DQS7
232
VSS
23
VSS
143
DM2
53
NC
173
VDD
83
VSS
203
DM4
113
VSS
233
DQ62
24

144
NC
54
VDD
174
A12/
84

204
NC
114
DQ58
234
DQ63
25
DQS2
145
VSS
55
A11
175
A9
85
DQS4
205
VSS
115
DQ59
235
VSS
26
VSS
146
DQ22
56
A7
176
VDD
86
VSS
206
DQ38
116
VSS
236
VDDSPD
27
DQ18
147
DQ23
57
VDD
177
A8
87
DQ34
207
DQ39
117
SA0
237
SA1
28
DQ19
148
VSS
58
A5
178
A6
88
DQ35
208
VSS
118
SCL
238
SDA
29
VSS
149
DQ28
59
A4
179
VDD
89
VSS
209
DQ44
119
SA2
239
VSS
30
DQ24
150
DQ29
60
VDD
180
A3
90
DQ40
210
DQ45
120
VTT
240
VTT
NOTE 1 CK1, 1, , CKE1 and ODT1 are not used for 4GB UDIMM.
Version 1.2
02/2014
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DDR3(L) 4GB/8GB UDIMM
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
Input/Output Functional Descriptions
Symbol
Type
Polarity
Function
CK0, CK1
, 
Input
Cross
point
CK and  are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on
the crossing of positive edge of CK and negative edge of . Output (read) data is referenced
to the crossing of CK and  (Both directions of crossing).
CKE[1:0]
Input
Active
High
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
[1:0]
Input
Active
Low
Enables the associated DDR3 SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue, Rank 0 is selected by ; Rank 1 is selected by 
, , 
Input
Active
Low
,  and (along with ) define the command being entered.
ODT[1:0]
Input
Active
High
Asserts on-die termination for DQ, DM, DQS, and  signals if enabled via the DDR3
SDRAM mode register.
BA[2:0]
Input
-
Selects which DDR3 SDRAM internal bank of eight is activated.
During a Bank Activate command cycle, defines the row address when sampled at the cross
point of the rising edge of CK and falling edge of . During a Read or Write command cycle,
defines the column address when sampled at the cross point of the rising edge of CK and
falling edge of . In addition to the column address, AP is used to invoke autoprecharge
operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected
and BA[3:0] defines the bank to be precharged. If AP is low, autoprecharge is disabled. During
a Precharge command cycle, AP is used in conjunction with BA[3:0] to control which bank(s) to
precharge. If AP is high, all banks will be precharged regardless of the state of BA[3:0] inputs. If
AP is low, then BA[3:0] are used to define which bank to precharge. A12/ is sampled during
READ and WRITE commands to determine if burst chop (on-the-fly) will be performed (HIGH,
no burst chop; LOW, burst chopped).
A[9:0]
A10/AP
A11
A12/
A[15:13]
Input
-
DM[7:0]
Input
Active
High
DM is an input mask signal for write data. Input data is masked when DM is sampled High
coincident with that input data during a write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
DQS[7:0]
[7:0]
I/O
Cross
point
Data strobe for input and output data. For raw cards using x16 organized DRAMs, Pins
DQ0–DQ7 are associated with the LDQS and  pins and Pins DQ8–DQ15 are associated
with UDQS and  pins.
DQ[63:0]
I/O
-
Data Input/Output pins.
VDD, VSS
Supply
-
Power and ground for the DDR3 SDRAM input buffers, and core logic. VDD and VDDQ pins
are tied to VDD/VDDQ planes on these modules.
VDDQ
Supply
-
Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all
current DDR3 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
VDDSPD
Supply
-
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane.
EEPROM supply is operable from 3.0V to 3.6V.
VREFDQ, VREFCA
Supply
-
Reference voltage for inputs.
SDA
I/O
-
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must
be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up.
SCL
Input
-
This pin is used to clock data into and out of the SPD EEPROM. A resistor must be connected
from the SCL bus line to VDDSPD on the system planar to act as a pull up.
SA[2:0]
Input
-
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD
EEPROM address range.

Input
-
The  pin is connected to the  pin on each DRAM. When low, all DRAMs are set to
aknown state.
ZQ
Supply
-
Reference pin for ZQ calibration.
Version 1.2
02/2014
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DDR3(L) 4GB/8GB UDIMM
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
4GB (1-Rank) Functional Block Diagram


DQS0
DM0

DQS4
DM4
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

DQS
0
1
2
3
4
5
6
7

DM
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
ZQ

DQS1
DM1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

DQS
0
1
2
3
4
5
6
7

DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
ZQ

DQS2
DM2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

DQS
0
1
2
3
4
5
6
7

SA0
SA1
SA2
D2
ZQ
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

DQS
0
1
2
3
4
5
6
7
SCL
A0
A1
A2

D4
ZQ

0
1
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DQS

D5
ZQ

0
1
2
3
4
5
6
7
DM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
ZQ
SPD
SDA
WP
DDR3
SDRAM
CKE0, A[15:0],
, , ,
ODT0, BA[2:0], 
VTT
DDR3
SDRAM
CK

Version 1.2
02/2014

DQS

D6
ZQ

DQS7
DM7
DM
SCL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS

DQS6
DM6
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

0
1
2
3
4
5
6
7

DQS5
DM5
DM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDDSPD
VDD/VDDQ
VREFDQ
VSS
VREFCA
BA0-BA2
A0-A15


CKE0

ODT0
CK0


I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7

DQS

D7
ZQ
SPD
D0-D7
D0-D7
D0-D7
D0-D7
BA0-BA2: SDRAMs D0-D7
A0-A15: SDRAMs D0-D7
: SDRAMs D0-D7
: SDRAMs D0-D7
CKE: SDRAMs D0-D7
: SDRAMs D0-D7
ODT: SDRAMs D0-D7
CK: SDRAMs D0-D7
: SDRAMs D0-D7
: SDRAMs D0-D7
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown.
3. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ
resistor is 240Ω ±1%.
4. One SPD exists per module.
10
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DDR3(L) 4GB/8GB UDIMM
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
8GB (2-Ranks) Functional Block Diagram



DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQS4
DM4
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D0
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D8
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
ZQ

DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D1
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D9
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DQS
D4
ZQ
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D12
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D13
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
ZQ
DQS
DQS
D5
ZQ
ZQ
DQS6
DQS6
DM6
DM
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D2
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D10
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
ZQ

DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CS

DQS5
DM5

DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D6
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D7
I/O 4
I/O 5
I/O 6
I/O 7
DQS
ZQ
CS
DQS
D14
ZQ

DQS7
DM7
DM
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
CS
DQS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D11
ZQ
VDDSPD
VDD/VDDQ
VREFDQ
VSS
VREFCA
BA0-BA2
A0-A15



CKE0
CKE1
ODT0
ODT1
CK0

CK1


DDR3
SDRAM
CKE[1:0], A[15:0],
, , ,
ODT[1:0], BA[2:0],
[1:0]
VTT
DDR3
SDRAM
CK

SCL
SA0
SA1
SA2
VDD
SCL
A0
A1
A2
SPD
SDA
WP
ZQ
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D15
I/O 4
I/O 5
I/O 6
I/O 7
DQS
ZQ
SPD
D0-D15
D0-D15
D0-D15
D0-D15
BA0-BA2: SDRAMs D0-D15
A0-A15: SDRAMs D0-D15
: SDRAMs D0-D15
: SDRAMs D0-D15
: SDRAMs D0-D15
CKE: SDRAMs D0-D7
CKE: SDRAMs D8-D15
ODT: SDRAMs D0-D7
ODT: SDRAMs D8-D15
CK: SDRAMs D0-D7
: SDRAMs D0-D7
CK: SDRAMs D8-D15
: SDRAMs D8-D15
: SDRAMs D8-D15
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown.
3. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ
resistor is 240Ω ±1%.
4. One SPD exists per module.
Version 1.2
02/2014
11
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DDR3(L) 4GB/8GB UDIMM
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
DDR3L Operating, Standby, and Refresh Currents
Symbol
Parameter/Condition
4GB
8GB
Unit
IDD0
Operating One Bank Active-Precharge Current
282
414
mA
IDD1
Operating One Bank Active-Read-Precharge Current
367
500
mA
IDD2P0
Precharge Power-Down Current Slow Exit
51
102
mA
IDD2P1
Precharge Power-Down Current Fast Exit
52
104
mA
IDD2Q
Precharge Quiet Standby Current
104
208
mA
IDD2N
Precharge Standby Current
133
266
mA
IDD3P
Active Power-Down Current
99
197
mA
IDD3N
Active Standby Current
187
319
mA
IDD4R
Operating Burst Read Current
790
923
mA
IDD4W
Operating Burst Write Current
651
784
mA
IDD5B
Burst Refresh Current
880
1013
mA
IDD6
Self Refresh Current: Normal Temperature Range
76
151
mA
IDD7
Operating Bank Interleave Read Current
1212
1345
mA
DDR3 Operating, Standby, and Refresh Currents
Symbol
4GB
8GB
Unit
IDD0
Operating One Bank Active-Precharge Current
Parameter/Condition
309
461
mA
IDD1
Operating One Bank Active-Read-Precharge Current
405
557
mA
IDD2P0
Precharge Power-Down Current Slow Exit
57
114
mA
IDD2P1
Precharge Power-Down Current Fast Exit
58
116
mA
IDD2Q
Precharge Quiet Standby Current
121
241
mA
IDD2N
Precharge Standby Current
152
304
mA
IDD3P
Active Power-Down Current
212
424
mA
IDD3N
Active Standby Current
106
259
mA
IDD4R
Operating Burst Read Current
863
1016
mA
IDD4W
Operating Burst Write Current
722
875
mA
IDD5B
Burst Refresh Current
919
1071
mA
80
160
mA
1289
1441
mA
IDD6
Self Refresh Current: Normal Temperature Range
IDD7
Operating Bank Interleave Read Current
Version 1.2
02/2014
12
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DDR3(L) 4GB/8GB UDIMM
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
Note
0 to 65
o
3
Storage Temperature
-50 to 100
o
C
1
TSTG
Storage Temperature (Plastic)
-55 to 100
°C
1
HSTG
Storage Humidity (without condensation)
5 to 95
%
1
PBAR
Barometric Pressure (operating & storage)
105 to 69
K Pascal
1, 2
TOPER
Operating Temperature (ambient)
TSTG
C
Note:
1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and device functional
operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. Up to 9850 ft.
3. The component maximum case temperature shall not exceed the value specified in the component spec.
Recommended DC Operating Conditions
Symbol
VDDSPD
Core Supply Voltage
VDD
Supply Voltage
VDDQ
Rating
Parameter
Unit
Min.
Typ.
Max.
─
3.0
3.3
3.6
DDR3
1.425
1.5
1.575
Note
V
1,2
V
DDR3L
1.283
1.35
1.45
DDR3
1.425
1.5
1.575
Supply Voltage for Output
3,4,5,6
1,2
V
DDR3L
1.283
1.35
1.45
3,4,5,6
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. Maximun DC value may not be great than 1.425V.The DC value is the linear average of VDD/ VDDQ(t) over a very long period of time
(e.g., 1 sec).
4. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
5. Under these supply voltages, the device operates to this DDR3L specification.
6. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed
for DDR3L operation.
7. VDD= VDDQ= 1.35V (1.283–1.45V )
Backward compatible to VDD= VDDQ= 1.5V ±0.075V
Supports DDR3L devices to be backward com-patible in 1.5V applications
Version 1.2
02/2014
13
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DDR3(L) 4GB/8GB UDIMM
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
Revision History
Version
Page
Modified
1.0
-
-
1.1
-
1.2
P4
Version 1.2
02/2014
Description
Released
12/2013
-
Official Release.
1. Add Part Number to ordering info.
2. Add DDR3L Spec
-
Remove 1.35V part number.
02/2014
14
12/2013
Nanya Technology Cooperation ©
All Rights Reserved.
DDR3(L) 4GB/8GB UDIMM
M2F(X)4G64CB88C4(5/7/H)N
M2F(X)8G64CB8HC4(5/9)N
http://www.elixir-memory.com/
Version 1.2
02/2014
15
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