XRD9814B/XRD9816B

XRD9814B/XRD9816B
XRD9814B/XRD9816B
3-Channel 14/16-Bit Linear
CCD/CIS Sensor Signal Processors
November 2002-2
FEATURES
• 14-Bit (XRD9814B) or 16-Bit (XRD9816B)
A/D Converter
• Triple-Channel, 2.5 MSPS Color Scan Mode
• Single-Channel, 6 MSPS Monochrome Scan
Mode
• Triple Correlated Double Sampler
• Triple 10-Bit Programmable Gain Amplifier
• Triple 10-Bit Offset Compensation DAC
• Fully Differential or Single-Ended Inputs
• CDS or S/H Mode
• Inverting or Non-Inverting Mode
• Internal Voltage Reference
• Serial Control: On Data Bus or Separate Pins
• Improved PGA Performance
• 14-Bit or 8-Bit (Nibble) Parallel Data Output
(XRD9814B)
• 16-Bit or 8-Bit (Nibble) Parallel Data Output
(XRD9816B)
• 5V Operation and 3V I/O Compatibility
• Low Power CMOS: 500mW @ 5V
APPLICATIONS
•
•
•
•
•
48-Bit Color Scanners (XRD9816B)
42-Bit Color Scanners (XRD9814B)
CCD or CIS Color Imagers
Gray Scale Scanners
Film Scanners
GENERAL DESCRIPTION
The XRD9814B/9816B is a fully integrated, high-performance analog signal processor/digitizer specifically designed for use in 3-channel linear Charge
Coupled Device (CCD) and Contact Image Sensitive
(CIS) imaging applications.
Each channel of the XRD9814B/9816B includes a
Correlated Double Sampler (CDS), Programmable
Gain Amplifier (PGA) and channel offset adjustment.
After gain and offset adjustment, the analog inputs are
sequentially sampled and digitized by an accurate 14/
16-bit A/D converter. The analog front-end can be
configured for inverting/non-inverting input, CDS or
sample-hold (S/H) mode, or AC/DC coupling,
making the XRD9814B/9816B suitable for use in CCD,
CIS and other data acquisition applications.
The CDS mode of operation supports both line and
pixel-clamp modes and can be used to achieve significant reduction in system 1/f noise and CCD reset
clock feed-through. In S/H mode the internal DCrestore voltage clamp can be enabled or disabled to
support AC-coupled or DC inputs. Sampling mode,
10-bit PGA gain (1024 linear steps), 8-bit fine offset
adjustment (256 linear steps), 2-bit gross offset adjustment and input signal polarity are all programmable
through a serial interface. PGA gain range is 1 to 10,
and channel offset range is -300mV to 300mV for fine
adjustment and additional -400mV to +200mV for
gross offset adjustment. The A/D Full-Scale Range
(FSR) is programmable to 2V or 3V.
ORDERING INFORMATION
Part No.
Package Type
Temperature Range
XRD9814BCV
48-Lead TQFP
0°C to +70°C
XRD9816BCV
48-Lead TQFP
0°C to +70°C
Rev. 1.00
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRD9814B/9816B
BSAMP
VSAMP
ADCCLK
LCLMP
INTERNAL TIMING CONTROL
INSEL
10-BIT
RED(+)
RED(-)
PROGRAMMABLE
BUFFERED
CDS or S/H
OUTSEL
I/O CONTROL AND
CONFIGURATION
REGISTERS
PGA
SDI
SCLK
REGISTER
LOAD
10-BIT
DAC
AGND1
TEST1
TEST2
REGISTER
AVDD1
AVDD2
10-BIT
GRN(+)
GRN(-)
PROGRAMMABLE
BUFFERED
CDS or S/H
AVDD3
3-1
MUX
PGA
REGISTER
SGND
VREF
1.24V
10-BIT
DAC
OEB
REGISTER
AGND2
14/16-BIT A/D
10-BIT
BLU(+)
BLU(-)
PROGRAMMABLE
BUFFERED
CDS or S/H
VREF- VREF+
OUTPUT
PORT
REFIN
14/16
DB<13:0>
or
DB<15:0>
PGA
CAPP
REGISTER
CAPN
10-BIT
DAC
VCLAMP
(Internal)
CREF
DVDD
REGISTER
DGND
Figure 1. Block Diagram
Rev. 1.00
2
XRD9814B/9816B
DB9
DB10
DB11
DB12
DB13
DVDD
DGND
SCLK
SDI
LOAD
OEB
OUTSEL
PIN CONFIGURATION
48
47
46
45
44
43
42
41
40
39
38
37
DB8
1
36
INSEL
DB7
2
35
ADCCLK
DB6
3
34
BSAMP
DB5
4
33
VSAMP
DB4
5
32
LCLMP
DB3
6
31
AVDD1
DB2
7
30
AGND1
DB1
8
29
SGND
DB0
9
28
CAPN
N/C
10
27
CAPP
N/C
11
26
CREF
AVDD3
12
25
TEST2
AGND2
RED(+)
RED(-)
N/C
GRN(+)
19
20
21
22
23
24
TEST1
18
N/C
17
BLU(-)
16
N/C
15
BLU(+)
14
GRN(-)
13
AVDD2
XRD9814BCV
Note:
Pins 17,20 and 23 should be connected to AGND2 to improve noise immunity
PIN DESCRIPTION - XRD9814B
Pin No.
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
N/C
N/C
AVDD3
AVDD2
AGND2
RED(+)
Description
Data Output Bit 8
Data Output Bit 7
Data Output Bit 6
Data Output Bit 5
Data Output Bit 4
Data Output Bit 3
Data Output Bit 2
Data Output Bit 1
Data Output Bit 0
No Connect
No Connect
Analog Power Supply
Analog Power Supply
Analog Ground (Substrate)
Red Positive Analog Input
Rev. 1.00
3
XRD9814B/9816B
PIN DESCRIPTION - XRD9814B (CONT'D)
Pin No.
Name
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
RED(-)
N/C
GRN(+)
GRN(-)
N/C
BLU(+)
BLU(-)
N/C
TEST1
TEST2
CREF
CAPP
CAPN
SGND
AGND1
AVDD1
LCLMP
VSAMP
BSAMP
ADCCLK
INSEL
OUTSEL
OEB
LOAD
SDI
SCLK
DGND
DVDD
DB13
DB12
DB11
DB10
DB9
Description
Red Negative Analog Input
No Connect, (Note 5)
Green Positive Analog Input
Green Negative Analog Input
No Connect, (Note 5)
Blue Positive Analog Input
Blue Negative Analog Input
No Connect, (Note 5)
Internal Use Only
Internal Use Only
Decoupling Cap for CDS Reference
Decoupling Cap for Positive Reference
Decoupling Cap for Negative Reference
Substrate Gnd
Analog Ground (Substrate)
Analog Power Supply
Line Clamp Enable
Video Level Sampling Clock
Black Level Sampling Clock
A/D Converter Clock
Input Mode Select (Note 1)
Output Mode Select (Note 2)
Data Output Enable
Register Write Enable (Note 5)
Serial Data Input (Note 4)
Serial Shift Clock (Note 3)
Ground (Output Drivers and Internal Decode Logic)
Digital Power Supply (Output Drivers and Internal Decode Logic)
Data I/O Bit 13 (Note 4)
Data I/O Bit 12 (Note 3)
Data Output Bit 11
Data Output Bit 10
Data Output Bit 9
Note 1: INSEL=0 —> SCLK, SDI, and LOAD pins are active for serial programming; INSEL=1 —> SCLK and SDI pins
are inactive, and the serial programming is done through I/O pins DB12 and DB13 as described in Notes 3~4 with
LOAD tri-stating DB12 and DB13.
Note 2: OUTSEL=0 —> 14-bit parallel output mode select; OUTSEL=1 —> 8-bit nibble output mode select.
Note 3: For INSEL=1, DB12 becomes the SCLK input during serial programming.
Note 4: For INSEL=1, DB13 becomes the SDI input during serial programming.
Note 5: Pins 17, 20 and 23 may be connected to AGND2 to improve noise immunity.
Rev. 1.00
4
XRD9814B/9816B
DB11
DB12
DB13
DB14
DB15
DVDD
DGND
SCLK
SDI
LOAD
OEB
OUTSEL
PIN CONFIGURATION
48
47
46
45
44
43
42
41
40
39
38
37
DB10
1
36
INSEL
DB9
2
35
ADCCLK
DB8
3
34
BSAMP
DB7
4
33
VSAMP
DB6
5
32
LCLMP
DB5
6
31
AVDD1
DB4
7
30
AGND1
DB3
8
29
SGND
DB2
9
28
CAPN
DB1
10
27
CAPP
DB0
11
26
CREF
AVDD3
12
25
TEST2
AGND2
RED(+)
RED(-)
N/C
GRN(+)
19
20
21
22
23
24
TEST1
18
N/C
17
BLU(-)
16
N/C
15
BLU(+)
14
GRN(-)
13
AVDD2
XRD9816BCV
Note:
Pins 17,20 and 23 should be connected to AGND2 to improve noise immunity
Pin No.
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AVDD3
AVDD2
AGND2
RED(+)
Description
Data Output Bit 10
Data Output Bit9
Data Output Bit 8
Data Output Bit 7
Data Output Bit 6
Data Output Bit 5
Data Output Bit 4
Data Output Bit 3
Data Output Bit 2
Data Output Bit 1
Data Output Bit 0
Analog Power Supply
Analog Power Supply
Analog Ground (Substrate)
Red Positive Analog Input
Rev. 1.00
5
XRD9814B/9816B
Pin Configuration - XRD9816B
Pin No.
Name
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
46
45
47
48
RED(-)
N/C
GRN(+)
GRN(-)
N/C
BLU(+)
BLU(-)
N/C
TEST1
TEST2
CREF
CAPP
CAPN
SGND
AGND1
AVDD1
LCLMP
VSAMP
BSAMP
ADCCLK
INSEL
OUTSEL
OEB
LOAD
SDI
SCLK
DGND
DVDD
DB15
DB13
DB14
DB12
DB11
Description
Red Negative Analog Input
No Connect, (Note 5)
Green Positive Analog Input
Green Negative Analog Input
No Connect, (Note 5)
Blue Positive Analog Input
Blue Negative Analog Input
No Connect, (Note 5)
Internal Use Only
Internal Use Only
Decoupling Cap for CDS Reference
Decoupling Cap for Positive Reference
Decoupling Cap for Negative Reference
Substrate Gnd
Analog Ground (Substrate)
Analog Power Supply
Line Clamp Enable
Video Level Sampling Clock
Black Level Sampling Clock
A/D Converter Clock
Input Mode Select (Note 1)
Output Mode Select (Note 2)
Data Output Enable
Register Write Enable (Note 5)
Serial Data Input (Note 4)
Serial Shift Clock (Note 3)
Ground (Output Drivers and Internal Decode Logic)
Digital Power Supply (Output Drivers and Internal Decode Logic)
Data I/O Bit 15 (Note 4)
Data Output Bit 13
Data I/O Bit 14 (Note 3)
Data Output Bit 12
Data Output Bit 11
Note 1: INSEL=0 —> SCLK, SDI, and LOAD pins are active for serial programming; INSEL=1 —> SCLK and SDI
pins are inactive, and the serial programming is done through I/O pins DB14 and DB15 as described in
Notes 3~4 with LOAD tri-stating DB14 and DB15.
Note 2: OUTSEL=0 —> 16-bit parallel output mode select; OUTSEL=1 —> 8-bit nibble output mode select.
Note 3: For INSEL=1, DB14 becomes the SCLK input during serial programming.
Note 4: For INSEL=1, DB15 becomes the SDI input during serial programming.
Note 5: Pins 17, 20 and 23 may be connected to AGND2 to improve noise immunity.
Rev. 1.00
6
XRD9814B/9816B
ELECTRICAL CHARACTERISTICS
AVDD=DVDD=5.0V, ADCCLK=6MHz, Input Range = 2V, Ta=25oC unless otherwise specified
Parameter
Symbol
Min
Resolution
R
Resolution
R
Fc
6
Typ
Max
Unit
Conditions
14
BITS
XRD9814B
16
BITS
XRD9816B
A/D CONVERTER
Maximum Conversion Rate
8
MSPS
Differential Non-Linearity
DNL
+/-0.8
LSB
XRD9814B
Differential Non-Linearity
DNL
-0.95/+1.2
LSB
XRD9816B
Monotonicity
M
Yes
XRD9814B
Monotonicity
M
Yes
XRD9816B
Input Referred Offset
ZSE
40
mV
Offset Drift
ZSD
15
uV/oC
Input Referred Gain Error
FSE
+/- 2
% FS
Gain Error Drift
FSD
0.003
% FS oC
Input Voltage Range
2V Full-Scale Range
IVR
0
2.0
V
PB5=0, Config Reg #1
3V Full-Scale Range
IVR
0
3.0
V
PB5=1, Config Reg #1
INVSR
AGND
AVDD
V
Pixel Clamp,
INVSRB
0.5
AVDD-1
V
Line Clamp,
CDS - S/H SPECIFICATIONS
Input Voltage Range
Input Buffer Disabled
(Note 1)
Input Buffer Enabled
PB1=0, Config Reg #1
PB1=1, Config Reg #1
Input Bias Current
Input Buffer Disabled
IB
25
uA
(Note 2)
Input Buffer Enabled
Gain=1,
PB1=0, Config Reg #1
IBB
25
nA
TA=70o C,
PB1=1, Config Reg #1
150
250
Ω
Clamp Enabled
MΩ
Clamp Disabled
Input Switch On -Resistance
Ron
Input Switch Off -Resistance
Roff
100
CCD Input (Inverting)
Vclamp
4.0
4.2
4.4
V
PB2=0, Config Reg #1
S/H Input (Non-Inverting)
Vclamp
0.6
0.8
1.0
V
PB2=1, Config Reg #1
1000
Internal Voltage Clamp
Note 1: ADC digitizing range = (A/D Full-Scale Range/PGA Gain)
Note 2: Due to switch capacitor input.
Rev. 1.00
7
XRD9814B/9816B
ELECTRICAL CHARACTERISTICS (CONT’D)
AVDD=DVDD=5.0V, ADCCLK=6MHz, Ta=25C unless otherwise specified
Parameter
Symbol
Min
Typ
Max
Unit
Fine Offset Adjustment Min
OFR
-270
-300
-330
mV
Fine Offset Adjustment Max
OFR
+270
+300
+330
mV
Fine Offset Adjustment Step
OFRES
2.34
OFRL
+/-1.5%
Conditions
OFFSET SPECIFICATIONS
Fine Offset Adjustment
mV
8-Bit, 256 Settings
Linearity
Gross Offset Adjustment Min
OFGR
-360
-400
-440
mV
Gross Offset Adjustment Max
OFGR
+360
+200
+440
mV
Gross Offset Adjustment Step OFGRES
+200
mV
2-Bit, 4 Settings
V/V
-1 for PB2=0,
PGA SPECIFICATIONS
Gain Range Min
(Absolute Value)
GRAN
1.0
1.10
1.20
+1 for PB2=1, Config Reg #1
Gain Range Max
(Absolute Value)
GRAN
8.5
9.5
10.5
V/V
-10 for PB2=0,
+10 for PB2=1,
Config Reg#1
Gain Resolution
GRES
Gain DNL
0.0083
V/V
10-Bit 1024 Steps
+/-2.0
LSB
By design
SYSTEM SPECIFICATIONS (Includes CDS, PGA and A/D)
Differential Non-Linearity
Differential Non-Linearity
DNL
DNL
Integral Non-Linearity
INL
PGA Gain = -1.63
PGA Gain = -5.0
-0.9
-0.95
+/-0.8
-0.95/+1.2
+1.5
+2.0
LSB
LSB
XRD9814B, PGA Gain = 1
XRD9816B, PGA Gain = 1
+/-10.0
LSB
XRD9814B, PGA Gain = 1
IRNmin
+3.4
LSB
XRD9814B, 1-Channel CIS
IRNmax
+1.1
LSB
Input Referred Noise
Mode, 6MSPS, Low Gain
XRD9814B, 1-Channel CIS
Mode, 6MSPS, Low Gain
System Offset
PGA Gain= -1
IROmin
+70
mV
XRD9814B/9816B, 3-Channel
Mode, 6MSPS
PGA Gain= -10
IROmax
+70
mV
XRD9814B/9816B, 3-Channel
Mode, 6MSPS
Rev. 1.00
8
XRD9814B/9816B
ELECTRICAL CHARACTERISTICS (CONT’D)
AVDD=DVDD=5.0V, ADCCLK=6MHz, Ta=25C unless otherwise specified
Parameter
Symbol
Min
Typ
Max
Unit
ADCCLK Pulse Width
taclk
66.5
ns
BSAMP falling edge delay from
tbfcr
10
ns
tbvf
70
ns
ADCCLK Period (1 Ch. Mode)
tcp1
166
ns
ADCCLK Period (3 Ch. Mode)
tcp3
133
ns
Conditions
TIMING SPECIFICATIONS
rising ADCCLK
BSAMP falling edge to VSAMP
falling edge.
1-Channel Conversion Period
tcr1
166
ns
3-Channel Conversion Period
tcr3
400
ns
BSAMP Pulse Width
tpwb
30
ns
VSAMP Pulse Width
tpwv
30
ns
VSAMP falling edge to BSAMP
tvbf
70
ns
VSAMP falling edge delay from
rising ADCCLK.
tvfcr
30
ns
All modes except 1-Channel
S/H
VSAMP falling edge delay
tvfcr
70
ns
1-Channel S/H, Config
from rising ADCCLK
PGA Settling Time
tstl
70
ns
Aperture Delay
tap
falling edge.
REG #1, PB2=1, PB7=1
5
ns
VSAMP TIMING OPTION #1
VSAMP rising edge delay from
tvrcf
15
ns
falling ADCCLK (Note 1)
tvrcr is not required, Config
REG #1, PB0=0
VSAMP TIMING OPTION #2
VSAMP rising edge delay from
tvrcr
15
ns
rising ADCCLK (Note 1)
tvrcf is not required, Config
REG # 1, PB0=1
WRITE SPECIFICATIONS
Data Setup Time
tds
15
ns
Data Hold Time
tdh
15
ns
Load Setup Time
tlcs
15
ns
Load Hold Time
tlch
15
ns
Load Pulse Width
tplw
25
ns
Note 1: VSAMP Timing Option #2 allows additional timing flexibility by allowing the rising edge of VSAMP to occur
approximately one-half ADCCLK period earlier than Option #1. Option #2 is only available in 3-Channel
Operation (PB4=0, PB3=0, Configuration Register #1).
Rev. 1.00
9
XRD9814B/9816B
ELECTRICAL CHARACTERISTICS (CONT’D)
AVDD=DVDD=5.0V, ADCCLK=6MHz, Ta=25C unless otherwise specified
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
DATA READBACK SPECIFICATIONS
Address Access Time
taa (1)
15
ns
Output Enable Access Time
taoe (1)
15
ns
ADC DIGITAL OUTPUT SPECIFICATIONS
Output Delay
tod
20
ns
Tri-State to Data Valid
tlz
8
ns
Output Enable High to Tri-State
thz
8
ns
Latency RGB inputs
lat
7
ADCCLK
DIGITAL INPUTS
Input High Logic Level
VIH
Input Low Logic Level
VIL
High Level Input Current
IIH
80
20
% DVDD
DVDD=3-5V
% DVDD
DVDD=3-5V
5
uA
Low Level Input Current
IIL
5
uA
Input Capacitance
CIN
10
pF
DIGITAL OUTPUTS (DVDD=5V)
Output High Voltage
VOH
Output Low Voltage
VOL
Output Capacitance
COUT
4.2
0.4
10
V
IL=2ma
V
IL=-2ma
pF
DIGITAL OUTPUTS (DVDD=3.3V)
Output High Voltage
VOH
Output Low Voltage
VOL
Output Capacitance
COUT
2.8
0.3
10
V
IL=2ma
V
IL=-2ma
pF
POWER SUPPLY
Analog Power Supply
AVDD
4.5
Digital Power Supply
DVDD
3.0
Analog Supply Current
IDDA
110
mA
3CH CDS Mode
Digital Supply Current
IDDD
2
mA
Digital Output CLoad=30pF,
all pins.
Stand-By Mode Power
PDoff
65
5.0
5.5
5.0
5.5
80
V
V
mW
Note 1: Start of valid data depends on which timing becomes effective last, taoe or taa.
Rev. 1.00
10
XRD9814B/9816B
Function
Configuration Reg #1
Configuration Reg #2
Red Gain
Green Gain
Blue Gain
Red Offset
Green Offset
Blue Offset
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PB9-PB0
See Configuration Register #1
See Configuration Register #2
10-Bit Gain
10-Bit Gain
10-Bit Gain
2-Bit Gross Offset Adjustment: 8-Bit Fine Offset Adjustment
2-Bit Gross Offset Adjustment: 8-Bit Fine Offset Adjustment
2-Bit Gross Offset Adjustment: 8-Bit Fine Offset Adjustment
Table 1. XRD9814B/9816B Register Overview
A2 A1 A0
Address
0
0
0
Bit
Assignment
PB9 Single Channel
Power Save Mode
PB8 Digital Reset
PB7 PB6
Clamp Mode
PB5 A/D Full Scale Range
PB4 PB3
Color Select
PB2
Input Signal Polarity
PB1
Input Buffer Enable
PB9-PB0 Bit Definition
0
1
0
1
Unused channels are powered down to 0
save power (single channel mode only)
Unused channels are powered up
No Reset
Resets all registers to the default configuration
00
01
10
11
0
1
00
01
10
11
CDS pixel
CDS line clamp
No clamp
S/H line clamp
2Vpp Full Scale
3Vpp Full Scale (recommended for better performance)
RGB 3 channel color mode
Red single channel mode
Green single channel mode
Blue single channel mode
0
1
Inverted for CCD or negative going signals
Non-inverted for CIS or positive going signals
0
No buffer (DC coupled or AC coupled inputs
with pixel clamp mode
Buffer enabled (AC Coupled inputs for line clamp or no
clamp mode
1
PB0
VSAMP Timing
0
1
Timing option #1 (see Figure 3, 4, 7 & 8 for details)
Timing option #2 (see Figure 3, 4, 7 & 8 for details)
Table 2. Configuration Register #1 Definition (Default Configuration is 000H)
Rev. 1.00
11
XRD9814B/9816B
A2 A1 A0
Address
0
0
1
Bit
Assignment
PB9-PB0 Bit Definition
PB9
Not Used
0
1
Normal This register should be set to zero for normal operation
Do Not Use
PB8
0
Normal
Not Used
1
Do Not Use
PB7
0
Normal
Not Used
1
Do Not Use
PB6
0
Normal
Not Used
1
Do Not Use
PB5
0
Normal
Not Used
1
Do Not Use
PB4 PB3
00
AVDD-0.8V (4.2V for AVDD = 5V) (See Figures 11 & 12 for VClamp
Settings)
This register should be set to zero for normal operation
This register should be set to zero for normal operation
This register should be set to zero for normal operation
This register should be set to zero for normal operation
CDS Clamp Voltage 01
AVDD-1.3V (3.7V for AVDD = 5V)
(Black Level)
10
AVDD-1.8V (3.2V for AVDD = 5V)
11
AVDD-2.3V (2.7V for AVDD = 5V)
PB2
0
Normal
Not Used
1
Do Not Use
PB1
0
All circuits active
Stand-By Mode
1
Low power mode (75mW, requires 5uS back to normal operation)
PB0
0
A/D digital outputs
Read Back Mode
1
Read back mode (A2:A1:A0 select register data)
This register should be set to zero for normal operation
Table 3. Configuration Register #2 Definition (Default Configuration is 000H)
Rev. 1.00
12
XRD9814B/9816B
A2
A1
A0
Function
PB9
PB8
PB7
PB6
PB5
PB4
PB3
0
1
0
Red Gain
MSB
LSB
0
1
1
Green Gain
MSB
LSB
1
0
0
Blue Gain
MSB
LSB
1
0
1
Red Offset
PB9-PB8 gross adj
PB7-PB0 fine adj
00
01
10
11
0V
MSB
+200mV
-200mV
-400mV
LSB
1
1
0
Green Offset
PB9-PB8 gross adj
PB7-PB0 fine adj
00
01
10
11
0V
MSB
+200mV
-200mV
-400mV
LSB
1
1
1
Blue Offset
PB9-PB8 gross adj
PB7-PB0 fine adj
00
01
10
11
0V
MSB
+200mV
-200mV
-400mV
LSB
Table 4. Gain and Offset Registers (Default Configuration is 000H)
Rev. 1.00
13
PB2
PB1
PB0
XRD9814B/9816B
GENERAL DESCRIPTION
Clamp Mode
The XRD9814B/9816B contains all of the circuitry
required to create a complete 3-channel signal processor /digitizer for use in CCD/CIS imaging systems.
Each channel includes a correlated double sampler
(CDS), programmable gain amplifier (PGA) and channel offset adjustment. The input stage can also be
configured for use with inverting/non-inverting, AC or
DC coupled signals. In order to maximize flexibility, the
specific operating mode is programmable through two
configuration registers. In addition, the gain and offset
of each channel can be independently programmed
through separate gain and offset registers. Configuration register data is loaded serially through a 3-pin
serial interface. Specific details for register writes are
detailed below. After signal conditioning the three PGA
outputs are digitized by a 14-bit/16-bit A/D converter.
The clamp mode setting determines the conditions
when the internal clamp is enabled (see Table 5). The
pixel and CCD line-clamp modes are used to DCrestore AC coupled CCD input signals to the PGA
common-mode input voltage while using correlated
double sampling. S/H line mode should be used to DCrestore AC coupled inputs which do not utilize correlated double sampling and have only one control input
(VSAMP). No-clamp mode should be used for DC
coupled S/H inputs.
Pixel Mode (CCD with CDS)
The input clamp is active each pixel period with a
pulse-width determined by the Black- level Sampling
Input (BSAMP). The position of BSAMP can be optimized to eliminate the effects of the CCD reset pulse.
Since the input capacitor is recharged to the clamp
voltage on each pixel, common-mode droop errors are
eliminated.
Writing Registers Data
The XRD9814B/9816B utilizes eight 10-Bit registers to
store configuration, gain and offset information. Register data is written through the 3-pin serial interface
consisting of SDI (serial data input), SCLK (serial shift
clock) and LOAD (positive edge write enable). A write
consists of pulling LOAD low, shifting in 3 bits of
address (MSB first) and 10 bits of data (MSB first).
Data is written on the rising edge of SCLK and the last
13 bits are latched. The timing for writing to registers
is shown in Figure 17 and 18.
CCD Line Mode (CCD with CDS)
The input clamp is enabled only at the beginning of the
line by gating BSAMP with LCLMP. Gating with
LCLMP maintains the ability to position the clamp
pulse (BSAMP) away from the CCD reset for varying
LCLMP position and width. Since the input capacitor
is clamped only at the beginning of each line a larger
input capacitor is required to satisfy the common-mode
input requirements of the analog front-end. (See Coupling Capacitor Requirements.) The input buffer should
be enabled in this mode (PB1=1, Register #1).
When INSEL=0, SCLK, SDI, and LOAD pins are active
for serial programming.
S/H Line Mode (S/H with AC Coupling)
When INSEL=1, SCLK and SDI pins are inactive, and
the serial programming is done through I/O pins DB12/
DB14 and DB13/DB15 while LOAD pin is low.
The S/H Line mode clamp is used to DC-restore AC
coupled inputs which do not utilize CDS. VSAMP is
used to sample and hold the input signal and LCLMP
performs the clamp function. This differs from the CDS
line and pixel modes which use BSAMP to clamp to the
reference level and VSAMP to hold the video input. The
input buffer should be enabled in this mode (PB1=1,
Register #1).
Configuration Register #1
The bit assignment and definition for this register is
detailed in the Configuration Register #1 Definition
Table (Table 2). The primary purpose of this register is
to configure the analog input blocks for CCD or S/H
operation.
Rev. 1.00
14
XRD9814B/9816B
No-Clamp Mode (S/H with DC input)
Used for DC coupled inputs. AC coupled inputs must
be externally clamped to the proper common-mode
input voltage of the XRD9814B/9816B.
Note: Pixel clamp is the default clamp mode.
Clamp
Mode
Pixel
CDS Line
PB7
PB6
0
0
0
1
No Clamp
S/H Line
1
1
0
1
Clamp Enable
BSAMP
BSAMP LCLMP
Disabled
LCLMP
Table 5. Clamp Enable Definition
Clamp
Enable
BSAMP
LCLMP
PB6
PB7
Figure 2. Clamp Enable Logic
A/D Full-Scale Range
Signal Polarity
This bit sets the Full-Scale Range (FSR) of the A/D
converter to 2V or 3V. Use the 3V FSR for lowest
noise performance.
This bit configures the analog inputs for positive or
negative transitioning inputs. This is required to provide the correct signal polarity to the A/D input and to
set the correct input clamp level. The default configuration is set to inverting mode (CCD input).
Color Select
The color input corresponds to the signal input to be
digitized by the A/D converter. If set to RGB (default)
the A/D input is sequentially cycled through the red,
green and blue channels. The green channel is synchronized on the rising edge of the first ADCCLK after
the falling edge of VSAMP. If set in single-channel mode,
the A/D multiplexer will not sequence and the A/D converter input will be continually connected to the channel that is selected, RED, GRN or BLU.
Input Buffer Enable
This bit enables the input buffer to the PGA amplifier
and is required only for AC coupled inputs operating in
CDS line or S/H line clamp modes. Since this input
buffer reduces the input voltage range its use is not
recommended under DC or pixel-mode operation. The
input buffer is disabled in the default configuration.
Rev. 1.00
15
XRD9814B/9816B
VSAMP Timing
Reading Register Data
This allows the user to select one of two VSAMP timing
controls. Timing Option #2 allows the rising edge of
VSAMP to occur approximately one-half ADCCLK
earlier than Option #1. This does not affect internal
timing and is provided only to allow additional flexibility
in the external timing control. Timing Option #2 is
available only in the 3-channel mode of operation (See
timing diagrams Figure 3 and Figure 4).
In order to enter read-back mode, set configuration
register #2, PB0 to 1. Follow the write timing in Figures
17 and 18.
In order to read a specific register, shift in 3-bits of
register address data (MSB first), followed by 10
dummy data bits. In the case of reading back configuration register #2, PB0 has to stay 1 and cannot be a
dummy.
Configuration Register #2
Read-Back Registers and Address
The bit assignment and definition for this register is
detailed in the Configuration Register #2 Definition
Table. A diagnostic read-back mode allows gain,
offset and configuration data to be output as the 8 or 10
MSBs on the digital output bus depending on the
selection of OUTSEL (see Reading Register Data
session for details). Additional bits are used to enable
a low-power stand-by state and manufacturing test
mode.
Address
Data
Register
001 XXXXXXXXXX
001 XXXXXXXXX1
Cfig1
Cfig2
010 XXXXXXXXXX
Red Gain
011 XXXXXXXXXX
Grn Gain
100 XXXXXXXXXX
Blu Gain
101 XXXXXXXXXX
Red Offset
110 XXXXXXXXXX
111 XXXXXXXXXX
Grn Offset
Blu Offset
Digital Reset
In order to exit read-back mode perform a write to
configuration register 2, PB0=0.
Setting this bit to one resets all registers to all zeros.
Test Mode
(OUTSEL = 0) In read-back mode the A/D output is
bypassed and internal register data is output to the 10
most significant bits of the data output bus. The
remaining LSB bits should be ignored. Register data
will be valid after the load pin goes high.
This is a reserved bit for testing and must be set to 0
in all writes to Configuration Register #2.
Stand-By Mode
(OUTSEL = 1) In nibble mode, the output bus is limited
to 8-bits. Therefore, in read-back mode, the 8 MSBs
are valid when ADCCLK is high, and the 2 LSBs are
valid when ADCCLK is low. Configuring and exiting the
read-back mode is done in the same manner of
OUTSEL = 0.
Setting this bit to one forces the circuit into a low-power
standby mode. Configuration, offset and gain registers
remain unchanged in stand-by mode. Pull OEB High
to set DB<15:0> to high impedance during stand-by
mode.
Read Back Mode
Important: The entire byte of register #2 is re-written when
exiting the readback mode. If any bits of configuration
register #2 were programmed prior to entering the readback mode, they must be re-programmed when exiting
read-back. See Figure 19 for read-back timing.
This is a special diagnostic mode which can aid in the
debugging of new system designs. Setting this bit to 1
allows all configuration, gain and offset register contents to be output on the data output bus (explained
below).
PGA Gain Settings
The gain for each color input is individually programmable from 1 to 10 in 1024 linear steps.
Rev. 1.00
16
XRD9814B/9816B
The fine offset correction for each channel is programmable from -300mV to +300mV.
 Code 
PGA Gain = 
 ⋅ 9. 0 + 1
 1024 
Fine Channel Offset = PB 7
where Code represents the binary contents of the 10bit gain setting register.
Channel Offset Adjustment
PB7=1 equals -1
PB7=0 equals +1
Code = (PB6:PB0) of the 10-bit offset register.
The gross offset correction for each channel is
progammable from -400mV to +200mV. It is adjusted
by toggling PB9 and PB8 of Offset Registers (Table 4).
10-Bit
 ( Code ) 
⋅ 
 ⋅ 300mV
 128 
XRD9814B/16B
Vout
Differential
Input
CDS
3:1
MUX
2-Bit
8-Bit
Offset Block
Programmable Serial Port
14-Bit
PGA
8-Bit Offset DAC
Fine Adjust
2-Bit Offset
Variable Capacitive Divider
Gross Adjust
Block Diagram of the Fine and Gross Offset Adjustment DAC
Theory ofRev.
Operation
1.00
17
ADC
XRD9814B/9816B
(Correlated Double Sampling)
3-Channel CDS Mode
Correlated double sampling is a technique used to level
shift and acquire CCD output signals whose information is equal to the difference between consecutive
reference (black) and signal (video) samples. The CDS
process consists of three steps:
This mode allows simultaneous CDS of the red, green
and blue inputs . Black-level sampling occurs on each
pixel and is equal to the width of the BSAMP sampling
input. The black level is held on the falling edge of
BSAMP and the PGA will immediately begin to track
the signal input until the falling edge of VSAMP.
1) Sampling and holding the reference black level.
2) Sampling the video level.
3) Subtracting the two samples to extract the video
information.
Two VSAMP timing modes are supported to allow
additional flexibility in the VSAMP pulse width (see
timing diagrams). At the end of the video sampling
phase the difference between the reference and video
levels is inverted, amplified and offset depending on
the contents of the PGA gain and offset registers. The
RGB channels are then sequentially converted by a
high speed A/D converter. A/D converter data appears
on the data output bus after 7 ADCCLK cycles. The
green channel is synchronized on the rising edge of the
first ADCCLK after the falling edge of VSAMP. The
power-up default mode is for CDS sampling a CCD
input (Pixel Clamp, Inverting Input, No Input Buffer).
Once the video information has been extracted it can
be processed further through amplification and/or offset adjustment. Since system noise is also stored and
subtracted during the CDS process, signals with bandwidths less than half the sampling frequency will be
substantially attenuated.
In order to reject higher frequency power supply noise
which is not attenuated near the sampling frequency
the XRD9814B/9816B utilizes a fully differential input
structure.
1-Channel CDS Mode
The 1-Channel CDS mode allows high-speed acquisition and processing of a single channel. The timing,
clamp and buffer configurations are similar to the 3channel mode described previously. To select a single
channel input the color bits of configuration register 1
must be set to the appropriate value. The A/D input will
begin to track the selected color input on the next
positive edge of ADCCLK. If the configuration is
toggled from single color to 3-channel mode RGB
scanning will not occur until the circuit is
resynchronized on the falling edge of VSAMP.
Since the CDS process uses AC coupled inputs the
coupling capacitor must be charged to the commonmode range of the analog front-end. This can be
accomplished by clamping the coupling capacitor to
the internal clamp voltage when the CCD is at a
reference level. This clamp may occur during each
pixel (Pixel Clamp), or at the beginning of each line
(CDS Line Clamp). If CDS Line Clamp mode is used the
input buffer (configuration register #1, PB1) must be
enabled to eliminate the effects of input bias current.
If Pixel mode is selected the input buffer is not required
or recommended.
Rev. 1.00
18
XRD9814B/9816B
3-Channel CIS/Sample and Hold Mode
Power Supplies and Digital I/O
The XRD9814B/9816B also supports operation for
Contact Image Sensor (CIS) and S/H applications. The
green channel is synchronized on the rising edge of the
first ADCCLK after the falling edge of VSAMP.
The XRD9814B/9816B utilizes separate analog and
digital power supplies. All digital I/O pins are 3V/5V
compatible and allow easy interfacing to external
digital ASICs. For single supply systems the analog
and digital supply pins can be separately connected
and bypassed to reduce noise coupling from digital to
analog circuits.
For DC coupled inputs the reference clamp and input
buffer should be disabled and input polarity should be
set to 1 (non-inverting). In this mode of operation the
BSAMP input is connected to DGND and input sampling occurs on the falling edge of VSAMP.
Coupling Capacitor Requirements
The size of the external coupling capacitors depends
on a number of items including the clamp mode, pixel
rate, channel gain, black-level variation and system
accuracy requirements. The major limitation for each
clamp mode is shown below:
When using AC coupled inputs the coupling capacitor
must be clamped to the required common-mode input
voltage when the signal source output is at a reference
level. This can be accomplished by enabling the S/H
Line clamp mode in configuration register 1 and clamping the input capacitor to the internal clamp voltage at
the beginning of each line via the LCLMP input. The
required width of the LCLMP signal is dependent on the
value of the coupling capacitor, XRD9814B/9816B
clamp resistance, source output resistance and desired accuracy. This is explained further in Coupling
Capacitor Requirements. If AC coupling is used the
input buffer (configuration register 1) must be enabled
to eliminate input-bias current errors inherent to the
sampling process. The input buffer is not required or
recommended in DC coupled applications.
CDS Mode
S/H Mode
Pixel Clamp
Black level
Not Applicable
(Buffer
pixel-pixel
Disabled)
variation
Initial charging
1-Channel CIS/ Sample and Hold Mode
Line Clamp
Initial charging
(Buffer
Capacitor droop
Enabled)
(common-mode
range)
Initial charging
Capacitor droop
range)
(accuracy error)
The 1-channel CIS S/H mode allows high-speed
acquisition and processing of a single channel. The
timing, clamp and buffer configurations are similar to
the 3-channel mode with the exception that VSAMP
timing option #2 is not supported. To select a single
channel input the color bits of configuration register 1
must be set to the appropriate value. The A/D input will
begin to track the selected color input on the next
positive edge of ADCCLK. If the configuration is
toggled from single color to 3-channel mode, RGB
scanning will not occur until the circuit is
resynchronized.
Table 5. Coupling Capacitor Limitation
Rev. 1.00
19
XRD9814B/9816B
Assuming that Vr=5V, Vc=4V, Vε=12.5uV, Rc=100Ω,
Maximum Capacitance (CDS Pixel Mode)
Rs=50Ω, tpwb=65ns and N=10 the maximum allowable input capacitor is equal to 384pF. In this case the
input capacitance is limited by pixel-pixel changes in
the black level (first calculation).
Limitation #1
Since the black level is clamped during each pixel
period the input bias current contributes an insignificant amount of droop during one pixel period. However,
pixel-pixel variations in the black level may appear as
errors . For a worst case gain of -10, 2V A/D FSR and
14-bit accuracy, one lsb of error corresponds to
12.5uV input-referred. Assuming 1mV of pixel-pixel
variation in the black level, the maximumcoupling
capacitor can be determined as a function of the
clamping period and internal clamp resistance.
The minimum coupling capacitance is limited by parasitic effects including pin and board capacitance. A
minimum value of 68pF is recommended.
Maximum Capacitance (CDS Line Mode)
Since the coupling capacitor is charged only at the
beginning of each line and not clamped at each pixel,
the pixel-pixel variation in the black level has no effect
on the capacitor size. The maximum size will be limited
by the number of clamp pulses, clamp pulse-width and
number of lines allowed to charge to a given accuracy.
tpwb
=
C max
Minimum Capacitance (CDS Pixel Mode)
 1 mV 

 12.5 µ V 
( Rc + Rs ) ⋅ ln 
where tpwb=clamp pulse width (BSAMP)
Rc=Clamp resistance
Rs=Signal source-resistance
C max =
For typical values of tpwb=65ns, Rc=100Ω, Rs=50Ω,
CMAX ≤100pF.
where tpwb
N
Rc
Rs
Vr
Vc
Vε
Limitation #2
The maximum input capacitance may also be limited
by the time allowed to charge the input capacitor to the
difference between the black level and clamp levels.
The capacitor value can be related to the number of
clamp pulses allowed before the capacitor voltage
settles to within the desired accuracy.
C max
where tpwb
N
Rc
Rs
Vr
Vc
Vε
=
=
=
=
=
=
=
=
tpwb ⋅ N
( Rc + Rs ) ⋅ ln 
Vr
=
=
=
=
=
=
=
N ⋅ L ⋅ tpwb
 Vr − Vc 
( Rc + Rs ) ⋅ ln 

 Vε 
clamp pulse width (BSAMP)
number of pixels allowed to settle
clamp resistance
signal source-resistance
black level
XRD9814B/9816B clamp voltage
error voltage
Assuming that Vr=5V, Vc=4V, Ve=12.5uV, Rc=100Ω,
Rs=500Ω, tpwb=65ns and N=10, the maximum allowable input capacitor is equal to 767pF.
If it is desired to settle within one line (L=1) for a given
capacitor value, the number of clamp pulses or the
clamp pulse-width must be increased using the above
equation.
− Vc 

Vε 
clamp pulse width (BSAMP)
number of pixels allowed to settle
clamp resistance
signal source-resistance
black level
XRD9814B/9816B clamp voltage
error voltage
Rev. 1.00
20
XRD9814B/9816B
Minimum Capacitance (CDS Line Mode)
Maximum Capacitance (S/H Line Mode)
In general, the minimum value coupling capacitance is
limited by the amount of droop which can occur before
the input voltage range of the input amplifier is exceeded. The input capacitor droop is related to the
input bias current by:
The maximum capacitance is determined by the
amount of time allowed to charge the coupling capacitor. In order to minimize the charging time, the maximum capacitor can be set to the minimum value as
previously calculated. In this case the time required to
charge the capacitor is:
Vdroop =
Ibias ⋅ n ⋅ T
C
t
where Ibias = input bias current
n = number of pixels per line
T = pixel period
where t
Rc
Rs
Vr
Vc
Vε
Cmin
If the minimum input voltage is allowed to equal the 0V
input voltage of the XRD9814B/9816B, the maximum
allowable droop will be equal to the clamp level minus
the difference between the black and video levels. For
example, if Vc=4V, and the CCD video output is -2V
relative to the black level the maximum allowable
droop is equal to 2V.
10 nA ⋅ 3000 ⋅ 500 ns
= 7.5pF
2V
Note: These are the absolute minimum capacitor requirements. As stated for pixel-mode, a minimum value of 68pF
is recommended.
Minimum Capacitance (S/H Line Mode)
Unlike Line or Pixel CDS modes voltage droop across
a line appears as an absolute error and is the dominant
factor in determining the minimum coupling capacitor
size.
C min =
=
=
=
=
=
=
=
clamp pulse - width ( SYNCH )
clamp resistance
signal source - resistance
input reference level
XRD9814B/9816B clamp voltage
error voltage
coupling capacitor
Assuming that Vr=.5 Vc=0V, Vε=12.5uV, Rc=100Ω,
Rs=500Ω and C=1.2uF, the minimum clamp period is
equal to 1.9mS.
Using the previous equation and assuming T=500ns,
n=3000
C min =
Vr − Vc 
= ( Rs + Rc ) ⋅ C min ⋅ ln 

 Vε 
Ibias ⋅ n ⋅ T
Vε
where Ibias=input bias current
n=number of pixels per line
Assuming n=3000, T=500nS, I=10nA and Ve=12.5uV,
the minimum required capacitor is 1.2uF.
Rev. 1.00
21
XRD9814B/9816B
X
tap
CCDIN
X
tcp3
taclk
taclk
ADCCLK
tvfcr
BSAMP
tvrcr(2)
tpwb
tvrcf(1)
VSAMP
tbvf
tpwv
tvbf
tstl
tcr3
Clamp
(Internal to XRD9814B/XRD9816B)
Notes: (1) VSAMP Timing Option #1 uses tvrcf (tvrcr is not required)
(2) VSAMP Timing Option #2 uses tvrcr (tvrcf is not required)
VSAMP Timing Option #2 only available in 3-Channel Operation
Figure 3. 3-Channel CDS Mode - Pixel Clamp
Configuration Register #1:
Pixel Clamp (PB7=0, PB6=0)
RGB (PB4=0, PB3=0)
Inverted Polarity (PB2=0)
Input Buffer Disabled (PB1=0)
Rev. 1.00
22
XRD9814B/9816B
tap
CCDIN
LCLMP
tcp3
taclk
taclk
ADCCLK
tvfcr
BSAMP
tvrcr(2)
tvrcf(1)
tvbf
tpwb
VSAMP
tbvf
tpwv
tstl
tcr3
Clamp
(Internal to XRD9814B/XRD9816B)
Notes: (1) VSAMP Timing Option #1 uses tvrcf (tvrcr is not required)
(2) VSAMP Timing Option #2 uses tvrcr (tvrcf is not required)
VSAMP Timing Option #2 only available in 3-Channel Operation
Figure 4. 3-Channel CDS Mode - Line Clamp
Configuration Register #1: CDS Line (PB7=0, PB6=1)
RGB (PB4=0, PB3=0)
Inverted Polarity (PB2=0)
Input Buffer Enabled (PB1=1)
Rev. 1.00
23
XRD9814B/9816B
tap
CCDIN
tcp1
taclk
taclk
ADCCLK
tstl
tbfcr
tvfcr
BSAMP
tpwb
VSAMP
tcr1
tpwv
tvbf
tbvf
Clamp
(Internal to XRD9814B/XRD9816B)
Figure 5. 1-Channel CDS Mode - Pixel Clamp
Configuration Register #1: Pixel Clamp (PB7=0, PB6=0)
Single Channel (PB4, PB3-RED 01, GRN 10, BLU 11)
Inverted Polarity (PB2=0)
Input Buffer Disabled (PB1=0)
Rev. 1.00
24
XRD9814B/9816B
tap
CCDIN
tcp1
LCLMP
taclk
taclk
ADCCLK
tstl
tvfcr
tbfcr
BSAMP
tpwb
VSAMP
tcr1
tpwv
tvbf
tbvf
Clamp
(Internal to XRD9814B/XRD9816B)
Notes: (1) Only VSAMP timing option #1 is supported in 1-channel mode
Figure 6. 1-Channel CDS Mode - Line Clamp
Configuration Register #1: CDS Line Clamp (PB7=0, PB6=1)
Single Channel (PB4, PB3-RED 01, GRN 10, BLU 11)
Inverted Polarity (PB2=0)
Input Buffer Enabled (PB1=1)
Rev. 1.00
25
XRD9814B/9816B
tap
CIS
LCLMP
tcp3
taclk
tvfcr
taclk
ADCCLK
tvrcf(1)
tvrcr(2)
VSAMP
tstl
tcr3
tpwv
Clamp
(Internal to XRD9814B/XRD9816B)
Figure 7. 3-Channel S/H Mode - Line Clamp (AC Coupled)
Configuration Register #1: S/H Line Clamp (PB7=1, PB6=1)
RGB (PB4=0, PB3=0)
Non-Inverted Polarity (PB2=1)
Input Buffer Enabled (PB1=1)
Rev. 1.00
26
XRD9814B/9816B
tap
CIS
tcp3
taclk
tvfcr
taclk
ADCCLK
tvrcf(1)
tvrcr(2)
VSAMP
tstl
tcr3
tpwv
Clamp
(Internal to XRD9814B/XRD9816B)
Notes: (1) VSAMP Timing option #1 uses tvrcf (tvrcr is not required)
(2) VSAMP Timing option #2 uses tvrcr (tvrcf is not required)
Figure 8. 3-Channel S/H Mode - No Clamp (DC Coupled)
Configuration Register #1: S/H No Clamp (PB7=1, PB6=0)
RGB (PB4=0, PB3=0)
Non-Inverted Polarity (PB2=1)
Input Buffer Disabled (PB1=0)
Rev. 1.00
27
XRD9814B/9816B
tap
CIS
LCLMP
tcp1
taclk
taclk
ADCCLK
tstl
tvfcr
VSAMP
tvrcf(1)
tpwv
tcr1
Clamp
(Internal to XRD9814B/XRD9816B)
Figure 9. 1-Channel S/H Mode - Line Clamp (AC Coupled)
Configuration Register #1: S/H Line Clamp (PB7=1, PB6=1)
Single Channel (PB4, PB3-RED 01, GRN 10, BLU 11)
Non-Inverted Polarity (PB2=1)
Input Buffer Enabled (PB1=1)
Rev. 1.00
28
XRD9814B/9816B
tap
CIS
tcp1
taclk
taclk
ADCCLK
tstl
tvfcr
VSAMP
tvrcf(1)
tpwv
tcr1
Clamp
(Internal to XRD9814B/XRD9816B)
Notes: (1) Only VSAMP timing option #1 is supported in 1-channel mode
Figure 10. 1-Channel S/H Mode - No Clamp (DC Coupled)
Configuration Register #1: S/H No Clamp (PB7=1, PB6=0)
Single Channel (PB4, PB3-RED 01, GRN 10, BLU 11)
Non-Inverted Polarity (PB2=1)
Input Buffer Disabled (PB1=0)
Rev. 1.00
29
XRD9814B/9816B
5.0 V
4.7 V
0.5V
VCLAMP=4.2 V
2.0V
Reset
Black Pixel
Video Pixel
Ground
Typical Operation, VCLAMP = 4.2V, (PB4 = 0, PB3 = 0)
VRESET = 0.5V, V VIDEO = 2.0V = FSR of XRD9814B/9816B
Figure 11. VCLAMP Setting Example 1
5.2 V
5.0 V
2.0V
VCLAMP=3.2 V
3.0V
Reset
Ground
Black Pixel
Video Pixel
Marginal Operation, V CLAMP = 3.2V, (PB4 = 1, PB3 = 0)
VRESET = 2.0V, V VIDEO = 3.0V = FSR of XRD9814B/9816B
Notes (3) Input signal does not exceed VDD + 0.3V (Reset)
Notes (4) Input signal does not go below 0V (Video pixel)
Figure 12. VCLAMP Setting Example 2
Rev. 1.00
30
XRD9814B/9816B
Pixel (n)
Pixel (n+1)
Pixel (n+2)
Pixel (n+4)
Pixel (n+3)
CCDOUT
(Parallel RGB)
7 ADCCLK Latency
ADCCLK
BSAMP
ADC Samples Green
Grn Pixel (n+1)
Red Pixel (n+1)
Blu Pixel (n)
Grn Pixel (n)
Red Pixel (n)
VSAMP
Figure 13. 3-Channel CDS Pixel Clamp Synchronization and ADC Latency Timing
Pixel (n)
Pixel (n+1)
Pixel (n+2)
Pixel (n+3)
Pixel (n+4)
Pixel (n+5) Pixel (n+6) Pixel (n+7)
Pixel (n+8)
CCDOUT
(Green Input)
7 ADCCLK Latency
ADCCLK
BSAMP
Figure 14. 1-Channel CDS Pixel Clamp Synchronization and ADC Latency Timing
Rev. 1.00
31
Grn Pixel (n+1)
Grn Pixel (n)
Grn Pixel (n-1)
Grn Pixel (n-2)
Grn Pixel (n-3)
VSAMP
XRD9814B/9816B
Pixel (n)
Pixel (n+1)
Pixel (n+2)
Pixel (n+4)
Pixel (n+3)
CISOUT
(Parallel RGB)
7 ADCCLK Latency
ADCCLK
ADC Samples Green
Grn Pixel (n+1)
Red Pixel (n+1)
Blu Pixel (n)
Grn Pixel (n)
Red Pixel (n)
VSAMP
Figure 15. 3-Channel S/H Synchronization and ADC Latency Timing
Pixel (n)
Pixel (n+1)
Pixel (n+2)
Pixel (n+3)
Pixel (n+4)
Pixel (n+5) Pixel (n+6) Pixel (n+7)
Pixel (n+8)
CISOUT
(Green Input)
7 ADCCLK Latency
ADCCLK
Figure 16. 1-Channel S/H Synchronization and ADC Latency Timing
Rev. 1.00
32
Grn Pixel (n+1)
Grn Pixel (n)
Grn Pixel (n-1)
Grn Pixel (n-2)
Grn Pixel (n-3)
VSAMP
XRD9814B/9816B
13 Data Bits
SCLK
(Pin 41)
tds
SDI
A2
tdh
A1
PB9
A0
PB8
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
(Pin 40)
tlcs
tlch
LOAD
(Pin 39)
tplw
Rising edge loads last 13
Data bits
Figure 17. Write Timing (INSEL = 0)
13 Data Bits
SCLK/
DB12/DB14
(Pin 45)
tds
tdh
SDI/
DB13/DB15
A2
A1
A0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
(Pin 44)
tlcs
tlch
tlch
LOAD
tplw
(Pin 39)
Rising edge loads last 13
Data bits
Figure 18. Write Timing (INSEL = 1)
Rev. 1.00
33
XRD9814B/9816B
XRD9814B/9816B Read Back Timing
LOAD
SCLK
Enables Read-back
SDI
Output
(DBx)
001XXXXXXXXX1
Disables Read-back
000XXXXXXXXXX
Cfig2
ADC Output Data
Not Valid
Reg data
Write to Cfig2, bit0 to
enable readback &
Address Cfig2
for register
read-back
Read-back
Cfig2 data
001XXXXXXXXX0
Cfig1
Not Valid
ADC Output Data
Reg data
Address Cfig1
for register
read-back
Read-back
Cfig1 data
This step can be repeated for all
registers before exiting to normal
mode
Write to Cfig2 bit0 to
enable ADC output data
& disable read-back
mode
Note: If any bits of Cfig2 were
programmed prior to readback mode,
they must be re-programmed when
exiting read-back
Figure 19. XRD9814B/9816B Read-Back Timing
Rev. 1.00
34
XRD9814B/9816B
OEB
N+1
N
ADCCLK
tod
DB13:0/
TRI-STATE
DB15:0
thz
DB13/15:DB0 (N-7)
TRI-STATE
DB13/15:0 (N-6)
tlz
LOAD = HI
LOAD
Figure 20. ADC Digital Output Timing (OUTSEL = 0)
OEB
N
N+1
ADCCLK
tod
thz
tod
DB13:0/
DB15:0
TRI-STATE
N-8
(LSB 6/8-BITS)
N-7
(MSB 8-BITS)
N-7
(LSB 6/8-BITS)
High Bits
Low Bits
N-6
(MSB 8-BITS)
tlz
LOAD = HI
LOAD
Figure 21. ADC Digital Output Timing (OUTSEL = 1)
Rev. 1.00
35
TRI-STATE
XRD9814B/9816B
tap
CCD
tstl
N-1
N
N+2
N+1
N+3
VSAMP
ADCCLK
1
ADCOUT
2
3
4
5
6
7
Non Valid Data
8
10
9
11
12
13
14
Dummy
GRN
BLU
RED
GRN
BLU
N-1
N-1
N-1
N
N
N
7 ADCCLK Latency
Figure 22. XRD9814B/XRD9816B Pipeline Latency
ADCCLK/SYNCHRONIZATION EVENTS
1
Necessary / No Sampling Events Occur
2
Beginning of Synchronization / Samples Green (N-1) / Converts Unkown Dummy Value
3
Samples Blue (N-1) / Converts Green (N-1)
4
Samples Red (N) / Converts Blue (N-1)
5
Synchronization / Samples Green (N) / Converts Red (N)
6
Samples Blue (N) / Converts Green (N)
7
Samples Red (N+1) / Converts Blue (N)
8
Synchronization / Samples Green (N+1) / Converts Red (N+1)
9
Dummy Pixel (N-1) Valid Generated From ADCCLK #2
10
GRN Pixel (N-1) Valid Generated From ADCCLK #3
11
BLU Pixel (N-1) Valid Generated From ADCCLK #4
12
RED Pixel (N) Valid Generated From ADCCLK #5
13
GRN Pixel (N) Valid Generated From ADCCLK #6
14
BLU Pixel (N) Valid Generated From ADCCLK #7
Note: Green Channel is Synchronized on the First Rising Edge of ADCCLK After the Falling Edge of VSAMP
Rev. 1.00
36
XRD9814B/9816B
Application Notes
Avdd
Dvdd
c1
c2
c3
c4
c1=c3=0.1uF
c2=c4=0.01uF
C
C
D
/
C
I
S
Red(+)
Red(-)
Ext Serial Load
Grn(+)
Grn(-)
No Connect
No Connect
Data 14/16 - 8 Bit
Databus (ASIC)
No Connect
No Connect
D
v
d
d
A
v
d
d
XRD9814B/XRD9816B
Control Signals
Blu(+)
Blu(-)
c
r
e
f
c
a
p
n
c
a
p
p
D
g
n
d
A
g
n
d
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
Figure 23. Single Channel DC-Coupled Mode
Avdd
Dvdd
c1
c2
c3
c4
c1=c3=0.1uF
c2=c4=0.01uF
100pF
Red(+)
Red(-)
A
v
d
d
Data 14/16- 8 Bit
Ext Serial Load
Grn(+)
Grn(-)
XRD9814B/XRD9816B
100pF
No Connect
No Connect
Control Signals
Blu(+)
Blu(-)
c
r
e
f
c
a
p
p
c
a
p
n
A
g
n
d
D
g
n
d
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
Figure 24. Single Channel AC-Coupled Mode
Rev. 1.00
37
Databus (ASIC)
C
C
D
/
C
I
S
No Connect
No Connect
D
v
d
d
XRD9814B/9816B
Dvdd
Avdd
c1
c2
c3
c4
c1=c3=0.1uF
c2=c4=0.01uF
Data 14/16-8 Bit
Ext Serial Load
Grn(+)
Grn(-)
Control Signals
XRD9814B/XRD9816B
Blu(+)
Blu(-)
c
r
e
f
c
a
p
n
c
a
p
p
A
g
n
d
Databus (ASIC)
Red(+)
Red(-)
C
C
D
/
C
I
S
D
v
d
d
A
v
d
d
D
g
n
d
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
Figure 25. Triple Channel DC-Coupled Mode
Avdd
Dvdd
c1
c2
c3
c4
c1=c3=0.1uF
c2=c4=0.01uF
100pF
A
v
d
d
100pF
Red(+)
Red(-)
100pF
Data 14/16-8 Bit
Ext Serial Load
Grn(+)
Grn(-)
100pF
XRD9814B/XRD9816B
Control Signals
Blu(+)
Blu(-)
100pF
100pF
c
a
p
n
c
a
p
p
c
r
e
f
A
g
n
d
D
g
n
d
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
Figure 26. Triple Channel AC-Coupled Mode
Rev. 1.00
38
Databus (ASIC)
C
C
D
/
C
I
S
D
v
d
d
XRD9814B/9816B
INSEL/OUTSEL Data Output Format
XRD9814B/9816B. The XRD9814B/9816B supports
14/16-bit parallel and 8-bit nibble output modes. When
OUTSEL is low, the output bus is standard 14/16-bit
parallel (Figure 20). To use the 8-bit nibble output
mode, OUTSEL must be set high (Figure 21). In either
14/16-bit or 8-bit nibble applications, the output bus is
tri-stated when the bi-directional serial load signal is
pulled low.
There are two control signals for setting the output data
format and the serial load control. INSEL is used to
select the mode for programming the serial port. To
use the external pins sdi, sclk and load, INSEL must
be low (Figure 17). When INSEL is set to high, DB13/
sdi and DB12/sclk become inputs through the bidirectional output bus to load the internal control
registers (Figure 18). The load pin is still used to latch
the data. This helps to reduce the pin count requirements for the ASIC that drives the XRD9814B/9816B.
OUTSEL is used to select the output data format of the
DB13/DB15
DB12/DB14
14/16-Bit Parallel
Digital
ASIC
XRD9814B/
DB0
XRD9816B
sdi
sclk
load
Insel
Outsel
External Serial Load
Insel=0, Outsel=0
Figure 27. 14/16-Bit Output (OUTSEL=0), External Serial Load (INSEL=0)
DB13/DB15/sdi
DB12/DB14/sclk
14/16-Bit Parallel
Bi-Directional Serial
Load
Digital
ASIC
XRD9814B /
DB0
XRD9816B
sdi
sclk
load
Insel
Outsel
No Connect
No Connect
Insel=1, Outsel=0
Figure 28. 14/16-Bit Output (OUTSEL=0), Bi-Directional Serial Load (INSEL=1)
Rev. 1.00
39
XRD9814B/9816B
8-Bit Nibble
DB13/DB15
DB12/DB14
Digital
ASIC
XRD9814B /
DB6/DB8
XRD9816B
External Serial Load
sdi
sclk
load
Insel=0, Outsel=1
Insel
Outsel
Figure 29. 8-Bit Nibble Output (OUTSEL=1), External Serial Load (INSEL=0)
8-Bit Nibble
Bi-Directional Serial
Load
DB13/DB15/sdi
DB12/DB14/sclk
Digital
ASIC
XRD9814B /
DB6/DB8
XRD9816B
sdi
sclk
load
No Connect
No Connect
Insel=1, Outsel=1
Insel
Outsel
Figure 30. 8-Bit Nibble Output (OUTSEL=1), Bi-Directional Serial Load (INSEL=1)
Rev. 1.00
40
XRD9814B/9816B
XRD9814B 1 Channel CIS No Clamp, AVDD = DVDD = 5V, Fs = 6MSPS, 2V Reference
DNL PLOT
1.5
1
0
-0.5
-1
Codes
Graph 1. XRD9814B 1-Channel CIS S/H No Clamp DNL Plot
Rev. 1.00
41
16169
15732
15295
14858
14421
13984
13547
13110
12673
12236
11799
11362
10925
10488
9614
10051
9177
8740
8303
7866
7429
6992
6555
6118
5681
5244
4807
4370
3933
3496
3059
2622
2185
1748
874
1311
0
-1.5
437
LSB
0.5
XRD9814B/9816B
XRD9814B 1-Channel CDS Pixel Clamp, AVDD = DVDD = 5V, Fs = 6MSPS, 2V Reference, DNL Plot
0.6
0.4
0
-0.2
-0.4
Codes
Graph 2. XRD9814B 1-Channel CDS Pixel Clamp DNL Plot
Rev. 1.00
42
16169
15732
15295
14858
14421
13984
13547
13110
12673
12236
11799
11362
10925
10488
9614
10051
9177
8740
8303
7866
7429
6992
6555
6118
5681
5244
4807
4370
3933
3496
3059
2622
2185
1748
874
1311
0
-0.6
437
LSB
0.2
XRD9814B/9816B
XRD9814B 3-Channel CDS Pixel Clamp, AVDD = DVDD = 5V, Fs = 6MSPS, 2V Reference, DNL Plot
0.8
0.6
0.4
0
-0.2
-0.4
-0.6
Code
Graph 3. XRD9814B 3-Channel CDS Pixel Clamp DNL Plot
Rev. 1.00
43
16200
15795
15390
14985
14580
14175
13770
13365
12960
12555
12150
11745
11340
10935
10530
9720
10125
9315
8910
8505
8100
7695
7290
6885
6480
6075
5670
5265
4860
4455
4050
3645
3240
2835
2430
2025
1620
810
1215
0
-0.8
405
LSB
0.2
XRD9814B/9816B
XRD9814B 1CH DC CIS Input Referred Noise vs. Gain of 1.63 to 5 V/V
ADCCLK = 1MSPS, ADC Input Range = 3Vpp, AVDD = 5V, DVDD = 3V
3
2.5
RMS Noise (LSB)
2
1.5
1
0.5
0
1.63
2.75
3.88
5
Gain
Graph 4. XRD9814B 1-Channel CIS S/H No Clamp Input Referred Noise vs. Gain (1 MSPS)
Rev. 1.00
44
XRD9814B/9816B
XRD9814B 1CH DC CIS Input Referred Noise vs. Gain of 1.63 to 5 V/V
ADCCLK = 6MSPS, ADC Input Range = 3Vpp, AVDD = 5V, DVDD = 3V
4
3.5
3
RMS Noise (LSB
2.5
2
1.5
1
0.5
0
1.63
2.75
3.88
5
Gain
Graph 5. XRD9814B 1-Channel CIS S/H No Clamp Input Referred Noise vs. Gain (6 MSPS)
Rev. 1.00
45
XRD9814B/9816B
XRD9814B 3CH CDS Input Referred Noise vs. Gain of 1.63 to 5 V/V ADCCLK = 6MSPS,
AVDD = 5V, DVDD = 3V, ADC Input Range = 3Vpp
6
5
RMS Noise (LSB)
4
Input Referred Noise Red Channel
3
Input Referred Noise Green Channel
Input Referred Noise Blue Channel
2
1
0
1.63
2.75
3.88
5
Gain
Graph 6. XRD9814B 3-Channel CDS Pixel Clamp Input Referred Noise vs. Gain
Rev. 1.00
46
XRD9814B/9816B
XRD9814B/9816B Gain vs. Gain Code
10
9
8
7
Gain
6
red
5
green
blue
4
3
2
1
0
0
63
127
191
255
319
383
447
511
575
639
703
767
Gain Code
Graph 7. XRD9814B/9816B Gain vs. Gain Code
Rev. 1.00
47
831
895
959
1023
XRD9814B/9816B
XRD9814B/9816B 3CH CDS, AVDD = 5V, DVDD = 3V, Fs = 6MSPS, 3Vpp, Gain = 0.5 - 5 V/V
Output Referred System Offset Vs. Gain
Inputs AC Coupled to Ground with 100pF Capacitors
100
95
Output Referred System Offset (mV
90
85
Red Channel Offset
80
Green Channel Offset
Blue Channel Offset
75
70
65
60
0.50
0.78
1.06
1.34
1.63
1.91
2.19
2.47
2.75
3.03
3.31
3.59
3.88
4.16
4.44
4.72
5.00
Gain (V/V)
Graph 8. XRD9814B /9816B 3-Channel CDS Pixel Clamp System Offset vs. Gain
Rev. 1.00
48
0
Rev. 1.00
49
Codes
Graph 9. XRD9816B 3-Channel CDS Pixel Clamp DNL Plot
63360
61776
60192
58608
57024
55440
53856
52272
50688
49104
47520
45936
44352
42768
41184
39600
38016
36432
34848
33264
31680
30096
28512
26928
25344
23760
22176
20592
19008
17424
15840
14256
12672
11088
9504
7920
6336
4752
3168
1584
LSB
XRD9814B/9816B
1.5
XRD9816B 3-Channel CDS Pixel Clamp Mode, AVDD = DVDD = 5V, Fs = 6MSPS, 2V Reference, DNL Plot
1
0.5
0
-0.5
-1
XRD9814B/9816B
XRD9816B 1CH DC CIS Input Referred Noise vs. Gain of 1.63 to 5 V/V
ADCCLK = 1MSPS, ADC Input Range = 3Vpp, AVDD = 5V, DVDD = 3V
12
10
RMS Noise (LSB)
8
6
4
2
0
1.63
2.75
3.88
5
Gain
Graph 10. XRD9816B 1-Channel CIS SS/H No Clamp Input Referred Noise vs. Gain (1 MSPS)
Rev. 1.00
50
XRD9814B/9816B
XRD9816B 1CH DC CIS Input Referred Noise vs. Gain of 1.63 to 5 V/V
ADCCLK = 6MSPS, ADC Input Range = 3Vpp, AVDD = 5V, DVDD = 3V
14
12
RMS Noise (LSB)
10
8
6
4
2
0
1.63
2.75
3.88
5
Gain
Graph 11. XRD9816B 1-Channel CIS SS/H No Clamp Input Referred Noise vs. Gain (6 MSPS)
Rev. 1.00
51
XRD9814B/9816B
Rev. 1.00
52
XRD9814B/9816B
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of
patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending
upon a user’s specific application. While the information in this publication has been carefully checked; no
responsibility, however, is assumed for in accuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure
or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the
circumstances.
Copyright 2002 EXAR Corporation
Datasheet November 2002
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.00
53
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