TPS6215x 3-V to 17-V, 1-A Step-Down Converter in 3-mm × 3

TPS6215x 3-V to 17-V, 1-A Step-Down Converter in 3-mm × 3
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TPS62150, TPS62150A, TPS62151, TPS62152, TPS62153
SLVSAL5C – NOVEMBER 2011 – REVISED OCTOBER 2015
TPS6215x 3-V to 17-V, 1-A Step-Down Converter in 3-mm × 3-mm QFN Package
1 Features
3 Description
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The TPS6215x family is an easy-to-use synchronous
step down dc-dc converter optimized for applications
with high power density. A high switching frequency
of typically 2.5 MHz allows the use of small inductors
and provides fast transient response as well as high
output-voltage accuracy by the use of DCS-Control
topology.
1
•
DCS-Control™ Topology
Input Voltage Range: 3 V to 17 V
Up to 1-A Output Current
Adjustable Output Voltage From 0.9 V to 6 V
Pin-Selectable Output Voltage (nominal, + 5%)
Programmable Soft Start and Tracking
Seamless Power-Save Mode Transition
Quiescent Current of 17 µA (typ.)
Selectable Operating Frequency
Power-Good Output
100% Duty-Cycle Mode
Short-Circuit Protection
Overtemperature Protection
Pin-to-Pin Compatible With TPS6213x, -4x
Devices
Available in a 3-mm × 3-mm, VQFN-16 Package
With their wide operating input-voltage range of 3 V
to 17 V, the devices are ideally suited for systems
powered from either Li-Ion or other batteries as well
as from 12-V intermediate power rails. The devices
support up to 1-A continuous output current at output
voltages between 0.9 V and 6 V (in 100% duty-cycle
mode).
The soft-start pin controls the output-voltage start-up
ramp, which allows operation as either a standalone
power supply or in tracking configurations. Power
sequencing is also possible by configuring the enable
(EN) and open-drain power-good (PG) pins.
2 Applications
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Standard 12-V Rail Supplies
POL Supply From Single or Multiple Li-Ion Battery
Solid-State Disk Drives
Embedded Systems
LDO Replacement
Mobile PCs, Tablets, Modems, Cameras
Server, Microserver
Data Terminal, Point of Sales (ePOS)
In power-save mode, the devices draw quiescent
current of about 17 μA from VIN. Power-save-mode,
entered automatically and seamlessly if the load is
small, maintains high efficiency over the entire load
range. In shutdown mode, the device turns off and
current consumption is less than 2 μA.
The device, available in adjustable- and fixed-outputvoltage versions, comes in a 16-pin VQFN package
measuring 3 × 3 mm (RGT).
Device Information(1)
PART NUMBER
TPS6215X
PACKAGE
VQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
(3 .. 17)V
Efficiency vs Output Current
1.8V / 1A
2.2µH
PVIN
SW
AVIN
VOS
PG
EN
10uF
100k
22uF
TPS62151
SS/TR
3.3nF
FB
DEF
AGND
FSW
PGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62150, TPS62150A, TPS62151, TPS62152, TPS62153
SLVSAL5C – NOVEMBER 2011 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1
8.2
8.3
8.4
Overview ................................................................... 8
Functional Block Diagrams ....................................... 8
Feature Description................................................... 9
Device Functional Modes........................................ 10
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
9.3 System Examples ................................................... 24
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 28
11.3 Thermal Considerations ........................................ 29
12 Device and Documentation Support ................. 30
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
31
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2013) to Revision C
Page
•
Added Device and Documentation Support section, Layout and ESD Ratings table. ........................................................... 1
•
Changed Device Comparison table ....................................................................................................................................... 3
•
Arranged Pin Functions table in alphabetical order by pin name........................................................................................... 4
Changes from Revision A (November 2012) to Revision B
Page
•
Added device TPS62150A to data sheet ............................................................................................................................... 1
•
Added device TPS62150A to Ordering Info table .................................................................................................................. 3
•
Added text to Tracking Function section for clarification. ..................................................................................................... 17
Changes from Original (November 2011) to Revision A
Page
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Changed the description of the AGND pin, and added Note 3. ............................................................................................. 4
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Added values to the Initial output voltage accuracy for TA = –10°C to 85°C......................................................................... 6
•
Power-Save Mode Operation section following Equation 1 ................................................................................................. 11
•
Changed the Layout Guidelines section............................................................................................................................... 28
•
Changed Figure 48............................................................................................................................................................... 28
2
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SLVSAL5C – NOVEMBER 2011 – REVISED OCTOBER 2015
5 Device Comparison Table (1)
(1)
(1)
(2)
PART NUMBER (1)
OUTPUT VOLTAGE
TPS62150
Adjustable
TPS62150A (2)
Adjustable
TPS62151
1.8 V
TPS62152
3.3 V
TPS62153
5V
For detailed ordering information see Mechanical, Packaging, and Orderable Information.
Contact the factory to check availability of other fixed output voltage versions.
Whereas TPS6215x has PG = High Z, TPS62150A features PG = Low, when device is in shutdown through EN, UVLO, or thermal
shutdown.
Copyright © 2011–2015, Texas Instruments Incorporated
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6 Pin Configuration and Functions
SW
3
PG
4
PGND
VOS
EN
13
Exposed
Thermal Pad
5
6
7
8
DEF
2
14
FSW
SW
15
AGND
1
16
FB
SW
PGND
RGT Package
16-Pin VQFN With Thermal Pad
Top View
12
PVIN
11
PVIN
10
AVIN
9
SS/TR
spacing
Pin Functions
PIN
NAME
(1)
NO.
I/O
DESCRIPTION
AGND
6
—
AVIN
10
I
Supply voltage for control circuitry. Connect to same source as PVIN.
DEF
8
I
Output voltage scaling (Low = nominal, High = nominal + 5%) (2)
EN
13
I
Enable input (High = enabled, Low = disabled) (2)
FB
5
I
Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. It is good practice to
connect FB to AGND on fixed output voltage versions for improved thermal performance.
FSW
7
I
Switching frequency select (Low ≈ 2.5 MHz, High ≈ 1.25 MHz (3) for typical operation) (2)
PG
4
O
Output power-good (High = VOUT ready, Low = VOUT below nominal regulation); open-drain (requires
pullup resistor)
PGND
15, 16
—
Power ground. Connect directly to the exposed thermal pad and common ground plane.
PVIN
11, 12
I
Supply voltage for power stage. Connect to the same source as AVIN.
9
I
Soft-start or tracking pin. An external capacitor connected to this pin sets the internal voltage-reference
rise time. Alternative uses can be for tracking or sequencing.
SW
1, 2, 3
O
Switch node, which connects to the internal MOSFET switches. Connect an inductor between SW and the
output capacitor.
VOS
14
I
Output voltage-sense pin and connection for the control-loop circuitry.
Exposed
thermal pad
—
—
SS/TR
(1)
(2)
(3)
4
Analog ground. Must be connected directly to the exposed thermal pad and common ground plane.
Connect to AGND (pin 6), PGND (pins 15,16) and common ground plane. see the Figure 48. Connection
to AGND is mandatory. Soldering is necessary to achieve appropriate power dissipation and mechanical
reliability.
For more information about connecting pins, see the Detailed Description and Application and Implementation sections.
An internal pulldown resistor keeps logic level low, if pin is floating.
Connect FSW to VOUT or PG in this case.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Pin voltage (2)
Power-good sink current
Temperature
(1)
(2)
MIN
MAX
AVIN, PVIN
–0.3
20
EN, SS/TR
–0.3
VIN + 0.3
SW
–0.3
VIN + 0.3
DEF, FSW, FB, PG, VOS
–0.3
7
10
mA
Operating junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–65
150
°C
PG
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground terminal.
7.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
±2000
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
Supply Voltage, VIN (at AVIN and PVIN)
MAX
UNIT
3
17
V
Operating free air temperature, TA
–40
85
°C
Operating junction temperature, TJ
–40
125
°C
7.4 Thermal Information
TPS6215x
THERMAL METRIC
(1)
RGT (VFQN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case(top) thermal resistance
29.1
°C/W
15
°C/W
RθJB
ψJT
Junction-to-board thermal resistance
11
°C/W
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
10
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
3.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2011–2015, Texas Instruments Incorporated
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7.5 Electrical Characteristics
over free-air temperature range (TA = -40°C to 85°C), typical values at VIN = AVIN = PVIN = 12 V and TA = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
SUPPLY
VIN
Input Voltage Range (1)
IQ
Operating Quiescent Current
EN = High, IOUT = 0 mA, device not switching
ISD
Shutdown Current (2)
EN = Low
VUVLO
3
Undervoltage Lockout Threshold
Falling Input Voltage (PWM mode operation)
2.6
Hysteresis
V
25
µA
1.5
4
µA
2.7
2.8
V
200
Thermal Shutdown Temperature
TSD
17
17
mV
160
Thermal Shutdown Hysteresis
°C
20
CONTROL (EN, DEF, FSW, SS/TR, PG)
VH
High Level Input Threshold Voltage (EN,
DEF, FSW)
VL
Low Level Input Threshold Voltage (EN,
DEF, FSW)
ILKG
Input Leakage Current (EN, DEF, FSW)
0.9
0.65
0.45
EN = VIN or GND; DEF, FSW = VOUT or GND
V
0.3
V
µA
0.01
1
Rising (%VOUT)
92%
95%
98%
Falling (%VOUT)
87%
90%
94%
VTH_PG
Power Good Threshold Voltage
VOL_PG
Power Good Output Low Voltage
IPG = –2 mA
0.07
0.3
V
ILKG_PG
Input Leakage Current (PG)
VPG = 1.8 V
1
400
nA
ISS/TR
SS/TR Pin Source Current
2.5
2.7
µA
VIN ≥ 6 V
90
170
VIN = 3 V
120
VIN ≥ 6 V
40
VIN = 3 V
50
2.3
POWER SWITCH
High-Side MOSFET ON-Resistance
rDS(on)
Low-Side MOSFET ON-Resistance
High-Side MOSFET Forward Current Limit (3) VIN = 12 V, TA = 25°C
ILIMF
1.4
1.7
70
mΩ
mΩ
2.2
A
100
nA
6
V
OUTPUT
VREF
Internal Reference Voltage (4)
ILKG_FB
Input Leakage Current (FB)
TPS62150, VFB = 0.8 V
Output Voltage Range (TPS62150)
VIN ≥ VOUT
DEF (Output Voltage Programming)
DEF = 0 (GND)
VOUT
DEF = 1 (VOUT)
VOUT
+ 5%
VOUT
Initial Output Voltage Accuracy
0.8
(5)
1
0.9
PWM mode operation, VIN ≥ VOUT + 1 V
–1.8%
1.8%
PWM mode operation, VIN ≥ VOUT + 1 V,
TA = –10°C to 85°C
–1.5%
1.6%
–2.3
2.8
Power Save Mode operation, COUT = 22 µF
(1)
(2)
(3)
(4)
(5)
(6)
6
V
Load Regulation (6)
VIN = 12 V, VOUT = 3.3 V, PWM mode
operation
0.05
%/A
Line Regulation (6)
3 V ≤ VIN ≤ 17 V, VOUT = 3.3 V, IOUT = 1 A,
PWM mode operation
0.02
%/V
The device is still functional down to Undervoltage Lockout (see parameter VUVLO).
Current into AVIN+PVIN pins.
This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current-Limit and ShortCircuit Protection section).
This is the voltage regulated at the FB pin.
This is the accuracy provided by the device itself (line and load regulation effects are not included). For the fixed voltage versions the
(internal) resistive divider is included.
Line and load regulation depend on external component selection and layout (see Figure 22 and Figure 23).
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7.6 Typical Characteristics
50
5
45
4.5
4
Input Current (µA)
Input Current (µA)
40
35
30
85°C
25°C
25
20
15
10
3.5
85°C
3
2.5
2
1.5
−40°C
1
−40°C
5
0
0
0
3
6
25°C
0.5
9
12
Input Voltage (V)
15
18
20
0
3
Figure 1. Quiescent Current
6
9
12
Input Voltage (V)
15
18
20
Figure 2. Shutdown Current
100
200
160
125°C
140
RDSon Low−Side (mW)
RDSon High−Side (mW)
180
85°C
120
25°C
100
80
−10°C
60
−40°C
40
80
125°C
85°C
60
25°C
40
−10°C
20
−40°C
20
0
0
3
6
9
12
Input Voltage (V)
15
Figure 3. High-Side Switch Resistance
Copyright © 2011–2015, Texas Instruments Incorporated
18
20
0
0
3
6
9
12
Input Voltage (V)
15
18
20
Figure 4. Low-Side Switch Resistance
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8 Detailed Description
8.1 Overview
The TPS6215x synchronous switched-mode power converter is based on DCS-Control topology, an advanced
regulation topology that combines the advantages of hysteretic, voltage-mode, and current-mode control,
including an ac loop directly associated with the output voltage. This control loop takes information about output
voltage changes and feeds that information directly to a fast comparator stage. It sets the switching frequency,
which is constant for steady-state operating conditions, and provides immediate response to dynamic load
changes. To get accurate dc load regulation, a voltage feedback loop is used. The internally compensated
regulation network achieves fast and stable operation with small external components and low-ESR capacitors.
The DCS-Control topology supports pulse-width modulation (PWM) mode for medium and heavy load conditions
and a power-save mode at light loads. During PWM, it operates at its nominal switching frequency in continuousconduction mode. This frequency is typically about 2.5 MHz or 1.25 MHz, with a controlled frequency variation
depending on the input voltage. If the load current decreases, the converter enters power-save mode to sustain
high efficiency down to very light loads. In power-save mode, the switching frequency decreases linearly with the
load current. Because DCS-Control topology supports both operation modes within a single building block, the
transition from PWM to power-save mode is seamless without effects on the output voltage.
Fixed-output voltage versions provide the smallest solution size and lowest current consumption, requiring only
three external components. An internal current limit supports nominal output currents of up to 1 A.
The TPS6215x offers both excellent dc voltage and superior load transient regulation, combined with very low
output voltage ripple, minimizing interference with RF circuits.
8.2 Functional Block Diagrams
PG
Soft
start
Thermal
Shtdwn
UVLO
AVIN
PVIN PVIN
PG control
HS lim
comp
EN*
SW
SS/TR
power
control
control logic
gate
drive
SW
DEF*
SW
FSW*
comp
LS lim
VOS
direct control
&
compensation
ramp
_
FB
comparator
+
timer tON
error
amplifier
DCS - ControlTM
*
This pin is connected to a pull down resistor internally
(see Detailed Description section).
AGND
PGND PGND
Figure 5. TPS62150 (Adjustable Output Voltage)
8
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Functional Block Diagrams (continued)
PG
Soft
start
Thermal
Shtdwn
UVLO
AVIN
PVIN PVIN
PG control
HS lim
comp
EN*
SW
SS/TR
power
control
control logic
DEF
gate
drive
SW
*
SW
FSW*
comp
LS lim
VOS
direct control
&
compensation
ramp
_
FB*
comparator
+
timer tON
error
amplifier
DCS - ControlTM
*
This pin is connected to a pull down resistor internally
(see Detailed Description section).
AGND
PGND PGND
Figure 6. TPS62151, -2, -3 (Fixed Output Voltage)
8.3 Feature Description
8.3.1 Enable / Shutdown (EN)
When Enable (EN) is set High, the device starts operation. Shutdown is forced if EN is pulled Low with a
shutdown current of typically 1.5 µA. During shutdown, the internal power MOSFETs as well as the entire control
circuitry are turned off. The internal resistive divider pulls down the output voltage smoothly. The EN signal must
be set externally to High or Low. An internal pulldown resistor of about 400 kΩ is connected and keeps the EN
logic Low, if Low is set initially and then the pin gets floating. The pulldown resistor is disconnected if the pin is
set High.
Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple
power rails.
8.3.2 Soft-Start or Tracking (SS/TR)
The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush
current and ensures a controlled output-voltage rise time. It also prevents unwanted voltage drops from highimpedance power sources or batteries. When EN is set to start device operation, the device starts switching after
a delay of about 50 µs, and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR
pin. See Figure 34 and Figure 35 for typical start-up operation.
Using a very small capacitor (or leaving the SS/TR pin disconnected) provides fastest start-up behavior. The
TPS6215x can start into a pre-biased output. During monotonic pre-biased start-up, both the power MOSFETs
are not allowed to turn on until the internal ramp of the device sets an output voltage above the pre-bias voltage.
If the device is set to shutdown (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistor pulls
the SS/TR pin down to ensure a proper low level. Returning from those states causes a new start-up sequence
as set by the SS/TR connection.
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Feature Description (continued)
A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage follows this voltage in
both directions, up and down (see Application and Implementation).
8.3.3 Power Good (PG)
The TPS6215x has a built-in power-good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. One use of the PG signal can be for start-up sequencing of multiple rails. The PG pin is
an open-drain output that requires a pullup resistor (to any voltage below 7 V). It can sink 2 mA of current and
maintain its specified logic-low level. It features PG = Low when EN, UVLO, or thermal shutdown turns the
device off and can actively discharge VOUT (see Figure 39). VIN must remain present for the PG pin to stay Low.
8.3.4 Pin-Selectable Output Voltage (DEF)
Setting the DEF pin to High increases the output voltage of the TPS62150x devices by 5% above the nominal
voltage (1). When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal voltage
allows adapting the power supply voltage to the variations of the application hardware. More detailed information
on voltage margining using the TPS62150x device is in SLVA489. The pin has an internally connected pulldown
resistor of about 400 kΩ to ensure a proper logic level if the pin is high-impedance or floating after an initially Low
setting. Setting the pin High disconnects the resistor.
8.3.5 Frequency Selection (FSW)
To get high power density with a very small solution size, a high switching frequency allows the use of small
external components for the output filter. However, switching losses increase with the switching frequency. If
efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz
typical) by pulling FSW to High. It is mandatory to start with FSW = Low to limit inrush current, which connecting
FSW to VOUT or PG can accomplish. Running with lower frequency produces higher efficiency, but also creates
higher output-voltage ripple. Pull FSW to Low for high-frequency operation (2.5 MHz typical). To get low ripple
and full output current at the lower switching frequency, the recommended minimum inductor value is 2.2 µH. An
application can change the switching frequency during operation, if needed. An internally connected pulldown
resistor of about 400 kΩ on this pin acts the same way as one on the DEF pin (see Pin-Selectable Output
Voltage (DEF)).
8.3.6 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents faulty operation of the device by switching off both
the power FETs. The typical undervoltage-lockout threshold setting is 2.7 V. The device is fully operational for
voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 200 mV.
8.3.7 Thermal Shutdown
An internal temperature sensor monitors the junction temperature (TJ) of the device. If TJ exceeds 160°C (typ),
the device goes into thermal shutdown. Both the high-side and low-side power FETs turn off and PG goes into
the high-impedance state. When TJ decreases below the hysteresis level, the converter resumes normal
operation, beginning with soft start. To avoid unstable conditions, the device implements a hysteresis of typically
20°C on the thermal shutdown temperature.
8.4 Device Functional Modes
8.4.1 Pulse-Width Modulation (PWM) Operation
The TPS6215x operates using pulse-width modulation in continuous-conduction mode (CCM) with a nominal
switching frequency of 2.5 MHz or 1.25 MHz, selectable with the FSW pin. The frequency variation in the PWM
mode is controlled and depends on VIN, VOUT, and the inductance. The device operates in PWM mode as long
the output current is higher than half the inductor ripple current. To maintain high efficiency at light loads, the
device enters power-save mode at the boundary of discontinuous conduction mode (DCM). This happens if the
output current becomes smaller than half the inductor ripple current.
(1)
10
Maximum allowed voltage is 7 V. Therefore, the recommended connection for DEF is to VOUT, not VIN.
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Device Functional Modes (continued)
8.4.2 Power-Save Mode Operation
The TPS6215x enters its built-in power-save mode seamlessly if the load current decreases. This secures a high
efficiency in light load operation. The device remains in power-save mode as long as the inductor current is
discontinuous.
In power-save mode, the switching frequency decreases linearly with the load current, maintaining high
efficiency. The transition into and out of power-save mode happens within the entire regulation scheme and is
seamless in both directions.
TPS6215x includes a fixed on-time circuitry. An estimate for this on-time (FSW = Low), in steady-state operation,
is:
space
t ON =
VOUT
´ 400 ns
VIN
(1)
space
For very small output voltages, an absolute minimum on-time of about 80 ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Also, the off-time can
reach its minimum value at high duty cycles. The output voltage remains regulated in such cases. Using tON, the
typical peak inductor current in power-save mode is approximated by:
space
ILPSM(peak) =
(VIN - VOUT )
L
´ t ON
(2)
space
When VIN decreases to typically 15% above VOUT, the TPS62150B device does not enter power-save mode,
regardless of the load current. The device maintains output regulation in PWM mode.
8.4.3 100% Duty-Cycle Operation
The duty cycle of the buck converter is given by D = VOUT / VIN and increases as the input voltage comes close
to the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch
100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal set
point. This allows the conversion of small input-to-output voltage differences, for example, for longest operation
time of battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, is calculated as:
spacing
(
VIN(min) = VOUT(min) + I OUT ´ R DS(on) + R L
)
where
•
•
•
IOUT is the output current
RDS(on) is the on-state resistance of the high-side FET
RL is the dc resistance of the inductor
(3)
8.4.4 Current-Limit and Short-Circuit Protection
The TPS6215x devices have protection against heavy-load and short-circuit events. At heavy loads, the current
limit determines the maximum output current. If the current limit is reached, the high-side FET is turned off.
Avoiding shoot-through current, then the low-side FET switches on to allow the inductor current to decrease. The
low-side current limit is typically 1.2 A. The high-side FET turns on again only if the current in the low-side FET
has decreased below the low-side current-limit threshold.
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Device Functional Modes (continued)
The output current of the device is limited by the current limit (see Electrical Characteristics). Due to internal
propagation delay, the actual current can exceed the static current limit during that time. The dynamic current
limit is calculated as follows:
spacing
Ipeak(typ) = ILIMF +
VL
L
´ t PD
where
•
•
•
•
ILIMF is the static current limit, specified in the Electrical Characteristics
VL is the voltage across the inductor (VIN – VOUT)
L is the inductor value
tPD is the internal propagation delay
(4)
space
The current limit can exceed static values, especially if the input voltage is high and the application uses very
small inductances. Calculate the peak current in the dynamic high-side switch using the following equation:
space
Ipeak(typ) = ILIMF +
12
(VIN - VOUT )´ 30 ns
L
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(5)
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS6215x devices are a switched-mode step-down converters, able to convert a 3-V to 17-V input voltage
into a 0.9-V to 6-V output voltage, providing up to 1 A. They require a minimum number of external components.
Apart from the LC output filter and the input capacitors, only the TPS62150 device needs an additional resistive
divider to set the output voltage level.
9.2 Typical Application
This application shows a point-of-load power supply using the TPS62150 device.
(3 .. 17)V
VOUT / 1A
2.2µH
10uF
PVIN
SW
AVIN
VOS
PG
EN
100k
R1
22uF
TPS62150
SS/TR
3.3nF
FB
DEF
AGND
FSW
PGND
R2
Figure 7. A Typical 1-A Step-Down Converter
9.2.1 Design Requirements
The following design guideline provides a component selection to operate the device within the recommended
operating conditions. Using the FSW pin, the design can be optimized for highest efficiency or smallest solution
size and lowest output-voltage ripple. For highest efficiency set FSW = High, and the device operates at the
lower switching frequency. For smallest solution size and lowest output voltage ripple set FSW = Low, and the
device operates with higher switching frequency. The typical values for all measurements are VIN = 12 V, VOUT =
3.3 V, and T = 25°C, using the external components of Table 1.
The component selection used for measurements is given as follows:
Table 1. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER (1)
IC
17-V, 1-A step-down converter, QFN
L1
2.2-µH, 3.1-A, 0.165-in × 0.165-in (4.19-mm × 4.19-mm)
Cin
10-µF, 25-V, ceramic
Standard
Cout
22-µF, 6.3-V, ceramic
Standard
Css
3300-pF, 25-V, ceramic
R1
Depending on VOUT
R2
Depending on VOUT
R3
100-kΩ, chip, 0603, 1/16-W, 1%
(1)
TPS62150RGT, Texas Instruments
XFL4020-222MEB, Coilcraft
Standard
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9.2.2 Detailed Design Procedure
9.2.2.1 Programming the Output Voltage
Whereas the output voltage of the TPS62150 (TPS62150A) is adjustable, the TPS62151, -2, and -3 are
programmed to fixed output voltages. For fixed output versions, the FB pin is pulled down internally and may be
left floating. It is recommended to connect the FB pin to AGND to decrease thermal resistance. The adjustable
version can be programmed for output voltages from 0.9 V to 6 V by using a resistive divider from VOUT to
AGND. The voltage at the FB pin is regulated to 800 mV. The value of the output voltage is set by the selection
of the resistive divider from Equation 6. It is recommended to choose resistor values which allow a current of at
least 2 µA, meaning the value of R2 should not exceed 400 kΩ. Lower resistor values are recommended for
highest accuracy and most robust design. For applications requiring lowest current consumption, the use of
fixed-output-voltage versions is recommended.
space
æV
ö
R 1 = R 2 ´ ç OUT - 1÷
ç VREF
÷
è
ø
(6)
In case of an open on the FB pin, the device clamps the output voltage at the VOS pin internally to about 7.4 V.
9.2.2.2 External Component Selection
The external components must fulfill the needs of the application, but also the stability criteria for the control loop
of the device. The TPS6215x device is optimized to work within a range of external components. Consider the
inductance and capacitance of the LC output filters in conjunction, creating the double pole responsible for the
corner frequency of the converter (see the Output Filter and Loop Stability section). Table 2 can simplify the
selection of output-filter components.
Table 2. L-C Output Filter Combinations (1)
4.7 µF
10 µF
22 µF
47 µF
100 µF
200 µF
√
√
√
√
2.2 µH
√
√ (2)
√
√
√
3.3 µH
√
√
√
√
400 µF
0.47 µH
1 µH
4.7 µH
(1)
(2)
The values in the table are nominal values.
This LC combination is the standard value, and is recommended for most applications.
spacing
The TPS6215x device can operate with an inductor as low as 1 µH or 2.2 µH. FSW should be set Low in this
case. However, for applications running with the low-frequency setting (FSW = High) or with low input voltages,
3.3 µH is recommended. More detailed information on further LC combinations can be found in SLVA463.
9.2.2.2.1 Inductor Selection
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-toPSM transition point, and efficiency. In addition, the inductor selected must be rated for appropriate saturation
current and dc resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under static
load conditions.
spacing
IL(max) = I OUT(max) +
DIL(max)
2
(7)
space
14
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DIL(max)
VOUT
æ
ç 1- V
IN(max)
= VOUT ´ ç
ç L (min) ´ f SW
çç
è
ö
÷
÷
÷
÷÷
ø
where
•
•
•
•
IL(max) is the maximum inductor current
ΔIL is the peak-to-peak inductor ripple current
L(min) is the minimum effective inductor value
fSW is the actual PWM switching frequency
(8)
spacing
Calculating the maximum inductor current using the actual operating conditions gives the minimum required
saturation current of the inductor. An added margin of about 20% is recommended. A larger inductor value is
also useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TPS6215x device and are recommended for use:
Table 3. List of Inductors
(1)
(2)
TYPE
INDUCTANCE [µH]
SATURATION
CURRENT [A] (1)
DIMENSIONS
[L × W × H], mm
MANUFACTURER (2)
XFL4020-222ME_
2.2 µH, ±20%
3.5
4 × 4 × 2.1
Coilcraft
XFL3012-222MEC
2.2 µH, ±20%
1.6
3 × 3 × 1.2
Coilcraft
XFL3012-332MEC
3.3 µH, ±20%
1.4
3 × 3 × 1.2
Coilcraft
VLS252012T-2R2M1R3
2.2 µH, ±20%
1.3
2.5 × 2 × 1.2
TDK
LPS3015-332
3.3 µH, ±20%
1.4
3 × 3 × 1.4
Coilcraft
744025003
3.3 µH, ±20%
1.5
2.8 × 2.8 × 2.8
Wuerth
PSI25201B-2R2MS
2.2 µH, ±20%
1.3
2 × 2.5 × 1.2
Cyntec
NR3015T-2R2M
2.2 µH, ±20%
1.5
3 × 3 × 1.5
Taiyo Yuden
Lower of IRMS at 40°C rise or ISAT at 30% drop.
See Third-Party Products Disclaimer
spacing
The inductor value also determines the load current at which the device enters power-save mode:
space
Iload(PSM) =
1
DIL
2
(9)
space
Using Equation 8, this current level can be adjusted by changing the inductor value.
9.2.2.2.2 Capacitor Selection
9.2.2.2.2.1 Output Capacitor
The recommended value for the output capacitor is 22 µF. The architecture of the TPS6215x device allows the
use of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low
output-voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, it is recommended to use X7R or X5R dielectric. Using a higher value of
output capacitance can have some advantages, like smaller voltage ripple and a tighter dc output accuracy in
power-save mode (see SLVA463).
Note: In power-save mode, the output-voltage ripple depends on the output capacitance, the ESR of the output
capacitor, and the peak inductor current. Using ceramic capacitors provides small ESR and low ripple.
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9.2.2.2.2.2 Input Capacitor
For most applications, 10 µF is sufficient and is recommended, though a larger value reduces input-current ripple
further. The input capacitor buffers the input voltage for transient events and also decouples the converter from
the supply. A low-ESR multilayer ceramic capacitor is recommended for best filtering and should be placed
between PVIN and PGND as close as possible to those pins. Even though AVIN and PVIN must be supplied
from the same input source, it is recommended to place a capacitance of 0.1 µF from AVIN to AGND, to avoid
potential noise coupling. An RC, low-pass filter from PVIN to AVIN may be used but is not required.
9.2.2.2.2.3 Soft-Start Capacitor
A capacitance connected between the SS/TR pin and AGND allows a user-programmable start-up slope of the
output voltage. A constant-current source supplies 2.5 µA to charge the external capacitance. The capacitor
required for a given soft-start ramp time for the output voltage is given by:
space
CSS = t SS ´
2.5 mA
1.25 V
éëF ùû
where
•
•
CSS is the capacitance (F) required at the SS/TR pin
tSS is the desired soft-start ramp time (s)
(10)
spacing
NOTE
DC bias effect: High capacitance ceramic capacitors have a dc bias effect, which has a
strong influence on the final effective capacitance. Therefore, selecting the right capacitor
value requires careful choice. Package size and voltage rating in combination with
dielectric material are responsible for differences between the rated capacitor value and
the effective capacitance.
spacing
9.2.2.3 Tracking Function
If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external
tracking voltage. The output voltage tracks that voltage. If the tracking voltage is between 50 mV and 1.2 V, the
FB pin will track the SS/TR pin voltage as described in Equation 11 and shown in Figure 8.
spacing
VFB » 0.64 ´ VSS/TR
(11)
VSS/
TR [V]
1.2
0.8
0.4
0.2
0.4
0.6
0.8
VFB [V]
Figure 8. Voltage Tracking Relationship
16
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Once the SS/TR pin voltage reaches about 1.2 V, the internal voltage is clamped to the internal feedback voltage
and device goes to normal regulation. This works for rising and falling tracking voltages with the same behavior,
as long as the input voltage is inside the recommended operating conditions. For decreasing SS/TR pin voltage,
the device does not sink current from the output. So, the resulting decrease of the output voltage may be slower
than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not
exceed the voltage rating of the SS/TR pin, which is VIN+ 0.3 V.
If the input voltage drops into undervoltage lockout or even down to zero, the output voltage goes to zero,
independent of the tracking voltage. Figure 9 shows how to connect devices to get ratiometric and simultaneous
sequencing by using the tracking function.
spacing
VOUT1
PVIN
SW
AVIN
VOS
PG
EN
TPS62150
SS/TR
FB
DEF
AGND
FSW
PGND
PVIN
SW
AVIN
VOS
VOUT2
R1
EN
PG
TPS62150
SS/TR
R2
FB
DEF
AGND
FSW
PGND
Figure 9. Schematic for Ratiometric and Simultaneous Start-Up
The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower, or the same as
that of VOUT1.
A sequential start-up is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. A ratiometric
start-up sequence happens if both supplies share the same soft-start capacitor. Equation 10 calculates the softstart time, though the SS/TR current must be doubled. Details about these and other tracking and sequencing
circuits are found in the TPS62130/40/50 Sequencing and Tracking application report, SLVA470.
Note: If the voltage at the FB pin is below its typical value of 0.8 V, the output voltage accuracy may have a
wider tolerance than specified.
9.2.2.4 Output Filter and Loop Stability
The devices of the TPS6215x family are internally compensated to be stable with L-C filter combinations
corresponding to a corner frequency to be calculated with Equation 12:
spacing
fLC =
1
2p L ´ C
(12)
space
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Proven nominal values for inductance and ceramic capacitance are given in Table 2 and are recommended for
use. Different values may work, but care must be taken on the loop stability, which is affected. More information,
including a detailed L-C stability matrix, can be found in the TPS62130/40/50 Sequencing and Tracking
application report, SLVA463.
The TPS6215x devices, both fixed and adjustable versions, include an internal 25-pF feedforward capacitor,
connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and
zero in the control loop with the resistors of the feedback divider, per equations Equation 13 and Equation 14:
spacing
f zero =
1
2p ´ R 1 ´ 25 pF
(13)
æ 1
1
1 ö
´ç
+
÷
2p ´ 25 pF çè R 1 R 2 ÷ø
(14)
spacing
f pole =
spacing
Though the TPS6215x devices are stable without the pole and zero being in a particular location, adjusting their
location to the specific needs of the application can provide better performance in power-save mode and/or
improved transient response. An external feedforward capacitor can also be added. A more-detailed discussion
on the optimization for stability versus transient response can be found in the Optimizing Transient Response of
Internally Compensated dc-dc Converters With Feedforward Capacitor and Using a Feedforward Capacitor to
Improve Stability and Bandwidth of TPS62130/40/50/60/70 application reports, SLVA289 and SLVA466,
respectively.
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9.2.3 Application Curves
VIN= 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)
100
100
90
90
80
70
VIN = 12 V
VIN = 17 V
Efficiency (%)
Efficiency (%)
80
60
50
40
70
60
30
30
20
20
10
10
0
0.0001
0.001
0.01
Output Current (A)
0.1
0
1
100
100
90
90
80
80
70
VIN = 17 V
60
50
VIN = 12 V
40
20
10
0
1
100
100
90
90
80
80
60
VIN = 12 V
VIN = 17 V
VIN = 5 V
50
40
20
10
Figure 14. Efficiency With 1.25 MHz, VOUT = 3.3 V
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17
IOUT = 1 A
8
9
10
11
12
13
14
Input Voltage (V)
15
16
17
1
IOUT = 1 A
IOUT = 1 mA
IOUT = 100 mA
IOUT = 10 mA
40
10
0.1
16
IOUT = 100 mA
50
30
0.01
Output Current (A)
7
60
20
0.001
IOUT = 10 mA
70
30
0
0.0001
15
Figure 13. Efficiency With 2.5 MHz, VOUT = 5 V
Efficiency (%)
Efficiency (%)
Figure 12. Efficiency With 2.5 MHz, VOUT = 5 V
70
11
12
13
14
Input Voltage (V)
40
10
0.1
10
50 IOUT = 1 mA
30
0.01
Output Current (A)
9
60
20
0.001
8
70
30
0
0.0001
7
IOUT = 100 mA
Figure 11. Efficiency With 1.25 MHz, VOUT = 5 V
Efficiency (%)
Efficiency (%)
Figure 10. Efficiency With 1.25 MHz, VOUT = 5 V
IOUT = 1 A
IOUT = 10 mA
50 IOUT = 1 mA
40
0
4
5
6
7
8
9 10 11 12 13 14 15 16 17
Input Voltage (V)
Figure 15. Efficiency With 1.25 MHz, VOUT = 3.3 V
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100
100
90
90
80
80
70
70
60
VIN = 12 V
50
Efficiency (%)
Efficiency (%)
VIN= 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)
VIN = 17 V
VIN = 5 V
40
60
30
20
20
10
10
0.001
0.01
Output Current (A)
0.1
0
1
100
100
90
90
80
80
70
VIN = 12 V
50
VIN = 17 V
VIN = 5 V
40
20
10
0
1
100
100
90
90
80
80
70
VIN = 17 V
VIN = 12 V
50
40
VIN = 5 V
20
10
Figure 20. Efficiency With 1.25 MHz, VOUT = 0.9 V
20
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3
4
5
6
7
8 9 10 11 12 13 14 15 16 17
Input Voltage (V)
1
IOUT = 1 A
IOUT = 100 mA
40
20
0.1
IOUT = 10 mA
IOUT = 1 mA
50
10
0.01
Output Current (A)
IOUT = 100 mA
60
30
0.001
9 10 11 12 13 14 15 16 17
Input Voltage (V)
70
30
0
0.0001
8
Figure 19. Efficiency With 1.25 MHz, VOUT = 1.8 V
Efficiency (%)
Efficiency (%)
Figure 18. Efficiency With 1.25 MHz, VOUT = 1.8 V
60
7
40
10
0.1
6
50
30
0.01
Output Current (A)
5
IOUT = 1 A
60
20
0.001
4
70
30
0
0.0001
IOUT = 1 A
Figure 17. Efficiency With 2.5 MHz, VOUT = 3.3 V
Efficiency (%)
Efficiency (%)
Figure 16. Efficiency With 2.5 MHz, VOUT = 3.3 V
60
IOUT = 1 mA
IOUT = 10 mA
40
30
0
0.0001
IOUT = 100 mA
50
0
IOUT = 10 mA
IOUT = 1 mA
3
4
5
6
7
8 9 10 11 12 13 14 15 16 17
Input Voltage (V)
Figure 21. Efficiency With 1.25 MHz, VOUT = 0.9 V
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VIN= 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)
3.4
3.4
Output Voltage (V)
Output Voltage (V)
VIN = 17 V
3.35
3.3
VIN = 5 V
VIN = 12 V
3.25
3.2
0.0001
0.001
0.01
Output Current (A)
0.1
IOUT = 1 A
3.25
4
4
3.5
3.5
3
2.5
2
IOUT = 0.5 A
IOUT = 1 A
1.5
1
0.5
0
4
7
16
3
2.5
2
1.5
1
4
6
8
10
12
Input Voltage (V)
14
16
0
18
0
0.2
0.5
Output Current (A)
0.8
1
FSW = Low
Figure 24. Switching Frequency
Figure 25. Switching Frequency
3
0.05
2.5
0.04
Output Current (A)
Output Voltage Ripple (V)
10
13
Input Voltage (V)
0.5
FSW = Low
0.03
VIN = 17 V
0.02
0.01
2
0
0.1
0.2
0.3
25°C
−40°C
1.5
1
85°C
0.5
VIN = 5 V
0
IOUT = 100 mA
Figure 23. Output Voltage Accuracy (Line Regulation)
Switching Frequency (MHz)
Switching Frequency (MHz)
Figure 22. Output Voltage Accuracy (Load Regulation)
IOUT = 10 mA
3.3
3.2
1
IOUT = 1 mA
3.35
VIN = 12 V
0.4 0.5 0.6 0.7
Output Current (A)
0.8
Figure 26. Output Voltage Ripple
Copyright © 2011–2015, Texas Instruments Incorporated
0.9
1
0
4
5
6
7
8
9 10 11 12 13 14 15 16 17
Input Voltage (V)
Figure 27. Maximum Output Current
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VIN= 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)
100
100
90
VIN=17V
PSRR (dB)
PSRR (dB)
70
60
50
40
30
VIN=17V
60
50
40
30
20
20
VOUT=3.3V, IOUT=1A
L=2.2uH (XFL4020)
Cin=10uF, Cout=22uF
10
10
100
1k
10k
Frequency (Hz)
VOUT=3.3V, IOUT=0.1A
L=2.2uH (XFL4020)
Cin=10uF, Cout=22uF
10
100k
1M
0
10
G000
IOUT = 1 A
100
1k
10k
Frequency (Hz)
100k
1M
G000
IOUT = 0.1 A
Figure 28. Power-Supply Rejection Ratio, fSW= 2.5 MHz
Figure 30. PWM-to-PSM Transition
Figure 32. Load Transient Response, Rising Edge
22
VIN=5V
80
VIN=12V
70
0
VIN=12V
90
VIN=5V
80
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Figure 29. Power-Supply Rejection Ratio, fSW = 2.5 MHz
Figure 31. Load Transient Response
Figure 33. Load Transient Response, Falling Edge
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VIN= 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)
Figure 34. Start-Up Into 100 mA
Figure 35. Start-Up Into 1 A
Figure 36. Typical Operation in PWM Mode, (IOUT = 1 A)
Figure 37. Typical Operation in Power-Save Mode, (IOUT =
10 mA)
Space
Space
Space
Space
Space
Space
Space
Space
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9.3 System Examples
9.3.1 LED Power Supply
The TPS62150 can be used as a power supply for power LEDs. The FB pin can be easily set down to lower
values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid
excessive power loss. Because this pin provides 2.5 µA, the feedback pin voltage can be adjusted by an external
resistor per Equation 15. This drop, proportional to the LED current, is used to regulate the output voltage (anode
voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TPS62150.
Figure 38 shows an application circuit, tested with analog dimming:
spacing
(4 .. 17) V
2.2 µH
PVIN
SW
AVIN
VOS
PG
EN
10uF
ADIM
22uF
TPS62150
FB
SS/TR
187k
DEF
AGND
FSW
PGND
0.3R
Figure 38. Single Power-LED Supply
spacing
The resistor at SS/TR sets the FB voltage to a level of about 300 mV, with a value calculated from Equation 15.
spacing
VFB = 0.64 ´ 2.5 mA ´ RSS/TR
(15)
spacing
The device now supplies a constant current, set by the resistor at the FB pin, by regulating the output voltage
accordingly. The forward voltage requirement of the LED determines the minimum input voltage rating. More
information is available in the Using the TPS62150 as Step-Down LED Driver With Dimming application report,
SLVA451.
9.3.2 Active Output Discharge
The TPS62150A device pulls the PG pin Low when the device is shut down by EN, UVLO, or thermal shutdown.
Connecting PG to VOUT through a resistor can be used to discharge VOUT in those cases (see Figure 39). The
discharge rate can be adjusted by R3, which is also used to pull up the PG pin in normal operation. For reliability,
keep the maximum current into the PG pin less than 10 mA.
spacing
(3 .. 17)V
2.2 µH
PVIN
Vout / 1A
SW
TPS62150A
AVIN
10uF
3.3nF
VOS
EN
PG
SS/TR
FB
DEF
AGND
FSW
PGND
R3
R1
22uF
R2
Figure 39. Discharge VOUT Through PG Pin with TPS62150A
spacing
24
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System Examples (continued)
9.3.3 Inverting Power Supply
The TPS6215x device can be used as an inverting power supply by rearranging external circuitry as shown in
Figure 40. As the former GND node now represents a voltage level below system ground, the voltage difference
between VIN and VOUT must be limited for operation to the maximum supply voltage of 17 V (see Equation 16).
spacing
VIN + VOUT £ VIN max
(16)
spacing
10uF
2.2µH
(3 .. 13.7)V
PVIN
SW
AVIN
VOS
10uF
PG
EN
1.21M
TPS62150
22uF
FB
SS/TR
3.3nF
DEF
AGND
FSW
PGND
383k
-3.3V
Figure 40. –3.3-V Inverting Power Supply
spacing
The transfer function of the inverting power supply configuration differs from the buck-mode transfer function,
additionally incorporating a right half-plane zero. The loop stability must be adapted, and an output capacitance
of at least 22 µF is recommended. A detailed design example is given in the Using the TPS6215x in an Inverting
Buck-Boost Topology application report, SLVA469.
spacing
9.3.4 Various Output Voltages
The following example circuits show how to use the various devices and configure the external circuitry to furnish
different output voltages at 1 A.
spacing
spacing
(5 .. 17)V
5V / 1A
2.2 µH
10uF
PVIN
SW
AVIN
VOS
PG
EN
100k
22uF
TPS62153
SS/TR
3.3nF
FB
DEF
AGND
FSW
PGND
Figure 41. 5-V, 1-A Power Supply
spacing
spacing
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System Examples (continued)
(3.3 .. 17)V
3.3V / 1A
2.2 µH
10uF
PVIN
SW
AVIN
VOS
100k
PG
EN
22uF
TPS62152
FB
SS/TR
3.3nF
DEF
AGND
FSW
PGND
Figure 42. 3.3-V, 1-A Power Supply
spacing
spacing
(3 .. 17)V
2.5V / 1A
2.2 µH
PVIN
SW
AVIN
VOS
100k
PG
EN
10uF
390k
22uF
TPS62150
FB
SS/TR
3.3nF
DEF
AGND
FSW
PGND
180k
Figure 43. 2.5-V, 1-A Power Supply
spacing
spacing
(3 .. 17)V
1.8V / 1A
2.2µH
10uF
PVIN
SW
AVIN
VOS
EN
100k
PG
22uF
TPS62151
SS/TR
3.3nF
FB
DEF
AGND
FSW
PGND
Figure 44. 1.8-V, 1-A Power Supply
spacing
spacing
26
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SLVSAL5C – NOVEMBER 2011 – REVISED OCTOBER 2015
System Examples (continued)
(3 .. 17)V
1.5V / 1A
2.2 µH
PVIN
SW
AVIN
VOS
100k
PG
EN
10uF
130k
22uF
TPS62150
FB
SS/TR
3.3nF
DEF
AGND
FSW
PGND
150k
Figure 45. 1.5-V, 1-A Power Supply
spacing
spacing
(3 .. 17)V
1.2V / 1A
2.2 µH
PVIN
SW
AVIN
VOS
100k
PG
EN
10uF
75k
22uF
TPS62150
FB
SS/TR
3.3nF
DEF
AGND
FSW
PGND
150k
Figure 46. 1.2-V, 1-A Power Supply
spacing
spacing
(3 .. 17)V
1V / 1A
2.2 µH
PVIN
SW
AVIN
VOS
PG
EN
10uF
100k
51k
22uF
TPS62150
SS/TR
3.3nF
FB
DEF
AGND
FSW
PGND
200k
Figure 47. 1-V, 1-A Power Supply
spacing
10 Power Supply Recommendations
The TPS6215x devices are designed to operate from a 3-V to 17-V input voltage supply. The output current of
the input power supply must be rated according to the output voltage and the output current of the power rail
application.
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11 Layout
11.1 Layout Guidelines
Proper layout is critical for the operation of a switched-mode power supply, even more at high switching
frequencies. Therefore, the PCB layout of the TPS6215x device demands careful attention to ensure operation
and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load),
stability and accuracy weaknesses, increased EMI radiation, and noise sensitivity.
See Figure 48 for the recommended layout of the TPS6215x device, which is designed for common external
ground connections. Both AGND (pin 6) and PGND (pins 15 and 16) are directly connected to the exposed
thermal pad. On the PCB, the direct common-ground connection of AGND and PGND to the exposed thermal
pad and the system ground (ground plane) is mandatory. Also, connect VOS (pin 14) in the shortest way to VOUT
at the output capacitor. To avoid noise coupling into the VOS line, this connection should be separated from the
VOUT power line and plane as shown in Layout Example.
Provide low-inductance and -resistance paths for loops with high di/dt. Paths conducting the switched load
current should be as short and wide as possible. Provide low-capacitance paths (with respect to all other nodes)
for wires with high dv/dt. The input and output capacitance should be placed as close as possible to the IC pins,
and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an
alternating current should outline an area as small as possible, as this area is proportional to the energy radiated.
Sensitive nodes like FB (pin 5) and VOS (pin 14) must be connected with short wires and not near high dv/dt
signals [for example, SW (pins 1, 2, and 3)]. As FB and VOS pins carry information about the output voltage,
they should be connected as closely as possible to the actual output voltage (at the output capacitor). The
capacitor on SS/TR (pin 9) and on AVIN (pin 19), as well as the FB resistors, R1 and R2, should be kept close to
the IC and connect directly to those pins and the system ground plane.
The exposed thermal pad must be soldered to the circuit board for mechanical reliability and to achieve adequate
power dissipation.
The recommended layout is implemented on the EVM and shown in its Users Guide, SLVU437. Additionally, the
EVM Gerber data are available for download here, SLVC394.
11.2 Layout Example
GND
R2
8
C
PVIN
AVIN
7
R1
6
5
9
4
10
3
11
2
12
1
13
CIN
14
15
PG
16
EN
L1
to GND
plane
VOUT
COUT
to
AGND
GND
Figure 48. TPS6215x Example Layout
28
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11.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks, and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB by soldering the exposed thermal pad
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the Thermal Characteristics of Linear and Logic
Packages Using JEDEC PCB Designs and Semiconductor and IC Package Thermal Metrics application reports,
SZZA017 and SPRA953, respectively.
The TPS6215x devices are designed for a maximum operating junction temperature (TJ) of 125°C. Therefore, the
maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance,
given by the package and the surrounding PCB structures. Because the thermal resistance of the package is
fixed, increasing the size of the surrounding copper area and improving the thermal connection to the IC can
reduce the thermal resistance. To get improved thermal behavior, it is recommended to use top-layer metal to
connect the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the
IC for improved thermal performance.
If short-circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
• Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor,
SLVA289
• Using the TPS62150 as Step-Down LED Driver With Dimming, SLVA451
• Optimizing the TPS62130/40/50/60/70 Output Filter, SLVA463
• Using a Feedforward Capacitor to Improve Stability and Bandwidth of TPS62130/40/50/60/70, SLVA466
• Using the TPS6215x in an Inverting Buck-Boost Topology, SLVA469
• TPS62130/40/50 Sequencing and Tracking, SLVA470
• Voltage Margining Using the TPS62130, SLVA489
• TPS62130EVM-505, TPS62140EVM-505, and TPS62150EVM-505 Evaluation Modules User's Guide,
SLVU437
• Semiconductor and IC Package Thermal Metrics, SPRA953
• Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs, SZZA017
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
Parts
Product Folder
Sample & Buy
Technical
Documents
Tools & Software
Support &
Community
TPS62150
Click here
Click here
Click here
Click here
Click here
TPS62150A
Click here
Click here
Click here
Click here
Click here
TPS62151
Click here
Click here
Click here
Click here
Click here
TPS62152
Click here
Click here
Click here
Click here
Click here
TPS62153
Click here
Click here
Click here
Click here
Click here
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
Space
Space
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SLVSAL5C – NOVEMBER 2011 – REVISED OCTOBER 2015
12.5 Trademarks
DCS-Control, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
Copyright © 2011–2015, Texas Instruments Incorporated
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PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
SCALE 3.600
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00
0.08
1.7 0.05
(0.2) TYP
5
12X 0.5
8
EXPOSED
THERMAL PAD
4
9
4X
1.5
1
12
16X
PIN 1 ID
(OPTIONAL)
16
13
0.5
16X
0.3
0.3
0.2
0.1
0.05
C A
B
4222419/A 10/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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SLVSAL5C – NOVEMBER 2011 – REVISED OCTOBER 2015
EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.7)
SYMM
13
16
16X (0.6)
1
12
16X (0.25)
SYMM
(0.6)
TYP
12X (0.5)
(2.8)
9
4
( 0.2) TYP
VIA
5
(R0.05)
ALL PAD CORNERS
8
(0.6) TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222419/A 10/2015
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.55)
16
13
16X (0.6)
1
12
16X (0.25)
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
SYMM
8
(R0.05) TYP
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
83% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4222419/A 10/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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27-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS62150ARGTR
ACTIVE
QFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
PA8I
TPS62150ARGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
PA8I
TPS62150RGTR
ACTIVE
QFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QUA
TPS62150RGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QUA
TPS62151RGTR
ACTIVE
QFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QWO
TPS62151RGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QWO
TPS62152RGTR
ACTIVE
QFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QWP
TPS62152RGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QWP
TPS62153RGTR
ACTIVE
QFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QWQ
TPS62153RGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QWQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jun-2014
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS62150A, TPS62152 :
• Automotive: TPS62150A-Q1, TPS62152-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Mar-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS62150ARGTR
QFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62150ARGTR
QFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62150ARGTT
QFN
RGT
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62150ARGTT
QFN
RGT
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62150RGTR
QFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62150RGTT
QFN
RGT
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62151RGTR
QFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62151RGTT
QFN
RGT
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62152RGTR
QFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62152RGTT
QFN
RGT
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62153RGTR
QFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62153RGTT
QFN
RGT
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Mar-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS62150ARGTR
QFN
RGT
16
3000
552.0
367.0
36.0
TPS62150ARGTR
QFN
RGT
16
3000
367.0
367.0
35.0
TPS62150ARGTT
QFN
RGT
16
250
552.0
185.0
36.0
TPS62150ARGTT
QFN
RGT
16
250
210.0
185.0
35.0
TPS62150RGTR
QFN
RGT
16
3000
367.0
367.0
35.0
TPS62150RGTT
QFN
RGT
16
250
210.0
185.0
35.0
TPS62151RGTR
QFN
RGT
16
3000
367.0
367.0
35.0
TPS62151RGTT
QFN
RGT
16
250
210.0
185.0
35.0
TPS62152RGTR
QFN
RGT
16
3000
367.0
367.0
35.0
TPS62152RGTT
QFN
RGT
16
250
210.0
185.0
35.0
TPS62153RGTR
QFN
RGT
16
3000
367.0
367.0
35.0
TPS62153RGTT
QFN
RGT
16
250
210.0
185.0
35.0
Pack Materials-Page 2
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