High-Definition Multimedia Interface (HDMI) IP Core User Guide

High-Definition Multimedia Interface (HDMI) IP Core User Guide
High-Definition Multimedia Interface
(HDMI) IP Core User Guide
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TOC-2
Contents
HDMI Quick Reference....................................................................................... 1-1
HDMI Overview.................................................................................................. 2-1
Resource Utilization.....................................................................................................................................2-5
HDMI Getting Started.........................................................................................3-1
Installing and Licensing IP Cores.............................................................................................................. 3-1
Specifying IP Core Parameters and Options............................................................................................ 3-2
HDMI Source.......................................................................................................4-1
Source Functional Description...................................................................................................................4-1
Source TMDS/TERC4 Encoder..................................................................................................... 4-2
Source Video Resampler................................................................................................................. 4-2
Source Window of Opportunity Generator..................................................................................4-7
Source Auxiliary Packet Encoder...................................................................................................4-8
Source Auxiliary Packet Generators............................................................................................4-10
Source Auxiliary Data Path Multiplexers................................................................................... 4-10
Source Auxiliary Control Port......................................................................................................4-10
Source Audio Encoder...................................................................................................................4-14
Source Interfaces........................................................................................................................................ 4-17
Source Clock Tree...................................................................................................................................... 4-21
HDMI Sink...........................................................................................................5-1
Sink Functional Description.......................................................................................................................5-1
Sink Channel Word Alignment and Deskew................................................................................5-2
Sink TMDS/TERC4 Decoder......................................................................................................... 5-3
Sink Video Resampler......................................................................................................................5-4
Sink Auxiliary Decoder................................................................................................................... 5-4
Sink Auxiliary Packet Capture........................................................................................................5-6
Sink Auxiliary Data Port................................................................................................................. 5-9
Sink Audio Decoding.................................................................................................................... 5-10
Sink Interfaces............................................................................................................................................ 5-14
Avalon-MM SCDC Management Interface................................................................................5-19
Status and Control Data Channel Interface................................................................................5-20
Sink Clock Tree.......................................................................................................................................... 5-20
HDMI Parameters............................................................................................... 6-1
HDMI Source Parameters...........................................................................................................................6-1
HDMI Sink Parameters............................................................................................................................... 6-2
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TOC-3
HDMI Design Example Parameters.......................................................................................................... 6-3
HDMI Hardware Demonstration....................................................................... 7-1
Hardware Demonstration Components................................................................................................... 7-1
Transceiver Native PHY (RX)........................................................................................................ 7-4
Altera PLL IP Cores......................................................................................................................... 7-8
Altera PLL Reconfig IP Core........................................................................................................ 7-10
Multirate Reconfig Controller (RX)............................................................................................ 7-10
Oversampler (RX)..........................................................................................................................7-11
DCFIFO...........................................................................................................................................7-12
Sink Display Data Channel (DDC) & Status and Control Data Channel (SCDC)...............7-12
Transceiver Reconfiguration Controller..................................................................................... 7-12
VIP Bypass and Audio, Auxiliary and InfoFrame Buffers........................................................7-13
Transceiver Native PHY (TX)...................................................................................................... 7-13
Transceiver PHY Reset Controller...............................................................................................7-15
Oversampler (TX)..........................................................................................................................7-15
Clock Enable Generator................................................................................................................ 7-16
Qsys System.................................................................................................................................... 7-16
HDMI Hardware Demonstration Requirements...................................................................................7-18
Demonstration Walkthrough................................................................................................................... 7-19
Set Up the Hardware......................................................................................................................7-19
Copy the Design Files....................................................................................................................7-20
Build and Compile the Design..................................................................................................... 7-20
View the Results............................................................................................................................. 7-20
HDMI Simulation Example................................................................................ 8-1
Simulation Walkthrough.............................................................................................................................8-2
HDMI IP Core User Guide Archives.................................................................. A-1
Document Revision History for HDMI User Guide.......................................... B-1
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The High-Definition Multimedia Interface (HDMI) IP core provides support for next-generation video
display interface technology.
Information
Release Information
Description
Version
16.1
Release
October 2016
Ordering Code
IP-HDMI
© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, NIOS, Quartus and Stratix words and logos are
trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
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HDMI Quick Reference
Information
IP Core Information
Description
Core Features
• Conforms to the High-​Definition Multimedia
Interface (HDMI) specification versions 1.4 and 2.0
• Supports transmitter and receiver on a single
device transceiver quad
• Supports pixel frequency up to 594 MHz
• Supports RGB and YCbCr 444, 422, and 420 color
modes
• Accepts standard H-SYNC, V-SYNC, data enable,
RGB video format, and YCbCr video format
• Supports 2-channel and 8-channel audios
• Supports 1, 2, or 4 symbols per clock
• Supports 8, 10, 12, or 16 bits per color (bpc)
• Supports Digital Visual Interface (DVI)
Typical Application
• Interfaces within a PC and monitor
• External display connections, including interfaces
between a PC and monitor or projector, between
a PC and TV, or between a device such as a DVD
player and TV display
Device Family
Supports Arria® 10, Arria V, and Stratix® V FPGA
devices
Design Tools
• Quartus® Prime software for IP design instantia‐
tion and compilation
• TimeQuest Timing Analyzer in the Quartus
Prime software for timing analysis
• ModelSim-Altera/SE software for design
simulation
Related Information
• HDMI IP Core Design Example User Guide
For more information about the Arria 10 HDMI design example.
• HDMI IP Core User Guide Archives on page 9-1
Provides a list of user guides for previous versions of the HDMI IP core.
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HDMI Overview
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The Altera High-Definition Multimedia Interface (HDMI) IP core provides support for next generation
video display interface technology.
The HDMI standard specifies a digital communications interface for use in both internal and external
connections:
• Internal connections—interface within a PC and monitor
• External display connections—interface between a PC and monitor or projector, between a PC and TV,
or between a device such a DVD player and TV display.
The HDMI system architecture consists of sinks and sources. A device may have one or more HDMI
inputs and outputs.
The HDMI cable and connectors carry four differential pairs that make up the Transition Minimized
Differential Signaling (TMDS) data and clock channels. You can use these channels to carry video, audio,
and auxiliary data.
The HDMI also carries a Video Electronics Standards Association (VESA) Display Data Channel (DDC)
and Status and Control Data Channel (SCDC). The DDC configures and exchanges status between a single
source and a single sink. The source uses the DDC to read the sink's Enhanced Extended Display Identifi‐
cation Data (E-EDID) to discover the sink's configuration and capabilities. The SCDC supports the sink's
read requests.
The optional Consumer Electronics Control (CEC) protocol provides high-level control functions between
various audio visual products in your environment.
The optional HDMI Ethernet and Audio Return Channel (HEAC) provides Ethernet compatible data
networking between connected devices and an audio return channel in the opposite direction of TMDS.
The HEAC also uses Hot-Plug Detect (HPD) line for signal transmission.
© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, NIOS, Quartus and Stratix words and logos are
trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
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HDMI Overview
Figure 2-1: Altera HDMI Block Diagram
The figure below illustrates the blocks in the Altera HDMI IP core.
HDMI IP Core
TDMS Channel 0
Video
Video
TDMS Channel 1
Audio
HDMI
Transmitter
TDMS Channel 2
Audio
HDMI
Receiver
TDMS Clock Channel
Control/Status
Control/Status
Status and Control Data Channel (SCDC)
Display Data Channel (DDC)
CEC
HEAC
Detect
CEC Line
Utility Line
HPD Line
EDID ROM
CEC
HEAC
High/Low
Based on TMDS encoding, the HDMI protocol allows the transmission of both audio and video data
between source and sink devices.
An HDMI interface consists of three color channels accompanied by a single clock channel. You can use
each color line to transfer both individual RGB colors and auxiliary data.
The receiver uses the TMDS clock as a frequency reference for data recovery on the three TMDS data
channels. This clock typically runs at the video pixel rate.
TMDS encoding is based on an 8-bit to 10-bit algorithm. This protocol attempts to minimize data channel
transmission and yet maintain sufficient bandwidth so that a sink device can lock reliably to the data
stream.
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Figure 2-2: HDMI Video Stream Data
Video
Guard
Band
Video
Preamble
Data Island
Preamble
Active Video
Active
Aux/Audio
Data Island
Guard
Band
Video
Guard
Band
Active Video
vid_de
aux_de
Video Guard Band
Case (TMDS Channel Number):
0:q_out[9:0] = 10’b1011001100;
1:q_out[9:0] = 10’b0100110011;
2:q_out[9:0] = 10’b1011001100;
endcase
Data Island Guard Band
Case (TMDS Channel Number):
0:q_out[9:0] = 10’bxxxxxxxxxx;
1:q_out[9:0] = 10’b0100110011;
2:q_out[9:0] = 10’b0100110011;
endcase
Video Preamble
{c3, c2, c1, c0} = 4’b0001
Data Island Preamble
{c3, c2, c1, c0} = 4’b0101
The figure above illustrates two data streams:
• Data stream in green—transports color data
• Data stream in dark blue—transports auxiliary data
Table 2-1: Video Data and Auxiliary Data
The table below describes the function of the video data and auxiliary data.
Data
Description
Video data
• Packed representation of the video pixels clocked at the source pixel clock.
• Encoded using the TMDS 8-bit to 10-bit algorithm.
Auxiliary data
• Transfers audio data together with a range of auxiliary data packets.
• Sink devices use auxiliary data packets to correctly reconstruct video and audio
data.
• Encoded using the TMDS Error Reduction Coding–4 bits (TERC4) encoding
algorithm.
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Each data stream section is preceded with guard bands and pre-ambles. The guard bands and pre-ambles
allow for accurate synchronization with received data streams.
The following figures show the arrangement of the video data, video data enable, video H-SYNC, and
video V-SYNC in 1, 2, and 4 symbols per clock.
Figure 2-3: Video Data, Video Data Valid, H-SYNC, and V-SYNC—1 Symbol per Clock
One Symbol per Clock
vid_clk
vid_data[47:0]
D0
D1
D2
D3
D4
D5
D6
D7
vid_de[0]
E0
E1
E2
E3
E4
E5
E6
E7
vid_hsync[0]
H0
H1
H2
H3
H4
H5
H6
H7
vid_vsync[0]
V0
V1
V2
V3
V4
V5
V6
V7
Figure 2-4: Video Data, Video Data Valid, H-SYNC, and V-SYNC—2 Symbols per Clock
Two Symbols per Clock
vid_clk
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vid_data[95:0]
D1
D0
D3
D2
D5
D4
D7
D6
vid_de[1:0]
E1
E0
E3
E2
E5
E4
E7
E6
vid_hsync[1:0]
H1
H0
H3
H2
H5
H4
H7
H6
vid_vsync[1:0]
V1
V0
V3
V2
V5
V4
V7
V6
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Resource Utilization
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Figure 2-5: Video Data, Video Data Valid, H-SYNC, and V-SYNC—4 Symbols per Clock
Four Symbols per Clock
vid_clk
vid_data[191:0]
D3
D2
D1
D0
D7
D6
D5
D4
vid_de[3:0]
E3
E2
E1
E0
E7
E6
E5
E4
vid_hsync[3:0]
H3
H2
H1
H0
H7
H6
H5
H4
vid_vsync[3:0]
V3
V2
V1
V0
V7
V6
V5
V4
Resource Utilization
The resource utilization data indicates typical expected performance for the HDMI IP core device.
Table 2-2: HDMI Data Rate
The table lists the maximum data rates for HDMI core configurations of 1, 2, and 4 symbols per clock.
Devices
Arria 10
Arria V GX
Stratix V
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Maximum Data Rate (Mbps)
1 Symbol per Clock
Not Supported
2 Symbols per Clock
5,940
(Example: 4Kp60 8bpc)
4 Symbols per Clock
Not Supported
1,875
3,276.8
5,940
(Example: 1080p60 10bpc)
(Example: 4Kp30 8bpc)
(Example: 4Kp60 8bpc)
5,800
5,940
(Example: 4Kp30 12bpc)
(Example: 4Kp60 8bpc)
Not Supported
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Resource Utilization
Table 2-3: Color Depth Supported for Each Video Format
Color Depth
Video Format
8
10
12
16
RGB
Yes
Yes
Yes
Yes
YCbCr 4:4:4
Yes
Yes
Yes
Yes
Not applicable
Not applicable
Yes
Not applicable
Yes
Yes
Yes
Yes
YCbCr 4:2:2(1)
YCbCr 4:2:0
Table 2-4: HDMI Resource Utilization
The table lists the performance data for the HDMI IP core targeting Arria 10, Arria V GX, and Stratix V
devices.
Device
Arria 10
Arria V GX
Stratix V
(1)
Symbols
per Clock
Direction
ALMs
2
RX
2
Logic Registers
Memory
Primary
Secondary
Bits
M10K or M20K
3,359
4,276
795
38,400
14
TX
3,374
5,014
1,543
12,680
13
1
RX
2,630
4,039
402
35,712
13
1
TX
2,700
4,462
417
11,108
11
2
RX
3,446
4,656
531
38,400
14
2
TX
3,759
6,091
450
12,680
13
4
RX
4,895
5,937
614
43,776
20
4
TX
6,135
9,156
445
15,824
18
1
RX
2,592
3,946
398
35,712
13
1
TX
2,634
4,415
461
11,108
11
2
RX
3,337
4,619
440
38,400
14
2
TX
3,644
5,919
680
12,680
13
According to section 6.5.1 of the HDMI 1.4b specifications, 8 and 10 bits per color use the same pixel
encoding as 12 bits per color, but the valid bits are left-justified with zeroes padding the bits below the least
significant bit.
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HDMI Getting Started
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This chapter provides a general overview of the Altera IP core design flow to help you quickly get started
with the HDMI IP core. The Altera IP Library is installed as part of the Quartus Prime installation process.
You can select and parameterize any Altera IP core from the library. Altera provides an integrated
parameter editor that allows you to customize the HDMI IP core to support a wide variety of applications.
The parameter editor guides you through the setting of parameter values and selection of optional ports.
Related Information
• Introduction to Altera IP Cores
Provides general information about all Altera FPGA IP cores, including parameterizing, generating,
upgrading, and simulating IP cores.
• Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for software or IP version upgrades.
• Project Management Best Practices
Guidelines for efficient management and portability of your project and IP files.
Installing and Licensing IP Cores
The Quartus Prime software includes the Altera FPGA IP Library. The library provides many useful IP
core functions for production use without additional license. You can fully evaluate any licensed Altera
FPGA IP core in simulation and in hardware until you are satisfied with its functionality and performance.
The HDMI IP core is part of the Altera MegaCore IP Library, which is distributed with the Quartus Prime
software and downloadable from the Altera web site.
Figure 3-1: HDMI Installation Path
Installation directory
ip - Contains the Altera IP Library
altera - Contains the Altera IP Library source code
altera_hdmi - Contains the HDMI IP core files
Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on
Linux it is <home directory>/altera/ <version number>.
© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, NIOS, Quartus and Stratix words and logos are
trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
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Specifying IP Core Parameters and Options
Figure 3-2: HDMI Installation Path
Installation directory
intelFPGA(_pro*)
quartus - Contains the Quartus Prime Software
ip - Contains the IP Library
altera - Contains the IP Library source code
altera_hdmi - Contains the HDMI IP core files
Note: The default IP installation directory on Windows is <drive>:\intelFPGA_pro\quartus\ip\
altera; on Linux it is <home directory>/intelFPGA_pro/quartus/ip/altera.
After you purchase a license for the HDMI IP core, you can request a license file from the licensing site
and install it on your computer. When you request a license file, Altera emails you a license.dat file.
If you do not have Internet access, contact your local Altera representative.
Related Information
• Altera Licensing Site
• Altera Software Installation and Licensing Manual
Specifying IP Core Parameters and Options
Follow these steps to specify the HDMI IP core parameters and options.
1. Create a Quartus Prime project using the New Project Wizard available from the File menu.
2. On the Tools menu, click IP Catalog.
3. Under Installed IP, double-click Library > Interface > Protocols > Audio&Video > HDMI.
The parameter editor appears.
4. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in
your project. If prompted, also specify the targeted Altera device family and output file HDL
preference. Click OK.
5. Specify parameters and options in the HDMI parameter editor:
• Optionally select preset parameter values. Presets specify all initial parameter values for specific
applications (where provided).
• Specify parameters defining the IP core functionality, port configurations, and device-specific
features.
• Specify options for generation of a timing netlist, simulation model, testbench, or example design
(where applicable).
• Specify options for processing the IP core files in other EDA tools.
6. Click Generate to generate the IP core and supporting files, including simulation models.
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7. Click Close when file generation completes.
8. Click Finish.
9. If you generate the HDMI IP core instance in a Quartus Prime project, you are prompted to add
Quartus Prime IP File (.qip) and Quartus Prime Simulation IP File (.sip) to the
current Quartus Prime project.
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Source Functional Description
The HDMI source core provides direct connection to the Transceiver Native PHY through a 10-bit, 20-bit,
or 40-bit parallel data path.
Figure 4-1: HDMI Source Signal Flow Diagram
The figure below shows the flow of the HDMI source signals. The figure shows the various clocking
domains used within the core.
mode
vid_clk
Video Data
Port
Video
Input
Video
Resampler
V-SYNC
WOP
Generator
TMDS/TERC4
Encoder
TMDS Data
CC
color-depth
Multiplexer
Auxiliary Control
Port
Override
GCP
Default
GCP
Auxiliary Packet
Generator
Override
AV
Default AV
Infoframe
Auxiliary Packet
Generator
Override
VSI
Default VSI
Infoframe
Auxiliary Packet
Generator
Clock Domains
pp
aux_de
audio_clk
vid_clk
ls_clk
Multiplexer
Auxiliary
Data Port
1
Audio Port
Audio
Encoder
Auxiliary Packet
Generator
Auxiliary
Packet Encoder
The source core provides four 10-bit, 20-bit or 40-bit parallel data paths corresponding to the 3 color
channels and the clock channel.
© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, NIOS, Quartus and Stratix words and logos are
trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
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Source TMDS/TERC4 Encoder
The source core accepts video, audio, and auxiliary channel data streams. The core produces a TMDS/
TERC4 encoded data stream that would typically connect to the high-speed transceiver parallel data
inputs.
Central to the core is the TMDS/TERC4 encoder. The encoder processes either video or auxiliary data.
Source TMDS/TERC4 Encoder
The source TMDS/TERC4 encoder implements 8-bit to 10-bit and 4-bit to 10-bit algorithms as defined in
the HDMI Specification Ver.2.0. Each channel has its own encoder.
The encoder processes symbol data at 1, 2, or 4 symbols per clock.
When the encoder operates in 2 or 4 symbols per clock, it also produces the output in the form of two or
four encoded symbols per clock.
The TMDS/TERC4 encoder also produces digital visual interface (DVI) signaling when you deassert the
mode input signal. DVI signaling is identical to HDMI signaling, except for the absence of data and video
islands and TERC4 auxiliary data.
Source Video Resampler
The core resamples the video data based on the current color depth.
The video resampler consists of a gearbox and a dual-clock FIFO (DCFIFO).
Figure 4-2: Source Video Resampler Signal Flow Diagram
The figure below shows the components of the video resampler and the signal flow between these
components.
H-SYNC
V-SYNC
de
r[15:0]
g[15:0]
b[15:0]
1
vid_clk
data
q
Gearbox
DCFIFO
wr
wrclk
rd
rdclk
Phase
Counter
Resampled
H-SYNC
V-SYNC
de
r[7:0]
g[7:0]
b[7:0]
packing-phase (pp)
bits per pixel (bpp)
ls_clk
The resampler adheres to the recommended phase encoding method described in HDMI Specification Ver.
1.4b.
• The phase counter must register the last packing-phase (pp) of the last pixel of the last active line.
• The resampler then transmits the pp value to the attached sink device in the General Control Packet
(GCP) for packing synchronization.
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Source Video Resampler
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Figure 4-3: RGB 4:4:4 Mapped to the Respective TMDS Channels
The R, G, and B components of the first pixel for a given line of video are transferred on the first pixel of
the video data period following the Guard Band characters.
Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 04
TMDS
Channel
...
0
B0
B1
B2
B3
B4
...
1
G0
G1
G2
G3
G4
...
2
R0
R1
R2
R3
R4
...
Figure 4-4: YCbCr 4:4:4 Mapped to the Respective TMDS Channels
Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 04
TMDS
Channel
...
0
Cb0
Cb1
Cb2
Cb3
Cb4
...
1
Y0
Y1
Y2
Y3
Y4
...
2
Cr0
Cr1
Cr2
Cr3
Cr4
...
Figure 4-5: Source Pixel Data Input Format RGB/YCbCr 4:4:4
The figure below shows the RGB color space pixel bit-field mappings.
24 bpp RGB/YCbCr 4:4:4 (8 bpc)
30 bpp RGB/YCbCr 4:4:4 (10 bpc)
36 bpp RGB/YCbCr 4:4:4 (12 bpc)
48 bpp RGB/YCbCr 4:4:4 (16 bpc)
47
32
31
16
15
0
vid_data[47:0]
Figure 4-6: YCbCr 4:2:2 Mapped to the Respective TMDS Channels
Y0 / Cb0
Y1 / Cr0
Y2 / Cb2
Y3 / Cr2
Y4 / Cb4
...
Y0 bits 3 - 0
Cb0 bits 3 - 0
Y1 bits 3 - 0
Cr0 bits 3 - 0
Y2 bits 3 - 0
Cb2 bits 3 - 0
Y3 bits 3 - 0
Cr2 bits 3 - 0
Y4 bits 3 - 0
Cb4 bits 3 - 0
...
...
Y0 bits 11 - 4 Y1 bits 11 - 4 Y2 bits 11 - 4 Y3 bits 11 - 4 Y4 bits 11 - 4
...
2 Bits 7 - 0 Cb0 bits 11 - 4 Cr0 bits 11 - 4 Cb2 bits 11 - 4 Cr2 bits 11 - 4 Cb4 bits 11 - 4
...
0
TMDS
Channel
HDMI Source
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Bits 3 - 0
Bits 7 - 4
1 Bits 7 - 0
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Source Video Resampler
The higher order 8 bits of the Y samples are mapped to the 8 bits of Channel 1 and the lower order 4 bits
are mapped to the lower order 4 bits of Channel 0.
The first pixel transmitted within a Video Data Period contains three components, Y0, Cb0 and Cr0. The
Y0 and Cb0 components are transmitted during the first pixel period while Cr0 is transmitted during the
second pixel period. This second pixel period also contains the only component for the second pixel, Y1.
In this way, the link carries one Cb sample for every two pixels and one Cr sample for every two pixels.
These two components (Cb and Cr) are multiplexed onto the same signal paths on the link.
Figure 4-7: Source Pixel Data Input Format YCbCr 4:2:2—12 bpc
47
40
31
Cb/Cr[11:4]
24
15
8
0
Y[11:4]
Cb/Cr[3:0]
Y[3:0]
The 4:2:2 data requires only two components per pixel. Therefore, each component is allocated more bits.
The available 24 bits are split into 12 bits for the Y component and 12 bits for C components.
Figure 4-8: YCbCr 4:2:0 Mapped to the Respective TMDS Channels
Line 0
Pixel 00
Pixel 01
TMDS
Channel
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Pixel 04
Pixel 05
Pixel 06
Pixel 07
Pixel 08
Pixel 09
...
0
Cb00
Cb02
Cb04
Cb06
Cb08
...
1
Y00
Y02
Y04
Y06
Y08
...
2
Y01
Y03
Y05
Y07
Y09
...
Pixel 12
Pixel 13
Pixel 14
Pixel 15
Pixel 16
Pixel 17
Pixel 18
Pixel 09
...
Line 1
Pixel 10
Pixel 11
TMDS
Channel
Pixel 02
Pixel 03
0
Cr00
Cr02
Cr04
Cr06
Cr08
...
1
Y10
Y12
Y14
Y16
Y18
...
2
Y11
Y13
Y15
Y17
Y19
...
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Mapping Formats
4-5
The two horizontally successive 8-bit Y components are transmitted in TMDS Channels 1 and 2, in that
order. The 8-bit Cb or Cr components are transmitted alternately in TMDS Channel 0, line by line.
Mapping Formats
The following figures illustrate the mapping of different formats.
Figure 4-9: Mapping Two 8-Bit per Component YCbCr 4:2:0 to One 24-Bit YCbCr 4:4:4 Pixel (Pre Deep Color
Packing)
First 8 YCbCr 4:2:0 Pixels on Each Line
Line 0
Line 1
Line 2
Line 3
HDMI Source
Send Feedback
Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Channel 2
Equivalent
YCbCr 4:4:4 Pixel
Cb[7:0]
Y[7:0]
Cr[7:0]
Cb[7:0]
Y[7:0]
Cr[7:0]
Cb[7:0]
Y[7:0]
Cr[7:0]
Cb[7:0]
Y[7:0]
Cr[7:0]
YCbCr 4:2:0
Pixel 0/1
Cb00[7:0]
Y00[7:0]
Y01[7:0]
Cr00[7:0]
Y10[7:0]
Y11[7:0]
Cb20[7:0]
Y20[7:0]
Y21[7:0]
Cr20[7:0]
Y30[7:0]
Y31[7:0]
YCbCr 4:2:0
Pixel 2/3
Cb02[7:0]
Y02[7:0]
Y03[7:0]
Cr02[7:0]
Y12[7:0]
Y13[7:0]
Cb22[7:0]
Y22[7:0]
Y23[7:0]
Cr22[7:0]
Y32[7:0]
Y33[7:0]
YCbCr 4:2:0
Pixel 4/5
Cb04[7:0]
Y04[7:0]
Y05[7:0]
Cr04[7:0]
Y14[7:0]
Y15[7:0]
Cb24[7:0]
Y24[7:0]
Y25[7:0]
Cr24[7:0]
Y34[7:0]
Y35[7:0]
YCbCr 4:2:0
Pixel 6/7
Cb06[7:0]
Y06[7:0]
Y07[7:0]
Cr06[7:0]
Y16[7:0]
Y17[7:0]
Cb26[7:0]
Y26[7:0]
Y27[7:0]
Cr26[7:0]
Y36[7:0]
Y37[7:0]
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Mapping Formats
Figure 4-10: Mapping Two 10-Bit per Component YCbCr 4:2:0 to One 30-Bit YCbCr 4:4:4 Pixel (Pre Deep
Color Packing)
First 10 YCbCr 4:2:0 Pixels on Each Line
Line 0
Line 1
Line 2
Line 3
Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Channel 2
Equivalent
YCbCr 4:4:4 Pixel
Cb[9:0]
Y[9:0]
Cr[9:0]
Cb[9:0]
Y[9:0]
Cr[9:0]
Cb[9:0]
Y[9:0]
Cr[9:0]
Cb[9:0]
Y[9:0]
Cr[9:0]
YCbCr 4:2:0
Pixel 0/1
Cb00[9:0]
Y00[9:0]
Y01[9:0]
Cr00[9:0]
Y10[9:0]
Y11[9:0]
Cb20[9:0]
Y20[9:0]
Y21[9:0]
Cr20[9:0]
Y30[9:0]
Y31[9:0]
YCbCr 4:2:0
Pixel 2/3
Cb02[9:0]
Y02[9:0]
Y03[9:0]
Cr02[9:0]
Y12[9:0]
Y13[9:0]
Cb22[9:0]
Y22[9:0]
Y23[9:0]
Cr22[9:0]
Y32[9:0]
Y33[9:0]
YCbCr 4:2:0
Pixel 4/5
Cb04[9:0]
Y04[9:0]
Y05[9:0]
Cr04[9:0]
Y14[9:0]
Y15[9:0]
Cb24[9:0]
Y24[9:0]
Y25[9:0]
Cr24[9:0]
Y34[9:0]
Y35[9:0]
YCbCr 4:2:0
Pixel 6/7
Cb06[9:0]
Y06[9:0]
Y07[9:0]
Cr06[9:0]
Y16[9:0]
Y17[9:0]
Cb26[9:0]
Y26[9:0]
Y27[9:0]
Cr26[9:0]
Y36[9:0]
Y37[9:0]
Figure 4-11: Mapping Two 12-Bit per Component YCbCr 4:2:0 to One 36-Bit YCbCr 4:4:4 Pixel (Pre Deep
Color Packing)
First 12 YCbCr 4:2:0 Pixels on Each Line
Line 0
Line 1
Line 2
Line 3
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Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Channel 2
Equivalent
YCbCr 4:4:4 Pixel
Cb[11:0]
Y[11:0]
Cr[11:0]
Cb[11:0]
Y[11:0]
Cr[11:0]
Cb[11:0]
Y[11:0]
Cr[11:0]
Cb[11:0]
Y[11:0]
Cr[11:0]
YCbCr 4:2:0
Pixel 0/1
Cb00[11:0]
Y00[11:0]
Y01[11:0]
Cr00[11:0]
Y10[11:0]
Y11[11:0]
Cb20[11:0]
Y20[11:0]
Y21[11:0]
Cr20[11:0]
Y30[11:0]
Y31[11:0]
YCbCr 4:2:0
Pixel 2/3
Cb02[11:0]
Y02[11:0]
Y03[11:0]
Cr02[11:0]
Y12[11:0]
Y13[11:0]
Cb22[11:0]
Y22[11:0]
Y23[11:0]
Cr22[11:0]
Y32[11:0]
Y33[11:0]
YCbCr 4:2:0
Pixel 4/5
Cb04[11:0]
Y04[11:0]
Y05[11:0]
Cr04[11:0]
Y14[11:0]
Y15[11:0]
Cb24[11:0]
Y24[11:0]
Y25[11:0]
Cr24[11:0]
Y34[11:0]
Y35[11:0]
YCbCr 4:2:0
Pixel 6/7
Cb06[11:0]
Y06[11:0]
Y07[11:0]
Cr06[11:0]
Y16[11:0]
Y17[11:0]
Cb26[11:0]
Y26[11:0]
Y27[11:0]
Cr26[11:0]
Y36[11:0]
Y37[11:0]
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Source Window of Opportunity Generator
4-7
Figure 4-12: Mapping Two 16-Bit per Component YCbCr 4:2:0 to One 48-Bit YCbCr 4:4:4 Pixel (Pre Deep
Color Packing)
First 16 YCbCr 4:2:0 Pixels on Each Line
Line 0
Line 1
Line 2
Line 3
Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Channel 2
Equivalent
YCbCr 4:4:4 Pixel
Cb[15:0]
Y[15:0]
Cr[15:0]
Cb[15:0]
Y[15:0]
Cr[15:0]
Cb[15:0]
Y[15:0]
Cr[15:0]
Cb[15:0]
Y[15:0]
Cr[15:0]
YCbCr 4:2:0
Pixel 0/1
Cb00[15:0]
Y00[15:0]
Y01[15:0]
Cr00[15:0]
Y10[15:0]
Y11[15:0]
Cb20[15:0]
Y20[15:0]
Y21[15:0]
Cr20[15:0]
Y30[15:0]
Y31[15:0]
YCbCr 4:2:0
Pixel 2/3
Cb02[15:0]
Y02[15:0]
Y03[15:0]
Cr02[15:0]
Y12[15:0]
Y13[15:0]
Cb22[15:0]
Y22[15:0]
Y23[15:0]
Cr22[15:0]
Y32[15:0]
Y33[15:0]
YCbCr 4:2:0
Pixel 4/5
Cb04[15:0]
Y04[15:0]
Y05[15:0]
Cr04[15:0]
Y14[15:0]
Y15[15:0]
Cb24[15:0]
Y24[15:0]
Y25[15:0]
Cr24[15:0]
Y34[15:0]
Y35[15:0]
YCbCr 4:2:0
Pixel 6/7
Cb06[15:0]
Y06[15:0]
Y07[15:0]
Cr06[15:0]
Y16[15:0]
Y17[15:0]
Cb26[15:0]
Y26[15:0]
Y27[15:0]
Cr26[15:0]
Y36[15:0]
Y37[15:0]
Source Window of Opportunity Generator
The source Window of Opportunity (WOP) generator creates valid data islands within the blanking
regions.
During active line region, the WOP generator creates a leading region to hold at least 12 period symbols
that include eight preamble symbols. The generator also creates a trailing region to hold two data island
trailing guard band symbols, at least 12 control period symbols that include eight preamble symbols and
two video leading guard band symbols.
During vertical blanking region, the source cannot send more than 18 auxiliary packets consecutively. The
WOP generator deasserts the data island output enable (aux_de) line after every 18th auxiliary packet for
32-symbol clocks.
The WOP generator also has an integral number of auxiliary packet cycles: 24 clocks when processing in
1-symbol mode, 16 clocks when processing in 2-symbol mode, and 8 clocks when processing in 4-symbol
mode.
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Source Auxiliary Packet Encoder
Figure 4-13: Typical Window of Opportunity
The figure below shows a typical output from the WOP generator.
Video Data Enable
V Sync
H Sync
Data Island Output Enable
Vertical
Blanking
Control Period
Data Island Guard Band
Active
Video
Video Guard Band
Horizontal
Blanking
Active
Video
Data Island
Source Auxiliary Packet Encoder
Auxiliary packets are encoded by the source auxiliary packet encoder.
The auxiliary packets originate from a number of sources, which are multiplexed into the auxiliary packet
encoder in a round-robin schedule. The auxiliary packet encoder converts a standard stream into the
channel data format required by the TERC4 encoder.
The source propagates the WOP signal backwards through the stream ready signal.
The auxiliary packet encoder also calculates and inserts the Bose-Chaudhuri-Hocquenghem (BCH) error
correction code.
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Source Auxiliary Packet Encoder
4-9
Figure 4-14: Auxiliary Packet Encoder Input
The figure below shows the auxiliary packet encoder input from a 72-bit input data.
Phase 0
Phase 1
Phase 2
Phase 3
PB24
PB26
0
PB21
PB23
PB25
PB27
PB15
PB17
PB19
0
PB14
PB16
PB18
PB20
PB8
PB10
PB12
0
PB7
PB9
PB11
PB13
PB1
PB3
PB5
0
PB0
PB2
PB4
PB6
HB1
HB2
0
Phase 1
Phase 2
Phase 3
Byte[8]
PB22
Input Data
HB0
Byte[0]
BCH Block 3
BCH Block 2
BCH Block 1
BCH Block 0
Startofpacket
Endofpacket
Ready
Phase 0
Clock
Cycle 1 Symbol
0
-
-
8
-
-
16
-
-
24
Cycle 2 Symbol
0
-
-
4
-
-
8
-
-
12
Cycle 4 Symbol
0
-
-
2
-
-
4
-
-
6
The encoder assumes the data valid input will remain asserted for the duration of a packet to complete. A
packet is always 24 clocks (in 1-symbol mode), 12 clocks (in 2-symbol mode), or 6 clocks (in 4-symbol
mode).
The encoder creates a NULL auxiliary packet if it doesn't detect a start-of-packet at the beginning of a
packet boundary. In this case, you can consider the output of the encoder as a stream of NULL packets
unless a valid packet is available.
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Source Auxiliary Packet Generators
Figure 4-15: Typical Auxiliary Packet Stream During Blanking Interval
The figure below shows a typical auxiliary packet stream in 1-symbol per clock mode, where 0 denotes a
null packet.
Ninth Packet
Skipped
wop
Auxiliary Packet
Clock Cycle
0
0
0
23
47
0
71
0
AVI
0
AI VSI
0
0
0
.......
AVI = Auxiliary Video Infoframe
AI = Audio Information Infoframe
VSI = Vendor Specific Infoframe
Source Auxiliary Packet Generators
The source core uses various auxiliary packet generators. The packet generators convert the packet field
inputs to the auxiliary packet stream format.
The packet generator propagates backpressure from the output ready signal to the input ready signal. The
generator asserts the input valid signal when a packet is ready to be transmitted. The input valid signal
remains asserted until the generator receives a ready acknowledgment.
Source Auxiliary Data Path Multiplexers
The auxiliary data path multiplexers provide paths for the various auxiliary packet generators.
The various auxiliary packet generators traverse a multiplexed routing path to the auxiliary packet
encoder. The multiplexers obey a round-robin schedule and propagate backpressure.
Source Auxiliary Control Port
To simplify the user logic, the source core has control ports to send the most common auxiliary control
packets.
These packets are: General Control Packet, Auxiliary Video Information (AVI) InfoFrame, HDMI Vendor
Specific InfoFrame (VSI), and Audio InfoFrame.
The core sends the default values in the auxiliary packets. The default values allow the core to send video
data compatible with the HDMI Specification Ver.1.4b with minimum description.
You can also override the generators using the customized input values. The override values replace the
default values when the input checksum is non-zero.
The core sends the auxiliary control packets on the active edge of the V-SYNC signal to ensure that the
packets are sent once per field.
Source General Control Packet
Table 4-1: Source General Control Packet Input Fields
This table lists the controllable bit-fields for the Source General Control Packet port.
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Source Auxiliary Video Information (AVI) InfoFrame
Bit Field
Name
Color
gcp[3:0]
Depth (CD)
4-11
Comment
CD3
CD2
CD1
CD0
0
0
0
0
Color depth not indicated
0
0
0
1
Reserved
0
0
1
0
Reserved
0
0
1
1
Reserved
0
1
0
0
8 bpc or 24 bits per pixel
(bpp)
0
1
0
1
10 bpc or 30 bpp
0
1
1
0
12 bpc or 36 bpp
0
1
1
1
16 bpc or 48 bpp
1
1
1
1
Reserved
gcp[4]
Set_
AVMUTE
Refer to HDMI Specification Ver.1.4b.
gcp[5]
Clear_
AVMUTE
Refer to HDMI Specification Ver.1.4b.
Color depth
All other fields for the source GCP, (for example, pixel packing) are calculated automatically inside the
core. You must provide the bit-field value in the table above through the source GCP port. The GCP on the
auxiliary data port will always be filtered.
Source Auxiliary Video Information (AVI) InfoFrame
The HDMI core produces the captured AVI InfoFrame to simplify user applications.
Table 4-2: Auxiliary Video Information (AVI) InfoFrame
The table below lists the bit-fields for the AVI InfoFrame port bundle.
The signal bundle is clocked by ls_clk.
Bit-field
Name
7:0
Checksum
9:8
S
Scan information
11:10
B
Bar info data valid
12
A0
Active information present
14:13
Y
RGB or YCbCr indicator
15
Reserved
19:16
R
Active format aspect ratio
21:20
M
Picture aspect ratio
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Comment
Checksum
Returns 0
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Source HDMI Vendor Specific InfoFrame (VSI)
Bit-field
Name
Comment
23:22
C
Colorimetry (for example: ITU BT.601, BT.
709)
25:24
SC
Non-uniform picture scaling
27:26
Q
Quantization range
30:28
EC
Extended colorimetry
31
ITC
IT content
38:32
VIC
Video format identification code
39
Reserved
43:40
PR
Picture repetition factor
45:44
CN
Content type
47:46
YQ
YCC quantization range
63:48
ETB
Line number of end of top bar
79:64
SBB
Line number of start of bottom bar
95:80
ELB
Pixel number of end of left bar
111:96
SRB
Pixel number of start of right bar
112
Control
Returns 0
Disables the core from inserting the
InfoFrame packet.
• 1: The core does not insert info_
avi[111:0]. The AVI InfoFrame packet
on the auxiliary data port passes through.
• 0: The core inserts info_avi[111:0]
when checksum field (info_avi[7:0]) is
non-zero. The core sends default values
when checksum field (info_avi[7:0]) is
zero. The core filters the AVI InfoFrame
packet on the auxiliary data port.
Source HDMI Vendor Specific InfoFrame (VSI)
The core transmits a HDMI Vendor Specific InfoFrame once per field.
Table 4-3: HDMI Vendor Specific InfoFrame Bit-Fields
The table below lists the bit-fields for VSI.
The signal bundle is clocked by ls_clk.
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Bit-field
Name
4:0
Length
Comment
Length = Nv
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Source Audio InfoFrame (AI)
Bit-field
Name
12:5
Checksum
36:13
IEEE
41:37
Reserved
44:42
HDMI_Video_Format
52:45
HDMI_VIC
57:53
Reserved
60:58
3D_Ext_Data
61
Control
4-13
Comment
Checksum
24-bit IEEE registration identified
(0×000C03)
All 0
HDMI video format
HDMI proprietary video format
identification code
All 0
3D extended data
Disables the core from inserting the
InfoFrame packet.
• 1: The core does not insert info_
vsi[60:0]. The VSI InfoFrame
packet on the auxiliary data port
passes through.
• 0: The core inserts info_
vsi[60:0] when checksum field
(info_vsi[12:5]) is non-zero.
The core sends default values
when checksum field (info_
vsi[12:5]) is zero. The core filters
the VSI InfoFrame packet on the
auxiliary data port.
Note: If the checksum input to the port is zero, the core uses a default value of zero for each bit-field.
Source Audio InfoFrame (AI)
The core transmits an Audio InfoFrame once per field.
Table 4-4: Source Audio InfoFrame Bundle Bit-Fields
The table below lists the signal bit-fields.
The signal bundle is clocked by ls_clk.
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Bit-field
Name
7:0
Checksum
10:8
CC
11
Reserved
15:12
CT
Comment
Checksum
Channel count
Returns 0
Audio format type
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Source Audio Encoder
Bit-field
Name
17:16
SS
Bits per audio sample
20:18
SF
Sampling frequency
23:21
Reserved
31:24
CXT
Audio format type of the audio
stream
39:32
CA
Speaker location allocation FL, FR
41:40
LFEPBL
LFE playback level information, dB
42
Reserved
Returns 0
46:43
LSV
47
DM_INH
48
Comment
Returns 0
Level shift information, dB
Down-mix inhibit flag
Disables the core of the InfoFrame
packets from inserting.
• 1: The core does not insert audio_
info_ai[47:0]. The Audio
InfoFrame packet on the auxiliary
data port passes through.
• 0: The core inserts audio_info_
ai[47:0] when checksum field
(audio_info_ai[7:0]) is nonzero. The core sends default values
when checksum field (audio_
info_ai[7:0]) is zero. The core
filters the Audio InfoFrame packet
on the auxiliary data port.
Note: If the checksum input to the port is zero, the core uses a default value of zero for each bit-field.
Source Audio Encoder
Audio transport requires three packet types: Audio Timestamp InfoFrame, Audio Information InfoFrame,
and Audio Sample Data.
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Source Audio Encoder
4-15
Figure 4-16: Source Audio Encoder
Timestamp
Scheduler
Multiplexer
Auxiliary Packet
Generator
CTS, N
Audio Data
Port
V-SYNC
Default AI
Default AI
Auxiliary Packet
Generator
1
Auxiliary Packet
Generator
Audio
Packetizer
DCFIFO
Audio Input
Audio
Auxiliary
Stream
Audio Format
Auxiliary Packet
Generator
Audio Metadata
The Audio Timestamp InfoFrame packet contains the CTS and N values. You need to provide these values.
The core schedules this packet to be sent every ms. The scheduler uses the audio_clk and N value to
determine a 1-ms interval.
The core sends the Audio Information InfoFrame packet on the active edge of the V-SYNC signal.
The Audio Sample Data packet queues on a DCFIFO. The core also uses the DCFIFO to synchronize its
clock to ls_clk. The Audio Packetizer packs the audio sample data into the Audio Sample packets
according to the specified audio format. An Audio Sample packet can contain up to 4 audio samples,
based on the required audio sample clock. The core sends the Audio Sample packets whenever there is an
available slot in the auxiliary packet stream.
The audio_data port is always at a fixed value of 256 bits and the audio_de port is always fixed to 1 bit.
For audio channels fewer than 8, insert 0 to the audio data of the unused audio channels.
The 32-bit audio data is packed in IEC-60958 standard. The least significant word is the left channel
sample.
Figure 4-17: Audio Data Packing
31
SP
24
x
x
B
P
C
U
V
0
Audio Sample
The fields are defined as:
SP
x
B
P
C
U
V
HDMI Source
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:
:
:
:
:
:
:
Sample Present
Not Used
Start of 192-bit IEC-60958 Channel Status
Parity Bit
Channel Status
User Data Bit
Valid Bit
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HDMI Audio Format
The Audio Timestamp InfoFrame and Audio Sample Data packets on the Auxiliary Data Port are not
filtered by the source. You must filter these packets externally if you want to loop back the auxiliary data
stream from the sink. The Audio Information InfoFrame packet on the Auxiliary Data Port will be filtered
by the source if the most significant bit of audio_info_ai port is set to 0.
HDMI Audio Format
The HDMI IP core uses the HDMI audio formats to transport payload data.
Table 4-5: Definition of HDMI Audio Format
Value
Name
Description
0
Linear Pulse-Code Modulation
(LPCM)
HDMI packet type 2 transports payload data
1
One-Bit Audio
HDMI packet type 7 transports payload data (not
supported)
2
Direct Stream Transport (DST)
Audio
HDMI packet type 8 transports payload data (not
supported)
3
High Bit Rate (HBR)
HDMI packet type 9 transports payload data
4
3D (LPCM)
HDMI packet type 11 transports payload data (not
supported)
5
3D (One-Bit)
HDMI packet type 12 transports payload data (not
supported)
6
Multi-Stream Audio (MST) for
LPCM
HDMI packet type 14 transports payload data
7
MST for One-Bit Audio
HDMI packet type 15 transports payload data (not
supported)
8–15
—
Reserved
In the LPCM format, the HDMI source accepts 2 to 8 channels. . The Sample Present bit determines
whether to use 2-channel or 8-channel layout. If the Sample Present bit from Channel 0 or 1 is high,
then audio interface uses the 2-channel layout. If otherwise, the audio interface uses the 8-channel layout.
The IP core ignores the Parity, Channel Status, User Data, and Valid bits if the Sample Present bit is
0.
In the HBR format, the sample packet data is identical to the LPCM format. In HBR mode, the HDMI
source transmits 8 samples per clock. The core transmits the HBR audio packets using AUX packet header
number 9.
In the MST format, the sample packet data is also identical to the LPCM format. The MST mode enables a
source to send up to 4 streams of audio to a sink device. The HDMI source sends 1, 2, or 4 streams. When
the source sends fewer than 4 streams, you must set the input audio data to zero.
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Source Interfaces
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Figure 4-18: MST Audio Format
4 Streams
2 Streams
1 Stream
ST3-L
0
0
ST3-R
0
0
ST2-L
0
0
ST2-R
0
0
ST1-L
ST1-L
0
ST1-R
ST1-R
0
ST0-L
ST0-L
ST0-L
ST0-R
ST0-R
ST0-R
Source Interfaces
The table lists the source's port interfaces.
Table 4-6: Source Interfaces
N is the number of symbols per clock.
Interface
Reset
Port Type
Reset
HDMI Source
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Clock
Domain
N/A
Port
reset
Direction
Input
Description
Main asynchronous
reset input.
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Source Interfaces
Interface
Port Type
Clock
Clock
Domain
N/A
Port
ls_clk
Direction
Input
Description
Link speed clock
input.
8/8 (1x), 10/8 (1.25x),
12/8 (1.5x), or 16/8
(2x) times the vid_clk
according to color
depth.
This signal connects to
the transceiver output
clock.
Clock
Clock
N/A
vid_clk
Input
Video data clock
input.
• 1 symbol per clock
mode = video pixel
clock
• 2 symbols per clock
mode = half the
pixel clock
• 4 symbols per clock
mode = quarter the
pixel clock
Clock
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N/A
audio_clk
Input
Audio clock input.
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Source Interfaces
Interface
Port Type
Conduit
Clock
Domain
vid_clk
Port
vid_data[N*48-1:0]
Direction
Input
Description
Video 48-bit pixel data
input port.
• In 2 symbols per
clock (N=2) mode,
this port accepts
two 48-bit pixels
per clock.
• In 4 symbols per
clock (N=4) mode,
this port accepts
four 48-bit pixels
per clock.
Video
Data
Port
TMDS
Data
Port
4-19
Conduit
vid_clk
vid_de[N-1:0]
Input
Video data enable
input that indicates
active picture region.
Conduit
vid_clk
vid_hsync[N-1:0]
Input
Video horizontal sync
input.
Conduit
vid_clk
vid_vsync[N-1:0]
Input
Video vertical sync
input.
Conduit
ls_clk
out_b[10*N-1:0]
Output
TMDS encoded blue
channel output.
Conduit
ls_clk
out_r[10*N-1:0]
Output
TMDS encoded red
channel output.
Conduit
ls_clk
out_g[10*N-1:0]
Output
TMDS encoded green
channel output.
Conduit
ls_clk
out_c[10*N-1:0]
Output
TMDS encoded clock
channel output.
Conduit
ls_clk
aux_ready
Output
Auxiliary data channel
valid output.
Conduit
ls_clk
aux_valid
Input
Auxiliary data channel
valid input.
ls_clk
aux_data[71:0]
Input
Auxiliary data channel
data input.
ls_clk
aux_sop
Input
Auxiliary data channel
start-of-packet input.
ls_clk
aux_eop
Input
Auxiliary data channel
end-of-packet input.
Auxiliar
Conduit
y Data
Port
Conduit
Conduit
HDMI Source
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Source Interfaces
Interface
Port Type
Conduit
Clock
Domain
ls_clk
Port
mode
Direction
Input
Description
Encoding mode input.
• 0 = DVI
• 1 = HDMI
Conduit
ls_clk
TMDS_Bit_clock_Ratio
Input
Encoder
Control Conduit
Port
• 0 = (TMDS bit
period) / (TMDS
clock period) ratio
is 1/10
• 1 = (TMDS bit
period) / (TMDS
clock period) ratio
is 1/40
ls_clk
Scrambler_Enable
Input
• 0 = Instructs the
source device not
to perform
scrambling
• 1 = Instructs the
source device to
perform
scrambling
Conduit
ls_clk
ctrl[6*N-1:0]
Input
DVI control side-band
inputs to override the
necessary control and
synchronization data
in the green and red
channels.
Conduit
audio_clk
audio_CTS[19:0]
Input
Audio CTS value
input.
Conduit
audio_clk
audio_N[19:0]
Input
Audio N value input.
Conduit
audio_clk
audio_data[255:0]
Input
Audio data input.
Conduit
audio_clk
audio_de
Input
Audio data valid input.
Conduit
audio_clk
audio_mute
Input
Audio mute input.
Conduit
audio_clk
audio_info_ai[48:0]
Input
Audio InfoFrame
input bundle input.
Conduit
audio_clk
audio_metadata[165:0]
Input
Carries additional
information related to
3D audio and multistream audio.
Audio
Port
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Source Clock Tree
Interface
Port Type
Clock
Domain
Port
Direction
4-21
Description
Conduit
audio_clk
audio_format[4:0]
Input
Indicates the audio
format to be
transmitted.
Conduit
ls_clk
gcp[5:0]
Input
General Control
Packet.
Auxiliar Conduit
y
Control
Port
Conduit
ls_clk
info_avi[112:0]
Input
Auxiliary Video
Information
InfoFrame input.
ls_clk
info_vsi[61:0]
Input
Vendor Specific
Information
InfoFrame input.
Misc.
–
version[31:0]
Output
Version of the HDMI
core.
Conduit
Source Clock Tree
The source uses various clocks.
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Source Clock Tree
Figure 4-19: Source Clock Tree
The figure shows how the different clocks connect in the source core.
vid_clk
Pixel Data
HDMI Source Core
ls_clk
tx_clk[0]
WRCLK RDCLK
WRCLK RDCLK
Resampler
FIFO
Sync
Transceiver
HSSI[0]
Channel [0]
HSSI[1]
Channel [1]
HSSI[2]
Channel [2]
HSSI[3]
Channel [3]
WRCLK RDCLK
Sync
AUX Data
TMDS
(TERC4)
Encoder
WRCLK RDCLK
Sync
WRCLK RDCLK
Sync
GPLL
CLK0
CLK1
CLK2
ls_clk
vid_clk
Transceiver
PLL
reconfig
The pixel data clocks into the core at the pixel clock (vid_clk). This same clock derives the required link
speed clock (ls_clk), which is used to drive the transceiver phase-locked loop (PLL) input. The ls_clk
depends on the color bits per pixel (bpp).
Because the transceiver is in bonding mode, the HDMI source core uses tx_clk[0] to clock the data from
the source core in the ls_clk domain into the transceiver in the tx_clk[0] domain.
For HDMI source, you must instantiate 4 transmitter channels: 3 channels to transmit data and 1 channel
to transmit clock information.
You must connect the core ls_clk to the transceiver clock output, which performs the TMDS and TERC4
encoding. The auxiliary data clocks into the core at the ls_clk rate.
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Source Clock Tree
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Related Information
HDMI Hardware Demonstration on page 7-1
For more information about the transmitter and receiver channels.
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Sink Functional Description
The HDMI sink core provides direct connection to the Transceiver Native PHY through a 10-bit, 20-bit, or
40-bit parallel data path.
Figure 5-1: HDMI Sink Signal Flow Diagram
The figure below shows the flow of the HDMI sink signals. The figure shows the various clocking domains
used within the core.
mode
Word Alignment and Channel Deskew
TMDS
Data
Bitslip
Word
Align
Deskew
reset
TMDS TERC4
Decoder
Video
Data
AUX
Data
vid_clk
Video
Resample
Video Data
Video
Data Port
Color Depth, pp
Capture GCP
GCP
Capture AVI
AVI Infoframe
Capture AI
AI Infoframe
Auxiliary
Decoder
AUX Data Port
Auxiliary
Memory Encoder
Clock Domains
ls_clk[2:0]
vid_clk[0]
ls_clk[0]
Control
Packet Ports
Audio
Decoder
Auxiliary
Memory Interface
Audio
Data Port
Auxiliary
Packet Capture
The sink core provides three 10-bit, 20-bit, or 40-bit data input paths corresponding to the color channels.
The sink core clocks the three 10-bit, 20-bit, or 40-bit channels from the transceiver outputs using the
respective transceiver clock outputs.
• Blue channel: 0
• Green channel: 1
• Red channel: 2
© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, NIOS, Quartus and Stratix words and logos are
trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
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Sink Channel Word Alignment and Deskew
Sink Channel Word Alignment and Deskew
The input stage of the sink is responsible for synchronizing the incoming parallel data channels correctly.
The synchronization is split to two stages: word alignment and channel deskew.
Table 5-1: Synchronization Stages
Stage
Word Alignment
Description
• Correctly aligns the incoming parallel data to word boundaries using bit-slip
technique.
• TMDS encoding does not guarantee unique control codes, but the core can
still use the sequence of continuous symbols found in data and video
preambles to align.
• The alignment algorithm searches for 12 consecutive 0×54 or 0×ab
corresponding to the data and video preambles.
Note: The preambles are also present in digital video interface (DVI)
coding.
• The alignment logic asserts a marker indicator when the 12 consecutive
signals are detected.
• Similarly, the logic infers alignment loss when 8K symbol clocks elapse
without a single marker assertion.
Channel Deskew
Altera Corporation
• When the data channels are aligned, the core then attempts to deskew each
channel.
• The sink core deskews at the rising edge of the marker insertion.
• For every correct deskewed lane, the marker insertion will appear in all three
TMDS encoded streams.
• The sink core deskews using three dual-clock FIFOs.
• The dual-clock FIFOs also synchronize all three data streams to the blue
channel clock to be used later throughout the decoder core.
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5-3
Figure 5-2: Channel Deskew DCFIFO Arrangement
The figure below shows the signal flow diagram of the deskew logic.
marker[2]
marker[1]
marker[0]
Alignment
Detection
DCFIFO
Channel 0
marker_in[0]
data_in[0]
data[0]
ls_clk[0]
rdreq
wrclk
rdclk
ls_clk[0]
DCFIFO
Channel 1
marker_in[1]
data_in[1]
data[1]
ls_clk[1]
rdreq
wrclk
rdclk
ls_clk[0]
DCFIFO
Channel 2
marker_in[2]
data_in[2]
data[2]
ls_clk[2]
rdreq
wrclk
rdclk
ls_clk[0]
The FIFO read signal of the channels is normally asserted. The sink core deasserts a particular FIFO read
signal if a marker appears at its output and not in the other two FIFO outputs. By deasserting, the sink
core stalls the data stream for sufficient cycles to remove the channel skew. If any of the FIFO channels
overflow, the sink core asserts a reset signal which propagates backwards to the word alignment logic.
Sink TMDS/TERC4 Decoder
The sink TMDS/TERC4 decoder follows the HDMI/DVI specification. The video data is encoded using
the TMDS algorithm and auxiliary data is encoded using TERC4 algorithm.
The sink core feeds the aligned channels into the TMDS/TERC4 decoder. You can parameterize the
decoder to operate in 1, 2, or 4 TMDS symbols per clock. If you choose 2 or 4 TMDS symbols per clock,
the decoder will produce 2 or 4 decoded symbols per clock. The decoded symbols per clock output
supports high pixel clock resolutions on low-end FPGA devices.
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Sink Video Resampler
Sink Video Resampler
The video resampler consists of a gearbox and a dual-clock FIFO (DCFIFO).
The gearbox converts 8-bpc data to 8-, 10-, 12- or 16-bpc data based on the current color depth. The GCP
conveys the color depth information.
Figure 5-3: Sink Resampler Signal Flow Diagram
r[7:0]
g[7:0]
b[7:0]
H-SYNC
V-SYNC
de
data
q
Gearbox
DCFIFO
pp
bpp
ls_clk
Phase
Counter
wr
wrclk
rd
rdwrclk
Resampled
H-SYNC
V-SYNC
de
r[15:0]
g[15:0]
b[15:0]
1
vid_clk
The resampler adheres to the recommended phase count method described in HDMI Specification Ver.
1.4b.
• To keep the source and sink resamples synchronized, the source must send the phase-packing (pp)
value to the sink during the vertical blanking phase, using the general control packet.
• The pp corresponds to the phase of the last pixel in the last active video line.
• The phase-counter logic compares its own pp value to the pp value received in the general control
packet and slips the phase count if the two pp values do not agree.
The output from the resampler is fixed at 16 bpc. When the resampler operates in lower color depths, the
low order bits are zero.
Sink Auxiliary Decoder
The sink core decodes the auxiliary data path into a 72-bit wide standard packet stream. The stream
contains a valid, start-of-packet (SOP) and end-of-packet (EOP) marker.
Table 5-2: Auxiliary Packet Memory Map
This table lists the addresses corresponding to the captured packets.
Memory Start Address
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Packet Name
0
NULL PACKET
4
Audio Clock Regeneration (N/CTS)
8
Audio Sample
12
General Control
16
ACP Packet
20
ISRC1 Packet
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Sink Auxiliary Decoder
Memory Start Address
Packet Name
24
ISRC2 Packet
28
One Bit Audio Sample Packet 5.3.9
32
DST Audio Packet
36
High Bit rate (HBR) Audio Stream Packet
40
Gamut Metadata Packet
44
3D Audio Sample Packet
48
One Bit 3D Audio Sample Packet
52
Audio Metadata Packet
56
Multi-Stream Audio Sample Packet
60
One Bit Multi-Stream Audio Sample Packet
64
Vendor-Specific InfoFrame
68
AVI InfoFrame
72
Source Product Descriptor InfoFrame
76
Audio InfoFrame
80
MPEG Source InfoFrame
84
TSC VBI InfoFrame
88
Dynamic Range and Mastering InfoFrame
Table 5-3: Packet Payload Data Byte
This table shows the representation of each packet payload data byte.
Byte Offset
Word Offset
8
7
6
5
4
3
2
1
0
0
PB22
PB21
PB15
PB14
PB8
PB7
PB1
PB0
HB0
1
PB24
PB23
PB17
PB16
PB10
PB9
PB3
PB2
HB1
2
PB26
PB25
PB19
PB18
PB12
PB11
PB5
PB4
HB2
3
BCH3
PB27
BCH2
PB20
BCH1
PB13
BCH0
PB6
HBCH0
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Sink Auxiliary Packet Capture
Figure 5-4: Auxiliary Data Stream Signal
The figure below shows the relationship between the data bit-field and its clock cycle based on 1-, 2-, or 4symbol per clock mode.
Phase 0
Phase 1
Phase 2
Phase 3
PB24
PB26
BCH3
PB21
PB23
PB25
PB27
PB15
PB17
PB19
BCH2
PB14
PB16
PB18
PB20
PB8
PB10
PB12
BCH1
PB7
PB9
PB11
PB13
PB1
PB3
PB5
BCH0
PB0
PB2
PB4
PB6
HB1
HB2
0
Phase 1
Phase 2
Phase 3
PB22
Byte[8]
HB0
Byte[0]
BCH Block 3
BCH Block 2
BCH Block 1
Output Data
BCH Block 0
Startofpacket
Endofpacket
Valid
Phase 0
Clock
Cycle 1 Symbol
0
-
-
8
-
-
16
-
-
24
Cycle 2 Symbol
0
-
-
4
-
-
8
-
-
12
Cycle 4 Symbol
0
-
-
2
-
-
4
-
-
6
The data output at EOP contains the received BCH error correcting code. The sink core does not perform
any error correction within the core. The auxiliary data is available outside the core.
Note: You can find the bit-field nomenclature in the HDMI Specification Ver.2.0.
Sink Auxiliary Packet Capture
The auxiliary streams transfer auxiliary packets.
The auxiliary packets can carry 15 different packet types.
The module produces 4 valid signals to simplify the user logic.
To simplify user applications and minimize external logic, the HDMI core captures 3 different packet
types and decodes the audio sample data. These packets are: General Control Packet, Auxiliary Video
Information (AVI) InfoFrame, and HDMI Vendor Specific InfoFrame (VSI).
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Sink General Control Packet
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Sink General Control Packet
Table 5-4: General Control Packet Input Fields
Bit Field
gcp[3:0]
Name
Comment
CD3
CD2
CD1
CD0
0
0
0
0
Color depth not
indicated
0
0
0
1
Reserved
0
0
1
0
Reserved
0
0
1
1
Reserved
0
1
0
0
8 bpc or 24 bpp
0
1
0
1
10 bpc or 30
bpp
0
1
1
0
12 bpc or 36
bpp
0
1
1
1
16 bpc or 48
bpp
1
1
1
1
Reserved
Color Depth
(CD)
gcp[4]
Set_
AVMUTE
Refer to HDMI Specification Ver.1.4b
gcp[5]
Clear_
AVMUTE
Refer to HDMI Specification Ver.1.4b
Color depth
Sink Auxiliary Video Information (AVI) InfoFrame
The HDMI core produces AVI InfoFrame to simplify user applications.
Table 5-5: Auxiliary Video Information (AVI) InfoFrame Bit-Fields
The table below lists the bit-fields for the AVI InfoFrame port bundle.
The signal bundle is clocked by ls_clk.
Bit-field
Default Value
(Hexadecimal)
Name
7:0
67
Checksum
9:8
0
S
Scan information
11:10
0
B
Bar info data valid
12
0
A0
Active information present
HDMI Sink
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Checksum
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Sink HDMI Vendor Specific InfoFrame (VSI)
Bit-field
Default Value
(Hexadecimal)
Name
Comment
14:13
0
Y
15
0
Reserved
19:16
8
R
Active format aspect ratio
21:20
0
M
Picture aspect ratio
23:22
0
C
Colorimetry (for example: ITU BT.601,
BT.709)
25:24
0
SC
Non-uniform picture scaling
27:26
0
Q
Quantization range
30:28
0
EC
Extended colorimetry
31
0
ITC
IT content
38:32
00
VIC
Video format identification code
39
0
Reserved
43:40
0
PR
Picture repetition factor
45:44
0
CN
Content type
47:46
0
YQ
YCC quantization range
63:48
0000
ETB
Line number of end of top bar
79:64
0000
SBB
Line number of start of bottom bar
95:80
0000
ELB
Pixel number of end of left bar
111:96
0000
SRB
Pixel number of start of right bar
RGB or YCbCr indicator
Returns 0
Returns 0
Sink HDMI Vendor Specific InfoFrame (VSI)
The core produces the captured HDMI Vendor Specific InfoFrame to simplify user applications.
Table 5-6: HDMI Vendor Specific InfoFrame Bit-Fields
The table below lists the bit-fields for VSI.
The signal bundle is clocked by ls_clk.
Bit-field
Default Value
(Hexadecimal)
Name
4:0
06
Length
12:5
69
Checksum
36:13
000C03
IEEE
41:37
00
Reserved
Altera Corporation
Comment
Length = Nv
Checksum
24-bit IEEE registration identified
(0x000C03)
All 0
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Sink Auxiliary Data Port
Bit-field
Default Value
(Hexadecimal)
Name
44:42
0
HDMI_Video_
Format
52:45
00
HDMI_VIC
57:53
00
Reserved
60:58
0
3D_Ext_Data
5-9
Comment
HDMI video format
HDMI proprietary video format identifi‐
cation code
All 0
3D extended data
Sink Auxiliary Data Port
The auxiliary port is attached to external memory. This port allows you to write packets to memory for use
outside the HDMI core.
The core calculates the address for the data port using the header byte of the received packet. The core
writes packet types 0–15 into a contiguous memory region.
Figure 5-5: Typical Application of AUX Packet Register Interface
The figure below shows a typical application of the auxiliary data port.
HDMI Sink Core
data[71:0]
addr[6:0]
wr
On-Chip
Memory
data[71:8]
addr[6:0]
rd
From 64 bit
Nios II
Avalon-MM
Table 5-7: Auxiliary Packet Memory Map
Memory Start Address
Packet Name
0
NULL PACKET
4
Audio Clock Regeneration (N/CTS)
8
Audio Sample
12
General Control
16
ACP Packet
20
ISRC1 Packet
24
ISRC2 Packet
28
One Bit Audio Sample Packet 5.3.9
32
DST Audio Packet
36
High Bitrate (HBR) Audio Stream Packet
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Sink Audio Decoding
Memory Start Address
Packet Name
40
Gamut Metadata Packet
44
3D Audio Sample Packet
48
One Bit 3D Audio Sample Packet
52
Audio Metadata Packet
56
Multi-Stream Audio Sample Packet
60
One Bit Multi-Stream Audio Sample Packet
64
Vendor-Specific InfoFrame
68
AVI InfoFrame
72
Source Product Descriptor InfoFrame
76
Audio InfoFrame
80
MPEG Source InfoFrame
84
TSC VBI InfoFrame
88
Dynamic Range and Mastering InfoFrame
Table 5-8: Packet Payload Data Byte
The table below lists the representation of each packet payload data byte.
Word
Offset
Byte Offset
8
7
6
5
4
3
2
1
0
0
PB22
PB21
PB15
PB14
PB8
PB7
PB1
PB0
HB0
1
PB24
PB23
PB17
PB16
PB10
PB9
PB3
PB2
HB1
2
PB26
PB25
PB19
PB18
PB12
PB11
PB5
PB4
HB2
3
BCH3
PB27
BCH2
PB20
BCH1
PB13
BCH0
PB6
HBCH0
Note: The packet fields (PB0-PB26) are described in the HDMI 1.4b Specification (Chapter 8.2.1).
Sink Audio Decoding
The sink core sends the audio data using auxiliary packets. You can use three packet types in transporting
audio: Audio InfoFrame, Audio Timestamp, and Audio Sample Data.
The Audio InfoFrame packet is not used within the core but it is captured and presented outside the core.
The Audio Timestamp packet transmits the CTS and N values required to synthesize the audio sample
clock. The core also makes the CTS and N values available outside the core. The audio clock synthesizer
uses a phase-counter to recover the audio sample rate.
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Sink Audio Decoding
5-11
Figure 5-6: Audio Decoder Signal Flow
Auxiliary
Stream
Packets
Capture Audio
InfoFrame
Audio Metadata
Capture Audio
InfoFrame
AI InfoFrame
CTS, N
Capture Audio
Timestamp
Audio
Depacketizer
Capture Audio
InfoFrame
Valid
Audio
Sample
Capture Audio
data InfoFrame
wr
Audio Valid
Audio Data
rd
q
Audio LPCM
Audio Format
The output from the audio clock synthesizer generates a valid pulse at the same rate as the audio sample
clock used in the HDMI source device. This valid pulse is available outside the core as an audio sample
valid signal. This signal reads from a FIFO, which governs the rate of audio samples. The audio depacke‐
tizer drives the input to the FIFO.
The audio depacketizer extracts the 32-bit audio sample data from the incoming Audio Sample packets.
The Audio Sample packets can hold from one to four sample data values. The audio format indicates the
format of the received audio data.
Table 5-9: Definition of HDMI Sink Audio Format
Value
Name
Description
0
LPCM
HDMI packet type 2 transports payload data
1
One-Bit Audio
HDMI packet type 7 transports payload data (not
supported)
2
DST Audio
HDMI packet type 8 transports payload data (not
supported)
3
HBR
HDMI packet type 9 transports payload data
4
3D (LPCM)
HDMI packet type 11 transports payload data (not
supported)
5
3D (One-Bit)
HDMI packet type 12 transports payload data (not
supported)
6
MST (LPCM)
HDMI packet type 14 transports payload data
7
MST (One-Bit)
HDMI packet type 15 transports payload data (not
supported)
—
Reserved
8–15
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HDMI Audio Format
HDMI Audio Format
The HDMI IP core uses the HDMI audio formats to transport payload data.
Table 5-10: Definition of HDMI Audio Format
Value
Name
Description
0
Linear Pulse-Code Modulation
(LPCM)
HDMI packet type 2 transports payload data
1
One-Bit Audio
HDMI packet type 7 transports payload data (not
supported)
2
Direct Stream Transport (DST)
Audio
HDMI packet type 8 transports payload data (not
supported)
3
High Bit Rate (HBR)
HDMI packet type 9 transports payload data
4
3D (LPCM)
HDMI packet type 11 transports payload data (not
supported)
5
3D (One-Bit)
HDMI packet type 12 transports payload data (not
supported)
6
Multi-Stream Audio (MST) for
LPCM
HDMI packet type 14 transports payload data
7
MST for One-Bit Audio
HDMI packet type 15 transports payload data (not
supported)
8–15
—
Reserved
In the LPCM format, the HDMI source accepts 2 to 8 channels. . The Sample Present bit determines
whether to use 2-channel or 8-channel layout. If the Sample Present bit from Channel 0 or 1 is high,
then audio interface uses the 2-channel layout. If otherwise, the audio interface uses the 8-channel layout.
The IP core ignores the Parity, Channel Status, User Data, and Valid bits if the Sample Present bit is
0.
In the HBR format, the sample packet data is identical to the LPCM format. In HBR mode, the HDMI
source transmits 8 samples per clock. The core transmits the HBR audio packets using AUX packet header
number 9.
In the MST format, the sample packet data is also identical to the LPCM format. The MST mode enables a
source to send up to 4 streams of audio to a sink device. The HDMI source sends 1, 2, or 4 streams. When
the source sends fewer than 4 streams, you must set the input audio data to zero.
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Audio InfoFrame
5-13
Figure 5-7: MST Audio Format
4 Streams
2 Streams
1 Stream
ST3-L
0
0
ST3-R
0
0
ST2-L
0
0
ST2-R
0
0
ST1-L
ST1-L
0
ST1-R
ST1-R
0
ST0-L
ST0-L
ST0-L
ST0-R
ST0-R
ST0-R
Audio InfoFrame
The sink produces the received Audio InfoFrame (AI) to simplify user applications.
Table 5-11: Audio InfoFrame Bundle Bit Fields
This table defines the signal bit fields. ls_clk clocks the signal bundle.
Bit Field
Name
7:0
Checksum
10:8
CC
11
Reserved
15:12
CT
Audio format type
17:16
SS
Bits-per-audio sample
20:18
SF
Sampling frequency
23:21
Reserved
31:24
CXT
Audio format type of the audio stream
39:32
CA
Speaker location allocation: front left (FL), front
right (FR)
41:40
LFEPBL
Low-frequency effects (LFE) playback level
information, Decibel (dB)
42
Reserved
Returns zero
46:43
LSV
47
DM_INH
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Description
Checksum
Channel count
Returns zero
Returns zero
Level shift information, dB
Down-mix inhibit flag
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Audio Metadata
Audio Metadata
The HDMI 2.0 specification introduces the Audio Metadata (AM) Packet. The Audio Metadata packet
manages the Multi-Stream and 3D audio sample packets.
Table 5-12: Audio Metadata Bundle Bit Fields
This table defines the signal bit fields.
Bit Field
Name
0
3D_AUDIO
2:1
NUM_VIEWS
4:3
NUM_AUDIO_STR
164:5
Payload data
165
ACTIVE
Description
• 1 = Transmits 3D audio
• 0 = Transmits MST
Indicates the number of views for an MST stream
Number of audio streams
Corresponds to PB0 to PB19 of the Metadata
packets.
When asserted, the core never sends the Metadata.
Note: For more information, refer to the HDMI 2.0 Specification, Chapter 8.3 Audio Metadata Packet.
Sink Interfaces
The table lists the sink's port interfaces.
Table 5-13: Sink Interfaces
N is the number of symbols per clock.
Interface
Reset
Port Type
Reset
Clock
Domain
N/A
Port
reset
Direction
Input
Description
Main asynchronous
reset input.
Note: Resetting
the input
will reset
the
SCDC
register.
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Sink Interfaces
Interface
Port Type
Clock
Clock
Clock
Domain
N/A
Port
ls_clk[2:0]
Direction
Input
5-15
Description
Link speed clock
input.
These clocks
correspond to the
in_r, in_g, and
in_b TMDS
encoded data
inputs.
Clock
N/A
vid_clk
Input
Video data clock
input.
Typically, 8/8, 8/10,
8/12, 8/16 times the
ls_clk according
to color depth (see
General Control
Packet output).
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Sink Interfaces
Interface
Port Type
Conduit
Clock
Domain
vid_clk
Port
vid_data[N*48-1:0]
Direction
Output
Description
Video 48-bit pixel
data output port.
In 2 symbols per
clock (N=2) mode,
this port produces
two 48-bit pixels
per clock.
In 4 symbols per
clock (N=4) mode,
this port produces
four 48-bit pixels
per clock.
Video Data Port
Conduit
vid_clk
vid_de[N-1:0]
Output
Video data enable
output that
indicates active
picture region.
Conduit
vid_clk
vid_hsync[N-1:0]
Output
Video horizontal
sync output.
Conduit
vid_clk
vid_vsync[N-1:0]
Output
Video vertical sync
output.
Conduit
vid_clk
locked[2:0]
Output
Indicates that the
HDMI sink core is
locked to the
TMDS signals.
Each bit represents
a color channel.
Conduit
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vid_clk
vid_lock
Output
Asserted when the
received video data
is determined to be
stable and
repetitive.
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Sink Interfaces
Interface
TMDS Data Port
Port Type
Clock
Domain
Port
Direction
5-17
Description
Conduit
ls_clk[0]
in_b[N*10-1:0]
Input
TMDS encoded
blue channel input.
Conduit
ls_clk[1]
in_g[N*10-1:0]
Input
TMDS encoded
green channel
input.
Conduit
ls_clk[2]
in_r[N*10-1:0]
Input
TMDS encoded red
channel input.
Conduit
ls_clk[2:0] in_lock[2:0]
Input
Ready signal from
the transceiver
reset controller that
indicates the
transceivers are
locked.
Each bit represents
a color channel.
Conduit
ls_clk[0]
aux_valid
Output
Auxiliary data
channel valid
output.
Conduit
ls_clk[0]
aux_data[71:0]
Output
Auxiliary data
channel data
output.
Conduit
ls_clk[0]
aux_sop
Output
Auxiliary data
channel start-ofpacket input.
Conduit
ls_clk[0]
aux_eop
Output
Auxiliary data
channel end-ofpacket output.
Conduit
ls_clk[0]
aux_error
Output
Asserted when
there is auxiliary
data channel CRC
error.
Auxiliary Data Port
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Sink Interfaces
Interface
Decoder Control Port
Port Type
Clock
Domain
Conduit
ls_clk[0]
Conduit
ls_clk[0]
Conduit
ls_clk[0]
Port
Direction
Description
Output
• 0 = (TMDS bit
period) /
(TMDS clock
period) ratio is
1/10
• 1 = (TMDS bit
period) /
(TMDS clock
period) ratio is
1/40
ctrl[N*6-1:0]
Output
DVI Control sideband signals that
show the data that
overwrite the
control and
synchronization
character in the
green and red
channels.
mode
Output
Encoding mode
TMDS_Bit_clock_
Ratio
• 0 = DVI
• 1 = HDMI
Audio Port
Altera Corporation
Conduit
ls_clk[0]
audio_CTS[19:0]
Output
Audio CTS value
output.
Conduit
ls_clk[0]
audio_N[19:0]
Output
Audio N value
output.
Conduit
ls_clk[0]
audio_data[255:0]
Output
Audio data output.
Conduit
ls_clk[0]
audio_de[7:0]
Output
Audio data valid
output.
Conduit
audio_clk
Output
Additional
information related
to 3D audio and
multi-stream audio.
Conduit
audio_clk
Output
Indicates the audio
format detected.
Conduit
ls_clk[0]
Input
Audio InfoFrame
input bundle.
audio_
metadata[164:0]
audio_format[4:0]
audio_info_
ai[47:0]
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Avalon-MM SCDC Management Interface
Interface
Auxiliary Memory
Interface
Port Type
Clock
Domain
Port
Direction
Misc.
Description
Conduit
ls_clk[0]
aux_pkt_addr[6:0]
Output
Auxiliary packet
memory buffer
address output.
Conduit
ls_clk[0]
aux_pkt_data[71:0]
Output
Auxiliary packet
memory buffer data
output.
Conduit
ls_clk[0]
aux_pkt_wr
Output
Auxiliary packet
memory buffer
write strobe output.
Conduit
ls_clk[0]
gcp[5:0]
Output
General Control
Packet output.
Conduit
ls_clk[0]
info_avi[111:0]
Output
Auxiliary Video
Information
InfoFrame output.
Conduit
ls_clk[0]
info_vsi[60:0]
Output
Vendor Specific
Information
InfoFrame output.
Conduit
scdc_i2c_
clk
in_5v_power
Input
Detects the
presence of 5V
input voltage.
Conduit
scdc_i2c_
clk
in_hpd
Input
Detects the Hot
Plug Detect (HPD)
status.
Conduit
–
version[31:0]
Output
Version of the
HDMI core.
Auxiliary Control Port
SCDC Control Port
5-19
Avalon-MM SCDC Management Interface
Table 5-14: Avalon-MM Status and Control Data Channel (SCDC) Management Interface Signals
The table lists the Avalon Memory-Mapped (Avalon-MM) Status and Control Data Channel (SCDC)
Management interface signals.
Signal
Direction
Description
scdc_i2c_clk
Input
Avalon-MM clock input.
scdc_i2c_addr[7:0]
Input
8-bit Avalon-MM address.
scdc_i2c_r
Input
Read signal.
scdc_i2c_rdata[7:0]
Output
Output data.
scdc_i2c_w
Input
Write signal.
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Status and Control Data Channel Interface
Signal
scdc_i2c_wdata[7:0]
Direction
Input
Description
Input data.
For more information about SCDC, refer to the HDMI 2.0 Specification Section 10.4 (Status and Control
Data Channel).
Status and Control Data Channel Interface
For applications using the HDMI 2.0 feature, the HDMI IP core provides a memory slave port to the
SCDC registers.
This memory slave port connects to an I2C slave component. The TMDS_Bit_clock_Ratio output from
the SCDC interface indicates when the core requires the 1/40 TMDS bit period to TMDS clock period.
This bit is also stored in its corresponding field in the SCDC registers.
The HDMI 2.0 specification requires the core to respond to the presence of the 5V input from the
connector and also the state of the HPD signal. The 5V input and HPD signal are used in the register
mechanism updates. The signals are synchronous to the scdc_i2c_clk clock domain. You must create a
100-ms delay on the HPD signal externally to the core.
For more information about the Status and Control Data Channel, you may refer to HDMI 2.0 Specifica‐
tion Chapter 10.4.You can obtain the address map for the registers in the HDMI 2.0 specification.
Sink Clock Tree
The sink core uses different clocks.
The logic clocks the transceiver data into the core using the three CDR clocks: (rx_clk[2:0]).
The TMDS and TERC4 decoding is done at the link-speed clock (ls_clk). The sink then resamples the pixel
data and presents the data at the output of the core at the video pixel clock (vid_clk).
The pixel data clock depends on the video format used (within HDMI specification).
For HDMI sink, you need to instantiate 3 receiver channels to receive data.
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Sink Clock Tree
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Figure 5-8: Sink Clock Tree
The figure shows how the different clocks can be selected for the sink core.
TMDS Clock
GPLL
CLK0
CLK1
CLK2
CDR Reference Clock
ls_clk
vid_clk
Channel [0]
reconfig
Transceiver
HDMI Sink Core
rx_clk[0]
HSSI[0]
ls_clk
vid_clk
WRCLK RDCLK
WRCLK RDCLK
Sync
Resampler
FIFO
Pixel Data
rx_clk[1]
WRCLK RDCLK
Channel [1]
HSSI[1]
Sync
rx_clk[2]
WRCLK RDCLK
Channel [2]
HSSI[2]
TMDS
(TERC4)
Decoder
AUX Data
Sync
Related Information
HDMI Hardware Demonstration on page 7-1
For more information about the transmitter and receiver channels.
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Use the settings in the HDMI parameter editor to configure your design.
HDMI Source Parameters
Table 6-1: HDMI Source Parameters
Parameter
Device family
Value
Stratix V
Arria V
Description
Targeted device family; matches the project
device family.
Arria 10
Direction
Transmitter = Source
Select HDMI source.
Receiver = Sink
Symbols per clock
1, 2, or 4 symbols per
clock
Determines how many TMDS symbols and pixels
are processed per clock.
• Stratix V supports 1 or 2 symbols per clock
• Arria V supports 1, 2, or 4 symbols per clock
• Arria 10 supports only 2 symbols per clock
Support auxiliary
0 = No AUX
1 = AUX
Support deep color
0 = No deep color
1 = Deep color
Determines if auxiliary channel encoding is
included.
Determines if the core can encode deep color
formats.
To enable this parameter, you must also enable
the Support auxiliary parameter.
© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, NIOS, Quartus and Stratix words and logos are
trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
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HDMI Sink Parameters
Parameter
Support audio
Value
Description
0 = No audio
Determines if the core can encode audio data.
1 = Audio
To enable this parameter, you must also enable
the Support auxiliary parameter.
HDMI Sink Parameters
Table 6-2: HDMI Sink Parameters
Parameter
Device family
Value
Stratix V
Arria V
Description
Targeted device family; matches the project
device family.
Arria 10
Direction
Transmitter = Source
Select HDMI sink.
Receiver = Sink
Symbols per clock
1, 2, or 4 symbols per
clock
Determines how many TMDS symbols and pixels
are processed per clock.
• Stratix V supports 1 or 2 symbols per clock
• Arria V supports 1, 2, or 4 symbols per clock
• Arria 10 supports only 2 symbols per clock
Support auxiliary
0 = No AUX
1 = AUX
Support deep color
0 = No deep color
1 = Deep color
Support audio
Altera Corporation
Determines if auxiliary channel encoding is
included.
Determines if the core can encode deep color
formats.
To enable this parameter, you must also enable
the Support auxiliary parameter.
0 = No audio
Determines if the core can encode audio data.
1 = Audio
To enable this parameter, you must also enable
the Support auxiliary parameter.
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HDMI Design Example Parameters
Parameter
Value
Manufacturer OUI
—
6-3
Description
The Manufacturer Organizationally Unique
Identifier (OUI) assigned to the manufactured
device to be written into the SCDC registers of
address 0xD0, 0xD1, and 0xD2.
Key in 3 byte hexadecimal data.
Device ID String
—
The Device Identification (ID) string to be written
into the SCDC registers from addresses 0xD3 to
0xDa.
Use this parameter to identify the sink device.
You can key in up to eight ASCII characters. If
you use less than eight characters, the unused
bytes are set to 0x00.
Hardware Revision
—
Indicates the major and minor revisions of the
hardware. Key in one byte of integer data.
• Upper byte represents major revision.
• Lower byte represents minor revision.
The hardware major revision increments on a
major silicon or board revision. The hardware
minor revision increments on a minor silicon
revision or minor board revision and resets to 0
when the major revision increments.
HDMI Design Example Parameters
Table 6-3: HDMI Design Example Parameters
These options are available only for Arria 10 devices.
Parameter
Value
Description
Available Design Example
Select Design
HDMI Parameters
Send Feedback
None, Arria 10
HDMI RX-TX
Retransmit
Select the design example to be generated.
• None: No design example is available for the current
parameter selection
• Arria 10 HDMI RX-TX Retransmit: The generated design
example which has preconfigured parameter settings—does
not follow user settings.
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HDMI Design Example Parameters
Design Example Files
Simulation
On, Off
Turn on this option to generate the necessary files for the
simulation testbench.
Synthesis
On, Off
Turn on this option to generate the necessary files for Quartus
Prime compilation and hardware demonstration.
Generated HDL Format
Generate File
Format
Verilog, VHDL
Select your preferred HDL format for the generated design
example fileset.
Note: This option only determines the format for the
generated top level IP files. All other files (e.g.
example testbenches and top level files for hardware
demonstration) are in Verilog HDL format.
Target Development Kit
Select Board
No Development Kit, Select the board for the targeted design example.
Arria 10 GX FPGA
Development Kit, • No Development Kit: This option excludes all hardware
aspects for the design example. The IP core sets all pin
Custom
assignments
to virtual pins.
Development Kit
• Arria 10 GX FPGA Development Kit: This option automati‐
cally selects the project's target device to match the device
on this development kit. You may change the target device
using the Change Target Device parameter if your board
revision has a different device variant. The IP core sets all
pin assignments according to the development kit.
• Custom Development Kit: This option allows the design
example to be tested on a third party development kit with
an Altera device. You may need to set the pin assignments
on your own.
Target Device
Change Target
Device
Altera Corporation
On, Off
Turn on this option and select the preferred device variant for
the development kit.
HDMI Parameters
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The High-Definition Multimedia Interface (HDMI) hardware demonstration helps you evaluate the
functionality of the HDMI IP core and provides a starting point for you to create your own design.
The demonstration runs on the following device kits:
• Arria V GX starter kit
• Stratix V GX development kit
Related Information
Design Guidelines for DisplayPort and HDMI Interfaces
Hardware Demonstration Components
The demonstration designs instantiate the Video and Image Processing (VIP) Suite IP cores or FIFO
buffers to perform a direct HDMI video stream passthrough between the HDMI sink and source.
© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, NIOS, Quartus and Stratix words and logos are
trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
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Hardware Demonstration Components
The hardware demonstration design comprises the following components:
• HDMI sink
•
•
•
•
• Transceiver Native PHY (RX)
• Transceiver PHY Reset Controller (RX)
• Altera PLL
• Altera PLL Reconfiguration
• Multirate Reconfiguration Controller (RX)
• Oversampler (RX)
• DCFIFO
Sink Display Data Channel (DDC) and Status and Control Data Channel (SCDC)
Transceiver Reconfiguration Controller
VIP bypass and audio, auxiliary and infoframe buffers
Qsys system
• VIP passthrough for HDMI video stream
• Source SCDC controller
• HDMI source reconfiguration controller
• HDMI source
•
•
•
•
•
•
•
•
Altera Corporation
Transceiver Native PHY (TX)
Transceiver fPLL
Transceiver PHY Reset Controller (TX)
Altera PLL
Altera PLL Reconfiguration
Oversampler (TX)
DCFIFO
Clock Enable Generator
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Hardware Demonstration Components
7-3
Figure 7-1: HDMI Hardware Demonstration Block Diagram
The figure below shows a high level architecture of the design.
HDMI Sink
Altera PLL
IP Core
Altera PLL
Reconfiguration
IP Core
(1)
Altera PLL
Reconfiguration
IP Core
Avalon-MM Master
Translator
Avalon-MM Slave
Translator
Nios II CPU
Transceiver
Native PHY
(RX) IP Core
Transceiver PHY
Reset Controller
(TX) IP Core
Avalon-MM Slave
Translator
Transceiver Native
PHY (TX) IP Core
(13)
DCFIFO
IP Core (2)
(3)
Altera HDMI (4)
IP Core (RX)
(10)
Clock Enable
Generator
(9)
(11)
Oversampler
(RX) (2)
Altera PLL
IP Core
Qsys System (HDMI Source, SCDC
Control, and VIP Passthrough)
Multi-Rate
Reconfiguration
Controller (RX)
(12)
Transceiver PHY
Reset Controller
(RX) IP Core
HDMI Source
Transceiver Reconfiguration
Controller IP Core
Rate
Detect
(5)
Clocked Video
Input IP Core
Video Frame
Buffer IP Core
Clocked Video
Output IP Core
(5)
(6)
Altera HDMI
IP Core (TX)
(7)
DCFIFO
IP Core (8)
Oversampler
(TX) (8)
Source SCDC
External Memory
Controller IP Core
I2C Master
(SCDC)
Sink DDC and SCDC
(14)
I2C Slave
(SCDC) (15)
I2C Slave
(EDID)
DCFIFO
IP Core
DCFIFO
IP Core
RAM 1-Port
IP Core
External Memory
(DDR3)
(14)
Arrow Legend
Data
Avalon-ST Video
Avalon-MM
Control/Status
Clock Legend
VIP Bypass and
Audio/Aux/IF Buffers
RX Transceiver Reference Clock
RX TDMS Clock
RX Transceiver Recovered Clock
TX Transceiver Reference Clock
RX Link Speed Clock
TX Transceiver Clock Out
RX Video Clock
TX Link Speed Clock
Management Clock
TX Video Clock
VIP Main Clock
I2C Clock
Memory Clock
The following details of the example design architecture correspond to the numbers in the block diagram.
1. The sink TMDS data has three channels: data channel 0 (blue), data channel 1 (green), and data
channel 2 (red).
2. The Oversampler (RX) and dual-clock FIFO (DCFIFO) instances are duplicated for each TMDS data
channel (0,1,2).
3. The video data input width for each color channel of the HDMI RX core is equivalent to RX transceiver
PCS-PLD parallel data width per channel.
4. Each color channel is fixed at 16 bits per color. The video data output width of the HDMI RX core is
equivalent to the value of symbols per clock*16*3.
5. The video data input width of the Clocked Video Input (CVI) and Clocked Video Output (CVO) IP
cores are equivalent to the value of NUMBER_OF_PIXELS_IN_PARALLEL *
BITS_PER_PIXEL_PER_COLOR_PLANE * NUMBER_OF_COLOR_PLANES. To interface with the
HDMI core, the values of NUMBER_OF_PIXELS_IN_PARALLEL,
BITS_PER_PIXEL_PER_COLOR_PLANE, and NUMBER_OF_COLOR_PLANES must match the
symbols per clock, 16 and 3 respectively.
6. The video data input width of the HDMI TX core is equivalent to the value of symbols per clock*16*3.
You can use the user switch to select the video data from the CVO IP core (VIP passthrough) or
DCFIFO (VIP bypass).
7. The video data output width for each color channel of the HDMI TX core is equivalent to TX
transceiver PCS-PLD parallel data width per channel.
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Transceiver Native PHY (RX)
8. The DCFIFO and the Oversampler (TX) instances are duplicated for each TMDS data channel (0,1,2)
and clock channel.
9. The Oversampler (TX) uses the clock enable signal to read data from the DCFIFO.
10.The source TMDS data has four channels: data channel 0 (blue), data channel 1 (green), data channel 2
(red), and clock channel.
11.The RX Multi-rate Reconfiguration Controller requires the status of TMDS_Bit_clock_ Ratio port to
perform appropriate RX reconfiguration between the TMDS character rates below 340 Mcsc (HDMI
1.4b) and above 340 Mcsc (HDMI 2.0). The status of the port is also required by the Nios II processor
and the HDMI TX core to perform appropriate TX reconfiguration and scrambling.
12.The reset control and lock status signals from HDMI PLL, RX Transceiver Reset Controller and HDMI
RX core.
13.The reset and oversampling control signals for HDMI PLL, TX Transceiver Reset Controller, and
HDMI TX core. The lock status and rate detection measure valid signals from the HDMI sink initiate
the TX reconfiguration process.
14.The I2C SCL and SDA lines with tristate buffer for bidirectional configuration. Use the ALTIOBUF IP
core for Arria V and Stratix V devices.
15.The SCDC is mainly designed for the source to update the TMDS_Bit_Clock_Ratio and
Scrambler_Enable bits of the sink TMDS Configuration register. The HDMI RX core does not support
SCDC read request feature for this release.
Transceiver Native PHY (RX)
• Transceiver Native PHY in Arria V devices
• To operate the TMDS bit rate up to 3,400 Mbps, configure the Transceiver Native PHY at 20 bits at
PCS – PLD interface with the HDMI RX core at 2 symbols per clock. When the PCS – PLD
interface width is 20 bits, the minimum link rate is 611 Mbps.
• To operate the TMDS bit rate up to 6,000 Mbps, configure the Transceiver Native PHY at 40 bits
with the HDMI RX core at 4 symbols per clock. When the PCS – PLD interface width is 40 bits, the
minimum link rate is 1,000 Mbps.
• Oversampling is required for TMDS bit rate which is below the minimum link rate.
• Transceiver Native PHY in Stratix V devices
• To operate the TMDS bit rate up to 6,000 Mbps, configure the Transceiver Native PHY at 20 bits at
PCS – PLD interface with the HDMI RX core at 2 symbols per clock. When the PCS – PLD
interface width is 20 bits, the minimum link rate is 611 Mbps.
Table 7-1: Arria V and Stratix V Transceiver Native PHY (RX) Configuration Settings (6,000 Mbps)
This table shows an example of Arria V and Stratix V Transceiver Native PHY (RX) configuration settings
for TMDS bit rate of 6,000 Mbps.
Parameters
Settings
Datapath Options
Enable TX datapath
Off
Enable RX datapath
On
Enable Standard PCS
On
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Parameters
7-5
Settings
Datapath Options
Initial PCS datapath selection
Standard
Number of data channels
3
Enable simplified data interface
On
RX PMA
Data rate
6,000 Mbps
Enable CDR dynamic reconfiguration
On
Number of CDR reference clocks
2 (2)
Selected CDR reference clock
0 (2)
Selected CDR reference clock frequency
600 MHz
PPM detector threshold
1,000 PPM
Enable rx_pma_clkout port
On
Enable rx_is_lockedtodata port
On
Enable rx_is_lockedtoref port
On
Enable rx_set_locktodata and rx_set_locktoref
ports
On
Standard PCS
Standard PCS protocol
Basic
Standard PCS/PMA interface width
• 10 (for 1 symbol per clock)
• 20 (for 2 and 4 symbols per clock)
Enable RX byte deserializer
• Off (for 1 and 2 symbols per clock)
• On (for 4 symbols per clock)
Table 7-2: Arria V and Stratix V Transceiver Native PHY (RX) Common Interface Ports
This table describes the Arria V and Stratix V Transceiver Native PHY (RX) common interface ports.
(2)
The Bitec HDMI 2.0 HSMC daughter card routes the TMDS clock pin to the transceiver serial data pin. To
use the TMDS clock to drive the HDMI PLL, the TMDS clock must also drive the transceiver dedicated
reference clock pin. The number of CDR reference clocks is 2 with reference clock 1 (unused) driven by the
TMDS clock and reference clock 0 driven by the HDMI PLL output clock. The selected CDR reference clock
will be fixed at 0.
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Transceiver Native PHY (RX)
Signals
Direction
Description
Clocks
rx_cdr_refclk[1:0]
Input
Input reference clock for the RX CDR circuitry.
• To support arbitrary wide data rate range from
250 Mbps to 6,000 Mbps, you need a generic
core PLL to obtain a higher clock frequency from
the TMDS clock. You need a higher clock
frequency to create oversampled stream for data
rates below the minimum transceiver data rate—
for example, 611 Mbps or 1,000 Mbps).
• If the TMDS clock pin is routed to the
transceiver dedicated reference clock pin, you
only need to create one transceiver reference
clock input. You can use the TMDS clock as
reference clock for a generic core PLL to drive
the transceiver.
• If you use Bitec HDMI 2.0 HSMC daughter card,
the TMDS clock pin is routed to the transceiver
serial data pin. In this case, to use the TMDS
clock as a reference clock for a generic core PLL,
the clock must also drive the transceiver
dedicated reference clock. Connect bit 0 to the
generic core PLL output and bit 1 to the TMDS
clock and set the selected CDR reference clock at
0.
rx_std_clkout[2:0]
Output
RX parallel clock output.
• The CDR circuitry recovers the RX parallel clock
from the RX data stream when the CDR is
configured at lock-to-data mode.
• The RX parallel clock is a mirror of the CDR
reference clock when the CDR is configured at
lock-to-reference mode.
rx_std_coreclkin[2:0]
Input
RX parallel clock that drives the read side of the RX
phase compensation FIFO.
Connect to rx_std_clkout ports.
rx_pma_clkout[2:0]
Output
RX parallel clock (recovered clock) output from
PMA.
Leave unconnected.
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Resets
rx_analogreset[2:0]
Input
Active-high, edge-sensitive, asynchronous reset
signal.
When asserted, resets the RX CDR circuit, deserial‐
izer.
Connect to Transceiver PHY Reset Controller IP
core.
rx_digitalreset[2:0]
Input
Active-high, edge-sensitive, asynchronous reset
signal.
When asserted, resets the digital component of the
RX data path.
Connect to the Transceiver PHY Reset Controller IP
core.
PMA Ports
rx_set_locktoref[2:0]
Input
When asserted, programs the RX CDR to lock to
reference mode manually. The lock to reference
mode enables you to control the reset sequence
using rx_set_locktoref and rx_set_locktodata.
The Multirate Reconfiguration Controller (RX) sets
this port to 1 if oversampling mode is required.
Otherwise, this port is set to 0.
Refer "Transceiver Reset Sequence" in Transceiver
Reset Control in Arria V/Stratix V Devices for more
information about manual control of the reset
sequence.
rx_set_locktodata[2:0]
Input
Always driven to 0. When rx_set_locktoref is
driven to 1, the CDR is configured to lock-toreference mode. Otherwise, the CDR is configured
to lock-to-data mode.
rx_is_lockedtoref[2:0]
Output
When asserted, the CDR is locked to the incoming
reference clock. Connect this port to rx_is_
lockedtodata port of the Transceiver PHY Reset
Controller IP core when rx_set_locktoref is 1.
rx_is_lockedtodata[2:0]
Output
When asserted, the CDR is locked to the incoming
data. Connect this port to rx_is_lockedtodata
port of Transceiver PHY Reset Controller IP core
when rx_set_locktoref is 0.
rx_serial_data[2:0]
Input
RX differential serial input data.
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PCS Ports
unused_rx_parallel_data
rx_parallel_data[S*3*101:0]
Output
Leave unconnected.
Output
PCS RX parallel data.
Note: S=Symbols per clock.
Calibration Status Port
rx_cal_busy[2:0]
Output
When asserted, indicates that the initial RX calibra‐
tion is in progress. This port is also asserted if the
reconfiguration controller is reset. Connect to the
Transceiver PHY Reset Controller IP core.
Reconfiguration Ports
reconfig_to_xcvr[209:0]
reconfig_from_
xcvr[137:0]
Input
Reconfiguration signals from the Transceiver
Reconfiguration Controller.
Output
Reconfiguration signals to the Transceiver Reconfi‐
guration Controller.
Altera PLL IP Cores
Use the Altera PLL IP core as the HDMI PLL to generate reference clock for RX or TX transceiver, link
speed, and video clocks for the HDMI RX or TX IP core.
The HDMI PLL is referenced by the arbitrary TMDS clock. For HDMI source, you can reference the
HDMI PLL by a separate clock source in the VIP passthrough design, which contains frame buffer. The
HDMI PLL for TX has the same desired output frequencies as RX across symbols per clock and color
depth.
• For TMDS bit rates ranging from 3,400 Mbps to 6,000 Mbps (HDMI 2.0), the TMDS clock rate is 1/40
of the TMDS bit rate. The HDMI PLL generates reference clock for RX/TX transceiver at 4 times the
TMDS clock.
• For TMDS bit rates below 3,400 Mbps (HDMI 1.4b), the TMDS clock rate is 1/10 of the TMDS bit rate.
The HDMI PLL generates reference clock for RX/TX transceiver at identical rate as the TMDS clock.
If the TMDS link operates at TMDS bit rates below the minimum RX/TX transceiver link rate, your
design requires oversampling and a factor of 5 is chosen. The minimum link rate of the RX/TX transceiver
vary across device families and symbols per clock. The HDMI PLL generates reference clock for RX/TX
transceiver at 5 times the TMDS clock.
Note: Place the Altera PLL in the transmit path (pll_hdmi_tx) in the physical location next to the
transceiver PLL.
Table 7-3: HDMI PLL Desired Output Frequencies for 8-bpc Video
This table shows an example of HDMI PLL desired output frequencies across various TMDS clock rates
and symbols per clock for all supported device families using 8-bpc video.
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Altera PLL IP Cores
Device
Family
Symb
ols
Per
Clock
2
Minimum
Link Rate
(Mbps)
611
Arria V
4
Stratix V
2
1,000
611
TMDS Bit
Rate
(Mbps)
Oversam‐
pling (5x)
Required
TMDS
RX/TX
Clock Rate Transceive
(MHz)
r Refclk
(MHz)
RX/TX
Link
Speed
Clock
(MHz)
RX/TX Video
Clock (MHz)
270
Yes
27
135
13.5
13.5
742.5
No
74.25
74.25
37.125
37.125
1,485
No
148.5
148.5
74.25
74.25
2,970
No
297
297
148.5
148.5
270
Yes
27
135
6.75
6.75
742.5
Yes
74.25
371.25
18.5625
18.5625
1,485
No
148.5
148.5
37.125
37.125
5,940
No
148.5
594
148.5
148.5
540
Yes
54
270
27
27
1,620
No
162
162
81
81
5,934
No
296.7
593.4
296.7
296.7
The color depths greater than 8 bpc or 24 bpp are defined to be deep color. For a color depth of 8 bpc, the
core carries the pixels at a rate of one pixel per TMDS clock. At deeper color depths, the TMDS clock runs
faster than the source pixel clock to provide the extra bandwidth for the additional bits.
The TMDS clock rate is increased by the ratio of the pixel size to 8 bits:
•
•
•
•
8 bits mode—TMDS clock = 1.0 × pixel or video clock (1:1)
10 bits mode—TMDS clock = 1.25 × pixel or video clock (5:4)
12 bits mode—TMDS clock = 1.5 × pixel or video clock (3:2)
16 bits mode—TMDS clock = 2 × pixel or video clock (2:1)
Table 7-4: HDMI PLL Desired Output Frequencies for Deep Color Video
This table shows an example of HDMI PLL desired output frequencies across symbols per clock and color
depths.
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Symbols
Per
Clock
2
Oversa
mpling
(5x)
Require
d
Yes
4
No
Bits per TMDS Bit Rate
color
(Mbps)
TMDS Clock
Rate (MHz)
RX/TX
Transceiver
Refclk (MHz)
RX/TX Link
Speed Clock
(MHz)
RX/TX Video Clock
(MHz)
8
270
27
135
13.5
13.5
10 (3)
337.5
33.75
168.75
16.875
13.5
12 (3)
405
40.5
202.5
20.25
13.5
16 (3)
540
54
270
27
13.5
8
1,485
148.5
148.5
37.125
37.125
10 (3)
1,856.25
185.625
185.625
46.40625
37.125
12 (3)
2,227.5
222.75
222.75
55.6875
37.125
16 (3)
2,970
297
297
74.25
37.125
The default frequency setting of the HDMI PLL is fixed at possible maximum value for each clock for
appropriate timing analysis.
Note: This default combination is not valid for any HDMI resolution. The core will reconfigure to the
appropriate settings upon power up.
Altera PLL Reconfig IP Core
The Altera PLL Reconfig IP core facilitates dynamic real-time reconfiguration of PLLs in Altera devices.
Use the IP core to update the output clock frequency, PLL bandwidth in real-time, without reconfiguring
the entire FPGA.
You can run this IP core at 100 MHz in Arria 10 and Stratix V devices. In Arria V devices, you need to run
at 75 MHz for timing closure. To simplify clocking in Arria V devices, the entire management clock
domain is capped at 75 MHz.
Multirate Reconfig Controller (RX)
The Multirate Reconfig Controller implements rate detection circuitry with the HDMI PLL to drive the
RX transceiver to operate at any arbitrary link rates ranging from 250 Mbps to 6,000 Mbps. Link rate of
6,000 Mbps is not the absolute maximum but the intention is to support HDMI 2.0 link rate.
The Multirate Reconfig Controller performs rate detection on the HDMI PLL arbitrary reference clock,
which is also the TMDS clock, to determine the clock frequency band. Based on the detected clock
frequency band, the circuitry dynamically reconfigures the HDMI PLL and transceiver settings to
accommodate for the link rate change.
(3)
For this release, deep color video is only demonstrated in VIP bypass mode. It is not available in VIP
passthrough mode.
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Oversampler (RX)
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Figure 7-2: Multirate Reconfiguration Sequence Flow
This figure illustrates the multirate reconfiguration sequence flow of the controller when it receives input
data stream and reference clock frequency, or when the tranceiver is unlocked.
Reset the RX HDMI PLL and RX transceiver.
Enable the rate detection circuit to measure incoming TMDS clock.
Accept acknowledgement with clock frequency band and desired
RX HDMI PLL and RX transceiver settings.
Determine if RX HDMI PLL and/or RX transceiver reconfiguration is
required based on the previous and current detected clock
frequency band and color depth. Different color depths may fall
within the same clock frequency band.
Reconfiguration Is Required
Reconfiguration Is Not Required
Request RX HDMI PLL and/or RX transceiver
reconfiguration if the previous and current
clock frequency band or color depth differs.
The controller reconfigures the RX HDMI PLL and/or RX
transceiver (followed by recalibration on Arria 10 device).
When all reconfiguration processes complete or the previous and
current clock frequency band and color depth do not differ, reset
the RX HDMI PLL and RX transceiver.
Enable rate the detection circuit periodically to monitor the
reference clock frequency. If the clock frequency band changes or
the RX HDMI PLL or RX transceiver or HDMI core lose lock, repeat
the process.
Oversampler (RX)
The Oversampler (RX) extracts data from the oversampled incoming data stream when the detected clock
frequency band is below the transceiver minimum link rate.
The oversampling factor is fixed at 5 and you can program the data width to support different number of
symbols. The supported data width is 20 bit for 2 symbols per clock and 40 bits for 4 symbols per clock.
The extracted bit will be accompanied by data valid pulse which asserts every 5 clock cycles.
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DCFIFO
DCFIFO
The DCFIFO transfers data from the RX transceiver recovered clock domain to the RX link speed clock
domain. The DCFIFO transfers data from the TX link speed clock domain to the TX transceiver parallel
clock out domain.
• Sink
• When the Multirate Reconfig Controller (RX) detects an incoming input stream that is below the
transceiver minimum link rate, the DCFIFO accepts the data from the Oversampler with data valid
pulse as write request asserted every 5 clock cycles.
• Otherwise, it accepts data directly from the transceiver with write request asserted at all times.
• Source
• When Nios II processor determines the outgoing data stream is below the TX transceiver minimum
link rate, the TX transceiver accepts the data from the Oversampler (TX).
• Otherwise, the TX transceiver reads data directly from the DCFIFO with read request asserted at all
times.
Sink Display Data Channel (DDC) & Status and Control Data Channel (SCDC)
The HDMI source uses the DDC to determine the capabilities and characteristics of the sink by reading
the Enhanced Extended Display Identification Data (E-EDID) data structure.
The E-EDID memory is stored using the RAM 1-Port IP core. A standard two-wire (clock and data) serial
data bus protocol (I2C slave-only controller) is used to transfer CEA-861-D compliant E-EDID data
structure.
The 8-bit I2C slave addresses for the E-EDID are 0xA0/0xA1. The LSB indicates the access type: 1 for read
and 0 for write. When an HPD event occurs, the I2C slave responds to E-EDID data by reading from the
RAM.
The I2C slave-only controller is also used to support SCDC for HDMI 2.0 operation. The 8-bit I2C slave
addresses for the SCDC are 0xA8/0xA9. When an HPD event occurs, the I2C slave performs write/read
transaction to/from SCDC interface of HDMI RX core. This I2C slave-only controller for SCDC is not
required if HDMI 2.0 is not intended.
Transceiver Reconfiguration Controller
You can use the Transceiver Reconfiguration Controller IP core to change the device transceiver settings at
any time.
You can selectively reconfigure any portion of the transceiver. The reconfiguration of each portion requires
a read-modify-write operation (read first, then write). The read-modify-write operation modifies only the
appropriate bits in a register and does not affect the other bits.
The Transceiver Reconfiguration Controller is only available and required in Arria V and Stratix V
devices. Because the RX and TX transceivers share a single controller, the controller requires Qsys
interconnects, such as Avalon-MM Master Translator and Avalon-MM Slave Translator, in the Qsys
system.
• The Avalon-MM Master Translator provides an interface between this controller and the RX Multirate
Reconfig Controller.
• The Avalon-MM Slave Translator arbitrates the RX and TX reconfiguration event for this controller.
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VIP Bypass and Audio, Auxiliary and InfoFrame Buffers
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In Arria 10 devices, the Transceiver Native PHY has a direct access the Avalon-MM reconfiguration
interface.
• The RX Multirate Reconfig Controller directly drives the RX transceiver reconfiguration interface.
• The Avalon-MM Slave Translator converts the Nios II reconfiguration command and directly drives
the TX transceiver reconfiguration interface.
VIP Bypass and Audio, Auxiliary and InfoFrame Buffers
The video data output and synchronization signals from HDMI RX core is looped through a DCFIFO
across RX and TX video clock domains. The General Control Packet (GCP), InfoFrames (AVI, VSI, and
AI), auxiliary data and audio data are looped through DCFIFOs across RX and TX link speed clock
domains.
The auxiliary data port of the HDMI TX core controls the auxiliary data that flow through DCFIFO
through backpressure. The backpressure ensures there is no incomplete auxiliary packet on the auxiliary
data port. This block also performs external filtering on the audio data and audio clock regeneration
packet from the auxiliary data stream before sending to the HDMI TX core auxiliary data port.
Transceiver Native PHY (TX)
The Arria V and Stratix V Transceiver Native PHY (TX) configuration settings are typically the same as
RX.
Table 7-5: Arria V and Stratix V Transceiver Native PHY (TX) Configuration Settings (6,000 Mbps)
This table shows an example of Arria V and Stratix V Transceiver Native PHY (TX) configuration settings
for TMDS bit rate of 6,000 Mbps.
Parameters
Settings
Datapath Options
Enable TX datapath
On
Enable RX datapath
Off
Enable Standard PCS
On
Initial PCS datapath selection
Standard
Number of data channels
4
Bonding mode
xN
Enable simplified data interface
On
TX PMA
Data rate
TX local clock division factor
6,000 Mbps
1
Enable TX PLL dynamic reconfiguration
On
Use external TX PLL
Off
Number of TX PLLs
1
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Transceiver Native PHY (TX)
TX PMA
Main TX PLL logical index
0
Number of TX PLL reference clocks
1
PLL type
CMU
Reference clock frequency
600 MHz
Selected reference clock source
0
Selected clock network
xN
Standard PCS
Standard PCS protocol
Basic
Standard PCS/PMA interface width
• 10 (for 1 symbol per clock)
• 20 (for 2 and 4 symbols per clock)
Enable TX byte serializer
• Off (for 1 and 2 symbols per clock)
• On (for 4 symbols per clock)
Table 7-6: Arria V and Stratix V Transceiver Native PHY (TX) Common Interface Ports
This table describes the Arria V and Stratix V Transceiver Native PHY (TX) common interface ports.
Signals
Direction
Description
Clocks
tx_pll_refclk
Input
The reference clock input to the TX PLL.
tx_std_clkout[3:0]
Output
TX parallel clock output.
tx_std_coreclkin[3:0]
Input
TX parallel clock that drives the write side of the TX
phase compensation FIFO.
Connect to tx_std_clkout[0] ports.
Resets
tx_analogreset[3:0]
Input
When asserted, resets all the blocks in TX PMA.
Connect to Transceiver PHY Reset Controller (TX)
IP core.
tx_digitalreset[3:0]
Input
When asserted, resets all the blocks in TX PCS.
Connect to the Transceiver PHY Reset Controller
(TX) IP core.
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TX PLL
pll_powerdown
Input
When asserted, resets the TX PLL.
Connect to the Transceiver PHY Reset Controller
(TX) IP core.
pll_locked
Output
When asserted, indicates that the TX PLL is locked.
Connect to the Transceiver PHY Reset Controller
(TX) IP core.
PCS Ports
unused_tx_parallel_data
tx_parallel_data[S*4*101:0]
Input
Leave unconnected.
Input
PCS TX parallel data.
Note: S=Symbols per clock.
PMA Port
tx_serial_data[3:0]
Output
TX differential serial output data.
Calibration Status Port
tx_cal_busy[3:0]
Output
When asserted, indicates that the initial TX calibra‐
tion is in progress. This port is also asserted if the
reconfiguration controller is reset. Connect to the
Transceiver PHY Reset Controller (TX) IP core.
Reconfiguration Ports
reconfig_to_xcvr[349:0]
reconfig_from_
xcvr[229:0]
Input
Reconfiguration signals from the Transceiver
Reconfiguration Controller.
Output
Reconfiguration signals to the Transceiver Reconfi‐
guration Controller.
Transceiver PHY Reset Controller
The Transceiver PHY Reset Controller IP core ensures a reliable initialization of the RX and TX
transceivers.
The reset controller has separate reset controls per channel to handle synchronization of reset inputs,
lagging of PLL locked status, and automatic or manual reset recovery mode.
Oversampler (TX)
The Oversampler (TX) transmits data by repeating each bit of the input word a given number of times and
constructs the output words.
The oversampling factor is fixed at 5. The Oversampler (TX) assumes that the input word is only valid
every 5 clock cycles. This block enables when the outgoing data stream is determined to be below the TX
transceiver minimum link rate by reading once from the DCFIFO every 5 clock cycles.
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Clock Enable Generator
The Clock Enable Generator is a logic that generates a clock enable pulse.
This clock enable pulse asserts every 5 clock cycles and serves as a read request signal to clock the data out
from DCFIFO.
Qsys System
The Qsys system consists of the VIP passthrough for HDMI video stream, source SDC controller, and
source reconfiguration controller blocks.
VIP Passthrough for HDMI Video Stream
For certain example designs, you can loop the video data output and synchronization signals from HDMI
RX core through the VIP data path.
The Clocked Video Input II (CVI II) IP core converts clocked video formats to Avalon-ST video by
stripping incoming clocked video of horizontal and vertical blanking, leaving only active picture data.
• The IP core provides clock crossing capabilities to allow video formats running at different frequencies
to enter the system.
• The IP core also detects the format of the incoming clocked video and provides this information in a
set of registers.
• The Nios II processor uses this information to reconfigure the video frame mode registers of the CVO
IP core in the VIP passthrough design.
The Video Frame Buffer II IP core buffers video frames into external RAM.
• The IP core supports double and triple buffering with a range of options for frame dropping and
repeating.
• You can use the buffering options to solve throughput issues in the data path and perform simple frame
rate conversion.
In a VIP passthrough design, you can reference the HDMI source PLL and sink PLL using separate clock
sources. However, in a VIP bypass design, you must reference the HDMI source PLL and sink PLL using
the same clock source.
The Clocked Video Output II (CVO II) IP core converts data from the flow-controlled Avalon-ST video
protocol to clocked video.
• The IP core provides clock crossing capabilities to allow video formats running at different frequencies
to be created from the system.
• It formats the Avalon-ST video into clocked video by inserting horizontal and vertical blanking and
generating horizontal and vertical synchronization information using the Avalon-ST video control and
active picture packets.
• The video frame is described using the mode registers that are accessed through the Avalon-MM
control port.
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Table 7-7: Difference between VIP Passthrough Design and VIP Bypass Design
VIP Passthrough Design
VIP Bypass Design
• Can reference the HDMI source PLL and
sink PLL using separate clock sources
• Demonstrates only certain video formats
—640×480p60, 720×480p60,
1280×720p60, 1920×1080p60, and
3840×2160p24
• Must reference the HDMI source PLL and sink PLL
using the same clock source
• Demonstrates all video formats.
Table 7-8: VIP Passthrough and VIP Bypass Options for the Supported Devices
Device
Family
Symbols
Per Clock
HDMI
Specifica‐
tion
Support
Bitec HDMI 2.0
Daughter Card
Directory
VIP
Passthrough
VIP Bypass
Arria V
2
1.4b
HSMC (Rev8)
av_sk
Supported
Supported
Arria V
4
2.0
HSMC (Rev8)
av_sk_hdmi2
Not supported
Supported
Stratix V
2
2.0
HSMC (Rev8)
sv_hdmi2
Not supported
Supported
Source SCDC Controller
The source SCDC Controller contains the I2C master controller. The I2C master controller transfers the
SCDC data structure from the FPGA source to the external sink for HDMI 2.0 operation.
For example, if the outgoing data stream is 6,000 Mbps, the Nios II processor commands the I2C master
controller to update the TMDS_Bit_Clock_Ratio and Scrambler_Enable bits of the sink TMDS configu‐
ration register to 1. The same I2C master can also transfer the DDC data structure (E-EDID) between the
HDMI source and external sink.
Source Reconfiguration Controller
The Nios II CPU acts as the multirate reconfiguration controller for the HDMI source.
The CPU relies on the periodic rate detection from the Multirate Reconfig Controller (RX) to determine if
TX requires reconfiguration. The Avalon-MM slave translator provides the interface between the Nios II
processor Avalon-MM master interface and the Avalon-MM slave interfaces of the externally instantiated
HDMI source's Altera PLL Reconfig IP core and Transceiver Native PHY (TX).
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HDMI Hardware Demonstration Requirements
Figure 7-3: Nios II Software Flow
The reconfiguration sequence flow for TX is the same as RX, except that the PLL and transceiver
reconfiguration, and the reset sequence is performed sequentially. The figure illustrates the Nios II
software flow that involves the controls for CVO, I2C master and HDMI source.
Reset the TX HDMI PLL and TX transceiver. Initialize the I 2C master controller core.
Poll periodic measure valid signal from RX rate detection circuit to determine whether TX
reconfiguration is required. Also, poll the TX hot-plug request to determine whether a TX
hot-plug event has occurred.
Measure Valid Received
Read TMDS_Bit_Clock_Ratio value from the HDMI
sink and the measure value.
Reconfiguration
Is Not Required
Retrieve the clock frequency band based on the
measure and TMDS_Bit_Clock_Ratio values and read
the color depth information from the HDMI sink to
determine whether TX HDMI PLL and TX transceiver
reconfiguration and oversampling is required.
A TX Hot-Plug Event
Has Occurred
Send SCDC via the I2C interface based on the
TMDS_Bit_Clock_Ratio register value from
the HDMI sink.
Reconfiguration Is Required
The Nios II processor commands the I 2C master to
send SCDC information.
The Nios II processor sends sequential commands to
reconfigure the TX HDMI PLL and TX transceiver (followed
by recalibration on Arria 10 device), and reset sequence
after reconfiguration. It then sends a reset to the HDMI TX core.
CVO Update
Is Not Required
Retrieve incoming video width and height from the
CVI to determine whether the CVO should be updated
to adjust the outgoing video frame resolution.
CVO Update Is Required
The Nios II processor sends commands to update the
CVO video frame resolution.
HDMI Hardware Demonstration Requirements
The HDMI demonstration requires an Altera FPGA board and supporting hardware.
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Demonstration Walkthrough
•
•
•
•
•
7-19
Altera FPGA board
Bitec HDMI 2.0 daughter card
Standard HDMI source—for example, PC with a graphic card and HDMI output
Standard HDMI sink—for example, monitor with HDMI input
2 HDMI cables
• A cable to connect the graphics card to the Bitec daughter card RX connector.
• A cable to connect the Bitec daughter card TX connector to the monitor.
Table 7-9: Altera FPGA Boards and Bitec HDMI 2.0 Daughter Cards Supported for the Demonstration
Example Design
Altera FPGA Board
Bitec HDMI 2.0 Daughter Card
Arria V (av_sk)
Arria V GX FPGA Starter Kit
HSMC (Rev8)
Arria V (av_sk_hdmi2)
Arria V GX FPGA Starter Kit
HSMC (Rev8)
Stratix V GX FPGA Development
Kit
HSMC (Rev8)
Stratix V (sv_hdmi2)
Related Information
• Arria V GX Starter Kit User Guide
• Stratix V GX FPGA Development Kit User Guide
Demonstration Walkthrough
Setting up and running the HDMI hardware demonstration consists of four stages.
You can use the Altera-provided scripts to automate these stages.
1.
2.
3.
4.
Set up the hardware.
Copy the design files to your working directory.
Build and compile the design.
View the results.
Set Up the Hardware
The first stage of the demonstration is to set up the hardware.
To set up the hardware for the demonstration:
1. Connect the Bitec HDMI 2.0 daughter card to the Altera FPGA board.
2. Connect the FPGA board to your PC using a USB cable.
Note: The Arria V GX FPGA Starter Kit and Stratix V GX FPGA Development Kit have an On-Board
USB-Blaster™ II connector. If your version of the board does not have this connector, you can
use an external USB-Blaster cable.
3. Connect an HDMI cable from the HDMI RX connector on the Bitec HDMI 2.0 daughter card to a
standard HDMI source, in this case a PC with a graphic card and HDMI output.
4. Connect another HDMI cable from the HDMI TX connector on the Bitec HDMI 2.0 daughter card to
a standard HDMI sink, in this case a monitor with HDMI input.
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Copy the Design Files
Copy the Design Files
After you set up the hardware, you copy the design files.
Copy the hardware demonstration files from one of the following paths to your working directory:
• Arria V
• 2 symbols per clock (HDMI 1.4b) demonstration: <IP root directory>/altera_hdmi/hw_
demo/av_sk
• 4 symbols per clock (HDMI 2.0) demonstration: <IP root directory>/altera_hdmi/hw_
demo/av_sk_hdmi2
• Stratix V
• 2 symbols per clock (HDMI 2.0) demonstration: <IP root directory>/altera_hdmi/hw_
demo/sv_hdmi2
Build and Compile the Design
After you copy the design files, you can build the design.
You can use the provided Tcl script to build and compile the FPGA design.
1. Open a Nios II Command Shell.
2. Change the directory to your working directory.
3. Type the command and enter source runall.tcl.
This script executes the following commands:
•
•
•
•
•
•
Generate IP catalog files
Generate the Qsys system
Create a Quartus Prime project
Create a software work space and build the software
Compile the Quartus Prime project
Run Analysis & Synthesis to generate a post-map netlist for DDR assignments—for VIP
passthrough design only
• Perform a full compilation
Note: If you are a Linux user, you will get a message cygpath: command not found. You can safely
ignore this message; the script will proceed to generate the next commands.
View the Results
At the end of the demonstration, you will be able to view the results on the on the standard HDMI sink
(monitor).
To view the results of the demonstration, follow these steps:
1. Power up the Altera FPGA board.
2. Type the following command on the Nios II Command Shell to download the Software Object File
(.sof) to the FPGA.
nios2-configure-sof output_files/<Quartus project name>.sof
3. Power up the standard HDMI source and sink (if you haven't done so).
The design displays the output of your video source (PC).
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Note: If the output does not appear, press cpu_resetn to reinitialize the system or perform HPD by
unplugging the cable from the standard source and plug it back again.
4. Open the graphic card control utility (if you are using a PC as source). Using the control panel, you can
switch between various video resolutions.
The av_hdmi2 and sv_hdmi2 demonstration designs allow any video resolutions up to 4Kp60. The
av_sk design allows 640×480p60, 720×480p60, 1280×720p60, 1920×1080p60, and 3840×2160p24 when
you select the VIP passthrough mode (user_dipsw[0] = 0). If you select the VIP bypass mode
(user_dipsw[0] = 1, the design allows any video resolutions up to 4Kp60.
Push Buttons, DIP Switches and LED Functions
Use the push buttons, DIP switches, and LED functions on the board to control your demonstration.
Table 7-10: Push Buttons, DIP Switches and LEDs Functions
Push Button/ DIP Switch/
LED
Pins
Functions
av_sk/
av_sk_hdmi2
sv_hdmi2
cpu_resetn
D5
AM34
user_pb[0]
A14
A7
Press once to toggle HPD signal to the
standard HDMI source.
user_pb[1]
B15
B7
Press and hold to instruct the TX to send
DVI encoded signal and release to send
HDMI encoded signal.
user_pb[2]
B14
C7
Press and hold to instruct the TX to stop
sending InfoFrames and release to resume
sending.
user_dipsw[0]
D15
Unused
Press once to perform system reset.
Only used in av_sk design which
demonstrates the VIP passthrough feature.
• 0: VIP passthrough
• 1: VIP bypass
RX HDMI PLL lock status.
user_led[0]
F17
J11
• 0: Unlocked
• 1: Locked
RX transceiver ready status.
user_led[1]
G15
U10
• 0: Not ready
• 1: Ready
RX HDMI core lock status
user_led[2]
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U9
• 0: At least 1 channel unlocked
• 1: All 3 channels locked
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Push Buttons, DIP Switches and LED Functions
Push Button/ DIP Switch/
LED
Pins
av_sk/
av_sk_hdmi2
Functions
sv_hdmi2
RX oversampling status.
user_led[3]
G17
AU24
• 0: Non-oversampled (more than 611
Mbps for av_sk and sv_hdmi2, more
than 1,000 Mbps for av_sk_hdmi2)
• 1: Oversampled (less than 611 Mbps for
av_sk and sv_hdmi2, less than 1,000
Mbps for av_sk_hdmi2)
TX HDMI PLL lock status.
user_led[4]
D16
AF28
• 0: Unlocked
• 1: Locked
TX transceiver ready status.
user_led[5]
C13
AE29
• 0: Not ready
• 1: Ready
TX transceiver PLL lock status.
user_led[6]
C14
AR7
• 0: Unlocked
• 1: Locked
TX oversampling status.
user_led[7]
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C16
AV10
• 0: Non-oversampled (more than 611
Mbps for av_sk and sv_hdmi2, more
than 1,000 Mbps for av_sk_hdmi2)
• 1: Oversampled (less than 611 Mbps for
av_sk and sv_hdmi2, less than 1,000
Mbps for av_sk_hdmi2)
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HDMI Simulation Example
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The HDMI simulation example evaluates the functionality of the HDMI IP core and provides a starting
point for you to create your own simulation.
This simulation example targets the ModelSim SE simulator. The simulation covers the following core
features:
•
•
•
•
IEC-60958 audio format
Standard H/V/DE/RGB input video format
Support for 4 symbols per clock
Support for HDMI 2.0 scrambled operation
Figure 8-1: HDMI Testbench
CRC
Check
Video TPG
Audio Sample Gen
HDMI TX
(4 Symbols/Clock)
HDMI RX
(4 Symbols/Clock)
Video data
CRC
Check
Audio data
Audio Data
Check
Aux data
Aux Data
Check
Aux Sample Gen
The Test Pattern Generator (TPG) provides the video stimulus. The IP core stimulates the HDMI TX core
using an audio packet generator and aux packet generator. The output from the HDMI TX core drives the
HDMI RX core.
The IP core requires a memory-mapped master stimulus to operate the testbench for HDMI 2.0
scrambling. This stimulus implements the activity normally seen across the I2C DDC channel. At this
point, the IP core asserts the scramble enable bit in the SCDC registers.
© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, NIOS, Quartus and Stratix words and logos are
trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
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The testbench implements CRC checking on the input and output video. The testbench checks the CRC
value of the transmitted data against the CRC calculated in the received video data. The testbench
performs the checking after detecting 4 stable V-SYNC signals from the receiver.
The aux sample generator generates a fixed data to be transmitted from the transmitter. On the receiver
side, the generator compares whether the expected aux data is received and decoded correctly.
The audio sample generator generates an incrementing test data pattern to be transmitted through the
audio channel. On the receiver side, the audio data checker checks and compares whether the
incrementing test data pattern is received and decoded correctly.
Simulation Walkthrough
Setting up and running the HDMI simulation example consists of two steps.
1. Copy the simulation files from <IP root directory>/altera/altera_hdmi/sim_example to
your working directory.
2. Generate the IP simulation files and scripts, compile, and simulate.
a. Open your command prompt.
b. Type the command below and enter.
sh runall.sh
This script executes the following commands:
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Command
Generate the simulation files for the
HDMI cores.
• ip-generate --project-directory=./ --componentfile=./hdmi_rx_single.qsys --output-directory=./
hdmi_rx_single/sim/ --file-set=SIM_VERILOG -report-file=sopcinfo:./hdmi_rx_single.sopcinfo -report-file=html:./hdmi_rx_single.html -report-file=spd:./hdmi_rx_single/sim/hdmi_rx_
single.spd --report-file=qip:./hdmi_rx_single/
sim/hdmi_rx_single.qip
• ip-generate --project-directory=./ --componentfile=./hdmi_rx_double.qsys --output-directory=./
hdmi_rx_double/sim/ --file-set=SIM_VERILOG -report-file=sopcinfo:./hdmi_rx_double.sopcinfo -report-file=html:./hdmi_rx_double.html -report-file=spd:./hdmi_rx_double/sim/hdmi_rx_
double.spd --report-file=qip:./hdmi_rx_double/
sim/hdmi_rx_double.qip
• ip-generate --project-directory=./ --componentfile=./hdmi_tx_single.qsys --output-directory=./
hdmi_tx_single/sim/ --file-set=SIM_VERILOG -report-file=sopcinfo:./hdmi_tx_single.sopcinfo -report-file=html:./hdmi_tx_single.html -report-file=spd:./hdmi_tx_single/sim/hdmi_tx_
single.spd --report-file=qip:./hdmi_tx_single/
sim/hdmi_tx_single.qip
• ip-generate --project-directory=./ --componentfile=./hdmi_tx_double.qsys --output-directory=./
hdmi_tx_double/sim/ --file-set=SIM_VERILOG -report-file=sopcinfo:./hdmi_tx_double.sopcinfo -report-file=html:./hdmi_tx_double.html -report-file=spd:./hdmi_tx_double/sim/hdmi_tx_
double.spd --report-file=qip:./hdmi_tx_double/
sim/hdmi_tx_double.qip
Merge the four resulting msim_
setup.tcl scripts to create a single
mentor/msim_setup.tcl script.
Compile and simulate the design in the
ModelSim software.
ip-make-simscript --spd=./hdmi_tx_single/sim/hdmi_
tx_single.spd --spd=./hdmi_tx_double/sim/hdmi_tx_
double.spd --spd=./hdmi_rx_single/sim/hdmi_rx_
single.spd --spd=./hdmi_rx_double/sim/hdmi_rx_
double.spd
vsim -c -do msim_hdmi.tcl
Generate the simulation files for the
HDMI cores.
Merge the resulting msim_setup.tcl
scripts to create a single mentor/msim_
setup.tcl script.
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Command
Compile and simulate the design in the
ModelSim software.
Example successful result:
#
#
#
#
#
#
SYMBOLS_PER_CLOCK = 4
VIC = 0
AUDIO_CLK_DIVIDE = 800
TEST_HDMI_6G = 1
Simulation pass
** Note: $finish : bitec_hdmi_tb.v (647)
Time: 15702552 ns Iteration: 3 Instance: /bitec_hdmi_tb
# End time: 14:39:02 on Feb 04,2016, Elapsed time: 0:03:17
# Errors: 0, Warnings: 134
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If an IP core version is not listed, the user guide for the previous IP core version applies.
IP Core Version
User Guide
16.0
HDMI IP Core User Guide
15.1
HDMI IP Core User Guide
15.0
HDMI IP Core User Guide
14.1
HDMI IP Core User Guide
© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, NIOS, Quartus and Stratix words and logos are
trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
B
Document Revision History for HDMI User
Guide
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Date
December
2016
Version
2016.12.20
Send Feedback
Changes
• Updated the HDMI IP core resource utilization table with 16.1
information.
• Added a note for YCbCr 4:2:2 video format that 8 and 10 bits per
color use the same pixel encoding as 12 bits per color, but the valid
bits are left-justified with zeroes padding the bits below the least
significant bit.
• Added information for the new Design Example parameters.
• Removed all Arria 10 design example related information. For more
information about Arria 10 design examples, refer to the HDMI IP
Core Design Example User Guide.
• Edited the typos in the HDMI Audio Format topic.
• Added information that the HDMI IP core does not support 8channel audio.
• Added a new output port version[31:0] for HDMI source and sink.
© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, NIOS, Quartus and Stratix words and logos are
trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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ISO
9001:2008
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Document Revision History for HDMI User Guide
Date
May 2016
Version
2016.05.02
Changes
• Updated the HDMI IP core resource utilization table with 16.0
information.
• Added information about Audio Metadata Packet for HDMI Specifica‐
tion Version 2.0.
• Added information about new HDMI source ports:
• audio_metadata[164:0]
• audio_format[4:0]
• Added information about new HDMI sink ports:
•
•
•
•
•
Altera Corporation
• audio_metadata[164:0]
• audio_format[4:0]
• vid_lock
• aux_error
Provided detailed information about the HDMI source and sink
audio_de[7:0] port.
Updated the testbench diagram and description to include audio data
and auxiliary data information.
Added a note for Altera PLL to place the PLL in the transmit path
(pll_hdmi_tx) in the physical location next to the transceiver PLL.
Updated the HDMI sideband signals (HDMI AVI and VSI bit-fields)
with default values.
Added links to archived versions of the HDMI IP Core User Guide.
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Date
November
2015
Version
2015.11.02
B-3
Changes
• Updated the HDMI IP core resource utilization table with 15.1
information.
• Changed instances of Quartus II to Quartus Prime.
• Added full support for Arria 10 devices.
• Added support for new features:
• Deep color
• 8-channel audio
• Added the following parameters for HDMI source:
• Support for 8-channel audio
• Support for deep color
• Added the following parameters for HDMI sink:
• Support for 8-channel audio
• Support for deep color
• Manufacturer OUI
• Device ID String
• Hardware Revision
• Updated the following interface ports for HDMI source:
• Added ctrl port
• Removed gcp_Set_AVMute and gcp_Clear_AVMute ports
• Updated the following interface ports for HDMI sink:
• Added ctrl , mode, in_5v_power, and in_hpd ports
• Removed gcp_Set_AVMute and gcp_Clear_AVMute ports
• Updated the HDMI sink and source block diagrams to reflect the new
features.
• Provided block diagrams for deep color mapping.
• Generalized the HDMI hardware demonstration design for all
supported device families (Arria V, Stratix V, and Arria 10) with
detailed description.
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Date
May 2015
Version
2015.05.04
Changes
• Updated the HDMI IP core resource utilization table with 15.0
information.
• Added information about 4 symbols per clock mode.
• Added information about Status and Control Data Channel (SCDC)
for HDMI specification version 2.0.
• Added the following interface ports for HDMI source:
• TMDS_Bit_clock_Ratio
• Scrambler_Enable
• Added the TMDS_Bit_clock_Ratio interface port for HDMI sink.
• Updated the HDMI hardware demonstration design with HDMI 2.0
information.
• Added software process flow for the HDMI hardware demonstration.
December
2014
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2014.12.15
Initial release.
Document Revision History for HDMI User Guide
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