E522.43 - Elmos Semiconductor AG

E522.43 - Elmos Semiconductor AG
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
General Description
Input voltage range from 6V to 32V (tran. 42V)
Fixed frequency Step-Down converter with selectable center frequency 250kHz, 500kHz or
2MHz
Advanced PWM voltage regulation loop with 100%
duty cycle capability
Fixed 5V±3% USB BUS voltage, with seven programmable negative resistance adjustments
Programmable USB corresponding output currents
of 0.6/1.8A/2.5A/3.5A with fixed limits or regulation
+/-25% synchronizable to center frequency via PLL
Exclusively pin-configurable
USB 2.0 high speed compatible data line switches
with protection function
Wake-on USB functionality
Adjustable coding network for SDP or BC1.2 CDP
downstream loads and DCP or individual USB
chargers
Short to GND and VBAT protection for BUS and
data lines, overvoltage and temperature protection
Full automotive qualification AEC-Q100
Thermally efficient 5x5mm 20pin QFN package
operational up to 105°C ambient
The E522.43 is a USB 2.0 compatible Stand-Alone
power supply with protection features for the automotive environment. Protection includes ISO7637 pulses
on the input, as well as short to battery/ground on the
USB bus and data lines.
The system setup and device configuration is done via
hard wired resistor divider to the VDD line with parity
check for coding safety.
An internal DC-DC converter provides efficient USB
5V supply from either vehicle battery or a lower voltage bus rail. Selectable soft power-up sequence protects the external parts from overload and reduces inrush currents. It is possible to program a current dependent output voltage gain up to -400mΩ for current
induced wire losses along the USB cable.
The switching frequency can be synchronized in Master-Slave configurations with other devices via PLL input. In addition the switchable spread spectrum option
reduces EMI.
The E522.43 supports USB charging downstream
loads according to the Battery Charging Specification
Revision 1.2 and various other specific USB charger
emulations.
Ordering Information
Applications
Ordering No.:
Automotive Infotainment, Navigation and Radio
Units.
• USB Chargers
•
ASystem activate inputA
ASynchronizing frequencyA
E52243B62C
E52243B62CXX2
Version
Package
-
QFN20L5
Wettable flanks
QFN20L5
EN
VDD
AInterrupt request outputA
ADevice Configuration Pin 1A
ADevice Configuration Pin 2A
ADevice Configuration Pin 3A
AUSB2.0 Data communication (+)A
AUSB2.0 Data communication (–)A
INTB
CFG1
CFG2
CFG3
E522.43
Optional ESD
Clamp
D+
D-
USB
Connector
Figure 1: Typical Application
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
Elmos Semiconductor AG
Data Sheet
1/49
QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
1 Package
The device is assembled in a 5x5mm 20pin QFN package according to JEDEC standard MO-220K, variant
VHHC-2.
Elmos packages meet the requirements of the latest JEDEC outline specification. For JEDEC outline specifications see the free downloads at http://www.jedec.org or contact your local Elmos key account manager.
1.1 Pinout
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
Elmos Semiconductor AG
Data Sheet
2/49
QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
1.2 Pin Description
Name
Pin
No.
Type
Description
SUP
1
HV,S
High voltage power supply input for IC. Needs to be bypassed with an
input capacitor >1uF.
GND
2
S
Ground connection of device. Make a short, low impedance connection to systems ground plane.
VDD
3
A,O
Linear regulator output for internal supply. Bypass with at least 1uF
ceramic capacitance.
D+
4
D,B
USB 2.0 - 480Mbit/s compatible digital bus line. Connect to hostcontroller.
D-
5
D,B
USB 2.0 - 480Mbit/s compatible digital bus line. Connect to hostcontroller.
PD+
6
A,B
High voltage and ESD protected USB 2.0 - 480Mbit/s compatible digital bus line for vehicle interface.
PD-
7
A,B
High voltage and ESD protected USB 2.0 - 480Mbit/s compatible digital bus line for vehicle interface.
CFG1
8
A,B
First analog input pin for device configuration.
CFG2
9
A,B
Second analog input pin for device configuration.
Enable pin and optional synchronization frequency input. Activates device from SLEEP and STANDBY modes. Needs a 250us(min) high
pulse to wake up IC from SLEEP mode. This pin doubles as a synchronization input. Synchronization frequencies of 500kHz ±25% will
be passed to the power supply.
EN
10
HV,I
INTB
11
A,I
Low-active interrupt line for error detection,and as an interrupt to the
microcontroller. NMOS open-drain 3.3V output.
CMP
12
A,B
Error amplifier compensation. Connect the compensation network to
this pin.
CFG3
13
A,B
Third analog input pin for device configuration.
LX1
14
HV,O
High side switch drain for DC-DC converter. Connect to cathode of
freewheeling Schottky diode and switching end of inductor.
LX2
15
HV,O
High side switch drain for DC-DC converter. Connect to cathode of
freewheeling Schottky diode and switching end of inductor.
SW1
16
HV,S
High side switch source for DC-DC converter. Connect to supply voltage and bypass to GND with a suitable capacitor. For dimensioning
see “Typical Operating Circuit”
SW2
17
HV,S
High side switch source for DC-DC converter. Connect to supply voltage and bypass to GND with a suitable capacitor. For dimensioning
see “Typical Operating Circuit”
CHDR
18
S
Gate supply for the internal power FET between SW[1,2] and LX[1,2].
Connect a low ESR ceramic capacitor between this pin and SW[1,2]
BUS
19
A,I
Feedback for USB bus voltage and low end current sense input. Connect directly to output capacitance of DC-DC circuitry at the downstream end of the current sense shunt.
CS
20
A,I
High end current sense input for DC-DC converter. Connect between
switching inductor and current sense shunt.
D = digital, A = analog, S = Supply, I = Input, O = Output, B = bidirectional, HV = High VoltageElectrical
Specification
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
Elmos Semiconductor AG
Data Sheet
3/49
QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
1.3 Die Marking
1.3.1 Top Side
ELMOS
52243B
XXXXP
YWWR@
Table 1: Top Side
where
Signature
Explanation
52243
ELMOS project number
B
ELMOS project revision code
XXXX
Production lot number
P
Assembler code
YWW
Year and week of assembly
R
Mask revision code
@
ELMOS internal code
Table 2: Marking of the Devices
1.3.2 Bottom Side
No marking.
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
2 Operating Conditions
2.1 Absolute Maximum Ratings
•
•
•
No.
Operating the device at or beyond these limits may cause permanent damage.
All voltages are referred to ground (0V) if not specified otherwise.
Currents flowing into the circuit have positive values.
Description
Condition
Symbol
Min
1
Supply voltage input
2
Supply voltage input at Load Dump
3
Regulator output voltage for internal
supply
4
Data signal voltage at host controller
side
5
Max
Unit
VSUP
-0.3
40
V
VSUP,LD
-0.3
42
V
VVDD
-0.3
3.6
V
VD+/-
-0.3
VVDD+0.3 or
3.6V
V
Data signal voltage at portable device
side
VPD+/-
-0.3
40
V
6
Data signal voltage for device configuration
VCFG1
-0.3
VVDD+0.3 or
3.6
V
7
Data signal voltage for device configuration
VCFG2
-0.3
VVDD+0.3 or
3.6
V
8
Output voltage of error amplifier
(1)
VCMP
-0.3
VVDD+0.3 or
3.6
V
9
Interrupt signal voltage
(1)
VINTB
-0.3
VVDD+0.3 or
3.6
V
10
Enable signal voltage
(1)
VEN
-0.3
40
V
11
Data signal voltage for device configuration
(1)
VCFG3
-0.3
VVDD+0.3 or
3.6
V
12
Output voltage of power MOSFET
(1),(2)
VLX1/2
-0.3
VSW1/2+0.3 or
40
V
13
Input voltage of power MOSFET
VSW1/2
-0.3
40
V
VCHDR
VVSW1,2-9V
VVSW1,2+0.3
V
Load dump: t <
400ms
(1)
(1)
14
Regulator output voltage for high-side
driver supply
15
Feedback input voltage
VBUS
-0.3
40
V
16
Current sense input voltage
VCS
-0.3
40
V
17
Current into digital pins SCL, SDA,
EN, INTB, ADR, CS
IDIG
-10
10
mA
18
Current into error amplifier compensation output pin CMP
ICMP
-7
7
mA
19
Current into high-side P-channel
driver pins SW1,SW2, LX1, LX2
IHSDRV
-1.5
1.5
A
20
Current into USB data line pins D+,
D-, PD+, PD-
IUSB,DAT
-30
30
mA
21
Current into USB output voltage pin
BUS
IBUS
-120
120
mA
22
Average current into high-side gate
driver supply pin CHDR
ICHDR
-20
20
mA
23
Ext. load current drawn from VDD
IVDD,LOAD
-2
0
mA
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
No.
Description
Condition
Symbol
Min
Max
Unit
-40
150
°C
2
Year
150
°C
RTJAH
24
K/W
RTJC
8
K/W
PVTOT
1500
mW
24
Storage temperature
Soldered device and
for QFN package
without wettable
flanks.
TSTG
25
Storage time information for a QFN
package with wettable flanks at room
temperature.
Unsoldered device,
Sidewall plating, maximum ambient temperature of 25°C is
mandatory
tSTGT
26
Junction temperature
TJ
(3)
27
Thermal resistance junction to ambi- QFN20L5
ent, high conductivity
28
Thermal resistance junction to case
29
Continuous power dissipation
QFN20L5(3)
(4)
TAMB=25°C
-40
Table 3: Maximum Ratings
(1)
whichever is smaller
(2)
static value
(3)
In general the thermal performance of a QFN package significantly depends of the PCB design:
The thermal resistance RTJAH from junction to ambient corresponds to a highly conductive environment like
e.g. a multilayer PCB with internal thermal planes and an adequate thermal contact between PCB and the exposed die pad of the package.
The thermal resistance RTJC from junction to case indicates the thermal performance of the QFN package as
such, assuming an ideal thermal contact between the exposed die pad and a heat sink.
These thermal resistance values shall help to estimate the actual thermal performance of the QFN package
in the customer application.
(4)
For safe operation meet the following condition: TAMB+RTH*PVTOT<150°C
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
2.2 Recommended Operating Conditions
•
•
•
•
No.
Parameters are guaranteed within the range of rec. operating conditions unless otherwise specified.
All voltages are referred to ground (0V).
Currents flowing into the circuit have positive values.
The first electrical potential connected to the IC must be GND. (If not specified specify timing sequence of electrical contacts.)
Description
Condition Symbol
Min
Typ
Max
U
Temperature
1
Operating temperature
TAMB
-40
VSUP
4
VSW1/2
8
VBUS
105
°C
32
V
32
V
VBUS+0.3
V
0.1
VVDD
VSUP
V
0.1
VVDD
VVDD
V
VCONF+0.05
V
Voltage
2
Supply voltage input range for internal supply at pin SUP
(1) (3)
3
Supply voltage input range for internal SMPS power switch
(2)
4
Measurement voltage related to
VBUS
VCS
5
Low-level input voltage at the pin
EN
VEN,L
6
High-level input voltage at the pin
EN
VEN,H
7
Low-level synchronizing input voltage at the pin EN
VSYNC,L
8
High-level synchronizing input voltage at the pin EN
VSYNC,H
9
High-Level voltage selection step
VCONF for device configuration at
the pins CFG1/2/3
(4)
VCFG,H
10
Low-Level voltage selection step
VCONF for device configuration at
the pins CFG1/2/3
(4)
VCFG,L
VCONF0.05
ICFG
0
10
µA
250
750
µs
12
VBUS+0.15
VVDD-0.6
VVDD-0.6
VCONF
VCONF
V
Currents
11
Input current at pin CFG1/2/3
Time and Frequency
12
rising edge at the tEN,WAKE
Time to wake-up the device in
SLEEP mode after a switch event pin EN
at the pin EN
13
Debounce time to activate the
SMPS after a switch event at the
pin EN
rising edge at the
pin EN(5)
tEN,ON
1
ms
14
Debounce time to deactivate the
SMPS after a switch event at EN
falling edge at
the pin EN(5)
tEN,OFF
200
µs
15
External synchronizing Frequency
(6)
fSYNC
350
650
kHz
(-30)
(+30)
(%)
16
Time for transition from active into
SLEEP mode after a switch event
at the pin EN
tTRAN,SLEEP
1.5
17
Time for synchronization frequency validation and completely
transition into locked PLL mode
tSYNC,DET
60
ms
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
No.
Description
Condition
Symbol
Min
Typ
Max
CIN
470
680
CVDD
300
1000
U
External Device
18
Supply bypass capacitance between VBAT and GND
-7
19
Supply bypass capacitance 1 between VDD and GND
ESR<800mΩ,
ceramic (X7R)
20
Supply bypass capacitance 2 between VDD and GND
ceramic (X7R)(8)
21
High-side driver regulator bypass
capacitance
ceramic (X7R)
CCHDR
100
nF
22
External capacitance SMPS
ESR>25mΩ,
fOP,SMPS=2MHz(9)
CBUS
150
µF
23
Compensation capacitance 1 for
the SMPS voltage regulation loop.
(9)
CCMP1
6.8
nF
24
Compensation capacitance 2 for
the SMPS voltage regulation loop.
(9)
CCMP2
33
pF
25
Compensation resistance for the
SMPS voltage regulation loop.
(9)
RCMP
10
kΩ
26
Shunt resistor for BUS current
measurement
PTOT≥500mW,
∆Rmax≤1%(9)
RS
50
mΩ
27
External inductance SMPS
RDC=45mΩ,
ISAT=3A,
fOP,SMPS=2MHz(9)
L1
15
µH
28
Freewheeling schottky diode forward voltage
IF=3.5A,
TAMB=25°C
VF,D1
500
mV
CVDD,EMC
µF
2200
nF
1
nF
Table 4: Recommended Operating Conditions
(1)
Supply voltage below this value may lead to reduced output voltages. Both the parameters and the functionalities are no longer guaranteed. Use external voltage detection and switch off the E522.43 via EN pin to
ensure the recommended operating conditions.
(2)
Supply voltage below this value may lead to reduced degree of efficiency of the internal power switch. Use
external voltage detection and switch off the E522.43 via EN pin to avoid this.
(3)
Above 18V the advanced PWM regulation loop approaches the behavior of a typical voltage control mode
(4)
This pin requires a hard-wired connection to one of the 16 possible voltage levels.
(5)
The upper limit depends on the desired functionality.
(6)
Independent of the switching frequency Version.
(7)
The required value can be different depending on the characteristic of supplying source and input filter
topology.
(8)
In parallel for EMC performance.
(9)
The value of the component affects the stability of the SMPS regulation loop and can be different depending on the individual application characteristics and performance properties. In particular, external
components and theirs ohmic parasitics, load resistance variations and corresponding current responses or
desired output voltage accuracy have to be considered for a robust solution. The recommended values correspond to the default standard application.
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
2.3 ESD Protection
Description
ESD HBM Protection at all Pins(1,2)
ESD HBM Protection at PD+/PD- Pins
ESD CDM Protection at all Pins
3)
Min
Max
Unit
-2
2
kV
-1.5
1.5
kV
-500
500
V
Table 5: ESD Conditions
(1)
According to AEC-Q100-002 (HBM) chip level test
Except the Pins PD+/PD3)
According to AEC-Q100-011 (CDM) chip level test
2)
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
3 Electrical Parameters
All electrical specifications are referred to application circuit above, and following working conditions unless
otherwise noted:
•
RUN mode: VSUP=12V, VVDD=3.3V, EN=true, DATA_SW=ON, VBUS=ON, NRP/PROT=ON, PD_DETECT=true, no external load current on VBUS
Other working conditions are:
•
PD_WAIT mode: VSUP=12V, VVDD=3.3V, EN=true, DATA_SW=OFF, VBUS=ON, NRP/PROT=OFF,
PD_DETECT=false
•
CHARG mode: VSUP=12V, VVDD=3.3V, EN=true, DATA_SW=OFF, VBUS=ON, NRP/PROT=ON,
PD_DETECT=true, no external load current on VBUS
•
SLEEP mode: VSUP=12V, tEN=0 for more than 30s, DATA_SW=OFF, Wake_Logic=ON
•
STANBY mode: VSUP=12V, VVDD=3.3V or EN=true with tEN,Wake< tEN < tEN,ON, Data_SW=OFF,
VBUS=OFF, ERR_REG=clear
•
The GND pin of the IC requires a short low-noise connection to the system's ground point. All regulators and reference voltages relate to this pin.
All the following parameters are valid for an ambient operating temperature range of -40°C to 105°C (with respect to the absolute maximum thermal power dissipation), unless otherwise specified.
3.1 Power Supply
No.
Description
Condition
1
Current into SUP pin
2
Min
Typ
Max
Unit
SLEEP mode,
VSUP=12V(1)
ISLEEP,SUP
11
20
µA
STANDBY mode(2)
ISTBY,SUP
6.5
9
mA
IRUN,SUP
7.5
10
mA
10
µA
200
µs
(2),(3),(4)
3
Total current into SUP pin
RUN mode
4
EN Input pull-down current
VEN=3.3V
Maximum time to wake-up the
device in SLEEP mode after a
switch event at the pin EN
rising edge at the pin
EN(2)
5
Symbol
IEN
2
tEN,WAKE
50
125
Table 6: Electrical Parameter: Power Supply
(1)
Operating temperature 25°C
(2)
Without digital communication.
(3)
No external load current on pin BUS and supply current into pin SW1 and SW2, respectively.
(4)
Ensured by design. Not tested in production.
3.1.1 Internal Voltage Regulator 3V3 (VDD)
No.
1
Description
Output voltage
Condition
IVDD=5mA
Symbol
Min
Typ
Max
Unit
VVDD
3.1
3.3
3.5
V
Table 7: Electrical Parameter: VDD
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
3.1.2 High-Side Drive Regulator
No.
1
Description
Condition
Symbol
Min
Typ
Max
Unit
VCHDR
VSW1/2-8
VSW1/2-7
VSW1/2-6
V
ICHDR=10mA
High-side driver voltage
Table 8: Electrical Parameter: HSDRV
3.1.3 Supply Monitor
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
1
Power supply undervoltage lockout
threshold at pin SUP
falling edge at
pin SUP
VSUP,UV
3.6
3.8
4.0
V
2
Power supply on threshold at pin SUP rising edge at
VSUP,ON
4
4.2
4.4
V
3
Power supply undervoltage lockout
threshold at pins SW1 and SW2
falling edge at
pin SW1/2(1)
VSW1/2,UV
5.5
5.75
6
V
4
Power supply on threshold at pins
SW1 and SW2
rising edge at
pin SW1/2
VSW1/2,ON
6
6.25
6.5
V
5
Power supply overvoltage lockout
threshold at pins SUP, SW1 and SW2
(1)
VOV
32
33.5
35
V
6
Critical SW1/2 input voltage low
threshold
falling edge at
pin SW1/2
VCRIT,L
6.5
7
7.5
V
7
Critical SW1/2 input voltage high
threshold
rising edge at
pin SW1/2
VCRIT,H
7
7.5
8
V
8
BUS Voltage reset threshold at the pin falling edge at
the pin BUS
BUS
VBUS,RES
0.5
0.7
V
9
SMPS undervoltage lockout threshold VBUS≤6V
at pin BUS
VBUS,UV
0.88
0.92
0.96
VBUS
10
SMPS overvoltage lockout threshold at VBUS≤6V
pin BUS
VBUS,OV
1.04
1.08
1.12
VBUS
11
Maximum SMPS voltage lockout
threshold at pin BUS
VBUS,MAX
6.3
6.5
6.7
V
12
High-side driver undervoltage lockout
threshold at pin CHDR
VCHDR,UV VSW1/2-5.5
13
Secondary Power supply undervoltage falling edge at
pin SUP
lockout threshold at pin SUP
VSUP,UV2
5.75
6
6.25
V
14
Secondary Power supply on threshold rising edge at
pin SUP
at pin SUP
VSUP,ON2
6.5
6.75
7
V
pin SUP
VSW1/2-5 VSW1/2-4.5
V
Table 9: Electrical Parameter: SUP_MON
(1)
Programmed via CFG1, CFG2 and CFG3 configuration pins.
3.1.4 Power Good - External Reset Generation
(1)
Table 10: Electrical Parameter: PWG
Rising edge of the output voltage of the SMPS crossing the undervoltage threshold level.
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
3.1.5 Power-on Reset - Internal Reset Generation
No.
Description
Condition
1
Power-on reset threshold at pin VDD
rising edge at pin
VDD
2
Power-off threshold at pin VDD
falling edge at pin
VDD
Symbol
Min
Typ
Max
Unit
VPOR,H
2.75
2.9
3.05
V
VPOR,L
2.65
2.8
2.95
V
Min
Typ
Max
Unit
Table 11: Electrical Parameter: POR
3.1.6 Temperature Monitor
No.
Description
Condition
Symbol
1
Shutdown temperature
TSHUTDOWN
165
°C
2
Recovery temperature
TRECOVER
145
°C
Table 12: Electrical Parameter: TEMP
3.2 Switch-Mode Power Supply
No.
Description
Condition
Symbol
ILX1/2
1
Maximum application output current
VSW1/2=8V, VCHDR=1V
to GND(1)
2
BUS voltage regulation voltage
(1)
3
Input resistance at the pin BUS
Min
Typ
Max
Unit
2.5
A
VBUS1
4.85
5.0
5.15
V
RBUS
15
22
28
kΩ
Symbol
Min
Typ
Max
Unit
Gm
1.2
1.8
2.4
mS
Table 13: Electrical Parameter: SMPS
(1)
Ensured by design. Not tested in production.
3.2.1 Voltage Regulation Loop
No.
Description
Condition
Error Amplifier
1
2
3
TAMB=25°C, ICMP=0µA(1)
Transconductance
(1),(2)
Open-loop DC gain
ICMP=0µA, VBUS=5.0V
Gain bandwidth product
ICMP=0µA, CCMP=60pF(1),(2)
ADC
60
GBW
3
dB
MHz
2-Level Feedback Limiter
4
Low threshold voltage of hard
feedback limitation at the pin
BUS
VLLIM
0.93
0.95
0.97
VBUS
5
High threshold voltage of hard
feedback limitation at the pin
BUS
VHLIM
1.03
1.05
1.07
VBUS
Table 14: Electrical Parameter: VRL
(1)
Ensured by design. Not tested in production.
(2)
Depending on the combined compensation network at the pin CMP and the application performance.
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
3.2.2 Current Regulation Loop
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
ILIM1
0.54
0.6
0.66
A
ILIM2
1.62
1.8
1.98
A
3
ILIM3
2.25
2.5
2.75
A
4
ILIM4
3.15
3.5
3.85
A
Current Regulation and Limitation limits
1
Current limit 1 to 4
2
(1)
Negative Resistance Programming (NRP)
5
6
Source resistance 1 to 3 of the BUS
output voltage
RSHUNT = 50mΩ
(1)
7
measured at the pin
BUS
8
Limitation threshold of output voltage
correction
9
Response time of the output regulation ∆ILOAD≤1A(2)
Rgain1
-100
mV/A
Rgain2
-250
mV/A
Rgain3
-400
mV/A
VNRP,LIM
5.75
tNRP
6
6.25
V
250
µs
Table 15: Electrical Parameter: CRL
(1)
Programmed via CFG1, CFG2 and CFG3 configuration pins.
(2)
Ensured by design. Not tested in production.
3.2.3 Softstart
No.
1
Description
Condition
Softstart times
Symbol
Min
tSST1
(1)
Typ
Max
4
Unit
ms
Table 16: Electrical Parameter: SOFT_ST
(1)
No external synchronizing frequency or SPC mode.
3.2.4 Power Stage
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
RLXT1,2
50
117
235
mΩ
30
60
ns
1
High-side P-channel driver ON- VSW1,2=8V, VCHDR=1V to
GND
resistance at pin LXT1/2
2
Maximum propagation delay
3
Minimum switch on-time
tON,MIN
30
60
4
High-side overcurrent threshold TAMB=25°C, trimmed
for safety shutdown
ILXT,H
4.4
4.6
5.2
A
5
Low-side discharge current
(1)
IBUS,L
85
105
130
mA
6
Duty cycle
(2)
DCYC
0
100
%
7
Low-side undervoltage threshold
for safety shutdown
VLXT,L
-2.4
-1.6
V
(2)
tSW,DEL
-2.0
ns
Table 17: Electrical Parameter: PWR_STAGE
(1)
Only valid during power-down sequence with active discharge.
(2)
Ensured by design. Not tested in production.
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
3.3 Peripheral
3.3.1 Device Configuration Decoding
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
1
VCONF0
0
0.03
0.05
VDD
2
VCONF1
0.07
0.09
0.11
VDD
3
VCONF2
0.14
0.16
0.18
VDD
4
VCONF3
0.2
0.22
0.24
VDD
5
VCONF4
0.26
0.28
0.30
VDD
6
VCONF5
0.32
0.34
0.36
VDD
VCONF6
0.39
0.41
0.43
VDD
VCONF7
0.45
0.47
0.49
VDD
VCONF8
0.51
0.53
0.55
VDD
10
VCONF9
0.57
0.59
0.61
VDD
11
VCONF10
0.64
0.66
0.68
VDD
12
VCONF11
0.7
0.72
0.74
VDD
13
VCONF12
0.76
0.78
0.8
VDD
14
VCONF13
0.82
0.84
0.86
VDD
15
VCONF14
0.89
0.91
0.93
VDD
16
VCONF15
0.95
0.97
1
VDD
ICFG
-1
1
µA
7
8
9
17
Selection thresholds for device
configuration at the pins CFG1,
CFG2 and CFG3
(1)
Input current at the pin
CFG1/2/3
Table 18: Electrical Parameter: Config Decoding
(1)
Programmed via CFG1, CFG2 and CFG3 configuration pins.
3.3.2 SMPS Oscillator
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
Spread Spectrum Mode
10
Output frequency of Spread
Spectrum Oscillator
40
fSPC
kHz
Table 19: Electrical Parameter: SMPS_OSC
(1)
Operating temperature 25°C.
(2)
Center switching frequency in FIX mode. Programmed via CFG1, CFG2 and CFG3 configuration pins.
(3)
Ensured by design. Not tested in production.
(4)
Independent of the switching frequency version.
3.3.3 BUS Current Measurement (BUS_CM)
No.
Description
Condition
Symbol
Min
Typ
1
1.5
MHz
50
kHz
1
Cutoff frequency of AC signal
path
IOUT=0µA(1)
fCUT,AC
2
Cutoff frequency of DC signal
path
(1)
fCUT,DC
3
Safety resistance between the
pins BUS and CS against wire
breakage of feedback
RSAFTY
Max
Unit
25
37.5
55
kΩ
Symbol
Min
Typ
Max
Unit
RON,SW
2
2.5
10
Ω
RON,DIF
-2
2
Ω
Table 20: Electrical Parameter: BUS_CM
(1)
Ensured by design. Not tested in production.
3.4 USB Data Switch and Protection
No.
1
Description
Condition
On resistance PD+/- to D+/-
VPD+/-=VVDD/2
IPD+/-=20mA
2
On resistance mismatch between data line PD+ and PD-
3
Input capacitance PD+/- On
mode
(1)
CON,SW
4
Leakage current off mode
VBUS ≥ 3.6V
ISW,OFF
2
6
-3dB bandwidth per data line
(1)
BW
500
750
Data line short circuit lockout
threshold at the pins PD+/-
(2)
VDAT,SHORT
4
5
6
4.5
pF
10
µA
MHz
4.6
V
Table 21: Electrical Parameter: USB_SWITCH)
(1)
Ensured by design. Not tested in production.
(2)
Only valid during RUN mode.
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
3.5 USB Port Identification
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
1
Detection voltage threshold for Lowspeed SDP/CDP device at the pin PD-
VLSD
2
2.5
2.8
V
2
Detection voltage threshold for Fullspeed SDP/CDP device at the pin PD+
VFSD
2
2.5
2.8
V
3
Minimum debounce time to detect a device at the pin PD+ or PD-
tPD,DET
2
4
Ready to operation time after completed
charger detection until activation the
data switches
5
Differential voltage threshold between
data lines PD+ and PD- for device remove detection
(3)
VPD,REM
100
6
Minimum duration of keep-alive signal
between an enumerated device and
host controller
(4)
tSOF,MIN
15
7
Minimum debounce time to detect a device remove at the pins PD+ and PD-
(5)
tPD,REM
500
(1)
ms
10
µs
200
300
mV
30
50
ns
660
ms
top
Table 22: Electrical Parameter: PORT_IDENT
(1)
See references in "Battery Charging Specification" Revison1.2: tPD,DET
(3)
Only valid after a successful attach event of a SDP/CDP data-transmitting Portable Device.
TDCNN
(4)
According to the “USB2.0 specification“ there must be an enumerated data connection between Portable
Device and host controller with minimum Start-of-Frame Packets at USB protocol layer.
(5)
Ensured by design. Not tested in production.
3.5.1 Standard Downstream Port (SDP)
No.
1
2
Description
Condition
Pull-down resistance at the pin PD+/- trimmed(1)
Symbol
Min
Typ
Max
Unit
RDWN,PD+
14.25
15
15.75
kΩ
RDWN,PD-
14.25
15
15.75
kΩ
Symbol
Min
Typ
Max
Unit
RDWN,PD+
14.25
15
15.75
kΩ
15
15.75
kΩ
0.4
V
1.2
V
Table 23: Electrical Parameter: SDP
(1)
Only connected in PD_WAIT mode configured as SDP for device detection.
3.5.2 Charging Downstream Port
No.
1
2
Description
Condition
trimmed(1)
Pull-down resistance at the pin PD+/-
3
Detection voltage threshold at the pin
PD+ to activate the source voltage
VSRC,PD-
(3)
4
Detection voltage threshold at the pin
PD+ to deactivate the source voltage
VSRC,PD-
(4)
RDWN,PD-
14.25
VSRC,ON
0.25
VSRC,OFF
0.8
1
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
VSRC,PD-
0.5
0.6
0.7
V
5
Source Voltage at the pin PD- in
BC1.2 portable device response
(2)
6
Enable time for activating voltage
source VSRC,PD-
(5)
tSRC,EN
1
ms
7
Disable time for deactivating voltage
source VSRC,PD- after detecting completed primary detection
(6)
tSRC,DIS
1
ms
8
Sink current at the pin PD+
0.6V ≤ VPD+ ≤ 1V
ISINK,PD+
150
µA
Disable time for deactivating current
source ISINK,PD+ after detecting LSD or
FSD
(7)
tSINK,DIS
1
ms
Typ
Max
Unit
100
200
Ω
9
50
100
Table 24: Electrical Parameter: CDP
(1)
Only connected in PD_WAIT mode configured as CDP for BC1.2 detection algorithm.
See references in "Battery Charging Specification" Revison1.2:
(2)
VSRC,PD-
VDM_SRC
(3)
VSRC,ON
VDAT_REF
(4)
VSRC,OFF
VLGC
(5)
tSRC,EN
TVDMSRC_EN
(6)
tSRC,EN
TVDMSRC_DIS
(6)
tSINK,OFF
TCON_IDPSNK_DIS
3.5.3 Dedicated Charging Port
No.
Description
Condition
Symbol
Min
BC1.2 Dedicated charging Port
1
Dedicated charging port resistance between the pins PD+ and PD-
RDCP
USB Custom Charging Port(1)
2
Output voltage at the pin PD+ to emulate (2),(3)
Apple-compatible charger
VCH,PD+
1.65
2
2.35
V
3
Output voltage at the pin PD- to emulate
Apple-compatible charger
(2),(3)
VCH,PD-
2.35
2.68
3
V
4
Input impedance at the pin PD+ to emulate Apple-compatible charger
(2),(3)
RCH,PD+
22
30
38
kΩ
5
Input impedance at the pin PD- to emulate Apple-compatible charger
(2),(3)
RCH,PD-
17
23
29
kΩ
USB Custom Charging Port for Apple-compatible Devices
6
Output voltage at the pin PD+ to emulate (2),(3)
Apple-compatible charger
VCH,PD+
2.35
2.68
3
V
7
Output voltage at the pin PD- to emulate
Apple-compatible charger
(2),(3)
VCH,PD-
1.65
2
2.35
V
8
Input impedance at the pin PD+ to emulate Apple-compatible charger
(2),(3)
RCH,PD+
17
23
29
kΩ
9
Input impedance at the pin PD- to emulate Apple-compatible charger
(2),(3)
RCH,PD-
22
30
38
kΩ
Table 25: Electrical Parameter: DCP
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
(1)
Only programmable via internal OTP Array. Default assignment Apple-compatible Devices for 1A.
(2)
Programmed via CFG1, CFG2 and CFG3 configuration pins.
(3)
Ensured by design. Not tested in production.
3.6 DIGITAL
No.
Description
Condition
Low-level output voltage at the pin INTB
IOUT=4mA
2
Input leakage current at the pin INTB
(1)
3
Maximum debounce time to activate the
SMPS after a switch event at the pin EN
4
1
Symbol
Min
Typ
VINTB,L
Max
Unit
0.4
V
1
µA
IINTB,LEAK
-1
rising edge at pin
EN(2)
tEN,ON
0.8
0.9
1
ms
Maximum debounce time to deactivate
the SMPS after a switch event at the pin
EN
falling edge at pin
EN(2)
tEN,OFF
80
120
160
µs
5
Active discharge switch off-time after
overcurrent event
(2)
tDIS,OFF
2
4
6
Recovery time after overcurrent powerdown sequence
tOVC
4
7
Maximum delay time for starting power-up rising edge at the
sequence of SMPS after a switch event at pin EN,
fOP,SMPS=250kHz(2),(3)
the pin EN
8
Standby timeout for a transition from
STANBY to SLEEP mode
9
Trigger pulse length for retriggering the
Standby timeout at the pin EN
10
(2)
µs
ms
tSMPS,ST
1
ms
tSTBY
29
32
s
tSTBY,TRG
1
100
µs
Timeout in case of incomplete soft powerup sequence
tOUT,ST
10
12
ms
11
Recovery time after aborted soft power-up
sequence
tREC,ST
20
25
ms
12
Break-before-make time between normal
SMPS operation and active discharge
tBBM
13
Minimum refresh time of current measurement
tREFR1
20
µs
14
Minimum refresh time of current measurement
tREFR2
10
µs
15
Error debounce time for all undervoltage
and overvoltage thresholds of the supply
monitor
tDEB,ERR
5
16
Recovery time after overcurrent powerdown sequence (Retry Periode)
tOVC
4
17
Waiting time for re-starting power-up sequence of SMPS after forced BUS reset
tBUS,RES
250
(2),(4),(5)
100
ns
10
µs
ms
335
ms
Table 26: Electrical Parameter: DIGITAL
(1)
In case of no fault condition detected.
(2)
Ensured by design. Not tested in production.
(3)
The delay time depends on the switching frequency of the SMPS an decreases with higher frequencies.
(4)
Forced by Automatic Charge Detection algorithm
(4)
See references in "Battery Charging Specification" Revison1.2: tBUS,RES-
tVBUS_REAPP
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
4 Typical Operating Characteristics
Efficiency [%]
Efficiency vs. Load Current
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
500kHz
2MHz
VSUP=12V, VBUS=5V
0
0.2
0.4
0.6
0.8
1
1.2
1.4 1.6
ILoad [A]
1.8
2
2.2
2.4
2.6
2.8
2.6
2.8
Output Voltage vs. Load Current with different Current Gains
6
400mV/A
350mV/A
300mV/A
250mV/A
200mV/A
150mV/A
100mV/A
disabled
5.9
5.8
5.7
VBUS [V]
5.6
5.5
5.4
5.3
5.2
5.1
5
4.9
0
0.2
0.4
0.6
0.8
1
1.2
1.4 1.6
ILoad [A]
1.8
2
2.2
2.4
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
USB Eye Diagram
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
5 Functional Diagram
PERIPHERAL
SMPS
DC_MAX
Gate
Device
Configuration
Decoding
Gate
Drv
VRAMP_PLL
BUS Current
Measurement
VRAMP_FC
PWM Control
PLL
OVC_S
VRAMP_SPC
VCO
With
Forward
Correction
VRSHUNT
ESD
Protect
PWM
LLIM
HLIM
BUS
Discharge
POWER SUPPLY
References
+
Bias
Sleep
Regulator
Short
Current
Limit
High-side
Driver
2-Level
Feedback
Limiter
PWM
Comp
V_REF
Fast Correction
+/- 3%
Thermal
Protection
POR
OTP
Fuse Array
V_REF
Supply
Monitor
Oscillator
VCMP
GM
OTA
NRZ/Soft-Start
Control
fSYNC
Control Logic
→ Statemachine
→ Sync Control
→ NRP Control
→ OTP Control
→ Clock Control
→ Switch Control
→ Port Control
SWITCH_CTR
PORT_IDENT
PORT_CTR
USB2.0 Standard
Downstream Port
Ident (SDP)
BC1.2 Charging
Downstream Port
Ident (CDP)
BC1.2 Dedicated
Charging Port
Ident (DCP)
Divider Mode
for USB
Charging
Portable Device
Detection
USB_SWITCH
Data Line
Protection
Figure 3: Block diagram
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
6 Functional Description
The E522.43 provides the Stand-Alone interface between commercially available USB host controllers and
the automotive environment. The IC includes a step down converter to supply USB loads with up to 2.5A of
current at 5.0V optional with a variable negative resistance. This voltage is provided by a high-frequency
Switched-Mode power supply with a selectable center frequency of 250kHz, 500kHz or 2MHz. The switching
frequency can be synchronized vial PLL to an external 500kHz 25% clock signal and will scale accordingly
to the center frequency. Spread spectrum and current limits are also pin-programmable. While supporting
USB2.0 data traffic with the host controller. It can withstand shorts to battery voltage and GND on all connector terminals. Standard ESD protection is included on power and data-lines up to 1.5kV, an external ESD
diode network may be necessary to increase this value.
The IC includes overtemperature shutoff, undervoltage, overvoltage and overcurrent protection of the battery
supply voltage and short circuit to ground and battery supply of the bus voltage and data lines. A short on the
data lines will disconnect the interface side PD+ and PD- from the host side D+ and D- keeping all other functions active to allow charging. Any other fault will shut down all outputs and assert INTB. Error conditions can
be cleared by cycling EN. It is possible to set the maximum allowable load current to 0.6A, 1.8A, 2.5 or 3.5A
depending on availability and thermal conditions in the application. Three levels of programmable negative resistance allows to compensate for wire losses from 0 to -400mOhm. In Stand-Alone operation of the IC, for
example in a HUB without microcontroller, or in a charging-only application, the configuration interface via the
pins CFG1, CFG2 and CFG3 can be used to hard-coded typical settings.
The E522.43 is compatible with USB battery charging spec BC1.2 and other commercial downstream loads.
The IC can be configured to operate as standard downstream port (SDP), charging downstream port (CDP)
and dedicated charging port (DCP). The coding resistors and voltages at the data-lines D+ and D- can also
be register selected.
6.1 Power Supply
The internal supply block provides all references, voltages and currents to ensure the functionality and monitoring of the internal blocks. It generates stabilized sleep voltage of 6.5V for the internal wake up logic and
drives the USB switches in the active modes. The internal digital and most of analog parts are powered from
the internal 3.3V regulator at pin VDD. It needs to be bypassed with short connection to GND with a 1uF and
1nF high-quality smoothing capacitor but must not be loaded externally with more than 2mA, for example to
supply pullup resistors, etc.
Furthermore, the E522.43 internally generates a supply rail for the high frequency switching SMPS high-side
gate driver CHDR.
6.1.1 Supply Monitor
The Supply Monitor is used to check the correctness of all supply voltages. It also generates various enable
and reset signals for the internal blocks. In case of power-down event a new power-up sequence is only possible if the voltage at the pin BUS is less than the BUS voltage reset threshold. In case of activated Negative
Resistance Programming option the monitor thresholds of the output voltage at the pin BUS are adjusted ratiometric.
If the supply voltage at the pin SUP in case of undervoltage falls below 3V, the E522.43 is shut down without
any indication at its INTB pin. In all other cases of undervoltage or overvoltage condition the faulty system
state is displayed at the pin INTB.
If the input voltage for the SMPS high-side driver at SW1/2 drops below under a value of 6V at the input voltage of SW1/2 (VSW1/2,UV) or at the input voltage of SUP (VSUP,UV2) the SMPS is switched off and the E522.43
enters in the undervoltage error state. The same behavior occurs in the case of overvoltage condition, but
where both input voltage lines at pins SW1/2 and SUP are monitored with the same lockout threshold (VOV).
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
The under- and overvoltage monitoring at the power supply inputs can be switched off using the corresponding configuration at the pin CFG1 regarding to all switching frequencies:
•
SW/SUP_Monitor_OFF = "0100", "0101", "1010" and "1011"
Note: Caution, it should be noted that the E522.43 in the case of deactivated power supply monitoring has no
further protection features.
Regardless of activating the under- and overvoltage monitoring, the SMPS is switched off at any case, if the
input voltage at pin SUP drops below 4V (VSUP,UV).
The enable signal of the internal circuitry is based on the VDD output voltage.
The internal power switch of the SMPS is enabled only, if the additional supply rail CHDR has settled within
their limits.
6.1.2 Reset Generation and Temperature Monitor
The POR block generates the internal power-on reset signal for the digital part and several analog blocks
above 2.8V. The power-on reset signal is based on the voltage at the pin VDD. If the VDD voltage falls below
2.4V, the digital part is reset. Therefore, the SMPS regulator is stopped and the data switches are turned off
immediately. The SMPS high-side driver and power switch are set to tristate.
After activating the SMPS power-up sequence with EN pin the output voltage have settled to their nominal
value. After the output voltage of the Switch-Mode Power Supply crossing the power good threshold VPWG for
more than tPWG,DUR the power-up sequence of the SMPS is hence completed successfully.
If the output voltage at the pin BUS is not reached within tOUT,ST of 10ms at least the power good level, it is assumed a faulty condition and the ongoing power-up sequence is aborted. When the BUS voltage has already
increased above the reset threshold level VBUS,RES by the incomplete power-up sequence, it is actively and current limited discharged again.
After complete discharge of the output voltage and expiration of the recovery time tREC,ST, the E522.43 initializes a new soft power-up sequence.
6.2 Switch-Mode Power Supply
The USB bus supply is powered by a fixed frequency, Switched-Mode Power Supply with input voltage feedforward architecture. The gate voltage for the internal Power MosFet is stored in a capacitor connected between CHDR and SW1/2. An external freewheeling Schottky diode, LC filter and 50mOhm current sense resistor complete the circuit. BUS is used as feedback for the converter. A first order compensation network
gets attached to the pin CMP. For detailed information see section 7 Typical Operating Circuit and Component Selection.
The Switch-Mode Power Supply is a high-voltage CMOS step-down DC-DC converter as a optimized voltage
control system. Four superimposed regulation loops control the output voltage of the SMPS:
•
The standard voltage-mode error amplifier path regulates the output voltage at the BUS pin.
•
A two point regulator improves fast load transient behavior.
•
A feed-forward architecture compensates the input power variations and improves the power supply
rejection of output voltage.
•
A optional current regulator loop allows for full current limited operation during output short-circuits.
The DC-DC converter has many features which are programmable via the configuration pin interface CFG1,
CFG2 and CFG3:
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
•
Soft-start time is 4ms to reduce inrush currents and output voltage overshoot.
•
Output voltage can be set to fixed 5.0V overlayed with a negative, load current dependent resistance
from 0mΩ to -400mΩ to compensate for wiring resistance.
•
Output current limit is programmable to allow maximum average load currents of 600mA, 1.8A, 2.5A,
and 3.5A to conform to various USB load levels.
•
Operating frequencies 250kHz, 500kHz and 2Mhz can be chosen as center frequencies.
•
Spread spectrum or frequency synchronization can be selected to control EMI.
The SMPS supports an active discharge control of the external capacitor to provide a safe power-down function, so the overall application is able to perform a BUS reset for the portable device or changing the port
characteristics. The sinking current at pin BUS is therefore internally limited during an active discharge event
(power-down sequence).
6.2.1 Voltage Regulation Loop
The voltage regulation loop represents an advanced fixed frequency voltage mode system, which compensates the disadvantages of conventional voltage regulation system. It offers with respect to the switching frequency and the usable load range better control characteristics as a current control system.
A major disadvantage of a typical voltage regulation system is the dependence of the output voltage from the
input voltage. This property leads to a constant readjustment of the input voltage variation by the error amplifier. To avoid this, the slope of the ramp voltage is adjusted as a function of the input voltage by the SMPS
oscillator. This improvement of the regulation loop leads to an effective feedforward correction of input voltage variations.
For a further improvement of the Voltage Regulation Loop provides an additional two-point controller, which is
superimposed on the fundamental error amplifier. It also compares the input with the reference voltage of the
voltage regulation loop and intervenes only when the control deviation exceeds a defined upper limit. Under
this circumstance, the analog regulation loop is bypassed and the two-point controller directly determines the
PWM sequence. With this topology transient load characteristics such as load current variations at output capacitances with higher ESR values can be compensated. Furthermore, it also allows a maximum duty cycle
of 100% in case of low-drop condition.
6.2.2 Current Regulation Loop
The E522.43 monitors the average value of the external application output current to the USB load by measuring of the corresponding voltage across the shunt resistor RS (see 6.3.3 BUS Current Measurement). The
limitation of the application current can be done in two different ways according to the USB port standards:
•
Current Regulation
•
Current Limitation (Shut-Down)
Current Regulation
When the Current Regulation option is enabled with the corresponding external resistor dividers, the primary
voltage control loop is superimposed by a combined output current regulation. For this purpose, the reference
voltage of the voltage control loop error amplifier will be modified in case of overload condition immediately
and unfiltered by the signal provided from the current measurement amplifier. With this function the
Switched-Mode Power Supply is permanently short-circuit proof and thus it preserves the external components from damaging overload.
Due to this reference regulation, the output voltage of the Switch-Mode Power Supply can be reduced until
the overload condition is removed. If this happens, the regulation process of the reference voltage is reversed
and the E522.43 regulates the output voltage back to the correct value in the usual manner. The response
time of the output current respectively voltage regulation is typically 250µs.
When exceeding the threshold of the programmed current range, the Switch-Mode Power Supply will automatically and smoothly change into the current regulation mode and vice versa in faultless condition. An oc-
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Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
curred overload event and subsequent derating of the output voltage is shown as a warning. The E522.43
displays this condition by setting the pin INTB on low level. If the current regulation option is activated, the undervoltage monitoring of the output voltage at the pin BUS is disabled and the appropriate system response
suppressed.
The current regulation option is activated at the pin CFG1 and the four possible regulation current limits are
set at pin CFG3 with the corresponding configuration voltage regarding to the NRP value:
•
ILIM1 = "0000", "0111", "1000", "1111" – 0.6A
•
ILIM2 = "0001", "0110", "1001", "1110" – 1.8A
•
ILIM3 = "0010", "0101", "1010", "1101" – 2.5A
•
ILIM4 = "0011", "0100", "1011", "1100" – 3.5A
Current Limitation
When the Current Limitation option is enabled with the corresponding external resistor dividers, a four-stage
programmable sharply bounded safety shutdown is available. If the application current reaches the specified
threshold, the Switched-Mode Power Supply is turned off and simultaneously the output voltage is actively
discharge. The current limit function is based on the mean value of current measurement amplifier and is
therefore bandwidth limited by its filter characteristic.
After detection of an overcurrent event and complete discharge of the output voltage the device will remain
disabled for the time tOVC before a restart can be initiated in faultless system condition.
An occurred overcurrent event and subsequent power-down sequence is shown as an error and the E522.43
displays this condition by setting the pin INTB on low level.
The current limitation option is activated at the pin CFG1 and the same four possible regulation current limits
are set at pin CFG3 with the corresponding configuration voltage regarding to the NRP value:
•
ILIM1 = "0000", "0111", "1000", "1111" – 0.6A
•
ILIM2 = "0001", "0110", "1001", "1110" – 1.8A
•
ILIM3 = "0010", "0101", "1010", "1101" – 2.5A
•
ILIM4 = "0011", "0100", "1011", "1100" – 3.5A
Negative Resistance Programming (NRP)
Supplying large currents via USB cables provides special challenges for the system designer. The E522.43
implements a strategie to prevent brown-out at the USB receptacle. The output voltage can b track the load
current. Negative Resistance Programming (NRP) implements a current dependent voltage gain on VBUS.
The E522.43 offers the possibility to compensate current induced wire losses along the USB cable with a
feedforward correction of the output. It acts as a negative resistance of the output voltage. The response time
of the output voltage correction is also typically 250µs. The feedforward correction is only activated after the
completed soft power-up sequence, to avoid exceeding overshoot at this phase. A limitation function prevents
the output voltage rises above 6V in case of overcurrent. This prevents overvoltage at the load in case of intermittent connections, or if the load is suddenly removed.
It should be noted that the application current measurement and therefore the overcurrent handling behaviour
is also influenced by the limitation function simultaneously. If the dynamic range of the current measurement
path is reduced by an excessive rising of the feedforward corrected BUS voltage, the current limit thresholds
of the overcurrent handling can be increased. Or the dynamic behavior can vary slightly. Therefore the application should be necessarily balanced with respect to output current, USB cable resistance and NRP value.
However, the system is always reliably protected by the additional fast current limitation of the high-side
power switch (ILXT,H).
The Negative Resistance Programming option and its three different source resistances of the BUS output
voltage are set with the corresponding configuration voltage at pin CFG3 regarding to the current limits:
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Data Sheet
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Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
• Rgain0 = "0000" to "0011" – off
•
Rgain1 = "0100" to "0111" – 100mV/A
•
Rgain2 = "1000" to "1011" – 250mV/A
•
Rgain3 = "1100" to "1111" – 400mV/A
6.2.3 Softstart
The Switch-Mode Power Supply has a soft power-up sequence with 4ms time period. This ensures that the
output voltage is reached without overshooting or with proper magnetization of the external inductor.
The charging current through the inductor L1 during the soft power-up sequence is calculated as follows:
The time periods of the soft power-up sequence must be adapted to the switching frequency and external
components. In case of external synchronization, the time periods of soft power-up sequence are changing
proportionally. In SPC mode, however, the change in power-up time is in accordance with the lesser effective
frequency modulation of only 5%.
6.2.4 Power Stage
The Switch-Mode Power Supply contains an internal high-current high-side power switch of P-channel MOSFET and the associated internal bridge driver. The output pins of the internal power switch LXT1 and LXT2
must be connected together with low-resistant and needs a short connection to the cathode of external freewheeling schottky diode and to the switching end of inductor, respectively. Consequently, the SMPS operates
in an asynchronous mode. This allows for high efficiency over a wide range of input voltages and output currents. For a optimal degree of efficiency and current distribution the input pins of the internal power switch
SW1 and SW2 must also be connected together with low-resistant, as well as the output pins LXT1 and
LXT2.
A Current measurement and corresponding safety shutdown is implemented in internal driver stage. The fast
current limitation is always active, that is during normal operation and soft power-up sequence. Regardless of
the selected handling of the application current to the USB load, this safety feature has priority.
In addition to a possible overcurrent event, systems with asynchronous driver stages have the application risk
that the necessary external free-wheeling schottky diode is not or not sufficiently contacted to the IC pin.
However, a resulting interruption of the inductor current flow doesn't necessarily lead to a noticeable failure of
the BUS output voltage but to a overload operation via parasitic bulk paths. For FMEA safety reasons the
switching notes LXT1 and LXT2 are monitored and in case of faulty voltage conditions the same safety
shutdown procedure is initiated as in overcurrent situations.
In addition to the high-side switch, the power stage includes a low-side N-channel MOSFET as a static current source to discharge actively the output capacitor and output BUS voltage, respectively. The Low-side
discharge current IBUS,L is typically 105mA. Thereby the discharge current and internal power dissipation is
limited. The power-down sequence is initiated whenever either the E522.43 was turned off with the appropriate EN signal or any fault condition has occurred except for USB data error (DAT_ERR). The active discharge is ceased, when the voltage at the feedback pin BUS drops below the reset threshold level VBUS,RES.
In case of a low-resistant short to VBAT only an overtemperature event terminates the discharge attempt. An
prolonged overvoltage condition is shown and will cause asserting a low-state on INTB pin to signalize a
warning.
At the same time, the low-side N-channel MOSFET can be used for improved switching performance at light
load conditions. If this light load option is enabled, the static current source turns on automatically under an
application output current of 100mA. Due to this additional load the Switch-Mode Power Supply remains in
the continuous mode and operates at the programmed, center switching frequency without pulse skipping. If
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Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
the application output current increases above 250mA, the current source switches off again to optimize the
power loss. For a reliable detection of the two operating conditions a debounce time of 1ms is implemented.
The light load option is set with the corresponding configuration voltage at pin CFG2 regarding to the high
current USB port charateristic and parity:
•
LightLoad_On = "1100" to "1111"
6.3 Peripheral
The block Peripheral includes all the components that are in some way interacting with external or applicative
signals. These include the Device Configuration Decoding, the synchronizable SMPS Oscillator and the BUS
Current Measurement. All components are assigned to different functional groups.
6.3.1 Device Configuration Decoding
With the configuration pin interface CFG1, CFG2 and CFG3 the system setup and device configuration is realized via hard wired resistor divider to the VDD line. The applied analog voltages of the three pins are
sequentially digitized with an internal ADC during the soft power-up sequence. For coding safety, the applied
configuration voltages are sampled three times in succession. If the sample process is not reproducible
respectively doesn't always give the same result, then the E522.43 assumes an impermissible state and
begins no soft power-up sequence. A parity check further improves the fault detection in coding configuration
(see chapter 6.6.4 Device Configuration).
6.3.2 SMPS Oscillator
The oscillator generates a sawtooth signal for the PWM comparator of the Switch-Mode Power Supply voltage regulation loop. It consists of a triangle oscillator with feedforward correction to compensate input power
supply variations.
The multifunctional oscillator can be used in 3 different modes of operation:
•
Fix Frequency Mode (FIX Mode)
•
Phase-Locked Loop Mode (PLL Mode)
•
Spread Spectrum Mode (SPC Mode)
Fix Frequency Mode
The FIX mode is the default method of operation, where the switching frequency of the Switch-Mode Power
Supply is derived exclusively from the internal sawtooth generator. It consists of a master oscillator and an
adjustable phase integrator which generates the different ramp voltages for the PWM comparator.
Whenever no valid external synchronizing frequency signal is present on EN pin or during the power-down
sequence of the output voltage, the voltage regulation loop works with this oscillator mode.
Three working frequencies can be programmed via the configuration pin CFG1 regarding to the overcurrent
handling option and spread spectrum mode:
•
fOP,SMPS1 = "0000" to "0101" - 2MHz
•
fOP,SMPS2 = "0110" to "1010" - 500kHz
•
fOP,SMPS3 = "1011" to "1111" - 250kHz
Phase-Locked Loop Mode
In the PLL mode the switching frequency of the E522.43 can be synchronized in Master-Slave configurations
with other devices via the PLL input pin EN or alternatively pin ADR. The master oscillator is thereby operated
as a voltage controlled oscillator and results in conjunction with the internal Frequency-Phase Detector and
the Loop Filter in a Phase-Locked Loop. As result, the master oscillator and thus the switching frequency of
the Switch-Mode Power Supply is synchronized to the external supplied reference frequency fSYNC.
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Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
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The Loop Filter is implemented as a first-order passive low pass filter and its parameter determine the properties of PLL for instance stability, lock time or damping factor. The Frequency-Phase Detector represents a
typical structure of type IV and thus has no effective bandwidth limitation. It also avoids crossover distortion at
the critical centerlock point. The output voltage of such a Frequency-Phase Detector depends in the lock condition from phase error and in the unlock condition from the frequency error.
Just as in the FIX mode, the same three working frequencies can be programmed however, as center frequencies. The external synchronizing frequency is independent of the programmed center frequency and
amounts to always 500kHz 25%. The Phase-Locked Loop shall be locked when the phase difference is
smaller than 10° and achieves this lock condition also independently of the programmed center frequencies
in all cases within the lock time tLOCK of 300µs.
The synchronization frequency can be applied either at the enable pin EN or - if separation of enable and synchronization is preferred - the configuration pin CFG3 offers an alternative for external frequency synchronization:
1. Using EN as a synchronization pin
To activate the PLL mode, a external synchronizing frequency within the recommended operating limits must
be applied on the PLL input pin EN. Once a valid frequency signal is detected for a minimum period tSYNC,DET
and the PLL is locked, the oscillator will automatically switch into the PLL mode. If the external synchronizing
signal is stopped, the system interprets the last applied voltage level as the static EN control signal and responds accordingly. If the Switched-Mode power supply remains active, the internal oscillator switches back
automatically to the programmed center switching frequency. This automatic frequency detection works already in the STANDBY mode and allows a synchronization of the switching frequency even during the powerup sequence phase. In this operating mode, the power-up time are changing at the same degree as the effective switching frequencies.
Note: The usual debounce time to activate the SMPS tEN,ON is omitted in case of properly external frequency
synchronization.
2. Using CFG3 as a synchronization pin
In contrast to the EN pin, CFG3 is used as a configuration pin for the system setup and must not be changed
for a proper device function. To activate the PLL mode via the config pin CFG3, the soft power-up sequence
of the SMPS must be first initiated conventionally with activating of EN. Upon entering soft power-up sequence the selection step of configuration voltage is latched and pin CFG3 can only after two system clocks
(about 100ns) act as synchronization input. The configuration setting of pin CFG3 will remain latched until
the soft power-up sequence is entered the next time.
Once a valid frequency signal is detected for a minimum period tSYNC,DET and the PLL is locked, the oscillator
will automatically switch into the PLL mode. If the external synchronizing frequency is stopped and the EN
signal is still active, internal oscillator switches back automatically to the programmed center switching frequency. Compare to the other case, the automatic frequency detection works not directly in the beginning of
power-up time. But still allows a synchronization of the external frequency shortly after the beginning of the
power-up sequence phase.
Spread Spectrum Mode
The SPC mode is a combination of the two oscillator modes described above and serves to reduce EMI due
to the high switching frequency. For this purpose, the master oscillator is superimposed a small additional frequency component by the Spread Spectrum Oscillator in the same manner as in the PLL mode by the voltage controlled oscillator. However, the wobble signal of the Spread Spectrum Oscillator has a fixed amplitude
of 100mV (5% signal swing of master oscillator) with respect to the programmed center frequency and a
constant frequency of 40kHz. The superimposition of the Spread Spectrum Oscillator reduces the conducted
disturbances from the Switch-Mode Power Supply according to the application by 8dB to 10dB.
Just as in the FIX or the PLL mode, the same three center frequencies can be programmed with the configuration pins. The SPC mode must be selected at the pin CFG1 regarding to the overcurrent handling option
and switching frequencies.
Note: Due to the oscillator superimposition, the switching frequency of the Switch-Mode Power Supply in this
SPC mode can not be simultaneously synchronized to an external reference frequency via the PLL.
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Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
6.3.3 BUS Current Measurement
The function of the BUS Current Measurement unit shall be to detect the instantaneous value of the external
inductor and prepare it for the further processing in the Current Regulation Loop of the Switch-Mode Power
Supply or for the analog to digital conversion. To do this, first the inductor-current equivalent voltage across
the shunt resistance RS is measured with an instrumentation amplifier. Thereafter, the resulting signals are filtered suitable. The instrumentation amplifier consists of two different signal paths, namely an AC and an DC
path.
Additionally, the current-depended forward correction of the output voltage (NRP) is determined based on the
bandwidth-limited average value of the external inductor. On the other hand the unfiltered signal path represents the current ripple of the external inductor and is used for fast Current Regulation Loop in the SwitchMode Power Supply.
6.4 USB Data Switch and Protection
The E522.43 transmits data traffic between the bus line pins D+/D- and the protected connector pins
PD+/PD-, thus from the host controller to the portable device in the automotive environment and vice versa
as it is necessar for the USB On-the-Go function. A high-voltage and wide-bandwidth analog switch connects
the two communicating participants together and supports USB2.0 operation up to the highest USB2.0 communication rate of 480MBit/s without significantly distorting the USB signal.
The analog switches are powered by the internal control voltage and protect the susceptible low-voltage interface of host controller against shorts to BUS voltage or battery voltage. The data line voltages are monitored
internally and in case of overvoltage condition the switches will be disabled.
The data switches connect the protected connector side with the host side only in RUN mode either after a
portable device attach event or by manual transition through the microcontroller. In the other functional states
the data lines are disconnected and used in PD_WAIT mode for the required handshake procedure according to the BC1.2 specification described below.
6.5 USB Port Identification
The following statements and information about USB port handling, data communication and various handshaking refer to the Universal Serial Bus Specification Revision 2.0 (USB2.0) and additionally to the Battery
Charging Specification Revision 1.2 (BC1.2) of 2010. It is advisable to consult these versions of documents
named above to implement any USB port applications with the E522.43.
The Universal Serial Bus (USB) has developed to a widely used method of data communication between personal computers and peripheral electronic equipment, such as keyboards or disk drives. This industry standard specifies cables, connectors, communication protocols, data rates or handshaking procedures.
The ability to recharge batteries and the prevalence of USB applications involved to separate USB chargers
as wall adapters. This allow the portable devices to utilize the same connection equipment for data communication and charging from either a computer port or alternatively a wall adapter. This type of power supply is
increasingly being used for portable media players, smartphones or PDAs. Such modern devices, however,
require significantly more current for normal operation and an optimum charging process simultaneously, as
offered by separate wall adapters. To meet these increasing demands on the charging process, additional
new ports have been developed with improved power supply properties beyond the USB2.0 standard downstream port (SDP). Another major advantage of the charging ports in addition to the increased currents itself
is the possibility that portable devices may draw the maximum charge current without digital negotiation. The
Battery Charging Specification Revision 1.2 is an extension of the basic USB2.0 specification and defines the
following two charging ports:
•
Charging Downstream Port (CDP)
•
Dedicated Charging Port (BC1.2-DCP)
Charging downstream ports support both improved power supply and data communication with the portable
device, whereas dedicated charging ports are intended only for pure charging applications. The dedicated
charging ports therefore represent a special form of wall adapters, the data channels are shorted. Both
charging ports provide a maximum current of 1.5A. In order to determine on which type of port a portable de-
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Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
vice is connected and how much current it can draw, a mandatory handshake process according to the
BC1.2 specification is required. The handshake process will be described later.
In addition to the BC1.2 standard, some manufacturers of consumer electronics pursue individual approaches for the wall adapters for charging the batteries of their portable devices. This allows the charging
process to be optimized individually for each device. In this case the upper current limit is determined only by
the USB2.0 cables and receptacles. This type of protocol is called Divider Mode or Custom Charging Port
(CCP) and differs from the BC1.2-DCP by the modified handshake procedure and available charging currents.
The following table shows the available ports according to the BC1.2 specification and to CCP Mode, which
are supported by the E522.43.
Port
Allowed Charging Current
by The Portable Device
USB Communication
Standard Downstream Port
500mA
Yes
Charging Downstream Port
1.5A
Yes
Dedicated Charging Port
1.5A
No
Dedicated Charging Port in Divider Mode
2.5A
No
Table 27: Supported standard USB Port Characteristics
6.5.1 Standard Downstream Port (SDP)
The SDP is a conventional downstream port that complies the USB2.0 definition and supports USB data
communication. A portable downstream device that is connected to an SDP can be enumerated with the host
and may draw a maximum charge current up to 500mA when the bus is not suspended and appropriately
configured.
The SDP data lines PD+ and PD- must be pulled down to ground with the two pull-down resistors RDWN,PD+
and RDWN,PD-. An SDP may recognize the communication speed of a connected portable device on the behavior of the data lines. After initial speed identification process the host and the portable device use one of the
communication protocol above to negotiate the high-speed data communication if both sides conform the
necessary hardware conditions. Thus the USB port handling, respectively handshaking is completed.
6.5.2 Charging Downstream Port (CDP)
The CDP is a downstream port that complies the USB2.0 definition and supports USB data communication
as well as the SDP. The difference to an SDP is the improved power supply and charging characteristic, respectively. A portable downstream device that is connected to a CDP can draw charge current up to maximum of 1.5A regardless of a successful enumeration with the host.
For the data communication and the accurate charging process of a portable device it is necessary to distinguish between the standard port and the charging port. The required handshake procedure for the port identification according to the BC1.2 specification consists of two steps: the primary detection and the secondary
detection.
Primary detection is used to differentiate between an SDP and the other two charging ports CDP or DCP.
Portable devices that have not been enumerated within the time of 1s after the primary detection is completed are required to perform a second step, the secondary detection. This step allows a portable device to
decide whether a CDP or a DCP it is attached to.
In conclusion the connected portable device notifies its communication speed in the same manner as an
SDP. The identification represented by the pull-up on the data lines PD+ or PD- completes the BC1.2 handshake again. This shared handshake completion indicator for both data communication port types allows all
exclusively SDP-devices to connect also to the CDP port. Therefore, even if the two handshake procedures
are not properly occurs, although a data connection is activated to the host controller.
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There are some newer portable devices on the market such as smartphones, where the above BC1.2 handshake procedure takes place not in all cases or only incompletely. To prevent deadlock's of the system due to
such errors or problems during the port handling process, the BC1.2 handshaking procedure must be finished within a maximum time periode of 1.5s. This time corresponds to TDCD_TIMEOUT from the "Battery Charging Specification" Revision1.2. There will be no activation of one of the data lines, the ongoing handshake
procedure is canceled and the USB data switches are automatically closed. This establishes in spite of the
handshake error a connection between the portable device and the host controller. It will proceed henceforth
as an Standard Downstream Port (SDP).
6.5.3 Dedicated Charging Port (DCP)
The DCP is a downstream port that can only provide power via the USB standard connector to a portable device and thus charge its batteries. This special form of wall adapters is used exclusively in charging applications with USB connection equipment. A DCP is unable to enumerate a downstream portable device and
therefore does not support USB data communication. With the help of different impedances either on or between the unused data lines a portable device can identify the port as an individual wall adapter. The E522.43
supports depending on the selected configuration in STANDBY mode either the BC1.2 standard or the individual states of USB custom charging mode.
BC1.2 Dedicated Charging Port
Due to its shorted data lines with the maximum impedance of RDCP a standardized BC1.2-DCP conforms with
the BC1.2 handshake procedure above and therefore provide a maximum charging current of 1.5A.
USB Custom Charging Port
In contrast to the BC1.2-DCP in the Custom Charging Port (CCP) or divider mode different settings are possible regarding impedances or identification voltages presented on the data lines.
However, the customized decoding values for impedances and identification voltages can be only specified
and individualized by programming of the internal OTP array because of lack of the communication interface.
If this is not the case, the preset configuration of an Apple-compatible Device is used for this port and the
E522.43 provides a maximum charging current of 1A.
Automatic Charge Detection
The E522.43offers the possibility of an automatic portable device BC1.2 charging handling for keeping an
connected USB Host Controller away from annoying tasks concerning BC1.2 Charging issues.
The implemented algorithm monitors the measured load current of an attached portable device and justifies
itself as an Dedicated Charging Port with either BC1.2-DCP or preset CCP configuration. Using this setings
the attached portable device is charging with an optimal load current. Hence this procedure can achieve fast
portable device battery charging times for many kinds of different devices.
After the power-up sequence of the Switch-Mode Power Supply is completed, the automatic charge detection
algorithm begins with the preset Custom Charging Port for Apple-compatible devices (see 3.5 USB Custom
Charging Port for Apple-compatible Devices). Thereafter in each time interval of 500ms the charging output
current is measured and evaluated, whether a portable device is connected or not. If the output current is
above 750mA, the state machine remains in this optimal charging configuration for this device. Otherwise,
the system switches to the standard BC1.2 Dedicated Charging Port (see 3.5.3 BC1.2 Dedicated charging
Port) and retest the output current over the same time interval. If the output current in any interval falls below
the limit of 75mA, the system will interpret this fact either as a detach event of the portable device or as completed charging process. The detection algorithm transferred the system then in an empty state with the standard BC1.2 DCP configuration and maintained until the charging current increases over the limit of 375mA. In
this case the automatic detection algorithm is pass through again from the initial configuration. At each port
change event between the two different charging ports or the Idle state a complete USB BUS Reset occurs
(see chapter Fehler: Referenz nicht gefunden Fehler: Referenz nicht gefunden).
According to the BC1.2 specification it relies on defined steps involving Port role changing, bus reset regulations, timings, etc. Also it handles portable device with weak or dead batteries.
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
For making the device ready for this mode you only have to configure the corresponding configuration voltage
at the pin CFG2 regarding to the properly parity:
•
AutoCharge_On = "1010" or "1011"
The Automatic Charge Detection is finally activated with an completed power-up sequence after EN pin is set
Figure 4: State Machine for Automatic Charge Detection
Note: The configuration of the USB port behavior only affects the data-lines PD+ and PD-. The actual current
capability of the power supply is defined by the settings of corresponding configuration pin CFG3.
6.5.4 Device Attach
Once a portable device is powered up via the 5V USB bus, two ways exist during which it negotiates the
sources capability to provide different currents.
1. Directly after attachment to the USB receptacle.
2. During digital enumeration with the host controller after attach has taken place.
The E522.43 can detect an attach event of a downstream device on its data-lines PD+ and PD-. Itsupports all
USB charging downstream loads according to the Battery Charging Specification Revision 1.2 and various
other specific USB charger emulations. For applications without extensive configuration options the Charging
Downtstream Port is the most appropriate alternative for data-communicating devices because SDP devices
can also connect without any compatibility problems. For Portable Devices in pure charging mode, the Automatic Charge Detection feature should be chosen in order to achieve the maximum flexibility.
6.5.5 USB Bus Reset
To change port behavior settings, it is necessary for the E522.43 to enter STANDBY mode and force a USB
bus reset by taking EN low. According to BC1.2 a bus reset has occurred once the USB bus voltage has
fallen below the BUS Voltage reset threshold VBUS,RES (max 0.7V) for a minimum time of 100ms. However,
there are some newer portable devices on the market such as tablet PC's that do not comply with all BC1.2
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
requirements. In order to prevent deadlock's of the system due to reset timing problems during the port
handling process in the Automativ Charge Detection algoritm, the time period of BUS reset has been
increased to a minimum value of 250ms. This time corresponds to tVBUS_REAPP from the "Battery Charging
Specification" Revision1.2.
An internal Low-side discharge current source of typical 105mA on VBUS discharges the typical bypass
capacitance of 150µF in approximately 6ms. Only after a complete BUS discharge under the reset threshold,
a Portable Device recognizes this reset condition and a new power-up sequence can be initiated. For faster
reset times, it is possible to attach an additional pull-down resistor to VBUS which may have to be gated with
EN in order to reduce the quiescent current.
6.5.6 Portable Device Remove Detection
In many applications, there is no status information or feedback signals from the host controller, if the
enumerated data connection to the Portable Device is still active or in general exist. Therefore, it is not possible for the E522.41 after a load detection and successful hand over process of the dataline control to the host
controller to assess the status of the data connection directly at USB protocol level. However, this status information is important for USB state control, because the emulation of different USB ports and the USB data
transmission can not be executed simultaneously. This leaves two possibilities for indirect connection status
detection, namely the USB load current measurement and the electrical monitoring of the USB data lines.
Since the load current consumption of a Portable Device depends on certain operating conditions such as
battery status, the load current measurement method is not always meaningful. For this reason, the Portable
Device remove detection is realized by monitoring the activity of both data lines D+ and D-.
If an active USB data communication takes place between the Portable Device and the host controller, then
the data pulses occur frequently within a (micro)frame corresponding to the USB speed modes (low-, full- or
high-speed). When no USB data is transferred but the Portable Device remains plugged in or enumerated in
the system, the host controller sends at least one keep-alive or Start-of-Frame (SOF) signal in recurring time
intervals. A high-speed mode microframe should take 125us (tHSFRAME). Consequently the SOF signals follow
every 125us in the shortest case with the fastest data transmission rate and have a partially evaluable period,
in which the both data lines have a speed characteristical signal difference. In the most critical high-speed
case a minimum of 400mV. Evaluating these recurring signal sequence with a pair of comparators within the
SOF signals, it results an image of the data line activity. Subsequently a contact status information is created
with a re-triggering monostable multivribator from the comparator signals.
Based on this status information the state machine is switched between the active RUN mode and the emulation ready PD_WAIT mode without VBUS reset at any time. This means that after correct activating of the
E522.41 the handling respectively transition between emulation and data transfer takes place independently
excluding the affecting of the host controller.
To allow a Host Negotiation according to On-The-Go and Embedded Host Supplement to the USB Revision
2.0 Specification (USB OTG), a Portable Device remove is only processed by the state machine if no data
line activity is monitored for at least tPD,REM.
The Portable Device Remove Detection function is only enabled in the data-transmitting USB modes and after a successful attach event of a Portable Device. Portable Devices in pure charging mode are usually not
connected on charging downstream ports. Should it be enforced, the remove detection is not necessary because no data transfer take place. In contrast, the attach or detach detection in charging modes is based on
the load current as described in the Automatic Charge Detection mechanism.
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
6.6 Sytem Setup and Configuration
The digital part controls the Switch-Mode Power Supply and the USB Data Switch handling by means of a
state machine. It also displays fault and critical conditions.
6.6.1 Control Unit
Fig. 1: State Machine
The state machine of the E522.43 controls the process of enabling and disabling the DC/DC converter and
USB Data Switches depending on the state of operation. The transitions are primarily depending on the behavior of the EN pin, the Supply Monitor signals or external attach events.
The E522.43 can be set to different states:
•
SLEEP mode: all circuitry except for the wake-up part is powered off.
•
STANDBY mode: all circuitry except for the Switch-Mode Power Supply is powered on.
•
RUN mode: EN is set to high level. The Switch-Mode Power Supply is operating. A USB device is
connected and able to communicate.
There are some transition states, that are managed completely by the state machine. These include the
PWR_UP_SMPS mode and PWR_ERROR mode. These states are necessary to ensure proper magnetization of the external coils without saturating them, and correct demagnetization and core reset, respectively. In
these transition states the Supply Monitor observes the voltages at the feedback input BUS and enforces the
power-down sequence of the SMPS voltage regulation. The power-up state PWR_UP_SMPS will be left automatically, when the output voltage of the SMPS has settled within its power-good limits.
Any detected fault or error condition will interrupt the general control flow. In dependence on the type of error
different reactions will be initiated. A detailed description of error handling can be found in section 6.7 System
Errors and Diagnostics.
The E522.43 returns in all device configurations and from all active system states to STANDBY mode, when
EN is deactivated again.
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
6.6.2 Start-up Procedure
In the Stand-Alone configuration, no microcontroller is available and the E522.43 is controlled by the EN pin
and the power supply voltage at the pin SUP, respectively. The device changes with increasing power supply
voltage VSUP into the SLEEP mode. The EN pin can be connected either to the power supply voltage or controlled separately with digital voltage level.
If the EN pin is switched on and power supply voltage at pin SUP has reached the On-threshold VSUP,ON2, the
E522.43 leaves the SLEEP mode, the Switch-Mode Power Supply is enabled and the soft power-up sequence is initiated within the PWR_UP_SMPS state. For this reason the STANDBY mode is passed over and
the power-up sequence begins after the start debounce time tEN,ON immediately.
Deactivating the EN pin to low state the BUS voltage will be powered down after the debounce time tEN,OFF and
the data lines becomes open simultaneously. This secures that the device is in its STANDBY mode. The
E522.43 will automatically revert to the SLEEP mode with its minimum power consumption after the time tSTBY
of typically 30 seconds. The timer begins to run only when the BUS voltage is completely discharged below
the BUS Voltage reset threshold VBUS,RES (max 0.7V). In the following timing range the EN pin should stay low.
If the conditions are fulfilled the E522.43 goes into the SLEEP mode. The Device can remain in STANDBY
mode, if an short high-pulse is generated periodically within standby timeout tSTBY at the pin EN.
In case of a connection between SUP pin and EN pin, the E522.43 can not switch from the RUN mode to the
STANDBY or to the SLEEP mode. The only way to control the E522.43, is to switch on or off completely with
the power supply voltage VSUP. However, it must be paid attention to the down-slope of the power supply voltage to ensure a safe power-down function prior an Power-On Reset event.
The system can also be started with a valid synchronization frequency on one of the input pins, namely EN
and CFG3. In dependence of selected frequency input pin this automatic frequency detection and immediate
start of the soft power-up sequence work already in, or shortly after the STANDBY mode. It allows a synchronization of the switching frequency even during the power-up sequence phase. For more information on how
to activate the PLL mode see section 6.3.2 Phase-Locked Loop Mode.
SLEEP Mode
STANDBY Mode
PWR_UP_SMPS Mode
RUN Mode
STANDBY Mode
SLEEP Mode
VSUP
VSUP,ON
VSUP,UV
EN
t
VVDD
t
VCHDR
t
VPWG VVBUS
t
VSUP
VEN,H
VEN,L
VPOR,H
VPOR,L
VSUP
VCHDR,UV
VBUS,RES
t
VVDD INTB
VDIG,L
t
tEN,WAKE
tEN,ON_MIN
tEN,OFF_MIN
tSTBY_MIN
Fig. 2: Start-up Procedure
6.6.3 User-Controllable Start-up/Power-down Procedures
The following tables show a summary of all meaningful user-controllable Start-up/Power-down procedures
are presented in the E522.43 depending on the device configuration used. Especially in the operating modes
with external synchronization, there are possible combinations that do not correspond to the intended purpose. For example, the attempt to synchronize the Switched-Mode power supply on input pin CFG3 to a external frequency without activating the EN pin. Although the SMPS will start with the external frequency, but is
no longer accessible via the configuration voltage.
Note: The E522.43 must always be first awakened with a short Wake-up pulse on EN.
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Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
Without External Synchronization
No
CFG3
pin
EN pin
Current OpMode
Device Behaviour
1
x(1)
1
STANDBY
Device Start-up with center frequency after
Debounce Time
2
x
0
RUN
Device Power-down with center frequency
after Debounce Time
Table 28: Start-up / Power-down procedures without external frequency synchronization
(1)
x represents don't care condition.
Synchronization on EN pin
No
CFG3 pin
(1)
EN pin
(2)
Current OpMode
Device Behaviour
STANDBY
Device Start-up with synchronization frequency without Debounce Time
fsync_ok
RUN
Device still in RUN mode and changes after
lock_ok to the external synchronization frequency
x
fsync_nok(3)
STANDBY
Device still in STANDBY mode
x
fsync_nok
RUN
Device still in RUN mode with center frequency
1
x
2
x
3
4
fsync_ok
Table 29: Start-up / Power-down procedures with frequency synchronization on EN pin
(1)
x represents don't care condition.
(2)
fsync_ok represents a valid external frequency at the corresponding synchronization input pin.
(3)
fsync_nok represents not valid external frequency at the synchronization input pin EN, but not smaller than
the corresponding Debounce Time for Start-up or Power-down.
Synchronization on CFG3 pin
No
CFG3 pin
(1)
EN pin
Current OpMode
Device Behaviour
1
STANDBY
Device Start-up with synchronization frequency without Debounce Time
fsync_ok
1
RUN
Device still in RUN mode and changes after lock_ok to the external synchronization
frequency
3
fsync_ok
0
RUN
Device Power-down with external synchronization frequency after Debounce Time
4
fsync_nok(2) 1
STANDBY
Device Start-up with center frequency after Debounce Time
5
fsync_nok
1
RUN
Device still in RUN mode with center frequency
6
fsync_nok
0
RUN
Device Power-down with center frequency
after Debounce Time
1
fsync_ok
2
Table 30: Start-up / Power-down procedures with frequency synchronization on CFG3 pin
(1)
fsync_ok represents a valid external frequency at the corresponding synchronization input pin.
(2)
fsync_nok represents not valid external frequency at the synchronization input pin EN
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
6.6.4 Device Configuration
In contrast to the E522.41 all configurations of the E522.43 are based on the background that the device is
not controlled by an external microcontroller and no possibility to communicate via I2C commands with the
device. In this Stand-Alone version, the three configuration pins CFG1, CFG2 and CFG3 are used and interpreted as fixed setup pins. At each of the three pins the setting is done by a resistor divider between VDD line
and GND (see Typical Application). The corresponding voltages for each coding value are listed in 3.3.1 Device Configuration Decoding. The hard wired settings of the three configuration pins must not be changed
during active operation. Changes can only be made during OFF or SLEEP mode.
The following tables show an overview of the possible Settings of the E522.43.
Note: For FMEA safety reasons the system properes are not strict sequenally coded in the configuraon
tables.
Configuration at Pin CFG1
The first configuration pin CFG1 is used for setting the switching frequency, the spread spectrum mode (see
chapter 6.3.2 SMPS Oscillator), the overcurrent handling (see chapter 6.2.2 Current Regulation Loop), and
the enabling of SW/SUP monitoring (see chapter 6.1.1 Supply Monitor):
CFG1
Setting
0
0
0
0
switching frequency 2 MHz, Regulation, SPC
0
0
0
1
switching frequency 2 MHz, Regulation
0
0
1
0
switching frequency 2 MHz, Limitation, SPC
0
0
1
1
switching frequency 2 MHz, Limitation
0
1
0
0
switching frequency 2 MHz, Regulation, SPC, SW/SUP monitor off
0
1
0
1
switching frequency 2 MHz, Limitation, SPC, SW/SUP monitor off
0
1
1
0
switching frequency 500 kHz, Regulation, SPC
0
1
1
1
switching frequency 500 kHz, Regulation
1
0
0
0
switching frequency 500 kHz, Limitation, SPC
1
0
0
1
switching frequency 500 kHz, Limitation
1
0
1
0
switching frequency 500 kHz, Regulation, SPC, SW/SUP monitor off
1
0
1
1
switching frequency 250 kHz, Regulation, SPC, SW/SUP monitor off
1
1
0
0
switching frequency 250 kHz, Regulation, SPC
1
1
0
1
switching frequency 250 kHz, Regulation
1
1
1
0
switching frequency 250 kHz, Limitation, SPC
1
1
1
1
switching frequency 250 kHz, Limitation
Table 31: Selectable Settings at Pin CFG1
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
Configuration at Pin CFG2
The USB port characteristics (see chapter 6.5 USB Port Identification), the Light Load Functionality (see
chapter 6.2.4Power Stage) and the parity extension bit (see below) can be selected by coding at the second
configuration pin CFG2:
CFG2
Setting
0
0
0
0 BC1.2 Standard Downstream Port (SDP), Par0
0
0
0
1 BC1.2 Standard Downstream Port (SDP), Par1
0
0
1
0 BC1.2 Charging Downstream Port (CDP), Par0
0
0
1
1 BC1.2 Charging Downstream Port (CDP), Par1
0
1
0
0 BC1.2 Dedicated Charging Port (DCP), Par0
0
1
0
1 BC1.2 Dedicated Charging Port (DCP), Par1
0
1
1
0 USB Custom Charging Port for Apple-compatible devices, Par0
0
1
1
1 USB Custom Charging Port for Apple-compatible devices, Par1
1
0
0
0 (OTP)Programmable USB Custom Charging Port (CCP), Par0
1
0
0
1 (OTP)Programmable USB Custom Charging Port (CCP), Par1
1
0
1
0 AutoCharge Detection active, Par0
1
0
1
1 AutoCharge Detection active, Par1
1
1
0
0 BC1.2 Charging Downstream Port (CDP), LightLoad, Par0
1
1
0
1 BC1.2 Charging Downstream Port (CDP), LightLoad, Par1
1
1
1
0 USB Custom Charging Port for Apple-compatible devices, LightLoad, Par0
1
1
1
1 USB Custom Charging Port for Apple-compatible devices, LightLoad, Par1
Table 32: Selectable Settings at Pin CFG2
In addition to the predefined USB Custom Charging Port for Apple-compatible Devices, there is a further
possibility of the CCP mode for another individual charging configuration, namely (OTP)Programmable USB
Custom Charging Port (CCP). The arbitrary parameters regarding impedances and identification voltages at
the data lines of the additional CCP option can be stored separately in the OTP array.
Configuration at Pin CFG3
NRP value (see chapter 6.2.2 Negative Resistance Programming (NRP)) and overcurrent thresholds (see
chapter 6.2.2 Current Regulation Loop) are coded at the third configuration pin CFG3:
CFG3
Setting
0
0
0
0
NRP off, overcurrent level 0.6A
0
0
0
1
NRP off, overcurrent level 1.8A
0
0
1
0
NRP off, overcurrent level 2.5A
0
0
1
1
NRP off, overcurrent level 3.5A
0
1
0
0
NRP 100mV/A, overcurrent level 3.5A
0
1
0
1
NRP 100mV/A, overcurrent level 2.5A
0
1
1
0
NRP 100mV/A, overcurrent level 1.8A
0
1
1
1
NRP 100mV/A, overcurrent level 0.6A
1
0
0
0
NRP 250mV/A, overcurrent level 0.6A
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Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
CFG3
Setting
1
0
0
1
NRP 250mV/A, overcurrent level 1.8A
1
0
1
0
NRP 250mV/A, overcurrent level 2.5A
1
0
1
1
NRP 250mV/A, overcurrent level 3.5A
1
1
0
0
NRP 400mV/A, overcurrent level 3.5A
1
1
0
1
NRP 400mV/A, overcurrent level 2.5A
1
1
1
0
NRP 400mV/A, overcurrent level 1.8A
1
1
1
1
NRP 400mV/A, overcurrent level 0.6A
Table 33: Selectable Settings at Pin CFG3
For all other parameterized operating values are not listed above, the following fixed settings will be used:
Parameter
Default Setting
Error handling
Retry activated
Softstart time of SMPS
4ms
Table 34: Default Settings
Parity Check
The parity check is a simple test method for fault detection of the effectively resistor coding. This test method
detects a single-bit transmission error in the interpreted hard wired configuration, but does not serve any
correction. If a single-bit in the resulting 12bit data word (three times 4Bit) of the settings combination above
is changed, then it will no longer have the correct parity. Changing a bit in the original parity checksum gives it
a different parity bit than the expected one. Vice versa changing the parity bit itself and not simultaneously
modifying the parity checksum it again leads to a noticeable error result as well. In this way a single-bit error
is detected in a non-readable system, such as can occur due to derating of the external resistor divider.
For the calculation of parity bit respectively parity combination with the config-pin CFG2 the first two 4-bit data
words of the other pins CFG1 andCFG3 are combined and supplemented with the appropriate third 4bit data
word of Pin CFG2 for an odd parity. Thereafter a simple calculation example, where the E522.43 is to be
configured with the following properties:
Parameter
Setting
NRP value
400mV/A
Overcurrent Threshold
2.5A
Switching Frequency
250kHz
Spread Spectrum Mode
On
Overcurrent Handling
Regulation
SW/SUP monitoring
Off
USB port characteristic
BC1.2 Charging Downstream Port (CDP)
Light Load Functionality
On
Table 35: Example Settings for Parity Calculation
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Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
For the first two configuration pins CFG1 and CFG3 are derived from the tables the first two 4bit data words:
•
CFG1 = "1011"
•
CFG3 = "1101"
For an odd parity the USB port characteristic must be finally chosen at the pin CFG2 so hat the checksum
with the first two 4bit data words is an odd number. In the example, the previous checksum is 6 and it must
therefore be selected the BC1.2 Charging Downstream port with the parity option Par1:
•
CFG2 = "1101"
If the parity check at the configuration pins indicates a data error, the E522.43 is still powered up with the
following safety condition :
Parameter
Default Setting
NRP value
Off
Overcurrent Threshold
0.6A
Switching Frequency
2MHz
Spread Spectrum Mode
Off
Overcurrent Handling
Regulation
SW/SUP monitoring
On
USB port characteristic
BC1.2 Charging Downstream Port (CDP)
Light Load Functionality
Off
Table 36: Safety Settings in case of Parity Error
6.7 System Errors and Diagnostics
Various safety features make the USB supply familiy E522.41 and E522.43 well suited for the automotive environment. While at the Stand-Alone version E522.43 only power supply related errors are communicated,
the use of the I2C bus enables the full diagnostic capabilities of the E522.41 and remains usable in most error
cases. In case of an emergency shutdown due to overtemperature or certain lockout events, all necessary
power supply voltages for the analog or digital part still operate, so the fault condition can be recognized at
the INTB pin. Open drain output INTB signals system errors and warnings to the application and can be used
as an interrupt by any discrete circuitry.
If the retry option is activated the E522.43 initializes continuously a new start-up sequence after complete discharge of the output voltage VBUS. After a successful restart of the Switched-Mode Power Supply the system
tries to come back to the preceding active mode.
The four errors overtemperature, short circuit at the pins LX1 or LX2 (serious overcurrent event), overcurrent
event in limitation mode and a maximum overvoltage at BUS output voltage lead immediately after their occurrence to a non-delayed system response. All other fault conditions regarding to the lockout thresholds of
the Supply Monitor will be delayed by the Error Debounce Time tDEB,ERR of 10µs.
6.7.1 System Errors
The following fault conditions will assert a low signal on the INTB pin to signalize an error:
Error Condition
BUS Voltage
Data
Switch
Identification
Device Action
Undervoltage at the
VDD pin (POR)
OFF
OFF
No identification without Transition to SLEEP mode.
digital part possible.
OverVoltage at the
OFF
OFF
INTB pin is set.
Transition to PWR_ERROR* mode.
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Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
Error Condition
BUS Voltage
Data
Switch
Identification
Device Action
Undervoltage at the
SUP pin
OFF
OFF
Shut down without any
indication.
Transition to OFF mode.
Undervoltage at the
CHDR pin
Power-down
OFF
INTB pin is set.
Transition to PWR_ERROR* mode.
Overcurrent at power Power-down
supply output
OFF
INTB pin is set.
Transition to PWR_ERROR* mode.
Overvoltage across
USB Data Switches
ON
OFF
INTB pin is set.
Transition to CHARG** mode.
Bandgap reference
out of range
Power-down
OFF
INTB pin is set.
Transition to PWR_ERROR* mode.
Timeout in case of in- Power-down
complete start-up sequence
OFF
INTB pin is set.
Transition to PWR_ERROR* mode.
Overtemperature
Power-down
OFF
INTB pin is set.
Transition to PWR_ERROR* mode.
Sampling error of
configuration pins
CFG1/2/3
OFF
OFF
INTB pin is set.
Transition to PWR_ERROR* mode.
pins SUP and SW1/2
Table 37: Fault Conditions
*PWR_ERROR mode deactivates the Switched-Mode Power Supply. As long as the voltage at pin SUP is
maintained, the output capacitance is discharged, and the voltage regulation loop reset for the next start-up
attempt. The subsequent procedure after the occurrence of an error initializes continuously a new start-up sequence after complete discharge of the output voltage VBUS. After a successful restart of the Switched-Mode
Power Supply the system tries to come back to the preceding active mode. When a VBUS overcurrent event is
detected, the Switched-Mode Power Supply will restart after a delay time of tOVC.
**CHARG mode disconnects the interface side PD+ and PD- from the application host side D+ and D- and
keeps all other functions reactive to allow charging. If the short on the data lines is removed, the USB Data
Switches are activated again.
6.7.2 System Warnings
One interrupt event indicates critical system conditions which do lead to a low on INTB. These critical system
conditions do not result in a power-down sequence of the SMPS and are attended for interaction with other
parts of the application.
Interrupt Condition
Identification
Comment
Overload at SMPS output INTB pin is set.
Indication of a SMPS overload condition and
change in the Current Regulation mode. Only
active if this option is configured.
Parity warning
Soft power-up sequence with safety settings.
INTB pin is set.
Table 38: Warning Conditions
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
7 Typical Operating Circuit and Component Selection
7.1 Inductor Selection and Output Current Limitation
In the following tables, the initial values are indicated for the choke. These inductance values should be used
for the first system design of the E522.43 as a function of the switching frequency and the required output
current limit. This provides a matrix that should be sufficient for a first, basic dimensioning. The calculations
are based on a typical input voltage for automotive applications of 13V. The calculated values are rounded to
standard values and takes into account a tolerance of 20% of the choke. The term ∆IL represents the output
current ripple in relation to the programmed current limit.
Recommended Inductance Value at 250kHz Switching Frequency
Current Limit [mA]
Inductance Value [µH]
∆IL = 10%
∆IL = 20%
∆IL = 30%
500
330
150
100
1500
100
56
33
2500
68
33
22
Recommended Inductance Value at 500kHz Switching Frequency
Current Limit [mA]
Inductance Value [µH]
∆IL = 10%
∆IL = 20%
∆IL = 30%
500
150
82
56
1500
56
27
18
2500
33
15
10
Recommended Inductance Value at 2MHz Switching Frequency
Current Limit [mA]
Inductance Value [µH]
∆IL = 10%
∆IL = 20%
∆IL = 30%
39
22
12
1500
12
6.8
4.7
2500
8.2
3.9
2.7
500
Functional Safety
The development of this product is based on a process according to an ISO/TS16949 certified quality
management system. Functional safety requirements according to ISO 26262 have not been submitted to
Elmos and therefore have not been considered for the development of this product.
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
Elmos Semiconductor AG
Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
8 Package Reference
It conforms to to Jedec MO-220-K, version VHHD-4. The pins are side-plated for ease of soldering and inspection.
Figure 5: Package outline
Figure 6: Package dimension table
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
Elmos Semiconductor AG
Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
9 Disclaimer
WARNING – Life Support Applications Policy
Elmos Semiconductor AG is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity
and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing Elmos Semiconductor
AG products, to observe standards of safety, and to avoid situations in which malfunction or failure of an Elmos Semiconductor AG Product could cause loss of human life, body injury or damage to property. In the development of your design, please ensure that Elmos Semiconductor AG products are used within specified
operating ranges as set forth in the most recent product specifications.
General Disclaimer
Information furnished by Elmos Semiconductor AG is believed to be accurate and reliable. However, no responsibility is assumed by Elmos Semiconductor AG for its use, nor for any infringements of patents or other
rights of third parties, which may result from its use. No license is granted by implication or otherwise under
any patent or patent rights of Elmos Semiconductor AG. Elmos Semiconductor AG reserves the right to make
changes to this document or the products contained therein without prior notice, to improve performance, reliability, or manufacturability.
Application Disclaimer
Circuit diagrams may contain components not manufactured by Elmos Semiconductor AG, which are included as means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. The information in the application examples has been carefully
checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of Elmos Semiconductor AG or others.
Contact Information
Headquarters
Elmos Semiconductor AG
Heinrich-Hertz-Str. 1 • D-44227 Dortmund (Germany)
℡: +492317549100
: sales-germany@elmos.com
Sales and Application Support Office North America
Elmos NA. Inc.
32255 Northwestern Highway • Suite 220 Farmington Hills
MI 48334 (USA)
℡: +12488653200
: sales-usa@elmos.com
Sales and Application Support Office China
Elmos Semiconductor Technology (Shanghai) Co., Ltd.
Unit 16B, 16F Zhao Feng World Trade Building,
No. 369 Jiang Su Road, Chang Ning District,
Shanghai, PR China, 200050
℡: +86216219 7502
: sales-china@elmos.com
Sales and Application Support Office Korea
Elmos Korea
Office: C-301, Innovalley, 253, Pangyo-ro,
Bundang-gu, Sungnam-si, Gyeonggi-do,
13486 Korea
℡: +8231714-1131
: sales-korea@elmos.com
Sales and Application Support Office Japan
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3-20-9 Shibaura, Minato-ku,
Tokyo 108-0023 Japan
℡: +81334517101
: sales-japan@elmos.com
Sales and Application Support Office Singapore
Elmos Semiconductor Singapore Pte Ltd.
3A International Business Park
#09-13 ICON@IBP • 609935 Singapore
℡: +65 6908 1261
: sales-singapore@elmos.com
: www.elmos.com
© Elmos Semiconductor AG, 2017. Reproduction, in part or whole, without the prior written consent of Elmos Semiconductor AG, is prohibited.
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
10 Record of revisions
Chapter
Rev.
Description of change
Date
Released
All
.00
Initial Revision
Jul 30, 2014
NGA
2.1 Absolute Maximum Ratings
.01
Defined thermal resistance
junction to case
Apr 8, 2015
NGA
.01
Reduction of ESD robustness
PD+/PD-
Apr 8, 2015
NGA
2.3 ESD Protection
.01
Line 4: (ESD CDM Protection
at Edge Pins) deleted
Apr 21, 2015 GUS/ZOE
First page
.02
Ordering-No. changed
Oct 27, 2015 DTO/ZOE
.03
Line 22: Adaptation of input caApr 20,.2016
pacitor
NGA
.03
Line 30-32: Compensation network usable for all switching
Apr 20,.2016
frequencies
NGA
3.2.4-7 Power Stage
.04
Monitoring of power stage
NGA
3.5 USB Port Identification
.04
Line 7: Adaptation of device reMar 30, 2017
move debounce time
HHAE
6.5.6 Portable Device Remove Detection
.04
Device remove debounce time
Mar 30, 2017
according to USB OTG
HHAE
3.1.3 Supply Monitor
.04
Line 13-14: New secondary
power supply undervoltage
threshold at pin SUP
Mar 30, 2017
HHAE
6.1.1 Supply Monitor
.04
Handling of power supply undervoltage at pin SUP
Mar 30, 2017
HHAE
6.2.4 Power Stage
.04
Detailed description of power
stages
Apr 07, 2017
NGA
6.6.2 Start-up Procedure
.04
Start-up with respect to power
supply undervoltage at pin
SUP
Mar 30, 2017
HHAE
2.3 ESD Protection
2.2 Recommended Operating Conditions
Apr 07, 2017
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
11 Index
11.1 Table of contents
1 Package............................................................................................................................................................2
1.1 Pinout.......................................................................................................................................................2
1.2 Pin Description.........................................................................................................................................3
1.3 Die Marking..............................................................................................................................................4
1.3.1 Top Side...........................................................................................................................................4
1.3.2 Bottom Side......................................................................................................................................4
2 Operating Conditions........................................................................................................................................5
2.1 Absolute Maximum Ratings.....................................................................................................................5
2.2 Recommended Operating Conditions......................................................................................................7
2.3 ESD Protection.........................................................................................................................................9
3 Electrical Parameters.....................................................................................................................................10
3.1 Power Supply.........................................................................................................................................10
3.1.1 Internal Voltage Regulator 3V3 (VDD)...........................................................................................10
3.1.2 High-Side Drive Regulator.............................................................................................................11
3.1.3 Supply Monitor...............................................................................................................................11
3.1.4 Power Good - External Reset Generation.....................................................................................11
3.1.5 Power-on Reset - Internal Reset Generation.................................................................................12
3.1.6 Temperature Monitor.....................................................................................................................12
3.2 Switch-Mode Power Supply....................................................................................................................12
3.2.1 Voltage Regulation Loop................................................................................................................12
3.2.2 Current Regulation Loop................................................................................................................13
3.2.3 Softstart..........................................................................................................................................13
3.2.4 Power Stage...................................................................................................................................13
3.3 Peripheral...............................................................................................................................................14
3.3.1 Device Configuration Decoding......................................................................................................14
3.3.2 SMPS Oscillator.............................................................................................................................14
3.3.3 BUS Current Measurement (BUS_CM).........................................................................................15
3.4 USB Data Switch and Protection............................................................................................................15
3.5 USB Port Identification...........................................................................................................................16
3.5.1 Standard Downstream Port (SDP).................................................................................................16
3.5.2 Charging Downstream Port............................................................................................................16
3.5.3 Dedicated Charging Port................................................................................................................17
BC1.2 Dedicated charging Port.........................................................................................................17
USB Custom Charging Port(1)...........................................................................................................17
USB Custom Charging Port for Apple-compatible Devices...............................................................17
3.6 DIGITAL.................................................................................................................................................18
4 Typical Operating Characteristics..................................................................................................................19
5 Functional Diagram........................................................................................................................................23
6 Functional Description....................................................................................................................................24
6.1 Power Supply.........................................................................................................................................24
6.1.1 Supply Monitor...............................................................................................................................24
6.1.2 Reset Generation and Temperature Monitor.................................................................................25
6.2 Switch-Mode Power Supply....................................................................................................................25
6.2.1 Voltage Regulation Loop................................................................................................................26
6.2.2 Current Regulation Loop................................................................................................................26
Current Regulation.............................................................................................................................26
Current Limitation...............................................................................................................................27
Negative Resistance Programming (NRP)........................................................................................27
6.2.3 Softstart..........................................................................................................................................28
6.2.4 Power Stage...................................................................................................................................28
6.3 Peripheral...............................................................................................................................................29
6.3.1 Device Configuration Decoding......................................................................................................29
6.3.2 SMPS Oscillator.............................................................................................................................29
Fix Frequency Mode..........................................................................................................................29
Phase-Locked Loop Mode.................................................................................................................29
Spread Spectrum Mode.....................................................................................................................30
6.3.3 BUS Current Measurement............................................................................................................31
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
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Data Sheet
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QM-No.: 25DS0140E.04
Stand-Alone Automotive USB Supply with Data-Line Protection
E522.43
Preliminary Information – Apr 21, 2017
6.4 USB Data Switch and Protection............................................................................................................31
6.5 USB Port Identification...........................................................................................................................31
6.5.1 Standard Downstream Port (SDP).................................................................................................32
6.5.2 Charging Downstream Port (CDP).................................................................................................32
6.5.3 Dedicated Charging Port (DCP).....................................................................................................33
BC1.2 Dedicated Charging Port.........................................................................................................33
USB Custom Charging Port...............................................................................................................33
Automatic Charge Detection..............................................................................................................33
6.5.4 Device Attach.................................................................................................................................34
6.5.5 USB Bus Reset..............................................................................................................................34
6.5.6 Portable Device Remove Detection...............................................................................................35
6.6 Sytem Setup and Configuration.............................................................................................................36
6.6.1 Control Unit....................................................................................................................................36
6.6.2 Start-up Procedure.........................................................................................................................37
6.6.3 User-Controllable Start-up/Power-down Procedures.....................................................................37
Without External Synchronization......................................................................................................38
Synchronization on EN pin.................................................................................................................38
Synchronization on CFG3 pin............................................................................................................38
6.6.4 Device Configuration......................................................................................................................39
Configuration at Pin CFG1.................................................................................................................39
Configuration at Pin CFG2.................................................................................................................40
Configuration at Pin CFG3.................................................................................................................40
Parity Check.......................................................................................................................................41
6.7 System Errors and Diagnostics..............................................................................................................42
6.7.1 System Errors................................................................................................................................42
6.7.2 System Warnings...........................................................................................................................43
7 Typical Operating Circuit and Component Selection......................................................................................44
7.1 Inductor Selection and Output Current Limitation..................................................................................44
Recommended Inductance Value at 250kHz Switching Frequency..................................................44
Recommended Inductance Value at 500kHz Switching Frequency..................................................44
Recommended Inductance Value at 2MHz Switching Frequency.....................................................44
8 Package Reference........................................................................................................................................45
9 Disclaimer.......................................................................................................................................................46
10 Record of revisions.......................................................................................................................................47
11 Index.............................................................................................................................................................48
11.1 Table of contents..................................................................................................................................48
ELMOS Semiconductor AG – Headquarters
Heinrich-Hertz-Str. 1 | 44227 Dortmund | Germany
Phone + 49 (0) 231 - 75 49 - 0 | Fax + 49 (0) 231 - 75 49 – 149
definer@elmos.eu | www.elmos.de
Note: ELMOS Semiconductor AG (below ELMOS) reserves the right to make changes to the product contained in this publication without notice. ELMOS assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the
circuits are free of patent infringement. While the information in this publication has been checked, no responsibility, however, is assumed for inaccuracies.
ELMOS does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of a life-support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications.
Copyright © 2017 ELMOS Reproduction, in part or whole, without the prior written consent of ELMOS, is prohibited.
This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.
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