RTC Block Diagram

RTC Block Diagram
Real Time Clock (RTC):
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The basic functions of a real time clock (RTC) are used to display the current time and an alarm
clock with calendar functions.
 The alarms are basically a CPU interrupts.
 Most of the RTC are designed for ultra low power.
 The RTC is driven with 32 KHz clock.
 There are various RTC like
I) RTC_A (uses ACLK or SMCLK).
II) RTC_B (uses LFXT (32 KHz crystal)).
 RTC_A is used on F5529 and provides to use external crystal or internal (on chip) REFO.
 RTC_B is used on FR5969 which is driven with Low frequency external crystal.
 The advantage of RTC_B can be operate LPM 3.5
RTC Block Diagram
 The input clock is divided by pre scalar 0 and pre scalar 1 to provide Sec, Min, Hour, and Day of
Week (DOW), from there to Day, Month, and Year.
 These pre scalar count values are used to…
 Create time-stamps
 Set displays & etc.
RTC Interrupts:
Interrupts are of six types:
1) Alarm (RTCA): Generate interrupt if match between time register and alarm register for
 Minutes
 Hours
 Day of the week

Day (of the month)
2) Interval timer (RTCTEV):
 Generates when RTC count events occur.
 Interrupt can happen for each minute, each hour, midnight, & noon.
3) Pre scalar 0(RT0PS) & 4) Pre scalar 1(RT1PS) : RTC has a capable of generating the time based
interrupts from the pre scalar count value when clock rate is divided by 2, 4, 8, 16, 32, 64, 128, 256.
5) Ready (RTCRDY) : Used to tell or notifies the CPU to safe read or write the RTC registers.
6) Oscillator fault: Generates when CPU is running in LPM 3.5, which cannot detect oscillator. Then
this interrupt wakes up the CPU and notify that the fault occurred at oscillator.
RTC Control Register (RTCCTL):
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If RTCHOLD is set then the clock does not run by default.
The current time and date held in registers.
The egiste s so eti es ill e as o d le gth fo a essi g the ea .
The RTCBCD is used to set the display.
The RTC takes the control on Basic Timer 1, when BTDIV bit = 1.
The interrupt flag bit RTCFG is enabled when RTCIE bit is set.
The flag is set for every minute, hour, daily at noon and at midnight based on RTCTEVx bit.
The bit RTCTEVx determines the intervals.
The maskable interrupts can be accessed in two ways:
1. Interrupts are generated when RTCIE bit is set. Both BTIFG & RTCFG are set when an
interrupt occurs and cleared automatically when it served.
2. Interrupts come from Basic Timer1, if RTCIE is clear. The interval is determined by BTIPx. The
Real-Time Clock sets its RTCFG flag according to RTCTEVx but this does not request an
interrupt. A program can poll the flag to check whether an interval of time has elapsed and
must clear RTCFG in software.
Additional features of RTC:
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All ‘TC s o k i LPM
The RTC_B and RTC_C can be operates in LPM 3.5 due to RTC_B & RTC_C are access the LF crystal
directly.
RTC_B / RTC_C provide BCD conversion
RTC_A can be used as 32-bit counter (rather than calendar mode).
Counter mode generates an overflow interrupts.
Measurement in Capture Mode:
 The capture mode is used to take a time stamp of an event. (Time at which it occurs).
 The timer can be used in two opposite ways as mentioned.
1. In most cases the timer clock is either ACLK or SMCLK.
 In the first method to measure the length of a single pulse the both edges are
captured (start & end).
 The du atio of the pulse is easu ed ith u it of the ti e lo k s pe iod.
 The rising edges of the pulse are captured for a periodic signal (falling edge if
needed).
 For a good resolution of a signal the period of the clock should be less than the
duration.
2. The second method used to measure a signal with a higher frequency.
 The signal is captured the events with clock edges whose frequency known.
 The difference between the timer clock and captured value gives the frequency
rather than the period.
 The first method is much more common.
Example:
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Many speed sensors produce a given number of pulses per revolution of a shaft where capture
mode is used to measure the period between pulses.
In communication the capture mode is used to detect the time stamp of the start time of data
received.
The FLL can be emulated with capture mode to compare the frequencies of SMCLK and ACLK.
Measurement of Time: Press and Release of a Button
 For example the time between press and release of the button S2 is connected to port P1.1 active
low with pull-up resistor.
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The Timer_A runs fast in continuous mode to detect the switch bounce.
The period should be longer than the press of button is 0.5 s.
The ACLK is accurate when it comes from crystal but SMCLK is not unless a FLL is used.
Capture/compare channel 0 is configured to capture and interrupt request on both raising and
falling edge to release and press the button.
 The capture compare channel copies the value of TAR into TACCRn when input is detected.
 Timer_A avoids the delay occurs if another interrupt is being served when it want to be computed.
 Timer_A can be programmed by setting CCIS 1 bit in TACCTL0, which set up port 1 to generate
interrupt when S2 is pressed or released and copy the new state to TACCTL0.
Measurement of Time: Reaction Time
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The Ti e _A is used to easu e the ‘ea tio Ti e .
The time is displayed in milliseconds, so 1 KHz clock is sufficient.
The ACLK generates 4 KHz with divider 8.
The limitation is the slowest reaction time is just 2s, which is not a problem in all cases.
In FG4618 microcontroller
 The Interrupts are enabled for the start button S2, connected to P1.1.
 The timing button S1, connected to P1.0, is routed to capture input CCI0A of Timer_A.
 Capture/compare channel 0 is used for the captures because S1 provides the input CCI0A.
 Timer_A runs from ACLK with no division, giving a period of 2s
 To measure the reaction time the formula is :
Measurement of frequency: Comparison of SMCLK and ACLK
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The
easu e of f e ue
is to ou t the u
�=
e
les, N i a k o
i te al of ti e T.
N
�
If T =
s the N gi es the f e ue
i KHz
The count of number of cycles is requires an accurate reference provided by ACLK.
The channel is configured to capture the value of TAR, which requires an interrupt at raising edge
of ACLK.
The difference between the new and old value of TAR (N1-N2) gives number of cycles of the signal
in one cycle of ACLK
Thus the frequency measured is
f = (N2−N1) fACLK.
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Basic timer 1 is configured for a real-time interrupts every 0.5s for measurement.
Capture/compare channel 2 is used for the measurements because ACLK is connected to CCI2B. It is
configured for rising edges and synchronized captures.
The ISR for basic Timer 1 enables the interrupt on TACCR2 to start a new measurement. First it
clears the COV and CCIFG bits, which are set by previous capture events.
The value of captures is determined automatically without TACCR2 value.
The MSP430 returns to LPM0 until the next interrupt generated from Basic timer 1 .
Analog to Digital Converter: ADC 10:
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The ADC 10 in MSP430 implements a 10-bit SAR code, sample select control reference generator
and data transfer controller (DTC).
The DTC allows the ADC 10 samples to be converted and stored in the memory without CPU
intervention.
ADC 10 features:
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ADC 10 conversion rate is greater than 200 KSPS.
It is a monotonic 10-bit converter without any missing code.
Sampled and can be programmable.
Software Timer_A can initiate the conversion
Software selectable of internal or external reference voltage (1.5v or 2.5v)
MSP430 supports up to 8 input channels. (12 on MSP430F22XX family)
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It supports single channel, repeated-single channel, sequence and repeated sequence
conversion modes.
ADC core and reference voltages sources can be power down automatically.
The ADC block diagram as shown below:
Simplified block diagram of ADC 10/12:
10-Bit ADC Core:
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The ADC core converts an analog input to its 10-bit digital equivalent and stores in memory (ADC10
MEM register).
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The upper and lower voltage levels are defined as VR+ and VR- .
The output digital value (NADC) arrives when full scale value (03FFH) reached when input signal
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equal or greater than VR+ and zero when VR- .
The input channel and the reference voltage levels (VR+ & VR- a e k o
e o .
The o e sio fo ula usi g st aight i a fo at s o ple e t fo
NADC =
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�
as
o e sio – control
at is
��� − ��−
��+ −��−
The ADC10 has two control word register ADC10CTL0 and ADC10CTL1.
The core is enabled with ADC10 on bit.
This ADC10 control bit can be modified using ENC = 0.
ENC must be 1 before conversion.
Conversion clock selection:
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The ADC source clock is selected by ADC10SSELx bit (SMCLK, ACLK, MCLK and internal oscillator
ADCOSC).
ADC10 CLK remains active until the end of conversion
ADC10 inputs & multiplexer:
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There are 8-external and four internal signals are selected by multiplexer.
Analog port selection:
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ADC10AEx bits provide the disabling the ports.
o P2.3 ON: MSP43022XX configures analog input.
o B1S.3 #08, ADC10AE0; P2.3 ADC10 function enable.
 Direct Memory Access (DMA) Introduction:
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The DMA controller transfers data from one address to another, without CPU intervention, across
the entire address range. For example, the DMA controller can move data from the ADC conversion
memory to RAM.
Devices that contain a DMA controller may have up to eight DMA channels available. Therefore,
depending on the number of DMA channels available, some features described in this chapter are
not applicable to all devices. See the device-specific data sheet for number of channels supported.
Using the DMA controller can increase the throughput of peripheral modules. It can also reduce
system power consumption by allowing the CPU to remain in a low-power mode, without having to
awaken to move data to or from a peripheral.
DMA controller features include:
• Up to eight i depe de t t a sfe ha els
• Co figu a le DMA ha el p io ities
• ‘e ui es o l t o MCLK lo k
les pe t a sfe
• B te o o d a d i ed te a d o d t a sfe apa ilit
• Blo k sizes up to
tes o o ds
• Co figu a le t a sfe t igge sele tio s
• “ele ta le-edge or level-triggered transfer
• Fou add essi g odes
• “i gle, lo k, o u st-block transfer modes
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1.2 DMA Operation:
The DMA controller is configured with user software. The setup and operation of the DMA is
discussed in
the following sections.
 1.2.1 DMA Addressing Modes:
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The DMA controller has four addressing modes. The addressing mode for each DMA channel is
independently configurable. For example, channel 0 may transfer between two fixed addresses,
while
channel 1 transfers between two blocks of addresses. The addressing modes are shown in Figure 12.
The addressing modes are:
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• Fi ed add ess to fixed address
• Fi ed add ess to lo k of add esses
• Blo k of add esses to fi ed add ess
• Blo k of add esses to lo k of add esses
The addressing modes are configured with the DMASRCINCR and DMADSTINCR control bits. The
DMASRCINCR bits select if the source address is incremented, decremented, or unchanged after
each
transfer. The DMADSTINCR bits select if the destination address is incremented, decremented, or
unchanged after each transfer.
Transfers may be byte to byte, word to word, byte to word, or word to byte. When transferring
word to
byte, only the lower byte of the source-word transfers. When transferring byte to word, the upper
byte of
the destination-word is cleared when the transfer occurs.
 1.2.2 DMA Transfer Modes:
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The DMA controller has six transfer modes selected by the DMADT bits as listed in Table 1-1. Each
channel is individually configurable for its transfer mode. For example, channel 0 may be configured
in
single transfer mode, while channel 1 is configured for burst-block transfer mode, and channel 2
operates
in repeated block mode. The transfer mode is configured independently from the addressing mode.
Any
addressing mode can be used with any transfer mode.
Two types of data can be transferred selectable by the DMAxCTL DSTBYTE and SRCBYTE fields. The
source and/or destination location can be either byte or word data. It is also possible to transfer
byte to
byte, word to word, or any combination.
 1.2.2.1 Single Transfer:
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In single transfer mode, each byte/word transfer requires a separate trigger. The single transfer
state
diagram is shown in Figure 1-3.
The DMAxSZ register is used to define the number of transfers to be made. The DMADSTINCR and
DMASRCINCR bits select if the destination address and the source address are incremented or
decremented after each transfer. If DMAxSZ = 0, no transfers occur.
The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary
values of DMAxSA and DMAxDA are incremented or decremented after each transfer. The DMAxSZ
register is decremented after each transfer. When the DMAxSZ register decrements to zero, it is
reloaded
from its temporary register and the corresponding DMAIFG flag is set. When DMADT = {0}, the
DMAEN
bit is cleared automatically when DMAxSZ decrements to zero and must be set again for another
transfer
to occur.
In repeated single transfer mode, the DMA controller remains enabled with DMAEN = 1, and a
transfer
Occurs every time a trigger occurs.
 1.2.2.2 Block Transfer:
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In block transfer mode, a transfer of a complete block of data occurs after one trigger. When
DMADT = {1}
,the DMAEN bit is cleared after the completion of the block transfer and must be set again before
another
block transfer can be triggered. After a block transfer has been triggered, further trigger signals
occurring
during the block transfer are ignored. The block transfer state diagram is shown in Figure 1-4.
The DMAxSZ register is used to define the size of the block, and the DMADSTINCR and
DMASRCINCR
bits select if the destination address and the source address are incremented or decremented after
each
transfer of the block. If DMAxSZ = 0, no transfers occur.
The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary
values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block.
The
DMAxSZ register is decremented after each transfer of the block and shows the number of transfers
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remaining in the block. When the DMAxSZ register decrements to zero, it is reloaded from its
temporary
register and the corresponding DMAIFG flag is set.
During a block transfer, the CPU is halted until the complete block has been transferred. The block
transfer takes 2 × MCLK × DMAxSZ clock cycles to complete. CPU execution resumes with its
previous
state after the block transfer is complete.
In repeated block transfer mode, the DMAEN bit remains set after completion of the block transfer.
The
next trigger after the completion of a repeated block transfer triggers another block transfer.
 1.2.2.3 Burst-Block Transfer:
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In burst-block mode, transfers are block transfers with CPU activity interleaved. The CPU executes
two MCLK cycles after every four byte/word transfers of the block, resulting in 20% CPU execution
capacity. After the burst-block, CPU execution resumes at 100% capacity and the DMAEN bit is
cleared.
DMAEN must be set again before another burst-block transfer can be triggered. After a burst-block
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transfer has been triggered, further trigger signals occurring during the burst-block transfer are
ignored.
The burst-block transfer state diagram is shown in Figure 1-5.
The DMAxSZ register is used to define the size of the block, and the DMADSTINCR and
DMASRCINCR
bits select if the destination address and the source address are incremented or decremented after
each
transfer of the block. If DMAxSZ = 0, no transfers occur.
The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary
values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block.
The
DMAxSZ register is decremented after each transfer of the block and shows the number of transfers
remaining in the block. When the DMAxSZ register decrements to zero, it is reloaded from its
temporary
register and the corresponding DMAIFG flag is set.
In repeated burst-block mode, the DMAEN bit remains set after completion of the burst-block
transfer and
no further trigger signals are required to initiate another burst-block transfer. Another burst-block
transfer
begins immediately after completion of a burst-block transfer. In this case, the transfers must be
stopped
by clearing the DMAEN bit, or by an (non)maskable interrupt (NMI) when ENNMI is set. In repeated
burstblock
mode the CPU executes at 20% capacity continuously until the repeated burst-block transfer is
stopped.
1.2.5 Stopping DMA Transfers:
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There are two ways to stop DMA transfers in progress:
• A si gle, lo k, o u st-block transfer may be stopped with an NMI, if the ENNMI bit is set in
register
DMACTL1.
• A u st-block transfer may be stopped by clearing the DMAEN bit.
1.2.6 DMA Channel Priorities:
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The default DMA channel priorities are DMA0 through DMA7. If two or three triggers happen
simultaneously or are pending, the channel with the highest priority completes its transfer (single,
block, or
burst-block transfer) first, then the second priority channel, then the third priority channel.
Transfers in
progress are not halted if a higher-priority channel is triggered. The higher-priority channel waits
until the
transfer in progress completes before starting.
The DMA channel priorities are configurable with the ROUNDROBIN bit. When the ROUNDROBIN
bit is
set, the channel that completes a transfer becomes the lowest priority. The order of the priority of
the
channels always stays the same, DMA0-DMA1-DMA2, for example, for three channels. When the
ROUNDROBIN bit is cleared, the channel priority returns to the default priority.
 1.2.6.1 DMA Triggering:
 1.2.7 DMA Transfer Cycle Time:
 The DMA controller requires one or two MCLK clock cycles to synchronize before each single
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transfer or
complete block or burst-block transfer. Each byte/word transfer requires two MCLK cycles after
synchronization, and one cycle of wait time after the transfer. Because the DMA controller uses
MCLK, the
DMA cycle time is dependent on the MSP430 operating mode and clock system setup.
If the MCLK source is active but the CPU is off, the DMA controller uses the MCLK source for each
transfer, without reenabling the CPU. If the MCLK source is off, the DMA controller temporarily
restarts
MCLK, sourced with DCOCLK, for the single transfer or complete block or burst-block transfer. The
CPU
remains off and after the transfer completes, MCLK is turned off. The maximum DMA cycle time for
all
operating modes is shown in Table 1-3.
1.2.8 Using DMA With System Interrupts:
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DMA transfers are not interruptible by system interrupts. System interrupts remain pending until
the
completion of the transfer. NMIs can interrupt the DMA controller if the ENNMI bit is set.
System interrupt service routines are interrupted by DMA transfers. If an interrupt service routine
or other
routine must execute with no interruptions, the DMA controller should be disabled prior to
executing the
routine.
1.2.9 DMA Controller Interrupts:
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Each DMA channel has its own DMAIFG flag. Each DMAIFG flag is set in any mode when the
corresponding DMAxSZ register counts to zero. If the corresponding DMAIE and GIE bits are set, an
interrupt request is generated.
All DMAIFG flags are prioritized, with DMA0IFG being the highest, and combined to source a single
interrupt vector. The highest-priority enabled interrupt generates a number in the DMAIV register.
This
number can be evaluated or added to the program counter (PC) to automatically enter the
appropriate
software routine. Disabled DMA interrupts do not affect the DMAIV value.
Any access, read or write, of the DMAIV register automatically resets the highest pending interrupt
flag. If
another interrupt flag is set, another interrupt is immediately generated after servicing the initial
interrupt.
For example, assume that DMA0 has the highest priority. If the DMA0IFG and DMA2IFG flags are
set
when the interrupt service routine accesses the DMAIV register, DMA0IFG is reset automatically.
After the
RETI instruction of the interrupt service routine is executed, the DMA2IFG generates another
interrupt.
UNIT – IV
Serial Communication Basics:
Serial communication is the process of sending data one bit at a time, sequentially over a
communication channel or computer bus. This is in contrast to parallel communication, where several bits
are sent as a whole on a link with several parallel channels.
Serial Transfer
Sender
Receiver
Serial data can be transferred in two modes. They are
1. Asynchronous Data Transfer.
2. Synchronous Data Transfer.
1) Asynchronous Data Transfer:
Asynchronous serial data communication is widely used for character oriented transmissions.
→ In the Asynchronous method each character is placed between starts and stop bits. This is
called framing.
→ Asynchronous data transfers has a protocol, which is as follows:
i. The first bit is always the START bit followed by DATA bits, followed by STOP bit.
There may be a PARITY bit just before the STOP bit. PARITY bit is used for error
checking.
ii. The START bit is always low (0) while STOP bit is always high (1).
2) Synchronous Data Transfer:
Synchronous data transfer is when the data bits are synchronized with a clock pulse.
The concept of synchronous data transfers is as follows:
I. Data bit sampling is done with respect to clock pulses.
II.
Since, data is sampled depending up on clock pulses and since the clock sources are
very reliable. So there is much less error in synchronous.
Serial Communication Terminologies:
1. MSB/LSB: this stands for Most Significant Bit (or Least Significant Bit). Since data is transferred bitby-bit in serial communication, one needs to know which bit is sent out first: MSB or LSB.
2. Simplex Communication: In this mode of serial communication, data can only be transferred from
transmitter to receiver and not vice versa.
3. Half Duplex Communication: this means that data transmission can occur in only one direction at
a time, i.e. either from master to slave, or slave to master, but not both.
4. Full Duplex Communication: full duplex communication means that data can be transmitted from
the master to the slave, and from slave to the master as the same time!
Synchronous / Asynchronous Interfaces:
UART:
A universal asynchronous receiver/ transmitter (UART) is a computer hardware device for
asynchronous serial communication in which the data format and transmission speeds are configurable.
The UART acts as an intermediate between parallel and serial interfaces. On one end of UART is bus
of eight-or- so data line (& some control pins), on the other is two serial wires – RX and TX.
Fig: simplified UART interface: parallel on one end, serial on the other
UA‘T s do e ist as sta d-alo e IC s, ut the a e
oe o
o l fou d i side
i o o t olle s.
As the R and T in the acronym indicates UA‘T s a e espo si le fo oth se di g a d e ei i g se ial
data on the transmit side a UART must create the data packet appending sync and parity bits and send that
packet out the TX line with precise timing. On the receive end, the UART has to sample the RX line at rates
according to the expected baud rate, pick out the sync bits and spit out the data.
Data Framing:
Bit
Number
1
Start
bit
Start
2
3
4
5
6
7
8
9
10
5-9 data bits
D0
D1
D2
D3
D4
D5
11
12
Stop bits
D6
D7
D8
Stop
The start bit signals the receiver that a new character is coming. The next 5-9 bits, depending on the code
set employed represent the character. If a parity bit is used, it would be placed after all of the data bits.
The next one or two bits are always in the logic high condition and called stop bits. Then the signal received
at that character is completed.
USB:
Universal serial bus (USB) is a set of interface specifications for high speed wired communication
between electronics system peripherals and devices with or without pc/computer. The USB was originally
developed in 1995.
USB offers users simple connectivity. USB allows hot swapping. The hot swapping means the
devices can be plugged and unplugged without rebooting the computer or turning off the devices it means,
when plugged in everything configures automatically.
There are different versions of USB. They are
1.
2.
3.
4.
USB 1.0
USB 1.1
USB 2.0
USB 3.0
USB system is made up of a host, multiple numbers of USB ports and multiple peripheral devices
connected in a tiered-star topology.
The host is USB systems master and as such, controls and schedules al communications activities.
Peripherals, the devices controlled by USB are slaves responding to the commands from host.
Fig: The U“B tie ed sta topolog
USB devices are linked in series through hubs. There always exists one hub known as Root Hub, which is
built in to the host controller. The pipes are unidirectional. The hubs are bridges.
USB can support 4 data transfer types or transfer modes.
1.
2.
3.
4.
Control
Isochronous
Bulk
Interrupt
Control transfers exchange configuration, setup and command information between the device and
host. The host can also send commands or query parameters with control packets.
Isochronous transfer is used by time critical, streaming device such as speakers and video cameras. It is
time sensitive information so, within limitations, it has guaranteed access to the USB bus.
Bulk transfer is used by devices like printers & scanners, which receives data in one big packet.
Interrupt transfer is used by peripherals exchanging small amounts of data that need immediate
attention.
All USB data is sent serially. USB data transfer is essentially in the form of packets of data, sent back
and forth between the host and peripheral devices. Initially all packets are sent from the host, via the root
hub and possibly more hubs, to devices.
Ea h U“B data t a sfe o sists of a…
1. Token packet (Header defining what it expects to follow)
2. Optional Data Packet (Containing the payload)
3. Status Packet (Used to acknowledge transactions and to provide a means of error correction).
Serial Peripheral Interface (SPI) :
Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between
microcontrollers and small peripherals such as shift registers, sensors and SD cards. It uses separate clock
and data lines along with select line.
SPI is a hardware / firmware communications protocol developed by Motorola. It is sometimes
alled as fou i e se ial us.
The Serial Peripheral Interface is a simple 4-wire serial communications interface. It operates at full
duplex.
Data and Control lines of the SPI are:
1. Master Out Slave In (MOSI) – MOSI signal is generated by Master, recipient is the slave.
2. Master in slave out (MISO) – slaves generate MISO signals and recipient is the master.
3. Serial clock (SCLK or SCK) – SCLK signal is generated by the master to synchronize data transfers
between the master and slave.
4. Slave select (SS) – It is an active low signal.
I2C :
I2C is a synchronous interface. It is a standard bidirectional interface that uses a controller, known
as the master to communicate with slave devices. A slave may not transmit data unless it has been
addressed by the master.

The physical I2C interface consists of the serial clock (SCL) and serial Data (SDA) lines. Both SDA
and SCL lines must be connected to vcc through a pull up resistor. The size of pull up resistor is
determined by the amount of capacitance on the I2C lines. Data transfer may be initiated only
when the bus is idle. A bus is idle if both SCL and SDA lines are high after a STOP condition.
The general procedure for a master to access a slave device is the following:
1. Suppose a master wants to send data to slave :
 Master – transmitter sends a START condition and address the slave – receiver.
 Master – transmitter sends data to slave – receiver.
 Master – transmitter terminates the transfer with a STOP condition.
2. If a master wants to receive / read data from a slave:
 Master – receiver sends a START condition and Addresses the slave – transmitter.
 Master – receiver sends the requested register to read to slave – transmitter.
 Master – receiver receives data from the slave – transmitter.
 Master – receiver terminates the transfer with a STOP condition.
I2C communication with the device is initiated by master sending a
START condition and terminated by master sending a stop condition. A high – to – low transition on the
SDA line which the SCL is high defines a STOP condition.
START and STOP Conditions:
UART protocol:
UART represents Universal Asynchronous receiver and transmitter.
Protocol Description:
a. Transmission: The UART transmitter section includes a transmitter hold register (THR) and a
transmitter shift register (TSR). When the UART is in the FIFO mode. THR is 16- byte FIFO.
Transmitter section control is a function of the UART line control register (LCR). Based on the
settings chosen in the LCR, UART transmitter sends the following to the receiving device.
 1 START bit
 5,6,7 or 8 data bits
 1 parity bit (optional)
 1,1.5 or 2 stop bits
b. Reception: The UART receiver section includes a receiver shift register(RSR) and a receiver
buffer register (RBR). When the UART is in FIFO mode, RBR is 16 – byte FIFO. Receiver section
control is function of the UART line control register (LCR). Based on the settings chosen in the LCR,
the UART receiver accepts the following from the transmitting device.
 1 START bit
 5,6,7 or 8 data bits
 1 parity bit (optional)
 1 STOP bit (any other STOP bits transferred with the above data are not detected).
c. Data Format:
The UART transmits in the following format.
1 START bit + data bits (5, 6, 7, 8) + 1 parity bit (optional) + STOP bit (1, 1.5, 2)
The UART receives in the following format:
1 START BIT + data bits (5,6,7,8) + 1 parity bit (optional) + 1 STOP bit
I2c Protocol: I2c represents Inter – Integrated circuit I2c is a multi – master – protocol that uses 2 signal
lines. The two I2 sig als a e alled se ial data “DA a d se ial lo k “CL .
Virtually any number of slaves and any number of masters can be connected onto these 2 signal lines and
communication between each other using a protocol that defines :
 7 bits slave addresses: each device connected to the bus has got a unique address.
 Data divided into 8 – bit bytes.
 A few control bits for controlling the communication start, end, direction and for an
acknowledgment mechanism.
The data rate has to be chosen between 100 kbps, 400 kbps and 3.4 kbps respectively called
standard mode, fast mode and high speed mode.
Physically, the I2c bus consists of 2 active wires SDA and SCL and a ground connection as
shown in above fig. the active wires are both bi-directional.
 First the master will issue a START condition.
 Then the master sends the ADDRESS of the device it wants to access, along with an
indication whether the access is a Read or Write operation.
 Ha i g e ei ed the add ess, all IC s ill o pa e ith thei o add ess. If it does t
match, they simply wait until the bus is released by stop condition. If address matches, it will
produce a response called Acknowledge signal.
 Once the master receives the acknowledgement, it can start transmitting or receiving data.
 When all data is sent, the master will issue the STOP condition.
 When a master wants to receive data from a slave, it proceeds the same way, but sets
RD/nWR bit at a logical one. Once the slave has acknowledged the address, it starts sending
the requested data, byte by byte.
SPI PROTOCOL:
SPI refers to serial peripheral interface. It is a synchronous serial communication
interface specification used for short distance communication.
SPI is a protocol on a 4 signal lines as shown in the following figure.
Fig: SPI Master connected to a single slave
Fig: SPI master connected to multiple slaves
 A clock signal named SCLK, sent from the bus master to all slaves all the SPI signals are synchronous
to this clock signal.
 A slave select signal for each slave, ss used to select the slave the master communicates with.
 A data line from the master to slaves, named MOSI (Master out - Slave In).
 A data line from the slaves to master, named MISO (Master in - Slave out).
SPI is a single master communication protocol.
Fig: A simple SPI Communication
Data bits on MOSI and MISO toggle on the SCLK falling edge and are sampled on the SCLK rising edge.
The SPI mode defines which SCLK edge is used for Toggling data and which SCLK dge is used for sampling
data.
Four communication modes are available (MODE 0,1,2,3) – that basically define the SCLK edge on
Which MOSI line toggles, the SCLK edge on which the master samples the MISO line and SCLK signal steady
level. Each mode is formally defined with a pair of parameters called clock polarity (CPOL) and clock phase
(CPHA).
Fig: SPI Modes
A master / slave pair must use the same set of parameters – SCLK frequency, CPOL & CPHA for a
communication to be possible.
Implementing and Programming UART Interface Using MSP430:
In MSP430 serial communication is handled by an on chip peripheral called USCI (Universal Serial
Communication Interface). It has two USCI modules names as USCI_A0 and USCI_B0 for handling multiple
communication formats. USCI_A0 can be configured to handle IrDA, SPI and UART while USCI_B0 can
handle SPI and I2C.
Here we are configure USCI_A0 in MSP430G2553 to handle asynchronous serial communication or
commonly known as UART mode. The UART mode uses two pins to transmit (UCA0TXD) and receive data
(UCA0RXD).
In this example we are configure the MSP430 UART to transmit and receive at 9600bps with 8 data bits, no
Parity and 1 Stop bit .In the above figure you can see that the USCI can source clock from either SMCLK or
ACLK to generate BRCLK which is used to generate the required timings.UC0CLK is external clock sourced
from outside through MSP430 pins.
To configure the DCO to generate 1MHz and use SMCLK as UART clock & to generate accurate 1MHz clock,
calibration constants into the Basic clock system register and DCO control registers as follows:
if (CALBC1_1MHZ == 0xFF) // If calibration constant erased
{
while(1);
// do not load, trap CPU!!
}
DCOCTL = 0;
BCSCTL1 = CALBC1_1MHZ;
DCOCTL = CALDCO_1MHZ;
// Select lowest DCOx and MODx settings
// Set range
// Set DCO step + modulation
CALBC1_1MHZ is a constant defined in the header file.
Registers Required for UART:
The registers and bits used for configuring the UART are:
1) UCAxCTL0 (USCI_Ax Control register0) :This register controls the settings for Parity selection, direction
of data transmission(LSB or MSB first),character length, number of stop bits, modes of serial transmission.
The important bits are
UCPEN
Used for enabling or disabling parity
UCPAR
Used for selecting between EVEN or ODD parity
UCMSB
Controls the direction of receive and transmit register(here LSB first)
UC7BIT
Selects the character length 7/8 bit(we are using 8 bit so 0)
UCSPB
Number of stop bits (here 1 so UCSPB = 0)
UCMODEx
2 bits used to select the asynchronous mode when UCSYNC = 0
UCSYNC
Selecting between asynchronous(UART) and synchronous modes(SPI)
2) UCAxCTL1--The two important bits contained in this register are
UCSSELx
These bits are used to select the clock source to the USCI module.
UCSWRST
This bit is used to put the USCI module in reset state.
3) UCAxSTAT --The two important bits contained in this register are
UCLISTEN
This bit is used to select the internal loop back mode.
UCBUSY
Indicates if a transmit or receive operation is in progress.
4) UCAxBR0and UCAxBR1--These are two 8 bit registers which are used to set the clock pre scalar value for
the Baud rate generator.
5) UCAxTXBUF-- 8 bit data register for holding the byte to be transmitted by the MSP430 UART.
6) UCAxRXBUF--8 bit data register that stores the received byte.
Interrupts of MSP430 UART are:
IE2:
UCA0TXIE
Used to enable/disable the transmit interrupt.
UCA0RXIE
Used to enable/disable the receive interrupt.
IFG2:
UCA0TXIFG
USCI_A0 transmit interrupt flag is set when UCA0TXBUF is empty
UCA0RXIFG
USCI_A0 receive interrupt flag is set when UCA0RXBUF have received a
complete character.
The code given below will configure the UART and transmit an ASCII character 'A' .The UART is configured
in loop back mode so 'A' is received back and is received back and is stored in UCA0RXBUF.LED connected
to P1.0 is lighted when 'A' is transmitted and LED connected to P1.6 is lighted when 'A' is received back.
#include "msp430g2553.h"
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop the Watch dog
//------------------- Configure the Clocks -------------------//
if (CALBC1_1MHZ==0xFF)
// If calibration constant erased
{
while(1);
// do not load, trap CPU!!
}
DCOCTL = 0;
BCSCTL1 = CALBC1_1MHZ;
DCOCTL = CALDCO_1MHZ;
// Select lowest DCOx and MODx settings
// Set range
// Set DCO step + modulation
//---------------- Configuring the LED's ----------------------//
P1DIR
P1OUT
|= BIT0 + BIT6;
&= ~BIT0 + BIT6;
// P1.0 and P1.6 output
// P1.0 and P1.6 = 0
//--------- Setting the UART function for P1.1 & P1.2 --------//
P1SEL |=
P1SEL2 |=
BIT1 + BIT2;
BIT1 + BIT2;
// P1.1 UCA0RXD input
// P1.2 UCA0TXD output
//------------ Configuring the UART(USCI_A0) ----------------//
UCA0CTL1 |= UCSSEL_2 + UCSWRST;
UCA0BR0
= 104;
UCA0BR1
= 0;
UCA0MCTL = UCBRS_1;
UCA0STAT |= UCLISTEN;
UCA0CTL1 &= ~UCSWRST;
//
//
//
//
//
//
USCI Clock = SMCLK,USCI_A0 disabled
104 From datasheet table-selects baud rate =9600,clk = SMCLK
Modulation value = 1 from datasheet
loop back mode enabled
Clear UCSWRST to enable USCI_A0
//---------------- Enabling the interrupts ------------------//
}
IE2 |= UCA0TXIE;
IE2 |= UCA0RXIE;
_BIS_SR(GIE);
// Enable the Transmit interrupt
// Enable the Receive interrupt
// Enable the global interrupt
UCA0TXBUF = 'A';
// Transmit a byte
_BIS_SR(LPM0_bits + GIE);
// Going to LPM0
//-----------------------------------------------------------------------//
//
Transmit and Receive interrupts
//
//-----------------------------------------------------------------------//
#pragma vector = USCIAB0TX_VECTOR
__interrupt void Transmit Interrupt(void)
{
P1OUT ^= BIT0;//light up P1.0 Led on Tx
}
#pragma vector = USCIAB0RX_VECTOR
__interrupt void Receive Interrupt (void)
{
P1OUT ^= BIT6;
// light up P1.6 LED on RX
IFG2 &= ~UCA0RXIFG; // Clear RX flag
}
After the WDT is stopped .The DCO is configured to produce clock at 1MHz using the calibration constants.
The ports P1.0 and P1.6 are configured as outputs to light up the respective LED' during transmission and
reception.
Implementing and Programming SPI Interface Using MSP430:
SPI is one of the most common interfaces in embedded systems and it is one of the most utilized in
MSP430. Although it requires more pins than UART, its external clock often enables very fast transfers that
are more reliable because both ends are synchronized. The MSP430 supports SPI in various modules.
Physical Interface:
A SPI connection between a master & slave is shown in below:
Configuring the MSP430 For SPI:
Configuring MSP430g2553 pins for SPI
#include <msp430.h>
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P1OUT |= BIT5;
P1DIR |= BIT5;
P1SEL =BIT1|BIT2|BIT4;
P2SEL =BIT1|BIT2|BIT4;
UCA0CTL1 = UCSWRST;
UCAOCTL1 |= UCCKPH+UCMSB+UCMST+UCSYNC; //3-PIN,8 bit SPI Master
UCAOCTL1 |= UCSSEL_2; // /2
UCA0BR0 = 0;
UCA0MCTL = 0; // No modulation
UCA0CTL1 &amp;amp;= ~UCSWRST; // **Initialize USCI state machine**
The MSP430G2553 has 2 SPI interfaces, mapped with the following pins:
UCAO
→ P1.1 - UCAOSOMI
→ P1.2 - UCAOSOM0
→ P1.4 – UCAOCLK
UCBO
→ P1.6 – UCBOSOMI
→ P1.7 – UCBOSOMI
→ P1.8 – UCBOCLK
Implementing and Programming SPI Interface using MSP430:
Both modules USCI_A and USCI_B can operate SPI, although USCI_A is nominally for asynchronous
operation. They work in exactly the same way and have the same set of registers, except that the interrupt
flags and enabling bits share the same register for the A and B channels of a USCI.
Fig: Simplified Block Diagram of the USCI_B0 Module in SPI Master Mode
The module should be put into synchronous mode with UCSYNC A transfer begins when a value is written
to the transmit buffer TXBUF. The clock is started in a master, while a slave waits for a clock signal on its
CLK input, and the flag UCBUSY is raised to show that the module is busy. No further action is required for
the byte to be sent and the corresponding byte received. Flags show the state of the transmit and receive
buffers.
Transmit interrupt flag, TXIFG: Raised when the buffer TXBUF is ready to accept another byte.
Receive interrupt flag, RXIFG: Raised when a new value has been received and moved from the shift
register to RXBUF. This indicates that a transaction is complete.
Implementing and Programming I2C Interface Using MSP430:
The universal serial communication Interface (USCI) module support multiple serial communication modes.
USCI_Bx modules support
→ I2C Mode
→ SPI Mode
Operation:
The I2C Mode supports any slave or master I2C compatible device. The following figure shows an example
of I2C bus.
Each I2C device is recognized by a unique address and can operate as either a transmitter or a receiver. I 2C
data is communicated using the serial data (SDA) pin and the serial clock (SCL) pin. Both SDA and SCL are
bidirectional and must be connected to a positive supply voltage using a pull-up resistor.
I2C mode supports 7-bit and 10-bit addressing modes.
7-Bit Addressing: In the 7-bit addressing format, the first byte is the 7-bit slave address and R/W bit. The
ACK bit is sent from the receiver after each byte.
10-Bit Addressing: In the 10- it add essi g ode, the fi st te is ade up of
plus the t o M“B s
of the 10-bit slave address and R/W bit. The ACK bit is sent from the receiver after each byte. The next byte
is the remaining eight bits of the 10-bit slave address followed by ACK bit and 8-bit data.
USCI_B I2C Mode Register:
UCBxCTL0 Register:
USCI_Bx Control Register 0
UCBxCTL1 Register:
USCI_Bx Control Register 1
UCBxBR0 Register:
USCI_Bx Baud Rate Control Register 0
UCBxBR1 Register:
USCI_Bx Baud Rate Control Register 1
UCBxSTAT Register:
USCI_Bx Status Register
UCBxRXBUF Register:
USCI_Bx Status Register
UCBxRXBUF Register:
USCI_Bx Receiver Buffer Register
UCBxTXBUF Register:
USCI_Bx Transmit Buffer Register
UCBxI2COA Register:
USCIBxI2C own Address Register
USCIBxI2CSA Register:
USCIBxI2C Slave Address Register
UCBxIE Register:
USCI_BX I2C Interrupt Enable Register
Interfacing External Devices:
Many members of the MSP430 family have integrated A/D converters (ADCs), but in some applications the
required analog conversion function is remote, optional, or perhaps an afterthought. In these types of
applications, using external ADCs such as the low-cost, easy to use TLC549 and TLV1549 are options. The
TLC549 interfaces serially with the MSP430F1121 using three I/O pins with no external components.
Operation:
Using three digital I/O pins, the MSP430F1121 drives the TLC549 A/D conversion using a synchronous serial
interface. In this application report, MSP430 I/O pins P2.0 and P2.1 are configured as outputs using the P2
direction register (P2DIR) and set/reset using the P2 output register (P2OUT). Pin P2.0 interfaces with the
TLC549 chip select (CS) pin P2.1 with the TLC549 input-output clock (I/O CLK).
When CS is high, DO is in a high-impedance state and I/O CLK inactive. To begin the conversion, the
MSP430 brings CS low. To drive a complete conversion, the MSP430 generates a total of eight clock pulses
on P2.1 which are applied to the TLC549 I/O CLK. After CS has been brought low, the most significant bit
(MSB) from the previous conversion appears on DO. The MSP430 reads the conversion data on DO on pin
P2.3 and serially shifts the data into a register ADCDATA (R11). The falling edge of the fourth clock begins
the sample function of the analog signal present at the analog terminal of the TLC549. Three more clock
pulses are applied to I/O CLK shifting out the least three most significant bits from the previous conversion.
The falling edge of the final (eighth) clock pulse terminates the TLC549 sample function and the hold and
conversion cycle begins.
Case study:
MSP430 based Embedded system application using the interface protocols for communication with
e te al de i es. A lo po e atte less i eless te pe atu e a d hu idit se so ith passi e lo
f e ue
‘FID .
The implementation is done using the SHT21 relative humidity & temperature (RH & T) sensor, an
MSP430f2274 microcontroller, and the TMS37157 (PaLFI) low frequency from the TI. The complete power
for operating the wireless sensor and the MSP430f2274 is derived from the RF field of a low frequency
reader module.
- This page is under
construction-
- This page is under
construction-
UNIT-V
1. INTERNET OF THINGS (IOT):

Internet of things (IOT) is a proposed development of internet in which everyday objects have
network connectivity, allowing them to send and receive data.
The concept of IOT has evolved from the convergence of wireless technologies, MicroElectromechanical systems (MEMS), micro services and internet.
The word internet of things (IOT) has two main parts:
1. Internet being the backbone of connectivity.
2. Things being objects or devices.
It is nothing but an embedded system device that helps in sensing and collecting the data and sending it
into the internet.




It provides unique address to interrelated computing devices and does not require human-human
or human-computer interaction during transfer of data over a network.
When devices can sense and communicate via the internet, they can go beyond local embedded
processing to access and take advantage of remote super-computing nodes. This allows a device to
run more sophisticated analysis and respond to local needs quickly.
The practical applications of IOT technology can be found in many industries today, including
precision agriculture, building management, health care, energy and transportation.
The major problem with IOT is that it triggers questions around the privacy and supplying power to
this new proliferation of IOT devices and their network connections can be expensive and logically
difficult.
IOT ARCHITECTURE:IOT needs an open architecture to maximize interoperability among heterogeneous systems
and distributed resources including provides and consumers of information and services, whether they be
human beings, software, smart objects or devices.
European Union projects of SENSEI and Internet of things-Architecture (IOT-A) have been
addressing the challenges particularly from wireless sensor network (WSN) perspective and have been very
successful in defining the architecture. It consists of 3 layers.
Fig: Architecture of IOT
1. Perception Layer:Perception layer in an IOT can be divided into perception components layer perception network
layer and perception coordination layer.
1. The perception component layer can be abstracted as sensing components. Sensing components
include RFID, barcodes, sensors etc and actuator components include value, switch, relay etc.
Sensing components and actuator components help in realizing signal acquisition and control functions.
2. Perception network layer includes various buses such as the control area network (CAN) bus,
RS-485 bus or wireless networks such as Wireless Sensor Network (WSN), Bluetooth, Wi-Fi etc. It
realizes communication connection between perception components or between perception
components and IOT gateway.
3. The perception coordination layer is responsible for collecting data from sensing components
controlling actuator components to perform some action, coordinating each component to work
orderly, and realize unity management for perception components.
2. Network Layer:The network layer is responsible for delivering the sensor data from source to destination across
multiple links. IP (Internet Protocol) is the network layer protocol of the internet because it provides
unique IP address to its devices, the routing of data is done through the network. These devices carry IP
packets from one device to another device.
3. Application Layer:The application layer governs the data flow and is responsible for data formatting. The importance of
this layer fo the IOT is that it has the a ilit to p o ide high ualit s a t se i es to eet usto e s
needs.
2. Adding Wi-Fi capability to Microcontroller:Interfacing a Wi-Fi/LAN and developing web server for a microcontroller is advanced part of
embedded systems.
The CC3100device can connect to any 8-16 bit or 32 bit MCU (Micro Controller Unit) over SPI or UART
interface. The device driver minimizes the host memory footprint requirements requiring less than 7KB of
code memory and 700KB of RAM memory for a TCP client application.
The CC
de i e is the i dust s fi st Wi-Fi certified chip used in the windows network solution. It is a
part of new sample link Wi-Fi family that dramatically simplifies the implementation of internet
connectivity.


With built-in security protocols, the CC3100 solution provides a robust and simple security
experience.
CC3100 device is a complete platform solution including various tools and software, sample
applications. It is available in an easy to layout QFN package.
The Wi-Fi network processor subsystem features a Wi-Fi Internet on a chip and contains an additional
dedicated ARM MCU that completely offloads the host MCU. This subsystem includes an 802.11 b/g/n
radio, baseband and MAC with powerful crypto engine for fast, secure internet connections with 256-bit
encryption. The CC3100 device supports station access point, and Wi-Fi direct modules. The device also
supports WPAZ personal and enterprise security and WPS 2.0. This subsystem includes embedded TCP/IP
and TLS/SSL stacks, HTTP server, and multiple internet protocols.
The power management subsystems includes integrated DC-DC converter supporting a wide range of
supply voltages. This subsystem enables low-power consumption modes such as the hibernate with RTC
mode requiring about 4µA of current.
Features:




CC3100 Simple link Wi-Fi consists of Wi-Fi network processor and power management subsystems.
Wi-Fi certified chip.
Wi-Fi network processor subsystem
o Featuring Wi-Fi internet-on-a-chip.
o Dedicated ARM MCU completely offloads Wi-Fi and internet protocols from the external
microcontroller.
Clock Source
o 40.0 MHz crystal with internal oscillator.
o 32.768 KHz crystal or external RTC clock.
Package and Operating Temperature
o 0.5mm pitch, 64pin, 9mm x 9mm QFN.
o Ambient temperature range: -400C to 850 C.
3. EMBEDDED WI-FI:Wi-Fi is a technology has become wide spread in the consumer market. Such maturity ensures that
companies in the embedded market can jump on board with a little risk. Typically, due to the complexity of
designing and deploying RF Applications, the embedded market has struggled implementing wireless
technologies and Wi-Fi is no different.
Making it easy to embedded Wi-Fi into small, low cost and resource constrained devices is the task at
hand for those supplying Wi-Fi solutions for embedded devices. There are many number of decision points
in the process.
Wi-Fi as an M2M Technology :Machine-to-machine (M2M) communication has been mostly associated with cellular connectivity.
In a M2M market study, there are many discussions on cellular modules that are embedded inside devices.
However, M2M is much broader and encompasses many wired and wireless communication technologies
such as Ethernet, Zigbee, Wi-Fi, cellular and more.
Wireless technology usually implies portable or mobile applications. If something is on the more, it
a t e tied do
ith i es. Ha i g no wires also implies not having to run new wires to stationary
applications, which in turn means stationary installations become easier and less costly to setup and
maintain.
Wi-Fi is exactly the LAN over the air. Wired Ethernet applications can be converted to Wi-Fi fairly
easily, thereby reducing the installation cot of new Ethernet wires.
SoC Vs Module:Choosing a module solution over a soc solution reduces the risk that the Wi-Fi base band chip will
become unavailable, at least as long as the module manufacturer stays with the same module footprint
when moving from one Wi-Fi standard to the next.
Soc solution requires drivers, which are actually available from manufactures of the baseband chips for
Linux or Windows.
Wi-Fi/IP Controller:A communication solution does not end with just Wi-Fi part. The use of a dedicated Wi-Fi/IP
controller solution provides the immediate, cost effective and highly secure solution. It allow designers to
focus on core competencies while offloading all communications and securing tasks to an external field
proven controller.
The Wi-Fi/IP controller first serves as a controller for the Wi-Fi baseband chip. It contains the
necessary drivers, stacks and application software to operate the Wi-Fi chip in all its modes of operation
working with Wi-Fi becomes seamless to the host CPU.
The Wi-Fi/IP controllers also serves as hardware Fi e all-on-a- hip, shieldi g the appli atio f o
malicious attacks originating from the internet, similar to the way a firewall resides at the edge of a
network to protect the network from the internet.
The controller also contains TCP/IP stack and protocols such as HTTP, FTP etc so CPU need only send
commands to the controller in order to involve these high level protocols SSL3 is also implemented by the
Wi-Fi/IP controller, encrypting the data to form device from end-to-end.
Management is the key component of deploying devices, so the Wi-Fi/IP controller contains secure
built-in web servers that can manage the operation of the device remotely over the network using a
standard browser.
4. User API for wireless and Networking Applications:An application programming interface (API) is a set of functions and procedures that allow the
creation of applications which access the features or a data of an operating system, application or other
service.


An API specifies how software components should interact and are used when programming
graphical user interface (GUI).
A good API makes it easier to develop a program by providing all the building blocks. A programmer
then puts the blocks together.
Types of API’s:The e a e a diffe e t t pes of API s fo ope ati g s ste s, appli atio s o
example, has many API sets that are used by system hardware and applications.
e sites. Wi do s fo
Most operating environments such as Ms-Wi do s, p o ide API s allo ing programmers to write
appli atio s o siste t ith the ope ati g e i o e t. Toda , API s a e also spe ified
e sites fo
e a ple, A azo o eBa API s allo de elope s to use the e isti g etail i f ast u tu e to eate
specialized web stores. Third pa t soft a e de elope s also use e API s to eate soft a e solutio s fo
end users.
Popular API examples:1. Google Maps API:- It lets developers embed Google maps on WebPages using a JavaScript or flash
interface the Google map API is designed to work on mobile devices and desktop browsers.
2. Youtube API:-
It let developers integrate YouTube videos and functionally into websites or
applications. YouTube API include the YouTube analytics API, YouTube data API, YouTube live streaming
API, YouTube pla e API s a d othe s.
3. Flicker API: - It is used by developers to access the flick photo sharing community data. The flicker API
consists of a set of callable methods and some API end points.
4. Twitter API: - T itte offe s t o API s. The est API allows developers to access core twitter data and
the search API provides methods for developers to interact with twitter search and trends data.
5. Amazon product advertising API: - It gives developers access to Amazon s p odu t sele tio a d
discovery functionality to advertise Amazon products to monetize a website.
5. Creating an IoT connected sensor using MQTT:
MQTT (Message Queuing Telemetry Transport ) is an ISO standard publish – su s i e ased light
weight messaging protocol for use on top of the TCP/IN protocol. It is designed for connections with
e ote lo atio s he e a s all ode foot p i t is e ui ed o the et o k a d idth is li ited. It is a
good fit for embedded Wi-Fi solutions because it is a light weight protocol.
With MQTT there are 3 – components
1. Publisher
2. Broker
3. Subscriber
The protocol uses publish/subscribe architecture in contrast to HTTP with its request/response
paradigm. Publish/subscribe is event-driven and enables messages to be pushed to clients. The
central communication point is the MQTT broker. It is in charge of dispatching all messages
between the senders and the rightful receivers. Each client that publishes a message to the broker
includes a topic into the message. The topic is routing the information for the broker. Each client
that wants to receive messages subscribes to a certain topic and the brokers deliver all messages
ith the at hi g topi to lie t. The efo e the lie ts do t ha e to k o ea h othe , the o l
communicate over the topic. This architecture enables highly scalable solutions without
dependencies between the data producers and the data consumers.
The difference to HTTP is that a lie t does t ha e to pull the i fo atio it eeds, ut the oke
pushes the information to the clients in the case there is something new. Therefore, each MQTT client has
a permanently open TCP connection to the broker. If this connection is interrupted by any circumstances,
the MQTT broker can buffer all messages and send them to the client when it is back online.
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