TVP5154 - Texas Instruments

TVP5154 - Texas Instruments
www.ti.com
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
1 Introduction
1.1 Features
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Four Separate Video Decoder Channels With
Features for Each Channel:
– Accept NTSC (M, 4.43), PAL (B, D, G, H, I,
M, N), and SECAM (B, D, G, K, K1, L) Video
Data
– Support ITU-R BT.601 Standard Sampling
– High-Speed 9-Bit Analog-to-Digital
Converter (ADC)
– Two Composite Inputs or One S-video Input
(for Each Channel)
– Fully Differential CMOS Analog
Preprocessing Channels With Clamping
and Automatic Gain Control (AGC) for Best
Signal to Noise (SNR) Performance
– Brightness, Contrast, Saturation, Hue, and
Sharpness Control Through Inter-Integrated
Circuit (I2C)
– Complementary 4-Line (3-H Delay) Adaptive
Comb Filters for Both Cross-Luminance
and Cross-Chrominance Noise Reduction
– Patented Architecture for Locking to Weak,
Noisy, or Unstable Signals
Four Independent Polymorphic Scalers
Single or Concurrent Scaled and Unscaled
Outputs Via Dual Clocking Data, Interleaved
54-MHz Data or Single 27-MHz Clock
Scaled/Unscaled Image Toggle Mode Gives
Variable Field Rate for Both Scaled and
Unscaled Video
Low Power Consumption: 700 mW Typical
128-Pin Thin Quad Flat Pack (TQFP) Package
Single 14.31818-MHz Crystal for All Standards
and All Channels
1.2
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Internal Phase-Locked Loop (PLL) for
Line-Locked Clock (Separate for Each
Channel) and Sampling
Sub-Carrier Genlock Output for Synchronizing
Color Sub-Carrier of External Encoder
Standard Programmable Video Output Format
– ITU-R BT.656, 8-Bit 4:2:2 With Embedded
Syncs
– 8-Bit 4:2:2 With Discrete Syncs
Advanced Programmable Video Output
Formats
– 2× Over-Sampled Raw Vertical Blanking
Interval (VBI) Data During Active Video
– Sliced VBI Data During Horizontal Blanking
or Active Video
VBI Modes Supported:
– Teletext (NABTS, WST)
– Closed-Caption Decode With FIFO, and
Extended Data Services (EDS)
– Wide Screen Signaling (WSS), Video
Program System (VPS), Copy Generation
Management System (CGMS), Vertical
Interval Time Code (VITC)
– Gemstar 1×/2× Electronic Program Guide
Compatible Mode
– Custom Configuration Mode Allows User to
Program the Slice Engine for Unique VBI
Data Signals
Improved Fast Lock Mode Can Be Used When
Input Video Standard Is Known and Signals on
Switching Channels Are Clean
Four Possible I2C Addresses Allowing 16
Decoder Channels on a Single I2C Bus
Applications
The following is a partial list of suggested applications:
– Security Camera Systems
– Large Format Video Wall Displays
– Games Systems
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2006, Texas Instruments Incorporated
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
www.ti.com
SLES163A – MARCH 2006 – REVISED JULY 2006
1.3 Description
The TVP5154 device is a 4-channel, low-power, NTSC/PAL/SECAM video decoder. Available in a
space-saving 128-pin thin quad flat pack (TQFP) package, each channel of the TVP5154 decoder
converts NTSC, PAL, or SECAM video signals to 8-bit ITU-R BT.656 format. Discrete syncs are also
available. All four channels of the TVP5154 are independently controllable. The decoders share one
crystal for all channels and for all supported standards. The TVP5154 can be programmed using a single
inter-integrated circuit (I2C) serial interface. The decoder uses a 1.8-V supply for its analog and digital
supplies, and a 3.3-V supply for its I/O. The optimized architecture of the TVP5154 decoder allows for low
power consumption. The decoder consumes less than 720 mW of power in typical operation.
Each channel of the TVP5154 is an independent video decoder with a programmable polymorphic scaler.
Each channel converts baseband analog video into digital YCbCr 4:2:2 component video, which can then
be scaled down to any resolution to 1/256 vertical and 15-bit horizontal in 2-pixel decrements. Composite
and S-video inputs are supported. Each channel includes one 9-bit analog-to-digital converter (ADC) with
2× sampling. Sampling is ITU-R BT.601 (27.0) MHz, generated from a single 14.31818-MHz crystal or
oscillator input) and is line locked. The output formats can be 8-bit 4:2:2 with discrete syncs or 8-bit ITU-R
BT.656 with embedded synchronization.
The TVP5154 utilizes Texas Instruments patented technology for locking to weak, noisy, or unstable
signals. A real-time control (RTC) output is generated for each channel for synchronizing downstream
video encoders.
Complementary 4-line adaptive comb filtering is available per channel for both the luma and chroma data
paths to reduce both cross-luma and cross-chroma artifacts. A chroma trap filter also is available.
An improved fast lock mode can be used when the input video standard is known and the signals on the
switching channels are clean. Note, switching from snow and/or noisy channels to good channels takes
longer. In fast lock mode, video lock is achieved in three fields or less.
Video characteristics, including hue, contrast, brightness, saturation, and sharpness, may be
independently programmed for each channel using the industry standard I2C serial interface. The
TVP5154 generates synchronization, blanking, lock, and clock signals in addition to digital video outputs
for each channel. The TVP5154 includes methods for advanced vertical blanking interval (VBI) data
retrieval. The VBI data processor slices, parses, and performs error checking on teletext, closed caption,
and other data in several formats.
I2C commands can be sent to one or more decoder cores simultaneously, reducing the amount of I2C
activity necessary to configure each core. A register controls which decoder core receives I2C commands,
and can be configured such that all four decoders receive commands at the same time.
The main blocks for each of the channels of the TVP5154 decoder include:
• Robust sync detector
• ADC with analog processor
• Y/C separation using 4-line adaptive comb filter
• Independent, concurrent scaler outputs
• Chrominance processor
• Luminance processor
• Video clock/timing processor and power-down control
• I2C interface
• VBI data processor
2
Introduction
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TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
www.ti.com
SLES163A – MARCH 2006 – REVISED JULY 2006
1.3.1 Related Products
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TVP5150
TVP5150AM1
TVP5145
TVP5146
TVP5147
TVP5160
1.3.2 Ordering Information
abc
TA
0°C to 70°C
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PACKAGED DEVICES
128-PIN TQFP-PowerPAD™
PACKAGE OPTION
TVP5154PNP
Tray
TVP5154PNPR
Tape and reel
Introduction
3
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
www.ti.com
SLES163A – MARCH 2006 – REVISED JULY 2006
OUTPUT FORMATTER
2 Functional Block Diagram
AIP1B
M
U
X
9−Bit
A/D
AGC
LUMINANCE
PROCESSING
SCALER
CHROMINANCE
PROCESSING
OUTPUT FORMATTER
AIP1A
Y/C
SEPARATION
VBI SLICER
AIP2B
M
U
X
9−Bit
A/D
AGC
LUMINANCE
PROCESSING
SCALER
CHROMINANCE
PROCESSING
OUTPUT FORMATTER
AIP2A
Y/C
SEPARATION
VBI SLICER
AIP3B
M
U
X
9−Bit
A/D
AGC
LUMINANCE
PROCESSING
SCALER
CHROMINANCE
PROCESSING
OUTPUT FORMATTER
AIP3A
Y/C
SEPARATION
VBI SLICER
AIP4B
M
U
X
9−Bit
A/D
AGC
SCL
SDA
SCALER
CHROMINANCE
PROCESSING
I2C
INTERFACE
HOST
PROCESSOR
XIN/OSC
LUMINANCE
PROCESSING
PLL
XOUT
CH2_OUT [7:0]
YCBCR 8−Bit 4:2:2
CH3_OUT [7:0]
YCBCR 8−Bit 4:2:2
CH4_OUT [7:0]
YCBCR 8−Bit 4:2:2
FID/GLCO[1−4]
SYNC PROCESSOR
AIP4A
Y/C
SEPARATION
VBI SLICER
CH1_OUT [7:0]
YCBCR 8−Bit 4:2:2
VSYNC/PAL[1−4]
INTERQ/GPCL/BLK[1−4]
HSYNC[1−4]
AVID[1−4]
CLK[1−4]
SCLK[1−4]
Figure 2-1. Functional Block Diagram
4
Functional Block Diagram
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TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
www.ti.com
SLES163A – MARCH 2006 – REVISED JULY 2006
3 Terminal Assignments
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
AGND
AVDD
REFP1
REFM1
XIN/OSC
XOUT
PDN
RESETB
SCL
SDA
I2CA0
I2CA1
DGND
DVDD
IOVDD
IOGND
CH1_OUT0
CH1_OUT1
CH1_OUT2
CH1_OUT3
CH1_OUT4
CH1_OUT5
CH1_OUT6
CH1_OUT7
SCLK1
CLK1
INT1/GPCL1/VBLK1
AVID1
HSYNC1
DGND
DVDD
IOVDD
3.1 Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TVP5154
128−Pin TQFP Package
(Top View)
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
IOGND
VSYNC1/PALI1
FID1/GLCO1
CH2_OUT0
CH2_OUT1
CH2_OUT2
CH2_OUT3
CH2_OUT4
CH2_OUT5
CH2_OUT6
CH2_OUT7
SCLK2
CLK2
INT2/GPCL2/VBLK2
DGND
DVDD
IOVDD
IOGND
AVID2
HSYNC2
VSYNC2/PALI2
FID2/GLCO2
CH3_OUT0
CH3_OUT1
CH3_OUT2
CH3_OUT3
CH3_OUT4
CH3_OUT5
CH3_OUT6
CH3_OUT7
DGND
DVDD
PLL_VDD
PLL_GND
AGND
TMS
FID4/GLCO4
VSYNC4/PALI4
HSYNC4
AVID4
INT4/GPCL4/VBLK4
CLK4
SCLK4
IOGND
IOVDD
DVDD
DGND
CH4_OUT7
CH4_OUT6
CH4_OUT5
CH4_OUT4
CH4_OUT3
CH4_OUT2
CH4_OUT1
CH4_OUT0
FID3/GLCO3
VSYNC3/PALI3
HSYNC3
AVID3
INT3/GPCL3/VBLK3
CLK3
SCLK3
IOGND
IOVDD
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AI1GND
AIP1A
AIP1B
PLL_VDD
PLL_GND
REFM2
REFP2
AVDD
AGND
AI2GND
AIP2A
AIP2B
PLL_VDD
PLL_GND
AVDD
AGND
REFM3
REFP3
AVDD
AGND
AI3GND
AIP3A
AIP3B
PLL_VDD
PLL_GND
REFM4
REFP4
AVDD
AGND
AI4GND
AIP4A
AIP4B
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Terminal Assignments
5
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
www.ti.com
SLES163A – MARCH 2006 – REVISED JULY 2006
3.2 Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
Analog Section
AIP1A
AIP1B
2
3
I
Analog inputs for Channel 1. Connect to the video analog input via a 0.1-µF capacitor. The
maximum input range is 0–0.75 VPP, and may require an attenuator to reduce the input
amplitude to the desired level. If not used, connect to AGND via a 0.1-µF capacitor. Refer to
the schematic in Section 12.
AIP2A
AIP2B
11
12
I
Analog inputs for Channel 2. Connect to the video analog input via a 0.1-µF capacitor. The
maximum input range is 0-0.75 VPP, and may require an attenuator to reduce the input
amplitude to the desired level. If not used, connect to AGND via a 0.1-µF capacitor. Refer to
the schematic in Section 12.
AIP3A
AIP3B
22
23
I
Analog inputs for Channel 3. Connect to the video analog input via a 0.1-µF capacitor. The
maximum input range is 0-0.75 VPP, and may require an attenuator to reduce the input
amplitude to the desired level. If not used, connect to AGND via a 0.1-µF capacitor. Refer to
the schematic in Section 12.
AIP4A
AIP4B
31
32
I
Analog inputs for Channel 4. Connect to the video analog input via a 0.1-µF capacitor. The
maximum input range is 0-0.75 VPP, and may require an attenuator to reduce the input
amplitude to the desired level. If not used, connect to AGND via a 0.1-µF capacitor. Refer to
the schematic in Section 12.
AVDD
8, 15, 19,
28, 127
P
Analog power supply. Connect to 1.8-V analog supply.
AGND
9, 16, 20,
29, 35,
128
P
Analog power supply return. Connect to analog ground.
AIxGND
1, 10, 21,
30
P
Analog input signal return. Connect to analog ground.
PLL_GND
5, 14, 25,
34
P
PLL power supply return. Connect to analog ground.
PLL_VDD
4, 13, 24,
33
P
PLL power supply. Connect to 1.8-V analog supply.
REFMx
6, 17, 26,
125
I
Reference supply decoupling . Connect to analog ground through a 1-µF capacitor. Connect
to REFPx through a 1-µF capacitor.
REFPx
7, 18, 27,
126
I
Reference supply decoupling . Connect to analog ground through a 1-µF capacitor. Connect
to REFMx through a 1-µF capacitor.
DGND
47, 66, 82,
99, 116
P
Digital power supply return. Connect to digital ground
DVDD
46, 65, 81,
98, 115
P
Digital power supply. Connect to 1.8-V digital supply.
IOGND
44, 63, 79,
96, 113
P
I/O power supply return. Connect to digital ground.
IOVDD
45, 64, 80,
97, 114
P
I/O power supply. Connect to 3.3-V digital supply
FID1/GLCO1
FID2/GLCO2
FID3/GLCO3
FID4/GLCO4
94
75
56
37
O
1. FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1
indicates the odd field.
2. GLCO: This serial output carries color PLL information. A slave device can decode the
information to allow chroma frequency control from the TVP5154 decoder. Data is
transmitted at the CLK rate in Genlock mode.
AVID1
AVID2
AVID3
AVID4
101
78
59
40
O
Active video indicator. This signal is high during the horizontal active time of the video
output.
INTREQ1/GPCL1/VBLK1
INTREQ2/GPCL2/VBLK2
INTREQ3/GPCL3/VBLK3
INTREQ4/GPCL4/VBLK4
102
83
60
41
I/O
1. Interrupt request : Open drain when active low.
Digital Section
2. GPCL: General-purpose output. In this mode, the state of GPCL is directly programmed
via I2C.
3. VBLK: Vertical blank output. In this mode, the GPCL terminal is used to indicate the VBI
of the output video. The beginning and end times of this signal are programmable via I2C.
6
Terminal Assignments
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TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
www.ti.com
SLES163A – MARCH 2006 – REVISED JULY 2006
TERMINAL
NAME
HSYNC1
HSYNC2
HSYNC3
HSYNC4
NO.
I/O
DESCRIPTION
100
77
58
39
O
Horizontal synchronization
95
76
57
38
O
1. VSYNC: Vertical synchronization
2. PALI: PAL line indicator or horizontal lock indicator. For the PAL line indicator, a 1
indicates a noninverted line, and a 0 indicates an inverted line.
PDN
122
I
Power down (active low). A 0 on this pin puts the decoder in standby mode. PDN preserves
the value of the registers.
RESETB
121
I
Active-low reset. RESETB can be used only when PDN = 1. When RESETB is pulled low, it
resets all the registers and restarts the internal microprocessor.
SCL
120
I/O
I2C serial clock (open drain)
SDA
119
I/O
I2C serial data (open drain)
I2CA0
118
I
During power-on reset, this pin is sampled along with pin 117 (I2CA1) to determine the I2C
address the device is configured to. A 10-kΩ resistor should pull this either high (to IOVDD)
or low to select different I2C device addresses.
I2CA1
117
I
During power-on reset, this pin is sampled along with pin 118 (I2CA0) to determine the I2C
address the device is configured to. A 10-kΩ resistor should pull this either high (to IOVDD)
or low to select different I2C device addresses.
CLK1
CLK2
CLK3
CLK4
103
84
61
42
O
Unscaled system data clock at either 27 MHz or 54 MHz
SCLK1
SCLK2
SCLK3
SCLK4
104
85
62
43
O
Scaled system data clock at 27 MHz. This signal can be used to qualify scaled/unscaled
data when the unscaled system data clock is set to 54 MHz.
XIN/OSC
XOUT
124
123
I
O
External clock reference. The user may connect XIN to an oscillator or to one terminal of a
crystal oscillator. The user may connect XOUT to the other terminal of the crystal oscillator
or not connect XOUT at all. One single 14.31818-MHz crystal or oscillator is needed for
ITU-R BT.601 sampling, for all supported standards.
CH1_OUT[7:0]
105–112
O
Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 1
CH2_OUT[7:0]
86–93
O
Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 2
CH3_OUT[7:0]
67–74
O
Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 3
CH4_OUT[7:0]
48–55
O
Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 4
36
I
Test-mode select. This pin should be connected to digital ground for correct device
operation.
VSYNC1
VSYNC2
VSYNC3
VSYNC4
TMS
/PALI1
/PALI2
/PALI3
/PALI4
4 Functional Description
4.1 Analog Front End
Each channel of the TVP5154 decoder has an analog input channel that accepts two video inputs, which
should be ac coupled through 0.1-µF capacitors. The decoder supports a maximum input voltage range of
0.75 V; therefore, an attenuation of one-half is needed for standard input signals with a peak-to-peak
variation of 1.5 V. The maximum parallel termination before the input to the device is 75 Ω. Refer to
schematic at the end of this document for recommended configuration. The two analog input ports can be
connected as follows:
• Two selectable composite video inputs or
• One S-video input
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level.
The programmable gain amplifier (PGA) and the automatic gain control (AGC) circuit work together to
ensure that the input signal is amplified or attenuated correctly, ensuring the proper input range for the
ADC.
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Functional Description
7
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
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SLES163A – MARCH 2006 – REVISED JULY 2006
When switching CVBS inputs from one input to the other, the AGC settings are internally stored and the
previous settings for the new input are restored. This eliminates flashes and dark frames associated with
switching between inputs that have different signal amplitudes.
The ADC has nine bits of resolution and runs at a maximum speed of 27 MHz. The clock input for the
ADC comes from the PLL.
4.2 Composite Processing Block Diagram
The composite processing block processes NTSC/PAL/SECAM signals into the YCbCr color space.
Figure 2-1 shows the basic architecture of this processing block.
Figure 2-1 shows the luminance/chrominance (Y/C) separation process in the TVP5154 decoders. The
composite video is multiplied by sub-carrier signals in the quadrature modulator to generate the color
difference signals Cb and Cr. Cb and Cr are then low pass (LP) filtered to achieve the desired bandwidth
and to reduce crosstalk.
An adaptive 4-line comb filter separates CbCr from Y. Chroma is remodulated through another quadrature
modulator and subtracted from the line-delayed composite video to generate luma. Contrast, brightness,
hue, saturation, and sharpness (using the peaking filter) are programmable via I2C.
The Y/C separation is bypassed for S-video input. For S-video, the remodulation path is disabled.
4.3 Adaptive Comb Filtering
The 4-line comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is
bypassed in the luma path, chroma notch filters are used. TI’s patented adaptive 4-line comb filter
algorithm reduces artifacts, such as hanging dots at color boundaries, and detects and properly handles
false colors in high-frequency luminance images, such as a multiburst pattern or circle pattern.
4.4 Color Low-Pass Filter
In some applications, it is desirable to limit the Cb/Cr bandwidth to avoid crosstalk. This is especially true
in the case of video signals that have asymmetrical Cb/Cr sidebands. The color LP filters provided limit the
bandwidth of the Cb/Cr signals.
Color LP filters are needed when the comb filtering turns off, due to extreme color transitions in the input
image. Refer to Chrominance Control #2 Register, for the response of these filters. The filters have three
options that allow three different frequency responses based on the color frequency characteristics of the
input video.
4.5 Luminance Processing
The luma component is derived from the composite signal by subtracting the remodulated chroma
information. A line delay exists in this path to compensate for the line delay in the adaptive comb filter in
the color processing chain. The luma information is then fed into the peaking circuit, which enhances the
high-frequency components of the signal, thus, improving sharpness.
4.6 Chrominance Processing
For NTSC/PAL formats, the color processing begins with a quadrature demodulator. The Cb/Cr signals
then pass through the gain control stage for chroma saturation adjustment. An adaptive comb filter is
applied to the demodulated signals to separate chrominance and eliminate cross-chrominance artifacts.
An automatic color-killer circuit is also included in this block. The color killer suppresses the chroma
processing when the color burst of the video signal is weak or not present. The SECAM standard is similar
to PAL except for the modulation of color, which is FM instead of QAM.
8
Functional Description
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TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
www.ti.com
SLES163A – MARCH 2006 – REVISED JULY 2006
4.7 Timing Processor
The timing processor is a combination of hardware and software running in the internal microprocessor
that serves to control horizontal lock to the input sync pulse edge, AGC and offset adjustment in the
analog front end, and vertical sync detection.
4.8 VBI Data Processor
The TVP5154 VBI data processor (VDP) slices various data services, such as teletext (WST, NABTS),
closed caption (CC), wide screen signaling (WSS), etc. These services are acquired by programming the
VDP to enable standards in the VBI. The results are stored in a FIFO and/or registers. The teletext results
are stored in a FIFO only. Table 4-1 lists a summary of the types of VBI data supported according to the
video standard. It supports ITU-R BT. 601 sampling for each.
Table 4-1. Data Types Supported by the VDP
LINE MODE REGISTER
(D0h–FCh) BITS [3:0]
NAME
DESCRIPTION
0000b
WST SECAM
Teletext, SECAM
0001b
WST PAL B
Teletext, PAL, System B
0010b
WST PAL C
Teletext, PAL, System C
0011b
WST, NTSC B
Teletext, NTSC, System B
0100b
NABTS, NTSC C
Teletext, NTSC, System C
0101b
NABTS, NTSC D
Teletext, NTSC, System D (Japan)
0110b
CC, PAL
Closed caption PAL
0111b
CC, NTSC
Closed caption NTSC
1000b
WSS, PAL
Wide-screen signal, PAL
1001b
WSS, NTSC
Wide-screen signal, NTSC
1010b
VITC, PAL
Vertical interval timecode, PAL
1011b
VITC, NTSC
Vertical interval timecode, NTSC
1100b
VPS, PAL
Video program system, PAL
1111b
Active Video
Active video/full field
At power up, the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents
with the lookup table (see Section 9.2.63). This is done through port address C3h. Each read from or write
to this address auto increments an internal counter to the next RAM location. To access the VDP-CRAM,
the line mode registers (D0h–FCh) must be programmed with FFh to avoid a conflict with the internal
microprocessor and the VDP in both writing and reading. Full field mode must also be disabled.
Available VBI lines are from line 6 to line 27 of both field 1 and field 2. Each line can be any VBI mode.
Output data is available either through the VBI-FIFO (B0h) or through dedicated registers at 90h–AFh,
both of which are available through the I2C port.
4.9 VBI FIFO and Ancillary Data in Video Stream
Sliced VBI data can be output as ancillary data in the video stream in the ITU-R BT.656 mode. VBI data is
output during the horizontal blanking period following the line from which the data was retrieved. Table 4-2
shows the header format and sequence of the ancillary data inserted into the video stream. This format is
also used to store any VBI data into the FIFO. The size of FIFO is 512 bytes. Therefore, the FIFO can
store up to 11 lines of teletext data with the NTSC NABTS standard.
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Table 4-2. Ancillary Data Format and Sequence
BYTE
NO.
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
DESCRIPTION
Ancillary data preamble
2
1
1
1
1
1
1
1
1
3
NEP
EP
0
1
0
DID2
DID1
DID0
4
NEP
EP
F5
F4
F3
F2
F1
F0
Secondary data ID (SDID)
5
NEP
EP
N5
N4
N3
N2
N1
N0
Number of 32 bit data (NN)
6
Video line # [7:0]
7
0
0
0
Data error
Match #1
Data ID (DID)
Internal data ID0 (IDID0)
Match #2
Video line # [9:8]
Internal data ID1 (IDID1)
8
1. Data
Data byte
9
2. Data
Data byte
10
3. Data
Data byte
11
4. Data
Data byte
•
•
•
•
•
•
— 1. Data
Data byte
m. Data
4(N+2)-1
NEP
EP
0
0
0
Nth word
Data byte
CS[5:0]
0
1st word
0
EP:
Even parity for D0–D5
NEP:
Negated even parity
DID:
91h: Sliced data of VBI lines of first field
Check sum
0
0
0
Fill byte
53h: Sliced data of line 24 to end of first field
55h: Sliced data of VBI lines of second field
97h: Sliced data of line 24 to end of second field
SDID:
This field holds the data format taken from the line mode register of the corresponding line.
NN:
Number of Dwords beginning with byte 8 through 4(N+2). This value is the number of Dwords where
each Dword is 4 bytes.
IDID0:
Transaction video line number [7:0]
IDID1:
Bit 0/1 = Transaction video line number [9:8]
Bit 2 = Match 2 flag
Bit 3 = Match 1 flag
Bit 4 = 1 if an error was detected in the EDC block. 0 if not.
CS:
Sum of D0–D7 of DID through last data byte
Fill byte: Fill bytes make a multiple of four bytes from byte 0 to last fill byte. For teletext modes, byte 8 is the
sync pattern byte. Byte 9 is 1. Data (the first data byte).
4.10 Raw Video Data Output
The TVP5154 decoder can output raw A/D video data at 2× sampling rate for external VBI slicing. This is
transmitted as an ancillary data block during the active horizontal portion of the line and during vertical
blanking.
10
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4.11 Output Formatter
The output formatter is responsible for generating the output digital video stream. The YCbCr digital output
can be programmed as 8-bit 4:2:2 or 8-bit ITU-R BT.656 parallel interface standard. Depending on which
output mode is selected, the output for each channel can be unscaled data, scaled data, or both scaled
and unscaled data interleaved in various ways.
Table 4-3. Summary of Line Frequencies, Data Rates, and Pixel Counts
STANDARDS
HORIZONTAL LINE RATE
(kHz)
PIXELS
PER LINE
ACTIVE PIXELS
PER LINE
CLK FREQUENCY
(MHz)
15.73426
858
720
27.00
NTSC (M, 4.43), ITU-R BT.601
PAL (B, D, G, H, I), ITU-R BT.601
15.625
864
720
27.00
PAL (M), ITU-R BT.601
15.73426
858
720
27.00
PAL (N), ITU-R BT.601
15.625
864
720
27.00
SECAM, ITU-R BT.601
15.625
864
720
27.00
4.12 Synchronization Signals
External (discrete) syncs are provided via the following signals:
• VSYNC (vertical sync)
• FID/VLK (field indicator or vertical lock indicator)
• GPCL/VBLK (general-purpose I/O or vertical blanking indicator)
• PALI/HLK (PAL switch indicator or horizontal lock indicator)
• HSYNC (horizontal sync)
• AVID (active video indicator)
VSYNC, FID, PALI, and VBLK are software set and programmable to the CLK pixel count. This allows any
possible alignment to the internal pixel count and line count. The default settings for a 525-/625-line video
output are shown in Figure 4-1.
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525 LINE
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
Composite
Video
VSYNC
FID
GPCL/VBLK
↔
VBLK Stop
↔
VBLK Start
262
263
264
265
266
267
268
269
270
271
272
273
282
283
284
Composite
Video
VSYNC
FID
GPCL/VBLK
↔
VBLK Stop
↔
VBLK Start
625 LINE
310
311
312
313
314
315
316
317
318
319
320
333
334
335
336
Composite
Video
VSYNC
FID
GPCL/VBLK
↔
VBLK Stop
↔
VBLK Start
622
623
624
625
1
2
3
4
5
6
7
20
21
22
23
Composite
Video
VSYNC
FID
GPCL/VBLK
↔
VBLK Start
↔
VBLK Stop
Line numbering conforms to ITU-R BT.470.
Figure 4-1. 8-Bit 4:2:2, Timing With 2× Pixel Clock (CLK) Reference
HSYN
HSYN START
AVID
AV ID STOP
AV ID STA RT
NOTE: AVID rising edge occurs four CLK cycles early when in ITU-R BT.656 output mode.
Figure 4-2. Horizontal Synchronization Signals
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4.13 Active Video (AVID) Cropping
AVID cropping provides a means to decrease the amount of video data output. This is accomplished by
horizontally blanking a number of AVID pulses and by vertically blanking a number of lines per frame. The
horizontal AVID cropping is controlled using registers 11h and 12h for start pixels MSB and LSB,
respectively.
Registers 13h and 14h provide access to stop pixels MSB and LSB, respectively. The vertical AVID
cropping is controlled using the vertical blanking (VBLK) start and stop registers at addresses 18h and
19h. Figure 4-3 shows an AVID application.
AVID cropping can be independently controlled for scaled (registers 25h, 26h, 29h, and 2Ah) and
unscaled (registers 11h thru 14h) data streams. AVID start and stop must be changed in multiples of two
pixels to ensure correct UV alignment.
Additionally, AVID start and stop can be configured to include the SAV- and EAV-embedded sync signals
or to exclude them, and to either include or exclude ITU656 ancillary data.
VBLK
Stop
Active Video Area
AVID Cropped Area
VSYNC
VBLK
Start
AVID
Start
AVID
Stop
HSYNC
Figure 4-3. AVID Application
4.14 Embedded Syncs
Standards with embedded syncs insert SAV and EAV codes into the data stream at the beginning and end
of horizontal blanking. These codes contain the V and F bits that also define vertical timing. F and V
change on EAV. Table 4-4 gives the format of the SAV and EAV codes.
H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line
and field counter varies depending on the standard. Please refer to ITU-R BT.656 for more information on
embedded syncs.
The P bits are protection bits:
P3 = V x or
H P2 = F x or
H P1 = F x or
V P0 = F x or
V x or H
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Table 4-4. EAV and SAV Sequence
8-BIT DATA
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
Preamble
1
1
1
1
1
1
1
1
Preamble
0
0
0
0
0
0
0
0
Preamble
0
0
0
0
0
0
0
0
Status word
1
F
V
H
P3
P2
P1
P0
The status word may be modified in order to pass information about whether the current data corresponds
to scaled or unscaled data. See register 1Fh for more information.
4.15 Clock and Data Control
Figure 4-4 shows a logical schematic of the data and clock control signals.
Blank
=01
Delay
=00
Scaler
=11
Data
Decoder
Field mode(0)
Field mode(1)
Field mode(2)
Field mode(3)
Field mode(4)
Field mode(5)
Field mode(6)
Field mode(7)
Field mode(8)
Field mode(9)
Field mode(10)
Field mode(11)
Field mode(12)
Field mode(13)
Field mode(14)
Field mode(15)
=4
01
=1
00
=0
/2 =
27MHz
=2/3
Mode
SCLK
SCLK OE
SCLK edge
!=3
CLK
54MHz
=3
CLK OE
Mode
CLK edge
Figure 4-4. Clock and Data Control
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5 I2C Host Interface
The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line
(SCL), which carry information between the devices connected to the bus. The input pins I2CA0 and
I2CA1 are used to select the slave address to which the device responds. Although the I2C system can be
multimastered, the TVP5154 decoder functions as a slave device only.
Both SDA and SCL must be connected to IOVDD via pullup resistors. When the bus is free, both lines are
high. The slave address select terminals (I2CA0 and I2CA1) enable the use of four TVP5154 decoders on
the same I2C bus. At the trailing edge of reset, the status of the I2CA0 and I2CA1 lines are sampled to
determine the device address used. Table 5-1 summarizes the terminal functions of the I2C-mode host
interface. Table 5-2 shows the device address selection options.
Table 5-1. I2C Terminal Description
SIGNAL
TYPE
I2CA0
I
Slave address selection
DESCRIPTION
I2CA1
I
Slave address selection
SCL
I/O (open drain)
Input/output clock line
SDA
I/O (open drain)
Input/output data line
Table 5-2. I2C Host Interface Device Addresses
A6
A5
A4
A3
A2
A1 (I2CA1)
A0 (I2CA0)
R/W
HEX
1
0
1
1
1
0
0
1/0
B9/B8
1
0
1
1
1
0
1
1/0
BB/BA
1
0
1
1
1
1
0
1/0
BD/BC
1
0
1
1
1
1
1
1/0
BF/BE
Data transfer rate on the bus is up to 400 kbit/s. The number of interfaces connected to the bus is
dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the
high period of the SCL, except for start and stop conditions. The high or low state of the data line can only
change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the
SCL is high indicates an I2C start condition. A low-to-high transition on the SDA line while the SCL is high
indicates an I2C stop condition.
Every byte placed on the SDA must be eight bits long. The number of bytes that can be transferred is
unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is
generated by the I2C master.
To simplify programming of each of the four decoder channels, a single I2C write transaction can be
transmitted to any one or more of the four cores in parallel. This reduces the time required to download
firmware or to configure the device when all channels are to be configured in the same manner. It also
enables the addresses for all registers to be common across all decoders.
I2C sub-address 0xFE contains four bits, with each bit corresponding to one of the decoder cores. If this
bit is set, I2C write transactions are sent to the corresponding decoder core. If the bit is 0, the
corresponding decoder does not receive the I2C write transactions.
I2C sub-address 0xFF contains four bits, with each bit corresponding to one of the decoder cores. If this
bit is set, I2C read transactions are sent to the corresponding decoder core. Note, only one of the bits in
this register should be set at a given time, ensuring that only one decoder core is accessed at a time for
read operations. If more than one bit is set, the lowest set bit number corresponds to the core that
responds to the read transaction.
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Note, when register 0xFE is written to with any value, register 0xFF is set to 0x00. Likewise, when register
0xFF is written to with any value, register 0xFE is set to 0x00.
5.1 I2C Write Operation
Data transfers occur utilizing the following illustrated formats.
An I2C master initiates a write operation to the TVP5154 decoder by generating a start condition (S)
followed by the TVP5154 I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate
a write cycle. After receiving an acknowledge from the TVP5154 decoder, the master presents the
sub-address of the register, or the first of a block of registers it wants to write, followed by one or more
bytes of data, MSB first. The TVP5154 decoder acknowledges each byte after completion of each
transfer. The I2C master terminates the write operation by generating a stop condition (P).
abc
Step 1
0
I2C start (master)
S
Step 2
7
6
5
4
3
2
1
0
I2C general address (master)
1
0
1
1
1
0
X
0
Step 3
9
I2C acknowledge (slave)
A
Step 4
I2C write register address (master)
7
6
5
4
3
2
1
0
addr
addr
addr
addr
addr
addr
addr
addr
Step 5
9
I2C acknowledge (slave)
A
Step 6
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
I2C
write data (master)
Step 7 (1)
9
I2C
A
acknowledge (slave)
Step 8
0
I2C
P
(1)
stop (master)
Repeat steps 6 and 7 until all data have been written.
5.2 I2C Read Operation
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C
master initiates a write operation to the TVP5154 decoder by generating a start condition (S) followed by
the TVP5154 I2C address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving
acknowledges from the TVP5154 decoder, the master presents the sub-address of the register or the first
of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycle
immediately by generating a stop condition (P).
The second phase is the data phase. In this phase, an I2C master initiates a read operation to the
TVP5154 decoder by generating a start condition followed by the TVP5154 I2C address (as shown below
for a read operation), in MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge
from the TVP5154 decoder, the I2C master receives one or more bytes of data from the TVP5154
decoder. The I2C master acknowledges the transfer at the end of each byte. After the last data byte
desired has been transferred from the TVP5154 decoder to the master, the master generates a not
acknowledge followed by a stop.
16
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Read Phase 1
abc
Step 1
0
I2C start (master)
S
Step 2
7
6
5
4
3
2
1
0
I2C general address (master)
1
0
1
1
1
0
X
0
Step 3
9
I2C
A
7
6
5
4
3
2
1
0
addr
addr
addr
addr
addr
addr
addr
addr
acknowledge (slave)
Step 4
I2C
read register address (master)
Step 5
9
I2C
A
acknowledge (slave)
Step 6
0
I2C stop (master)
P
Read Phase 2
abc
Step 7
0
I2C start (master)
S
Step 8
7
6
5
4
3
2
1
0
I2C
1
0
1
1
1
0
X
1
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
general address (master)
Step 9
9
I2C
A
acknowledge (slave)
Step 10
I2C
read data (slave)
Step 11 (1)
9
I2C not acknowledge (master)
A
Step 12
0
I2C stop (master)
P
(1)
Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
5.2.1
I2C Timing Requirements
The TVP5154 decoder requires delays in the I2C accesses to accommodate its internal processor’s timing.
In accordance with I2C specifications, the TVP5154 decoder holds the I2C clock line (SCL) low to indicate
the wait period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low
condition, the maximum delays must always be inserted where required. These delays are of variable
length; maximum delays are indicated in the following diagram:
Table 5-3. I2C Timing
Start
(1)
Slave address (B8h)
Ack
Subaddress
Ack
Data (XXh)
Ack
Wait 128 µs (1)
Stop
If the SCL pin is not monitored by the master to enable pausing, a delay of 128 µs should be inserted between transactions for registers
00h through 8Fh.
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6 Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to
drive the PLL. This may be input to the TVP5154 decoder on terminal 124 (XIN), or a crystal of
14.31818-MHz fundamental resonant frequency may be connected across terminals 123 and 124 (XIN
and XOUT). Figure 6-1 shows the reference clock configurations. For the example crystal circuit shown (a
parallel-resonant crystal with 14.31818-MHz fundamental frequency), the external capacitors must have
the following relationship:
CL1 = CL2 = 2CL – CSTRAY
where CSTRAY is the terminal capacitance with respect to ground. Figure 6-1 shows the reference clock
configurations.
14.31818-MHz
Crystal
124
14.31818 MHz
1.8-V Clock
CL1
124
R
123
123
CL2
Figure 6-1. Clock and Crystal Connectivity
7 Genlock Control and RTC
A Genlock control (GLCO) function is provided to support a standard video encoder to synchronize its
internal color oscillator for properly reproduced color with unstable timebase sources like VCRs.
The frequency control word of the internal color subcarrier digital control oscillator (DTO) and the
subcarrier phase reset bit are transmitted via the GLCO terminal. The frequency control word is a 23-bit
binary number. The frequency of the DTO can be calculated from the following equation:
F
F dto + ctrl
F clk
223
(1)
where Fdto is the frequency of the DTO, Fctrl is the 23–bit DTO frequency control, and Fclk is the
frequency of the CLK.
7.1 TVP5154 Genlock Control Interface
A write of 1 to bit 4 of the chrominance control register at I2C subaddress 1Ah causes the subcarrier DTO
phase reset bit to be sent on the next scan line on GLCO. The active-low reset bit occurs seven CLKs
after the transmission of the last bit of DCO frequency control. Upon the transmission of the reset bit, the
phase of the TVP5154 internal subcarrier DCO is reset to zero.
A Genlock slave device can be connected to the GLCO terminal and uses the information on GLCO to
synchronize its internal color phase DCO to achieve clean line and color lock.
7.2 RTC Mode
Figure 7-1 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is four times slower
than the GLCO clock rate. For PLL frequency control, the upper 22 bits are used. Each frequency control
bit is two clock cycles long. The active-low reset bit occurs six CLKs after the transmission of the last bit of
PLL frequency control.
18
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CLK
GLCO
22
MSB
LSB
21
0
>128 CLK
23 CLK
23-Bit Frequency Control
7 CLK
1 CLK
1 CLK
Start Bit
DCO Reset Bit
GLCO Timing
M
S
B
RTC
L
S
B
0
21
128 CLK
16 CLK
44 CLK
1 CLK
22-Bit Fsc Frequency Control
2 CLK
PAL
Switch
2 CLK
Start
Bit
3 CLK
1 CLK
Reset
Bit
Figure 7-1. RTC Timing
8 Power-Up, Reset, and Power-Down Sequence (Required)
Terminals 121 (RESETB) and 122 (PDN) work together to put the TVP5154 decoder into one of three
modes. Table 8-1 shows the configuration.
After power up, the device is in an unknown state with its outputs undefined until it receives a RESETB
active low for at least 200 ns. The power supplies should be active and stable for 10 ms before RESETB
becomes inactive. There are no power-sequencing requirements, except that all power supplies should
become active and stable within 500 ms of each other.
After each power-up and hardware reset, this procedure must be followed:
1. Wait at least 1 ms. Each decoder must be started by writing 0x00h to register 7Fh for all four decoders.
2. Wait at least 1 ms. Check the status of the TVP5154 by doing an I2C read of the version number,
register 81h, for all four decoders.
3. Verify that the value 0x54h is read.
4. If the value 0x54h is not read, toggle the TVP5154 reset pin (RESETB, pin number 121).
This procedure should be repeated if necessary until the value 0x54h is read from register 81h for all four
decoders.
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Table 8-1. Reset and Power-Down Modes
PDN
RESETB
CONFIGURATION
0
0
Reserved (undefined state)
0
1
Powers down the decoder
1
0
Resets the decoder
1
1
Normal operation
9 Internal Control Registers
9.1 Overview
The TVP5154 decoder is initialized and controlled by sets of internal registers that set all device operating
parameters. Communication between the external controller and the TVP5154 decoder is through the I2C.
Two sets of registers exist, direct and indirect. Table 9-1 shows the summary of the direct registers.
Reserved registers must not be written. Reserved bits in the defined registers must be written with 0s,
unless otherwise noted. The detailed programming information of each register is described in the
following sections.
I2C register 0xFE controls which of the four decoders receives I2C commands. I2C register 0xFF controls
which decoder core responds to I2C reads. Note, for a read operation, it is necessary to perform a write
first, in order to set the desired sub-address for reading.
After power up and the hardware reset, each decoder must be started by writing 0x00h to register 7Fh for
all four decoders.
Table 9-1. Direct Register Summary
ADDRESS
DEFAULT
R/W (1)
Video input source selection #1
00h
00h
R/W
Analog channel controls
01h
15h
R/W
Operation mode controls
02h
00h
R/W
Miscellaneous controls
03h
01h
R/W
Autoswitch mask
04h
DCh
R/W
Clock control
05h
08h
R/W
Color killer threshold control
06h
10h
R/W
Luminance processing control #1
07h
60h
R/W
Luminance processing control #2
08h
00h
R/W
Brightness control
09h
80h
R/W
Color saturation control
0Ah
80h
R/W
Hue control
0Bh
00h
R/W
Contrast control
0Ch
80h
R/W
Outputs and data rates select
0Dh
47h
R/W
Luminance processing control #3
0Eh
00h
R/W
Configuration shared pins
0Fh
08h
R/W
Reserved
10h
Active video cropping start MSB for unscaled data
11h
00h
R/W
Active video cropping start LSB for unscaled data
12h
00h
R/W
Active video cropping stop MSB for unscaled data
13h
00h
R/W
Active video cropping stop LSB for unscaled data
14h
00h
R/W
Genlock/RTC
15h
01h
R/W
Horizontal sync start
16h
80h
R/W
REGISTER FUNCTION
(1)
20
R = Read only, W = Write only, R/W = Read and write
Internal Control Registers
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Table 9-1. Direct Register Summary (continued)
ADDRESS
DEFAULT
R/W (1)
Ancillary SAV/EAV control
17h
52h
R/W
Vertical blanking start
18h
00h
R/W
REGISTER FUNCTION
Vertical blanking stop
19h
00h
R/W
Chrominance processing control #1
1Ah
0Ch
R/W
Chrominance processing control #2
1Bh
14h
R/W
Interrupt reset register B
1Ch
00h
R/W
Interrupt enable register B
1Dh
00h
R/W
Interrupt configuration register B
1Eh
00h
R/W
Output control
1Fh
00h
R/W
Reserved
20h
I2C indirect registers
21h–24h
00h
R/W
AVID start/control for scaled data
25h–26h
00h
R/W
28h
00h
R/W
29h–2Ah
00h
R/W
Reserved
Video standard
AVID stop for scaled data
27h
Reserved
2Bh
Cb gain factor
2Ch
R
Cr gain factor
2Dh
R
Reserved
656 Revision Select
Reserved
2Eh–2Fh
30
00h
R/W
31h–7Fh
MSB of device ID
80h
51h
R
LSB of device ID
81h
54h
R
ROM major version
82h
02h
R
ROM minor version
83h
00h
R
Vertical line count MSB
84h
R
Vertical line count LSB
85h
R
Interrupt status register B
86h
R
Interrupt active register B
87h
R
Status register #1
88h
R
Status register #2
89h
R
Status register #3
8Ah
R
Status register #4
8Bh
R
Status register #5
8Ch
R
Reserved
8Dh–8Fh
Closed caption data registers
90h–93h
R
WSS data registers
94h–99h
R
VPS data registers
9Ah–A6h
R
VITC data registers
A7h–AFh
R
VBI FIFO read data
B0h
R
Teletext filter 1
B1h–B5h
00h
R/W
Teletext filter 2
B6h–BAh
00h
R/W
BBh
00h
R/W
Teletext filter enable
Reserved
BCh–BFh
Interrupt status register A
C0h
00h
R/W
Interrupt enable register A
C1h
00h
R/W
Interrupt configuration
C2h
04h
R/W
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Table 9-1. Direct Register Summary (continued)
ADDRESS
DEFAULT
R/W (1)
VDP configuration RAM data
C3h
B8h
R/W
Configuration RAM address low byte
C4h
1Fh
R/W
Configuration RAM address high byte
C5h
00h
R/W
VDP status register
C6h
R
FIFO word count
C7h
R
FIFO interrupt threshold
C8h
80h
FIFO reset
C9h
00h
W
Line number interrupt
CAh
00h
R/W
Pixel alignment register low byte
CBh
4Eh
R/W
Pixel alignment register high byte
CCh
00h
R/W
FIFO output control
CDh
01h
R/W
Reserved
CEh
Full field enable
CFh
00h
R/W
D0h
D1h–FBh
00h
FFh
R/W
Full field mode register
FCh
7Fh
R/W
Reserved
FDh
Decoder core write enables
FEh
0Fh
R/W
Decoder core read enables
FFh
00h
R/W
REGISTER FUNCTION
Line mode registers
R/W
9.2 Direct Register Definitions
Direct registers are written to by performing a 3-byte I2C transaction:
START : DEVICE_ID : SUB_ADDRESS : DATA : STOP
Each direct register is eight bits wide.
9.2.1
Video Input Source Selection #1 Register
Address
00h
Default
00h
7
6
5
4
Reserved
3
2
1
0
Black output
Reserved
Channel n source selection
S-video selection
Channel n source selection:
0 = AIPnA selected (default)
1 = AIPnB selected
22
Internal Control Registers
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Table 9-2. Analog Channel and Video Mode Selection
ADDRESS 00
INPUT(S) SELECTED
BIT 1
BIT 0
AIPnA (default)
0
0
AIPnB
1
0
AIPnA (luma), AIPnB (chroma)
x
1
Composite
S-Video
Where n = 1, 2, 3, 4
Black output:
0 = Normal operation (default)
1 = Force black screen output (outputs synchronized)
a. Forced to 10h in normal mode
b. Forced to 01h in extended mode
9.2.2
Analog Channel Controls Register
Address
01h
Default
15h
7
6
5
Reserved
4
1
3
2
Automatic offset control
1
0
Automatic gain control
Automatic offset control:
00 = Disabled
01 = Automatic offset enabled (default)
10 = Reserved
11 = Offset level frozen to the previously set value
Automatic gain control (AGC):
00 = Disabled (fixed gain value)
01 = AGC enabled (default)
10 = Reserved
11 = AGC frozen to the previously set value
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9.2.3
Operation Mode Controls Register
Address
02h
Default
00h
7
6
Fast lock mode
Color burst
reference enable
5
4
TV/VCR mode
3
2
1
0
White peak
disable
Color subcarrier
PLL frozen
Luma peak
disable
Power down
mode
Fast lock mode:
0 = Normal operation (default)
1 = Fast lock mode. Locks within three fields if stable input signal and forced video standard.
Color burst reference enable:
0 = Color burst reference for AGC disabled (default)
1 = Color burst reference for AGC enabled
TV/VCR mode:
00 = Automatic mode determined by the internal detection circuit (default)
01 = Reserved
10 = VCR (nonstandard video) mode
11 = TV (standard video) mode
With automatic detection enabled, unstable or nonstandard syncs on the input video forces the detector into the VCR mode. This turns off
the comb filters and turns on the chroma trap filter.
White peak disable:
0 = White peak protection enabled (default)
1 = White peak protection disabled
Color subcarrier PLL frozen:
0 = Color subcarrier PLL increments by the internally generated phase increment (default).
GLCO pin outputs the frequency increment.
1 = Color subcarrier PLL stops operating.
GLCO pin outputs the frozen frequency increment.
Luma peak disable
0 = Luma peak processing enabled (default)
1 = Luma peak processing disabled
Power-down mode:
0 = Normal operation (default)
1 = Power-down mode. A/Ds are turned off and internal clocks are reduced to minimum.
24
Internal Control Registers
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9.2.4
Miscellaneous Control Register
Address
03h
Default
01h
7
6
5
4
3
2
1
0
VBKO
GPCL pin
GPCL output
enable
Lock status
(HVLK)
YCbCr output
enable(TVPOE)
HSYNC, VSYNC/PALI,
AVID, FID/GLCO output
enable
Vertical blanking
on/off
CLK output
enable
VBKO (pins 41, 60, 83, 102) function select:
0 = GPCL (default)
1 = VBLK
Note, if these pins are not configured as outputs, they must not be left floating. A 10-kΩ pulldown resistor is recommended if
not driven externally.
GPCL (data is output based on state of bit 5):
0 = GPCL outputs 0 (default)
1 = GPCL outputs 1
GPCL output enable:(1)
0 = GPCL is inactive (default).
1 = GPCL is output.
Note, if these pins are not configured as outputs, they must not be left floating. A 10-kΩ pulldown resistor is recommended if
not driven externally.
(1)GPCL should not be programmed to be 0 when register 0Fh bit 1 is ‘1 (programmed to be GPCL/VBLK).
Lock status (HVLK) (configured along with register 0Fh, see Figure 9-1 for the relationship between the configuration shared pins):
0 = Terminal VSYNC/PALI outputs the PAL indicator (PALI) signal and terminal FID/GLCO outputs the field ID (FID) signal
(default) (if terminals are configured to output PALI and FID in register 0Fh).
1 = Terminal VSYNC/PALI outputs the horizontal lock indicator (HLK) and terminal FID outputs the vertical lock indicator (VLK) (if
terminals are configured to output PALI and FID in register 0Fh).
These are additional functionalities that are provided for ease of use.
YCbCr output enable:
0 = YOUT[7:0] high impedance (default)
1 = YOUT[7:0] active
Note, if these pins are not configured as outputs, they must not be left floating. A 10-kΩ pulldown resistor is recommended if
not driven externally.
HSYNC, VSYNC/PALI, active video indicator (AVID), and FID/GLCO output enables:
0 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high impedance (default).
1 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are active.
Note, if these pins are not configured as outputs, they must not be left floating. A 10-kΩ pulldown resistor is recommended if
not driven externally.
Vertical blanking on/off:
0 = Vertical blanking (VBLK) off (default)
1 = Vertical blanking (VBLK) on
CLK output enable:
0 = CLK output is high impedance.
1 = CLK output is enabled (default).
Note: CLK edge and SCLK are configured through register 05h.
Table 9-3. Digital Output Control
(1)
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REGISTER 03h,
BIT 3 (TVPOE) (1)
REGISTER C2h,
BIT 2 (VDPOE) (1)
YCbCr OUTPUT
0
X
High impedance
X
0
High impedance
1
1
Active
VDPOE default is 1 and TVPOE default is 0.
Internal Control Registers
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0F(Bit 2)
VSYNC/PALI
0F(Bit 4)
LOCK24B
VSYNC
PALI
HLK
0
HVLK
1
HVLK
1
VLK
0
0
0
M
U
X
HLK/HVLK
1
M
U
X
VLK/HVLK
1
FID
0
M
U
X
PALI/HLK/HVLK
1
M
U
X
FID/VLK/HVLK
0
GLCO
1
M
U
X
VSYNC/PALI/HLK/HVLK
M
U
X
FID/GLCO/VLK/HVLK
Pins 38, 57, 76, 95
Pins 37, 56, 75, 94
0F(Bit 6)
LOCK23
0F(Bit 3)
FID/GLCO
03(Bit 4)
HVLK
VBLK
1
GPCL
0
M
U
X
VBLK/GPCL
1
INTREQ
03(Bit 7)
VBKO
0
M
U
X
INTREQ/GPCL//VBLK
Pins 41, 60, 83, 102
CLK
0
PCLK
1
0F(Bit 1)
INTREQ/GPCL/VBLK
M
U
X
PCLK/CLK
Pins 42, 61, 84, 103
0F(Bit 0)
CLK/PCLK
NOTE: Also refer to the configuration shared pins register at subaddress 0Fh.
Figure 9-1. Configuration Shared Pins
26
Internal Control Registers
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9.2.5
Autoswitch Mask Register
Address
04h
Default
DCh
7
6
Reserved
N443_OFF:
0=
1=
PALN_OFF:
0=
1=
PALM_OFF:
0=
1=
SEC_OFF:
0=
1=
9.2.6
5
4
3
2
SEC_OFF
N443_OFF
PALN_OFF
PALM_OFF
1
0
Reserved
NTSC443 is unmasked from the autoswitch process. Autoswitch does switch to NTSC443.
NTSC443 is masked from the autoswitch process. Autoswitch does not switch to NTSC443 (default).
PAL-N is unmasked from the autoswitch process. Autoswitch does switch to PAL-N.
PAL-N is masked from the autoswitch process. Autoswitch does not switch to PAL-N (default).
PAL-M is unmasked from the autoswitch process. Autoswitch does switch to PAL-M.
PAL-M is masked from the autoswitch process. Autoswitch does not switch to PAL-M (default).
SECAM is unmasked from the autoswitch process. Autoswitch does switch to SECAM (default).
SECAM is masked from the autoswitch process. Autoswitch does not switch to SECAM.
Clock Control Register
Address
05h
Default
08h
7
6
5
4
Reserved
3
2
1
0
SCLK OE
Reserved
SCLK edge
CLK edge
CLK edge
0 = CLK data changes on falling edge of CLK.
1 = CLK data changes on rising edge of CLK.
SCLK edge
0 = SCLK data changes on falling edge of SCLK.
1 = SCLK data changes on rising edge of SCLK.
SCLK OE
0 = SCLK output disabled. Output is high impedance.
1 = SCLK output enabled.
NOTE: CLK OE is configured through register 0x03 to maintain compatibility with the TVP5150 family of devices.
9.2.7
Color Killer Threshold Control Register
Address
06h
Default
10h
7
Reserved
6
5
Automatic color killer
4
3
2
1
0
Color killer threshold
Automatic color killer:
00 = Automatic mode (default)
01 = Reserved
10 = Color killer enabled, the CbCr terminals are forced to a zero color state.
11 = Color killer disabled
Color killer threshold:
11111 = –30 dB (minimum)
10000 = – 24 dB (default)
00000 = – 18 dB (maximum)
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9.2.8
Luminance Processing Control #1 Register
Address
07h
Default
60h
7
6
5
4
3
2× luma output
enable
Pedestal not
present
Disable raw
header
Luma bypass enabled during vertical
blanking
2
1
0
Luminance signal delay with respect to
chrominance signal
2× luma output enable:
0 = Output depends on bit 4, luminance bypass enabled during vertical blanking (default).
1 = Outputs 2x luma samples during the entire frame. This bit takes precedence over bit 4.
Pedestal not present:
0 = 7.5 IRE pedestal is present on the analog video input signal.
1 = Pedestal is not present on the analog video input signal (default).
Disable raw header:
0 = Insert 656 ancillary headers for raw data
1 = Disable 656 ancillary headers and instead force dummy ones (0x40) (default)
Luminance bypass enabled during vertical blanking:
0 = Disabled. If bit 7, 2× luma output enable, is 0, normal luminance processing occurs and YCbCr samples are output during
the entire frame (default).
1 = Enabled. If bit 7, 2× luma output enable, is 0, normal luminance processing occurs and YCbCr samples are output during
VACTIVE and 2× luma samples are output during VBLK. Luminance bypass occurs for the duration of the vertical blanking
as defined by registers 18h and 19h.
Luma signal delay with respect to chroma signal in pixel clock increments (range –8 to 7 pixel clocks):
1111 = – 8 pixel clocks delay
1011 = – 4 pixel clocks delay
1000 = – 1 pixel clocks delay
0000 = 0 pixel clocks delay (default)
0011 = 3 pixel clocks delay
0111 = 7 pixel clocks delay
9.2.9
Luminance Processing Control #2 Register
Address
08h
Default
00h
7
6
Reserved
Luminance filter select
5
4
3
Reserved
2
1
Peaking gain
0
Reserved
Luminance filter select:
0 = Luminance comb filter enabled (default)
1 = Luminance chroma trap filter enabled
Peaking gain (sharpness):
00 = 0 (default)
01 = 0.5
10 = 1
11 = 2
Information on peaking frequency: ITU-R BT.601 sampling rate: all standards — peaking center frequency is 2.6 MHz
9.2.10
Brightness Control Register
Address
09h
Default
80h
7
6
5
4
3
2
1
0
Brightness control
Brightness control:
1111 1111 = 255 (bright)
1000 0000 = 128 (default)
0000 0000 = 0 (dark)
28
Internal Control Registers
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9.2.11 Color Saturation Control Register
Address
0Ah
Default
80h
7
6
5
4
3
2
1
0
3
2
1
0
3
2
1
0
Saturation control
Saturation control:
1111 1111 = 255 (maximum)
1000 0000 = 128 (default)
0000 0000 = 0 (no color)
9.2.12 Hue Control Register (does not apply to SECAM)
Address
0Bh
Default
00h
7
6
5
4
Hue control
Hue control:
0111 1111 = +180 degrees
0000 0000 = 0 degrees (default)
1000 0000 = – 180 degrees
9.2.13 Contrast Control Register
Address
0Ch
Default
80h
7
6
5
4
Contrast control
Contrast control:
1111 1111 = 255 (maximum contrast)
1000 0000 = 128 (default)
0000 0000 = 0 (minimum contrast)
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9.2.14
Outputs and Data Rates Select Register
Address
0Dh
Default
47h
7
6
5
Reserved
YCbCr output code range
CbCr code format
4
3
YCbCr data path bypass
2
1
0
YCbCr output format
YCbCr output code range:
0 = ITU-R BT.601 coding range (Y ranges from 16 to 235. U and V range from 16 to 240)
1 = Extended coding range (Y, U, and V range from 1 to 254) (default)
CbCr code format:
0 = Offset binary code (2s complement + 128) (default)
1 = Straight binary code (2s complement)
YCbCr data path bypass:
00 = Normal operation (default)
01 = Decimation filter output connects directly to the YCbCr output pins. This data is similar to the digitized composite data, but
the HBLANK area is replaced with ITU-R BT.656 digital blanking.
10 = Digitized composite (or digitized S-video luma). A/D output connects directly to the YCbCr output pins.
11 = Reserved
YCbCr output format:
000 = 8-bit 4:2:2 YCbCr with discrete sync output
001 = Reserved
010 = Reserved
011 = Reserved
100 = Reserved
101 = Reserved
110 = Reserved
111 = 8-bit ITU-R BT.656 interface with embedded sync output (default)
9.2.15 Luminance Processing Control #3 Register
Address
0Eh
Default
00h
7
6
5
4
Reserved
3
2
1
0
Luminance trap filter select
Luminance filter stop band bandwidth (MHz):
00 = No notch (default)
01 = Notch 1
10 = Notch 2
11 = Notch
Luminance filter select [1:0] selects one of the four chroma trap (notch) filters to produce luminance signal
by removing the chrominance signal from the composite video signal. The stopband of the chroma trap
filter is centered at the chroma subcarrier frequency, with stopband bandwidth controlled by the two
control bits. Refer to Table 9-4 for the stopband bandwidths. The WCF bit is controlled in the chrominance
control #2 register.
30
Internal Control Registers
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Table 9-4. Luma Filter Selection
WCF
0
1
9.2.16
FILTER SELECT
NTSC/PAL/SECAM
ITU-R BT.601
00
1.2214
01
0.8782
10
0.7297
11
0.4986
00
1.4170
01
1.0303
10
0.8438
11
0.5537
Configuration Shared Pins Register
Address
0Fh
Default
08h
7
6
5
4
3
2
1
0
Reserved
FID PIN
Reserved
PALI PIN
FID/GLCO
VSYNC/PALI
INTREQ/GPCL/VBLK
CLK/PCLK
FID PIN function select:
0 = FID (default, if bit 3 is selected to output FID)
1 = Lock indicator (indicates whether the device is locked vertically)
PALI PIN function select:
0 = PALI (default, if bit 2 is selected to output PALI)
1 = Lock indicator (indicates whether the device is locked horizontally)
FID/GLCO function select (also refer to register 03h for enhanced functionality):
0 = FID
1 = GLCO (default)
VSYNC/PALI function select (also refer to register 03h for enhanced functionality):
0 = VSYNC (default)
1 = PALI
INTREQ/GPCL/VBLK function select:
0 = INTREQ (default)
1 = GPCL or VBLK depending on bit 7 of register 03h
CLK/PCLK (pins 42, 61, 84, 103) function select:
0 = CLK at 27 MHz (default)
1 = PCLK (1× pixel clock frequency at 13.5 MHz)
See Figure 9-1 for the relationship between the configuration shared pins.
9.2.17
Active Video Cropping Start Pixel MSB for Unscaled Data Register
Address
11h
Default
00h
7
6
5
4
3
2
1
0
AVID start pixel MSB [9:2]
Active video cropping start pixel MSB [9:2], set this register first before setting register 12h. The TVP5154
decoder updates the AVID start values only when register 12h is written to. This start pixel value is relative
to the default values of the AVID start pixel.
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9.2.18
Active Video Cropping Start Pixel LSB for Unscaled Data Register
Address
12h
Default
00h
7
6
5
4
3
2
Reserved
1
AVID active
0
AVID start pixel LSB [1:0]
AVID active:
0 = AVID out active in VBLK (default)
1 = AVID out inactive in VBLK
AVID start [9:0] (combined registers 11h and 12h):
01 1111 1111 = 511
00 0000 0001 = 1
00 0000 0000 = 0 (default)
11 1111 1111 = – 1
10 0000 0000 = – 512
Active video cropping start pixel LSB [1:0]: The TVP5154 decoder updates the AVID start values only when this register is written to.
9.2.19
Active Video Cropping Stop Pixel MSB LSB for Unscaled Data Register
Address
13h
Default
00h
7
6
5
4
3
2
1
0
AVID stop pixel MSB [9:2]
Active video cropping stop pixel MSB [9:2], set this register first before setting the register 14h. The
TVP5154 decoder updates the AVID stop values only when register 14h is written to. This stop pixel value
is relative to the default values of the AVID stop pixel.
9.2.20
Active Video Cropping Stop Pixel LSB for Unscaled Data Register
Address
14h
Default
00h
7
6
5
4
Reserved
3
2
1
0
AVID stop pixel LSB [1:0]
Active video cropping stop pixel LSB [1:0]: The number of pixels of active video must be an even number.
The TVP5154 decoder updates the AVID stop values only when this register is written to.
AVID stop [9:0] (combined registers 13h and 14h):
01 1111 1111 = 511
00 0000 0001 = 1
00 0000 0000 = 0 (default) (see Figure 4-2) and Figure 4-3)
11 1111 1111 = – 1
10 0000 0000 = – 512
32
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9.2.21
Genlock and RTC Register
Address
15h
Default
01h
7
6
Stable syncs
Reserved
5
4
3
F/V bit control
2
Auto inc
1
0
GLCO/RTC
Stable syncs
0 = Output F and V bits follow the input signal producing fixed vertical blanking periods by adapting the active video.
1 = Output F and V bits produce fixed active video periods by adapting the vertical blanking.
F/V bit control
Table 9-5. F/V Bit Control
BIT 5
0
BIT 4
NUMBER OF LINES
0
0
1
1
0
1
1
F BIT
V BIT
Standard
ITU-R BT.656
ITU-R BT.656
Nonstandard even
Force to 1
Switch at field boundary
Nonstandard odd
Toggles
Switch at field boundary
Standard
ITU-R BT.656
ITU-R BT.656
Nonstandard
Toggles
Switch at field boundary
Standard
ITU-R BT.656
ITU-R BT.656
Nonstandard
Pulse mode
Switch at field boundary
Illegal
Auto inc: When this bit is set to 1, subsequent reading/writing from/to back door registers automatically
increment the address index.
GLCO/RTC: Table 9-6 for different modes.
Table 9-6. GLCO/RTC Control
BIT 2
BIT 1
BIT 0
0
x
0
GLCO
GENLOCK/RTC MODE
0
x
1
RTC output mode 0 (default)
1
x
0
GLCO
1
x
1
RTC output mode 1
All other values are reserved.
Figure 7-1 shows the timing of GLCO and the timing of RTC.
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9.2.22
Horizontal Sync (HSYNC) Start Register
Address
16h
Default
80h
7
6
5
4
3
2
1
0
HSYNC start
HSYNC start:
1111 1111 =
1111 1110 =
1000 0001 =
1000 0000 =
0111 1111 =
0111 1110 =
0000 0000 =
– 127 × 4 pixel clocks
– 126 × 4 pixel clocks
– 1 × 4 pixel clocks
0 pixel clocks (default)
1 × 4 pixel clocks
2 × 4 pixel clocks
128 × 4 pixel clocks
BT.656 EAV Code
YOUT[7:0]
U
Y
V
Y
F
F
0
0
0
0
X
Y
8
0
BT.656 SAV Code
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
U
Y
HSYNC
AVID
128 SCLK
Start of Digital
Active Line
Nhbhs
Nhb
Figure 9-2. Horizontal Sync
Table 9-7. Clock Delays (CLKs)
STANDARD
Nhbhs
Nhb
NTSC
16
272
PAL
20
284
SECAM
40
280
Detailed timing information is also available in Section 4.12, Synchronization Signals.
34
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9.2.23
Ancillary SAV/EAV Control
Address
17h
Default
52h
7
6
5
4
3
2
1
0
Reserved
Scaler PD
Include scale
ancillary
Include scale
SAV
Include scale
EAV
Include unscale
ancillary
Include
unscale SAV
Include unscale
EAV
Include unscaled EAV:
0 = AVID period does not include the EAV sync codes (default).
1 = AVID period includes the EAV sync codes.
Include unscaled SAV:
0 = AVID period does not include the SAV sync codes.
1 = AVID period includes the SAV sync codes (default).
Include unscaled ancillary data:
0 = AVID period includes the ancillary data region (default).
1 = AVID period does not include the ancillary data region.
Include scaled EAV:
0 = AVID period does not include the EAV sync codes (default).
1 = AVID period includes the EAV sync codes.
Include scaled SAV:
0 = AVID period does not include the SAV sync codes.
1 = AVID period includes the SAV sync codes (default).
Include scaled ancillary data:
0 = AVID period includes the ancillary data region (default).
1 = AVID period does not include the ancillary data region.
Scaler PD (scaler power down):
0 = Scaler active
1 = Scaler powered down (default)
Data
SAV
EAV
Pixel Data
ANC
Un−scaled pixel data
AVID
Include SAV = 0, Include EAV = 0,
Include ancillary = 1
AVID
Include SAV = 1, Include EAV = 0,
Include ancillary = 0
AVID
Data
Include SAV = 0, Include EAV = 1,
Include ancillary = 1
SAV
Pixel Data
EAV
ANC
Scaled pixel data, AVID start/stop reduced
AVID
Include SAV = 0, Include EAV = 0,
Include ancillary = 1
AVID
Include SAV = 1, Include EAV = 0,
Include ancillary = 0
AVID
Include SAV = 0, Include EAV = 1,
Include ancillary = 1
Figure 9-3. AVID Behavior When Ancillary Data Present
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Data
SAV
Pixel Data
EAV
Un−scaled pixel data
AVID
Include SAV = 0, Include EAV = 0
AVID
Include SAV = 1, Include EAV = 0
AVID
Include SAV = 0, Include EAV = 1
Data
SAV
0 Data
Pixel Data
EAV
Scaled pixel data, AVID start/stop same as for un−scaled data
AVID
Include SAV = 0, Include EAV = 0
AVID
Include SAV = 1, Include EAV = 0
AVID
Include SAV = 0, Include EAV = 1
Data
SAV
Pixel Data
EAV
Scaled pixel data, AVID start/stop reduced
AVID
Include SAV = 0, Include EAV = 0
AVID
Include SAV = 1, Include EAV = 0
AVID
Include SAV = 0, Include EAV = 1
Figure 9-4. AVID Behavior When No Ancillary Data Present
36
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9.2.24
Vertical Blanking Start Register
Address
18h
Default
00h
7
6
5
4
3
2
1
0
Vertical blanking start
Vertical blanking (VBLK) start:
0111 1111 = 127 lines after start of vertical blanking interval
0000 0001 = 1 line after start of vertical blanking interval
0000 0000 = Same time as start of vertical blanking interval (default) (see Figure 4-1, Figure 4-2, and Figure 4-3)
1111 1111 = 1 line before start of vertical blanking interval
1000 0000 = 128 lines before start of vertical blanking interval
Vertical
register
register
register
9.2.25
blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this
determines the timing of the GPCL/VBLK signal when it is configured to output vertical blank (see
03h). The setting in this register also determines the duration of the luma bypass function (see
07h).
Vertical Blanking Stop Register
Address
19h
Default
00h
7
6
5
4
3
2
1
0
Vertical blanking stop
Vertical blanking (VBLK) stop:
0111 1111 = 127 lines after stop of vertical blanking interval
0000 0001 = 1 line after stop of vertical blanking interval
0000 0000 = Same time as stop of vertical blanking interval (default) (see Figure 4-1, Figure 4-2, and Figure 4-3)
1111 1111 = 1 line before stop of vertical blanking interval
1000 0000 = 128 lines before stop of vertical blanking interval
Vertical
register
register
register
9.2.26
blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this
determines the timing of the GPCL/VBLK signal when it is configured to output vertical blank (see
03h). The setting in this register also determines the duration of the luma bypass function (see
07h).
Chrominance Control #1 Register
Address
1Ah
Default
0Ch
7
6
5
Reserved color
4
3
2
1
PLL reset
Chrominance adaptive comb filter
enable (ACE)
Chrominance comb filter enable
(CE)
0
Automatic color gain control
Color PLL reset:
0 = Color PLL not reset (default)
1 = Color PLL reset
Writing a 1 to this bit resets the color PLL and transmits a 1 in the reset bit of the GLCO output stream.
Chrominance adaptive comb filter enable (ACE):
0 = Disable
1 = Enable (default)
Chrominance comb filter enable (CE):
0 = Disable
1 = Enable (default)
Automatic color gain control (ACGC):
00 = ACGC enabled (default)
01 = Reserved
10 = ACGC disabled
11 = ACGC frozen to the previously set value
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9.2.27
Chrominance Control #2 Register
Address
1Bh
Default
14h
7
6
5
4
Reserved
3
2
Reserved
WCF
1
0
Chrominance filter select
Wideband chroma filter (WCF):
0 = Disable
1 = Enable (default)
Chrominance filter select:
00 = No notch (default)
01 = Notch 1
10 = Notch 2
11 = Notch 3
Chrominance output bandwidth (MHz), see Table 9-8
Table 9-8. Chroma Output Bandwidth Select
WCF
0
1
38
Internal Control Registers
FILTER SELECT
NTSC/PAL/SECAM
ITU-R BT.601
00
1.2214
01
0.8782
10
0.7297
11
0.4986
00
1.4170
01
1.0303
10
0.8438
11
0.5537
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9.2.28
Interrupt Reset Register B
Address
1Ch
Default
00h
7
6
5
4
3
2
1
0
Software
initialization reset
Reserved
Reserved
Field rate
changed reset
Line alternation
changed reset
Color lock
changed reset
H/V lock
changed reset
TV/VCR
changed reset
Interrupt reset register B is used by the external processor to reset the interrupt status bits in interrupt
status register B. Bits loaded with a 1 allow the corresponding interrupt status bit to reset to 0. Bits loaded
with a 0 have no effect on the interrupt status bits.
Software initialization reset:
0 = No effect (default)
1 = Reset software initialization bit
Field rate changed reset:
0 = No effect (default)
1 = Reset field rate changed bit
Line alternation changed reset:
0 = No effect (default)
1 = Reset line alternation changed bit
Color lock changed reset:
0 = No effect (default)
1 = Reset color lock changed bit
H/V lock changed reset:
0 = No effect (default)
1 = Reset H/V lock changed bit
TV/VCR changed reset [TV/VCR mode is determined by counting the total number of lines/frame. The mode switches to VCR for
nonstandard number of lines]:
0 = No effect (default)
1 = Reset TV/VCR changed bit
9.2.29
Interrupt Enable Register B
Address
1Dh
Default
00h
7
6
5
4
3
2
1
0
Software initialization
occurred enable
Reserved
Reserved
Field rate
changed
Line alternation
changed
Color lock
changed
H/V lock
changed
TV/VCR
changed
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Software initialization occurred enable:
0 = Disabled (default)
1 = Enabled
Field rate changed:
0 = Disabled (default)
1 = Enabled
Line alternation changed:
0 = Disabled (default)
1 = Enabled
Color lock changed:
0 = Disabled (default)
1 = Enabled
H/V lock changed:
0 = Disabled (default)
1 = Enabled
TV/VCR changed:
0 = Disabled (default)
1 = Enabled
Interrupt enable register B is used by the external processor to mask unnecessary interrupt sources for
interrupt B. Bits loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the
external pin. Conversely, bits loaded with 0s mask the corresponding interrupt condition from generating
an interrupt on the external pin. This register only affects the external pin; it does not affect the bits in the
interrupt status register. A given condition can set the appropriate bit in the status register and not cause
an interrupt on the external pin. To determine if this device is driving the interrupt pin, either AND interrupt
status register B with interrupt enable register B, or check the state of interrupt B in the interrupt B active
register.
9.2.30
Interrupt Configuration Register B
Address
1Eh
Default
00h
7
6
5
4
Reserved
3
2
1
0
Interrupt polarity B
Interrupt polarity B:
0 = Interrupt B is active low (default).
1 = Interrupt B is active high.
Interrupt polarity B must be same as interrupt polarity A bit at bit 0 of the interrupt configuration register A
at address C2h.
Interrupt configuration register B is used to configure the polarity of interrupt B on the external interrupt
pin. When the interrupt B is configured for active low, the pin is driven low when active and high
impedance when inactive (open drain). Conversely, when the interrupt B is configured for active high, it is
driven high for active and driven low for inactive.
40
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9.2.31
Output Control
Address
1Fh
Default
00h
7
6
5
4
3
2
Bit swap
Ancillary Enable
Parity modifier
SAV/EAV modifier
1
0
Output mode
Output mode:
000 = Mode 0 : Unscaled data clocked by clock 1
001 = Mode 1 : Scaled data clocked by clock 1
010 = Mode 2 : Multiplexed data with separate clocks
011 = Mode 3 : Multiplexed data with clock 1 at 54 MHz
100 = Mode 4 : Unscaled/scaled field toggled data clocked by clock 1
SAV/EAV modifier:
0 = SAV/EAV codes not modified
1 = SAV/EAV MSB modified. MSB = 1 indicates unscaled data, MSB = 0 indicates scaled data
Parity modifier:
0 = Parity calculation includes SAV/EAV MSB.
1 = Parity calculation does not include SAV/EAV MSB.
Ancillary enable:
0 = Ancillary data not enabled
1 = Ancillary data packet added to indicate scaled or unscaled data
Note : Scaled/unscaled ancillary data cannot be enabled at the same time as VBI ancillary data
Bit swap:
0 = chx_out(0) corresponds to data LSB, chx_out(7) corresponds to data MSB
1 = chx_out(0) corresponds to data MSB, chx_out(7) corresponds to data LSB
Table 9-9. Ancillary Data Format and Sequence
BYTE
NO.
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
(LSB)
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
DESCRIPTION
Ancillary data preamble
2
1
1
1
1
1
1
1
1
3
NEP
EP
0
1
DID3
DID2
DID1
DID0
4
1
0
0
0
0
0
0
0
Secondary data ID (SDID)
5
0
1
0
0
0
0
0
1
Number of 32 bit data (NN)
6
Z
Video line # [7:0]
0
0
0
0
8
Internal data ID0 (IDID0)
0
0
Video line # [9:8]
00h
9
1
0
11
1
0
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0
Data
Data byte
00h
0
Internal data ID1 (IDID1)
Data byte
00h
10
Data ID (DID)
0
Check sum
0
0
0
Fill byte
Internal Control Registers
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EP:
Even parity for D0–D5
NEP:
Negated even parity
DID:
For unscaled data D0–D3 taken from EAV DID value for unscaled data stream register low nibble for field 0 and from high nibble
for field 1
For scaled data D0–D3 taken from EAV DID value for scaled data stream register low nibble for field 0 and from high nibble for
field 1
SDID:
Zero data
NN:
Indicates 1 D word of data
IDID0:
Transaction video line number [7:0]
IDID1:
Bit 0/1 = Transaction video line number [9:8]
CS:
Sum of D0–D7 of DID through last data byte
Fill byte:
Fill bytes make a multiple of four bytes from byte 0 to last fill byte. For teletext modes, byte 8 is the sync pattern byte. Byte 9 is
1. Data (the first data byte).
9.2.32
Active Video Cropping Start Pixel MSB for Scaled Data Register
Address
25h
Default
00h
7
6
5
4
3
2
1
0
AVID start pixel MSB [9:2]
Active video cropping start pixel MSB [9:2], set this register first before setting register 26h. The TVP5154
decoder updates the AVID start values only when register 26h is written to. This start pixel value is relative
to the default values of the AVID start pixel.
9.2.33 Active Video Cropping Start Pixel LSB for Scaled Data Register
Address
26h
Default
00h
7
6
5
Reserved
4
3
2
Active
1
0
AVID start pixel LSB [1:0]
AVID active:
0 = AVID out active in VBLK (default)
1 = AVID out inactive in VBLK
Active video cropping start pixel LSB [1:0]: The TVP5154 decoder updates the AVID start values only when this register is written to.
AVID start [9:0]:
01 1111 1111 = 511
00 0000 0001 = 1
00 0000 0000 = 0 (default)
11 1111 1111 = – 1
10 0000 0000 = – 512
42
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9.2.34
Video Standard Register
Address
28h
Default
00h
7
6
5
4
3
2
Reserved
Video standard:
0000 =
0001 =
0010 =
0011 =
0100 =
0101 =
0110 =
0111 =
1000 =
1001 =
1010 =
1011 =
1100 =
1
0
Video standard
Autoswitch mode (default)
Reserved
(M) NTSC ITU-R BT.601
Reserved
(B, G, H, I, N) PAL ITU-R BT.601
Reserved
(M) PAL ITU-R BT.601
Reserved
(Combination-N) PAL ITU-R BT.601
Reserved
NTSC 4.43 ITU-R BT.601
Reserved
SECAM ITU-R BT.601
With the autoswitch code running, the user can force the device to operate in a particular video standard
mode and sample rate by writing the appropriate value into this register.
9.2.35
Active Video Cropping Stop Pixel MSB for Scaled Data Register
Address
29h
Default
00h
7
6
5
4
3
2
1
0
AVID stop pixel MSB [9:2]
Active video cropping stop pixel MSB [9:2], set this register first before setting the register 2Ah. The
TVP5154 decoder updates the AVID stop values only when register 2Ah is written to. This stop pixel value
is relative to the default values of the AVID stop pixel.
9.2.36 Active Video Cropping Stop Pixel LSB for Scaled Data Register
Address
2Ah
Default
00h
7
6
5
4
3
Reserved
AVID stop [9:0]:
01 1111 1111
00 0000 0001
00 0000 0000
11 1111 1111
10 0000 0000
=
=
=
=
=
2
1
0
AVID stop pixel LSB [1:0]
511
1
0 (default) (see Figure 4-1, Figure 4-2, and Figure 4-3)
–1
– 512
Active video cropping stop pixel LSB [1:0]: The number of pixels of active video must be an even number.
The TVP5154 decoder updates the AVID stop values only when this register is written to.
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9.2.37
Address
Cb Gain Factor Register
2Ch
7
6
5
4
3
2
1
0
Cb gain factor
This is a read-only register that provides the gain applied to the Cb in the YCbCr data stream.
9.2.38
Address
Cr Gain Factor Register
2Dh
7
6
5
4
3
2
1
0
Cr gain factor
This is a read-only register that provides the gain applied to the Cr in the YCbCr data stream.
9.2.39
656 Revision Select Register
Address
30h
Default
00h
7
6
5
4
3
2
1
0
656 Rev
656 revision select:
0 = Adheres to ITU-R BT656.4 timing
1 = Adheres to ITU-R BT656.3 timing
9.2.40
MSB of Device ID Register
Address
80h
Default
51h
7
6
5
4
3
2
1
0
2
1
0
2
1
0
MSB of device ID
This register identifies the MSB of the device ID. Value = 0x51.
9.2.41 LSB of Device ID Register
Address
81h
Default
54h
7
6
5
4
3
LSB of device ID
This register identifies the LSB of the device ID. Value = 0x54.
9.2.42 ROM Major Version Register
Address
82h
Default
02h
7
6
5
4
3
ROM major version (1)
(1)
44
This register can contain a number from 0x01 to 0xFF.
Internal Control Registers
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9.2.43
ROM Minor Version Register
Address
83h
Default
00h
7
6
5
4
3
ROM minor
(1)
2
1
0
2
1
0
version (1)
This register can contain a number from 0x01 to 0xFF.
9.2.44
Vertical Line Count MSB Register
Address
84h
7
6
5
4
3
Reserved
Vertical line count MSB
Vertical line count bits [9:8]
9.2.45
Vertical Line Count LSB Register
Address
85h
7
6
5
4
3
2
1
0
Vertical line count LSB
Vertical line count bits [7:0]
Registers 84h and 85h can be read and combined to extract the detected number of lines per frame. This
can be used with nonstandard video signals, such as a VCR in fast-forward or rewind modes, to
synchronize the downstream video circuitry.
9.2.46
Interrupt Status Register B
Address
86h
7
6
5
4
3
2
1
0
Software
initialization
Reserved
Command
ready
Field rate
changed
Line alternation
changed
Color lock
changed
H/V lock
changed
TV/VCR
changed
Software initialization:
0 = Software initialization is not ready (default).
1 = Software initialization is ready.
Command ready:
0 = TVP5154 is not ready to accept a new command (default).
1 = TVP5154 is ready to accept a new command.
Field rate changed:
0 = Field rate has not changed (default).
1 = Field rate has changed.
Line alternation changed:
0 = Line alteration has not changed (default).
1 = Line alternation has changed.
Color lock changed:
0 = Color lock status has not changed (default).
1 = Color lock status has changed.
H/V lock changed:
0 = H/V lock status has not changed (default).
1 = H/V lock status has changed.
TV/VCR changed:
0 = TV/VCR status has not changed (default).
1 = TV/VCR status has changed.
Interrupt status register B is polled by the external processor to determine the interrupt source for interrupt
B. After an interrupt condition is set, it can be reset by writing to the interrupt reset register B at
subaddress 1Ch with a 1 in the appropriate bit.
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9.2.47
Interrupt Active Register B
Address
87h
7
6
5
4
3
2
1
0
Reserved
Interrupt B
Interrupt B:
0 = Interrupt B is not active on the external terminal (default).
1 = Interrupt B is active on the external terminal.
The interrupt active register B is polled by the external processor to determine if interrupt B is active.
9.2.48 Status Register #1
Address
88h
7
6
5
4
3
2
1
0
Peak white
detect status
Line-alternating
status
Field rate
status
Lost lock
detect
Color subcarrier
lock status
Vertical sync
lock status
Horizontal sync
lock status
TV/VCR
status
Peak white detect status:
0 = Peak white is not detected.
1 = Peak white is detected.
Line–alternating status:
0 = Nonline alternating
1 = Line alternating
Field rate status:
0 = 60 Hz
1 = 50 Hz
Lost lock detect:
0 = No lost lock since status register #1 was last read
1 = Lost lock since status register #1 was last read
Color subcarrier lock status:
0 = Color subcarrier is not locked.
1 = Color subcarrier is locked.
Vertical sync lock status:
0 = Vertical sync is not locked.
1 = Vertical sync is locked.
Horizontal sync lock status:
0 = Horizontal sync is not locked.
1 = Horizontal sync is locked.
TV/VCR status. TV mode is determined by detecting standard line-to-line variations and specific chroma SCH phases based on the
standard input video format. VCR mode is determined by detecting variations in the chroma SCH phases compared to the chroma SCH
phases of the standard input video format.
0 = TV
1 = VCR
9.2.49
Address
Status Register #2
89h
7
6
5
4
3
2
Reserved
Weak signal detection
PAL switch polarity
Field sequence status
AGC and offset frozen status
1
0
Reserved
Weak signal detection:
0 = No weak signal
1 = Weak signal mode
PAL switch polarity of first line of odd field:
0 = PAL switch is 0.
1 = PAL switch is 1.
Field sequence status:
0 = Even field
1 = Odd field
AGC and offset frozen status:
0 = AGC and offset are not frozen.
1 = AGC and offset are frozen.
46
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9.2.50
Status Register #3
Address
8Ah
7
6
5
4
3
Front-end AGC gain value (analog and
(1)
2
1
0
2
1
0
digital) (1)
Represents eight bits (MSB) of a 10-bit value
This register provides the front-end AGC gain value of both analog and digital gains.
9.2.51 Status Register #4
Address
8Bh
7
6
5
4
3
Subcarrier to horizontal (SCH) phase
SCH (color PLL subcarrier phase at 50% of the falling edge of horizontal sync of line one of odd field; step size 360°/256):
0000 0000 = 0.00o
0000 0001 = 1.41o
0000 0010 = 2.81o
1111 1110 = 357.2o
1111 1111 = 358.6o
9.2.52
Status Register #5
Address
8Ch
7
6
5
Autoswitch mode
4
3
Reserved
2
1
Video standard
0
Sampling rate
Autoswitch mode:
0 = Stand-alone (forced video standard) mode
1 = Autoswitch mode
This register contains information about the detected video standard and the sampling rate at which the
device is currently operating. When autoswitch code is running, this register must be tested to determine
which video standard has been detected.
Table 9-10. Auto Switch Video Standard
SR (1)
VIDEO STANDARD [3:1]
(1)
VIDEO STANDARD
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
Reserved
0
0
0
1
(M) NTSC ITU-R BT.601
0
0
1
0
Reserved
0
0
1
1
(B, G, H, I, N) PAL ITU-R BT.601
0
1
0
0
Reserved
0
1
0
1
(M) PAL ITU-R BT.601
0
1
1
0
Reserved
0
1
1
1
PAL-N ITU-R BT.601
1
0
0
0
Reserved
1
0
0
1
NTSC 4.43 ITU-R BT.601
1
0
1
0
Reserved
1
0
1
1
SECAM ITU-R BT.601
Sampling rate (SR): 0 = Reserved, 1 = ITU-R BT.601
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9.2.53
Closed Caption Data Registers
Address
90h–93h
Address
7
6
5
4
3
2
90h
Closed caption field 1 byte 1
91h
Closed caption field 1 byte 2
92h
Closed caption field 2 byte 1
93h
Closed caption field 2 byte 2
1
0
These registers contain the closed caption data arranged in bytes per field.
9.2.54
WSS Data Registers
Address
94h–99h
NTSC
abc
Address
7
6
94h
95h
b13
4
3
2
1
0
b4
b3
b2
b1
b0
WSS field 1 byte 1
BYTE
b11
b10
b9
b8
b7
b6
WSS field 1 byte 2
96h
b19
b18
b17
b16
b15
b14
WSS field 1 byte 3
97h
b5
b4
b3
b2
b1
b0
WSS field 2 byte 1
b11
b10
b9
b8
b7
b6
WSS field 2 byte 2
b19
b18
b17
b16
b15
b14
WSS field 2 byte 3
98h
b13
b12
5
b5
b12
99h
These registers contain the wide screen signaling (WSS) data for NTSC.
Bits 0–1 represent word 0, aspect ratio.
Bits 2–5 represent word 1, header code for word 2.
Bits 6–13 represent word 2, copy control.
Bits 14–19 represent word 3, CRC.
PAL/SECAM
abc
Address
7
6
94h
b7
b6
95h
5
3
2
1
0
BYTE
b5
b4
b3
b2
b1
b0
WSS field 1 byte 1
b13
b12
b11
b10
b9
b8
WSS field 1 byte 2
96h
97h
4
Reserved
b7
b6
98h
99h
b5
b4
b3
b2
b1
b0
WSS field 2 byte 1
b13
b12
b11
b10
b9
b8
WSS field 2 byte 2
Reserved
Bits 0–3 represent group 1, aspect ratio.
Bits 4–7 represent group 2, enhanced services.
Bits 8–10 represent group 3, subtitles.
Bits 11–13 represent group 4, others.
48
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9.2.55 VPS Data Registers
Address
9Ah–A6h
Address
7
6
5
4
3
9Ah
VPS byte 1
9Bh
VPS byte 2
9Ch
VPS byte 3
9Dh
VPS byte 4
9Eh
VPS byte 5
9Fh
VPS byte 6
A0h
VPS byte 7
A1h
VPS byte 8
A2h
VPS byte 9
A3h
VPS byte 10
A4h
VPS byte 11
A5h
VPS byte 12
A6h
VPS byte 13
2
1
0
These registers contain the entire VPS data line except the clock run-in code or the start code.
9.2.56 VITC Data Registers
Address
A7h–AFh
Address
7
6
5
4
A7h
3
2
1
0
VITC byte 1, frame byte 1
A8h
VITC byte 2, frame byte 2
A9h
VITC byte 3, seconds byte 1
AAh
VITC byte 4, seconds byte 2
ABh
VITC byte 5, minutes byte 1
ACh
VITC byte 6, minutes byte 2
ADh
VITC byte 7, hour byte 1
AEh
VITC byte 8, hour byte 2
AFh
VITC byte 9, CRC
These registers contain the VITC data.
9.2.57
Address
7
VBI FIFO Read Data Register
B0h
6
5
4
3
2
1
0
FIFO read data
This address is provided to access VBI data in the FIFO through the host port. All forms of teletext data
come directly from the FIFO, while all other forms of VBI data can be programmed to come from the
registers or from the FIFO. Current status of the FIFO can be found at address C6h and the number of
bytes in the FIFO is located at address C7h. If the host port is to be used to read data from the FIFO, the
output formatter must be disabled at address CDh bit 0. The format used for the VBI FIFO is shown in
Section 4.9.
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9.2.58
Teletext Filter and Mask Registers
Address
B1h–BAh
Default
00h
Address
7
6
5
4
3
2
1
B1h
Filter 1 mask 1
Filter 1 pattern 1
B2h
Filter 1 mask 2
Filter 1 pattern 2
B3h
Filter 1 mask 3
Filter 1 pattern 3
B4h
Filter 1 mask 4
Filter 1 pattern 4
B5h
Filter 1 mask 5
Filter 1 pattern 5
B6h
Filter 2 mask 1
Filter 2 pattern 1
B7h
Filter 2 mask 2
Filter 2 pattern 2
B8h
Filter 2 mask 3
Filter 2 pattern 3
B9h
Filter 2 mask 4
Filter 2 pattern 4
BAh
Filter 2 mask 5
Filter 2 pattern 5
0
For an NABTS system, the packet prefix consists of five bytes. Each byte contains four data bits (D[3:0])
interlaced
with
four
Hamming
protection
bits
(H[3:0]):
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D[3]
H[3]
D[2]
H[2]
D[1]
H[1]
D[0]
H[0]
Only the data portion D[3:0] from each byte is applied to a teletext filter function with the corresponding
pattern bits P[3:0] and mask bits M[3:0]. Hamming protection bits are ignored by the filter.
For a WST system (PAL or NTSC), the packet prefix consists of two bytes so that two patterns are used.
Patterns 3, 4, and 5 are ignored.
The mask bits enable filtering using the corresponding bit in the pattern register. For example, a 1 in the
LSB of mask 1 means that the filter module must compare the LSB of nibble 1 in the pattern register to
the first data bit on the transaction. If these match, a true result is returned. A 0 in a bit of mask 1 means
that the filter module must ignore that data bit of the transaction. If all 0s are programmed in the mask bits,
the filter matches all patterns returning a true result (default 00h).
Pattern and mask for each byte and filter are referred as <1,2><P,M><1,2,3,4,5> where:
<1,2> identifies the filter 1 or 2
<P,M> identifies the pattern or mask
<1,2,3,4,5> identifies the byte number
50
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9.2.59 Teletext Filter Control Register
Address
BBh
Default
00h
7
6
5
4
Reserved
3
Filter logic
2
1
0
Mode
TTX filter 2 enable
TTX filter 1 enable
Filter logic: Allows different logic to be applied when combining the decision of filter 1 and filter 2 as follows:
00 = NOR (default)
01 = NAND
10 = OR
11 = AND
Mode:
0 = Teletext WST PAL mode B (2 header bytes) (default)
1 = Teletext NABTS NTSC mode C (5 header bytes)
TTX filter 2 enable:
0 = Disabled (default)
1 = Enabled
TTX filter 1 enable:
0 = Disabled (default)
1 = Enabled
If the filter matches or if the filter mask is all 0s, a true result is returned.
9.2.60
Interrupt Status Register A
Address
C0h
Default
00h
7
6
Lock state interrupt
Lock interrupt
5
4
Reserved
3
2
1
0
FIFO threshold interrupt
Line interrupt
Data interrupt
Lock state interrupt:
0 = TVP5154 is not locked to the video signal (default)
1 = TVP5154 is locked to the video signal.
Lock interrupt:
0 = A transition has not occurred on the lock signal (default).
1 = A transition has occurred on the lock signal.
FIFO threshold interrupt:
0 = The amount of data in the FIFO has not yet crossed the threshold programmed at address C8h (default).
1 = The amount of data in the FIFO has crossed the threshold programmed at address C8h.
Line interrupt:
0 = The video line number has not yet been reached (default).
1 = The video line number programmed in address CAh has occurred.
Data interrupt:
0 = No data is available (default).
1 = VBI data is available either in the FIFO or in the VBI data registers.
The interrupt status register A can be polled by the host processor to determine the source of an interrupt.
After an interrupt condition is set it can be reset by writing to this register with a 1 in the appropriate bit(s).
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9.2.61 Interrupt Enable Register A
Address
C1h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Lock interrupt
enable
Cycle complete
interrupt enable
Bus error
interrupt enable
Reserved
FIFO threshold
interrupt enable
Line interrupt
enable
Data interrupt
enable
Lock interrupt enable:
0 = Disabled (default)
1 = Enabled
Cycle complete interrupt enable:
0 = Disabled (default)
1 = Enabled
Bus error interrupt enable:
0 = Disabled (default)
1 = Enabled
FIFO threshold interrupt enable:
0 = Disabled (default)
1 = Enabled
Line interrupt enable:
0 = Disabled (default)
1 = Enabled
Data interrupt enable:
0 = Disabled (default)
1 = Enabled
The interrupt enable register A is used by the host processor to mask unnecessary interrupt sources. Bits
loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin.
Conversely, bits loaded with a 0 mask the corresponding interrupt condition from generating an interrupt
on the external pin. This register only affects the interrupt on the external terminal, it does not affect the
bits in interrupt status register A. A given condition can set the appropriate bit in the status register and not
cause an interrupt on the external terminal. To determine if this device is driving the interrupt terminal
either perform a logical AND of interrupt status register A with interrupt enable register A, or check the
state of the interrupt A bit in the interrupt configuration register at address C2h.
52
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9.2.62 Interrupt Configuration Register A
Address
C2h
Default
04h
7
6
5
4
3
Reserved
2
1
0
YCbCr enable (VDPOE)
Interrupt A
Interrupt polarity A
YCbCr enable (VDPOE):
0 = YCbCr pins are high impedance.
1 = YCbCr pins are active if other conditions are met (default).
Interrupt A (read only):
0 = Interrupt A is not active on the external pin (default).
1 = Interrupt A is active on the external pin.
Interrupt polarity A:
0 = Interrupt A is active low (default).
1 = Interrupt A is active high.
Interrupt configuration register A is used to configure the polarity of the external interrupt terminal. When
interrupt A is configured as active low, the terminal is driven low when active and high impedance when
inactive (open collector). Conversely, when the terminal is configured as active high, it is driven high when
active and driven low when inactive.
9.2.63 VDP Configuration RAM Register
Address
C3h
C4h
C5h
Default
B8h
1Fh
00h
Address
7
C3h
C4h
C5h
6
5
4
3
2
1
0
Configuration data
RAM address (7:0)
Reserved
RAM address 8
The configuration RAM data is provided to initialize the VDP with initial constants. The configuration RAM
is 512 bytes organized as 32 different configurations of 16 bytes each. The first 12 configurations are
defined for the current VBI standards. An additional two configurations can be used as a custom
programmed mode for unique standards, such as Gemstar.
Address C3h is used to read or write to the RAM. The RAM internal address counter is automatically
incremented with each transaction. Addresses C5h and C4h make up a 9-bit address to load the internal
address counter with a specific start address. This can be used to write a subset of the RAM for only
those standards of interest. Registers D0h–FBh must all be programmed with FFh before writing or
reading the configuration RAM. Full field mode (CFh) must be disabled as well.
The suggested RAM contents are shown in the following table. All values are hexadecimal.
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Index
Address
Reserved
000
WST SECAM
010
Reserved
020
WST PAL B
030
Reserved
040
WST PAL C
050
Reserved
060
WST NTSC
070
Reserved
080
NABTS, NTSC
090
Reserved
0A0
0
1
2
3
4
5
6
7
8
AA
AA
FF
FF
E7
2E
20
26
E6
AA
AA
FF
FF
27
2E
20
2B
AA
AA
FF
FF
E7
2E
20
22
A6
B
C
D
E
F
B4
0E
0
0
0
10
0
72
10
0
0
0
10
0
98
0D
0
0
0
10
0
93
0D
0
0
0
10
0
93
0D
0
0
0
15
0
93
0D
0
0
0
10
0
7B
09
0
0
0
27
0
8C
09
0
0
0
27
0
CD
0F
0
0
0
3A
0
7C
08
0
0
0
39
0
85
08
0
0
0
4C
0
94
08
0
0
0
4C
0
DA
0B
0
0
0
60
0
Reserved
A6
Reserved
AA
AA
FF
FF
27
2E
20
23
69
Reserved
AA
AA
FF
FF
E7
2E
20
22
69
Reserved
0B0
Reserved
0C0
CC, PAL/SECAM
0D0
Reserved
0E0
CC, NTSC
0F0
Reserved
100
WSS, PAL/SECAM
110
Reserved
120
WSS, NTSC C
130
Reserved
140
VITC, PAL/SECAM
150
Reserved
160
VITC, NTSC
170
Reserved
180
VPS, PAL
190
Reserved
1A0
Reserved
Custom 1
1B0
Programmable
Reserved
1C0
Reserved
Custom 2
1D0
Programmable
Internal Control Registers
A
Reserved
NABTS, NTSC–J
54
9
Reserved
AA
AA
FF
FF
A7
2E
20
23
69
Reserved
AA
2A
FF
3F
04
51
6E
02
A6
Reserved
AA
2A
FF
3F
04
51
6E
02
69
Reserved
5B
55
C5
FF
0
71
6E
42
A6
Reserved
38
00
3F
00
0
71
6E
43
69
Reserved
0
0
0
0
0
8F
6D
49
A6
Reserved
0
0
0
0
0
8F
6D
49
AA
AA
FF
FF
BA
CE
2B
0D
69
Reserved
A6
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9.2.64
Address
VDP Status Register
C6h
7
6
5
4
3
2
1
0
FIFO full
error
FIFO empty
TTX available
CC field 1 available
CC field 2
available
WSS available
VPS available
VITC available
The VDP status register indicates whether data is available in either the FIFO or data registers, and status information about the FIFO.
Reading data from the corresponding register does not clear the status flags automatically. These flags are only reset by writing a 1 to the
respective bit. However, bit 6 is updated automatically.
FIFO full error:
0 = No FIFO full error
1 = FIFO was full during a write to FIFO.
The FIFO full error flag is set when the current line of VBI data can not enter the FIFO. For example, if the FIFO has only ten bytes left and
teletext is the current VBI line, the FIFO full error flag is set, but no data is written because the entire teletext line will not fit. However, if the
next VBI line is closed caption requiring only two bytes of data plus the header, this goes into the FIFO (even if the full error flag is set).
FIFO empty:
0 = FIFO is not empty.
1 = FIFO is empty.
TTX available:
0 = Teletext data is not available.
1 = Teletext data is available.
CC field 1 available:
0 = Closed caption data from field 1 is not available.
1 = Closed caption data from field 1 is available.
CC field 2 available:
0 = Closed caption data from field 2 is not available.
1 = Closed caption data from field 2 is available.
WSS available:
0 = WSS data is not available.
1 = WSS data is available.
VPS available
0 = VPS data is not available.
1 = VPS data is available.
VITC available:
0 = VITC data is not available.
1 = VITC data is available.
9.2.65
Address
FIFO Word Count Register
C7h
7
6
5
4
3
2
1
0
1
0
Number of words
This register provides the number of words in the FIFO. One word equals two bytes.
9.2.66
FIFO Interrupt Threshold Register
Address
C8h
Default
80h
7
6
5
4
3
2
Number of words
This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this
value (default 80h). This interrupt must be enabled at address C1h. One word equals two bytes.
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9.2.67 FIFO Reset Register
Address
C9h
Default
00h
7
6
5
4
3
2
1
0
Any data
Writing any data to this register resets the FIFO and clears any data present in both the FIFO and the
VDP registers.
9.2.68
Line Number Interrupt Register
Address
CAh
Default
00h
7
6
Field 1 enable
Field 2 enable
5
4
3
2
1
0
Line number
This register is programmed to trigger an interrupt when the video line number matches this value in bits 5:0. This interrupt must be enabled
at address C1h. The value of 0 or 1 does not generate an interrupt.
Field 1 enable:
0 = Disabled (default)
1 = Enabled
Field 2 enable:
0 = Disabled (default)
1 = Enabled
Line number: (default 00h)
9.2.69
Pixel Alignment Registers
Address
CBh
CCh
Default
4Eh
00h
Address
7
6
5
4
CBh
3
2
1
0
Switch pixel [7:0]
CCh
Reserved
Switch pixel [9:8]
These registers form a 10-bit horizontal pixel position from the falling edge of sync, where the VDP
controller initiates the program from one line standard to the next line standard; for example, the previous
line of teletext to the next line of closed caption. This value must be set so that the switch occurs after the
previous transaction has cleared the delay in the VDP, but early enough to allow the new values to be
programmed before the current settings are required.
9.2.70 FIFO Output Control Register
Address
CDh
Default
01h
7
6
5
4
3
2
1
0
Reserved
Host access enable
I2C
This register is programmed to allow
access to the FIFO or allowing all VDP data to go out the video port.
Host access enable:
0 = Output FIFO data to the video output Y[7:0]
1 = Allow I2C access to the FIFO data (default)
56
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9.2.71 Full Field Enable Register
Address
CFh
Default
00h
7
6
5
4
Reserved
3
2
1
0
Full field enable
This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines in the line mode registers
programmed with FFh are sliced with the definition of register FCh. Values other than FFh in the line mode registers allow a different slice
mode for that particular line.
Full field enable:
0 = Disable full field mode (default)
1 = Enable full field mode
9.2.72
Line Mode Registers
Address
D0h
D1h–FBh
Default
00h
FFh
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Address
58
7
6
5
4
3
D0h
Line 6 Field 1
D1h
Line 6 Field 2
D2h
Line 7 Field 1
D3h
Line 7 Field 2
D4h
Line 8 Field 1
D5h
Line 8 Field 2
D6h
Line 9 Field 1
D7h
Line 9 Field 2
D8h
Line 10 Field 1
D9h
Line 10 Field 2
DAh
Line 11 Field 1
DBh
Line 11 Field 2
DCh
Line 12 Field 1
DDh
Line 12 Field 2
DEh
Line 13 Field 1
DFh
Line 13 Field 2
E0h
Line 14 Field 1
E1h
Line 14 Field 2
E2h
Line 15 Field 1
E3h
Line 15 Field 2
E4h
Line 16 Field 1
E5h
Line 16 Field 2
E6h
Line 17 Field 1
E7h
Line 17 Field 2
E8h
Line 18 Field 1
E9h
Line 18 Field 2
EAh
Line 19 Field 1
EBh
Line 19 Field 2
ECh
Line 20 Field 1
EDh
Line 20 Field 2
EEh
Line 21 Field 1
EFh
Line 21 Field 2
F0h
Line 22 Field 1
F1h
Line 22 Field 2
F2h
Line 23 Field 1
F3h
Line 23 Field 2
F4h
Line 24 Field 1
F5h
Line 24 Field 2
F6h
Line 25 Field 1
F7h
Line 25 Field 2
F8h
Line 26 Field 1
F9h
Line 26 Field 2
FAh
Line 27 Field 1
FBh
Line 27 Field 2
Internal Control Registers
2
1
0
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These registers program the specific VBI standard at a specific line in the video field.
Bit 7:
0 = Disable filtering of null bytes in closed caption modes.
1 = Enable filtering of null bytes in closed caption modes (default).
In teletext modes, bit 7 enables the data filter function for that particular line. If it is set to 0, the data filter passes all data on that line.
Bit 6:
0 = Send VBI data to registers only.
1 = Send VBI data to FIFO and the registers. Teletext data only goes to FIFO. (default)
Bit 5:
0 = Allow VBI data with errors in the FIFO.
1 = Do not allow VBI data with errors in the FIFO (default).
Bit 4:
0 = Do not enable error detection and correction.
1 = Enable error detection and correction (when bits [3:0] = 1 2, 3, and 4 only) (default).
Bits [3:0]:
0000 = WST SECAM
0001 = WST PAL B
0010 = WST PAL C
0011 = WST NTSC
0100 = NABTS NTSC C
0101 = NABTS NTSC D
0110 = CC PAL
0111 = CC NTSC
1000 = WSS PAL
1001 = WSS NTSC
1010 = VITC PAL
1011 = VITC NTSC
1100 = VPS PAL
1101 = Custom 1
1110 = Custom 2
1111 = Active video (VDP off) (default)
A value of FFh in the line mode registers is required for any line to be sliced as part of the full field mode.
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9.2.73 Full Field Mode Register
Address
FCh
Default
7Fh
7
6
5
4
3
2
1
0
Full field mode
This register programs the specific VBI standard for full field mode. It can be any VBI standard. Individual
line settings take priority over the full field register. This allows each VBI line to be programmed
independently but have the remaining lines in full field mode. The full field mode register has the same
definitions as the line mode registers (default 7Fh).
9.2.74 Decoder Write Enable
Address
FEh
Default
0Fh
7
6
5
4
Reserved
3
2
1
0
Decoder 4
Decoder 3
Decoder 2
Decoder 1
This register controls which of the four decoder cores receives I2C write transactions. A 1 in the
corresponding bit position enables the decoder to receive write commands.
Any combination of decoders can be configured to receive write commands, allowing all four decoders to
be programmed concurrently.
9.2.75 Decoder Read Enable
Address
FFh
Default
00h
7
6
5
Reserved
4
3
2
1
0
Decoder 4
Decoder 3
Decoder 2
Decoder 1
This register controls which of the four decoder cores responds to I2C read transactions. A 1 in the
corresponding bit position enables the decoder to respond to read commands.
If more than one decoder is enabled for reading, only the lowest numbered decoder responds. Reads from
multiple decoders at the same time is not possible.
Note that when register 0xFE is written to with any value, register 0xFF is set to 0x00. Likewise, when
register 0xFF is written to with any value, register 0xFE is set to 0x00.
9.3 Indirect Register Definitions
To write to the TVP5154 indirect registers, it is required that the registers be unlocked using a password.
The password prevents undesirable writes into the device at start-up due to power surges, for example.
The following example demonstrates the method for unlocking the indirect registers.
After writing to the desired indirect registers described in the following text, it is recommended that the
device be locked again.
• Unlock the device
1. Write 0x51 to I2C_0x21. //MSB data
2. Write 0x54 to I2C_0x22. //LSB data
3. Write 0xFF to I2C_0x23. //Data address
4. Write 0x04 to I2C_0x24. //Write command
60
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•
Lock the device
1. Write 0x00 to I2C_0x21. //MSB data
2. Write 0x00 to I2C_0x22. //LSB data
3. Write 0xFF to I2C_0x23. //Data address
4. Write 0x04 to I2C_0x24. //Write command
Indirect registers are written to by performing the following I2C transaction:
START : DEVICE_ID_w : 0x21 : DATA_HIGH : STOP
START : DEVICE_ID_w : 0x22 : DATA_LOW : STOP
START : DEVICE_ID_w : 0x23 : ADDRESS_LOW : STOP
START : DEVICE_ID_w : 0x24 : WR_STROBE : STOP
To read from an indirect register, the following I2C transaction should be performed:
START : DEVICE_ID_w : 0x23 : ADDRESS_LOW : STOP
START : DEVICE_ID_w : 0x24 : RD_STROBE : STOP
START : DEVICE_ID_r : 0x21 : data_msb : STOP
START : DEVICE_ID_r : 0x22 : data_lsb : STOP
Where:
DEVICE_ID_w is the selected TVP5154 device ID with the read/write bit (LSB) set to write.
DEVICE_ID_r is the selected TVP5154 device ID with the read/write bit (LSB) set to read.
ADDRESS_LOW is the low byte of the register address.
WR_STROBE is 0x06.
RD_STROBE is 0x05.
Note, the upper byte of the address is not directly used but is replaced by the corresponding STROBE
signal.
Each indirect register is 16 bits wide.
9.3.1
DID Control
Address
36Ah
Default
000h
7
6
5
4
3
Unscaled field 1 DID
15
14
2
1
0
Unscaled field 0 DID
13
Scaled field 1 DID
12
11
10
9
8
Scaled field 0 DID
This register controls the value of the EAV DID bytes for scaled and unscaled data. The value for each
field can be independently set, allowing identification of both which field is being processed and whether
the data comes from the scaled or unscaled channel.
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9.3.2
Misc Control
Address
36Bh
Default
0Ch
7
6
15
14
5
4
3
13
12
11
Clock rate
2
1
10
9
Clock OE
0
Clock edge
8
Scaled blank data
Scaled blank data:
When no active scaled data is available, this value is output during the active video region.
Clock rate:
This register controls various clock modes. Since this register is modified by the device during normal operation, the clock rate bits
should not be modified by the user.
Clock OE:
This register controls various clock modes. Since this register is modified by the device during normal operation, the clock rate bits
should not be modified by the user.
Clock edge:
This register controls various clock modes. Since this register is modified by the device during normal operation, the clock rate bits
should not be modified by the user.
9.3.3
Interleave Field Control 1
Address
36Dh
Default
0h
7
6
5
4
3
2
1
0
11
10
9
8
Reserved
Blank timing
End pixel count[7:0]
15
14
13
12
Field count
End pixel count[9:8]
End pixel count:
Pixel count at which the frame status is updated. Do not change this value.
Blank timing:
0: No timing signals are generated for blank fields.
1: H, V, and F timing generated for blank fields based on unscaled video timing sequences
Field count:
Number of output fields in field interleaved sequence
9.3.4
Interleave Field Control 2
Address
36Eh
Default
0h
7
6
5
Field mode(3)
15
14
13
Field mode(7)
9.3.5
3
2
1
Field mode(1)
12
11
Field mode(6)
0
Field mode(0)
10
9
Field mode(5)
8
Field mode(4)
Interleave Field Control 3
Address
36Fh
Default
0h
7
6
5
14
13
Field mode(11)
15
4
3
12
11
Field mode(10)
Field mode(15)
62
4
Field mode(2)
Internal Control Registers
Field mode(14)
2
1
10
9
Field mode(9)
Field mode(13)
0
Field mode(8)
8
Field mode(12)
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These registers allow the output data stream to toggle between unscaled and scaled data on a field basis.
By setting Field mode[n] appropriately, it is possible to use the available output bandwidth to interleave
unscaled and scaled frames to achieve reduced frame rates, while still maintaining compatibility with
legacy data receivers. These registers can also be used to reduce the frame rate of either unscaled data
or scaled data by disabling fields within the sequence.
A counter automatically moves from Field mode[0] to Field mode[n] where n can be 0 through 15, then
returns back to Field mode[0]. Depending on the value of Field mode[n], either unscaled data, scaled data,
or no data is sent for the current frame.
00 = Unscaled data
01 = Null frame (no SAV/EAV sequence will be generated)
10 = Scaled data
11 = Reserved
The values programmed for registers 3A8h and 3A9h are different for NTSC (also NTSC4.43 and PAL-M)
and for PAL (also PAL-Nc and SECAM).
9.3.6
Vertical Scaling Field 1 Control
Address
3A8h
Default
0h
7
6
5
4
3
2
1
11
10
9
0
V_Field1[7:0]
15
14
13
12
Reserved
8
V_Field1[8]
Vertical scaling initial value in field 1 [8:0]: Initial value of vertical accumulator for field 1
For NTSC:
V_Field1 = (1.5 × V_Field2) – 128
If V_Field 1 is negative, add V_Field2 to V_Field1 and add V_Field2 to V_Field2 until V_Field1 is positive.
For PAL:
V_Field1 = (Vdesired/Vactive) × 256
9.3.7
Vertical Scaling Field 2 Control
Address
3A9h
Default
0h
7
6
5
4
15
14
13
12
3
2
1
11
10
9
0
V_Field2[7:0]
Reserved
8
V_Field2[8]
Vertical scaling initial value in field 2 [8:0]: Initial value of vertical accumulator for field 2
For NTSC:
V_Field2 = (Vdesired/Vactive) × 256
For PAL:
V_Field2 = (1.5 × V_Field1) – 128
If V_Field 2 is negative, add V_Field1 to V_Field2 and add V_Field1 to V_Field1 until V_Field2 is positive.
9.3.8
Scaler Output Active Pixels
Address
3ABh
Default
2D0h
7
6
5
4
3
2
1
0
10
9
8
SCAL_PIXEL[7:0]
15
14
13
12
Reserved
11
SCAL_PIXEL[9:8]
SCAL_PIXEL [9:0]: Scaler active pixel outputs per line
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9.3.9
Vertical Scaling Control
Address
3ACh
Default
2100h
7
6
5
4
3
2
1
10
9
0
VERT_COEF[7:0]
15
14
Reserved
13
12
1
Enable
11
Reserved
8
VERT_COEF[8]
Enabled: Enable vertical and horizontal scaler
0 = Disable scaler (default)
1 = Enable scaler
VERT_COEF [8:0]: Vertical scaling coefficient
VERT_COEF = (Vdesired/Vactive) × 256
9.3.10 Horizontal Scaling Control
Address
3ADh
Default
400h
7
6
5
4
3
2
1
0
10
9
8
HORZ_COEF[7:0]
15
14
Reserved
HORZ_COEF[14:0]:
13
12
11
HORZ_COEF[14:8]
Horizontal scaling coefficient, MSB five bits are integer values and LSB ten bits are fraction numbers.
HORZ_COEF = Hactive/Hdesired
10 Scaler Configuration
10.1 Overview
The TVP5154 contains four independent scalers, one for each video decoder channel. Each scaler is able
to filter and scale both horizontally and vertically to different ratios.
Horizontally, a 7-tap poly-phase filter is used to ensure optimal scaling performance, and can be
configured to scale to any output size below the input resolution, in decrements of two pixels. Vertically a
running average filter is used to filter vertically and can be configured to scale to any output size below the
input resolution.
When scaling horizontally, the output pixels are packed together to allow continuous reading of the pixels.
AVID should be configured so that it qualifies the active pixels, allowing the receiving back end to ignore
nonactive pixels. When scaling vertically, inactive lines are not removed from the output since there is no
internal frame memory. The receiving back end must use AVID to qualify active lines/pixels. AVID can be
configured to be either active or inactive during invalid output lines.
Due to the fact that vertical scaling is performed on a field basis, it is possible that the vertical resolution
will be reduced due to filtering across lines within the field, rather than adjacent lines in the frame. Aliasing
will not occur, but the output image will appear soft vertically. If the desired scaling ration is 0.5, this can
be achieved by simply ignoring every other field. This maintains sharpness, but may introduce aliasing
artifacts.
64
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10.2 Horizontal Scaling
10.2.1 Registers
The horizontal scaler uses a 32-phase polymorphic filter. Excellent performance can be achieved by using
the set of coefficients programmed into the 5154 for all scaling ratios.
It is necessary to program the input and output scaling control registers (3AB and 3AD).
Figure 10-1 shows how data is packed horizontally when scaled.
Unscaled
SAV
EAV
Scaled
SAV
EAV
Figure 10-1. Unscaled and Scaled Pixel Data Alignment
10.3 Vertical Scaling
10.3.1 Registers
The vertical scaler implements a weighted running average filter, which requires the initial weights and the
ratio registers to be configured.
Additionally, it is necessary to program the input and output scaling control registers (3A8, 3A9, and 3AC).
Figure 10-2 shows the active and inactive data lines when scaled vertically.
Unscaled
Un
Line n
SAV
EAV
Line n+1
SAV
EAV
Line n+2
SAV
EAV
Line n+3
SAV
EAV
Line n+4
SAV
EAV
Line n+5
SAV
EAV
Line n+6
SAV
EAV
Line n+7
SAV
EAV
Scaled
Line n
SAV
EAV
Line n+1
SAV
EAV
Line n+3
SAV
EAV
Line n+4
SAV
EAV
Line n+6
SAV
EAV
Line n+7
SAV
EAV
Line n+2
Line n+5
Figure 10-2. Unscaled and Scaled Vertical Data Formatting
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10.4 Field Interleaving
In systems where either there are insufficient video ports on the back end processor to accommodate both
scaled and unscaled video streams, or where the back end processor does not have sufficient processing
power to perform compression on the unscaled image at the same time as other video processing, such
as composting of scaled images for display, it is possible to configure the TVP5154 to output different
image types on consecutive fields. In this configuration, the field rates for each of the scaled and unscaled
images is reduced to accommodate the interleaving of fields, while maintaining a 27-MHz pixel clock.
This is useful in video recording systems that are required to display a scaled image but still wish to
compress and store full resolution images, albeit at reduced field rates.
Field interleaving can generate a sequence of up to 16 fields, where each field can be either unscaled,
scaled, or blank.
10.4.1 Registers
The field loop count register controls how many fields are in the sequence. The field mode registers
control the output field type for each field.
Figure 10-3 shows how to configure field interleaving for a sequence of five fields where the first field is
unscaled, the second field is scaled, the third field is blank, the fourth field is scaled, and the fifth field is
blank.
Field 0
Field 1
Field 2
Field 3
Field 4
Field 0
Field 1
Figure 10-3. Field Interleaving
Various additional registers exist to configure how the TVP5154 indicates to the back-end processor the
state of the current field. The Output Control register 1Fh allows the scaled/unscaled status to be indicated
by the upper bit of the SAV/EAV codes. The Output Control register 1Fh also allows the scaled/unscaled
status to be indicated by the DID codes of ancillary data.
66
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11 Electrical Specifications
Absolute Maximum Ratings (1)
11.1
over operating free-air temperature range (unless otherwise noted)
VALUE
Supply voltage range
IOVDD to DGND
–0.5 to 3.6
DVDD to DGND
– 0.5 to 2
PLL_AVDD to PLL_AGND
–0.5 to 2
AVDD to AGND
–0.5 to 2
V
Digital input voltage range, VI to DGND
–0.5 to 3.6
V
Input voltage range, XIN to PLL_GND
–0.5 to 2
V
Analog input voltage range, AI to AGND
–0.2 to 2
V
Digital output voltage range, VO to DGND
TA
Operating free-air temperature range
Tstg
Storage temperature range
(1)
UNIT
–0.5 to 3.6
V
0 to 70
°C
–65 to 150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
11.2
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
IOVDD
Digital I/O supply voltage
3.0
3.3
3.6
V
DVDD
Digital supply voltage
1.65
1.8
1.95
V
PLL_AVDD
Analog PLL supply voltage
1.65
1.8
1.95
V
AVDD
Analog core supply voltage
1.65
1.8
1.95
V
VI(P–P)
Analog input voltage (ac-coupling necessary)
0.75
V
VIH
Digital input voltage high
VIL
Digital input voltage low
VIH_XIN
XIN input voltage high
VIL_XIN
XIN input voltage low
IOH
High-level output current
2
4
mA
IOL
Low-level output current
–2
–4
mA
IOH_CLK
CLK high-level output current
4
8
mA
IOL_CLK
CLK low-level output current
–4
–8
mA
TA
Operating free-air temperature
11.3
0
0.7 IOVDD
V
0.3 IOVDD
0.7 PLL_AVDD
V
0.3 PLL_AVDD
0
V
70
V
°C
Crystal Specifications
Frequency
Frequency tolerance
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TYP
UNIT
14.31818
MHz
±50
ppm
Electrical Specifications
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11.4
Electrical Characteristics
For typical values: Nominal conditions, TA = 25°C
For minimum/maximum values: Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS (1)
MIN
TYP
MAX
UNIT
DC
I/O digital supply current at 27 MHz
Color bar input
(2)
46
52
mA
I/O digital supply current at 54 MHz
Color bar input
(2)
84
90
mA
Digital supply current
Color bar input
(2)
154
174
mA
IDD(PLL_A) Analog PLL supply current
Color bar input
(2)
20
29
mA
IDD(A)
Analog core supply current
Color bar input
(2)
134
168
mA
PTOT
Total power dissipation, normal mode at 27 MHz
Color bar input
(2)
706
910
mW
Total power dissipation, normal mode at 54 MHz
Color bar input
(2)
832
1050
mW
IDD(IO_D)
IDD(D)
Ci
Input capacitance
(3)
10
VOH
Output voltage high
IOH = 2 mA
VOL
Output voltage low
IOL = –2 mA
VOH_CLK
CLK output voltage high
IOH = 4 mA
VOL_CLK
CLK output voltage low
IOL = –4 mA
IIH
High-level input current
IIL
Low-level input current
0.8
IOVDD
pF
V
0.22
IOVDD
0.8
IOVDD
V
V
0.22
IOVDD
V
VI = VIH
±22
µA
VI = VIL
±22
µA
Analog Processing and ADCs (at FS = 30 MSPS)
Zi
Input impedance, analog video inputs
By design
Ci
Input capacitance, analog video inputs
By design
VI(pp)
Input voltage range (4)
Ccoupling = 0.1 µF
DG
Gain control minimum
DG
Gain control maximum
DNL
DC differential nonlinearity
A/D only
INL
DC integral nonlinearity
A/D only
Fr
Frequency response
6 MHz
SNR
Signal-to-noise ratio
1 MHz, 0.5 VP-P
48
50
NS
Noise spectrum (3)
50% flat field
48
50
dB
DP
Differential phase (3)
Modulated ramp
1.5
deg
DG
Differential gain (3)
Modulated ramp
0.5
%
(1)
(2)
(3)
(4)
68
200
500
kΩ
10
0
0.75
0
pF
V
dB
12
dB
±0.5
±1
LSB
±1
±2.5
LSB
–0.9
–3
dB
dB
Measured with a load of 15 pF.
For typical measurements only
By design, not production tested
The 0.75-V maximum applies to the sync-chroma amplitude, not sync-white. The recommended termination resistors are 37.4 Ω.
Electrical Specifications
Submit Documentation Feedback
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
www.ti.com
SLES163A – MARCH 2006 – REVISED JULY 2006
11.5
Timing Requirements
TEST CONDITIONS (1)
PARAMETER
MIN
Duty cycle SCL
TYP
MAX
50
UNIT
%
t1
CLK high time (at 27 MHz)
13.5
t2
CLK low time (at 27 MHz)
13.5
t3
CLK fall time (at 27 MHz)
90% to 10%
t4
CLK rise time (at 27 MHz)
10% to 90%
t5
Output hold time
t6
Output delay time
t7
Output hold time
t8
Output delay time
t9
Data period
t10
Output hold time
t11
Output delay time
t12
Data period
t13
CLK high time (at 54 MHz)
t14
CLK low time (at 54 MHz)
t15
CLK fall time (at 54 MHz)
90% to 10%
6
ns
t16
CLK rise time (at 54 MHz)
10% to 90%
6
ns
(1)
ns
ns
5
ns
5
ns
10
ns
25
4
ns
ns
16.5
18.5
ns
ns
4
ns
16.5
18.5
ns
ns
3
ns
3
ns
Measured with a load of 15 pF for 27-MHz signals, 25 pF for 54-MHz signals. By design. Timing not production tested.
t1
t2
Negative edge
clock
Positive edge
clock
t3
t4
Data 1
Y/C & Syncs
Data 2
t5
t6
Figure 11-1. Output Modes 0 and 1: Clocks, Video Data, and Sync
t1
t2
SCLK
CLK
t3
Y/C & Syncs
Unscaled Data 1
t4
Scaled Data 1
Unscaled Data 2
Scaled Data 2
t7
t8
t9
t9
Figure 11-2. Output Mode 2: Clocks, Video Data, and Sync
Submit Documentation Feedback
Electrical Specifications
69
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
www.ti.com
SLES163A – MARCH 2006 – REVISED JULY 2006
t13
t14
CLK
t15
Y/C & Syncs
Scaled Data 1
Unscaled Data 1
t16
Unscaled Data 2
Scaled Data 2
t10
t11
t12
t12
Figure 11-3. Output Mode 3: Clock, Video Data, and Sync (Positive Edge Clock)
70
Electrical Specifications
Submit Documentation Feedback
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
www.ti.com
SLES163A – MARCH 2006 – REVISED JULY 2006
11.6 I2C Host Port Timing
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
t1
Bus free time, between STOP and START
1.3
µs
t2
Setup time, (repeated) START condition
0.6
µs
t3
Hold time, (repeated) START condition
0.6
µs
t4
Setup time, STOP condition
0.6
ns
t5
Data setup time
100
t6
Data hold time
t7
Rise time, VC1(SDA) and VC0(SCL) signal
t8
Cb
fI2C
I2C clock frequency
ns
0.9
µs
Specified by design
250
ns
Fall time, VC1(SDA) and VC0(SCL) signal
Specified by design
250
ns
Capacitive load for each bus line
Specified by design
400
pF
400
kHz
0
Stop Start
VC1
(SDA)
Stop
Data
t1
t3
t7
t3
t5
t6
t8
t2
t4
VC0
(SCL)
Figure 11-4. I2C Host Port Timing
Submit Documentation Feedback
Electrical Specifications
71
A
B
1
37.4
R
37.4
R
37.4
R
37.4
R
R
37.4
R
37.4
R
37.4
R
37.4
CH4_A
CH3_A
CH2_A
CH1_A
CH4_B IN
CH3_B IN
CH2_B IN
CH1_B IN
I2CA0
R
10k
2
R
10k
IOVDD
I2CA1
R
10k
2
R
10k
IOVDD
2-3 Base Addr 0xB8 - Default
I2C ADDRESS SELECTION
CH4_A IN
CH3_A IN
CH2_A IN
CH1_A IN
1
3
C
C
0.1uF
C
0.1uF
REMEMBER 75ohm TERMINATION
FOR 0-0.75V INPUT RANGE
INPUT V DIVIDER NETWORK
C
0.1uF
DVDD
1
3
D
C
0.1uF
PLL_VDD
C
0.1uF
C
0.1uF
37.4
R
37.4
R
37.4
R
37.4
R
C
0.1uF
C
0.1uF
2
R
37.4
R
37.4
R
37.4
R
37.4
CH4_B
CH3_B
CH2_B
CH1_B
C
0.1uF
C
0.1uF
TMS
R
10k
R
100
IOVDD
C
CH1_B
0.1uF
0.1uF
C
CH2_B
0.1uF
0.1uF
C
CH3_B
0.1uF
0.1uF
0.1uF
0.1uF
C
C
CH4_A
CH4_B
REFM4
REFP4
C
CH3_A
REFM3
REFP3
C
CH2_A
REFM2
REFP2
C
CH1_A
C
1uF
PLL_VDD
AVDD
REFM1
C
0.1uF
1uF
C
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C
1uF
TVP5154PNP
AI1GND
AI1A
AI1B
PLL_VDD
PLL_GND
REFM2
REFP2
AVDD
AGND
AI2GND
AI2A
AI2B
PLL_VDD
PLL_GND
AVDD
AGND
REFM3
REFP3
AVDD
AGND
AI3GND
AI3A
AI3B
PLL_VDD
PLL_GND
REFM4
REFP4
AVDD
AGND
AI4GND
AI4A
AI4B
U1
XIN/OSC
CL1 = CL2 = 2CL CSTRAY
CL1
R
100k
Y4
14.31818MHz
TMS
C
0.1uF
C
1uF
REFM2
3
1uF
C
REFP2
2
CL2
DVDD
IOVDD
C
1uF
C
1uF
REFM3
IOVDD
1uF
C
REFP3
AVDD
REFP1
XOUT
REFP1
REFM1
XIN/OSC
XOUT
PDN
/RESET
SCL
SDA
I2CA0
I2CA1
4
C
1uF
4
C
1uF
IOGND
VSYNC1/PALI1
FID1/GLCO1
CH2OUT0
CH2OUT1
CH2OUT2
CH2OUT3
CH2OUT4
CH2OUT5
CH2OUT6
CH2OUT7
SCLK2
CLK2
INT2/GPCL2/VBLK2
DGND
DVDD
IOVDD
IOGND
AVID2
HSYNC2
VSYNC2/PALI2
FID2/GLCO2
CH3OUT0
CH3OUT1
CH3OUT2
CH3OUT3
CH3OUT4
CH3OUT5
CH3OUT6
CH3OUT7
DGND
DVDD
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
AGND
AVDD
REFP1
REFM1
XIN/OSC
XOUT
PDN
RESETB
SCL
SDA
I2CA0
I2CA1
DGND
DVDD
IOVDD
IOGND
CH1OUT0
CH1OUT1
CH1OUT2
CH1OUT3
CH1OUT4
CH1OUT5
CH1OUT6
CH1OUT7
SCLK1
CLK1
INT1/GPCL1/VBLK1
AVID1
HSYNC1
DGND
DVDD
IODVDD
PLL_VDD
PLL_GND
AGND
TMS
FID4/GLCO4
VSYNC4/PALI4
HSYNC4
AVID4
INT4/GPCL4/VBLK4
CLK4
SCLK4
IOGND
IOVDD
DVDD
DGND
CH4OUT7
CH4OUT6
CH4OUT5
CH4OUT4
CH4OUT3
CH4OUT2
CH4OUT1
CH4OUT0
FID3/GLCO3
VSYNC3/PALI3
HSYNC3
AVID3
INT4/GPCL4/VBLK4
CLK3
SCLK3
IOGND
IOVDD
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Schematic
REFM4
72
1uF
C
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
REFP4
1
C
1uF
CH4_D0
CH4_D1
CH4_D2
CH4_D3
CH4_D4
CH4_D5
CH4_D6
CH4_D7
CH3_D0
CH3_D1
CH3_D2
CH3_D3
CH3_D4
CH3_D5
CH3_D6
CH3_D7
CH2_D0
CH2_D1
CH2_D2
CH2_D3
CH2_D4
CH2_D5
CH2_D6
CH2_D7
CH1_D0
CH1_D1
CH1_D2
CH1_D3
CH1_D4
CH1_D5
CH1_D6
CH1_D7
SCLK4
CLK4
GPCL4/VBLK4
AVID4
HSYNC4
VSYNC4/PALI4
FID4/GLCO4
SCLK3
CLK3
GPCL3/VBLK3
AVID3
HSYNC3
VSYNC3/PALI3
FID3/GLCO3
AVID2
HSYNC2
VSYNC2/PALI2
FID2/GLCO2
SCLK2
CLK2
GPCL2/VBLK2
SCLK1
CLK1
GPCL1/VBLK1
AVID1
HSYNC1
VSYNC1/PALI1
FID1/GLCO1
5
5
Scale
Size
C
FCSM No.
TVP5154
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
RPACK8-33
Sheet
/RESET
SDA
SCL
SCK4
CK4
VB4
AV4
HS4
VS4
FID4
RPACK8-33
CH4_OUT0
CH4_OUT1
CH4_OUT2
CH4_OUT3
CH4_OUT4
CH4_OUT5
CH4_OUT6
CH4_OUT7
RPACK8-33
SCK3
CK3
VB3
AV3
HS3
VS3
FID3
RPACK8-33
CH3_OUT0
CH3_OUT1
CH3_OUT2
CH3_OUT3
CH3_OUT4
CH3_OUT5
CH3_OUT6
CH3_OUT7
RPACK8-33
SCK2
CK2
VB2
AV2
HS2
VS2
FID2
RPACK8-33
CH2_OUT0
CH2_OUT1
CH2_OUT2
CH2_OUT3
CH2_OUT4
CH2_OUT5
CH2_OUT6
CH2_OUT7
RPACK8-33
SCK1
CK1
VB1
AV1
HS1
VS1
FID1
RPACK8-33
CH1_OUT0
CH1_OUT1
CH1_OUT2
CH1_OUT3
CH1_OUT4
CH1_OUT5
CH1_OUT6
CH1_OUT7
DWG No.
SCLK4
CLK4
GPCL4/VBLK4
AVID4
HSYNC4
VSYNC4/PALI4
FID4/GLCO4
CH4_D0
CH4_D1
CH4_D2
CH4_D3
CH4_D4
CH4_D5
CH4_D6
CH4_D7
SCLK3
CLK3
GPCL3/VBLK3
AVID3
HSYNC3
VSYNC3/PALI3
FID3/GLCO3
CH3_D0
CH3_D1
CH3_D2
CH3_D3
CH3_D4
CH3_D5
CH3_D6
CH3_D7
SCLK2
CLK2
GPCL2/VBLK2
AVID2
HSYNC2
VSYNC2/PALI2
FID2/GLCO2
CH2_D0
CH2_D1
CH2_D2
CH2_D3
CH2_D4
CH2_D5
CH2_D6
CH2_D7
SCLK1
CLK1
GPCL1/VBLK1
AVID1
HSYNC1
VSYNC1/PALI1
FID1/GLCO1
CH1_D0
CH1_D1
CH1_D2
CH1_D3
CH1_D4
CH1_D5
CH1_D6
CH1_D7
6
2 of 17
/RESET
SDA
SCL
SCK4
CK4
VB4
AV4
HS4
VS4
FID4
CH4_OUT[7..0]
SCK3
CK3
VB3
AV3
HS3
VS3
FID3
CH3_OUT[7..0]
SCK2
CK2
VB2
AV2
HS2
VS2
FID2
CH2_OUT[7..0]
SCK1
CK1
VB1
AV1
HS1
VS1
FID1
CH1_OUT[7..0]
6
Rev
1
CH4_OUT[7..0]
CH3_OUT[7..0]
CH2_OUT[7..0]
CH1_OUT[7..0]
A
B
C
D
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
www.ti.com
12 Schematic
Submit Documentation Feedback
www.ti.com
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
13 MECHANICAL
Submit Documentation Feedback
MECHANICAL
73
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
www.ti.com
SLES163A – MARCH 2006 – REVISED JULY 2006
74
MECHANICAL
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TVP5154PNP
NRND
HTQFP
PNP
128
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
TVP5154
TVP5154PNPR
NRND
HTQFP
PNP
128
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
TVP5154
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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