10Base-T/100Base-TX Physical Layer Transceiver

10Base-T/100Base-TX Physical Layer Transceiver

KSZ8051MNLU/KSZ8051RNLU

10Base-T/100Base-TX

Physical Layer Transceiver

Data Sheet Rev. 1.0

General Description

The KSZ8051 is an AEC-Q100 standard qualified singlesupply 10Base-T/100Base-TX Ethernet physical-layer transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair (UTP) cable for automotive applications.

The KSZ8051 is a highly-integrated PHY solution. It reduces board cost and simplifies board layout by using on-chip termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core.

The KSZ8051MNLU offers the Media Independent Interface

(MII) and the KSZ8051RNLU offers the Reduced Media

Independent Interface (RMII) for direct connection with

MII/RMII-compliant Ethernet MAC processors and switches.

A 25MHz crystal is used to generate all required clocks, including the 50MHz RMII reference clock output for the

KSZ8051RNLU.

The KSZ8051 provides diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ8051 I/Os and the board. Micrel LinkMD

®

TDR-based cable diagnostics identify faulty copper cabling.

The KSZ8051MNLU and KSZ8051RNLU are available in

32-pin, lead-free QFN packages (see “ Ordering

Information ”).

Data sheets and support documentation are available on

Micrel’s web site at: www.micrel.com

.

Features

• Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet transceiver

• AEC-Q100 qualified for automotive applications

• MII interface support (KSZ8051MNLU)

• RMII v1.2 Interface support with a 50MHz reference clock output to MAC, and an option to input a 50MHz reference clock (KSZ8051RNLU)

• Back-to-back mode support for a 100Mbps copper repeater

• MDC/MDIO management interface for PHY register configuration

• Programmable interrupt output

• LED outputs for link, activity, and speed status indication

• On-chip termination resistors for the differential pairs

• Baseline wander correction

• HP Auto MDI/MDI-X to reliably detect and correct straight-through and crossover cable connections with disable and enable option

• Auto-negotiation to automatically select the highest linkup speed (10/100Mbps) and duplex (half/full)

• Power-down and power-saving modes

• LinkMD TDR-based cable diagnostics to identify faulty copper cabling

• Parametric NAND Tree support for fault detection between chip I/Os and the board

Functional Diagram

LinkMD is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (

408

) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

February, 17 2013

Revision 1.0

Micrel, Inc.

Features (Continued)

• Loopback modes for diagnostics

• Single 3.3V power supply with VDD I/O options for

1.8V, 2.5V, or 3.3V

• Built-in 1.2V regulator for core

• 32-pin (5mm x 5mm)

QFN package

Ordering Information

Applications

• Automotive (throughout vehicle)

Part Number

KSZ8051MNLU

KSZ8051RNLU

(1)

(1)

Temperature

Range

Package

Lead

Finish

−40°C to 85°C

32-Pin QFN Pb-Free

−40°C to 85°C

32-Pin QFN Pb-Free

Note:

1. Contact factory for lead time.

Wire

Bonding

KSZ8051MNLU/KSZ8051RNLU

Description

MII, Automotive Qualified Device

RMII, Automotive Qualified Device

February 17, 2013 2 Revision 1.0

Micrel, Inc.

Revision History

Revision

0.1

0.2

1.0

Date

7/6/12

7/9/12

2/17/13

KSZ8051MNLU/KSZ8051RNLU

Summary of Changes

Initial Release

Added AEC-Q100 qualified to General Description and Features on page 1.

General upgrade to align to KSZ8081 DS. Loopback details added.

February 17, 2013 3 Revision 1.0

Micrel, Inc.

Contents

KSZ8051MNLU/KSZ8051RNLU

General Description ................................................................................................................................................................ 1

Features .................................................................................................................................................................................. 1

Functional Diagram ................................................................................................................................................................. 1

Features (Continued) .............................................................................................................................................................. 2

Applications ............................................................................................................................................................................. 2

Ordering Information ............................................................................................................................................................... 2

Revision History ...................................................................................................................................................................... 3

Contents .................................................................................................................................................................................. 4

List of Figures .......................................................................................................................................................................... 6

List of Tables ........................................................................................................................................................................... 7

Pin Configuration– KSZ8051MNLU ........................................................................................................................................ 8

Pin Description– KSZ8051MNLU ............................................................................................................................................ 9

Strapping Options – KSZ8051MNLU .................................................................................................................................... 12

Pin Configuration – KSZ8051RNLU ...................................................................................................................................... 13

Pin Description– KSZ8051RNLU .......................................................................................................................................... 14

Strapping Options – KSZ8051RNLU .................................................................................................................................... 17

Functional Description: 10Base-T/100Base-TX Transceiver ................................................................................................ 18

100Base-TX Transmit .......................................................................................................................................................................... 18

100Base-TX Receive ........................................................................................................................................................................... 18

Scrambler/De-Scrambler (100Base-TX Only)...................................................................................................................................... 18

10Base-T Transmit .............................................................................................................................................................................. 18

10Base-T Receive ............................................................................................................................................................................... 19

SQE and Jabber Function (10Base-T Only) ........................................................................................................................................ 19

PLL Clock Synthesizer ........................................................................................................................................................................ 19

Auto-Negotiation .................................................................................................................................................................................. 19

MII Interface (KSZ8051MNLU only) ...................................................................................................................................... 20

MII Signal Definition ............................................................................................................................................................................. 20

MII Signal Diagram .............................................................................................................................................................................. 22

RMII Data Interface (KSZ8051RNLU only) ........................................................................................................................... 23

RMII – 25MHz Clock Mode .................................................................................................................................................................. 23

RMII – 50MHz Clock Mode .................................................................................................................................................................. 23

RMII Signal Definition .......................................................................................................................................................................... 23

RMII Signal Diagram ........................................................................................................................................................................... 25

Back-to-Back Mode – 100Mbps Copper Repeater ............................................................................................................... 26

MII Back-to-Back Mode (KSZ8051MNLU only) ................................................................................................................................... 26

RMII Back-to-Back Mode (KSZ8051RNLU only) ................................................................................................................................. 27

MII Management (MIIM) Interface ......................................................................................................................................... 27

Interrupt (INTRP) ................................................................................................................................................................... 28

HP Auto MDI/MDI-X .............................................................................................................................................................. 28

Straight Cable ...................................................................................................................................................................................... 28

February 17, 2013 4 Revision 1.0

Micrel, Inc. KSZ8051MNLU/KSZ8051RNLU

Crossover Cable .................................................................................................................................................................................. 29

Loopback Mode ..................................................................................................................................................................... 30

Local (Digital) Loopback ...................................................................................................................................................................... 30

Remote (Analog) Loopback ................................................................................................................................................................. 30

LinkMD

®

Cable Diagnostic .................................................................................................................................................... 31

NAND Tree Support .............................................................................................................................................................. 31

NAND Tree I/O Testing ....................................................................................................................................................................... 33

Power Management .............................................................................................................................................................. 34

Power-Saving Mode ............................................................................................................................................................................ 34

Energy-Detect Power-Down Mode ...................................................................................................................................................... 34

Power-Down Mode .............................................................................................................................................................................. 34

Slow-Oscillator Mode ........................................................................................................................................................................... 34

Reference Circuit for Power and Ground Connections ......................................................................................................... 35

Typical Current/Power Consumption .................................................................................................................................... 36

Transceiver (3.3V), Digital I/Os (3.3V) ................................................................................................................................................. 36

Transceiver (3.3V), Digital I/Os (2.5V) ................................................................................................................................................. 36

Transceiver (3.3V), Digital I/Os (1.8V) ................................................................................................................................................. 37

Register Map ......................................................................................................................................................................... 38

Register Description .............................................................................................................................................................. 39

Absolute Maximum Ratings

(1)

................................................................................................................................................ 48

Operating Ratings

(2)

.............................................................................................................................................................. 48

Electrical Characteristics

(3)

.................................................................................................................................................... 48

Timing Diagrams ................................................................................................................................................................... 50

MII SQE Timing (10Base-T) ................................................................................................................................................................ 50

MII Transmit Timing (10Base-T) .......................................................................................................................................................... 51

MII Receive Timing (10Base-T) ........................................................................................................................................................... 52

MII Transmit Timing (100Base-TX) ...................................................................................................................................................... 53

MII Receive Timing (100Base-TX) ....................................................................................................................................................... 54

RMII Timing ......................................................................................................................................................................................... 55

Auto-Negotiation Timing ...................................................................................................................................................................... 56

MDC/MDIO Timing .............................................................................................................................................................................. 57

Power-Up/Reset Timing ...................................................................................................................................................................... 58

Reset Circuit .......................................................................................................................................................................... 59

Reference Circuits – LED Strap-In Pins ................................................................................................................................ 60

Reference Clock – Connection and Selection ...................................................................................................................... 61

Magnetics – Connection and Selection ................................................................................................................................. 62

Recommended Land Pattern ................................................................................................................................................ 64

Package Information

(1)

.......................................................................................................................................................... 65

February 17, 2013 5 Revision 1.0

Micrel, Inc. KSZ8051MNLU/KSZ8051RNLU

List of Figures

Figure 1. Auto-Negotiation Flow Chart ................................................................................................................................. 20

Figure 2. KSZ8051MNLU MII Interface ................................................................................................................................ 22

Figure 3. KSZ8051RNLU RMII Interface (25MHz Clock Mode) .......................................................................................... 25

Figure 4. KSZ8051RNLU RMII Interface (50MHz Clock Mode) .......................................................................................... 25

Figure 5. KSZ8051MNLU/RNLU to KSZ8051MNLU/RNLU Back-to-Back Copper Repeater ............................................. 26

Figure 6. Typical Straight Cable Connection ....................................................................................................................... 29

Figure 7. Typical Crossover Cable Connection ................................................................................................................... 29

Figure 8. Local (Digital) Loopback ....................................................................................................................................... 30

Figure 9. Remote (Analog) Loopback .................................................................................................................................. 31

Figure 10. KSZ8051MNLU/RNLU Power and Ground Connections ................................................................................... 35

Figure 11. MII SQE Timing (10Base-T) ............................................................................................................................... 50

Figure 12. MII Transmit Timing (10Base-T) ......................................................................................................................... 51

Figure 13. MII Receive Timing (10Base-T) .......................................................................................................................... 52

Figure 14. MII Transmit Timing (100Base-TX) ..................................................................................................................... 53

Figure 15. MII Receive Timing (100Base-TX) ...................................................................................................................... 54

Figure 16. RMII Timing – Data Received from RMII ............................................................................................................ 55

Figure 17. RMII Timing – Data Input to RMII ....................................................................................................................... 55

Figure 18. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 56

Figure 19. MDC/MDIO Timing .............................................................................................................................................. 57

Figure 20. Power-Up/Reset Timing ...................................................................................................................................... 58

Figure 21. Recommended Reset Circuit .............................................................................................................................. 59

Figure 22. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ..................................................... 59

Figure 23. Reference Circuits for LED Strapping Pins......................................................................................................... 60

Figure 24. 25MHz Crystal/Oscillator Reference Clock Connection ..................................................................................... 61

Figure 25. 50MHz Oscillator Reference Clock Connection ................................................................................................. 61

Figure 26. Typical Magnetic Interface Circuit ....................................................................................................................... 62

Figure 27. Recommended Land Pattern, 32-Pin (5mm x 5mm) QFN ................................................................................. 64

February 17, 2013 6 Revision 1.0

Micrel, Inc. KSZ8051MNLU/KSZ8051RNLU

List of Tables

Table 1. MII Signal Definition ............................................................................................................................................... 21

Table 2. RMII Signal Definition ............................................................................................................................................. 23

Table 3. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater) ............................................ 26

Table 4. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater) ...................................... 27

Table 5. MII Management Frame Format for the KSZ8051MNLU/RNLU ............................................................................ 28

Table 6. MDI/MDI-X Pin Definition ....................................................................................................................................... 28

Table 7. NAND Tree Test Pin Order for KSZ8051MNLU .................................................................................................... 32

Table 8. NAND Tree Test Pin Order for KSZ8051RNLU ..................................................................................................... 33

Table 9. KSZ8051MNLU/RNLU Power Pin Description ...................................................................................................... 35

Table 10. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V) .......................................................... 36

Table 11. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V) .......................................................... 36

Table 12. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V) .......................................................... 37

Table 13. MII SQE Timing (10Base-T) Parameters ............................................................................................................. 50

Table 14. MII Transmit Timing (10Base-T) Parameters ...................................................................................................... 51

Table 15. MII Receive Timing (10Base-T) Parameters........................................................................................................ 52

Table 16. MII Transmit Timing (100Base-TX) Parameters .................................................................................................. 53

Table 17. MII Receive Timing (100Base-TX) Parameters ................................................................................................... 54

Table 18. RMII Timing Parameters – KSZ8051RNLU (25MHz input to XI pin, 50MHz output from REF_CLK pin) ........... 55

Table 19. RMII Timing Parameters – KSZ8051RNLU (50MHz input to XI pin) ................................................................... 55

Table 20. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ............................................................................... 56

Table 21. MDC/MDIO Timing Parameters ........................................................................................................................... 57

Table 22. Power-Up/Reset Timing Parameters ................................................................................................................... 58

Table 23. 25MHz Crystal / Reference Clock Selection Criteria ........................................................................................... 61

Table 24. 50MHz Oscillator / Reference Clock Selection Criteria ....................................................................................... 61

Table 25. Magnetics Selection Criteria ................................................................................................................................ 63

Table 26. Compatible Single-Port 10/100 Magnetics........................................................................................................... 63

February 17, 2013 7 Revision 1.0

Micrel, Inc.

Pin Configuration– KSZ8051MNLU

KSZ8051MNLU/KSZ8051RNLU

32-Pin (5mm x 5mm) QFN

February 17, 2013 8 Revision 1.0

3

4

5

6

7

8

Micrel, Inc.

Pin Description– KSZ8051MNLU

Pin Number Pin Name Type

(1)

Pin Function

1

2

GND

VDD_1.2

9

10

11

12

13

14

15

16

17

18

19

VDDA_3.3

RXM

RXP

TXM

TXP

XO

XI

REXT

MDIO

MDC

RXD3/

PHYAD0

RXD2/

PHYAD1

RXD1/

PHYAD2

RXD0/

DUPLEX

VDDIO

RXDV/

CONFIG2

RXC/

B-CAST_OFF

KSZ8051MNLU/KSZ8051RNLU

Gnd

P

P

I/O

I/O

I/O

I/O

O

I

Ground

1.2V core V

DD

(power supplied by KSZ8051MNLU)

Decouple with 2.2µF and 0.1µF capacitors to ground.

3.3V analog V

DD

Physical receive or transmit signal (

− differential)

Physical receive or transmit signal (+ differential)

Physical transmit or receive signal (

− differential)

Physical transmit or receive signal (+ differential)

Crystal feedback for 25MHz crystal

This pin is a no connect if an oscillator or external clock source is used.

Crystal / Oscillator / External Clock input

25MHz ±50ppm

I Set PHY transmit output current

Connect a 6.49kΩ resistor to ground on this pin.

Ipu/Opu Management Interface (MII) Data I/O

This pin has a weak pull-up, is open-drain, and requires an external 1.0kΩ pull-up resistor.

Ipu

Ipu/O

Management Interface (MII) Clock input

This clock pin is synchronous to the MDIO data pin.

MII mode: MII Receive Data Output[3]

(2)

Ipd/O

Ipd/O

Config mode: The pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of reset.

See the “ Strapping Options ” section for details.

MII Receive Data Output[2]

(2)

MII mode:

Config mode: The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of reset.

MII mode:

See the “ Strapping Options ” section for details.

MII Receive Data Output[1]

(2)

Ipu/O

P

Ipd/O

Ipd/O

Config mode: The pull-up/pull-down value is latched as PHYADDR[2] at the de-assertion of reset.

MII mode:

See the “ Strapping Options ” section for details.

MII Receive Data Output[0]

(2)

Config mode: The pull-up/pull-down value is latched as DUPLEX at the de-assertion of reset.

See the “ Strapping Options ” section for details.

3.3V, 2.5V, or 1.8V digital V

DD

MII mode: MII Receive Data Valid output

Config mode: The pull-up/pull-down value is latched as CONFIG2 at the de-assertion of reset.

MII mode:

See the “ Strapping Options ” section for details.

MII Receive Clock output

Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the de-assertion of reset.

See the “ Strapping Options ” section for details.

February 17, 2013 9 Revision 1.0

21

22

23

24

25

26

27

28

Micrel, Inc.

Pin Number

20

Pin Name

RXER/

ISO

29

30

INTRP/

NAND_Tree#

TXC

TXEN

TXD0

TXD1

TXD2

TXD3

COL/

CONFIG0

CRS/

CONFIG1

LED0/

NWAYEN

KSZ8051MNLU/KSZ8051RNLU

Type

(1)

Pin Function

Ipd/O MII mode: MII Receive Error output

Config mode: The pull-up/pull-down value is latched as ISOLATE at the de-assertion of reset.

See the “ Strapping Options ” section for details.

Ipu/Opu Interrupt output: Programmable interrupt output

This pin has a weak pull-up, is open-drain, and requires an external 1.0kΩ pull-up resistor.

Config mode: The pull-up/pull-down value is latched as NAND Tree# at the de-assertion of reset.

See the “ Strapping Options ” section for details

I/O MII mode:

MII back-to-back mode:

MII Transmit Clock output

MII Transmit Clock input

I

I

I

I

I

MII mode:

MII mode:

MII mode:

MII mode:

MII Mode:

MII Transmit Enable input

MII Transmit Data Input[0]

(3)

MII Transmit Data Input[1]

(3)

MII Transmit Data Input[2]

(3)

MII Transmit Data Input[3]

(3)

Ipd/O

Ipd/O

Ipu/O

MII mode: MII Collision Detect output

Config mode: The pull-up/pull-down value is latched as CONFIG0 at the de-assertion of reset.

See the “ Strapping Options ” section for details.

MII mode: MII Carrier Sense output

Config mode: The pull-up/pull-down value is latched as CONFIG1 at the de-assertion of reset.

LED output:

See the “ Strapping Options ” section for details.

Programmable LED0 output

Config mode: Latched as auto-negotiation enable (register 0h, bit [12]) at the de-assertion of reset.

See the “ Strapping Options ” section for details.

The LED0 pin is programmable using register 1Fh bits [5:4], and is defined as follows.

LED mode = [00]

Link/Activity

No link

Link

Activity

Pin State

High

Low

Toggle

LED mode = [01]

Link Pin State

No link

Link

High

Low

LED mode = [10], [11]

Reserved

LED Definition

OFF

ON

Blinking

LED Definition

OFF

ON

February 17, 2013 10 Revision 1.0

Micrel, Inc.

Pin Number

KSZ8051MNLU/KSZ8051RNLU

31

Pin Name

LED1/

SPEED

Type

(1)

Pin Function

Ipu/O LED output: Programmable LED1 output

Config mode: Latched as Speed (register 0h, bit [13]) at the de-assertion of reset.

See the “ Strapping Options ” section for details.

The LED1 pin is programmable using register 1Fh bits [5:4], and is defined as follows.

LED mode = [00]

Speed Pin State LED Definition

OFF

ON

Ipu

Gnd

10Base-T

100Base-TX

High

Low

LED mode = [01]

Activity Pin State

No activity High

Activity Toggle

LED mode = [10], [11]

Reserved

Chip reset (active low)

Ground

LED Definition

OFF

Blinking

32

PADDLE

RST#

GND

Notes:

1. P = Power supply.

Gnd = Ground.

I = Input.

O = Output.

I/O = Bi-directional.

Ipu = Input with internal pull-up (see “ Electrical Characteristics ” for value).

Ipu/O = Input with internal pull-up (see “ Electrical Characteristics ” for value) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (see “ Electrical Characteristics ” for value) during power-up/reset; output pin otherwise.

Ipu/Opu = Input with internal pull-up (see “ Electrical Characteristics ” for value) and output with internal pull-up (see “ Electrical Characteristics ” for

value).

2. MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] presents valid data to the MAC. RXD[3:0] is invalid data from the PHY when RXDV is de-asserted.

3. MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] presents valid data from the MAC. TXD[3:0] has no effect on the PHY when TXEN is de-asserted.

February 17, 2013 11 Revision 1.0

Micrel, Inc.

Strapping Options – KSZ8051MNLU

KSZ8051MNLU/KSZ8051RNLU

Pin Number

15

14

13

18

29

28

20

31

16

30

19

21

Pin Name

PHYAD2

PHYAD1

PHYAD0

CONFIG2

CONFIG1

CONFIG0

ISO

SPEED

DUPLEX

NWAYEN

B-CAST_OFF

NAND_Tree#

Type

(1)

Pin Function

Ipd/O PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value from 0 to 7 with PHY Address 1 as the default value.

Ipd/O

Ipu/O

PHY Address 0 is assigned by default as the broadcast PHY address, but it can be assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high or writing a ‘1’ to register 16h, bit [9].

Ipd/O

Ipd/O

Ipd/O

PHY Address bits [4:3] are set to 00 by default.

The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.

CONFIG[2:0] Mode

000

110

001 – 101, 111

MII (default)

MII back-to-back

Reserved – not used

Ipd/O

Ipu/O

Ipu/O

Ipu/O

Ipd/O

Ipu/Opu

Isolate mode

Pull-up = Enable

Pull-down (default) = Disable

At the de-assertion of reset, this pin value is latched into register 0h, bit [10].

Speed mode

Pull-up (default) = 100Mbps

Pull-down = 10Mbps

At the de-assertion of reset, this pin value is latched into register 0h, bit [13] as the speed select, and also is latched into register 4h (auto-negotiation advertisement) as the speed capability support.

Duplex mode

Pull-up (default) = Half-duplex

Pull-down = Full-duplex

At the de-assertion of reset, this pin value is latched into register 0h, bit [8].

Nway auto-negotiation enable

Pull-up (default) = Enable auto-negotiation

Pull-down = Disable auto-negotiation

At the de-assertion of reset, this pin value is latched into register 0h, bit [12].

Broadcast off – for PHY Address 0

Pull-up = PHY Address 0 is set as an unique PHY address

Pull-down (default) = PHY Address 0 is set as a broadcast PHY address

At the de-assertion of reset, this pin value is latched by the chip.

NAND tree mode

Pull-up (default) = Disable

Pull-down = Enable

At the de-assertion of reset, this pin value is latched by the chip.

Note:

1.

Ipu/O = Input with internal pull-up (see “ Electrical Characteristics ” for value) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (see “ Electrical Characteristics ” for value) during power-up/reset; output pin otherwise.

Ipu/Opu = Input with internal pull-up (see “ Electrical Characteristics ” for value) and output with internal pull-up (see “ Electrical Characteristics ” for value).

The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to unintended high/low states. In this case, external pull-ups (4.7k

Ω) or pull-downs (1.0kΩ) should be added on these PHY strap-in pins to ensure that the intended values are strapped-in correctly.

February 17, 2013 12 Revision 1.0

Micrel, Inc.

Pin Configuration – KSZ8051RNLU

KSZ8051MNLU/KSZ8051RNLU

32-Pin (5mm x 5mm) QFN

February 17, 2013 13 Revision 1.0

3

4

5

6

7

8

Micrel, Inc.

Pin Description– KSZ8051RNLU

Pin Number Pin Name Type

(1)

Pin Function

1

2

GND

VDD_1.2

9

10

11

12

13

14

15

16

17

18

19

VDDA_3.3

RXM

RXP

TXM

TXP

XO

XI

REXT

MDIO

MDC

PHYAD0

PHYAD1

RXD1/

PHYAD2

RXD0/

DUPLEX

VDDIO

CRS_DV/

CONFIG2

REF_CLK/

B-CAST_OFF

KSZ8051MNLU/KSZ8051RNLU

P

I/O

I/O

I/O

I/O

O

Gnd

P

I

Ground

1.2V core V

DD

(power supplied by KSZ8051RNLU)

Decouple with 2.2µF and 0.1µF capacitors to ground.

3.3V analog V

DD

Physical receive or transmit signal (

− differential)

Physical receive or transmit signal (+ differential)

Physical transmit or receive signal (

− differential)

Physical transmit or receive signal (+ differential)

Crystal feedback for 25MHz crystal

This pin is a no connect if an oscillator or external clock source is used.

25MHz Mode: 25MHz ±50ppm Crystal / Oscillator / External Clock Input

50MHz Mode: 50MHz ±50ppm Oscillator / External Clock Input

I Set PHY transmit output current

Connect a 6.49kΩ resistor to ground on this pin.

Ipu/Opu Management Interface (MII) Data I/O

This pin has a weak pull-up, is open-drain, and requires an external 1.0kΩ pull-up resistor.

Ipu Management Interface (MII) Clock input

This clock pin is synchronous to the MDIO data pin.

Ipu/O

Ipd/O

Ipd/O

Ipu/O

P

Ipd/O

The pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of

reset. See the “ Strapping Options ” section for details.

The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of

reset. See the “ Strapping Options ” section for details.

RMII mode: RMII Receive Data Output[1]

(2)

Config mode: The pull-up/pull-down value is latched as PHYADDR[2] at the de-assertion of reset.

RMII mode:

See the “ Strapping Options ” section for details.

RMII Receive Data Output[0]

(2)

Config mode: The pull-up/pull-down value is latched as DUPLEX at the de-assertion of reset.

See the “ Strapping Options ” section for details.

3.3V, 2.5V, or 1.8V digital V

DD

RMII mode: RMII Carrier Sense/Receive Data Valid output /

Config mode: The pull-up/pull-down value is latched as CONFIG2 at the de-assertion of reset.

See the “ Strapping Options ” section for details.

Ipd/O RMII mode: 25MHz mode: This pin provides the 50MHz RMII reference clock output to the MAC. See also XI (pin 9).

50MHz mode: This pin is a no connect. See also XI (pin 9).

Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the de-assertion of reset.

See the “ Strapping Options ” section for details.

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21

22

23

24

25

26

27

28

29

30

Micrel, Inc.

Pin Number

20

Pin Name

RXER/

ISO

INTRP/

NAND_Tree#

NC

TXEN

TXD0

TXD1

NC

NC

CONFIG0

CONFIG1

LED0/

NWAYEN

KSZ8051MNLU/KSZ8051RNLU

Type

(1)

Pin Function

Ipd/O RMII mode: RMII Receive Error output

Config mode: The pull-up/pull-down value is latched as ISOLATE at the de-assertion of reset.

See the “ Strapping Options ” section for details.

-

-

I

I

Ipu/Opu Interrupt output: Programmable interrupt output

This pin has a weak pull-up, is open-drain, and requires an external 1.0k

Ω pull-up resistor.

Config mode: The pull-up/pull-down value is latched as NAND Tree# at the de-assertion of reset.

See the “ Strapping Options ” section for details.

- No connect – This pin is not bonded and can be left floating.

I

RMII Transmit Enable input

RMII Transmit Data Input[0]

(3)

RMII Transmit Data Input[1]

(3)

No connect – This pin is not bonded and can be left floating.

No connect – This pin is not bonded and can be left floating.

Ipd/O

Ipd/O

Ipu/O

The pull-up/pull-down value is latched as CONFIG0 at the de-assertion of reset.

See the “ Strapping Options ” section for details.

The pull-up/pull-down value is latched as CONFIG1 at the de-assertion of reset.

See the “ Strapping Options ” section for details.

LED output: Programmable LED0 output

Config mode: Latched as auto-negotiation enable (register 0h, bit [12]) at the de-assertion of reset.

See the “ Strapping Options ” section for details.

The LED0 pin is programmable using register 1Fh bits [5:4], and is defined as follows.

LED mode = [00]

Link/Activity

No link

Link

Activity

Pin State

High

Low

Toggle

LED mode = [01]

Link Pin State

No link

Link

High

Low

LED mode = [10], [11]

Reserved

LED Definition

OFF

ON

Blinking

LED Definition

OFF

ON

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Pin Number

KSZ8051MNLU/KSZ8051RNLU

31

Pin Name

LED1/

SPEED

Type

(1)

Pin Function

Ipu/O LED output: Programmable LED1 output

Config mode: Latched as Speed (register 0h, bit [13]) at the de-assertion of reset.

See the “ Strapping Options ” section for details.

The LED1 pin is programmable using register 1Fh bits [5:4], and is defined as follows.

LED mode = [00]

Speed Pin State LED Definition

OFF

ON

10Base-T

100Base-TX

High

Low

LED mode = [01]

Activity Pin State

No activity High

Activity Toggle

LED mode = [10], [11]

Reserved

LED Definition

OFF

Blinking

32

PADDLE

RST#

GND

Ipu

Gnd

Chip reset (active low)

Ground

Notes:

1. P = Power supply.

Gnd = Ground.

I = Input.

O = Output.

I/O = Bi-directional.

Ipu = Input with internal pull-up (see “ Electrical Characteristics ” for value).

Ipu/O = Input with internal pull-up (see “ Electrical Characteristics ” for value) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (see “ Electrical Characteristics ” for value) during power-up/reset; output pin otherwise.

Ipu/Opu = Input with internal pull-up (see “ Electrical Characteristics ” for value) and output with internal pull-up (see “ Electrical Characteristics ” for

value).

NC = Pin is not bonded to the die.

2. RMII RX Mode: The RXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the MAC.

3. RMII TX Mode: The TXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC.

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Strapping Options – KSZ8051RNLU

KSZ8051MNLU/KSZ8051RNLU

Pin Number

15

14

13

18

29

28

20

31

16

30

19

21

Pin Name

PHYAD2

PHYAD1

PHYAD0

CONFIG2

CONFIG1

CONFIG0

ISO

SPEED

DUPLEX

NWAYEN

B-CAST_OFF

NAND_Tree#

Type

(1)

Pin Function

Ipd/O PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value from 0 to 7 with PHY Address 1 as the default value.

Ipd/O

Ipu/O

PHY Address 0 is assigned by default as the broadcast PHY address, but it can be assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high or writing a ‘1’ to register 16h, bit [9].

Ipd/O

Ipd/O

Ipd/O

PHY Address bits [4:3] are set to 00 by default.

The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.

CONFIG[2:0] Mode

001

101

RMII

RMII back-to-back

000, 010 – 100, 110, 111 Reserved – not used

Ipd/O

Ipu/O

Ipu/O

Ipu/O

Ipd/O

Ipu/Opu

Isolate mode

Pull-up = Enable

Pull-down (default) = Disable

At the de-assertion of reset, this pin value is latched into register 0h, bit [10].

Speed mode

Pull-up (default) = 100Mbps

Pull-down = 10Mbps

At the de-assertion of reset, this pin value is latched into register 0h, bit [13] as the speed select, and also is latched into register 4h (auto-negotiation advertisement) as the speed capability support.

Duplex mode

Pull-up (default) = Half-duplex

Pull-down = Full-duplex

At the de-assertion of reset, this pin value is latched into register 0h, bit [8].

Nway auto-negotiation enable

Pull-up (default) = Enable auto-negotiation

Pull-down = Disable auto-negotiation

At the de-assertion of reset, this pin value is latched into register 0h, bit [12].

Broadcast off – for PHY Address 0

Pull-up = PHY Address 0 is set as an unique PHY address

Pull-down (default) = PHY Address 0 is set as a broadcast PHY address

At the de-assertion of reset, this pin value is latched by the chip.

NAND tree mode

Pull-up (default) = Disable

Pull-down = Enable

At the de-assertion of reset, this pin value is latched by the chip.

Note:

1.

Ipu/O = Input with internal pull-up (see “ Electrical Characteristics ” for value) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (see “ Electrical Characteristics ” for value) during power-up/reset; output pin otherwise.

Ipu/Opu = Input with internal pull-up (see “ Electrical Characteristics ” for value) and output with internal pull-up (see “ Electrical Characteristics ” for value).

The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive high/low during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched to unintended high/low states. In this case, external pull-ups (4.7k

Ω) or pull-downs (1.0kΩ) should be added on these PHY strap-in pins to ensure that the intended values are strapped-in correctly.

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Functional Description: 10Base-T/100Base-TX Transceiver

KSZ8051MNLU/KSZ8051RNLU

The KSZ8051 is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3

Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two differential pairs and by integrating the regulator to supply the 1.2V core.

On the copper media side, the KSZ8051 supports 10Base-T and 100Base-TX for transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and correction for straight-through and crossover cables.

On the MAC processor side, the KSZ8051MNLU offers the Media Independent Interface (MII) and the KSZ8051RNLU offers the Reduced Media Independent Interface (RMII) for direct connection with MII and RMII compliant Ethernet MAC processors and switches, respectively.

The MII management bus option gives the MAC processor complete access to the KSZ8051 control and status registers.

Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change.

The KSZ8051MNLU/RNLU is used to refer to both KSZ8051MNLU and KSZ8051RNLU versions in this data sheet.

100Base-TX Transmit

The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding and transmission.

The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 6.49k

Ω 1% resistor for the 1:1 transformer ratio.

The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX transmitter.

100Base-TX Receive

The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.

The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations.

Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit compensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit converts MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock-recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal to NRZ format. This signal is sent through the de-scrambler, then the 4B/5B decoder. Finally, the NRZ serial data is converted to MII format and provided as the input data to the MAC.

Scrambler/De-Scrambler (100Base-TX Only)

The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and baseline wander. The de-scrambler recovers the scrambled signal.

10Base-T Transmit

The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.

The drivers perform internal wave-shaping and pre-emphasis, and output 10Base-T signals with a typical amplitude of

2.5V peak. The 10Base-T signals have harmonic contents that are at least 27dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.

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10Base-T Receive

On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV, or with short pulse widths, to prevent noise at the RXP and RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8051MNLU/RNLU decodes a data frame. The receive clock is kept active during idle periods between data receptions.

SQE and Jabber Function (10Base-T Only)

In 10Base-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE test is needed to test the 10Base-T transmit/receive path. If transmit enable (TXEN) is high for more than 20ms (jabbering), the 10Base-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250ms, the 10Base-T transmitter is re-enabled and COL is de-asserted (returns to low).

PLL Clock Synthesizer

The KSZ8051MNLU/RNLU generates all internal clocks and all external clocks for system timing from an external 25MHz crystal, oscillator, or reference clock. For the KSZ8051RNLU in RMII 50MHz clock mode, these clocks are generated from an external 50MHz oscillator or system clock.

Auto-Negotiation

The KSZ8051MNLU/RNLU conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3

Specification.

Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.

During auto-negotiation, link partners advertise capabilities across the UTP link to each other and then compare their own capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of operation.

The following list shows the speed and duplex operation mode from highest to lowest priority.

• Priority 1:

100Base-TX, full-duplex

• Priority 2:

• Priority 3:

• Priority 4:

100Base-TX, half-duplex

10Base-T, full-duplex

10Base-T, half-duplex

If auto-negotiation is not supported or the KSZ8051MNLU/RNLU link partner is forced to bypass auto-negotiation, then the

KSZ8051MNLU/RNLU sets its operating mode by observing the signal at its receiver. This is known as parallel detection, which allows the KSZ8051MNLU/RNLU to establish a link by listening for a fixed signal protocol in the absence of the auto-negotiation advertisement protocol.

Auto-negotiation is enabled by either hardware pin strapping (NWAYEN, pin 30) or software (register 0h, bit [12]).

By default, auto-negotiation is enabled after power-up or hardware reset. After that, auto-negotiation can be enabled or disabled by register 0h, bit [12]. If auto-negotiation is disabled, the speed is set by register 0h, bit [13], and the duplex is set by register 0h, bit [8].

The auto-negotiation link-up process is shown in Figure 1 .

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Figure 1. Auto-Negotiation Flow Chart

MII Interface (KSZ8051MNLU only)

The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface between MII PHYs and MACs, and has the following key characteristics:

• Pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indication).

• 10Mbps and 100Mbps data rates are supported at both half- and full-duplex.

• Data transmission and reception are independent and belong to separate signal groups.

• Transmit data and receive data are each 4 bits wide, a nibble.

By default, the KSZ8051MNLU is configured to MII mode after it is powered up or hardware reset with the following:

• A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.

• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 000 (default setting).

MII Signal Definition

Table 1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.

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MII Signal

Name

Direction

(with respect to PHY,

KSZ8051MNLU signal)

Direction

(with respect to MAC)

Description

KSZ8051MNLU/KSZ8051RNLU

TXC

TXEN

TXD[3:0]

RXC

RXDV

RXD[3:0]

RXER

CRS

COL

Output

Input

Input

Output

Output

Output

Output

Output

Output

Input

Transmit Clock

(2.5MHz for 10Mbps; 25MHz for 100Mbps)

Output

Output

Input

Transmit Enable

Transmit Data[3:0]

Receive Clock

(2.5MHz for 10Mbps; 25MHz for 100Mbps)

Input

Input

Receive Data Valid

Receive Data[3:0]

Input, or (not required) Receive Error

Input

Input

Carrier Sense

Collision Detection

Table 1. MII Signal Definition

Transmit Clock (TXC)

TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0].

TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.

Transmit Enable (TXEN)

TXEN indicates that the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII. It is negated before the first TXC following the final nibble of a frame.

TXEN transitions synchronously with respect to TXC.

Transmit Data[3:0] (TXD[3:0])

TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted by the PHY for transmission. TXD[3:0] is 00 to indicate idle when TXEN is de-asserted. Values other than 00 on TXD[3:0] while TXEN is de-asserted are ignored by the PHY.

Receive Clock (RXC)

RXC provides the timing reference for RXDV, RXD[3:0], and RXER.

• In 10Mbps mode, RXC is recovered from the line while the carrier is active. RXC is derived from the PHY’s reference clock when the line is idle or the link is down.

• In 100Mbps mode, RXC is continuously recovered from the line. If the link is down, RXC is derived from the

PHY’s reference clock.

RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.

Receive Data Valid (RXDV)

RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].

• In 10Mbps mode, RXDV is asserted with the first nibble of the start-of-frame delimiter (SFD), 5D, and remains asserted until the end of the frame.

• In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.

RXDV transitions synchronously with respect to RXC.

Receive Data[3:0] (RXD[3:0])

RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0] transfers a nibble of recovered data from the PHY.

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Receive Error (RXER)

RXER is asserted for one or more RXC periods to indicate that a symbol error (for example, a coding error that a PHY can detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being transferred from the PHY.

RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC.

Carrier Sense (CRS)

CRS is asserted and de-asserted as follows:

• In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the reception of an end-of-frame (EOF) marker.

• In 100Mbps mode, CRS is asserted when a start-of-stream delimiter or /J/K symbol pair is detected. CRS is deasserted when an end-of-stream delimiter or /T/R symbol pair is detected. Additionally, the PMA layer deasserts CRS if IDLE symbols are received without /T/R.

Collision (COL)

COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This informs the MAC that a collision has occurred during its transmission to the PHY.

COL transitions asynchronously with respect to TXC and RXC.

MII Signal Diagram

The KSZ8051MNLU MII pin connections to the MAC are shown in Figure 2 .

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Figure 2. KSZ8051MNLU MII Interface

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RMII Data Interface (KSZ8051RNLU only)

KSZ8051MNLU/KSZ8051RNLU

The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:

• Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50MHz reference clock).

• 10Mbps and 100Mbps data rates are supported at both half- and full-duplex.

• Data transmission and reception are independent and belong to separate signal groups.

• Transmit data and receive data are each 2 bits wide, a dibit.

RMII – 25MHz Clock Mode

The KSZ8051RNLU is configured to RMII – 25MHz clock mode after it is powered up or hardware reset with the following:

• A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.

• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 001.

• Register 1Fh, bit [7] is set to 0 (default value) to select 25MHz clock mode.

RMII – 50MHz Clock Mode

The KSZ8051RNLU is configured to RMII – 50MHz clock mode after it is powered up or hardware reset with the following:

• An external 50MHz clock source (oscillator) connected to XI (pin 9).

• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 001.

• Register 1Fh, bit [7] is set to 1 to select 50MHz clock mode.

RMII Signal Definition

Table 2 describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.

RMII Signal

Name

REF_CLK

TXEN

TXD[1:0]

CRS_DV

RXD[1:0]

RXER

Direction

(with respect to PHY,

KSZ8051RNLU signal)

Output (25MHz clock mode) /

<no connect> (50MHz clock mode)

Input

Input

Output

Output

Output

Direction

(with respect to MAC)

Description

Input/

Input or <no connect>

Output

Output

Input

Input

Synchronous 50MHz reference clock for receive, transmit, and control interface

Transmit Enable

Transmit Data[1:0]

Carrier Sense/Receive Data Valid

Receive Data[1:0]

Input, or (not required) Receive Error

Table 2. RMII Signal Definition

Reference Clock (REF_CLK)

REF_CLK is a continuous 50MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0], and

RX_ER.

For 25MHz clock mode, the KSZ8051RNLU generates and outputs the 50MHz RMII REF_CLK to the MAC at REF_CLK

(pin 19).

For 50MHz clock mode, the KSZ8051RNLU takes in the 50MHz RMII REF_CLK from the MAC or system board at XI (pin

9) and leaves the REF_CLK (pin 19) as a no connect.

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Transmit Enable (TXEN)

TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated before the first REF_CLK following the final dibit of a frame.

TXEN transitions synchronously with respect to REF_CLK.

Transmit Data[1:0] (TXD[1:0])

TXD[1:0] transitions synchronously with respect to REF_CLK. When TXEN is asserted, the PHY accepts TXD[1:0] for transmission.

TXD[1:0] is 00 to indicate idle when TXEN is de-asserted. The PHY ignores values other than 00 on TXD[1:0] while TXEN is de-asserted.

Carrier Sense / Receive Data Valid (CRS_DV)

The PHY asserts CRS_DV when the receive medium is non-idle. It is asserted asynchronously when a carrier is detected.

This happens when squelch is passed in 10Mbps mode, and when two non-contiguous 0s in 10 bits are detected in

100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.

While carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered dibit of the frame through the final recovered dibit. It is negated before the first REF_CLK that follows the final dibit. The data on RXD[1:0] is considered valid after CRS_DV is asserted. However, because the assertion of CRS_DV is asynchronous relative to

REF_CLK, the data on RXD[1:0] is 00 until receive signals are properly decoded.

Receive Data[1:0] (RXD[1:0])

RXD[1:0] transitions synchronously with respect to REF_CLK. For each clock period in which CRS_DV is asserted,

RXD[1:0] transfers two bits of recovered data from the PHY.

RXD[1:0] is 00 to indicate idle when CRS_DV is de-asserted. The MAC ignores values other than 00 on RXD[1:0] while

CRS_DV is de-asserted.

Receive Error (RXER)

RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for example, a coding error that a

PHY can detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being transferred from the PHY.

RXER transitions synchronously with respect to REF_CLK. . While CRS_DV is de-asserted, RXER has no effect on the

MAC.

Collision Detection (COL)

The MAC regenerates the COL signal of the MII from TXEN and CRS_DV.

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RMII Signal Diagram

The KSZ8051RNLU RMII pin connections to the MAC for 25MHz clock mode are shown in Figure 3 .

The connections for

50MHz clock mode are shown in Figure 4 .

Figure 3. KSZ8051RNLU RMII Interface (25MHz Clock Mode)

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Figure 4. KSZ8051RNLU RMII Interface (50MHz Clock Mode)

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Back-to-Back Mode – 100Mbps Copper Repeater

KSZ8051MNLU/KSZ8051RNLU

Two KSZ8051MNLU/RNLU devices can be connected back-to-back to form a 100Base-TX copper repeater.

Figure 5. KSZ8051MNLU/RNLU to KSZ8051MNLU/RNLU Back-to-Back Copper Repeater

MII Back-to-Back Mode (KSZ8051MNLU only)

In MII back-to-back mode, a KSZ8051MNLU interfaces with another KSZ8051MNLU to provide a complete 100Mbps copper repeater solution.

The KSZ8051MNLU devices are configured to MII back-to-back mode after power-up or reset with the following:

• Strapping pin CONFIG[2:0] (pins 18, 29, 28) set to 110

• A common 25MHz reference clock connected to XI (pin 9) of both KSZ8051MNLU devices

• MII signals connected as shown in

Table 3

KSZ8051MNLU (100Base-TX copper)

[Device 1]

Pin Name Pin Number Pin Type

RXC

RXDV

RXD3

RXD2

19

18

13

14

Output

Output

Output

Output

RXD1

RXD0

TXC

TXEN

TXD3

TXD2

TXD1

TXD0

15

16

22

23

27

26

25

24

Output

Output

Input

Input

Input

Input

Input

Input

KSZ8051MNLU (100Base-TX copper)

[Device 2]

Pin Name Pin Number Pin Type

TXC

TXEN

TXD3

TXD2

22

23

27

26

Input

Input

Input

Input

TXD1

TXD0

RXC

RXDV

RXD3

RXD2

RXD1

RXD0

25

24

19

18

13

14

15

16

Input

Input

Output

Output

Output

Output

Output

Output

Table 3. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater)

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Micrel, Inc. KSZ8051MNLU/KSZ8051RNLU

RMII Back-to-Back Mode (KSZ8051RNLU only)

In RMII back-to-back mode, a KSZ8051RNLU interfaces with another KSZ8051RNLU to provide a complete 100Mbps copper repeater solution.

The KSZ8051RNLU devices are configured to RMII back-to-back mode after power-up or reset with the following:

• Strapping pin CONFIG[2:0] (pins 18, 29, 28) set to 101

• A common 50MHz reference clock connected to XI (pin 9) of both KSZ8051RNLU devices

• RMII signals connected as shown in

Table 4

KSZ8051RNLU (100Base-TX copper)

[Device 1]

Pin Name Pin Number Pin Type

KSZ8051RNLU (100Base-TX copper)

[Device 2]

Pin Name Pin Number Pin Type

CRSDV

RXD1

RXD0

18

15

16

Output

Output

Output

TXEN

TXD1

TXD0

23

25

24

Input

Input

Input

TXEN

TXD1

23

25

Input

Input

CRSDV

RXD1

18

15

Output

Output

TXD0 24 Input RXD0 16 Output

Table 4. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater)

MII Management (MIIM) Interface

The KSZ8051MNLU/RNLU supports the IEEE 802.3 MII management interface, also known as the Management Data

Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and control the state of the KSZ8051MNLU/RNLU. An external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3

Specification.

The MIIM interface consists of the following:

• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).

• A specific protocol that operates across the physical connection mentioned earlier, which allows the external controller to communicate with one or more PHY devices.

• A set of 16-bit MDIO registers. Registers [0:8] are standard registers, and their functions are defined in the IEEE

802.3 Specification. The additional registers are provided for expanded functionality. See the “ Register Map ”

section for details.

As the default, the KSZ8051MNLU/RNLU supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The latter is defined in the IEEE 802.3 Specification, and can be used to read/write to a single KSZ8051MNLU/RNLU device, or write to multiple KSZ8051MNLU/RNLU devices simultaneously.

PHY address 0 can optionally be disabled as the broadcast address by either hardware pin strapping (B-CAST_OFF, pin

19) or software (register 16h, bit [9]), and assigned as a unique PHY address.

The PHYAD[2:0] strapping pins are used to assign a unique PHY address between 0 and 7 to each

KSZ8051MNLU/RNLU device.

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Table 5 shows the MII management frame format for the KSZ8051MNLU/RNLU.

Preamble

Read

32 1’s

Write 32 1’s

Start of

Frame

01

01

Read/Write

OP Code

10

01

PHY Address

Bits [4:0]

00AAA

00AAA

REG Address

Bits [4:0]

RRRRR

RRRRR

KSZ8051MNLU/KSZ8051RNLU

TA

Data

Bits [15:0]

Idle

Z0 DDDDDDDD_DDDDDDDD Z

10 DDDDDDDD_DDDDDDDD Z

Table 5. MII Management Frame Format for the KSZ8051MNLU/RNLU

Interrupt (INTRP)

INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status update to the KSZ8051MNLU/RNLU PHY register. Bits [15:8] of register 1Bh are the interrupt control bits to enable and disable the conditions for asserting the INTRP signal. Bits [7:0] of register 1Bh are the interrupt status bits to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register 1Bh.

Bit [9] of register 1Fh sets the interrupt level to active high or active low. The default is active low.

The MII management bus option gives the MAC processor complete access to the KSZ8051MNLU/RNLU control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.

HP Auto MDI/MDI-X

HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable between the KSZ8051MNLU/RNLU and its link partner. This feature allows the KSZ8051MNLU/RNLU to use either type of cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive pairs from the link partner and assigns transmit and receive pairs to the KSZ8051MNLU/RNLU accordingly.

HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a ‘1’ to register 1Fh, bit [13]. MDI and MDI-X mode is selected by register 1Fh, bit [14] if HP Auto MDI/MDI-X is disabled.

An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.

Table 6 shows how the IEEE 802.3 Standard defines MDI and MDI-X.

MDI MDI-X

RJ-45 Pin

1

2

3

6

Signal

TX+

TX

RX+

RX

RJ-45 Pin

1

2

3

6

Signal

RX+

RX

TX+

TX

Table 6. MDI/MDI-X Pin Definition

Straight Cable

A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 6 shows a

typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).

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Micrel, Inc. KSZ8051MNLU/KSZ8051RNLU

Figure 6. Typical Straight Cable Connection

Crossover Cable

A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. Figure 7

shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).

February 17, 2013

Figure 7. Typical Crossover Cable Connection

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Loopback Mode

KSZ8051MNLU/KSZ8051RNLU

The KSZ8051MNLU/RNLU supports the following loopback operations to verify analog and/or digital data paths.

• Local (digital) loopback

• Remote (analog) loopback

Local (Digital) Loopback

This loopback mode checks the MII/RMII transmit and receive data paths between the KSZ8051MNLU/RNLU and the external MAC, and is supported for both speeds (10/100Mbps) at full-duplex.

The loopback data path is shown in Figure 8 .

1. The MII/RMII MAC transmits frames to the KSZ8051MNLU/RNLU.

2. Frames are wrapped around inside the KSZ8051MNLU/RNLU.

3. The KSZ8051MNLU/RNLU transmits frames back to the MII/RMII MAC.

Figure 8. Local (Digital) Loopback

The following programming action and register settings are used for local loopback mode.

For 10/100Mbps loopback,

Set register 0h,

• Bit [14] = 1

• Bit [13] = 0/1

• Bit [12] = 0

• Bit [8] = 1

// Enable local loopback mode

// Select 10Mbps/100Mbps speed

// Disable auto-negotiation

// Select full-duplex mode

Remote (Analog) Loopback

This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and receive data paths between the KSZ8051MNLU/RNLU and its link partner, and is supported for 100Base-TX full-duplex mode only.

The loopback data path is shown in Figure 9 .

1. The Fast Ethernet (100Base-TX) PHY link partner transmits frames to the KSZ8051MNLU/RNLU.

2. Frames are wrapped around inside the KSZ8051MNLU/RNLU.

3. The KSZ8051MNLU/RNLU transmits frames back to the Fast Ethernet (100Base-TX) PHY link partner.

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Micrel, Inc. KSZ8051MNLU/KSZ8051RNLU

Figure 9. Remote (Analog) Loopback

The following programming steps and register settings are used for remote loopback mode.

1. Set Register 0h,

• Bits [13] = 1

• Bit [12] = 0

• Bit [8] = 1

// Select 100Mbps speed

// Disable auto-negotiation

// Select full-duplex mode

Or just auto-negotiate and link up at 100Base-TX full-duplex mode with the link partner.

2. Set Register 1Fh,

• Bit [2] = 1

LinkMD

®

Cable Diagnostic

// Enable remote loopback mode

The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems.

These include open circuits, short circuits, and impedance mismatches.

LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as a numerical value that can be translated to a cable distance.

LinkMD is initiated by accessing register 1Dh, the LinkMD Control/Status register, in conjunction with register 1Fh, the

PHY Control 2 register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as the cable differential pair for testing.

NAND Tree Support

The KSZ8051MNLU/RNLU provides parametric NAND tree support for fault detection between chip I/Os and board. The

NAND tree is a chain of nested NAND gates in which each KSZ8051MNLU/RNLU digital I/O (NAND tree input) pin is an input to one NAND gate along the chain. At the end of the chain, the CRS/CONFIG1 pin provides the output for the nested NAND gates.

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Micrel, Inc. KSZ8051MNLU/KSZ8051RNLU

The NAND tree test process includes:

• Enabling NAND tree mode

• Pulling all NAND tree input pins high

• Driving each NAND tree input pin low, sequentially, according to the NAND tree pin order

• Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input driven low

Table 7

and Table 8 list the NAND tree pin orders for KSZ8051MNLU and KSZ8051RNLU, respectively.

Pin Number Pin Name

NAND Tree Description

19

20

21

22

23

24

25

11

12

13

14

15

16

18

MDIO

MDC

RXD3

RXD2

RXD1

RXD0

RXDV

RXC

RXER

INTRP

TXC

TXEN

TXD0

TXD1

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

26

27

30

TXD2

TXD3

LED0

Input

Input

Input

31

28

LED1

COL

Input

Input

29 CRS Output

Table 7. NAND Tree Test Pin Order for KSZ8051MNLU

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15

16

18

19

20

21

23

Pin Number

11

12

13

14

Pin Name

MDIO

MDC

PHYAD0

PHYAD1

RXD1

RXD0

CRS_DV

REF_CLK

RXER

INTRP

TXEN

NAND Tree Description

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

24

25

30

31

TXD0

TXD1

LED0

LED1

Input

Input

Input

Input

28 CONFIG0 Input

29 CONFIG1 Output

Table 8. NAND Tree Test Pin Order for KSZ8051RNLU

NAND Tree I/O Testing

Use the following procedure to check for faults on the KSZ8051MNLU/RNLU digital I/O pin connections to the board:

1. Enable NAND tree mode using either hardware (NAND_Tree#, pin 21) or software (register 16h, bit [5]).

2. Use board logic to drive all KSZ8051MNLU/RNLU NAND tree input pins high.

3. Use board logic to drive each NAND tree input pin, in KSZ8051MNLU/RNLU NAND tree pin order, as follows: a. Toggle the first pin (MDIO) from high to low, and verify that the CRS/CONFIG1 pin switches from high to low to indicate that the first pin is connected properly. b. Leave the first pin (MDIO) low. c. Toggle the second pin (MDC) from high to low, and verify that the CRS/CONFIG1 pin switches from low to high to indicate that the second pin is connected properly. d. Leave the first pin (MDIO) and the second pin (MDC) low. e. Toggle the third pin (RXD3/PHYAD0)) from high to low, and verify that the CRS/CONFIG1 pin switches from high to low to indicate that the third pin is connected properly. f. Continue with this sequence until all KSZ8051MNLU/RNLU NAND tree input pins have been toggled.

Each KSZ8051MNLU/RNLU NAND tree input pin must cause the CRS/CONFIG1 output pin to toggle high-to-low or lowto-high to indicate a good connection. If the CRS pin fails to toggle when the KSZ8051MNLU/RNLU input pin toggles from high to low, the input pin has a fault.

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Power Management

The KSZ8051MNLU/RNLU incorporates a number of power-management modes and features that provide methods to consume less energy. These are discussed in the following sections.

Power-Saving Mode

Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled by writing a ‘1’ to register 1Fh, bit [10], and is in effect when auto-negotiation mode is enabled and the cable is disconnected

(no link).

In this mode, the KSZ8051MNLU/RNLU shuts down all transceiver blocks, except for the transmitter, energy detect, and

PLL circuits.

By default, power-saving mode is disabled after power-up.

Energy-Detect Power-Down Mode

Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is unplugged. It is enabled by writing a ‘0’ to register 18h, bit [11], and is in effect when auto-negotiation mode is enabled and the cable is disconnected (no link).

EDPD mode works with the PLL off (set by writing a ‘1’ to register 10h, bit [4] to automatically turn the PLL off in EDPD mode) to turn off all KSZ8051MNLU/RNLU transceiver blocks except the transmitter and energy-detect circuits.

Power can be reduced further by extending the time interval between transmissions of link pulses to check for the presence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ8051MNLU/RNLU and its link partner, when operating in the same low-power state and with Auto MDI/MDI-X disabled, can wake up when the cable is connected between them.

By default, energy-detect power-down mode is disabled after power-up.

Power-Down Mode

Power-down mode is used to power down the KSZ8051MNLU/RNLU device when it is not in use after power-up. It is enabled by writing a ‘1’ to register 0h, bit [11].

In this mode, the KSZ8051MNLU/RNLU disables all internal functions except the MII management interface. The

KSZ8051MNLU/RNLU exits (disables) power-down mode after register 0h, bit [11] is set back to ‘0’.

Slow-Oscillator Mode

Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (pin 9) and select the on-chip slow oscillator when the KSZ8051MNLU/RNLU device is not in use after power-up. It is enabled by writing a ‘1’ to register 11h, bit [5].

Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8051MNLU/RNLU device in the lowest power state, with all internal functions disabled except the MII management interface. To properly exit this mode and return to normal PHY operation, use the following programming sequence:

1. Disable slow-oscillator mode by writing a ‘0’ to register 11h, bit [5].

2. Disable power-down mode by writing a ‘0’ to register 0h, bit [11].

3. Initiate software reset by writing a ‘1’ to register 0h, bit [15].

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Reference Circuit for Power and Ground Connections

KSZ8051MNLU/KSZ8051RNLU

The KSZ8051MNLU/RNLU is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and

ground connections are shown in Figure 10 and Table 9 for 3.3V VDDIO.

Figure 10. KSZ8051MNLU/RNLU Power and Ground Connections

Power Pin

VDD_1.2

VDDA_3.3

VDDIO

Pin Number Description

2 Decouple with 2.2µF and 0.1µF capacitors to ground.

3

17

Connect to board’s 3.3V supply through a ferrite bead.

Decouple with 22µF and 0.1µF capacitors to ground.

Connect to board’s 3.3V supply for 3.3V VDDIO.

Decouple with 22µF and 0.1µF capacitors to ground.

Table 9. KSZ8051MNLU/RNLU Power Pin Description

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Typical Current/Power Consumption

KSZ8051MNLU/KSZ8051RNLU

Table 10

through Table 12 show typical values for current consumption by the transceiver (VDDA_3.3) and digital I/O

(VDDIO) power pins and typical values for power consumption by the KSZ8051MNLU/RNLU device for the indicated nominal operating voltages. These current and power consumption values include the transmit driver current and on-chip regulator current for the 1.2V core.

Transceiver (3.3V), Digital I/Os (3.3V)

Condition

100Base-TX Link-up (no traffic)

100Base-TX Full-duplex @ 100% utilization

10Base-T Link-up (no traffic)

10Base-T Full-duplex @ 100% utilization

Power-saving mode (Reg. 1Fh, bit [10] = 1)

EDPD mode (Reg. 18h, bit [11] = 0)

EDPD mode (Reg. 18h, bit [11] = 0) and

PLL off (Reg. 10h, bit [4] = 1)

Software power-down mode (Reg. 0h, bit [11] =1)

Software power-down mode (Reg. 0h, bit [11] =1) and slow-oscillator mode (Reg. 11h, bit [5] =1)

3.3V Transceiver

(VDDA_3.3) mA

34

34

14

30

14

10

3.3V Digital I/Os

(VDDIO) mA

12

13

11

11

10

10

Total Chip Power mW

152

155

82.5

135

79.2

66.0

3.77

2.59

1.36

1.54

1.51

0.45

17.5

13.5

5.97

Table 10. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V)

Transceiver (3.3V), Digital I/Os (2.5V)

Condition

100Base-TX Link-up (no traffic)

100Base-TX Full-duplex @ 100% utilization

10Base-T Link-up (no traffic)

10Base-T Full-duplex @ 100% utilization

Power-saving mode (Reg. 1Fh, bit [10] = 1)

EDPD mode (Reg. 18h, bit [11] = 0)

EDPD mode (Reg. 18h, bit [11] = 0) and

PLL off (Reg. 10h, bit [4] = 1)

Software power-down mode (Reg. 0h, bit [11] =1)

Software power-down mode (Reg. 0h, bit [11] =1) and slow-oscillator mode (Reg. 11h, bit [5] =1)

3.3V Transceiver

(VDDA_3.3) mA

34

34

15

27

15

11

2.5V Digital I/Os

(VDDIO) mA

11

12

10

10

10

10

Total Chip Power mW

140

142

74.5

114

74.5

61.3

3.55

2.29

1.15

1.35

1.34

0.29

15.1

10.9

4.52

Table 11. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V)

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Micrel, Inc.

Transceiver (3.3V), Digital I/Os (1.8V)

KSZ8051MNLU/KSZ8051RNLU

Condition

100Base-TX Link-up (no traffic)

100Base-TX Full-duplex @ 100% utilization

10Base-T Link-up (no traffic)

10Base-T Full-duplex @ 100% utilization

Power-saving mode (Reg. 1Fh, bit [10] = 1)

EDPD mode (Reg. 18h, bit [11] = 0)

EDPD mode (Reg. 18h, bit [11] = 0) and

PLL off (Reg. 10h, bit [4] = 1)

Software power-down mode (Reg. 0h, bit [11] =1)

Software power-down mode (Reg. 0h, bit [11] =1) and slow-oscillator mode (Reg. 11h, bit [5] =1)

3.3V Transceiver

(VDDA_3.3) mA

34

34

15

27

15

11

1.8V Digital I/Os

(VDDIO) mA

11

12

9.0

9.0

9.0

9.0

Total Chip Power mW

132

134

65.7

105

65.7

52.5

4.05 1.21 15.5

2.79 1.21 11.4

1.65 0.19 5.79

Table 12. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V)

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Register Map

1Bh

1Ch

1Dh

1Eh

1Fh

11h

12h – 14h

15h

16h

17h

18h

19h – 1Ah

4h

5h

6h

7h

8h

9h

10h

Register Number (Hex)

0h

1h

2h

3h

Description

Basic Control

Basic Status

PHY Identifier 1

PHY Identifier 2

Auto-Negotiation Advertisement

Auto-Negotiation Link Partner Ability

Auto-Negotiation Expansion

Auto-Negotiation Next Page

Link Partner Next Page Ability

Reserved

Digital Reserved Control

AFE Control 1

Reserved

RXER Counter

Operation Mode Strap Override

Operation Mode Strap Status

Expanded Control

Reserved

Interrupt Control/Status

Reserved

LinkMD Control/Status

PHY Control 1

PHY Control 2

KSZ8051MNLU/KSZ8051RNLU

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Register Description

Address Name Description

Mode

(1)

Register 0h – Basic Control

0.15

0.14

0.13

0.12

0.11

0.10

Reset

Loopback

1 = Software reset

0 = Normal operation

This bit is self-cleared after a ‘1’ is written to it.

1 = Loopback mode

0 = Normal operation

Speed Select 1 = 100Mbps

0 = 10Mbps

This bit is ignored if auto-negotiation is enabled

(register 0.12 = 1).

Auto-

Negotiation

Enable

Power-Down

1 = Enable auto-negotiation process

0 = Disable auto-negotiation process

If enabled, the auto-negotiation result overrides the settings in registers 0.13 and 0.8.

1 = Power-down mode

0 = Normal operation

If software reset (register 0.15) is used to exit power-down mode (register 0.11 = 1), two software reset writes (register 0.15 = 1) are required. The first write clears power-down mode; the second write resets the chip and relatches the pin strapping pin values.

Isolate 1 = Electrical isolation of PHY from MII/RMII

0 = Normal operation

RW/SC

RW

RW

RW

RW

RW

0.9

0.8

Restart Auto-

Negotiation

Duplex Mode

1 = Restart auto-negotiation process

0 = Normal operation.

This bit is self-cleared after a ‘1’ is written to it.

1 = Full-duplex

0 = Half-duplex

RW/SC

RW

RW

KSZ8051MNLU/KSZ8051RNLU

Default

0

0

Set by the SPEED strapping pin.

See the “ Strapping Options ”

section for details.

Set by the NWAYEN strapping pin.

See the “ Strapping Options ”

section for details.

0

Set by the ISO strapping pin.

See the “ Strapping Options ”

section for details.

0

The inverse of the DUPLEX strapping pin value.

See the “ Strapping Options ”

section for details.

0 0.7 Collision Test 1 = Enable COL test

0 = Disable COL test

Reserved Reserved 0.6:0

Register 1h – Basic Status

1.15 100Base-T4

1.14

1.13

1.12

100Base-TX

Full-Duplex

100Base-TX

Half-Duplex

10Base-T

Full-Duplex

1 = T4 capable

0 = Not T4 capable

1 = Capable of 100Mbps full-duplex

0 = Not capable of 100Mbps full-duplex

1 = Capable of 100Mbps half-duplex

0 = Not capable of 100Mbps half-duplex

1 = Capable of 10Mbps full-duplex

0 = Not capable of 10Mbps full-duplex

RO

RO

RO

RO

RO

000_0000

0

1

1

1

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Address

1.11

1.10:7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

Name Description

10Base-T

Half-Duplex

1 = Capable of 10Mbps half-duplex

0 = Not capable of 10Mbps half-duplex

Reserved Reserved

No Preamble

Auto-

Negotiation

Complete

1 = Preamble suppression

0 = Normal preamble

1 = Auto-negotiation process completed

0 = Auto-negotiation process not completed

Remote Fault 1 = Remote fault

0 = No remote fault

Auto-

Negotiation

Ability

Link Status

1 = Can perform auto-negotiation

0 = Cannot perform auto-negotiation

1 = Link is up

0 = Link is down

Jabber Detect 1 = Jabber detected

0 = Jabber not detected (default is low)

Extended

Capability

1 = Supports extended capability registers

Register 2h – PHY Identifier 1

2.15:0 PHY ID

Number

Assigned to the 3rd through 18th bits of the

Organizationally Unique Identifier (OUI).

KENDIN Communication’s OUI is 0010A1

(hex).

Register 3h – PHY Identifier 2

3.15:10

3.9:4

3.3:0

PHY ID

Number

Assigned to the 19th through 24th bits of the

Organizationally Unique Identifier (OUI).

KENDIN Communication’s OUI is 0010A1

(hex).

Model Number Six-bit manufacturer’s model number

Revision

Number

Four-bit manufacturer’s revision number

Register 4h – Auto-Negotiation Advertisement

4.15 Next Page 1 = Next page capable

0 = No next page capability

4.14

4.13

4.12

4.11:10

Reserved

Remote Fault 1 = Remote fault supported

Reserved

Pause

Reserved

0 = No remote fault

Reserved

[00] = No pause

[10] = Asymmetric pause

[01] = Symmetric pause

[11] = Asymmetric and symmetric pause

4.9 100Base-T4 1 = T4 capable

0 = No T4 capability

RO/LH

RO

RO

RO

RO

RO

RW

RO

RW

RO

RW

KSZ8051MNLU/KSZ8051RNLU

Mode

(1)

RO

Default

1

RO

RO

RO

000_0

1

0

RO/LL

RO/LH

RO

RO

0

0

0

0

00

0

0

1

0

1

0022h

0001_01

01_0110

Indicates silicon revision

0

February 17, 2013 40 Revision 1.0

Micrel, Inc.

Address

4.8

4.7

Name

100Base-TX

Full-Duplex

100Base-TX

Half-Duplex

Description

1 = 100Mbps full-duplex capable

0 = No 100Mbps full-duplex capability

1 = 100Mbps half-duplex capable

0 = No 100Mbps half-duplex capability

4.6

4.5

4.4:0

10Base-T

Full-Duplex

10Base-T

Half-Duplex

1 = 10Mbps full-duplex capable

0 = No 10Mbps full-duplex capability

1 = 10Mbps half-duplex capable

0 = No 10Mbps half-duplex capability

Selector Field [00001] = IEEE 802.3

Register 5h – Auto-Negotiation Link Partner Ability

5.15 Next Page 1 = Next page capable

5.14

0 = No next page capability

Acknowledge 1 = Link code word received from partner

5.13

0 = Link code word not yet received

Remote Fault 1 = Remote fault detected

0 = No remote fault

5.12

5.11:10

5.9

Reserved

Pause

100Base-T4

Reserved

[00] = No pause

[10] = Asymmetric pause

[01] = Symmetric pause

[11] = Asymmetric and symmetric pause

1 = T4 capable

0 = No T4 capability

5.8

5.7

5.6

5.5

5.4:0

100Base-TX

Full-Duplex

100Base-TX

Half-Duplex

10Base-T

Full-Duplex

10Base-T

Half-Duplex

1 = 100Mbps full-duplex capable

0 = No 100Mbps full-duplex capability

1 = 100Mbps half-duplex capable

0 = No 100Mbps half-duplex capability

1 = 10Mbps full-duplex capable

0 = No 10Mbps full-duplex capability

1 = 10Mbps half-duplex capable

0 = No 10Mbps half-duplex capability

Selector Field [00001] = IEEE 802.3

Register 6h – Auto-Negotiation Expansion

6.15:5 Reserved Reserved

6.4

6.3

6.2

Parallel

Detection Fault

Link Partner

Next Page

Able

Next Page

Able

1 = Fault detected by parallel detection

0 = No fault detected by parallel detection

1 = Link partner has next page capability

0 = Link partner does not have next page capability

1 = Local device has next page capability

0 = Local device does not have next page capability

February 17, 2013 41

RO

RO

RO

RO

RO

KSZ8051MNLU/KSZ8051RNLU

Mode

(1)

RW

RW

RW

Default

Set by the SPEED strapping pin.

See the “ Strapping Options ”

section for details.

Set by the SPEED strapping pin.

See the “ Strapping Options ”

section for details.

1

RW

RW

1

0_0001

0

0

0

0

00

RO

RO

RO

RO

RO

RO

0

0

0

0

0

0_0001

RO

RO/LH

RO

0000_0000_000

0

0

RO 1

Revision 1.0

Micrel, Inc.

Address

6.1

6.0

Name Description

Page Received 1 = New page received

0 = New page not received yet

Link Partner

Auto-

Negotiation

Able

1 = Link partner has auto-negotiation capability

0 = Link partner does not have auto-negotiation capability

Register 7h – Auto-Negotiation Next Page

7.15 Next Page 1 = Additional next pages will follow

7.14 Reserved

0 = Last page

Reserved

7.13

7.12

7.11

7.10:0

Message Page 1 = Message page

0 = Unformatted page

Acknowledge2 1 = Will comply with message

0 = Cannot comply with message

Toggle 1 = Previous value of the transmitted link code word equaled logic 1

0 = Logic 0

Message Field 11-bit field to encode 2048 messages

Register 8h – Link Partner Next Page Ability

8.15 Next Page 1 = Additional next pages will follow

0 = Last page

8.14

8.13

8.12

8.11

8.10:0

Acknowledge 1 = Successful receipt of link word

0 = No successful receipt of link word

Message Page 1 = Message page

0 = Unformatted page

Acknowledge2 1 = Can act on the information

0 = Cannot act on the information

Toggle 1 = Previous value of transmitted link code word equal to logic 0

0 = Previous value of transmitted link code word equal to logic 1

Message Field 11-bit field to encode 2048 messages

Register 10h – Digital Reserved Control

10.15:5

10.4

10.3:0

Reserved

PLL Off

Reserved

Reserved

1 = Turn PLL off automatically in EDPD mode

0 = Keep PLL on in EDPD mode.

See also register 18h, bit [11] for EDPD mode

Reserved

Register 11h – AFE Control 1

11.15:6 Reserved Reserved

Mode

(1)

RO/LH

RO

RW

RO

RW

RW

RO

RW

RO

RO

RO

RO

RO

RO

RW

RW

RW

RW

KSZ8051MNLU/KSZ8051RNLU

Default

0

0

0

0

1

0

0

000_0000_0001

0

0

0

0

0

000_0000_0000

0000_0000_000

0

0000

0000_0000_00

February 17, 2013 42 Revision 1.0

Micrel, Inc.

Address

11.5

Name

Slow-Oscillator

Mode Enable

Reserved

Description

Slow-oscillator mode is used to disconnect the input reference crystal/clock on the XI pin and select the on-chip slow oscillator when the

KSZ8051MNLU/RNLU device is not in use after power-up.

1 = Enable

0 = Disable

This bit automatically sets software power-down to the analog side when enabled.

Reserved

Mode

(1)

RW

RW 11.4:0

Register 15h – RXER Counter

15.15:0 RXER Counter Receive error counter for symbol error frames RO/SC

Register 16h – Operation Mode Strap Override

16.15:11

16.10

16.9

16.8

16.7

Reserved

Reserved

B-CAST_OFF

Override

Reserved

Reserved

Reserved

1 = Override strap-in for B-CAST_OFF

If bit is ‘1’, PHY Address 0 is non-broadcast.

Reserved

16.6

16.5

16.4:2

16.1

16.0

MII B-to-B

Override

1 = Override strap-in for MII back-to-back mode (also set bit 0 of this register to ‘1’)

This bit applies only to KSZ8051MNLU.

RMII B-to-B

Override

1 = Override strap-in for RMII Back-to-Back mode (also set bit 1 of this register to ‘1’)

This bit applies only to KSZ8051RNLU.

1 = Override strap-in for NAND tree mode NAND Tree

Override

Reserved Reserved

RMII Override 1 = Override strap-in for RMII mode

MII Override

This bit applies only to KSZ8051RNLU.

1 = Override strap-in for MII mode

This bit applies only to KSZ8051MNLU.

Register 17h – Operation Mode Strap Status

17.15:13 PHYAD[2:0]

Strap-In Status

[000] = Strap to PHY Address 0

[001] = Strap to PHY Address 1

[010] = Strap to PHY Address 2

17.12:10 Reserved

[011] = Strap to PHY Address 3

[100] = Strap to PHY Address 4

[101] = Strap to PHY Address 5

[110] = Strap to PHY Address 6

[111] = Strap to PHY Address 7

Reserved

17.9

17.8

B-CAST_OFF

Strap-In Status

Reserved

1 = Strap to B-CAST_OFF

If bit is ‘1’, PHY Address 0 is non-broadcast.

Reserved

RW

RO

RW

RW

RW

RW

RW

RW

RW

RW

RO

RO

RO

RO

KSZ8051MNLU/KSZ8051RNLU

Default

0

0_0000

0000h

0000_0

0

0

0

0

0

0

0_00

0

1

February 17, 2013 43 Revision 1.0

Micrel, Inc.

Address

17.7

17.6

17.5

17.4:2

17.1

17.0

Name

MII B-to-B

Strap-In Status

RMII B-to-B

Strap-In Status

Description

1 = Strap to MII back-to-back mode

This bit applies only to KSZ8051MNLU.

1 = Strap to RMII Back-to-Back mode

This bit applies only to KSZ8051RNLU.

1 = Strap to NAND tree mode NAND Tree

Strap-In Status

Reserved

RMII Strap-In

Status

MII Strap-In

Status

Reserved

1 = Strap to RMII mode

This bit applies only to KSZ8051RNLU.

1 = Strap to MII mode

This bit applies only to KSZ8051MNLU.

Mode

RO

RO

RO

RO

RO

RO

Register 18h – Expanded Control

18.15:12

18.11

Reserved

EDPD

Disabled

18.10 100Base-TX

Latency

Reserved

Energy-detect power-down mode

1 = Disable

0 = Enable

See also register 10h, bit [4] for PLL off.

1 = MII output is random latency

0 = MII output is fixed latency

For both settings, all bytes of received preamble are passed to the MII output.

This bit applies only to KSZ8051MNLU.

18.9:7

18.6

18.5:0

Reserved

10Base-T

Preamble

Restore

Reserved

Reserved

1 = Restore received preamble to MII output

0 = Remove all seven bytes of preamble before sending frame (starting with SFD) to MII output

This bit applies only to KSZ8051MNLU

Reserved

RW

RW

RW

RW

RW

RW

Register 1Bh – Interrupt Control/Status

1B.15

1B.14

1B.13

Jabber

Interrupt

Enable

Receive Error

Interrupt

Enable

Page Received

Interrupt

Enable

1 = Enable jabber interrupt

0 = Disable jabber interrupt

1 = Enable receive error interrupt

0 = Disable receive error interrupt

1 = Enable page received interrupt

0 = Disable page received interrupt

1B.12

1B.11

Parallel Detect

Fault Interrupt

Enable

Link Partner

Acknowledge

Interrupt

Enable

1 = Enable parallel detect fault interrupt

0 = Disable parallel detect fault interrupt

1 = Enable link partner acknowledge interrupt

0 = Disable link partner acknowledge interrupt

RW

RW

RW

RW

RW

(1)

KSZ8051MNLU/KSZ8051RNLU

Default

0000

1

0

00_0

0

00_0000

0

0

0

0

0

February 17, 2013 44 Revision 1.0

Micrel, Inc.

Address

1B.10

1B.9

1B.8

1B.7

1B.6

1B.5

1B.4

Name

Link-Down

Interrupt

Enable

Remote Fault

Interrupt

Enable

Link-Up

Interrupt

Enable

Jabber

Interrupt

Receive Error

Interrupt

Page Receive

Interrupt

Parallel Detect

Fault Interrupt

Description

1= Enable link-down interrupt

0 = Disable link-down interrupt

1 = Enable remote fault interrupt

0 = Disable remote fault interrupt

1 = Enable link-up interrupt

0 = Disable link-up interrupt

1 = Jabber occurred

0 = Jabber did not occur

1 = Receive error occurred

0 = Receive error did not occur

1 = Page receive occurred

0 = Page receive did not occur

1 = Parallel detect fault occurred

0 = Parallel detect fault did not occur

1 = Link partner acknowledge occurred

0 = Link partner acknowledge did not occur

1B.3

1B.2

1B.1

1B.0

Link Partner

Acknowledge

Interrupt

Link-Down

Interrupt

Remote Fault

Interrupt

Link-Up

Interrupt

1 = Link-down occurred

0 = Link-down did not occur

1 = Remote fault occurred

0 = Remote fault did not occur

1 = Link-up occurred

0 = Link-up did not occur

Register 1Dh – LinkMD Control/Status

1D.15

1D.14:13

1D.12

Cable

Diagnostic

Test Enable

Cable

Diagnostic

Test Result

Short Cable

Indicator

1 = Enable cable diagnostic test. After test has completed, this bit is self-cleared.

0 = Indicates cable diagnostic test (if enabled) has completed and the status information is valid for read.

[00] = Normal condition

[01] = Open condition has been detected in cable

[10] = Short condition has been detected in cable

[11] = Cable diagnostic test has failed

1 = Short cable (<10 meter) has been detected by LinkMD

1D.11:9

1D.8:0

Reserved

Cable Fault

Counter

Reserved

Distance to fault

Register 1Eh – PHY Control 1

1E.15:10 Reserved Reserved

1E.9 Enable Pause

(Flow Control)

1 = Flow control capable

0 = No flow control capability

Mode

(1)

RW

RW

RW

RO/SC

RO/SC

RO/SC

RO/SC

RO/SC

RO/SC

RO/SC

RO/SC

RW/SC

RO

RO

RW

RO

RO

RO

KSZ8051MNLU/KSZ8051RNLU

Default

0

0

0

0

0

0

0

0

0

0

0

0

00

0

000

0_0000_0000

0000_00

0

February 17, 2013 45 Revision 1.0

Micrel, Inc.

Address

1E.8

1E.7

1E.6

1E.5

1E.4

1E.3

1E.2:0

Name Description

Link Status 1 = Link is up

0 = Link is down

Polarity Status 1 = Polarity is reversed

0 = Polarity is not reversed

Reserved

MDI/MDI-X

State

Reserved

1 = MDI-X

PHY Isolate

0 = MDI

Energy Detect 1 = Signal present on receive differential pair

0 = No signal detected on receive differential pair

1 = PHY in isolate mode

0 = PHY in normal operation

Operation

Mode

Indication

[000] = Still in auto-negotiation

[001] = 10Base-T half-duplex

[010] = 100Base-TX half-duplex

[011] = Reserved

[100] = Reserved

[101] = 10Base-T full-duplex

[110] = 100Base-TX full-duplex

[111] = Reserved

Register 1Fh – PHY Control 2

1F.15 HP_MDIX

1F.14

1F.13

1F.12

MDI/MDI-X

Select

Pair Swap

Disable

Reserved

1 = HP Auto MDI/MDI-X mode

0 = Micrel Auto MDI/MDI-X mode

When Auto MDI/MDI-X is disabled,

1 = MDI-X mode

Transmit on RXP,RXM (pins 5, 4) and

Receive on TXP,TXM (pins 7, 6)

0 = MDI mode

Transmit on TXP,TXM (pins 7, 6) and

Receive on RXP,RXM (pins 5, 4)

1 = Disable Auto MDI/MDI-X

0 = Enable Auto MDI/MDI-X

Reserved

1F.11

1F.10

1F.9

1F.8

Force Link 1 = Force link pass

0 = Normal link operation

This bit bypasses the control logic and allows the transmitter to send a pattern even if there is no link.

Power Saving 1 = Enable power saving

0 = Disable power saving

Interrupt Level 1 = Interrupt pin active high

0 = Interrupt pin active low

Enable Jabber 1 = Enable jabber counter

0 = Disable jabber counter

Mode

(1)

RO

RO

RO

RO

RO

RW

RO

RW

RW

RW

RW

RW

RW

RW

RW

KSZ8051MNLU/KSZ8051RNLU

0

0

Default

0

0

0

0

000

1

0

0

0

0

1

February 17, 2013 46 Revision 1.0

Micrel, Inc.

Address

1F.7

1F.6

1F.5:4

Name

RMII

Reference

Clock Select

Reserved

LED Mode

1F.3

1F.2

1F.1

1F.0

Note:

1. RW = Read/Write.

RO = Read only.

SC = Self-cleared.

LH = Latch high.

LL = Latch low.

Disable

Transmitter

Remote

Loopback

Enable SQE

Test

Disable Data

Scrambling

Description

1 = RMII 50MHz clock mode; clock input to XI

(pin 9) is 50MHz

0 = RMII 25MHz clock mode; clock input to XI

(pin 9) is 25MHz

This bit applies only to KSZ8051RNLU.

Reserved

[00] = LED1: Speed

LED0: Link/Activity

[01] = LED1: Activity

LED0: Link

[10], [11] = Reserved

1 = Disable transmitter

0 = Enable transmitter

1 = Remote (analog) loopback is enabled

0 = Normal mode

1 = Enable SQE test

0 = Disable SQE test

1 = Disable scrambler

0 = Enable scrambler

Mode

(1)

RW

RW

RW

RW

RW

RW

RW

KSZ8051MNLU/KSZ8051RNLU

Default

0

0

00

0

0

0

0

February 17, 2013 47 Revision 1.0

Micrel, Inc.

Absolute Maximum Ratings

(1)

Supply Voltage (V

(V

DD_1.2

(V

DDIO,

V

DDA_3.3

IN

)

) ..................................................

−0.5V to +1.8V

) .......................................

−0.5V to +5.0V

Input Voltage (all inputs) ..............................

−0.5V to +5.0V

Output Voltage (all outputs) .........................

−0.5V to +5.0V

Lead Temperature (soldering, 10sec.) ....................... 260°C

Storage Temperature (T s

) ......................... –55°C to +150°C

KSZ8051MNLU/KSZ8051RNLU

Operating Ratings

(2)

Supply Voltage

(V

DDIO_3.3,

V

DDA_3.3

) .......................... +3.135V to +3.465V

(V

DDIO_2.5

) ........................................ +2.375V to +2.625V

(V

DDIO_1.8

) ........................................ +1.710V to +1.890V

Ambient Temperature

(T

A

, Automotive Qualified) .................... –40°C to +85°C

Maximum Junction Temperature (T

J max.) ................ 125°C

Thermal Resistance (

θ

JA

) ......................................... 34°C/W

Thermal Resistance (

θ

JC

) ........................................... 6°C/W

Electrical Characteristics

(3)

Symbol Parameter

I

Supply Current (V

DDIO

, V

DDA_3.3

= 3.3V)

(4)

DD1_3.3V

10Base-T

I

DD2_3.3V

I

DD3_3.3V

I

DD4_3.3V

100Base-TX

EDPD Mode

Power-Down Mode

CMOS Level Inputs

Condition

Full-duplex traffic @ 100% utilization

Full-duplex traffic @ 100% utilization

Ethernet cable disconnected (reg. 18h.11 = 0)

Software power-down (reg. 0h.11 = 1)

Min. Typ.

41

47

20

4

Max. Units

mA mA mA mA

V

V

IH

IL

|I

IN

|

Input High Voltage

Input Low Voltage

Input Current

V

DDIO

= 3.3V

V

DDIO

= 2.5V

V

DDIO

= 1.8V

V

DDIO

= 3.3V

V

DDIO

= 2.5V

V

DDIO

= 1.8V

V

IN

= GND ~ VDDIO

2.0

1.8

1.3

0.8

0.7

0.5

10

CMOS Level Outputs

V

V

OH

OL

Output High Voltage

Output Low Voltage

V

DDIO

= 3.3V

V

DDIO

= 2.5V

V

DDIO

= 1.8V

V

DDIO

= 3.3V

V

DDIO

= 2.5V

V

DDIO

= 1.8V

2.4

2.0

1.5

0.4

0.4

0.3

10 |I oz

| Output Tri-State Leakage

I

LED Output

LED

Output Drive Current Each LED pin (LED0, LED1) 8 mA

Notes:

1. Exceeding the absolute maximum rating can damage the device. Stresses greater than the absolute maximum rating can cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.

2. The device is not guaranteed to function outside its operating rating.

3. T

A

= 25°C. Specification is for packaged product only.

4. Current consumption is for the single 3.3V supply KSZ8051MNLU/RNLU device only, and includes the transmit driver current and the 1.2V supply voltage (V

DD_1.2

) that are supplied by the KSZ8051MNLU/RNLU.

V

V

V

V

V

V

µA

V

V

V

V

V

V

µA

February 17, 2013 48 Revision 1.0

Micrel, Inc.

Symbol Parameter Condition

All Pull-Up/Pull-Down Pins (including Strapping Pins)

pu pd

Internal Pull-Up Resistance

Internal Pull-Down Resistance

V

DDIO

= 3.3V

V

DDIO

= 2.5V

V

DDIO

= 1.8V

V

DDIO

= 3.3V

V

DDIO

= 2.5V

V

DDIO

= 1.8V

100Base-TX Transmit (measured differentially after 1:1 transformer)

V

V

O

IMB

Peak Differential Output Voltage 100

Ω termination across differential output

Output Voltage Imbalance 100

Ω termination across differential output t r

, t f

Rise/Fall Time

Rise/Fall Time Imbalance

Duty Cycle Distortion

Overshoot

Output Jitter Peak-to-peak

10Base-T Transmit (measured differentially after 1:1 transformer)

V

P

Peak Differential Output Voltage 100

Ω termination across differential output

Jitter Added Peak-to-peak t r

, t f

Rise/Fall Time

10Base-T Receive

V

SQ

Squelch Threshold 5MHz square wave

Transmitter – Drive Setting

V

SET

Reference Voltage of I

SET

R(I

SET

) = 6.49k

Ω

REF_CLK Output

50MHz RMII Clock Output Jitter Peak-to-peak

(Applies only to KSZ8051RNLU in RMII –

25MHz clock mode) t

100Mbps Mode – Industrial Applications Parameters

llr

Clock Phase Delay – XI Input to

MII TXC Output

Link Loss Reaction (Indication)

Time

XI (25MHz clock input) to MII TXC (25MHz clock output) delay, referenced to rising edges of both clocks.

(Applies only to KSZ8051MNLU in MII mode)

Link loss detected at receive differential inputs to PHY signal indication time for each of the following:

1. For LED mode 00, Speed LED output changes from low (100Mbps) to high (10Mbps, default state for link-down).

2. For LED mode 01, Link LED output changes from low (link-up) to high (link-down).

3. INTRP pin asserts for link-down status change.

KSZ8051MNLU/KSZ8051RNLU

Min. Typ.

30

39

48

26

34

53

0.95

3

0

2.2

15

0.7

45

61

99

43

59

99

25

400

0.65

300

20

4.4

Max. Units

1.05

2

5

0.5

±0.25

5

73

102

178

79

113

200

2.8

3.5

25

V

% ns ns ns

% ns k

Ω k

Ω k

Ω k

Ω k

Ω k

Ω

V ns ns mV

V ps ns

µs

February 17, 2013 49 Revision 1.0

Micrel, Inc.

Timing Diagrams

MII SQE Timing (10Base-T)

KSZ8051MNLU/KSZ8051RNLU

Figure 11. MII SQE Timing (10Base-T)

t t

Timing Parameter Description

P

WL t

WH t

SQE t

SQEP

TXC period

TXC pulse width low

TXC pulse width high

COL (SQE) delay after TXEN de-asserted

COL (SQE) pulse duration

Min. Typ. Max. Unit

400

200 ns ns

200

2.2

1.0 ns

µs

µs

Table 13. MII SQE Timing (10Base-T) Parameters

February 17, 2013 50 Revision 1.0

Micrel, Inc.

MII Transmit Timing (10Base-T)

KSZ8051MNLU/KSZ8051RNLU

Figure 12. MII Transmit Timing (10Base-T)

t t

Timing Parameter Description

P t

WL

TXC period

TXC pulse width low

WH t

SU1 t

SU2 t

HD1

TXC pulse width high

TXD[3:0] setup to rising edge of TXC

TXEN setup to rising edge of TXC

TXD[3:0] hold from rising edge of TXC t

HD2 t

CRS1 t

CRS2

TXEN hold from rising edge of TXC

TXEN high to CRS asserted latency

TXEN low to CRS de-asserted latency

Min. Typ. Max. Unit

400 ns

200 ns

120

120

0

200 ns ns ns ns

0

600

1.0 ns ns

µs

Table 14. MII Transmit Timing (10Base-T) Parameters

February 17, 2013 51 Revision 1.0

Micrel, Inc.

MII Receive Timing (10Base-T)

KSZ8051MNLU/KSZ8051RNLU

Figure 13. MII Receive Timing (10Base-T)

t t

Timing Parameter Description

t

P t

WL t

WH

RXC period

RXC pulse width low

RXC pulse width high

OD

RLAT

(RXDV, RXD[3:0], RXER) output delay from rising edge of RXC

CRS to (RXDV, RXD[3:0]) latency

Min. Typ. Max. Unit

400

200

200

205

7.2

Table 15. MII Receive Timing (10Base-T) Parameters

ns ns ns ns

µs

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MII Transmit Timing (100Base-TX)

KSZ8051MNLU/KSZ8051RNLU

Figure 14. MII Transmit Timing (100Base-TX)

t t

Timing Parameter Description

P

TXC period

WL t

WH t

SU1 t

SU2 t

HD1

TXC pulse width low

TXC pulse width high

TXD[3:0] setup to rising edge of TXC

TXEN setup to rising edge of TXC

TXD[3:0] hold from rising edge of TXC

TXEN hold from rising edge of TXC t

HD2 t

CRS1 t

CRS2

TXEN high to CRS asserted latency

TXEN low to CRS de-asserted latency

0

0

Min. Typ. Max. Unit

40 ns

10

10

20

20 ns ns ns ns

72

72 ns ns ns ns

Table 16. MII Transmit Timing (100Base-TX) Parameters

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MII Receive Timing (100Base-TX)

KSZ8051MNLU/KSZ8051RNLU

Figure 15. MII Receive Timing (100Base-TX)

t t t t

Timing Parameter Description

P

RXC period

WL t

WH

RXC pulse width low

RXC pulse width high

OD

RLAT

(RXDV, RXD[3:0], RXER) output delay from rising edge of RXC

CRS to (RXDV, RXD[3:0]) latency

Min. Typ. Max. Unit

40 ns

20

20

25

170

Table 17. MII Receive Timing (100Base-TX) Parameters

ns ns ns ns

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RMII Timing

KSZ8051MNLU/KSZ8051RNLU

Figure 16. RMII Timing – Data Received from RMII

Figure 17. RMII Timing – Data Input to RMII

t t

Timing Parameter Description

CYC

Clock cycle

1 t

2 t

OD

Setup time

Hold time

Output delay

Min. Typ. Max. Unit

4

2

7

20

10 13 ns ns ns ns

Table 18. RMII Timing Parameters – KSZ8051RNLU (25MHz input to XI pin, 50MHz output from REF_CLK pin)

t t

Timing Parameter Description

CYC

Clock cycle

1 t

2 t

OD

Setup time

Hold time

Output delay

Min. Typ. Max. Unit

4

2

8

20

11 13

Table 19. RMII Timing Parameters – KSZ8051RNLU (50MHz input to XI pin)

ns ns ns ns

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Auto-Negotiation Timing

KSZ8051MNLU/KSZ8051RNLU

Figure 18. Auto-Negotiation Fast Link Pulse (FLP) Timing

Timing Parameter

t

BTB t

FLPW t

PW t

CTD t

CTC

Description

FLP burst to FLP burst

FLP burst width

Clock/Data pulse width

Clock pulse to data pulse

Clock pulse to clock pulse

Number of clock/data pulses per

FLP burst

Min.

8

55.5

111

17

Typ.

16

2

100

64

128

Table 20. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters

Max.

24

69.5

139

33

Units

ms ms ns

µs

µs

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MDC/MDIO Timing

KSZ8051MNLU/KSZ8051RNLU

Figure 19. MDC/MDIO Timing

Timing Parameter Description

t

P t

MD1 t

MD2 t

MD3

MDC period

MDIO (PHY input) setup to rising edge of MDC

MDIO (PHY input) hold from rising edge of MDC

MDIO (PHY output) delay from rising edge of MDC

Min. Typ. Max. Unit

10

4

5

400 ns ns ns ns

Table 21. MDC/MDIO Timing Parameters

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Power-Up/Reset Timing

The KSZ8051MNLU/RNLU reset timing requirement is summarized in Figure 20 and Table 22 .

Figure 20. Power-Up/Reset Timing

t

Parameter Description

t

VR t

SR

CS t

CH

Supply voltage (V

DDIO,

V

DDA_3.3

Stable supply voltage (V

Configuration setup time

Configuration hold time

DDIO,

V

) rise time

DDA_3.3

) to reset high

Min.

300

10

5

5

Max. Units

µs ms ns ns t

RC

Reset to strap-in pin output 6 ns

Table 22. Power-Up/Reset Timing Parameters

The supply voltage (V

DDIO and V

DDA_3.3

) power-up waveform should be monotonic. The 300µs minimum rise time is from

10% to 90%.

For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500µs. The strap-in pin values are read and updated at the de-assertion of reset.

After the de-assertion of reset, wait a minimum of 100µs before starting programming on the MIIM (MDC/MDIO) interface.

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Reset Circuit

KSZ8051MNLU/KSZ8051RNLU

Figure 21 shows a reset circuit recommended for powering up the KSZ8051MNLU/RNLU if reset is triggered by the power

supply.

Figure 21. Recommended Reset Circuit

Figure 22 shows a reset circuit recommended for applications where reset is driven by another device (for example, the

CPU or an FPGA). At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the

KSZ8051MNLU/RNLU device. The RST_OUT_N from the CPU/FPGA provides the warm reset after power-up.

Figure 22. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output

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Reference Circuits – LED Strap-In Pins

KSZ8051MNLU/KSZ8051RNLU

The pull-up, float, and pull-down reference circuits for the LED1/SPEED and LED0/NWAYEN strapping pins are shown in

Figure 23 for 3.3V and 2.5V VDDIO.

Figure 23. Reference Circuits for LED Strapping Pins

For 1.8V VDDIO, LED indication support is not recommended due to the low voltage. Without the LED indicator, the

SPEED and NWAYEN strapping pins are functional with a 4.7k

Ω pull-up to 1.8V VDDIO or float for a value of ‘1’, and with a 1.0k

Ω pull-down to ground for a value of ‘0’.

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Reference Clock – Connection and Selection

KSZ8051MNLU/KSZ8051RNLU

A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the

KSZ8051MNLU/RNLU. For the KSZ8051MNLU in all operating modes and for the KSZ8051RNLU in RMII – 25MHz Clock

Mode, the reference clock is 25 MHz. The reference clock connections to XI (pin 9) and XO (pin 8), and the reference

clock selection criteria, are provided in Figure 24 and Table 23 .

Figure 24. 25MHz Crystal/Oscillator Reference Clock Connection

Characteristics Value Units

Frequency 25 MHz

Frequency tolerance (max.) ±50 ppm

Table 23. 25MHz Crystal / Reference Clock Selection Criteria

For the KSZ8051RNLU in RMII – 50MHz clock mode, the reference clock is 50MHz. The reference clock connections to

XI (pin 9), and the reference clock selection criteria are provided in Figure 25 and Table 24 .

Figure 25. 50MHz Oscillator Reference Clock Connection

February 17, 2013

Characteristics

Frequency

Frequency tolerance (max)

Value

50

±50

Units

MHz ppm

Table 24. 50MHz Oscillator / Reference Clock Selection Criteria

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Magnetics – Connection and Selection

KSZ8051MNLU/KSZ8051RNLU

A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs exceeding FCC requirements.

The KSZ8051MNLU/RNLU design incorporates voltage-mode transmit drivers and on-chip terminations.

With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential pairs. Therefore, the two transformer center tap pins on the KSZ8051MNLU/RNLU side should not be connected to any power supply source on the board; instead, the center tap pins should be separated from one another and connected through separate 0.1µF common-mode capacitors to ground. Separation is required because the common-mode voltage is different between transmitting and receiving differential pairs.

Figure 26 shows the typical magnetic interface circuit for the KSZ8051MNLU/RNLU.

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Figure 26. Typical Magnetic Interface Circuit

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Micrel, Inc.

Table 25 lists recommended magnetic characteristics.

KSZ8051MNLU/KSZ8051RNLU

Parameter

Turns ratio

Value

1 CT : 1 CT

Test Condition

Open-circuit inductance (min.)

Insertion loss (typ.)

350µH

–1.1dB

100mV, 100kHz, 8mA

100kHz to 100MHz

HIPOT (min.) 1500Vrms

Table 25. Magnetics Selection Criteria

Table 26 is a list of compatible single-port magnetics with separated transformer center tap pins on the PHY chip side that

can be used with the KSZ8051MNLU/RNLU.

Manufacturer Part Number

Bel Fuse

Bel Fuse

Bel Fuse

Delta

HALO

HALO

LANKom

S558-5999-U7

SI-46001-F

SI-50170-F

LF8505

HFJ11-2450E

TG110-E055N5

LF-H41S-1

Pulse

Pulse

Pulse

Pulse

Pulse

TDK

Transpower

H1102

H1260

HX1188

J00-0014

JX0011D21NL

TLA-6T718A

HB726

Wurth/Midcom 000-7090-37R-LF1

Temperature

Range

0°C to 70°C

0°C to 70°C

0°C to 70°C

0°C to 70°C

0°C to 70°C

No

Yes

–40°C to 85°C No

0°C to 70°C No

0°C to 70°C

0°C to 70°C

No

No

–40°C to 85°C No

0°C to 70°C Yes

Magnetic +

RJ-45

No

Yes

Yes

–40°C to 85°C Yes

0°C to 70°C Yes

0°C to 70°C No

–40°C to 85°C No

Table 26. Compatible Single-Port 10/100 Magnetics

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Recommended Land Pattern

KSZ8051MNLU/KSZ8051RNLU

Figure 27. Recommended Land Pattern, 32-Pin (5mm x 5mm) QFN

Red circles indicate thermal vias. They should be 0.350mm in diameter and be connected to the GND plane for maximum thermal performance.

Green rectangles (with shaded area) indicate solder stencil openings on the exposed pad area. They should be 0.87 x

0.87mm in size, 1.07mm pitch.

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Package Information

(1)

KSZ8051MNLU/KSZ8051RNLU

32-Pin (5mm x 5mm) QFN

Note:

1. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com

.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com

Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A

Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

February 17, 2013

© 2013 Micrel, Incorporated.

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