The Design and Linearization of 60GHz Injection Locked

The Design and Linearization of 60GHz Injection Locked
Master’s Thesis
The Design and Linearization of 60GHz
Injection Locked Power Amplifier
Luhao Wang
Department of Electrical and Information Technology,
Faculty of Engineering, LTH, Lund University, 2016.
The Design and Linearization of 60GHz
Injection Locked Power Amplifier
By
Luhao Wang
A Thesis Submitted to
Lund University
in Partial Fulfillment of the Requirements for
the Degree of Master of Science
in Electrical Engineering
August 2016, Lund, Sweden
Supervisor: Leijun Xu
Examiner: Henrik Sjöland
Keywords: Power Amplifier, Injection-locking, Adaptive biasing, predistortion
Abstract
The RF power amplifier is one of the most critical blocks of transceivers, as it is
expected to provide a suitable output power with high gain, efficiency and linearity.
In this paper, a 60-GHz power amplifier based on an injection locked structure is
demonstrated in a standard 65 CMOS technology. The PA core consists of a
cross-coupled pair of NMOS transistors with an NMOS current source. This structure
can achieve large output power and high PAE, but with poor linearity performance. In
order to improve the linearity, several linearization techniques are investigated,
including adaptive biasing and predistortion. The results show that the adaptive
biasing technique can enlarge the linear operation region, but results in poor AM-PM
performance. By instead using the predistortion technique, the AM-PM performance
can be improved, but the linear region only extends slightly. Considering these two
techniques different advantages, we combine them together to improve not only the
linear region but also the AM-PM performance.
Finally, a common source amplifier is added as the first stage. With proper bias, the
linear operation region is then effectively extended by 7.3 dB. This two stage power
amplifier achieves large output power, high linearity and high PAE simultaneously. It
delivers a gain of 20dB, a Psat of 16.3dBm, a P1dB of 15.41dBm, and a PAE of 30%.
I
Acknowledgements
|I would like to take this opportunity to express my gratitude to all those who gave
me a lot of supports during this master thesis.
First of all, I am greatly indebted to Professor Henrik, who has offered my valuable
instructions and suggestions in the academic studies.
I would also gratefully acknowledge the help of my supervisor Xu Leijun, for his
constant encouragement and guidance. Without his patient instruction and expert
guidance, it is impossible for me to complete this thesis.
I also feel grateful to all the teachers and classmates in Lund University. I learned a
lot form all of you.
Finally, I would like to express my gratitude to my beloved parents and girlfriend
who have always been helping me out or difficulties and supporting without a word of
complaint.
II
Contents
Abstract ...................................................................................................................................... i
Acknowledgements ................................................................................................................... II
Contents....................................................................................................................................III
Chapter 1 Introduction................................................................................................................1
1.1 Motivation for 60 GHz CMOS Power Amplifiers ...............................................................1
1.2 About this thesis work ..........................................................................................................4
1.3 Organization .........................................................................................................................4
Chapter 2 RF Power Amplifier Basics .......................................................................................5
2.1 Introduction ..........................................................................................................................5
2.2 Performance metrics of power amplifiers ............................................................................5
2.2.1 Power gain and Bandwidth ........................................................................................ 6
2.2.2 Stability ..................................................................................................................... 6
2.2.3 Power Efficiency ....................................................................................................... 8
2.2.4 Linearity .................................................................................................................... 9
2.3 Class of PA operation .........................................................................................................12
2.3.1 Linear power amplifiers ............................................................................................. 12
2.3.1.1 Class-A Power amplifier ...................................................................................... 13
2.3.1.2 Class-B Power Amplifiers .................................................................................... 15
2.3.1.3 Class-AB Amplifier .............................................................................................. 16
2.3.1.4 Class-C Amplifier................................................................................................. 17
2.3.2 Switching-mode PA................................................................................................. 18
2.3.2.1 Class-D PA ........................................................................................................... 19
2.3.2.2 Class-E Power Amplifier ...................................................................................... 20
2.3.2.2 Class-F Power Amplifier ...................................................................................... 22
2.3.3 Summary .................................................................................................................... 23
2.4 Linearization of RF power amplifier ..................................................................................24
III
2.4.1 Power backoff.......................................................................................................... 24
2.4.2 Feedforward............................................................................................................. 25
2.4.3 Feedback linearization ............................................................................................. 26
2.4.4 Predistortion ............................................................................................................ 27
Chapter 3 Power Amplifier Design ..........................................................................................28
3.1 Power Amplifier specifications .......................................................................................28
3.2 Injection locked power amplifier technique ....................................................................28
3.3 Circuit design ..................................................................................................................30
3.4 Balun design ....................................................................................................................32
3.5 PA Simulation Results........................................................................................................37
Chapter 4 Power Amplifier Linearization ................................................................................40
4.1 Adaptive biasing technique .............................................................................................40
4.2 Pre-distortion technique ..................................................................................................45
4.3 Two-stage PA ..................................................................................................................52
Chapter 5 Conclusion and the future work ...............................................................................56
Reference ..................................................................................................................................58
IV
Chapter 1
Introduction
1.1 Motivation for 60 GHz CMOS Power Amplifiers
Since the invention of radio-frequency (RF) wireless communication more than 100
years ago, mobile phones and other wireless communications products for civilian
consumption have developed rapidly, especially in recent years. From the view of the
personal
mobile
communication,
the
personal-oriented
commercial
mobile
communication technology has expanded from Advantage mobile phone system
(AMPS) to today’s Time division long term evolution (TD-LTE), Frequency division
duplex long term evolution (FDD-LTE) and so on. As another application for wireless
communication, the accessing technology of broadband network is developing rapidly
and it becomes a very active area. In recent years, new technologies are constantly
emerging such as Bluetooth, Ultra wideband (UWB), Radio frequency identification
devices (RFID) and Near field communication (NFC). There are two developing trends:
one is towards low power consumption, including the RFID and NFC technologies;
another is towards high bandwidth such as UWB technology.
Nowadays, with the rapid development of the communication system, the demand
for larger volume and high data rate also rises sharply. The traditional wireless
bandwidth is no longer able to meet some high-rate applications requirement. Based on
Shannon’s theorem, the maximum possible date rate of the communication channel is
given by:
ୗ
ൌ Ž‘‰ ଶ ሺͳ ൅ )
୒
(1. 1)
Where C is the maximum possible data rate, BW is the bandwidth of the channel, S is
the total received power over the bandwidth, and N is the total noise power. It is
obvious that the maximum data rate increases with increasing channel bandwidth.
1
Nowadays, the spectrum around 60GHz is available in various region over the world
shown in Table 1. This available spectrum can enable a huge channel bandwidth (2500
MHz) compared to other wireless communication standards. Hence, it will take
tremendous push function to the development and expansion. The 60GHz-band
short-distance communication technology has become the hot topic of applied research.
An enormous amount of research effort goes into designing mm-wave CMOS circuits
for the up to 7 GHz unlicensed wide band around 60GHz and it brings not only
opportunities but also challenges.
However, the free-space loss in 60 GHz band is high due to the oxygen absorption.
This limits the maximum distance of communication. While this limit distances also
offers interference and security advantages which make 60GHz band has prevailed for
short-range, high data rate and high security wireless communication[1][2][3].
The 60Ghz band is developing under the IEEE standard 802.15.3c, 802.15.11ad, and
the European Computer Manufacturers Association (ECMA) standard 387. And there
are a lot of usages for communication at the band, such as the wireless personal area
networks (WPANs) and wireless local area networks (WLANs). The application areas
is including borne radar, cordless telephone, military use, medical endoscopes,
high-definition TV (HDTV) and so on.
Region
Low frequency
High frequency
Bandwidth
USA
57 GHz
64 GHz
7 GHz
Canada
57 GHz
64 GHz
7 GHz
Europe
57 GHz
66 GHz
9 GHz
Japan
59 GHz
66 GHz
7 GHz
Australia
59.4 GHz
62.5 GHz
3.1 GHz
Table 1. Allocation of spectrum around 60 GHz in the various region around the world[4]
Traditionally, technologies based on SiGe and III-V semiconductor are widely used
in millimeter-wave circuits and communication system. A direct advantage is that the
high power gain and output can be achieved, and solve the signal attenuation problem
2
in such a high frequency band. However, its obvious disadvantage is the high cost
manufacturing and low integration. This greatly limits the mass production and
integration in system level and it can’t realize the real SOC(system on chip). Hence,
CMOS technology due to feasibility, low cost, low power consumption and high
integration has become a trend. Moreover, with the increasing technological
sophistication, the maximum frequency of operation (ˆ୘ ) for the 90nm technology node
is above 100GHz and it continues to increase for smaller nodes. The continuous
progress of the CMOS technology make it possible for the millimeter wave
communication system.
As we have seen, the RF power amplifier as the last building block before the
antenna is critical for wireless communications system. In order to achieve high data
rate, some complex digital modulation schemes are needed, which require highly linear
transmitter to minimize both error vector magnitude (EVM) and spectral
regrowth[5][6]. At the same time, the power amplifier contributes the most of power
consumption of the whole transceiver, which means the efficiency of the power
amplifier is significant, it directly determines the quality of the whole system. Besides
the efficiency and linearity, the size, gain, output power level are also very important.
However, it is impossible to maximize all the design criteria at the same time, some
tradeoffs should be made.
Moreover, the power amplifier design realized by CMOS process at millimeter
wave faces great challenges, such as the low breakdown voltage, parasitic capacitance
and limited gain due to the low transconductance. And with the dimensions of the
CMOS scaling down, the supply voltage dropping results in the low output power and
bad performance as well. For example, with the breakdown voltage dropping, the
supply voltage decreases. In order to maintain the same power as before, the current has
to be increased. The increased current will result in reduction of the gain and
efficiency due to the parasitic resistor; Moreover, to obtain larger DC current, we need
to increase either the amplitude of the input signal or size of the transistor. However,
3
this will reduce the gain and much more parasitic capacitance will be introduced.
1.2 About this thesis work
This thesis is carried out at the Department of information and Electrical
Technology (EIT) at Lund University. The main objective of this thesis project is to
design a 60 GHz-Band injection locked power amplifier and increase linearity while
maintaining the power gain and efficiency. In this thesis, all the circuits are designed by
using the STM 65nm CMOS process.
1.3 Organization
This chapter provides a background based on RF wireless communication system at
60 GHz band frequency, and poses the motivation for CMOS power amplifier.
Chapter 2 reviews the basic structure and performance metrics of RF power amplifier.
And different classes of power amplifiers are discussed as well.
Chapter 3 introduces a power amplifier based on the injection locked structure and
explain its principle of operation.
Chapter 4 describes the linearization theory; several techniques are used to extend
the linear operation. And the simulation results of each techniques are described and
analyzed.
Chapter 5 summarizes the thesis and further work is also discussed.
4
Chapter 2
RF Power Amplifier Basics
2.1 Introduction
RF power amplifier is widely used in the wireless communication system. It is used
to provide the output signal at a desirable gain with high linearity and efficiency. It
should fulfill the output power requirement, which is the greatest different from
small-signal amplifier. Due to the high power output, the transistor normally operates in
large-signal model, and non-linear phenomenon is obvious. The characteristic of RF
power amplifier is low power and large current. In order to withstand large current,
the chip area must be increased. At the same time, parasitic capacitance and resistance
increases as well and it results in degraded operating frequency and efficiency.
Furthermore, the impedances of the input and output are complex number and it is hard
to perform impedance matching. In order to get maximum output power and efficiency,
the matching network is indispensable. A complete RF amplifier is normally consists of
input matching network, DC biasing circuit, transistor amplifier circuit and output
matching network. The basic block of RF power amplifier is shown in Fig. 2.1.
Signal
Source
Input Impedance
Matching Network
Core Circuit
Output Impedance
Matching Network
Bias Circuit
Fig. 2. 1Basic block of RF power amplifier
2.2 Performance metrics of power amplifiers
5
Load
Many metrics are used to evaluate the performance of power amplifiers. In this
section, some of the important metrics are discussed, such as the power gain, efficiency
and linearity.
2.2.1 Power gain and Bandwidth
Power amplifier is required to amplify the power of the input signal. Hence, the level
of the gain is power gain which is defined as the ratio of the output power delivered to
the load to the input power.
ൌ
୔୭୵ୣ୰ୢୣ୪୧୴ୣ୰ୣୢ୲୭୲୦ୣ୪୭ୟୢ
୔୭୵ୣ୰ୟ୲୲୦ୣ୧୬୮୳୲
ൌ
୔౥౫౪
୔౟౤
(2. 1)
If the input is sinusoidal signal and the load is a resistor, the power can be written as:
୭୳୲ ൌ
ෝመ˪
୴
ଶ
ൌ
ෝమ
୴
ଶୖ
ൌ
መ˪మ ୖ
ଶ
(2. 2)
Where ˜ො and ˪መare the amplitudes of voltage and current swing respectively. And for
most of the case, the output impedance is equal to 50 ¡.
The power amplifier bandwidth is the range of frequency for which the PA can obtain
acceptable performance. Normally, it is defined as the frequency range for which the
corresponding gain can be maintained at least 0.7 times of the peak value and is also
called 3-dB bandwidth.
2.2.2 Stability
Stability is an important criteria that should be considered in power amplifier design.
This is important because oscillation is a highly undesirable phenomenon. In such cases
the amplifier performance may change strongly and it may lead to circuitry damage.
6
Zs
Power Amplifier
[S]
Input Impedance
Matching Network
Output Impedance
Matching Network
ZL
*out *L
* s *in
Fig. 2. 2 Block diagram of a one-stage PA
Fig.2. 2 shows the two-port system of power amplifier, Γ
in
and Γ
out
can be
expressed in terms of transistor S-parameters and reflection coefficients ( Γ S and Γ L )
as given:
S12 S 21*L
1 S 22*L
(2. 3)
S12 S 21*S
1 S11*S
(2. 4)
*in
S11 *out
S 22 Oscillations are possible when resistance at the input or output are negative. And
the power amplifier is unconditional stability when it meet the following conditions.
*S ¢1
(2. 5)
*L ¢1
(2. 6)
S12 S 21*L
¢1
1 S 22*L
*in
S11 *out
S 22 (2. 7)
S12 S 21*S
¢1
1 S11*S
(2. 8)
Another way to mathematically express the necessary and sufficient conditions for
unconditional stability is:
1 S11 S 22 '
2
Kf
2
2 S12 S 21
'
S11S 22 S12 S 21 ¢1
7
2
²1
(2. 9)
(2. 10)
2.2.3 Power Efficiency
Power efficiency is one of the most important PA performance metrics. It measures
the ability of converting the DC power to the RF power at the output. An efficient PA
will deliver most of the power drawn from the supply to the load. On the other hand,
power amplifier with low efficiency will result in high level of heat dissipation. In the
wireless transceiver, the power amplifiers are the most power-consuming components.
Hence, to preserve the battery lifetime, the efficiency of PA is of great importance.
There are three definitions are commonly used: the drain efficiency, the power
added efficiency and the overall efficiency.
The drain efficiency of PA is defined as:
K drain
POut
PDC
(2. 11)
Where PDC is the DC power supplied to the amplifier, and Pout is useful signal power
delivered to the load. The DC supply power can be written as:
P DC VDC I DC
(2. 12)
An ideal PA has η=100%, which implies that the entire supply power is delivered to
the load. However, this is practically impossible to obtain. The drain efficiency ignores
the input power to the PA, and in most of case, especially the high-frequency power
amplifier, the overall power gain is low, the input power may become a substantial
portion of the output power. The results we got from this definition will be higher than
the real efficiency. In this case, the power added efficiency and the overall efficiency
will be introduced to provide a more accurate measure of PA performances.
Power added efficiency (PAE) is defined as:
PAE
Pout Pin
PDC
(1 1 Pout
)
G PDC
(1 1
)K
G
(2. 13)
Where Pin is the power of the input signal, and G is the overall power gain of the PA.
The power added efficiency is less than the drain efficiency, considering the input RF
8
power. If the power gain is higher than 20dB, the input power can be ignored and at this
time PAE is the same with drain efficiency. While the overall efficiency ( K overall ) is
defined as:
Pout
PDC P in
K overall
(2. 14)
To achieve a high efficiency, the power amplifier is always operated to a point near its
point of saturation. Unfortunately, at the same time, the distortion will occur. Doherty
amplifier circuit topology and Envelope-tracking power supply methods can be
employed to improve the efficiency without sacrificing linearity.
2.2.4 Linearity
Besides efficiency, linearity is another key parameter for evaluating the
performance of the power amplifier. For all the power amplifier, the relationship
between the input and output is non-linear, especially when the signal is large. Assume
the amplifier is a memoryless system, the transfer characteristic can be fit by the third
order function approximately.
›ሺ–ሻ ൌ Ƚଵ …‘•ɘ– ൅ Ƚଶ ଶ …‘•ଶ ɘ– ൅ Ƚଷ ଷ …‘•ଷ ɘ–
(2. 15)
If the input signal is sinusoidal waveform, šሺ–ሻ ൌ …‘•ሺɘ–ሻ, the output signal is:
›ሺ–ሻ ൌ Ƚଵ …‘•ɘ– ൅ Ƚଶ ଶ …‘•ଶ ɘ– ൅ Ƚଷ ଷ …‘•ଷ ɘ–
ൌ
where
஑మ ୅మ
ଶ
൅ ቀȽଵ ൅
ቀαଵ ൅
ଷαయ ୅య
ସ
ଷ஑య ୅య
ସ
ቁ …‘•ሺɘ–ሻ ൅
ቁ …‘•ሺω–ሻ ,
αమ ୅మ
ଶ
஑ మ ୅మ
ଶ
…‘•ሺʹɘ–ሻ ൅
…‘•ሺʹω–ሻ
and
஑ య ୅య
ସ
αయ ୅య
ସ
…‘•ሺ͵ɘ–ሻሺʹǤͳ͸ሻ
…‘•ሺ͵ω–ሻ
are
the
fundamental component, second harmonics and third harmonics respectively. As we
have seen, because of its nonlinear characteristics, the amplifier not only amplifies the
input signal but also produce the harmonics. The amplification of the input signal is
ƒଵ ൅ ͵ƒଷ ଷ ȀͶ. If A is small enough, the amplification approximately equals to ƒଵ
which is constant. This means the gain of the amplifier is constant and the amplifier
9
has a good linear behavior. However, as the input signal level increase, ͵ƒଷ ଷ ȀͶ
becomes a substantial portion of this part, and the amplification drops, because
ƒଷ ൏ Ͳ, (ƒଷ ൐ Ͳ would mean that the amplifier oscillates, or that the quiescent point
is close to the breakdown voltage)[7]. This gain compression phenomena is also
called AM-AM distortion. And the concept of 1-dB compression point is proposed,
which is defined as the power level where the amplification is 1dB less than the linear
gain. 1-dB compression point is often used to measure the linearity of the amplifier
and we can obtain this by measurement of output vs. input power. (see Fig. 2. 3).
Non-linear region
1dB
Output power (dBm)
P1dB
1dB compression point
linear region
Input power (dBm)
Figure 2. 4 Output vs. input power and 1-dB Compression point
Besides the AM-AM distortion, the amplifier nonlinearity will also cause the
AM-PM distortion which is a phenomenon that the phase of the output depends on the
level of the input. The AM-PM distortion is caused by the parasitic capacitance
variation, especially the input gate capacitance. In other words, the output phase will
follow the level of the input signal due to the variability of the capacitance and due to
this distortion, the modulation schemes such as OFDM is badly affected.
When the amplifier has two input signals with the same amplitude and similar
frequency simultaneously, i.e. for ୧ ሺ–ሻ ൌ …‘• ɘଵ – ൅ …‘• ɘଶ –. The output can be
calculated by submitting the input signal into the transfer characteristics equation.
10
ଽ
ଽ
ଷ
›ሺ–ሻ ൌ ሺȽଵ ൅ ସ Ƚଷ ଷ ሻ…‘•ɘଵ – ൅ ሺȽଵ ൅ ସ Ƚଷ ଷ ሻ…‘•ɘଶ – ൅ ସ Ƚଷ ଷ …‘•ሺʹɘଵ െ ɘଶ ሻ– ൅
ଷ
ସ
ଵ
ଵ
Ƚଷ ଷ …‘•ሺʹɘଶ െ ɘଵ ሻ– ൅ ଶ Ƚଶ ଶ …‘•ʹɘଵ – ൅ ଶ Ƚଶ ଶ …‘•ʹɘଶ – ൅ ‫ڮ‬
(2. 17)
As can be seen, the output not only consists of the fundamental component (frequencies
ɘଵ , ɘଶ ሻ, their harmonics ( frequencies ʹɘଵ , ʹɘଶ ሻ , but also the result of mixing of
the input tones (frequencies ʹɘଵ െ ɘଶ , ʹɘଶ െ ɘଵ ). Except for the fundamental parts,
the additional signal are generated due to the PA nonlinearity. Of all the possible
intermodulation products, the third order intermodulation component with the
frequencies ʹɘଵ െ ɘଶ and ʹɘଶ െ ɘଵ are the most critical. Because they have large
amplitude and it is almost impossible to filter out as they are close to the carrier
frequencies ɘଵ and ɘଶ , and they can cause interference in multichannel
communication. The IMD3 increases as the input power increases, and it is a theoretical
point at which the desired output signal are equal to the third-order IM. This theoretical
points is the IIP3 and the corresponding output is OIP3. IP3 is also widely used to
evaluate the linearity of PA. A higher IP3 means lower distortion generation and better
linearity performance. Fig.2.5 shows the output spectrum around the input tones,
Fig.2.6 shows the third-order intercept point.
Output power (dBm)
Fundamental components
IM3
IM5
IM5
3¹1-2¹2 2¹1-¹2
¹1
¹2
2¹2-¹1 3¹1-2¹2
Fig. 2. 5 shows the output spectrum around the input tones
11
desired linear output
Output power (dBm)
OIP3
IM3
product
Input power (dBm)
IIP3
Fig. 2. 6 The third-order intercept point
2.3 Class of PA operation
The power amplifier can be divided into two types: Linear amplifiers and
switching-mode amplifiers. Conventional linear amplifiers include Class-A, Class-AB,
Class-B, and Class-C amplifiers and the transistor acts as a current source. These
amplifiers can achieve high linearity with low efficiency. Switching-mode amplifiers
include Class-D, Class-E, and Class-F amplifiers and the transistor acts as a switch.
Theses amplifiers can achieve high efficiency at the price of linearity.
2.3.1 Linear power amplifiers
For the linear power amplifiers, the output signal is a linear function of the input
signal. Class-A, Class-AB, Class-B and Class-C amplifiers can be seen as linear
amplifiers and they have almost the same configuration which is shown in Fig 2.7.
12
Vdd
RF choke
DC
blocking
capacitor
Vout
Vin
Rload
Fig. 2. 7 Typical configuration of class-A power amplifier
This circuit consists of a transistor, a RF choke, a DC blocking capacitor, a parallel
LC tank and the load. The transistor remains in saturation region is used as a current
source, driving a controlled current into the load network, and this current has the same
shape with the input signal. The RF choke is a large inductor which provides the
constant DC current to the transistor and also prevent the AC signal leaking into the
supply. DC blocking capacitor blocks the DC current flowing into the load. The parallel
LC tank tuned to be resonant at the fundamental frequency is used to filter out the
out-of-band emission result from the non-linearity of the transistor[8][9].
2.3.1 .1 Class-A Power amplifier
Class-A power amplifier is the simplest, but has the highest linearity power amplifier
over the other classes of operation. And it is similar with the small-signal amplifier.
The main difference is the signal current in the small-signal amplifier is small, it can’t
affect the biasing condition. But in power amplifier, in order to maximize the efficiency,
the signal current may become a substantial portion of the biasing current and thus the
certain distortion is inevitable.
13
VD
Vdd
t
ID
IDC
t
V0
0
t
Fig. 2. 8 Voltage and current waveforms of an ideal class-A power amplifier
Class-A power amplifier achieve high linearity at the cost of efficiency. We can
analyze the efficiency quantitatively, assuming that the power amplifier is perfectly
linear, and the input is sinusoidal. The drain current of the transistor consists of the
quiescent current and the signal current.
ୈୗ ሺ–ሻ ൌ ୈୗǡ୕ ൅ ˪෡ୢ •‹ɘ଴ –
(2. 18)
Where IDS,Q is the quiescent current, ˪෡ୢ is the amplitude of the signal current swing
and ɘ଴ is the signal frequency. The output voltage equals the signal current times load
resistance.
଴ ሺ–ሻ ൌ െ˪෡ୢ •‹ɘ଴ –
(2. 19)
The corresponding drain voltage consists of the DC voltage and signal voltage.
ୈୗ ሺ–ሻ ൌ ୢୢ ൅ ଴ ሺ–ሻ ൌ ୢୢ െ ˪෡ୢ •‹ɘ଴ –
(2. 20)
The current and voltage waveforms is shown in Fig 2. 8. It is obvious that both the
current and voltage on the transistor are large than zero during the entire period, which
means the transistor dissipates power all the time.
The drain efficiency of the amplifier is:
Ʉୢ୰ୟ୧୬ǡ୫ୟ୶ ൌ
୔౥౫౪
୔ీి
ൌ
భ෡మ
˪ ୖ
మౚ
୚ౚౚ ୍ీ౏ǡ్
˪෡ ୖ
ൌ ଶ୚ౚ
ౚౚ
ൌ ͷͲΨ
(2. 21)
The class-A amplifier is the most linear amplifier and have the highest gain.
However, its biggest disadvantage is the ideal maximum efficiency of 50%., and any
14
loss will further reduce its efficiency. In addition, the peak voltage across the transistor
of 2Vdd is large. Therefore, the class-A amplifier is usually used in applications
requiring high linearity, high gain, high-frequency operation.
2.3.1.2
Class-B Power Amplifiers
In order to increase the efficiency, the concept of the conduction angle is proposed.
The idea is to bias the transistor with low quiescent voltage and the transistor conducts
only for part of the cycle. In other words, the voltage waveform is the same as class-A
amplifier, but the current waveform has a period time during which the current is equal
to zero. And when it occurs, the voltage always gets the maximum value, so this
technique can increase the efficiency obviously.
For the class-B amplifier, the conduction angle is Ɏ, meaning the transistor conducts
only half of the period. The waveform of the drain voltage and current is shown in Fig.
2.9.
Vin
Vth
t
VDS
Vdd
t
IDS
T/2
t
T
Fig. 2. 9 Voltage and current waveforms of an ideal class-B power amplifier
As we can see, the drain voltage waveform is the same as class-A amplifier, the drain
current clipping occurs when the input signal level is less than the threshold voltage,
and it can be written by:
15
˪෡ •‹ɘ଴ –ǡ‹ˆͲ ൏ ߱‫ ݐ‬൏ ߨ
ୈୗ ሺ–ሻ ൌ ൜ ୢ
Ͳǡ‘–Š‡”™‹•‡
(2. 22)
The fundamental current is shown as below:
ଶ
୘Ȁଶ
‹୤୳୬ୢ ൌ ‫׬‬଴
୘
෡
˪
˪෡ୢ ሺ•‹ɘ଴ –ሻሺ•‹ɘ଴ –ሻ†– ൌ ଶౚ
(2. 23)
The output voltage equals to the current times resistance:
଴ ൌ
˪෡ౚ
ଶ
•‹ɘ଴ –
(2. 24)
Since ଴ ൑ ୢୢ , from the equation above we can get the maximum value for ˪෡ୢ
ଶ୚
˪෡ୢ ୫ୟ୶ ൌ ୖౚౚ
(2. 25)
And the average drain current can be calculated as:
ಘ
෡
ଵ ୘
ன
˪
ଶ୚
തതതത
˪ୢ ൌ ୘ ‫׬‬଴ ୈୗ ሺ–ሻ†– ൌ ଶ஠ ‫׬‬଴౭ ˪෡ୢ •‹ɘ଴ –†– ൌ ౚ ൌ ౚౚ
஠
(2. 26)
஠ୖ
The maximum output voltage swing is Vdd, so the maximum output power is:
୭ǡ୫ୟ୶ ൌ
୚మౚౚ
ଶୖ
(2. 27)
The DC power is given by:
ୈେ ൌ
ଶ୚మౚౚ
஠ୖ
(2. 28)
Thus, the maximum efficiency of the class-B amplifier is:
Ʉ୫ୟ୶ ൌ
୔౥ǡౣ౗౮
୔ీి
ൌ
஠
ସ
ൌ ͲǤ͹ͺͷ(2. 29)
As we have seen, class-B amplifier is much more efficient than class-A amplifier,
and its maximum efficiency reaches to 78.5%. However, the linearity is worse, and
harmonic distortion will occur. Hence, the filter is necessary to eliminate the harmonics.
In other words, the class-B amplifier can achieve increased efficiency at the cost of
reduced linearity.
2.3.1.3 Class-AB Amplifier
The class-AB amplifier is a compromise between class A and class B amplifier in
terms of efficiency and linearity, and it has a conduction angle of Ɏ ൏ ߠ ൏ ʹߨǤ The
maximum drain efficiency is between 50% and 78.5% and the linearity is also between
16
class-A and class-B. The corresponding waveforms are shown in Fig. 2.10.
Vin
Vth
t
VDS
Vdd
t
IDS
t
Fig. 2. 4
Voltage and current waveforms of an ideal class-AB power amplifier
2.3.1.4 Class-C Amplifier
In the Class-C mode, the conduction angle is less than π, and the transistor remains
in the saturation region for less than half of the RF cycle. The overlapping between the
drain voltage and current decreases compared to the Class-A and Class-B mode.
However, due to the fixed maximum drain current, the amount of charge that can be
injected into the load also diminishes and the output power drops. In order to maintain
the output power level, the amplitude of input signal should be increased . In other
words, the overall power gain decreases as the conduction angle. Fig 2. 5 shows the
voltage and current waveforms of a Class-C PA.
17
Vin
Vth
t
VDS
Vdd
t
IDS
t
Figure 2. 6
Voltage and current waveforms of an ideal class-AB power amplifier
The maximum drain efficiency of the amplifier can be calculated from the
following equation:
ଵ
Ʉ୫ୟ୶ ൌ
ସ
஘ିୱ୧୬஘
ୱ୧୬ቀ஘ൗଶቁିቀ஘ൗଶቁୡ୭ୱቀ஘ൗଶቁ
(2. 30)
This equation can be also applied to all types of transconductance amplifiers. Where
Ʌ is the conduction angle, which is 2Ɏ for class-A, Ɏfor Class-B, between Ɏand 2π for
Class-AB and less than π for Class-C.
Besides efficiency, the output power is related to the conduction angle, the
coefficient equation can be specified as:
஘ିୱ୧୬஘
୭୳୲ ‫ ן‬ଵିୡ୭ୱሺ஬Ȁଶሻ
(2. 31)
It illustrates that the maximum efficiency of Class-C power amplifier is 100%.
However, there are several drawbacks for this PA. Firstly, it’s highly non-linearity, and
secondly, as the conduction angle approaches to zero, the output power delivered to the
load approaches to zero as well. Therefore, the Class-C power amplifier is only suitable
for the system with low power gain and linearization techniques are required.
2.3.2 Switching-mode PA
In contrast to linear power amplifier, where operation in the saturation region, the
18
switching-mode power amplifier is operated in the triode region in order to optimal
efficiency and output power. It is driven with a large amplitude input signal and the
transistor acts as a switch. During the ON-stage, the transistor can be modeled as a
small on-resistance and the voltage across it is zero and during the OFF-stage, the
transistor is cut off and the current is zero. In these amplifiers, the efficiency increases
by reducing the power dissipation. And we can achieve this by eliminating the drain
voltage and current overlapping time. Ideally, the switching-mode power amplifier
can achieve maximum 100% efficiency at the expense of linearity performance.
2.3.2.1 Class-D PA
9LQ
7
0
9GG
7
&
/
5/
9R
0
Fig. 2. 7 The basic configuration of Class-D power amplifier
The transformer coupled Class-D PA is shown in Fig. 2.12. The input transformer
M1 is used to convert the input signal to differential signal. The transistor M1 and M2
are driven by this differential input signal and turn on with no simultaneity. The series
LC tank is tuned to the operation frequency and it is used to remove the harmonic
components, so only fundamental signal can be delivered to the load. The waveform
of voltage and current is shown in Fig. 2.13.
Class-D PAs have some disadvantages. First of all, two transistors and transformers
are needed to implement and this introduces additional power losses. Secondly, in
19
high power and high frequency amplifiers, the devices are typically large in size, it
could result in a large output capacitance which cannot be ignored in practical design.
Furthermore, we assume that the transistors can be toggled between ON and OFF
stage instantaneously, unfortunately, it is hard to realize in practice.
VD1
2Vdd
t
ID1
t
Vo
t
Fig 2. 8 Voltage and current waveforms of an ideal class-D power amplifier
2.3.2.2 Class-E Power Amplifier
The basic configuration of Class-E power amplifier is shown in Fig 2.14.
Vdd
L1
C2
L2
jXL
Vout
Vin
C1
Rload
Figure 2. 9 The basic configuration of Class-E power amplifier
20
The transistor which is controlled by the input signal acts as an ON/OFF switch. The
inductor L1 prevent the AC signal flowing into the supply and provide the DC current as
well. L2 and C2 are designed to be a series LC resonator to filter out the harmonics; The
capacitance C1 consists of two parts, and the parasitic capacitance of the transistor Cds is
also taken into account. This means the power amplifier can tolerate much larger
parasitic capacitance, so the transistor with larger size can be used to optimize the
overall efficiency.
During the time when the switch is OFF, the current flowing into the transistor is
zero; when the switch is On, the voltage across the transistor is zero.
The waveform of class-E PA is shown in Fig. 2.15. It is seen that when the switch is
ON, the voltage across the transistor has already fallen to zero, and there is no
overlapping between the voltage and the current during operation. Class-E amplifier
can achieve maximum 100% efficiency. However, class-E PA has main drawback in
terms of peak voltage. The peak drain voltage is approximately 3.6Vdd, this limited its
application, especially in high frequency system.
Vin
t
Vds
t
Id
t
Fig. 2. 15 voltage and current waveforms of an ideal class-E power amplifier
21
2.3.2.2 Class-F Power Amplifier
The configuration of Class-F power amplifier is shown in Fig 2.16. This circuits
consists of a quarter-wave transmission line and a harmonic resonator. At the center
frequency, the resonator circuit can be seen open for fundamental frequency but short
for the other frequency and the impedance at the fundamental frequency is Rload. At
even harmonics, the quarter-wave transmission line leaves the circuit as a short
circuits and at odd harmonics, the short circuit is transformed into an open circuit.
The voltage and current waveforms of class-F power amplifier is shown in Fig.2.16.
It is capable of high efficiency and it can achieve maximum 100% efficiency, which
means the voltage and current waveforms do not exist simultaneously, as shown in
Fig.2.17. However, it is difficult to design the Class-F amplifier due to the complex
output-matching network.
Vdd
RF chock
¬/4 @ ¹0
Vout
Vin
C
L
Fig. 2. 10 The basic configuration of Class-F power amplifier
22
Rload
Vd
2Vdd
t
Id
t
Vout
t
Fig. 2. 11 voltage and current waveforms of an ideal class-F power amplifier
2.3.3 Summary
The performance comparison in terms of output power, gain, efficiency and
linearity for the different classes of power amplifiers is given in Table 2.1. As
mentioned before, linearity and efficiency are the opposite requirements in power
amplifier design. The efficiency of linear amplifiers decreases from Class-A to Class
C power amplifier, however, when moving from Class-A to Class-C power amplifier,
the power gain decreases and the amplifier trends to the higher nonlinearity. When
design the power amplifier, the linearity and efficiency should be trade-off between the
linear amplifiers and switching-mode amplifiers. While Class-A amplifiers are the most
linear power amplifier, which can achieve a maximum efficiency of 50%.
Switching-mode amplifier can achieve an ideal efficiency of 100%, but it is strongly
non-linear. We can start from the Class-A or Class-AB amplifier and try to find a way
to improve the efficiency, we can also choose the switching-mode configuration as the
starting point in order to obtain high efficiency, and then use some linearization
technology to improve the linearity[10].
23
Table 2. 1 Performances comparison for different classes of PAs
Class
Mode
Conduction
Output
Angle
Power
Ideal Efficiency
Gain
Linearity
Excellent
2π
Moderate
50%
Large
AB
Current
π̚2π
Moderate
50̚78.5%
Moderate
Good
B
Source
π
Moderate
78.5%
Moderate
Moderate
C
0̚π
Small
78.5̚100%
Small
Poor
D
π
Large
100%
Small
Poor
π
Large
100%
Small
Poor
π
Large
100%
Small
Poor
A
E
Switch
F
2.4 Linearization of RF power amplifier
The nonlinear behavior of the RF front-end, especially RF transmitters, can
significantly degrade the overall performance of the wireless systems. The power
efficiency of an RF amplifier is optimal when it is operated near saturation. An
amplifier operating in this nonlinear range generates IM distortion that interferes with
neighboring channels. Therefore, there should be compensation for the nonlinearities
and distortions of the RF transmitter.
Linearization is a systematic approach to reduce an amplifier’s distortion which is
inevitable for enhancing the linearity of an amplifier to the high input power drive
levels and achieving linearity requirements when operating the device over its entire
power range. Linearization allows a PA to generate more power and operate with
higher efficiency for a given level of distortion[11][12] [13].
2.4.1 Power backoff
Power backoff is the simplest and most common linearization technique. It does not
make any changes to the circuit configuration, just shrink the input voltage.
Its main principle can be illustrated by using Taylor series:
୭୳୲ ൌ ଴ ൅ ƒଵ ୧୬ ൅ ƒଶ ୧୬ ଶ ൅ ƒଷ ୧୬ ଷ ൅ ‫ڮ‬
Where Iout is the output current, Vin is the input voltage and I0 is the bias output
24
current which can be easily blocked. As can be seen that, As the amplitude of input
signal decreases, the fundamental part ƒଵ ୧୬ becomes dominant term and the higher
order terms is no longer important as before. And 1dB reduction of the output power
results in 3dB reduction in IM3 and 2dB linearity improvement respectively.
However, this approach also has its drawbacks, Firstly, the system can achieve high
linearity performance at the price of the efficiency. Secondly, it cannot improve the
linearity performance any more beyond a certain range. Hence, for some high
linearity requirements circuit design, this technique is not sufficient, other
linearization techniques has to be employed.
2.4.2 Feedforward
The idea of the feedforward method is to extract and remove the distortion at the
output. Fig.2.18 shows the block diagram of the feedforward linearization method.
The system consists of main amplifier, auxiliary amplifier, attenuator, couplers,
combiner, and delay lines. The couplers is used to split the input signal into two paths,
the delay lines is used for phase-matching and better signal performance can be
achieved. The auxiliary amplifier is used to amplify the error signal.
V in
9D
$
ě
GHOD\
V out
$
9E
GHOD\
9H
ě
$
9F
Fig. 2. 12 The basic block diagram of the feedforward linearization
Assuming that the nonlinear distortion signal can be seen as the sum of linear signal
and error signal.
25
ୟ ൌ ଴ ୧୬ ൅ ୢ
The voltage of node b can be express as:
ୟ
ୢ
ൌ ୧୬ ൅
଴
଴
This error voltage can be get by using the comparator:
ୢ
ୢ
െ ୧୬ ൌ
ୣ ൌ ୠ െ ୧୬ ൌ ୧୬ ൅
଴
଴
Error voltage is amplified by the auxiliary amplifier:
ୢ
ୡ ൌ ଴ ୣ ൌ ଴
ൌ ୢ
଴
Then the amplified signal by main amplifier is combined with amplified error
voltage in opposite phase.
୭୳୲ ൌ ୟ െ ୡ ൌ ଴ ୧୬ ൅ ୢ െ ୢ ൌ ଴ ୧୬
ୠ ൌ
As we can see, the distortion is cancelled out theoretically. And this method is
inherently stable However, it is depend on accurate amplitude and phase matching,
and susceptible to drift and aging. Due to the losses of delay line, couplers and
auxiliary amplifier, the system is low power efficiency.
2.4.3 Feedback linearization
The block diagram of feedback linearization method is shown in Fig.2.19.
This method is based on the feedback loop, which is widely used in control theory.
The output signal is fed back via feedback loop and subtracted from the input signal.
If the gain is high enough, the local feedback can be used for linearization. However,
in RF communication system, the gain is hard-earned, this method suffers the
drawback of gain loss. Furthermore, the delay associated with the feedback loop will
make the system unstable and limit its use to narrowband signals[14][15].
26
Input
Output
PA
Feedback loop
Fig. 2. 19 The basic block diagram of the feedback linearization
2.4.4 Predistortion
The block diagram of predistortion technique is shown in Fig.2.20.
3$
+
Output
Output
Predistorter
Output
=
Output
Input
Input
Input
Input
Fig. 2.20 The diagram of predistortion technique
As we known, at high power level, the power amplifier has gain compression
which leads to signal distortion. In order to address this issue, a predistorter which has
a transfer characteristic inverse to that of amplifier is introduced to the system. The
nonlinear gain compression of the power amplifier is compensated by this predistorter
and the 1 dB compression point is extended. The RF predistortion technique is widely
used in academia community since it has a simple structure and does not suffer a
bandwidth limitation[16].
27
Chapter 3
Power Amplifier Design
3.1 Power Amplifier specifications
Supply Voltage:
1.2V
Frequency:
60 GHz
Power gain:
20 dB
Output power at 1 dB compression: > 11 dBm
Saturated output power:
Power added efficiency:
> 15 dBm
> 10%
Input and output impedance:
50Ω
3.2 Injection locked power amplifier technique
In order to reduce the input driving requirement and improve the efficiency, the
injection locked amplifier is investigated which is well-suited for power amplifier
design.
Injection locked technique means the condition in which another self-oscillating
circuit is forced to run at the same frequency as the input signal. A general model for
the injection locked power amplifier is given in Fig.3.1. This positive feedback loop
consists of a nonlinear gain block g(vi,vo) and linear filter H(jω), where the nonlinear
block g(vi,vo) is formed by the cross-coupled devices and H(jω) is implemented by the
matching and load network[17][18].
Without the external current flowing through the PA core, the PA core would self
oscillate at a natural oscillating frequency ω0 if the circuits satisfies the Barkhausen
criterion: The loop gain should be greater than unity and the total phase shift around
the loop has to be multiple of 2π[19].
28
f ˜ H ( jZ0 ) t 1
‘f ‘H ( jZ)
(3. 1)
2kS
(3. 2)
Where k is an integer. When the signal v i with the frequency Z i injects into the
circuit, the output of f has a phase shift with the respect to the input signal, to
compensate this extra phase shift, the H ( jZ ) must change its phase to ensure the
total phase along the loop keep 2kπ, which also makes the oscillator to track the
injected frequency Z i .
Suppose that vi
Vdc VI cos(Zi t ) and vo
VO cos(Zo t M ) , where Vdc is the
DC point. By using the Taylor series expansion of vi around DC point Vdc. f can be
written as:
f
f (v i , v o )
¦A
m 0
m
cos(mZ0 t mM ) 1 wAm
˜
2 wvi
f
vi Vdc
˜ ¦VI cos[(mZo r Zi )t mM ]
m 0
(3. 3)
Where the coefficient Am is the function of am and VO. And the first part is the
expression for the free-running oscillator, the second term shows the mixer products
due to the presence of the injected signal.
If the first term is much smaller than the second term, g is almost in proportion to
the magnitude of the injected signal VI, so the magnitude of the output signal V0 can
be written as [20]:
V0 | g ˜ H
VI
2
f
¦B
m
˜ H( jZ0 )
m 0
It is obvious that the output power can be increased by the input power.
vi@¹i
H(jω)
( ω)
H(j
f(v
f vii,v
f(
,v00))
vo@¹o
Fig. 3.1 Model of the proposed injection locked power amplifier
29
The Adler’s equation can be used to establish the lock-in range [21]:
dT
dt
Z 0 Z1 Z 0 I INj
2QIT
sin T
(3. 4)
Where I INj is the peak current of the injected signal, I T is the peak current
through the negative resistance and T is the phase difference between V0 and VINJ .
At steady state, dT / dt
0 and sin T d 1 , the lock-in range is:
Z L Z 0 Z1
Z 0 I INJ
2QIT
(3. 5)
This equation implies that the injection locking only occur within a finite frequency
range around the natural oscillation frequency and the locking range is positively
correlated with the injection current. Hence, to expand the locking range, we can
increase the size of the injection devices and decrease the cross-coupling pairs in
design.
3.3 Circuit design
The power amplifier based on injection-locked structure will redound to improve
gain and efficiency by means of reducing the input driving requirement. The schematic
of the implemented PA is shown in Fig.3.2.
30
Fig. 3.2 The schematic of injection locked power amplifier
This PA core circuit consists of a NMOS cross-coupling pair together with NMOS
transistors used for signal current injection. Among which M1 and M2 are driving
transistors. M3 and M4 are the key devices, this cross-coupling pairs turn the circuits
into an injection locked oscillator. An NMOS current source is used to control the free
running output voltage swing of the PA core. The circuit is free running until the
injected current is large enough to lock the output signal to the input signal.
To avoid self-oscillation, two conditions should be guaranteed. Firstly, we need to
ensure that when the PA is powered up, the input power will always be available and
large enough to make the output signal follow the input signal. Besides, a power-down
mechanism is introduced to avoid free oscillation when PA is not driven. During power
down, M5 is turned off and M6 will pull the local ground node to Vdd., and the entire
amplifier will be shut down[22][23].
Fig.3.3 plots the power gain versus different transistor size with a fixed bias voltage.
In the left figure, the width of M3 and M4 is set to 30μm and the width of M1 and M2
is set to 60μm in the right figure. It is found that the power gain increases at first, then
decreases with increasing of the transistor size. This is because the transistor size
determines its current. For the injection transistor M1 and M2, the large width results
31
to the larger injection current and power gain. However, due to the circuit limitation,
the power gain decreases finally. As mentioned before, the locking range is positively
correlated with the injection current and inversely proportional to the core current. In
order to improve the bandwidth, we decrease the size of the cross-coupled pair.
However, the cross-coupling pairs M3 and M4 provide for a negative resistance, and
too small transistor is unable to satisfy the oscillatory condition. Hence, we need to
make our selection according to actual situation.
20
35
Power Gain (dB)
Power Gain (dB)
30
25
20
15
15
10
50
55
60
65
70
75
80
10
15
W1 and W2 (um)
20
25
30
35
40
W3 and W4 (um)
Fig. 3.3 Power gain versus different device size with Vb
0.3V and Vc
0.8V
According to the simulation and optimization, the width/length of the injection
driving transistors M1,M2 is 60μm/65nm, with the figure number of 50; the
width/length of the cross-coupling pair M3,M4 is 30μm/65nm, with the figure number
of 50; and for the current source M5 is 120μm/65nm, with the figure number of 120.
3.4 Balun design
As a passive component, balun plays an key role in the power amplifier design. In
practice, it performs the following functions: First of all, the differential structure is
designed in the power amplifier core in order to reject the common-mode signal and
noise, improve the output voltage swing and reduce the interference to the external
circuit resulting from the power amplifier. However, the load of the power amplifier is
32
always single-ended, A balun is necessary to transfer between the single-ended and
differential signals. Furthermore, as we known, in order to obtain the maximum
output power, matching network is needed to transform the optimum load to a 50Ω
load, and the balun can realize this function perfectly. Finally, balun also plays a role
in isolation.
The balun is a three-port device which is used to convert the single-ended signal
into differential signals. The amplitude of the output differential signals is equal and
the phase is opposite, so when analyzing the balun performance, the amplitude and
phase imbalance are the main figures of merit. Furthermore, the insertion loss is also a
important parameter which measures the energy absorbed when the signal passing
through the balun[24].
The balun is designed based on the Marchand type. The circuit diagram of
Marchand balun with centre-tap is given in Fig 3.4.
,QSXW
3ULPDU\
&
6HFRQGO\
2XWSXW
%LDV
6HFRQGO\
2XWSXW
&
3ULPDU\
Fig 3.4 The Schematic diagram of Marchand balun
The balun consists of two symmetrical quarter-wave coupled lines, where the
primary line is open-ended and the two secondary lines are connected to the two
output ports respectively, and the top two metal layers M6 and M7 are used as
broadside coupled lines. Center-tap for DC bias is added and two symmetrical
capacitances are connected between the center-tap and the ground to provide an AC
33
path for the signal[25]. The balun is symmetric and the layout is shown in Fig.3.5.
Fig.3.5 The layout of the balun
The carrier frequency of the balun is 60 GHz, and, the width and length of the
coupled lines are optimized by the EM simulation in ADS, and the simulated
S-parameters, insertion loss and imbalances are shown in Fig.3.6-3.8.
-4
-6
S11 (dB)
-8
-10
-12
-14
-16
-18
50
52
54
56
58
60
62
64
Freq (GHz)
Fig.3.6 S11 for the input balun
34
66
68
70
3.5
3.0
IL (dB)
2.5
2.0
1.5
1.0
50
52
54
56
58
60
62
64
66
68
70
Freq (GHz)
1.8
0.55
1.6
0.50
1.4
0.45
1.2
0.40
1.0
0.35
0.8
0.30
0.6
0.25
0.4
0.20
0.2
0.15
50
o
0.60
Phase Imbalance ( )
Amplitude imbalance (dB)
Fig.3.7 Insertion loss for the input balun
52
54
56
58
60
62
64
66
68
0.0
70
Freq (GHz)
Fig.3.8 Amplitude and phase imbalance for the input balun
The input balun is matched to the input impedance of the PA core. S11 of the
designed input balun is about -18dB at 60 GHz. The insertion loss (IL) is less than
1.5dB in the frequency ranging from 56 GHz to 64 GHz and the minimum insertion
loss is 1.21dB at 60 GHz. In this frequency band, the amplitude imbalance is 0.3 dB
and the phase imbalance is less than 0.25°.
Comparing with the input balun, the output balun is matched to the output
impedance of the PA core, and the width is thicker in order to flow through higher
current. The simulation results of the output balun are shown in Fig.3.9-3.11. S11 is
about -24dB at 60 GHz, the insertion loss is less than 1.5dB in the frequency ranging
35
from 58 GHz to 62 GHz and the minimum insertion loss is 1.32dB at 60 GHz. In this
frequency band, the amplitude imbalance is 0.9 dB and the phase imbalance is less
than 0.7°.
-5
S11 (dB)
-10
-15
-20
-25
50
52
54
56
58
60
62
64
66
68
70
Freq (GHz)
Fig.3.9 S11 for the output balun
4.0
3.5
IL (dB)
3.0
2.5
2.0
1.5
1.0
50
52
54
56
58
60
62
64
66
Freq (GHz)
Fig.3.10 Insertion loss for the output balun
36
68
70
2.5
0.6
1.5
o
0.4
Phase Imbalance ()
Amplitude Imbalance (dB)
2.0
1.0
0.5
0.2
0.0
-0.5
50
52
54
56
58
60
62
64
66
0.0
70
68
Freq (GHz)
Fig.3.11 Amplitude and phase imbalance for the input balun
3.5 PA Simulation Results
The circuit is simulated by using ADS tools, and the single tone harmonic balance
simulation is done to get the transducer power gain and the power efficiency. Fig.3.12
shows the transducer power gain. As expected, the gain decreases as the output power
increases. At 1-dB compression point, the output power is 7.9 dBm.
Power Gain (dB)
20
15
10
5
-10
-5
0
5
10
output Power (dBm)
Fig.3.12 Power gain of PA
37
15
20
Fig 3.13 shows the power added efficiency of the amplifier. The efficiency is directly
proportional with the output power. The PAE can reach its maximum value of 40% at
the output power of 15dBm and at 1-dB compression point, the PAE is 6%.
40
PAE (%)
30
20
10
0
-10
-5
0
5
10
15
20
Output Power (dBm)
Fig.3.13 PAE of the PA
Fig.3.14 shows the power gain reduction and phase shift as the function of the input
power. With the increasing of input power, the phase difference increases at first, and
then decreases. When the input power increases to -11dBm, the gain difference is less
than 1dB. And the phase shift increases as the input power increases. In the input
power ranging from -25dBm to -10dBm, the AM-PM characteristics drops from -0.3噛
to -3.8噛.
38
0
0.0
-1
AM-PM (degrees)
Gain Variation (dB)
0.5
-0.5
-1.0
-1.5
-25
-2
-3
-20
-15
-10
Pin (dBm)
-4
-25
-20
-15
-10
Pin (dBm)
Fig. 3.13 AM to AM and AM to PM versus input power
The results show that the linearity performance of the power amplifier leaves much
to be desired and cannot meet demand completely. In order to improve the available
linear output power and the overall efficiency, the linearization enhancement technique
is necessary. We will put emphasis on discussing the linearization of the power
amplifier in next chapter.
39
Chapter 4
Power Amplifier Linearization
4.1 Adaptive biasing technique
To ensure the power gain is maintained in the whole amplification process, the bias
is operated at a high quiescent point with the high output power. However, when the
power is low, due to this high voltage bias, significant amount of power is wasted and
the efficiency will be decreased greatly. Now adaptive biasing technique is proposed
to solve this problem. Fig.4.1 shows the basic block diagram of this method. Actually,
it is a feedback regulation. The dynamic bias control unit can track and monitor the
output power in real time and then adjust the bias adaptively. The bias is lower than
the normal value at low power level and it gradually increases with the increasing of
the output power. As we known, after the amplifier reaches to its 1-dB gain
compression point, the gain will be degraded. Fortunately, the increased adaptive bias
will boost the power gain in order to compensate the gain reduction. In this way, the
linear operation region extends and both the linearity and efficiency is improved at the
same time[26][27][28].
PA In
RF Power
Vb
En
PA Out
PA
Dynamic Bias
Control
Fig.4.1 The basic block diagram of adaptive biasing technique
40
The schematic of the dynamic bias control part is shown in Fig.4.2.
9G
0
0
2XWSXW
2XWSXW
9H
0
5
E
9E
5
7R9E
&
Figure 4.2 Schematic of the dynamic bias control part
Where, Vb is the bias of the injection transistor. Two low-threshold PMOS
transistors M7 and M8 are connected to the differential output in order to sense the
output level. These two transistors with small size and little current consuming have
little influence on PA’s performance. These transistors will turn off when the output
power is low. At this time, the feedback voltage can be expressed as the following
equation:
Vb
R2
Vb1
R1 R2
(4. 1)
It is obvious that the starting point of the feedback voltage Vb is determined by
the voltage Vb1 and the resistor network. As the output voltage swing becoming
larger than the threshold voltage, the feedback loop turns on and the feedback voltage
can be calculated by using the following equations:
Vb
R2
Vb1 ib ˜ Z b
R1 R2
41
(4. 2)
ip ib
Zb
Vb1 Vb
R1
( R1 // R2 ) //(
(4. 3)
1
)
jZCb
(4. 4)
Where ib and Z b represent the total current and impedance at the node b. It is
apparent that the feedback voltage Vb increases with the increasing power level. And
the same method is applied to Vc , which is the bias voltage of the current source.
Fig.4.3 shows the power gain versus different bias voltage. As we have seen, the
power gain is proportional to the bias voltage.
30
20.4
28
Power Gain (dB)
Power Gain (dB)
20.3
26
24
20.2
20.1
22
20
0.30
0.32
0.34
0.36
0.38
0.40
20.0
0.80
0.42
Vb Bias (V)
0.82
0.84
0.86
0.88
0.90
Vc Bias (V)
Fig.4.3 Power gain versus different bias voltage
Fig.4.4 plots the bias voltage versus different input power. When the power is low,
the feedback loop doesn’t work and the bias voltage maintain its original value. When
the input power is more than -20dBm, the bias voltage Vb and Vc increase rapidly.
As mentioned before, the power gain is proportional to the bias voltage. Hence, the
power gain will increase greatly at the high power level by adjusting the bias voltage
and this increased power gain can compensate for the gain reduction in order to extent
the linear region.
42
0.90
0.42
0.40
0.88
Vc bias (V)
Vb bias (V)
0.38
0.36
0.86
0.84
0.34
0.82
0.32
0.30
-30
-20
-10
0
0.80
-30
10
-20
-10
0
10
RFpower (dBm)
RFpower (dBm)
Fig.4.4 Bias voltage versus different input power
Fig.4.5 shows the power gain of PA with and without the adaptive biasing operated
at 1.2V supply. When the output power is low, the power gain is the same as before
because the transistors M7 and M8 are closed and the feedback loop doesn’t work. As
the power increases, because of the increased bias voltage, the power gain is boosted
obviously. It starts to compress eventually until the maximum value of 21.3 dB is
experienced. However, the parasitic capacitance in the layout will mitigate this
overshoot in real design. The 1dB compression point increases from 7.9 dBm to
11.5dBm, and in this region, the power gain keep steady. In another words, the linear
operation region is effectively extended by 3.6 dB.
43
25
20
Gain (dB)
15
without adaptive biasing
wiith adaptibe biasing
10
5
0
-10
-5
0
5
10
15
Output power (dBm)
Fig.4.5 Simulated power gain with and without the adaptive biasing
Fig.4.6 compares the power added efficiency with and without the adaptive biasing.
As we mentioned before, the PAE has obviously positive correlation with the power
gain. Hence, the increased power gain results in the improvement of PAE. The PAE
can reach its maximum value of 40 % at 15dBm of the output power and it can get the
value of 17 % at 1-dB compression point. In conclusion, this technique improves not
only the performance of linearity but also the efficiency.
40
without adaptive biasing
wiith adaptibe biasing
PAE (%)
30
20
10
0
-10
-5
0
5
10
15
Output power (dBm)
Fig.4.6 Simulated PAE with and without the adaptive biasing
44
Fig.4.7 plots the power gain variation and phase shift as the function of the input
power. These curves represent the AM to AM and AM to PM characteristics under
different conditions when the adaptive bias is on and off, respectively. In the input
power ranging from -25dBm to -20dBm, the results of the original and adaptive
biasing is almost the same. When the adaptive bias is on, the gain variation increases
at first, then decreases with the increasing of input power and the maximum gain
variation reaches to 1.25 dB. But when relatively large changes in bias levels occur,
undesired phase shift occurs as well. The performance of AM to PM with adaptive
biasing is worse than the original power amplifier, and the maximum phase shift
reaches to -6.6 degrees.
1.5
0
without adaptive biasing
wiith adaptibe biasing
-1
1.0
AM-PM (degrees)
Gain Variation (dB)
-2
0.5
0.0
-0.5
-1.0
-1.5
-25
-3
-4
-5
without adaptive biasing
wiith adaptibe biasing
-6
-20
-15
-7
-25
-10
Pin (dBm)
-20
-15
-10
Pin (dBm)
Fig. 4.7 AM to AM and AM to PM versus input power
4.2 Pre-distortion technique
As we mentioned in chapter 2, power amplifier exhibiting the gain compression at
saturation region results in distortion. And a predistorter with a gain expansion
characteristic is introduced to the system in order to compensate for the gain lost in
compression and extend the linear output region. In this paper, a predistortion
45
linearizer using a shunt cold-mode structure is proposed. The schematic is shown in
Fig.4.8.
3LQ
3RXW
3$
5
9S
9V
5
&
&
Fig.4.8 Schematic of the pre-distortion linearizer.
This circuit consists of a cold-mode operation transistor, two resistors and two
bypass capacitors. It can be expressed as the combination of a capacitor ( C off ) series
with a small resistor ( Roff ) and a current source in parallel. The equivalent circuit
model is shown in Fig.4.9.
5RII
,GV
5RII
9GV
5GV
&RII
&RII
Fig. 4.9 The equivalent circuit model of predistortion linearizer
Consider that the variations of C off and Roff are much smaller than the variation
of Rds . So the C off and Roff are assumed to be constants and gain ( S 21 ) can be
expressed by:
46
S 21
2
(4. 5)
§
·
¨
¸
1
1
¨
¸
2 Z0 ¨
¸
1
Rds
((
) Roff ) ¸
¨¨
¸
jZC off
©
¹
Where Z0 is a 50Ω characteristic impedance and the drain to source resistor Rds is
the key element of the linearizer which can be expressed by using the equation below.
Rds
1
wI ds
wVds
(4. 6)
Where the wI ds / wVds indicates the slope of its DC-IV curve. As we have seen,
there is negative correlation between Rds and the slope of DC-IV curve. In Fig.4.10,
when the input power is low, the transistor operates in the linear region and Rds is
constant. As the input power increases, the slop of DC-IV curve decreases especially
near the pinch-off voltage which results in the increased Rds [29][30][31].
12
10
Ids(mA)
8
6
4
2
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Vds (V)
Fig.4.10 DC-IV curve of the transistor with V p
47
1 V and Vs
0.6 V
Fig.4.11 shows the gain expansion of the predistortion linearizer. At low input
power, Rds is a constant. As the input power increases, due to the gain is
proportional to the Rds , the increased Rds will result in 1.4dB gain expansion.
-0.2
-0.4
Gain Expansion (dB)
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
-30
-20
-10
0
10
Input Power (dBm)
Fig. 4.11 Gain expansion of the predistortion linearizer
Fig.4.12 shows the power gain of PA with and without the predistortion linearizer.
The result implies that the linearizer adopts insertion loss of 2 dB and at 1-dB
compression point, the output power is 9 dBm and the linear operation region is
extended by 1.1 dB. The improvement is not obvious because the original power gain
has shown a sharp decline at the high output level, and the output power with
predistortion linearizer is always less than the original power amplifier. Hence, its
improvement of the linear region is limited to the original output power level.
48
Power Gain (dB)
20
15
without predistortion linearizer
wiith predistortion linearizer
10
5
-10
-5
0
5
10
15
20
output Power (dBm)
Fig.4.12 Power gain of PA with and without the predistortion linearizer
PAE versus output power has been investigated in Fig. 4.13. When the predistortion
linearizer is introduced, PAE slightly decreases. But it improves PAE@OP1dB from 6%
to 9.5%.
40
without predistortion linearizer
wiith predistortion linearizer
PAE (%)
30
20
10
0
-10
-5
0
5
10
15
20
Output Power (dBm)
Fig.4.13 PAE of PA with and without the predistortion linearizer
Fig4.14 shows the AM-AM and AM-PM with the predistortion linearizer. Unlike
the previous results, the result of the phase shift is positive value. The phase shift is
within the range from 0 to 1.75 degrees.
49
2
1
AM-PM (degrees)
Gain Variation (dB)
0
-1
1
-2
-3
-20
-15
-10
-5
0
-20
Pin (dBm)
-15
-10
-5
Pin (dBm)
Fig.4.14 AM-AM and AM-PM with the predistortion linearizer
As we mentioned before, PA with adaptive biasing technique can extend the linear
region but results in worse AM-PM performance and PA with predistortion linearizer
will improve the AM-PM performance but it is limited to the low output power. Now,
we combine these two techniques together to improve not only the linear region but
also the AM-PM performance. Due to the insertion loss, the bias voltage is required to
increase in order to maintain the gain of 20dB. Now, the gain and PAE of the power
amplifier is shown in Fig.4.15. Compared with the results we got before, the power
gain has delivered an obvious boost for the output power from 0dBm to 10dBm. This
PA delivers a P1dB of 11.5dBm, and a PAE of 13.5%.
50
40
25
35
30
25
15
20
Power gain
PAE
15
PAE (%)
Power Gain (dB)
20
10
10
5
5
-10
0
-5
0
5
10
15
output Power (dBm)
Fig.4.15 Gain and PAE of PA with adaptive biasing and predistortion technique
Fig.4.16 shows AM-AM and AM-PM performances of PA with adaptive biasing
and predistortion technique. In the input power ranging from -20dBm to -15dBm, the
gain variation increases from 0.5dB to 1.45dB, and then it drops with the increasing
of the input power. When the input power is larger than -8.5dBm, then gain variation
is less than -1dB. And AM-PM performance is improved a lot now. The phase shift is
within the ranging from -1.75 to 0.5 degrees.
1
0
AM-PM (degrees)
Gain Variation (dB)
1
-1
0
-1
-2
-3
-20
-15
-10
-2
-20
-5
-15
-10
Pin (dBm)
Pin (dBm)
Fig. 4.16 AM-AM and AM-PM of PA with adaptive biasing and predistortion technique
51
-5
4.3 Two-stage PA
In this section, two-stage power amplifier is proposed and its schematic is shown in
Fig.4.17. The first stage circuit consists of a transistor, an inductor and a DC blocking
capacitor is added between the input and injection-lock PA. The transistor is used as a
current source, driving a controlled current into the load. The inductor provides the
constant current to the transistor and DC blocking capacitor blocks the DC current
flowing into the load. And the two amplifier stages are connected without any
matching network. Furthermore, a voltage bias with a DC feed is added at the gate of
the first stage. The results show that the power gain almost remains the same level and
it is little affected by this voltage bias. However, this bias had significant effect on
efficiency and linearity of the power amplifier. When this bias increases from 0.4V to
0.9V, PAE drops from 31% to 22%, but the AM-PM performance is improved
obviously. As we mentioned before, efficiency and linearity have the opposite
tendency, and a tradeoff must be made. In this thesis, we set voltage bias equal to
0.6V in order to achieve high linearity and high efficiency at the same time.
9
/
3LQ
9GG
/
,QMHFWLRQ
ORFNHG3$
&
3RXW
Fig. 4.17 The schematic of two-stage PA
Fig 4.18 shows the gain of the both two PA stages. As we can see, the first stage
and injection-locked stage deliver a gain of 8dB and 12dB respectively. In the output
52
power ranging from -10dBm to 0dBm, power gain is maintained constant. With the
increasing of the output power, the gain of the injection-locked stage decreases.
Fortunately, the first stage delivers an expansion gain at the high power level. When
the output power is 15dBm, its gain can get almost 12dBm. And the first-stage
expansion gain can boost the overall power gain in order to compensate the
second-stage gain reduction.
12
Gain (dB)
10
8
6
The first stage
The Injection-locked stage
4
2
-10
-5
0
5
10
15
Output Power (dBm)
Fig.4.18 The schematic of two-stage PA
The overall power gain is shown in Fig.4.19. It is obvious that the first-stage
expansion gain is matched to the gain reduction of the injection-locked stage perfectly.
In the output power ranging from -10dBm to 10dBm, power gain is almost maintained
constant. The results indicates that this power amplifier can deliver Psat
and OP1dB
15.41dBm .
53
16.3dBm
20
18
Power Gain (dB)
16
14
The original power amplifier
Two-stage power amplifier
12
10
8
6
-10
-5
0
5
10
15
Output Power (dBm)
Fig.4.19 Power gain of original and two-stage power amplifier
PAE of the two-stage power amplifier is shown in Fig.4.20. The first stage is a
linear PA. As we mentioned in chapter 2, it can get a good linear performance at the
cost of the efficiency. So the introducing of the first stage can result in the reduction
of efficiency. However, due to its linear region extended, we can get PAE from 6% to
30%.
40
The original power amplifier
Two-stage power amplifier
PAE (%)
30
20
10
0
-10
-5
0
5
10
15
20
Output Power (dBm)
Fig. 4.20 PAE of original and two-stage power amplifier
Fig 4.21 shows the AM to AM and AM to PM characteristics versus the different
input power. The AM-AM curve with two-stage is more flatten. Its gain variation is
less than 1dB until the input power reaches to -3dBm. In the input power ranging
from -20dBm to -10dBm, the phase shift is less than 2 degrees and its AM-PM
54
characteristic is better than the original PA as well. With the increasing of input power,
1
8
0
6
Phase shift (degrees)
Power Variation (dB)
the phase difference increases at first, and then decreases.
-1
-2
-3
Two-stage Power amplifier
The original Power amplifier
Two-stage power amplifier
The original power amplifier
4
2
0
-2
-4
-4
-5
-20
-15
-10
-5
0
-20
Output power (dBm)
-15
-10
-5
Output power (dBm)
Fig.4.21 AM-AM and AM-PM of original and two-stage power amplifier
55
0
Chapter 5
Conclusion and the future work
The increasing demands for high data rates are pushing systems to utilize more and
wider bands at higher frequencies. Now, the 60GHz-band short-distance
communication technology has become the hot topic of the wireless researches. As the
last building block before the antenna, RF power amplifier is critical for wireless
communications system.
In this thesis, we have presented the design of a power amplifier based on the
injection-locked technique in 60GHz band. First of all, the basic principle of
the
proposed injection locked power amplifier is analyzed. And then, the balun based on
the Marchand type with centre-tap is introduced. Finally, the simulation results of this
type of power amplifier are got. The results show that the amplifier delivers a gain of
20dB, a Psat of 15dBm and a OP1dB of 7.9 dBm under a 1.2V supply voltage. At 1-dB
compression point, the power added efficiency is 6%.
Moreover, several methods are used to linearize this injection-locked power
amplifier. First of all, adaptive biasing technique is introduced, and the simulation
results show that the linear operation region is extended by 3.6 dB. Next, the
pre-distortion technique is used and due to the output power limitation, the linear
operation region is extended slightly, but its AM-PM performance is improved
obviously. Considering the advantage of these two techniques respectively, we
combine them together to improve not only the linear region but also the AM-PM
performance. The simulation results show that the PA delivers a OP1dB of 11.5dBm, a
PAE of 13.5%, and phase shift is within the ranging from -1.75 to 0.5 degrees. Finally,
two-stage power amplifier is proposed. The first stage and the injection-locked stage
deliver a gain of 8dB and 12dB respectively. At the high output power level, the first
stage produces a boost gain, and this expansion gain compensates the second-stage
56
gain reduction perfectly. The simulation results show that the power amplifier delivers
a gain of 20dB, a Psat of 16.3dBm, a P1dB of 15.41dBm, and a PAE of 30%.
In this thesis, single tone harmonic balance simulation is used to simulate the
amplifier and tuning for harmonic frequency components was discarded. The future
work will focus on two-tone measurements and a good extension of this thesis would
be to make further discussion of IM3.
Furthermore, for the two-stage power amplifier, we analyze and discuss the results
but the operational principle is unknown and the next work is to figure out the reason
and explain how it works.
Finally, we just give the pre-simulation results in this thesis, and the future work
will focus on layout, post-simulation and test.
57
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60
Series of Master’s theses
Department of Electrical and Information Technology
LU/LTH-EIT 2016-544
http://www.eit.lth.se
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