AdvancedTCA® High Performance Intel
AdvancedTCA®
High Performance Intel® Server Blade
SB-ATCA7300
Installation and Use Guide
June 2012
Rev 1.1A
© Copyright 2011-12 SANBlaze Technology, Inc.
All rights reserved.
Printed in the United States of America.
Portions of this documents are reprinted with permission of Emerson Network Power - Embedded
Computing, Inc.
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trademarks or registered trademarks of PCI Industrial Computer Manufacturers Group.
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the following notice shall apply unless otherwise agreed to in writing by SANBlaze Technology,
Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in
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and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS
252.227-7014 (Jun. 1995).
SANBlaze Technology, Inc.
One Monarch Drive
Suite 204
Littleton, MA 01460
www.SANBlaze.com
Table of Contents
Safety Notices .......................................................................................................................... Safety-1
Flammability.....................................................................................................................Safety-2
EMC ...................................................................................................................................Safety-2
Safety Statement ...............................................................................................................Safety-2
CE Notice (European Community) ...............................................................................Safety-2
Installation.........................................................................................................................Safety-3
Operation ..........................................................................................................................Safety-3
Switch Settings .................................................................................................................Safety-3
Battery................................................................................................................................Safety-3
Environment .....................................................................................................................Safety-4
Notice ................................................................................................................................Safety-4
About This Manual ..................................................................................................................About-1
How This Manual Is Organized .................................................................................. About-1
· Abbreviations ................................................................................................................ About-2
· Conventions Used in This Manual ............................................................................. About-5
1 Introduction..................................................................................................................................1-1
1.1 SB-ATCA7300 Overview....................................................................................................1-1
1.2 SB-ATCA7300 Features ......................................................................................................1-1
1.3 Standards Compliance .......................................................................................................1-2
1.3.1 Compliance Notes......................................................................................................1-3
1.4 Mechanical Data..................................................................................................................1-4
1.5 Product Identification Labels ............................................................................................1-4
1.5.1 Blade Serial Number..................................................................................................1-5
1.6 Ordering Information.........................................................................................................1-5
2 Functional Description ................................................................................................................2-1
2.1 Block Diagram .....................................................................................................................2-1
2.2 Processor ..............................................................................................................................2-2
2.2.1 Processor Speeds ........................................................................................................2-2
2.2.2 Intel L5638 Processor Features .................................................................................2-3
2.3 Intel QuickPath Interconnect.............................................................................................2-3
SB-ATCA7300 Installation and Use Guide
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Table of Contents
2.4 Integrated Memory Controller..........................................................................................2-4
2.4.1 SATA-Cube/SFMMOD module..............................................................................2-4
2.5 Intel Xeon 5520 I/O Hub ...................................................................................................2-4
2.6 Intel ICH10R I/O Controller .............................................................................................2-4
2.7 Ethernet Ports ......................................................................................................................2-5
2.8 Embedded USB Disk Module ...........................................................................................2-6
2.9 BIOS ......................................................................................................................................2-6
2.9.1 BIOS Flash Memory...................................................................................................2-6
2.10 IPMC ...................................................................................................................................2-6
2.10.1 IPMC Firmware........................................................................................................2-7
2.10.2 IPMC Watchdog Timers..........................................................................................2-7
2.10.3 IPMC Status Information ........................................................................................2-7
2.11 Serial Port Redirection......................................................................................................2-7
2.12 Serial Over LAN................................................................................................................2-8
2.13 Blade Front Panel ..............................................................................................................2-8
2.14 USB 2.0 Interfaces..............................................................................................................2-8
2.15 Real Time Clock Battery...................................................................................................2-9
3 Hardware Preparation and Installation ....................................................................................3-1
3.1 Unpacking and Inspecting the Blade ...............................................................................3-1
3.2 Environmental and Power Requirements .......................................................................3-1
3.2.1 Environmental Requirements ..................................................................................3-1
3.2.2 Power Requirements .................................................................................................3-3
3.2.2.1 Power Inputs......................................................................................................3-4
3.3 Blade Layout ........................................................................................................................3-5
3.4 Board Control Switch Settings ..........................................................................................3-5
3.4.1 Control Switch Settings.............................................................................................3-7
3.5 Installing and Removing the Blade ..................................................................................3-8
3.5.1 Installing the Blade Into a Chassis...........................................................................3-8
3.5.2 Removing the Blade from a Chassis......................................................................3-10
3.6 Installing the SB-ATCA7300 Accessories ......................................................................3-11
3.6.1 Memory DIMMs.......................................................................................................3-11
3.6.1.1 DIMM Models .................................................................................................3-11
3.6.1.2 DIMM Installation Order...............................................................................3-12
3.6.1.3 Installing DIMMs ............................................................................................3-13
3.6.1.4 Removing DIMMs...........................................................................................3-13
3.6.2 SSD and SFMMOD Module Installation ..............................................................3-13
3.6.2.1 Installing the SATA or SFMMOD Module..................................................3-14
3.6.2.2 Removing the SATA or SFMMOD Module ................................................3-15
3.6.3 eUSB 2.0 Flash Module............................................................................................3-15
3.6.3.1 Installing the eUSB Flash Module ................................................................3-16
3.6.3.2 Removing the eUSB Flash Module...............................................................3-16
3.6.4 VGA Module.............................................................................................................3-16
3.6.4.1 Installing the VGA Module ...........................................................................3-17
3.6.4.2 Removing the VGA Module..........................................................................3-17
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Table of Contents
4 Controls, Indicators, and Connectors ........................................................................................4-1
4.1 Front Panel ...........................................................................................................................4-1
Table 4-1 Front Panel LEDs ...............................................................................................4-2
4.1.1 Reset Button ................................................................................................................4-3
4.1.2 Blade Connectors .......................................................................................................4-3
4.1.2.1 Ethernet Connector ...........................................................................................4-3
4.1.2.2 Serial Port Connector........................................................................................4-4
4.1.2.3 USB Connectors.................................................................................................4-4
4.1.2.4 VGA Connector .................................................................................................4-4
4.2 On-board Connectors .........................................................................................................4-5
4.2.1 SFMMOD/SSD Module Connector ........................................................................4-5
4.2.2 eUSB Flash Module Connector ................................................................................4-7
4.3 AdvancedTCA Backplane Connectors ............................................................................4-7
4.3.1 Zone 1 (P10) ................................................................................................................4-8
4.3.2 Zone 2 (P20 and P23) .................................................................................................4-8
4.3.3 Zone 3 (J30, J32 and J33) ............................................................................................4-9
5 BIOS Configuration.....................................................................................................................5-1
5.1 Overview ..............................................................................................................................5-1
5.2 Hardware Architecture ......................................................................................................5-1
5.2.1 Processor .....................................................................................................................5-2
5.2.2 Processor Support Chip Set ......................................................................................5-2
5.2.3 Memory .......................................................................................................................5-2
5.3 BIOS Considerations...........................................................................................................5-2
5.3.1 BIOS Update and Recovery ......................................................................................5-2
5.3.2 DRAM Support ..........................................................................................................5-2
5.3.2.1 Autosizing ..........................................................................................................5-3
5.3.2.2 Memory Test ......................................................................................................5-3
5.3.2.3 ECC Support ......................................................................................................5-3
5.3.3 Interrupt Routing .......................................................................................................5-3
5.3.4 PCI Initialization ........................................................................................................5-3
5.3.5 I/O Device Configuration ........................................................................................5-4
5.3.5.1 Serial Ports .........................................................................................................5-4
5.3.5.2 Integrated SATA Controller ............................................................................5-4
5.3.6 Boot Options ...............................................................................................................5-4
5.3.6.1 Boot Support for the SAS Controller on the ARTM.....................................5-5
5.3.6.2 Boot Support for Fibre Channel on the ARTM.............................................5-5
5.3.6.3 Network Boot Support .....................................................................................5-5
5.3.7 Redirection of Serial I/O to COM Ports (Console Redirection)..........................5-5
5.3.7.1 SOL (Serial Over LAN) ....................................................................................5-6
5.3.8 IPMI Support ..............................................................................................................5-6
5.3.8.1 Watchdog Timers..............................................................................................5-6
5.3.9 SMBIOS Support ........................................................................................................5-7
5.3.10 Configuring Boot Parameters Using IPMC..........................................................5-7
5.3.11 LED Behavior During POST...................................................................................5-7
5.3.12 ARTM SAS Controller .............................................................................................5-7
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5.3.13 CPU and Chipset Firmware ...................................................................................5-8
5.3.14 Legacy Free Support................................................................................................5-8
5.3.15 BIOS Setup Layout...................................................................................................5-8
5.3.15.1 Board Information Display............................................................................5-8
5.3.16 USB Ports...................................................................................................................5-8
5.3.17 Supported Operating Systems ...............................................................................5-9
5.3.18 SRAM Flash Memory Module (SFMMOD)..........................................................5-9
5.3.19 CPU Specific Initialization......................................................................................5-9
5.3.20 Intel 5520-Specific Initializations ...........................................................................5-9
5.3.20.1 Intel 5520 QPI Link Speed Configuration....................................................5-9
5.3.20.2 PCI Express Port Configuration..................................................................5-10
5.3.20.3 SPI Boot Flash ................................................................................................5-10
5.3.21 Virtualization Support ..........................................................................................5-10
5.3.22 BIOS CLI tool - ipmibpar ...................................................................................5-10
5.3.23 Dual BIOS Flash Devices.......................................................................................5-10
5.4 BIOS Initialization.............................................................................................................5-11
5.4.1 Power On Self-Test (POST).....................................................................................5-11
5.4.2 BIOS Boot Process ....................................................................................................5-12
5.4.3 Initiating Setup .........................................................................................................5-13
5.5 BIOS Setup ........................................................................................................................5-13
5.5.1 BIOS Main Menu......................................................................................................5-15
5.5.2 BIOS Advanced Menu.............................................................................................5-16
5.5.2.1 CPU Configuration .........................................................................................5-17
5.5.2.2 Memory Configuration ..................................................................................5-18
5.5.2.3 Chipset - North Bridge ...................................................................................5-19
5.5.2.4 Chipset - South Bridge ...................................................................................5-20
5.5.2.5 SATA Configuration.......................................................................................5-20
5.5.2.6 USB Configuration..........................................................................................5-21
5.5.2.7 Super IO Configuration..................................................................................5-21
5.5.2.8 Serial Port Console Redirection ....................................................................5-22
5.5.2.9 Runtime Error Logging ..................................................................................5-24
5.5.2.10 SMBIOS Event Log .......................................................................................5-24
5.5.2.11 Local IPMI System Event Log .....................................................................5-24
5.5.3 BIOS IPMI Menu .....................................................................................................5-25
5.5.3.1 IPMI Watchdog Configuration .....................................................................5-26
5.5.3.2 System Event Log............................................................................................5-26
5.5.3.3 View FRU information ...................................................................................5-26
5.5.4 BIOS Boot Menu .......................................................................................................5-27
5.5.4.1 Boot Option ROM Execution.........................................................................5-28
5.5.5 BIOS Security Menu.................................................................................................5-29
5.5.6 Save and Exit Menu .................................................................................................5-30
6 Maps and Registers......................................................................................................................6-1
6.1 Interrupt Structure ..............................................................................................................6-1
6.1.1 APIC Mode Interrupts...............................................................................................6-2
6.1.2 Non-APIC Mode Interrupts .....................................................................................6-3
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6.2 PCI Express Lane Mapping ...............................................................................................6-4
6.3 Configuration Registers .....................................................................................................6-4
6.3.1 FPGA Register Access and Addresses ....................................................................6-5
6.3.1.1 LPC Addresses ..................................................................................................6-5
6.3.1.2 SPI Register Access and Addresses ................................................................6-6
6.3.2 POST Code Register...................................................................................................6-6
6.3.3 Super IO Functionality Configuration Register.....................................................6-7
6.3.3.1 Entering Configuration State...........................................................................6-7
6.3.3.2 Configuration State...........................................................................................6-7
6.3.3.3 Super IO Functionality Configuration Registers..........................................6-8
6.3.4 UART1 and UART2 Register Map ........................................................................6-13
6.3.4.1 UART Register Overview ..............................................................................6-13
6.3.4.2 UART Registers DLAB=0 ..............................................................................6-14
6.3.4.3 Programmable Baud Rate Generator ...........................................................6-24
6.4 FPGA Register Mapping ..................................................................................................6-25
6.4.1 LPC I/O Register Map ............................................................................................6-25
6.4.2 IPMC SPI Register Map...........................................................................................6-25
6.4.3 Module Identification Register ..............................................................................6-26
6.4.4 Version Register .......................................................................................................6-27
6.4.5 Serial Redirection Control Register .......................................................................6-27
6.4.6 Serial Over LAN (SOL) Control Register .............................................................6-27
6.4.7 Serial Line Routing Register ...................................................................................6-28
6.4.8 IPMC Power Level Register....................................................................................6-29
6.4.9 SPD PROM MUX Control Register .......................................................................6-29
6.4.10 Reset Registers........................................................................................................6-30
6.4.10.1 BIOS Reset Source Register..........................................................................6-30
6.4.10.2 Reset Mask Register......................................................................................6-31
6.4.10.3 BIOS IPMC Watchdog Timeout Register ..................................................6-31
6.4.10.4 BIOS Push Button Enable Register .............................................................6-32
6.4.10.5 OS Reset Source Register .............................................................................6-32
6.4.10.6 OS IPMC Watchdog Timeout Register ......................................................6-33
6.4.10.7 IPMC Watchdog Timeout Register ............................................................6-33
6.4.10.8 IPMC Reset Source Register ........................................................................6-34
6.4.11 RTM SPI Interface Registers .................................................................................6-35
6.4.12 Interrupt Control and Status Registers ...............................................................6-36
6.4.12.1 RTM Interrupt Status Register ....................................................................6-36
6.4.12.2 External Interrupt Status Register ..............................................................6-36
6.4.12.3 Processor Hot Status/Control Register .....................................................6-37
6.4.12.4 Telecom Status/Control Register ...............................................................6-37
6.4.12.5 Interrupt Mask and Map Registers ............................................................6-38
6.4.13 Flash Status and Write Protection Registers ......................................................6-40
6.4.13.1 Flash Write Protection Registers.................................................................6-40
6.4.14 BIOS Boot Mode Register......................................................................................6-41
6.4.15 SFMMOD Module Configuration Register ........................................................6-42
6.4.16 IPMC E-Keying Status Register ...........................................................................6-42
6.4.17 IPMC E-Keying Control Register.........................................................................6-42
SB-ATCA7300 Installation and Use Guide
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6.4.18 IPMC GPIO Register..............................................................................................6-43
6.4.19 LED Status and Control Register.........................................................................6-43
6.4.20 NMI Status and Control Register ........................................................................6-44
6.4.21 Telecom Clock Supervision Registers .................................................................6-45
6.4.21.1 Telecom Clocking Status Registers.............................................................6-45
6.4.21.2 Telecom Timer Registers..............................................................................6-46
6.4.22 Miscellaneous Status/Control Registers ............................................................6-47
6.4.23 Scratch Registers ....................................................................................................6-47
7 Serial Over LAN ..........................................................................................................................7-1
7.1 Overview ..............................................................................................................................7-1
7.1.1 SOL Configuration Steps ..........................................................................................7-1
7.2 Installing ipmitool...........................................................................................................7-2
7.3 Configuring the IPMC SOL Parameters ..........................................................................7-2
7.3.1 Configuring the SOL Facility ...................................................................................7-2
7.3.2 Configuring the IPMI SOL User ..............................................................................7-4
7.3.3 Configuring the IPMC Network Environment......................................................7-4
7.3.3.1 Using the Shelf Manager Configuration File ................................................7-4
7.3.3.2 Using DHCP ......................................................................................................7-5
7.3.3.3 Using ipmitool From the Blade OS ............................................................7-6
7.3.3.4 Using ipmitool Through the Shelf Manager .............................................7-7
7.4 Establishing a SOL Session ................................................................................................7-8
8 FRU Information and Sensor Data Records .............................................................................8-1
8.1 FRU ID Information............................................................................................................8-1
8.2 E-Keying ...............................................................................................................................8-4
8.3 Power Configuration ..........................................................................................................8-5
8.4 Sensor Data Record Types .................................................................................................8-5
8.5 Detailed Sensor Data Records ...........................................................................................8-8
9 SB-ATCA7300 Firmware Updates.............................................................................................9-1
9.1 Firmware Update Mechanisms.........................................................................................9-1
9.1.1 Obtaining Updates.....................................................................................................9-1
9.2 Updating the BIOS and FPGA Firmware ........................................................................9-1
9.2.1 The Update Package ..................................................................................................9-2
9.2.2 Determining the Current BIOS and FPGA Firmware Versions ..........................9-2
9.2.3 Performing the Update..............................................................................................9-2
9.2.3.1 BIOS Update Example......................................................................................9-3
9.3 Updating the IPMC Firmware ..........................................................................................9-4
9.3.1 Installing ipmitool..................................................................................................9-5
9.3.2 Determining the Current IPMC Firmware Version ..............................................9-5
9.3.2.1 From the Shelf Manager...................................................................................9-5
9.3.2.2 Using ipmitool ..................................................................................................9-5
9.3.3 HPM.1 Firmware Update of the IPMC ...................................................................9-6
9.3.4 Update Package..........................................................................................................9-6
9.3.5 Basic Update Commands..........................................................................................9-6
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Table of Contents
9.3.5.1 IPMC Update Example ....................................................................................9-7
9.3.6 ipmitool Update Interfaces ...................................................................................9-7
9.3.6.1 Using the Local KCS Interface.........................................................................9-7
9.3.6.2 Using the Shelf Manager..................................................................................9-8
9.3.6.3 Using IPMI over Ethernet (Base Network) ...................................................9-8
Appendix A Replacing the Blade Battery....................................................................................A-1
A.1 Replacing the Battery .......................................................................................................A-1
A.2 Replacement Procedure ...................................................................................................A-2
Appendix B BIOS Status Codes ................................................................................................... B-1
B.1 BIOS Status Codes ............................................................................................................. B-1
B.1.1 Status Code Ranges .................................................................................................. B-1
B.1.2 Standard Status Codes ............................................................................................. B-2
B.1.2.1 Security (SEC) Status Codes........................................................................... B-2
B.1.2.2 Security (SEC) Beep Codes............................................................................. B-2
B.1.2.3 PEI Status Codes .............................................................................................. B-2
B.1.2.4 PEI Beep Codes ................................................................................................ B-5
B.1.2.5 DXE Status Codes ............................................................................................ B-5
B.1.2.6 DXE Beep Codes .............................................................................................. B-8
B.1.2.7 CPU Exception Status Codes ......................................................................... B-9
B.1.2.8 CPU Exception Beep Codes ........................................................................... B-9
B.1.2.9 ASL Status Codes............................................................................................. B-9
B.1.2.10 OEM-Reserved Status Code Ranges ......................................................... B-10
B.1.3 Network Device PCIe Addresses ......................................................................... B-10
Appendix C Supported IPMI Commands ................................................................................... C-1
C.1 Standard IPMI Commands ..............................................................................................C-1
C.1.1 Global IPMI Commands .........................................................................................C-1
C.1.2 System Interface .......................................................................................................C-1
C.1.3 Watchdog Commands.............................................................................................C-2
C.1.4 SEL Device Commands ...........................................................................................C-2
C.1.5 FRU Data Commands..............................................................................................C-3
C.1.6 Sensor Device Commands ......................................................................................C-3
C.1.7 Chassis Device Commands.....................................................................................C-4
C.1.7.1 System Boot Options Commands .................................................................C-4
C.1.8 LAN Device Commands .......................................................................................C-13
C.2 PICMG 3.0 Commands...................................................................................................C-13
C.2.1 Set/Get Power Level..............................................................................................C-14
C.3 SANBlaze Specific Commands .....................................................................................C-15
C.3.1 Serial Output Commands .....................................................................................C-15
C.3.1.1 Set Serial Output Command........................................................................C-15
C.3.1.2 Get Serial Output Command.......................................................................C-16
C.4 Pigeon Point Specific Commands.................................................................................C-18
C.4.1 Get Status Command.............................................................................................C-19
C.4.2 Get Serial Interface Properties Command ..........................................................C-21
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C.4.3 Set Serial Interface Properties Command ...........................................................C-22
C.4.4 Get Debug Level Command .................................................................................C-23
C.4.5 Set Debug Level Command ..................................................................................C-24
C.4.6 Get Hardware Address Command .....................................................................C-25
C.4.7 Set Hardware Address Command ......................................................................C-25
C.4.8 Get Handle Switch Command .............................................................................C-25
C.4.9 Set Handle Switch Command ..............................................................................C-26
C.4.10 Get Payload Communication Time-Out Command .......................................C-27
C.4.11 Set Payload Communication Time-Out Command ........................................C-27
C.4.12 Enable Payload Control Command...................................................................C-28
C.4.13 Disable Payload Control Command..................................................................C-28
C.4.14 Reset IPMC Command ........................................................................................C-28
C.4.15 Hang IPMC Command........................................................................................C-29
C.4.16 Graceful Reset Command ...................................................................................C-29
C.4.17 Get Payload Shutdown Time-Out Command .................................................C-30
C.4.18 Set Payload Shutdown Time-Out Command ..................................................C-31
C.4.19 Get Module State Command ..............................................................................C-31
C.4.20 Enable Module Site Command ..........................................................................C-32
C.4.21 Disable Module Site Command .........................................................................C-33
C.4.22 Reset Carrier SDR Repository Command ........................................................C-33
Index...........................................................................................................................................Index-1
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SB-ATCA7300 Installation and Use Guide
Table of Tables
1 Introduction
1-1 Standards Compliance ......................................................................................................... 1-2
1-2 Mechanical Data .................................................................................................................. 1-4
1-3 SB-ATCA7300 Serial Number Breakdown ........................................................................ 1-5
1-4 Blade Model ........................................................................................................................ 1-5
1-5 Blade Accessories................................................................................................................ 1-5
2 Functional Description
2-2 Intel L5638 Processor Characteristics ................................................................................. 2-2
2-3 Intel L5638 Processor Features ........................................................................................... 2-3
2-4 Ethernet Controller Types ................................................................................................... 2-5
3 Hardware Preparation and Installation
3-1 Environmental Conditions................................................................................................... 3-2
3-2 Critical Temperature Limits ................................................................................................ 3-2
3-3 Power Requirements............................................................................................................ 3-3
3-4 Board Control Switch Settings ............................................................................................ 3-7
4 Controls, Indicators, and Connectors
4-1 SB-ATCA7300 Front Panel Components ........................................................................... 4-1
4-2 SB-ATCA7300 Status LEDs ............................................................................................... 4-2
4-3 DB15 Video Connector Pinout............................................................................................ 4-5
5 BIOS Configuration
5-1 Ethernet Interfaces Supported for Network Boot ................................................................ 5-5
5-2 SB-ATCA7300 USB Ports .................................................................................................. 5-8
5-3 IPMI Boot Parameter List.................................................................................................. 5-10
5-4 BIOS Execution Phases ..................................................................................................... 5-11
5-5 Primary Menus .................................................................................................................. 5-14
5-6 Aptio BIOS Navigation Keys ............................................................................................ 5-14
5-7 BIOS Main Menu .............................................................................................................. 5-15
5-8 Advanced Menu................................................................................................................. 5-16
5-9 CPU Configuration ............................................................................................................ 5-17
SB-ATCA7300 Installation and Use Guide
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Table of Tables
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
CPU Socket 0/1 CPU Information................................................................................... 5-18
Memory Configuration .................................................................................................... 5-18
Per Processor DIMM Information................................................................................... 5-19
Chipset - North Bridge .................................................................................................... 5-19
Intel® VT for Directed I/O Configuration ...................................................................... 5-20
Chipset - South Bridge .................................................................................................... 5-20
USB Configuration .......................................................................................................... 5-20
SATA Configuration ....................................................................................................... 5-20
USB Configuration .......................................................................................................... 5-21
Super IO Configuration ................................................................................................... 5-21
Serial Port 0 Configuration.............................................................................................. 5-22
Serial Port 1 Configuration.............................................................................................. 5-22
Serial Port Console Redirection ...................................................................................... 5-22
COM0/1 Console Redirection Settings ........................................................................... 5-23
Runtime Error Logging ................................................................................................... 5-24
SMBIOS Event Log......................................................................................................... 5-24
Local IPMI System Event Log ........................................................................................ 5-24
BIOS IPMI Menu ............................................................................................................ 5-25
IPMI Watchdog Configuration........................................................................................ 5-26
System Event Log............................................................................................................ 5-26
View FRU information.................................................................................................... 5-26
BIOS Boot Menu ............................................................................................................. 5-27
BIOS Boot Option ROM Execution................................................................................ 5-28
BIOS Security Menu ....................................................................................................... 5-29
Save and Exit Menu......................................................................................................... 5-30
6 Maps and Registers
6-1 APIC Mode Interrupt Mapping ........................................................................................... 6-2
6-2 Non-APIC (PIC mode / 8259 Mode) Interrupt Mapping .................................................... 6-3
6-3 PCI Express Lane Naming .................................................................................................. 6-4
6-4 Register Default Value Conventions ................................................................................... 6-4
6-6 LPC I/O Register Map Overview ........................................................................................ 6-5
6-5 Register Access Type Conventions ..................................................................................... 6-5
6-7 IPMC SPI Register .............................................................................................................. 6-6
6-8 POST Code Register............................................................................................................ 6-6
6-9 Super IO Configuration Index Register............................................................................... 6-7
6-10 Super IO Configuration Data Register .............................................................................. 6-7
6-11 Global Configuration Register Summary .......................................................................... 6-8
6-12 Super IO Logical Device Number Register....................................................................... 6-9
6-13 Super IO Device Identification Register ........................................................................... 6-9
6-14 Super IO Device Revision Register................................................................................... 6-9
6-15 Super IO LPC Control Register......................................................................................... 6-9
6-16 Global Super IO SERIRQ and Pre-divide Control Register.............................................. 6-9
6-17 Logical Device Configuration Register Summary .......................................................... 6-10
6-18 Logical Device Enable Register ...................................................................................... 6-11
6-19 Logical Device Base IO Address MSB Register............................................................. 6-11
Tables-2
SB-ATCA7300 Installation and Use Guide
Table of Tables
6-20
6-21
6-23
6-24
6-22
6-26
6-25
6-27
6-28
6-29
6-30
6-32
6-31
6-33
6-34
6-35
6-36
6-37
6-38
6-40
6-39
6-41
6-42
6-43
6-44
6-45
6-46
6-47
6-48
6-49
6-50
6-51
6-52
6-53
6-54
6-55
6-56
6-57
6-58
6-59
6-60
6-61
6-62
6-63
6-64
6-65
Logical Device Base IO Address LSB Register.............................................................. 6-11
Logical Device Common Decode Ranges....................................................................... 6-11
Logical Device 0x74 Reserved Register ......................................................................... 6-12
Logical Device 0x75 Reserved Register ......................................................................... 6-12
Logical Device Primary Interrupt Register ..................................................................... 6-12
UART Register Overview ............................................................................................... 6-13
Logical Device 0xF0 Reserved Register ......................................................................... 6-13
Receiver Buffer Register (RBR) if DLAB=0 .................................................................. 6-14
Transmitter Holding Register (THR) if DLAB=0........................................................... 6-14
Interrupt Enable Register (IER), if DLAB=0 .................................................................. 6-15
UART Interrupt Priorities................................................................................................ 6-15
FIFO Control Register (FCR).......................................................................................... 6-16
Interrupt Identification Register (IIR) ............................................................................. 6-16
Line Control Register (LCR)........................................................................................... 6-17
Modem Control Register (MCR)..................................................................................... 6-18
Line Control Register (LCR)........................................................................................... 6-20
Modem Status Register (MSR)........................................................................................ 6-22
Scratch Register (SCR)) .................................................................................................. 6-24
Divisor Latch LSB Register (DLL), if DLAB=1 ............................................................ 6-24
FPGA Register Map Overview........................................................................................ 6-25
Divisor Latch MSB Register (DLM), if DLAB=1 .......................................................... 6-25
Module Identification Register........................................................................................ 6-26
Version Register .............................................................................................................. 6-27
Serial Redirection Control Register................................................................................. 6-27
Serial over LAN Control Register ................................................................................... 6-28
Serial Line Routing Register ........................................................................................... 6-28
IPMC Power Level Register............................................................................................ 6-29
SPD PROM MUX Control Registerr .............................................................................. 6-29
BIOS Reset Source Register............................................................................................ 6-30
Reset Mask Register ........................................................................................................ 6-31
BIOS IPMC Watchdog Timeout Register ....................................................................... 6-31
BIOS Push Button Enable Register ................................................................................. 6-32
Reset Source Register...................................................................................................... 6-32
OS IPMC Watchdog Timeout Register ........................................................................... 6-33
IPMC Watchdog Timeout Register ................................................................................. 6-34
IPMC Reset Source Register ........................................................................................... 6-34
RTM SPI Address/Command Register............................................................................ 6-35
RTM SPI Write Register ................................................................................................. 6-35
RTM SPI Read Register .................................................................................................. 6-36
External Interrupt Status Register.................................................................................... 6-36
Processor Hot Status/Control Register ............................................................................ 6-37
Telecom Status/Control Register..................................................................................... 6-37
Address Map of Interrupt Mask and Map Registers........................................................ 6-38
Interrupt Mask and Map Registers .................................................................................. 6-39
Flash Status Register ....................................................................................................... 6-40
Default Boot SPI Flash Write Enable.............................................................................. 6-41
SB-ATCA7300 Installation and Use Guide
Tables-3
Table of Tables
6-66
6-67
6-68
6-69
6-70
6-71
6-72
6-73
6-74
6-75
6-76
6-77
6-78
6-79
6-80
6-82
6-83
6-84
6-81
Recovery Boot SPI Flash Write Enable .......................................................................... 6-41
BIOS Boot Mode Register............................................................................................... 6-41
SFMMOD Module Configuration Register..................................................................... 6-42
IPMC E-Keying Status Register...................................................................................... 6-42
IPMC E-Keying Control Register ................................................................................... 6-42
IPMC GPIO Register....................................................................................................... 6-43
LED Status and Control Register .................................................................................... 6-43
NMI Status and Control Register .................................................................................... 6-44
Telecom Backplane Clocking Status Register................................................................. 6-45
Telecom Backplane Clocking Latch Register ................................................................. 6-45
Telecom CH1_CLK1A Clock Period MSB Register ...................................................... 6-45
Telecom CH1_CLK1A clock period LSB Register ........................................................ 6-45
Telecom CH1_CLK1B Clock Period MSB Register ...................................................... 6-46
Telecom CH1_CLK1B Clock Period LSB Register ....................................................... 6-46
Telecom Timer MSB Register......................................................................................... 6-46
CPLD Version and Spare Signal Status Register ............................................................ 6-47
LPC Scratch Register....................................................................................................... 6-47
IPMC Scratch Register .................................................................................................... 6-47
Telecom Timer LSB Register.......................................................................................... 6-47
7 Serial Over LAN
7-2 SOL Facility Properties ....................................................................................................... 7-2
8 FRU Information and Sensor Data Records
8-1 FRU ID Definition............................................................................................................... 8-1
8-2 Contents of the Blade Point-to-Point Connectivity Record Area........................................ 8-4
8-3 Power Configuration............................................................................................................ 8-5
8-4 SDR Record Types .............................................................................................................. 8-5
8-5 Sensor Data Records............................................................................................................ 8-8
9 SB-ATCA7300 Firmware Updates
9-1 SB-ATCA7300 Firmware Update Methods ........................................................................ 9-1
9-2 BIOS Update Package ......................................................................................................... 9-2
9-3 IPMC HPM.1 Update Package............................................................................................ 9-6
Appendix A Replacing the Blade Battery
Appendix B BIOS Status Codes
B-1 Status Code Ranges............................................................................................................
B-2 SEC Status Codes ..............................................................................................................
B-3 PEI Status Codes................................................................................................................
B-4 PEI Beep Codes .................................................................................................................
B-5 DXE Status Codes..............................................................................................................
B-6 DXE Beep Codes ...............................................................................................................
B-7 CPU Exception Status Codes.............................................................................................
B-8 ASL Status Codes ..............................................................................................................
Tables-4
B-1
B-2
B-2
B-5
B-5
B-8
B-9
B-9
SB-ATCA7300 Installation and Use Guide
Table of Tables
B-9 OEM-Reserved Status Code Ranges ............................................................................... B-10
B-10 Network Device PCIe Addresses................................................................................... B-10
Appendix C Supported IPMI Commands
C-1 Supported Global IPMI Commands................................................................................... C-1
C-2 Supported System Interface Commands............................................................................ C-1
C-3 Supported Watchdog Commands ...................................................................................... C-2
C-4 Supported SEL Device Commands ................................................................................... C-2
C-5 Supported FRU Data Commands....................................................................................... C-3
C-6 Supported Sensor Device Commands................................................................................ C-3
C-7 Supported Chassis Device Commands .............................................................................. C-4
C-8 Configurable System Boot Option Parameters .................................................................. C-5
C-9 System Boot Options Parameter #96 ................................................................................. C-5
C-10 System Boot Options Parameter #97 ............................................................................... C-6
C-11 System Boot Options Parameter #98 ............................................................................... C-6
C-12 System Boot Options - Parameter #100 - Data Format ................................................... C-8
C-13 System Boot Options Parameter #100 - SET Command Usage ...................................... C-8
C-14 System Boot Options Parameter #100 - GET Command Usage ..................................... C-9
C-15 System Boot Options Parameter #100 - Supported Parameters..................................... C-10
C-16 boot_order Devices.................................................................................................. C-11
C-17 Supported LAN Device Commands .............................................................................. C-13
C-18 Supported PICMG 3.0 Commands ................................................................................ C-13
C-19 Serial Output Commands............................................................................................... C-15
C-20 Request Data of Set Serial Output Command................................................................ C-15
C-21 Response Data of Set Serial Output Command ............................................................. C-16
C-22 Request Data of Get Serial Output Command............................................................... C-17
C-23 Response Data of Get Serial Output Command ............................................................ C-17
C-24 Pigeon Point Extension Commands............................................................................... C-18
C-25 IPMC Modes.................................................................................................................. C-19
C-26 Get Status Command Description.................................................................................. C-19
C-27 Get Serial Interface Properties Command Description.................................................. C-21
C-28 Set Serial Interface Properties Command Description .................................................. C-22
C-29 Get Debug Level Command Description....................................................................... C-23
C-30 Set Debug Level Command Description ....................................................................... C-24
C-31 Get Hardware Address Command Description.............................................................. C-25
C-32 Set Hardware Address Command Description .............................................................. C-25
C-33 Get Handle Switch Command Description.................................................................... C-26
C-34 Set Handle Switch Command Description .................................................................... C-26
C-35 Get Payload Communication Time-Out Command Description ................................... C-27
C-36 Set Payload Communication Time-Out Command Description.................................... C-27
C-37 Enable Payload Control Command Description ............................................................ C-28
C-38 Disable Payload Control Command Description........................................................... C-28
C-39 Reset IPMC Command Description............................................................................... C-28
C-40 Hang IPMC Command Description............................................................................... C-29
C-41 Graceful Reset Command Description .......................................................................... C-30
C-42 Get Payload Shutdown Time-Out Command Description............................................. C-30
SB-ATCA7300 Installation and Use Guide
Tables-5
Table of Tables
C-43
C-44
C-45
C-46
C-47
Tables-6
Set Payload Shutdown Time-Out Command Description .............................................
Get Module State Command Description ......................................................................
Enable Module Site Command Description ..................................................................
Disable Module Site Command Description .................................................................
Reset Carrier SDR Repository Command Description..................................................
C-31
C-31
C-32
C-33
C-33
SB-ATCA7300 Installation and Use Guide
Table of Figures
1 Introduction
1-1 Product Identification Labels and Locations ....................................................................... 1-4
2 Functional Description
2-1 SB-ATCA7300 Block Diagram........................................................................................... 2-1
3 Hardware Preparation and Installation
3-1 SB-ATCA7300 Blade Layout ............................................................................................. 3-5
3-2 Loosening the Blade Ejector Handle ................................................................................... 3-9
3-3 Ejector Handle When Inserting a Board.............................................................................. 3-9
3-4 SB-ATCA7300 DIMM Population Order ......................................................................... 3-12
3-5 SB-ATCA7300 SSD Module ............................................................................................ 3-13
3-6 SB-ATCA7300 SFMMOD Module (Installed in a Different Blade Model)..................... 3-14
3-7 SB-ATCA7300 eUSB Flash Module ................................................................................ 3-15
3-8 SB-ATCA7300 VGA Module ........................................................................................... 3-16
4 Controls, Indicators, and Connectors
4-1 SB-ATCA7300 Front Panel................................................................................................. 4-1
4-2 Location of Front Panel Reset Button ................................................................................. 4-3
4-3 Ethernet Interface Connectors Pinout.................................................................................. 4-3
4-4 Serial Port Connector Pinout ............................................................................................... 4-4
4-5 USB Connector Pinout ........................................................................................................ 4-4
4-6 DB15 Video Connector ....................................................................................................... 4-5
4-7 SFMMOD/SSD Module Connector Pinout......................................................................... 4-6
4-8 eUSB Flash Module Connector Pin Assignment ................................................................ 4-7
4-9 Location of AdvancedTCA Backplane Connectors ............................................................ 4-7
4-10 SB-ATCA7300 Zone 1 Backplane Connector Pinout....................................................... 4-8
4-11 Zone 2 P20 Backplane Connector Pinout.......................................................................... 4-9
4-12 Zone 2 P23 Backplane Connector Pinout.......................................................................... 4-9
4-13 Zone 3 J30 Backplane Connector Pinout ........................................................................ 4-10
4-14 Zone 3 J32 Backplane Connector Pinout ........................................................................ 4-10
4-15 Zone 3 J33 Backplane Connector Pinout ........................................................................ 4-11
SB-ATCA7300 Installation and Use Guide
Figures-1
Table of Figures
5 BIOS Configuration
5-1 SB-ATCA7300 Black Diagram........................................................................................... 5-1
5-2 BIOS Main Menu .............................................................................................................. 5-15
5-3 BIOS Advanced Menu....................................................................................................... 5-16
5-4 BIOS IPMI Menu .............................................................................................................. 5-25
5-5 BIOS Boot Menu ............................................................................................................... 5-27
5-6 BIOS Boot Option ROM Execution.................................................................................. 5-28
5-7 BIOS Security Menu ......................................................................................................... 5-29
5-8 Save and Exit Menu........................................................................................................... 5-30
6 Maps and Registers
6-1 Interrupt Structure of the SB-ATCA7300 ........................................................................... 6-1
6-2 IOH36D PCIe Lane Mapping on SB-ATCA7300............................................................... 6-4
7 Serial Over LAN
7-1 SOL On-Blade Data Path .................................................................................................... 7-1
8 FRU Information and Sensor Data Records
9 SB-ATCA7300 Firmware Updates
9-1 IPMC Component Elements................................................................................................ 9-4
Appendix A Replacing the Blade Battery
A-1 Location of On-board Battery............................................................................................ A-1
A-2 Battery Location Detail...................................................................................................... A-2
Appendix B BIOS Status Codes
Appendix C Supported IPMI Commands
C-3 System Boot Options Parameter #100 - Information Flow Overview............................... C-7
Figures-2
SB-ATCA7300 Installation and Use Guide
Safety Notices
This section provides warnings that precede potentially dangerous procedures
throughout this manual. Instructions contained in the warnings must be followed
during all phases of operation, service, and repair of this equipment. You should
also employ all other safety precautions necessary for the operation of the
equipment in your operating environment. Failure to comply with these
precautions or with specific warnings elsewhere in this manual could result in
personal injury or damage to the equipment.
The following general safety precautions must be observed during all phases of
operation, service, and repair of this equipment. Failure to comply with these
precautions or with specific warnings elsewhere in this manual could result in
personal injury or damage to the equipment.
The safety precautions listed below represent warnings of certain dangers of
which SANBlaze is aware. You, as the user of the product, should follow these
warnings and all other safety precautions necessary for the safe operation of the
equipment in your operating environment.
OBSERVE WARNINGS IN MANUAL. Warnings, such as those below,
precede potentially dangerous procedures throughout this manual. Instructions
contained in the warnings must be followed. You should also employ all other
safety precautions which you deem necessary for the operation of the equipment
in your operating environment.
WARNING - To prevent serious injury or death from dangerous voltages,
use extreme caution when handling, testing, and adjusting this equipment.
WARNING - DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE.
Do not operate the equipment in any explosive atmosphere such as in the
presence of flammable gases or fumes. Operation of any electrical equipment
in such an environment could result in an explosion and cause injury or
damage.
WARNING - KEEP AWAY FROM LIVE CIRCUITS INSIDE THE
EQUIPMENT. Operating personnel must not remove equipment covers.
Only Factory Authorized Service Personnel or other qualified service
personnel may remove equipment covers for internal subassembly or
component replacement or any internal adjustment.
CAUTION - The information given in this manual is meant to complete the
knowledge of a specialist and must not be used as replacement for qualified
personnel.
SB-ATCA7300 Installation and Use Guide
Safety-1
About This Manual
WARNING - Do not install substitute parts or perform any unauthorized
modification of the equipment or the warranty may be voided. Contact your
local SANBlaze representative for service and repair to make sure that all
safety features are maintained.
Flammability
All SANBlaze PWBs (printed wiring boards) are manufactured with a
flammability rating of 94V-0 by UL-recognized manufacturers.
EMC
This peoduct has been tested in a standard SANBlaze system and found to comply
with the limits for a Class A digital device in this system, pursuant to part 15 of
the FCC Rules, EN 55022 Class A respectively. These limits are designed to
provide reasonable protection against harmful interference when the system is
operated in a commercial environment.
This is a Class A product based on the standard of the Voluntary Control Council
for Interference by Information Technology Interference (VCCI). If this
equipment is used in a domestic environment, radio disturbance may arise. When
such trouble occurs, the user may be required to take corrective actions.
This blade generates and uses radio frequency energy and, if not installed properly
and used in accordance with this guide, may cause harmful interference to radio
communications. Operating the system in a residential area is likely to cause
harmful interference, in which case the user will be required to correct the
interference at his own expense.
Safety Statement
The SB-ATCA7300 is designed to comply with EN60950-1 Revision 2, and is
intended to be used with similarly tested AdvancedTCA products that have a
user's guide detailing user installation.
CE Notice (European Community)
SANBlaze Technology products with the CE marking comply with the EMC
Directive (89/336/EEC). Compliance with this directive implies conformity to the
following European Norms:
Safety-2

EN55022 ―Limits and Methods of Measurement of Radio Interference
Characteristics of Information Technology Equipmentǁ; this product tested to
Equipment Class A

EN50024-1:1998 ―Information Technology Equipment - Immunity
Characteristics -Limits and Methods of Measurement Amendment A1:2001,
Amendment A2:2003
SB-ATCA7300 Installation and Use Guide
About This Manual
System products also fulfill EN60950 (product safety), which is essentially the
requirement for the Low Voltage Directive (73/23/EEC).
Board products are tested in a representative system to show compliance with the
above mentioned requirements. A proper installation in a CE-marked system will
maintain the required EMC/safety performance.
In accordance with European Community directives, a Declaration of Conformity
has been made and is on file within the European Union. The Declaration of
Conformity is available on request. Please contact your sales representative.
Installation
CAUTION - Electrostatic discharge and incorrect blade installation and removal
can damage circuits or shorten their life. Before touching the blade or electronic
components, make sure that you are working in an ESD-safe environment.
CAUTION - Removing the blade with the blue LED off or still blinking can
cause data loss. Wait until the blue LED is permanently illuminated before
removing the blade from the chassis.
CAUTION - Incorrect installation of additional devices or modules may damage
the blade or the additional devices or modules. Before installing or removing an
additional device or module, read the respective documentation
Operation
CAUTION - Operating the blade without adequate forced air cooling may lead to
blade overheating and blade damage. When operating the blade, make sure that
forced air cooling is available in the shelf.
Switch Settings
CAUTION - Blade configuration switches marked reserved can affect
production-related functions, and can cause the blade to malfunction, if their
setting is changed. Do not change settings of switches marked as reserved. The
setting of switches which are not marked as 'reserved' should be checked and set
before blade installation.
Battery
WARNING - Installation of the wrong battery may result in a hazardous
explosion and blade damage. Always use the same type of Lithium battery as
is installed and make sure the battery is installed as described in this manual.
Safety-3
SB-ATCA7300 Installation and Use Guide
About This Manual
Environment
Always dispose of used blades, system components and RTMs according to your
country’s legislation and manufacturer’s instructions.
Notice
While reasonable efforts have been made to assure the accuracy of this document,
SANBlaze Technology, Inc. assumes no liability resulting from any omissions in
this document, or from the use of the information obtained therein. SANBlaze
reserves the right to revise this document and to make changes from time to time
in the content hereof without obligation of SANBlaze to notify any person of such
revision or changes.
Electronic versions of this material may be read online, downloaded for personal
use. The text itself may not be published commercially in print or electronic form,
edited, translated, or otherwise altered without the permission of SANBlaze
Technology, Inc.
Safety-4
SB-ATCA7300 Installation and Use Guide
About This Manual
This manual supports the following configurations and model numbers.
Part Number
SB-ATCA7300
Description
AdvancedTCA High Performance Intel Server Blade
How This Manual Is Organized

Safety Notes lists safety information applicable to the SB-ATCA7300.

Chapter 1 "Introduction" describes the features of the SB-ATCA7300
blade.

Chapter 2 "Functional Description" describes the functional blocks of the
blade in detail. This includes a block diagram, description of the main
components used and similar information.

Chapter 3 "Hardware Preparation and Installation" outlines the
installation requirements, hardware accessories, switch settings, and
component installation and removal procedures.

Chapter 4 "Controls, Indicators, and Connectors" describes the external
interfaces of the blade. This includes connectors and LEDs.

Chapter 5 "BIOS Configuration" describes the features and setup of the
SB-ATCA7300 BIOS.

Chapter 6 "Maps and Registers" provides information on the blade’s
internal data maps and configuration registers.

Chapter 7 "Serial Over LAN" provides information on how to establish a
serial-over LAN session with your blade’s IPMC.

Chapter 8 "FRU Information and Sensor Data Records" gives detailed
information on the blade’s ATCA FRU information and sensor data.

Chapter 9 "SB-ATCA7300 Firmware Updates" shows how to update the
blade’s firmware components.

Appendix A "Replacing the Blade Battery" descrbes the battery
replacement procedure.

Appendix B "BIOS Status Codes" lists the status and beep codes issued
by the various BIOS components.

Appendix C "Supported IPMI Commands" lists and describes the IPMI
commands supported by the blade.
SB-ATCA7300 Installation and Use Guide
Safety-1
About This Manual
Abbreviations
This document uses the following abbreviations.
Abbreviation
Safety-2
Definition
AC
Alternating Current
ANSI
American National Standards Institute
API
Application Programming Interface
APIC
Advanced Programmable Interrupt Controller
ATA
Advanced Technology Attachment
ATCA
Advanced Telecommunications Computing
Architecture
BDS
BIOS Boot Device Selection phase
BIOS
Basic Input/Output System
CAS
Column Address Strobe
CMOS
Complementary Metal Oxide Semiconductor
CPU
Central Processing Unit
DDR
Double Data Rate
DIMM
Dual Inline Memory Module
DMA
Direct Memory Access
DPLL
Digital Phase Locked Loop
DRAM
Dynamic Random Access Memory
DXE
BIOS Driver Execution Environment phase
ECC
Error-Correction Code
EMC
Electromagnetic Compatibility
EMV
Elektromagnetische Vertraeglichkeit
EN
European Norm
ESCD
Extended System Configuration Data
ESD
Electrostatic Sensitive Device
eUSB
Embedded USB
FAE
Field Application Engineers
FC
Fibre Channel
FCC
Federal Communications Commission
FIFO
First In First Out
FPGA
Field-Programmable Gate Array
SB-ATCA7300 Installation and Use Guide
About This Manual
Abbreviation
Safety-3
Definition
FRU
Field Replaceable Unit
GmbH
Gesellschaft mit beschraenkter Haftung
GND
Ground
HDD
Hard Disk Drive
HPM.1
Hardware Platform Management 1
IDE
Integrated Device Electronics
IEC
International Electric Code
IEEE
Institute of Electrical and Electronics Engineers
IPMB
Intelligent Platform Management Bus
IPMC
Intelligent Platform Management Controller
IPMI
Intelligent Platform Management Interface
ISA
Industry Standard Architecture
ISO
International Organization for Standardization
KCS
Keyboard Controller Style
LCCB
Line Card Clock Building Block
LED
Light Emitting Diode
LFM
Linear Feet per Minute
LPC
Low Pin Count bus
MAC
Media Access Control
MTD
Memory Technology Device
MVCGE
MontaVista Carrier Grade Edition (Linux)
NEBS
Network Equipment Building System
NMI
Non-Maskable Interrupt
NVRAM
Nonvolatile Random Access Memory
OEM
Original Equipment Manufacturer
OOS
Out-Of-Service
OS
Operating System
PCB
Printed Circuit Board
PCI
Peripheral Component Interconnect
PEI
BIOS Pre-EFI Initialization phase
PEM
Power Entry Module
PICMG
PCI Industrial Computer Manufacturers Group
PMC
PCI Mezzanine Card
SB-ATCA7300 Installation and Use Guide
About This Manual
Abbreviation
Safety-4
Definition
POST
Power-On Self-Test
PROM
Programmable Read-Only Memory
PTMC
PCI Telecom Mezzanine Card
RAM
Random Access Memory
RHEL
Red Hat Enterprise Linux
RoHS
Restriction of the use of Certain Hazardous
Substances
ROM
Read-Only Memory
RT
BIOS Run Time phase
RTC
Real Time Clock
RTM
Rear Transition Module
SAS
Serial Attached SCSI
SATA
Serial ATA
SCSI
Small Computer System Interface
SDR
Sensor Data Record
SDRAM
Synchronous Dynamic Random Access Memory
SEC
BIOS Security phase
SELV
Safety Extra Low Voltages
SFMMOD
SRAM Flash Memory Module
SMI
Serial Management Interface
SOL
Serial Over LAN
SPD
Serial Presence Detect
SPI
Serial Peripheral Interface
SRAM
Static Random Access Memory
SROM
Serial Read-Only Memory
TSL
BIOS Transient System Load phase
UEFI
Unified Extensible Firmware Interface
UL
Underwriters Laboratory Inc.
USB
Universal Serial Bus
VGA
Video Graphics Array
VLAN
Virtual Local Area Network
VLP
Very Low Profile
WDT
Watchdog Timer
SB-ATCA7300 Installation and Use Guide
About This Manual
Conventions Used in This Manual
The following table describes the conventions used throughout this manual.
Notation
Description
0x00000000
Typical notation for hexadecimal numbers
(digits are 0 through F), for example used for
addresses and offsets
0b0000
Same for binary numbers (digits are 0 and 1)
bold
Screen
Courier +
Bold
Reference
text
Used to emphasize a word
Used for on-screen output and code related
elements or commands in body text
Used to characterize user input and to
separate it from system output
Used for references and for table and figure
descriptions
Notation for variables and keys
...
Repeated item for example node 1, node 2,
..., node 12
.
.
.
Omission of information from example or
command that is not needed
..
Ranges, for example: 0..4 means one of the
integers 0,1,2,3, and 4 (used in registers)
|
Logical OR
Indicates a hazardous situation which, if not
avoided, could result in death or serious
injury
Indicates a hazardous situation which, if not
avoided, may result in minor or moderate
injury
Indicates a property damage message, or an
action which, if done incorrectly, could lead
to data loss or an extended recovery time.
No danger encountered. Pay attention to
important information
Safety-5
SB-ATCA7300 Installation and Use Guide
About This Manual
Safety-6
SB-ATCA7300 Installation and Use Guide
1 Introduction
1.1 SB-ATCA7300 Overview
The SANBlaze SB-ATCA7300 is a high performance dual processor
AdvancedTCA Server blade designed according to PICMG 3.0 Revision 3.0
Advanced TCA Base Specification. SB-ATCA7300 is a single board computer
that offers a powerful processing complex through dual six core Intel L5638
(Westmere-EP) processors providing a symmetrical MP architecture with support
for up to 192 GB of DDR3 memory.
The SB-ATCA7300 provides local storage through optional SATA-Cube SSD
and eUSB flash devices. It has dual 1 Gb Ethernet connections to the ATCA
backplane Base networks, and dual 10 Gb Ethernet Fabric network interfaces
(PICMG 3.1 option 9).
The SB-ATCA7300 provides system management capabilities and is hot swap
compatible as per the ATCA specification. The power and flexibility of the design
makes it ideally suited for the military, telecom, datacom and commercial
markets.
1.2 SB-ATCA7300 Features
The SB-ATCA7300 is a high-performance ATCA-compliant single board
computer designed for demanding storage and processing applications.
 Intel L5638 (Westmere-EP) six core CPU with two 5.86 GT/s QuickPath
interconnect (QPI) links per CPU

Integrated 3-channel DDR3 memory controller per CPU, for a total of 6
DDR3 channels





2 VLP DIMM slots per channel, totaling 12 DIMM slots per blade
DDR3 speeds of 800, 1066, and 1333 MT/s supported
DIMM sizes of 512MB, 1GB, 2GB, 4GB, 8GB and 16GB supported
Regular (1.5 V) and Low Voltage (1.35 V) DIMMs supported
Intel Xeon 5520 (Tylersburg IOH36 D) chipset with two Intel Quick Path
interconnects



Connects to both CPUs of the SB-ATCA7300 server blade
Provides 36 PCIe Gen2 lanes
Supportes Intel Virtualization Technology

Express 58 (ICH10R) Soutbridge connects through the Enterprise South
Bridge Interface (ESI) to Xeon 5520

Dual SPI BIOS boot flash memories
SB-ATCA7300 Installation and Use Guide
1-1
Introduction








Dual 1Gb Ethernet AdvancedTCA Base interfaces

IPMC Serial over LAN connectivity extension using the Base network
interface

1 MB IPMC boot and 1 MB backup boot Flash devices
Dual 10 G Ethernet AdvancedTCA Fabric interfaces
Zone 3 I/O routing in support of a ATCA Rear Transition Module
Update Channel is routed to the RTM Zone 3 interface
Optional onboard eUSB Flash module with 8 GB capacity
Optional onboard SATA-Cube SSD module with 32 or 64 GB capacity
One serial RS232 RJ-45 interface connection to the front panel
Onboard IPMI Management Controller (IPMC) supporting IPMI version
1.5
1.3 Standards Compliance
The SB-ATCA7300 is designed to meet or exceed the following standards.
Table 1-1 Standards Compliance
Standard
Description
SN29500/8,
MIL-HDBK-217F,
GR-332,
TR-NWT-000357
Reliability requirements
IEC 60068-2-1/2/3/13/14
IEC 60068-2-27/32/35
Climatic environmental requirements and
mechanical environmental requirements
EN 60950/UL 60950
(in predefined Force system)
Legal requirements, safety
UL 94V-0/1, Oxygen index for
PCBs below 28%
Flammability
VCCI:V-3/2010.04
EN 55024
EN 61000-6-2
EN 300386 FCC Part 15 Class A
C-TICK:AS/NZS CISPR
22:2009
ICES-003:2004
EMC requirements on system level
Attention: ATCA boards require CISPR 22 Class A
on conducted emissions
EMC immunity requirements industrial
EMC for telecom equipment
ISO 8601
Y2K compliance
SB-ATCA7300 Installation and Use Guide
1-2
Introduction
Table 1-1 Standards Compliance (Continued)
Standard
Description
NEBS Standard GR-63-CORE,
NEBS level three
NEBS Standard GR-1089 CORE Product is designed to support NEBS level three.
The compliance tests must be done with the
customer target system.
PICMG 3.0 and 3.1
Defines mechanics, blade dimensions, power
distribution, power and data connectors, and system
management.
1.3.1 Compliance Notes

To fulfill the requirements of Telcordia GR-1089,R4-14, use Shielded
Twisted Pair (STP) cables grounded at both ends to connect to the
Ethernet ports.

This blade contains an embedded power source rated above 150 W. To
achieve NEBS compliance on a system level, the Shelf Ground (chassis
ground) and Logic Ground (logic signal return) must be connected. This
connection may be implemented inside the shelf, for example at the
backplane, or the shelf must provide the ability to connect Logic Ground
out of the shelf for external connection to Central Office Ground. For
further information refer to Telcordia GR-1089-CORE, section 9.8.2,
requirement R9-14.

The SB-ATCA7300 has been designed to meet the directive on the
restriction of the use of certain hazardous substances in electrical and
electronic equipment (RoHS) Directive 2002/95/EC.

REACH compliance for SVHC (Substances of Very High Concern):
REACH (Registration, Evaluation, Authorization and Restriction of
Chemicals) is an EU Regulation to control a list of hazardous chemicals
and their safe use. When used in normal or reasonably predictable
conditions, the SB-ATCA7300 contains no SVHC substances in
concentrations exceeding 0.1 % weight by weight (w/w), based on
research and statements collected from our suppliers. This product, with
no intentional emission of SVHC, has no pre-registration obligation (Art.
7 sub-paragraph 1 point b), REACH Directive (EC 1907/2006).

WEEE Directive (2002/96/EC), which fosters responsible recycling:
SANBlaze Technology is a producer of embedded computer components
that fall outside the scope of the WEEE Directive. Items such as AMCs,
RTM and ATCAcards are generally not end products in themselves but
become part of a larger system or another supplier’s product which itself
may or may not be within the scope of WEEE legislation.
SB-ATCA7300 Installation and Use Guide
1-3
Introduction
1.4 Mechanical Data
The following table provides details about the blade's mechanical data, such as
dimensions and weight.
Table 1-2 Mechanical Data
Feature
Value
Dimensions (width x height x depth) 283.79 mm x 322.25 mm x 30.48 mm
11.17 in x 12.69 in x 1.2 in
Weight of blade
3.7 kg/8.16 lb
1.5 Product Identification Labels
Figure 1-1 below shows the location of the Product Part Number, Revision, and
Serial Number labels.
Figure 1-1 Product Identification Labels and Locations
SB-ATCA7300 Installation and Use Guide
1-4
Introduction
1.5.1 Blade Serial Number
The SB-ATCA7300 blade serial number has the following format:
730EYMMssss. The breakdown of this format is shown in Table 1-3 below.
Table 1-3 SB-ATCA7300 Serial Number Breakdown
Section
730
Meaning
Indicates the SB-ATCA7300 blade
E
Manufacturing site code
Y
Year of manufacture (Decimal: 1=2011, 2=2012, ...)
MM
Month of manufacture (01=January, 02=February, ...)
ssss
Manufacturing sequence number (0-9999)
1.6 Ordering Information
The following table lists the blade variants that are available upon release of this
publication. Consult your local SANBlaze sales representative for the availability
of other models.
Table 1-4 Blade Model
Product Name
Description
SB-ATCA7300
Dual Intel Westmere-EP Quad/Six-Core CPU (L5638), 2.0
GHz, 12 MB Last Level Cache, with 12 DIMM sockets, video
module
SB-ATCA7300G48
Same as above, with 48 GB installed memory
SB-ATCA7300G96
Same as above, with 96 GB installed memory
SB-ATCA7300G192
Same as above, with 192 GB installed memory
The following table lists the blade accessories that are available upon release of
this publication. Consult your local sales representative for the availability of
other accessories
Table 1-5 Blade Accessories
Accessory
Description
SB-7300MEM8G
8 GB DDR3 VLP 1.5V memory module for SB-ATCA7300
SB-7300MEM16G
16 GB DDR3 VLP 1.5V memory module for SB-ATCA7300
SB-7300SC32
32 GB on-board solid state SATA disk for SB-ATCA73001
SB-7300SC64
64 GB on-board solid state SATA disk for SB-ATCA73001
SB-ATCA7300 Installation and Use Guide
1-5
Introduction
Table 1-5 Blade Accessories (Continued)
Accessory
Description
SB-7300EU04
eUSB boot module, 4 GB capacity
SB-7300EU08
eUSB boot module, 8 GB capacity
SB-7300SFMMOD Reset persistent memory module, 16MB SRAM
64MBFlash for the SB-ATCA73001
SB-RTM404
RTM I/O Expansion (PCIe/SAS) Module
SB-RTM415
RTM Video, USB, Ethernet, RAID controller, 2 SAS disks
1. The persistent memory module and the solid state disk are mutually exclusive.
SB-ATCA7300 Installation and Use Guide
1-6
2 Functional Description
2.1 Block Diagram
The block diagram shows how the SB-ATCA7300 components work together and
the data paths used.
Figure 2-1 SB-ATCA7300 Block Diagram
SB-ATCA7300 Installation and Use Guide
2-1
Functional Description
2.2 Processor
The SB-ATCA7300’s Intel L5638 (Xeon 5600, Westmere-EP) CPUs are six core
processors, based on a 32nm process technology and the Intel Nahelem micro
architecture. Each processor features two Intel QuickPath Interconnect point-topoint links capable of up to 5.86 GT/s, 12 MB of shared level 3 cache, and an
Integrated Memory Controller (IMC).
Table 2-2 Intel L5638 Processor Characteristics
Feature
Intel L5638 Processor
Cache Size
- Instruction Cache – 32 KB per core
- Data Cache – 32 KB per core
- 256 KB level 2 cache per core
- 12 MB level 3 cache, share among all cores
Data transfer rate
Two full-width Intel® QuickPath Interconnect links
5.86 GT/s in each direction
Multi-Core support Six cores per processor
Hyper-Threading
Two threads per core
Twelve threads per processor
Memory Support
48 GB per processor, as implemented
2.2.1 Processor Speeds
The SB-ATCA7300 has the ability to run its processors at two different speeds.
These speeds are based on the board power level.
By default, to comply with the ATCA 200 W/slot cooling limits, the processors
run at 1.87 GHz (power level 1). If the Shelf Manager determines that the slot has
260 W or more of cooling capabiity, the SB-ATCA7300 processor speeds will be
increased to 2.0 GHz (power level 2).
CAUTION - Do not use the Shelf Manager to increase the cooling capacity of an
ATCA chassis slot to more than the chassis is rated to handle. This can cause
permanent damage to the blade in the slot, other blades in the chassis, and to the
chassis itself.
SB-ATCA7300 Installation and Use Guide
2-2
Functional Description
2.2.2 Intel L5638 Processor Features
The Intel processors feature a wide range of processing features to enhance
performance and functionality. The table below indicates those provided by the
Intel L5638 processor.
Table 2-3 Intel L5638 Processor Features
Feature
Support
AES instructions
Yes
EM64T technology
Yes
Execute Disable bit
Yes
Hyper-Threading technology
Yes
MMX instruction set
Yes
SSE instructions
Yes
SSE2 instructions
Yes
SSE3 instructions
Yes
SSE3 Supplemental instructions
Yes
SSE4.1 instructions
Yes
SSE4.2 instructions
Yes
Trusted Execution Technology
Yes
Turbo Boost Technology
Yes
Virtualization Technology (VT-c)
Yes
Virtualization Technology (VT-d)
Yes
Virtualization Technology (VT-x)
Yes
Note - The processor’s Hyper-threading and the VT-d features are disabled by
default. See section 5.5.2.1 “CPU Configuration” on page 5-17 and section
5.5.2.3.1 “Intel® VT for Directed I/O Configuration” on page 5-20, respectively,
for more information.
2.3 Intel QuickPath Interconnect
Intel’s QuickPath Interconnect (QPI) is used to connect the two L5638 processors
to each other and to the Intel 5520 I/O Hub. The QPI’s main features are:
 Point to point link architecture


Differential, full-duplex connections
The L5638 runs at a 5.86 GT/s (billion transactions per second) QPI rate
SB-ATCA7300 Installation and Use Guide
2-3
Functional Description
2.4 Integrated Memory Controller
The Intel L5638 CPU features an integrated memory controller. The memory
controller provides three memory channels that allow flexible memory
configurations.
Only DDR3 DIMM technology is supported. Different types of DDR3 memory
modules can be installed, including registered DIMMs with ECC and un-buffered
DIMMs either with or without ECC. DIMM speeds can be DDR3-800, DDR31066 or DDR3-1333. DIMMs of different speed selections can be mixed, but the
lowest speed present in any channel will set the speed for all three of a CPU’s
memory channels.
SB-ATCA7300 supports Low Voltage LVDDR3 Memory running at 1.35 V,
which reduces the power consumption and improves the thermal performance of
the blade. Either standard DDR3 (1.5 V) or the LVDDR3 (1.35V) DIMMS can be
used. Mixing DIMMs with different voltage levels on a board is not supported.
2.4.1 SATA-Cube/SFMMOD module
The SB-ATCA7300 has a connector that can be used for either a SATA-Cube
SSD or a SFMMOD module. See section 3.6.2 “SSD and SFMMOD Module
Installation” on page 3-13 for more information.
2.5 Intel Xeon 5520 I/O Hub
The Intel Xeon 5520 I/O Hub provides connectivity between the two processors
and the I/O subsystem. The hub provides 36 PCI Express generation 2 (Gen 2)
lanes (see section 6.2 “PCI Express Lane Mapping” on page 6-4). The blade uses
one x8 PCIe bus and one x4 PCIe bus to connect to the on-board Ethernet
controllers, and two x4 PCIe buses are routed to the Zone 3 connector.
The Xeon 5520 is further connected to the ICH10R I/O Controller by the
Enterprise South Bridge Interface (ESI).
2.6 Intel ICH10R I/O Controller
The Intel ICH10R I/O controller provides extensive I/O interface support,
including the boot path to the SPI Boot Flash (BIOS) devices for the processors.
The ICH10R is connected to the system through a four-lane (x4) Enterprise
Southbridge Interface (ESI) of the Intel 5520 I/O Hub.
The following is a list of the main internal features and the I/O interface functions
provided by the ICH10R I/O controller.
 Six x4 PCI Express 1.1 Interface


LPC interface
SPI Interface for boot flash
SB-ATCA7300 Installation and Use Guide
2-4
Functional Description














Six serial ATA (SATA) interfaces (2 used on SB-ATCA7300)
Twelve USB 2.0 interfaces (5 used on SB-ATCA7300)
Two 8259 Interrupt Controllers and I/O APIC controllers
Integrated I/O APIC
Power management support
Two 8237 DMA controller
8254 based Counter Timer/timers
High Precision Event Timers (HPET)
RTC with 256-byte battery-backed SRAM
System TCO (total cost of ownership) Reduction circuits
SMBus interface
Two watchdog timers (IPMC and OS boot)
PCI 2.3 interface 32-bit/ 33 MHz (connects to SFMMOD module)
General purpose I/O pins
The SB-ATCA7300 does not provide a legacy Super-IO device or legacy
keyboard and mouse serial interfaces. A keyboard and mouse are supported
through the USB 2.0 ports on the front panel. Serial COM interfaces are provided
from the FPGA. The available Super IO functionality is integrated into the
ICH10R.
2.7 Ethernet Ports
The SB-ATCA7300 has two Ethernet controllers that serve the ATCA Base
interface, Fabric interface, ARTM, and front panel. All of the Ethernet interfaces
have 10/100/1000 Mb capability except for the Fabric interface controller which
can operate only at 1 Gb or 10 Gb (PICMG 3.1 Option 9).
The Ethernet controllers supports I/O virtualization using VT-c, the Intel
Virtualization Technology for Connectivity feature.
Table 2-4 Ethernet Controller Types
Interface
Location
Controller
Count
Ethernet Type
Base Interface
RTM interface
P23
Intel I350-AM4
4
10/100/1000 Mb copper
Fabric Interface
P23
Intel 82599
2
1Gb/10Gb Serdes
Faceplate Interface P27
Intel 82567
1
10/100/1000 Mb copper
SB-ATCA7300 Installation and Use Guide
2-5
Functional Description
2.8 Embedded USB Disk Module
An optional 8 GB Embedded USB (eUSB) flash device is available for the SBATCA7300. This add-on module installs onto to the motherboard, and can hold
data, application software and OS boot images. Booting from this device is
supported. The flash disk controller provides a wear leveling algorithm to
improve the lifetime of the flash device.
2.9 BIOS
SB-ATCA7300 provides a BIOS firmware that is stored in flash memory (see the
previous section). It can be updated over Ethernet or locally by the operating
system. Along with the BIOS and BIOS Setup program, the flash memory devices
contain POST and Plug and Play support.
The BIOS displays a message during POST identifying the type of BIOS and a
revision code.
See Chapter 5 "BIOS Configuration" for more information.
2.9.1 BIOS Flash Memory
The Blade has two physically separate 1 MB flash devices hosting the BIOS
firmware:
 Primary (or Default BIOS) Flash (SPI 0)

Recovery (or backup) BIOS Flash (SPI 1)
The flash devices are used to hold the BIOS. The SB-ATCA7300 boots from the
primary flash (SPI 0) under normal circumstances. If booting the BIOS from
primary flash fails, the IPMC automatically changes the flash device select logic
to boot from the recovery flash (SPI 1). The image that the processor will boot
from after a reset is determined by the IPMC, or by the setting of blade switches.
2.10 IPMC
The SB-ATCA7300 includes an Intelligent Platform Management Controller
(IPMC) compliant to PICMG 3.0 and IPMI 1.5 and 2.0 (Serial over LAN support
only). The IPMC is a management subsystem that provides blade management,
monitoring, event logging, and recovery control. The IPMC serves as the gateway
for management applications to access the blade hardware.
The IPMC supports the Serial Over LAN (SOL) feature from IPMV v.2 for use as
the blade’s serial console port. The SOL interface is available over the ATCA
base network interface. SOL is activated by specific IPMI commands. (See
section 2.12 “Serial Over LAN” on page 2-8 and Chapter 7 "Serial Over LAN" for
more information.)
SB-ATCA7300 Installation and Use Guide
2-6
Functional Description
The IPMC provides the ability to signal a graceful shutdown request to the blade
OS. (See section C.4.16 “Graceful Reset Command” on page C-29.) The IPMC
can also force the processors to reset. The IPMC also controls power and general
reset of the blade processors, and helps control component power sequencing.
2.10.1 IPMC Firmware
The IPMC firmware is stored in two independent memory images. A recovery
mechanism is provided to permit the reboot of the IPMC from a second image if
the primary firmware image is corrupted. The IPMC firmware images can be
updated using IPMI and HPM.1 protocols, from the OS, the Shelf Manager, or
directly to the IPMC over Ethernet. (See Chapter 9 "SB-ATCA7300 Firmware
Updates" for more information.)
The IPMC also supports the update of the ARTM firmware.
2.10.2 IPMC Watchdog Timers
The IPMC provides a watchdog timer that supervises the blade OS boot. Enabled
by default, the blade’s OS must signal the IPMC to prevent a time-out and a boot
failure. The OS watchdog time-out can generate a non-maskable interrupt (NMI),
a payload reset or the power cycling of the blade. The watchdog settings,
including enable/disable, can be changed from the BIOS Setup menu. Time-out
values can be selected from as short as a few seconds to as long as several
minutes.
The IPMC boot is supervised by a separate hardware watchdog timer, which can
not be disabled. This timer will switch to the alternate IPMC firmware image if
the IPMC fails to boot properrly.
2.10.3 IPMC Status Information
The IPMC is connected to various sensors on the blade that provide temperature
sensor readings, voltage sensor readings and other status information. The IPMC
monitors all blade reset events caused by devices like watchdog timers, IPMI
commands, and the reset button.
The ATCA FRU information from the components including blade and ARTM
can be obtained through the IPMC.
See Chapter 8 "FRU Information and Sensor Data Records" for more information.
2.11 Serial Port Redirection
Serial port redirection allows the rerouting of console input and output; that is, the
text output to the screen and input from the keyboard. The console typically is
used by the BIOS setup menus, BIOS initialization and boot routines, OS boot
loaders and loaded OS.
SB-ATCA7300 Installation and Use Guide
2-7
Functional Description
The serial console can be redirected to:
 The front panel serial port



The front panel VGA port
An ARTM serial port
A Serial Over LAN (SOL) session (the front panel serial port will only
display outut at this time)
If needed, an IPMC serial console can be accessed from the front panel serial
connector. This can be requested by using a specific IPMI OEM command. (See
section C.3.1 “Serial Output Commands” on page C-15.)
2.12 Serial Over LAN
Serial Over LAN (SOL) is a feature of IPMI v.2 that has been inpmented in the
SB-ATCA7300 IPMC. It allows a remote client to communicate directly with the
blade’s IPMC over an Ethernet interface on the Base network.
This enables users at remote consoles to access the serial port of a blade/server
and interact with a text-based BIOS console, operating system, command line
interfaces, and serial text-based applications.
Client software such as ipmitool is required to enable SOL and to
communicate with the SOL based serial console.
See Chapter 7 "Serial Over LAN" for more information.
2.13 Blade Front Panel
The blade's front panel provides the following interfaces and control elements:
 Two USB 2.0 ports





A serial console port
Out of Service, In Service, Attention, and Hot Swap LEDs
One 10/100/1000 Mb Base-T Ethernet port
One VGA graphics port
Recessed reset button
2.14 USB 2.0 Interfaces
The blade’s ICH10R I/O controller provides internal USB1.1/ 2.0 host controllers.
Two USB ports are routed to the front panel, one port is used onboard to connect
an eUSB flash module, and two ports are routed to the ARTM.
SB-ATCA7300 Installation and Use Guide
2-8
Functional Description
2.15 Real Time Clock Battery
The provided battery is a +3V lithium battery (CR-2032) with a capacity of
200mAh, which provides 3 years of backup with no external power, and up to
seven years of life in use.
See Appendix A "Replacing the Blade Battery" for more information.
SB-ATCA7300 Installation and Use Guide
2-9
Functional Description
SB-ATCA7300 Installation and Use Guide
2-10
3 Hardware Preparation and
Installation
3.1 Unpacking and Inspecting the Blade
To inspect the shipment, perform the following steps.
1. Verify that you have received all items of your shipment:


SB-ATCA7300 blade
Any optional items ordered
2. Check for damage and report any damage or differences to customer service.
3. Remove the desiccant bag shipped with the blade and dispose of it
appropriately.
Note - The blade is thoroughly inspected before shipment. If any damage
occurred during transportation or any items are missing, please contact our
customer service immediately.
3.2 Environmental and Power Requirements
In order to meet the environmental requirements, the blade has to be tested in the
system in which it is to be installed.
Before you power up the blade, calculate the power needed according to your
combination of blade upgrades and accessories.
3.2.1 Environmental Requirements
The environmental conditions must be tested and proven in the shelf configuration
used. The conditions refer to the surroundings of the blade within the user
environment.
CAUTION - The environmental requirements of the blade may be further limited
by installed accessories, such as hard disks or RTM modules, with more
restrictive environmental requirements than the board itself.
Note - Operating temperatures refer to the temperature of the air circulating
around the blade and not to the actual component or case temperature.
SB-ATCA7300 Installation and Use Guide
3-1
Hardware Preparation and Installation
Table 3-1 Environmental Conditions
Requirement
Operating
Non-Operating
Temperature
-5 °C to +55 °C
-40 °C to +70 °C
Forced Air Flow
Required
N/A
Air Volume
CPTA B.4
N/A
Pressure Loss
(Reference to sea level)
Temp. Change
0.15 H2O (37 Pa) at 30 CFM
+/- 0.5 °C/min
Relative Humidity
+/- 1 °C/min
5% to 95% non condensing at +40 °C
Altitude
-300 m to +3,000 m
-300 m to +13,000 m
Vibration
20 to 2000Hz
Sweep sine at a level 1.0g from
5-200Hz and return with a
sweep rate of 0.25 octaves/
minute.
5 g (RMS) random
5 g (RMS) random
Shock
5 g/30 ms half sine
15 g/11 ms half sine
Free Fall
1,200 mm/all edges and corners (packed state)
100 mm/3 axis (unpacked)
During the safety qualification of this blade, the following on-board locations
were identified as critical with regards to the maximum temperature during blade
operation. To guarantee proper blade operation and to ensure safety, you have to
make sure that the temperatures at the locations specified in the following are not
exceeded. If not stated otherwise, the temperatures should be measured by placing
a sensor exactly at the given locations.
Table 3-2 Critical Temperature Limits
Component
Intel L5638 processor
Xeon 5520 (Tylersburg IOH36 D)
Thermal Design
Power
60 W
27.1 W
SB-ATCA7300 Installation and Use Guide
Maximum Case or Junction
Temperature
Tcmax = 70°C for long term
operation, and Tcmax = 85°C for
short term operation
Tcmax = 95.1°C (case)
3-2
Hardware Preparation and Installation
Table 3-2 Critical Temperature Limits (Continued)
Thermal Design
Power
Component
Maximum Case or Junction
Temperature
ICH10R
4.5 W
Tcmax = 109°C
Intel 82599
8.82 W
Tcmax = 119°C
Intel I350
4W
Tcmax = 111°C (case)
DDR3 DIMM Module (pair)
3W
85° C
If you integrate the blade in your own system please contact your local sales
representative for further safety information.
3.2.2 Power Requirements
The SB-ATCA7300’s total power consumption will increase if you install an
RTM. When calculating total slot power requirements, you must consult the
documentation for the RTM and add its power requirements to the blade’s power
requirements shown in Table 3-3 below.
The SB-ATCA7300 can operate at two different power levels to support the
capabilities of the chassis and slot. The Shelf Manager sets power level based on
power available to the slot.
Table 3-3 Power Requirements
Characteristic
ATCA7300
Rated Voltage
Exception in the US and Canada
-48 VDC to -60 VDC
-48 VDC
Operating Voltage
Exception in the US and Canada
-40 VDC to -72 VDC
-40 VDC to -60 VDC
Max. power consumption of SB-ATCA7300
(Power level 1 = Reduced speed mode)
196 W
Max. power consumption of SB-ATCA7300
(Power level 2 = Standard/fast mode)
260 W
See section 2.2.1 “Processor Speeds” on page 2-2 for a discussion of the processor
speed modes.
Use the IPMI/ATCA command Get Power Level to see the current power
level for an active blade.
The blade provides two independent power inputs according to the AdvancedTCA
Specification. Each input has to be equipped with an additional fuse of max. 90 A
SB-ATCA7300 Installation and Use Guide
3-3
Hardware Preparation and Installation
located either in the shelf where the blade is installed or the power entry module
(PEM).
3.2.2.1 Power Inputs
When connected to a -60 V power source, the SB-ATCA7300 must be connected
to a TNV-2 or a safety-extra-low-voltage (SELV) circuit. A TNV-2 circuit is a
circuit whose normal operating voltages exceed the limits for a SELV circuit
under normal operating conditions, and which is not subject to overvoltages from
telecommunication networks.
CAUTION - Power consumption has been measured using specific boards in a
configuration considered to represent the worst-case (with 20 W RTM, maximum
memory population, USB Flash, SF-MEM persistent memory module) and with
software simultaneously exercising as many functions and interfaces as possible.
This includes a particular load software provided by Intel designed to stress the
processors to reach their theoretical maximum power specification.
Any difference in the system configuration or the software executed by the
processors can affect the actual power dissipation. Depending on the actual
operating configuration and conditions, customers can see slightly higher power
dissipation, or it may even be significantly lower. There is also a dependency on
the batch variance of the major components like the processor and DIMMs used.
Hence, SANBlaze does not represent or warrant that measurement results of a
specific board provide guaranteed maximum values for a series of boards.
SB-ATCA7300 Installation and Use Guide
3-4
Hardware Preparation and Installation
3.3 Blade Layout
The following figure shows the location of components on the SB-ATCA7300.
CPU 1
CPU 1
Memory
Intel
5520
I/O Hub
Intel
ICH10R
I/O Ctlr
SATA/
SFMMOD
Connector
SATA/
SFMMOD
Screw
Mounts
eUSB
Flash
Connector
Intel
82599
CPU 0
Memory
VGA
Module
CPU 0
Battery
(Under
VGA)
1 2 3 4
Switches
(On back
of board)
Power
Supply
Figure 3-1 SB-ATCA7300 Blade Layout


The VGA module is installed over the battery (at the lower left)
The blade control switches (see the following section) are located under
the board where shown in the diagram above.
3.4 Board Control Switch Settings
The blade provides the configuration switches SW1, SW2, SW3 and SW4. Their
location is shown in Figure 3-1 above. Remember that these are located on the
back side of the board.
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Hardware Preparation and Installation
CAUTION - If you change a switch setting, remember to set it back to its default
position when you have completed your work to avoid unexpected problems.
CAUTION - Switches marked as reserved can affect production-related
functions, and can cause the blade to malfunction, if their setting is changed. Do
not change settings of switches marked as reserved. The setting of switches
which are not marked as 'reserved' should be checked and set before blade
installation.
CAUTION - Setting or resetting the switches during operation can cause blade
damage. Check and set switch settings before you install the blade.
CAUTION - For normal operation, all switches must be OFF. Switches are used
only for repair, manual maintenance and critical crisis recovery. For remote
maintenance and in order that all firmware update features through IPMC are
available, all switches must be in their default OFF position and are controlled
through IPMC.
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Hardware Preparation and Installation
3.4.1 Control Switch Settings
Table 3-4 Board Control Switch Settings
Switch
Description
SW1-1
Default Boot-Flash 0 (BIOS) image write protection
OFF: Write-enabled (default)
ON: Write-protected
SW1-2
Recovery Boot-Flash (BIOS) image write protection
OFF: Write-enabled (default)
ON: Write-protected
SW1-3
Normal or debug-socket SPI boot select
OFF: Boot from Normal SPI flash (either Default or Backup) (default)
ON: Boot from debug socket SPI flash
SW1-4
ICH10 GPIO33-Pinstrap: SPI Flash Descriptor Security Override Strap
and ME disable
OFF: No SPI Flash Descriptor security override and ME working in S0/S1
(default)
ON: Flash security descriptor and ME disabled (for debugging only)
SW2-1
Serial Line #1 and #2 Routing
OFF: FPGA-COM#1 to front panel, FPGA-COM#2 to RTM (default)
ON: FPGA-COM#1 to RTM, FPGA-COM#2 to front panel
SW2-2
IPMC Debug Console Routing (Set off for normal operation)
OFF: IPMC debug console at 3-pin header (default)
ON: IPMC debug console at front panel instead of FPGA COM
SW2-3
FPGA-Bitstream PROM selection
OFF: FPGA loads from Default image PROM
ON: FPGA loads from Backup image PROM
SW2-4
XILINX Flash or SPI Flash Type for FPGA image PROM
OFF: SPI
ON: XIL Flash
SW3-1
Enable manual “Default Boot Flash” / “Backup Boot Flash” selection
OFF: IPMI selects boot flash (default)
ON: SW3-2 selects Boot Flash
SW3-2
SW3-2 controls boot flash selection if SW3-1 is set to ON
OFF: Boot from “Default Boot Flash” device (default)
ON: Boot from “Backup Boot Flash” device
SW3-3
Enable front panel (Frontboard and RTM) reset push button
OFF: Reset push button enabled (default)
ON: Reset push button disabled
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Hardware Preparation and Installation
Table 3-4 Board Control Switch Settings (Continued)
Switch
Description
SW3-4
ICH10 TCO Timer system reboot feature
OFF: ICH10 TCO Timer system reboot feature enabled (default)
ON: ICH10 will disable the TCO Timer system reboot feature
SW4-1
Reserved
OFF: Default
SW4-2
ICH10 TCO Timer system reboot feature
OFF: ICH10 TCO Timer system reboot feature enabled (default)
ON: System is strapped to the “No Reboot” mode (ICH10 will disable the
TCO Timer system reboot feature).
SW4-3 and SW4-4 Load BIOS default settings
OFF, OFF: Normal operation (default)
OFF, ON: Load BIOS default from IPMI Boot Parameter DEFAULT area
ON, OFF: Crisis recovery
ON, ON: Status codes reported to seerial port
3.5 Installing and Removing the Blade
The blade is fully compatible to the AdvancedTCA standard and is designed to be
used in AdvancedTCA shelves. The blade can be installed in any AdvancedTCA
node slot. Do not install this blade in an AdvancedTCA hub slot.
CAUTION - Electrostatic discharge and incorrect blade installation and removal
can damage circuits or shorten their life. Before touching the blade or electronic
components, make sure that you are working in an ESD-safe environment.
CAUTION - Incorrect blade installation and removal can result in blade
malfunctions. When installing or removing the blade, do not press or pull on the
front panel; use the handles instead.
3.5.1 Installing the Blade Into a Chassis
The following procedure describes the installation of the SB-ATCA7300 blade. It
assumes that your system is powered on. If your system is not powered on, you
can disregard the blue LED status and skip step 7. In this case, it is purely a
mechanical installation.
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Hardware Preparation and Installation
1. Ensure that the top and bottom ejector handles are in the outward position by
squeezing the lever and the latch together.
Figure 3-2 Loosening the Blade Ejector Handle
2. Insert blade into the shelf by placing the top and bottom edges of the blade in
the card guides of the shelf. Ensure that the guiding module of shelf and blade are
aligned properly.
3. Apply equal and steady pressure to the blade to carefully slide the blade into
the shelf until you feel resistance. Continue to gently push the blade until the
blade connectors engage.
4. Squeeze the lever and the latch together and hook the lower and the upper
handles into the shelf rail recesses.
5. Seat the blade in the shelf and lock it in place by squeezing the lever and the
latch together, for both the upper and lower handles at the same time, and moving
both handles towards the front panel.
Figure 3-3 Ejector Handle When Inserting a Board
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Hardware Preparation and Installation
If your shelf is powered on, as soon as the blade is connected to the backplane
power pins, the blue LED will illuminate.
When the blade is completely seated, the blue LED will start to blink. This usually
indicates that the shelf management controller is activating the blade.
Note - If an RTM is connected to the front blade, make sure that the handles of
both the RTM and the front blade are closed in order to power up the blade’s
payload.
6. Tighten the two front panel screws which secure the blade to the shelf.
7. When the blue LED goes off, this indicates that the blade’s payload has been
powered up and that the blade is active.
8. Connect cables to the front panel, if present.
3.5.2 Removing the Blade from a Chassis
The following procedure describes how to remove the blade from a system. It
assumes that the system is powered on. If the system is not powered on, you can
disregard the blue LED and skip the respective step. In that case, it is purely a
mechanical procedure.
1. Unlatch the lower handle by squeezing the lever and the latch together and
turning the handle outward just enough to unlatch the handle from the front panel.
Do not rotate the handle fully outward.
2. The blue LED will blink, indicating that the blade power-down process has
begun.
Note - If the LED continues to blink, a possible reason may be that the Shelf
Manager has rejected the blade extraction request.
3. Wait until the blue LED is on solidly (no longer blinking), then unlatch the
upper handle and rotate both handles fully outward.
CAUTION - Removing the blade with the blue LED off or still blinking can
cause data loss. Wait until the blue LED is permanently illuminated before
removing the blade from the chassis.
4. Remove the front panel cables if present.
5. Unfasten the screws of the front panel until the blade is unfastened from the
shelf.
6. Remove the blade from the shelf (see Figure 3-2 on page 3-9).
7. Replace the removed blade with another blade or a filler panel to prevent loss
of cooling air pressure.
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Hardware Preparation and Installation
3.6 Installing the SB-ATCA7300 Accessories
The following additional components are available for the blade:
 DIMM memory modules




SFMMOD (persistent memory) module
SSD module
USB 2.0 flash module
Rear transition modules
Except for the RTM, these items are described in detail in the following sections.
For part numbers, refer to section 1.6 “Ordering Information” on page 1-5.
3.6.1 Memory DIMMs
The SB-ATCA7300 provides 12 slots for main memory DIMMs, six per
processor. You can install and remove DIMMs in order to configure the blade’s
memory size to your needs. The DIMM configuration, installation and removal
procedures are described in this section.
The location of the DIMM modules is shown in Figure 3-1 on page 3-5.
CAUTION - Electrostatic discharge and incorrect module installation and
removal can damage circuits or shorten their life. Before touching the module or
electronic components, make sure that you are working in an ESD-safe
environment.
3.6.1.1 DIMM Models
The SB-ATCA7300 supports 12 VLP (Very Low Profile) DDR3 ECC memory
DIMMs. Supported data rates include 800, 1066, and 1333 MT/s. Supported sizes
include 512MB, 1GB, 2GB, 4GB, 8 GB and 16GB.
Only qualified DDR3 DIMMs (Dual Ranked RDIMMs) are supported. This
because of the thermal limit/budget of the blade and the high variation in power
consumptions of different DIMM types. For thermal reasons, 4-rank DIMMs are
not supported.
The SB-ATCA7300 supports Low Voltage LVDDR3 Memory running at 1.35 V
which reduces power consumption and improves thermal performance of the
blade. Either the normal DDR3 (1.5 V) or the LVDDR3 (1.35V) can be used.
CAUTION - Do not mix Low Voltage and regular voltage DIMMs on the same
board. Component damage and/or unpredictable results may occur.
The standard DIMMs provided by SANBlaze are 8 GB (1 Gb x 72), with ECC,
and are rated at 1333 MT/s. Regular voltage (1.5 V) DIMMs are used.
8 GB DIMMs are installed by SANBlaze unless otherwise requested.
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Hardware Preparation and Installation
CAUTION - DIMM modules used within one channel must use the same
memory technology. For maximum memory performance all three channels of
one CPU must be configured with the same number and size of DIMMs.
3.6.1.2 DIMM Installation Order
Memory DIMMs should be installed in a specific order to get the best
performance. Each CPU provides 3 memory access channels, and each channel
supports two DIMMs, for a total of six DIMMs per processor.
It is recommended that DIMMs be installed in pairs, one DIMM for each
processor, but this is not required.
If you are using fewer than six DIMMs per processor, refer to the diagram below
and begin populating the DIMM sockets labeled "first.” After all these positions
are full, proceed to populate sockets labeled "second." This order ensures that the
access channels are balanced for best performance.
Each Processor must have at least one DIMM to function.
Figure 3-4 SB-ATCA7300 DIMM Population Order
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Hardware Preparation and Installation
3.6.1.3 Installing DIMMs
To install a DIMM module, proceed as follows:
1. Remove blade from system as described in section 3.5.2 “Removing the Blade
from a Chassis” on page 3-10.
2. Determine where the DIMMs will be installed, as described in the previous
section.
3. Open the locks of memory module socket.
4. Press the module evenly and carefully into socket. As soon as the memory
module has been fully inserted, the locks will automatically click closed.If
applicable, repeat steps 2-4 to install further modules.
3.6.1.4 Removing DIMMs
To remove a DIMM module, proceed as follows:
1. Remove blade from system as described in section 3.5.2 “Removing the Blade
from a Chassis” on page 3-10.
2. Push open the locks of DIMM socket on both sides together. The memory
module will automatically lift up.
3. Remove the module from its socket.
4. Repeat steps 2 to 3 in order to remove further memory modules.
3.6.2 SSD and SFMMOD Module Installation
The SSD/SFMMOD extension slot supports the installation of either an
SFMMOD (PMEM) or SATA-based SSD module which are available as
accessories for SB-ATCA7300. There is only one connector, so only one of these
modules can be installed on the blade at a time.
Note the fastening screw holes at the center left and lower right corner.
Figure 3-5 SB-ATCA7300 SSD Module
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Hardware Preparation and Installation
The SSD module consists of a 32 or 64 GBSolid State Disk and a SATA
controller. It connects to ICH10R’s SATA Port #5. It’s built using SLC flash, and
its controller uses a wear-leveling algorithm to extend the life of the module.
Figure 3-6 SB-ATCA7300 SFMMOD Module (Installed in a Different Blade Model)
The SFMMOD (SRAM-Flash-Memory Module) consists of an SRAM and a flash
memory. The SRAM has a capacity of up to 16 MB and can be used as persistent
memory, i.e. a memory that holds up the contents during reset. The flash memory
has a capacity of up to 64 MB organized as two memory banks. The SFMMOD
connects to the blade's PCI subsystem. It can be configured via an FPGA register.
The SFMMOD can be used by some operating systems to record debugging and
status information.
The extension module is mechanically fastened to the blade with two screws. The
location of the two corresponding mounting holes as well as the S/F memory
module connector is shown in Figure 3-1 on page 3-5.
Note - The SFMMOD and SSD modules are accessory kits and are not part of the
default SB-ATCA7300 blade configuation.
3.6.2.1 Installing the SATA or SFMMOD Module
To install a SATA or SFMMOD module, proceed as follows:
CAUTION - Electrostatic discharge and incorrect module installation and
removal can damage circuits or shorten their life. Before touching the module or
electronic components, make sure that you are working in an ESD-safe
environment.
1. Remove the blade from the system as described in section 3.5.2 “Removing
the Blade from a Chassis” on page 3-10.
2. Plug the SATA or SFMMOD module into the blade so that the module's
standoffs fit in the blade's mounting holes.
3. Fasten the SATA or SFMMOD module to the blade using the two screws that
previously had fixed the S/F memory module to the blade.
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Hardware Preparation and Installation
4. Reinstall the blade into the system as described in section 3.5.1 “Installing the
Blade Into a Chassis” on page 3-8.
The new resource (either persistent memory or SATA SSD) will be detected
automatically during the boot-up sequence.
3.6.2.2 Removing the SATA or SFMMOD Module
To remove the SATA or SFMMOD module, proceed as follows:
CAUTION - Electrostatic discharge and incorrect module installation and
removal can damage circuits or shorten their life. Before touching the module or
electronic components, make sure that you are working in an ESD-safe
environment.
1. Remove the blade from the system as described in section 3.5.2 “Removing
the Blade from a Chassis” on page 3-10.
2. Remove the two screws holding the SATA or SFMMOD module.
3. Lift the SATA or SFMMOD module from the blade.
4. Reinstall the blade into the system as described in section 3.5.1 “Installing the
Blade Into a Chassis” on page 3-8.
3.6.3 eUSB 2.0 Flash Module
The SB-ATCA7300 provides support for one optional eUSB 2.0 flash module
with a capacity of 8 GB. It can be used for a flash file system or as a boot device.
Its controller includes a wear-leveling algorithm to extend the life of the module.
Figure 3-7 SB-ATCA7300 eUSB Flash Module
The location of the eUSB 2.0 Flash Module is shown in Figure 3-1 on page 3-5.
CAUTION - Electrostatic discharge and incorrect module installation and
removal can damage circuits or shorten their life. Before touching the module or
electronic components, make sure that you are working in an ESD-safe
environment.
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Hardware Preparation and Installation
3.6.3.1 Installing the eUSB Flash Module
To install the eUSB Flash module, proceed as follows:
1. Remove blade from system as described in section 3.5.2 “Removing the Blade
from a Chassis” on page 3-10.
2. Insert the new flash module in socket (see Figure 3-1 on page 3-5). be careful
not to bend the connector pins.
3. Tighten the screw on the left side of the flash module.
4. Reinstall the blade into the system as described in section 3.5.1 “Installing the
Blade Into a Chassis” on page 3-8.
3.6.3.2 Removing the eUSB Flash Module
To remove the eUSB Flash module, proceed as follows:
1. Remove blade from system as described in section 3.5.2 “Removing the Blade
from a Chassis” on page 3-10.
2. Remove the screw on the left side of the flash module (see figure Figure 3-7
above).
3. Lift the flash module from its socket.
4. Reinstall the blade into the system as described in section 3.5.1 “Installing the
Blade Into a Chassis” on page 3-8.
3.6.4 VGA Module
The SB-ATCA7300 provides a VGA module as a standard feature.However, it
may need to be removed for repair, or to access the board battery residing
underneath it.
Figure 3-8 SB-ATCA7300 VGA Module
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Hardware Preparation and Installation
The location of the VGA module is also shown in Figure 3-1 on page 3-5.
CAUTION - Electrostatic discharge and incorrect module installation and
removal can damage circuits or shorten their life. Before touching the module or
electronic components, make sure that you are working in an ESD-safe
environment.
3.6.4.1 Installing the VGA Module
To install the VGA module, proceed as follows:
1. Remove blade from system as described in section 3.5.2 “Removing the Blade
from a Chassis” on page 3-10.
2. Insert the new VGA module in socket (see Figure 3-1 on page 3-5 and
Figure 3-8 on page 3-16). Be careful not to bend any pins on the connector at the
center right.
3. Tighten the screw on the top left side of the VGA module.
4. Reinstall the blade into the system as described in section 3.5.1 “Installing the
Blade Into a Chassis” on page 3-8.
3.6.4.2 Removing the VGA Module
To remove the VGA module, proceed as follows:
1. Remove blade from system as described in section 3.5.2 “Removing the Blade
from a Chassis” on page 3-10.
2. Remove the screw on the top right side of the VGA module (see Figure 3-7
above).
3. Carefully lift the VGA module from its socket.
4. Reinstall the blade into the system as described in section 3.5.1 “Installing the
Blade Into a Chassis” on page 3-8.
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Hardware Preparation and Installation
SB-ATCA7300 Installation and Use Guide
3-18
4 Controls, Indicators, and
Connectors
See section 3.3 “Blade Layout” on page 3-5 for the board layout of the SBATCA7300 blade components.
4.1 Front Panel
The following figure illustrates the connectors and LEDs available at the front
panel.
1
2
3
4
5
6
7
8
9
10
11
12
Figure 4-1 SB-ATCA7300 Front Panel
The labeled components are identified in Table 4-1 below.
Table 4-1 SB-ATCA7300 Front Panel Components
Number
Item
1
Captive screw
2
Out of Service LED
3
Active (power on)
SB-ATCA7300 Installation and Use Guide
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Controls, Indicators, and Connectors
Table 4-1 SB-ATCA7300 Front Panel Components
Number
Item
4
Attention
5
Management Ethernet interface
6
Reset button
7
U1, U2 – Base Ethernet activity
U3 – User-programmable LED
8
Console serial port
9
USB 2.0 ports (2)
10
Hot swap LED
11
VGA video port
12
Captive screw
Front Panel LEDs
The SB-ATCA7300 status LEDs, located vertically in the center of the front panel
(see Figure 4-1 on page 4-1), are explained in Table 4-2 below.
Table 4-2 SB-ATCA7300 Status LEDs
Label
ATN
Color
Amber
(Ethernet activity) Green
State
Use is under OS or application control
Link is available
Yellow
Link is active
H/S
Blue
Hot swap component status
Solid - OK to remove
Blinking – Board is coming up or going down
Off - Board is active
IS
Green
Payload power is present
Can also be set to red or yellow
OOS
Red
Out Of Service; board is not operational
Can also be set to be amber
U1, U2
(Varies) Base network interface activity
(eth0 and eth1, respectively)
U3
(Varies) Use is under OS or application control
Can be red, green or orange
SB-ATCA7300 Installation and Use Guide
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Controls, Indicators, and Connectors
4.1.1 Reset Button
The SB-ATCA7300 provides a reset button on its front panel.
E
T
H
R
E
S
E
T
U1 U2 U3
C
O
M
1
Figure 4-2 Location of Front Panel Reset Button
By pressing the reset button, a hard reset is triggered and all attached on-board
devices are reset. The button is recessed in a small hole, and requires a small
object be used to push it.
Note that you cannot reset the IPMC using this button.
4.1.2 Blade Connectors
The blade provides the following connectors on its front panel.
 One 10/100/1000 Mb Ethernet port



One serial port
Two USB 2.0 ports
One VGA port
4.1.2.1 Ethernet Connector
The blade provides one Ethernet 10/100/1000Base-T interface connector on its
front panel. This is a separate interface from those that connect to the ATCA
backplane.
The pinout of this connector is as follows.
1
2
3
4
5
6
7
8
ETH_TX+
ETH_TXETH_RX+
n.c.
n.c.
ETH_RXn.c.
n.c.
1
8
Figure 4-3 Ethernet Interface Connectors Pinout
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Controls, Indicators, and Connectors
4.1.2.2 Serial Port Connector
The SB-ATCA7300 provides one RS-232 serial interface RJ-45 connector on its
front panel. This port is physical serial interface port 1. (Port 2 goes to the
ARTM.)
Note - By default, the BIOS maps this interface to serial interface COM1. Board
configuration switch SW2-2 allows you to swap the physical ports assigned to
COM1 and COM2, and thus make the COM2 interface accessible from the front
panel connector. (See section 3.4 “Board Control Switch Settings” on page 3-5 for
more information on the switches.)
The BIOS serial redirection feature uses COM1 as its access interface. If you use
switch SW2-2 to swap the serial interface identities, this also swaps the port used
by the serial redirection feature.
The pinout of the serial port connector is shown below.
1
2
3
4
5
6
7
8
n.c.
n.c.
COM1_RS232_TXD
GND
GND
COM1_RS232_RXD
n.c.
n.c.
1
8
Figure 4-4 Serial Port Connector Pinout
4.1.2.3 USB Connectors
The SB-ATCA7300 provides two USB 2.0 connectors on its front panel. They
correspond to USB interfaces 3 and 4.
The pinout of each USB connector is shown in the figure below.
1
2
3
4
VP5_USB
USB_x_DUSB_x_D+
GND
1
4
Figure 4-5 USB Connector Pinout
4.1.2.4 VGA Connector
The blade provides one DB-14 VGA connector on its front panel.
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Controls, Indicators, and Connectors
The DB15 video connector uses the following pinout.
Figure 4-6 DB15 Video Connector
Table 4-3 DB15 Video Connector Pinout
Pin
Signal
Description
1
RED
Red video
2
GREEN
Green video
3
BLUE
Blue video
4
N/C
Not connected
5
GND
Ground (HSync)
6
RED_RTN
Red return
7
GREEN_RTN Green return
8
BLUE_RTN
Blue return
9
+5 V
+5 VDC
10
GND
Ground (VSync, DDC)
11
N/C
Not connected
12
SDA
I²C data
13
HSync
Horizontal sync
14
VSync
Vertical sync
15
SCL
I²C clock
4.2 On-board Connectors
The blade provides the following on-board connectors:
 SFMMOD/SSD module connector

eUSB Flash module connector
4.2.1 SFMMOD/SSD Module Connector
The SFMMOD and SSD module connect to the blade through a connector that
carries the following types of signals. The connector only supports the installation
one module.
 PCI interface signals


I2C signals for connection with the on-board IDROM device
Four configuration pins used for memory configuration
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Controls, Indicators, and Connectors


1 SATA port connection (to ICH10R SATA port #5)
Power supply at 5V and 3.3V
The location of the SFMMOD/SFMMOD module connector is shown in Figure 31 on page 3-5. The pinout of this connector is shown in the following figure.
Figure 4-7 SFMMOD/SSD Module Connector Pinout
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Controls, Indicators, and Connectors
4.2.2 eUSB Flash Module Connector
The location of the flash memory module connector is shown in Figure 3-1 on
page 3-5. You can find the pin assignment of the flash connector in the following
figure.
Figure 4-8 eUSB Flash Module Connector Pin Assignment
4.3 AdvancedTCA Backplane Connectors
The AdvancedTCA backplane connectors reside in the three zones, numbered 1 to
3 as specified by the AdvancedTCA standard. The connectors used by the SBATCA7300 are named P10, P20 and P23, and J30, J32 and J33, respectively. The
pinouts of all of these connectors are given in this section.
J30
J32
J33
P23
P20
P10
Figure 4-9 Location of AdvancedTCA Backplane Connectors
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Controls, Indicators, and Connectors
4.3.1 Zone 1 (P10)
The Zone 1 connector is identified as P10 and carries the following signals:
 Power feed for the blade (VM48_x_CON and RTN_x_CON)





Power enable (ENABLE_x)
IPMB bus signals (IPMB0_x_yyy)
Geographic address signals (HAx)
Ground signals (SHELF_GND and GND)
Reserved signals
Contact Number
Destination
Description
1–4
Reserved
Reserved
5
IPMC ISC PC0
Hardware Address Bit 0
6
IPMC ISC PC1
Hardware Address Bit 1
7
IPMC ISC PC2
Hardware Address Bit 2
8
IPMC ISC PC3
Hardware Address Bit 3
9
IPMC ISC PD4
Hardware Address Bit 4
10
IPMC ISC PD5
Hardware Address Bit 5
11
IPMC ISC PD6
Hardware Address Bit 6
12
IPMC ISC PD7
Hardware Address Bit 7
13
IPMC IMC PD0
IPMB Clock Port A
14
IPMC IMC PD1
IPMB Data Port A
15
IPMC ISC PC5
IPMB Clock Port B
16
IPMC ISC PC4
IPMB Data Port A
17 – 24
Not used
Not used
25
Shelf Ground
Shelf Ground
26
Logic Ground
Logic Ground
27
Power Building Block
Enable B
28
Power Building Block
Voltage Return A
29
Power Building Block
Voltage Return B
30
Power Building Block
Early -48V A
31
Power Building Block
Early -48V B
32
Power Building Block
Enable A
33
Power Building Block
-48V A
34
Power Building Block
-48V A
Figure 4-10 SB-ATCA7300 Zone 1 Backplane Connector Pinout
4.3.2 Zone 2 (P20 and P23)
Zone 2 contains the two connectors, P20 and P23. They carry the following types
of signals:
 Telecom clock signals (CLKx_)


Base interface signals (B_)
Fabric interface signals (F_)
SB-ATCA7300 Installation and Use Guide
4-8
Controls, Indicators, and Connectors

Blade update channel (Sa_)
Some of the pins provided by P20 and P23 are defined as optional in the
AdvancedTCA specification and are unused by the blade. If the AdvancedTCA
specification defines these signals as input signals, they are terminated on the
blade and marked as "TERM_" in the following pinouts. In all other cases, the
pins are unconnected and marked as NC.
The pinouts of P20 and P23 are as follows.
P20
Row #
Interface
1
CLKs
Col AB
2
3
Update Channel
4
Col CD
Col EF
CLK1A+
CLK1A-
CLK1B+
CLK1B-
RES_RX4+
RES_RX4-
RES_TX4+
RES_TX4-
SA_RX2+
SA_RX2-
SA_TX2+
SA_TX2-
SA_RX0+
SA_RX0-
SA_TX0+
SA_TX0-
CLK2A+
Col GH
CLK2A-
SA_RX3+
CLK2B+
SA_RX3-
SA_RX1+
SA_RX1-
CLK2B-
SA_TX3+
SA_TX3-
SA_TX1+
SA_TX1-
NC
NC
Term
Term
NC
NC
Term
Term
6
NC
NC
Term
Term
NC
NC
Term
Term
7
NC
NC
Term
Term
NC
NC
Term
Term
8
NC
NC
Term
Term
NC
NC
Term
Term
9
NC
NC
Term
Term
NC
NC
Term
Term
NC
NC
Term
Term
NC
NC
Term
Term
5
Fabric Channel 15
Fabric Channel 14
Fabric Channel 13
10
Figure 4-11 Zone 2 P20 Backplane Connector Pinout
P23
Row #
Interface
Col AB
Col CD
Col EF
Col GH
F2[2]_TX+
F2[2]_TX-
F2[2]_RX+
F2[2]_RX-
F2[3]_TX+
F2[3]_TX-
F2[3]_RX+
F2[3]_RX-
2
F2[0]_TX+
F2[0]_TX-
F2[0]_RX+
F2[0]_RX-
F2[1]_TX+
F2[1]_TX-
F2[1]_RX+
F2[1]_RX-
3
F1[2]_TX+
F1[2]_TX-
F1[2]_RX+
F1[2]_RX-
F1[3]_TX+
F1[3]_TX-
F1[3]_RX+
F1[3]_RX-
F1[0]_TX+
F1[0]_TX-
F1[0]_RX+
F1[0]_RX-
F1[1]_TX+
F1[1]_TX-
F1[1]_RX+
F1[1]_RX-
1
Fabric Channel 2
Fabric Channel 1
4
5
Base Channel 1
BI1_DA+
BI1_DA-
BI1_DB+
BI1_DB-
BI1_DC+
BI1_DC-
BI1_DD+
BI1_DD-
6
Base Channel 2
BI2_DA+
BI2_DA-
BI2_DB+
BI2_DB-
BI2_DC+
BI2_DC-
BI2_DD+
BI2_DD-
7
n/a
NC
NC
NC
NC
NC
NC
NC
NC
8
n/a
NC
NC
NC
NC
NC
NC
NC
NC
9
n/a
NC
NC
NC
NC
NC
NC
NC
NC
10
n/a
NC
NC
NC
NC
NC
NC
NC
NC
Figure 4-12 Zone 2 P23 Backplane Connector Pinout
4.3.3 Zone 3 (J30, J32 and J33)
Zone 3 contains the three connectors J30,J32 and J33. They are used to connect an
ARTM to the blade and carry the following signals:
 Serial (RS232_x_yyyy)



Serial ATA (SATAx_yyy)
USB (USBxy)
PCI Express (PCIEx_yyy)
SB-ATCA7300 Installation and Use Guide
4-9
Controls, Indicators, and Connectors




IPMI (IPMB1_xxx, ISMB_xxx)
Power (VP12_RTM, V3P3_RTM, VP5_RTM)
Update channel
General control signals (BD_PRESENTx, RTM_PRSNT_N,
RTM_RST_KEY-, RTM_RST-)
The pinouts for these connectors are as follows.
Row# Interface 1
2
Pin Length
e
Pwr
PS1#
NC
short
d
Pwr
+12V PP
+12V PP
long
c
IPMI
IPMI_SCL_L
IPMI_SDA_L
medium
b
Pwr
Logic_GND
+3.3V MP
long
a
Pwr
Logic_GND
Shelf_GND
long
Figure 4-13 Zone 3 J30 Backplane Connector Pinout
Row#
1
Interface
2
RS232/SAS
SA_TX0+
3
RS232/SAS
SA_TX1+
4
RS232/SAS
5
6
7
8
9
10
A
B
C
NC
NC
RES_TX4+
D
RES_TX4-
E
SA_TX0-
SA_RX0+
SA_RX0-
SR0_RTS
SR0_DTR
SA_TX1-
SA_RX1+
SA_RX1-
SR0_TXD
SR0_RXD
SA_TX2+
SA_TX2-
SA_RX2+
SA_RX2-
SR0_DSR
SR0_CTS
SA_TX3+
SA_TX3-
SA_RX3+
SA_RX3-
NC
LAN0_BLAN0_D-
RES_RX4+
F
RES_RX4-
LAN
(MNGT)
LAN0_A+
LAN0_C+
LAN0_ALAN0_C-
LAN0_CTV
ACT_LED#
LAN0_CTV
LINK_LED#
NC
LAN0_B+
LAN0_D+
LAN1
(SerDes)
SLAN_TX1+
SLAN_TX1-
SLAN_RX1+
SLAN_RX1-
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Figure 4-14 Zone 3 J32 Backplane Connector Pinout
SB-ATCA7300 Installation and Use Guide
4-10
Controls, Indicators, and Connectors
Row#
Interface A
B
C
D
E
F
1
PCIe
PETx0+
PETx0-
PERx0+
PERx0-
FCLKA+
FCLKA-
2
PCIe
PETx1+
PETx1-
PERx1+
PERx1-
3
PCIe
PETx2+
PETx2-
PERx2+
PERx2-
4
PCIe
PETx3+
PETx3-
PERx3+
PERx3-
5
PCIe
PETx4+
PETx4-
PERx4+
PERx4-
6
PCIe
PETx5+
PETx5-
PERx5+
PERx5-
7
PCIe
PETx6+
PETx6-
PERx6+
PERx6-
8
PCIe
PETx7+
PETx7-
PERx7+
PERx7-
9
Misc
USB0+
USB0-
NC
NC
10
Misc.
USB1+
USB1-
FCLKB+
FCLKB+
PCI_RST#
PS0#
Enable#
Figure 4-15 Zone 3 J33 Backplane Connector Pinout
SB-ATCA7300 Installation and Use Guide
4-11
Controls, Indicators, and Connectors
SB-ATCA7300 Installation and Use Guide
4-12
5 BIOS Configuration
5.1 Overview
The BIOS (Basic Input Output System) provides an interface between the
operating system and the hardware of the blade. It is used for hardware
configuration. Before loading the operating system, the BIOS identifies and
configures the installed hardware components, performs basic hardware tests, and
prepares the blade for the initial boot-up procedure. The SB-ATCA7300 BIOS is
based on American Megatrends (AMI) Aptio UEFI (Unified Extensible Firmware
Interface) BIOS. This BIOS supports the SMBIOS 2.4 and ACPI 3.0
Specifications.
5.2 Hardware Architecture
Figure 5-1 SB-ATCA7300 Black Diagram
SB-ATCA7300 Installation and Use Guide
5-1
BIOS Configuration
5.2.1 Processor
SB-ATCA7300 supports dual Intel six core L5638 (Xeon, Westmere-EP)
processor with two QuickPath interconnect links of 5.866GT/s (which
corresponds to a 1333 MHz front side bus). For more detail, see section 2.2
“Processor” on page 2-2.
5.2.2 Processor Support Chip Set
The SB-ATCA7300 provides a North Bridge Intel 5520 chipset (Tylersburg
IOH36D). This provides two QPI interfaces for connecting to two Intel processors
and 36 PCI-E Gen2 lanes. It also supports Intel Virtualization Technology,
Enterprise Southbridge Interface (ESI) and Management Engine.
The ICH10R I/O controller connects to the Intel 5520 through a four lane (x4)
Enterprise Southbridge Interface (ESI). This controller provides I/O support and
the boot path to the redundant BIOS boot flash devices. The controller I/O
interfaces used include SATA, USB2.0, LAN, LPC, and RTC. For more
information see section 2.6 “Intel ICH10R I/O Controller” on page 2-4.
5.2.3 Memory
Each CPU provides a three-channel DDR3 memory controller with two DIMM
slots per channel, for a total of six DIMM slots per processor. The DDR3 interface
(supporting DDR3-800, DDR3-1066 and DDR3-1333 data rates) supports
512MB, 1GB, 2GB, 4GB, 8GB and 16GB memory DIMMs. See section 2.4
“Integrated Memory Controller” on page 2-4 for more information.
5.3 BIOS Considerations
5.3.1 BIOS Update and Recovery
There are three different ways to update the BIOS in SB-ATCA7300:
 Flash tool (FCU and ipmitool in Linux)


USB CD ROM or eUSB Flash device (USB recovery mode)
Serial recovery (emergency recovery mode using the front panel serial
port with Xmodem)
A flash tool is used for normal update modes. The USB CD ROM/flash device
and serial port recovery are used in BIOS recovery modes. The BIOS will be
recoverable after a failed update without any special hardware even when only the
bootblock remains usable on a flash device.
5.3.2 DRAM Support
The BIOS supports the following features of the memory controller:
 Independent Channel Mode
SB-ATCA7300 Installation and Use Guide
5-2
BIOS Configuration



Mirroring Channel Mode
Spare Channel Mode
Lockstep Channel Mode
BIOS uses the independent channel mode as the default for memory initialization.
Asymmetrical DIMM populations are supported, as long as the DIMMs are the
same voltage. Patrol scrubbing of main memory can be enabled through the BIOS
Setup menu.
5.3.2.1 Autosizing
DRAM autosizing is supported. The BIOS reads the Serial Presence Detect (SPD)
data from the memory modules and automatically configures the chipset
accordingly.
5.3.2.2 Memory Test
The BIOS executes simple memory tests during POST. The memory test mode
can be selected through the BIOS Setup item.
5.3.2.3 ECC Support
By default, the BIOS enables ECC support in the chipset, but an option is
provided to enable or disable ECC on the BIOS Setup menu.
5.3.3 Interrupt Routing
The BIOS provides the interrupt routing to OS through the following interfaces:
 ACPI_PRT packages (ACPI environment)



ACPI Multiple APIC Description Table (ACPI environment)
PCI IRQ Routing Table (non-ACPI environment)
Multi Processor Table (non-ACPI environment)
5.3.4 PCI Initialization
The BIOS supports the following PCI initialization specifications:
 PCI BIOS Specification, Revision 2.1
During POST, the BIOS identifies all PCI-to-PCI bridges and all PCI devices with
a header type 1 in the system, then initializes them according to their resource
requirements.
SB-ATCA7300 Installation and Use Guide
5-3
BIOS Configuration
5.3.5 I/O Device Configuration
5.3.5.1 Serial Ports
The routing of the output of the FPGA serial ports to the front panel connectors is
set by IPMI and onboard switches (see section 3.4 “Board Control Switch
Settings” on page 3-5). There is no BIOS setup item for this routing.
The routing of the IPMI debug output to the front panel connector can only be
enabled via IPMI; there is no BIOS setup items for this routing. IPMI debug
output is not routed to front panel connector by default.
5.3.5.2 Integrated SATA Controller
The BIOS provides the setup items to configure the ICH10R I/O controller
embedded Serial ATA controller for debugging purposes. Hard disk autotyping is
supported. The BIOS automatically determines the proper geometry for hard disks
by reading information from the drive.
5.3.6 Boot Options
The SB-ATCA7300 BIOS supports BIOS Boot Specification version 1.01. The
BIOS will identify all IPL (Initial Program Load) BAID (BIOS Aware IPL
Device) and BEV (Boot Entry Vector) devices as well as all BCV (Boot
Connection Vector) devices (such as hard drives and USB devices) in the system
and attempt to boot them in the order specified in Setup.
The following boot devices are supported in the BIOS:
 USB devices (sticks, onboard embedded USB Flash disk, hard drives,
CD-ROM)




SAS controller on ARTM
Fibre Channel Controller on ARTM
Network (BEV)
Onboard Embedded SSD
The default boot order is:
 Attached USB CDROM




Attached USB devices of any USB external port
SAS HDD connected to ARTM SAS Controller
Base Ethernet Interface
EFI shell
If the BIOS does not find any ready bootable device, it will report an error on the
IPMI channel and loop infinitely on the source list until a boot device becomes
ready or the IPMC watchdog timer triggers.
SB-ATCA7300 Installation and Use Guide
5-4
BIOS Configuration
5.3.6.1 Boot Support for the SAS Controller on the ARTM
ARTM products with an integrated LSI SAS controller also contain an option
ROM to support disk boot. The option ROM facilitates legacy boot, allowing the
host to see and boot an OS from a disk connected to the SAS topology. UEFI boot
is not supported.
5.3.6.2 Boot Support for Fibre Channel on the ARTM
ARTM products with an integrated LSI Fibre Channel controller also contain an
option ROM to support disk boot. The option ROM facilitates legacy boot,
allowing the host to see and boot an OS from a disk connected to the FC topology.
UEFI boot is not supported.
5.3.6.3 Network Boot Support
The BIOS uses standard PXE Option PROMs to support booting from the
network.
The following table summarizes network boot support status:
Table 5-1 Ethernet Interfaces Supported for Network Boot
Ethernet Interface
PXE Boot
Support
Front Panel Network Interface 1 (82567EB - 1)
YES
Base Network Interface 1 (I350-AM4 - 1)
YES
Base Network Interface 2 (I350-AM4 - 2)
YES
Fabric Network Interface 1 (82599EB - 1)
YES
Fabric Network Interface 2 (82599EB - 2)
YES
I350-AM4 (Quad GbE), two interfaces (3, 4) to ARTM
YES
5.3.7 Redirection of Serial I/O to COM Ports (Console Redirection)
Redirection of serial I/O to a COM port makes it possible to configure the BIOS
using the Setup menu in the absence of a VGA adapter.
This allows the user to select either of the onboard serial ports or to disable the
console redirection. Possible settings: Enabled or Disabled.
The default value is Enabled. If Disabled is selected, no redirection of I/O to a
COM port will be performed. COM1 is fully compliant with industry standard
16550 asynchronous communication controllers (UARTs) and are implemented in
the Glue Logic FPGA. If COM1 is selected as console redirection, COM0 must be
set to "Disabled" due to console redirection limitations.
The following options are configurable via BIOS setup:
SB-ATCA7300 Installation and Use Guide
5-5
BIOS Configuration

Baud rates supported



9600 baud, 19200 baud, and 115200 baud
The default is 9600 baud
COM0 port
See section 5.5.2.8 “Serial Port Console Redirection” on page 5-22 for more
information.
5.3.7.1 SOL (Serial Over LAN)
The BIOS writes to an FPGA register the COM port number through which the
console redirection is done:
 0=Serial Redirection

1=COM0
The rest of the SOL initialization is done by the blade IPMC. See Chapter 7
"Serial Over LAN" for more information.
5.3.8 IPMI Support
The SB-ATCA7300 BIOS provides the following IPMI support based on the
IPMI version 1.5 specification:
 Check whether the board IPM Controller is active, and display an
appropriate error message if not.

Read the SelfTest result from the IPM Controller, and display an error
message if the SelfTest failed.






Set the initial timestamp.
Read the IPMC firmware version and display it in BIOS Setup menu.
Send System Firmware Progress status to the IPMC.
Log Boot Errors to the IPMC event log (SEL).
Send an OS boot event to the IPMC.
Read IPMC GUID and fill the DMI structure Type 1 UUID field.
Only the KCS interface is supported. The IPMI base address and interrupt is
provided to OS via SMBIOS structure type38.
5.3.8.1 Watchdog Timers
The watchdog timers in SB-ATCA7300 are implemented by the IPMC watchdog
facility. The BIOS uses the IPMC watchdog timer during two phases.
 BIOS boot

OS boot
The IPMC watchdog for BIOS boot is started by IPMC automatically after board
is powered on. You can disable the IPMC’s watchdog timer for BIOS boot in the
SB-ATCA7300 Installation and Use Guide
5-6
BIOS Configuration
BIOS Setup menu. If the BIOS boot timer is enabled, it will be temporarily
disabled when the BIOS Setup menu is running, or on a boot to the EFI shell or
the blade OS. The timer setting for BIOS boot is configurable through the BIOS
Setup menu. The default timer setting is three minutes. The IPMC watchdog for
BIOS boot is enabled by default.
If the IPMC watchdog times out during BIOS boot, the IPMC will switch BIOS
banks and boot from the other image.
The BIOS can disable the IPMC watchdog for OS boots through the BIOS Setup
menu. The timer setting for OS boot is configurable through BIOS setup. The
default timer setting is five minutes. The IPMC watchdog for OS boot is disabled
by default.
See section 5.5.3.1 “IPMI Watchdog Configuration” on page 5-26 for watchdog
timer configuration information.
5.3.9 SMBIOS Support
The BIOS includes SMBIOS structures follwoing the SMBIOS 2.4 and IPMI1.5
specifications. The IPMI IRQ number is not defined in SMBIOS 2.4; it is defined
in IPMI 1.5 specification.
5.3.10 Configuring Boot Parameters Using IPMC
You can set the OS boot device and some OS boot parameters through the
IPMC.BIOS The following can be set:
 boot_order



serial port baud rate
console_port
os_boot_watchdog status
5.3.11 LED Behavior During POST
After power up/reset and while BIOS is running, LEDs are used to determine the
current power up or BIOS stage. The state of LEDs is defined so that in case of a
system hang, the LEDs will clearly indicate the boot up phase on which the hang
occurred.
To indicate that POST is in progress, the BIOS switches the state of the user LED
for different POST task that is executing. After POST has completed, the BIOS
switches off the LEDs. The LEDs labeled B1/U1, B2/U2 and U3 are used for this
purpose.
5.3.12 ARTM SAS Controller
The BIOS extension firmware supports both RAID 0 and RAID 1.
SB-ATCA7300 Installation and Use Guide
5-7
BIOS Configuration
5.3.13 CPU and Chipset Firmware
The BIOS programs for SB-ATCA7300 use CPUs with the latest CPU microcode.
The CPU-related code will be updated to be compliant with the latest related Intel
BIOS specifications and Intel reference source code.
5.3.14 Legacy Free Support
The SB-ATCA7300 BIOS meets the Legacy Free BIOS requirements. The
Legacy Free status and support level reports to the OS over ACPI interface. A
USB keyboard is fully functional in BIOS Setup, in DOS, during OS installation,
OS recovery and in the OS preboot environment, as a standard 8042 Keyboard
Controller is not available to the blade.
5.3.15 BIOS Setup Layout
The BIOS Setup defaults are aligned with the SB-ATCA7300 BIOS defaults.
5.3.15.1 Board Information Display
The BIOS displays the following board related information in BIOS Setup under
Board Info.
 Current System (label for the loaded BIOS defaults set)








BIOS Version
BIOS Date
IPMI Firmware Version
FPGA Version (Onboard FPGA version)
BIOS Source (boot flash device bank used)
CPU information
CPLD information
Board Serial Number stored in the IPMC FRU data
5.3.16 USB Ports
The five USB ports can be enabled or disabled in the BIOS Setup menu.
Table 5-2 SB-ATCA7300 USB Ports
USB Port BIOS Setting Format/Options Default Value
Onboard eUSB Flash disk
Enabled/Disabled
Enabled
Front Panel USBports
Enabled/Disabled
Enabled
ARTM USB ports
Enabled/Disabled
Enabled
SB-ATCA7300 Installation and Use Guide
5-8
BIOS Configuration
Note - The maximum current for every USB port is 800 mA to 1 A. Peripheral
USB devices (such as DVD-ROM) should not exceed this limit.
5.3.17 Supported Operating Systems
Contact your SANBlaze sales person for information about other OSes and OS
versions tested since this prinitng.
 Wind River PNE LE 4.x Linux





Red Hat Enterprise Linux 5.x


VMware ESXi 5.0
Windows 2008 x64 R2
Windows 2003 x64 R2
VMware ESXi 4.1
VMware ESXi 4.1 Update 1
DOS is used for debugging.
Note - When installing Red Hat Enterprise Linux 5.x using the DVD Installer
media, the installation interface and instructions will be displayed on the display
device that is connected to the VGA port, not on the serial terminal.
5.3.18 SRAM Flash Memory Module (SFMMOD)
The SANBlaze SFMMOD persistent memory module can be installed in the SBATCA7300. If installed, the BIOS automatically initializes the PCI bridge on the
SFMMOD during the normal BIOS PCI initialization phase. There are no BIOS
Setup items related to the SFMMOD.
5.3.19 CPU Specific Initialization
The BIOS provides support for setting the processors into Turbo mode and
returning them to normal state. After power-up, the Turbo mode of the processors
will be turned off by default. Enabling and disabling CPU Turbo mode is
implemented in BIOS Setup.
P states are supported in ACPI.
A single processor can be initialized if the other has failed.
5.3.20 Intel 5520-Specific Initializations
5.3.20.1 Intel 5520 QPI Link Speed Configuration
At reset, the Intel QPI links initializes in slow mode (66 MT/s). The BIOS will
determine the proper speed at which to run the Intel QPI links in full speed mode
(5.866GT/s), and then program the transmitter equalization parameters, clear
GP56, and issue a reset to bring the Intel QPI links to full speed.
SB-ATCA7300 Installation and Use Guide
5-9
BIOS Configuration
5.3.20.2 PCI Express Port Configuration
The width of all PCIe links is programmed through the PCIE_PRTx_BIF_CTRL
register instead of by GPIO by using PEWIDTH[5:0] to strap the PCI Express
Port width configuration. The value for PEWIDTH[5:0] is 11111b (Wait-OnBIOS).
5.3.20.3 SPI Boot Flash
The SPI boot flash contains a descriptor mode image with all the parameters
described in Intel® ICH Family SPI Flash Programming Guide Revision 2.4.
5.3.21 Virtualization Support
Intel Virtualization Technology (Intel VT) is the technology that makes a single
system appear as multiple independent systems to software. This allows for
multiple independent operating systems to be running simultaneously on a single
system. See section 2.2.2 “Intel L5638 Processor Features” on page 2-3, section
5.5.2.1 “CPU Configuration” on page 5-17, and section 5.5.2.3.1 “Intel® VT for
Directed I/O Configuration” on page 5-20 for more information.
The SB-ATCA7300 supports the Intel VT-c, VT-d and VT-x technologies.
5.3.22 BIOS CLI tool - ipmibpar
The Linux ipmibpar tool can be used to configure the IPMI Boot Parameter list
when blade is running. It supports the following options:
Table 5-3 IPMI Boot Parameter List
Option
Description
-a xx
IPMB Address; if not present local IPMC is used
-d
Enable debug output
-g
Read the IPMI Boot Parameter USER area
-h
Help
-i
Get device ID
-s file Store IPMI Boot Parameter (USER area), read from file
5.3.23 Dual BIOS Flash Devices
SB-ATCA7300 has two copies of the BIOS image, residing on two separate SPI
flash devices. Each copy of BIOS consists of the bootblock and main BIOS parts.
In addition, the flash devices may contain vendor specific data and setup data.
You can set either flash device A or flash device B as the active BIOS device; the
other becomes the backup. The flash device used is controlled by the IPMC.
SB-ATCA7300 Installation and Use Guide
5-10
BIOS Configuration
The BIOS bootblock verifies the main BIOS image’s integrity by a checksum
calculation. If the active BIOS image is corrupted, the BIOS bootblock will make
a switchover to the backup BIOS image.
A switchover will also occur if the bootblock code is missing or corrupted. This
BIOS independent switch is triggered by IPMC watchdog logic (see section
5.3.8.1 “Watchdog Timers” on page 5-6). Switching to the backup BIOS device is
reported to the console and logged to SMBIOS log. The switchover is performed
by setting the backup flash device active.
5.4 BIOS Initialization
The BIOS executes in multiple phases, in the following order.
Table 5-4 BIOS Execution Phases
Component
Phase
Function
SEC
Security
Early CPU initialization, run from CPU cache
PEI
Pre-EFI Initialization
Full CPU, memory, and board initialization,
determines boot type (cold, S3, S4)
DXE
Driver Execution Environment
Locates and runs firmware driver code that
initializes the rest of the system hardware
BDS
Boot Device Select
Determines the proper boot device
TSL
Transient System Load
Loads and calls the initial OS boot loader
RT
Run Time
OS execution
The first three phases together are often referred to as platform initialization or
POST (Power On Self-Test).
Status and error codes for the BIOS are given in Appendix B, "BIOS Status
Codes".
5.4.1 Power On Self-Test (POST)
After power-up or reset, the BIOS performs a Power On Self-Test (POST) which
attempts to determine if continued operation is possible and if the detected
hardware configuration is supportable and at least minimally complete.
This process can complete normally or result in a warning or error. The BIOS
boot process does not stop when a warning occurs, but displays a message on the
primary display device. If an error is detected, the boot process is stopped.
Failures early in POST can be indicated by POST codes (see Appendix B, "BIOS
Status Codes".)
Viewing the status codes as they are generated by the Aptio BIOS firmware
requires access to the status LEDs near the battery/VGA module during boot. (See
SB-ATCA7300 Installation and Use Guide
5-11
BIOS Configuration
Figure A-2 on page A-2.) The LED display is located to the lower right of the
battery/VGA module.
5.4.2 BIOS Boot Process
While performing the functions of the traditional BIOS, the Aptio 4.x BIOS core
follows the firmware model described by the Intel Platform Innovation
Framework for EFI ("the Framework"). The Framework refers to the following
boot phases, which may apply to various status code descriptions:
 Security (SEC) - initial low-level initialization



Pre-EFI Initialization (PEI) - memory initialization1
Driver Execution Environment (DXE) - main hardware initialization
Boot Device Selection (BDS) - system setup, pre-OS user interface and
selecting a bootable device (CD/DVD, HDD, USB, Network, EFI Shell)
During boot process, information message including BIOS version and build date,
board information, BOOT devices, CPU and memory information will be
displayed. The following is an example for SB-ATCA7300:
SANBlaze ATCA7300 BIOS Version 1.0.4 build 0009 (09/09/2011 - 16:36:35)
Board-Info:
FPGA version: 01
CPLD version: 2
Reset Cause: CPU
BIOS Boot Mode: Normal
Boot Flash Selection: Bank A (IPMI)
Last Boot Flash Selection: Bank A
Flash Bank A: WP off
Flash Bank B: WP off
System Time: 09/10/2011 - 11:28:07
IPMC Version: 2.2.0005
ATCA Power Level 2: 259.6 Watt - No Power Limit
Current System: Standard
Available BOOT Devices:
Base Network 1
Base Network 2
Fabric Network 1
Fabric Network 2
FrontPanel Network
UEFI: Built-in EFI Shell
BOOT Order:
SANBlaze ATCA7300 BIOS Version 1.0.4 build 0009 (09/09/2011 - 16:36:35)
Board: SB-ATCA7300 Version: 01 S/N:
CPU 0: Intel(R) Xeon(R) CPU L5638 @ 2.00GHz, Version: 206C2, MCVer: 13
CPU 1: Intel(R) Xeon(R) CPU L5638 @ 2.00GHz, Version: 206C2, MCVer: 13
SB-ATCA7300 Installation and Use Guide
5-12
BIOS Configuration
Memory
CPU 0
P01:
P02:
P03:
P04:
P05:
P06:
CPU 1
P11:
P12:
P13:
P14:
P15:
P16:
Info: Total Memory 98304 MB
Channel
Channel
Channel
Channel
Channel
Channel
0
0
1
1
2
2
Socket
Socket
Socket
Socket
Socket
Socket
0:
1:
0:
1:
0:
1:
8192
8192
8192
8192
8192
8192
MB
MB
MB
MB
MB
MB
(DDR3
(DDR3
(DDR3
(DDR3
(DDR3
(DDR3
@
@
@
@
@
@
1333MHz)
1333MHz)
1333MHz)
1333MHz)
1333MHz)
1333MHz)
Channel
Channel
Channel
Channel
Channel
Channel
0
0
1
1
2
2
Socket
Socket
Socket
Socket
Socket
Socket
0:
1:
0:
1:
0:
1:
8192
8192
8192
8192
8192
8192
MB
MB
MB
MB
MB
MB
(DDR3
(DDR3
(DDR3
(DDR3
(DDR3
(DDR3
@
@
@
@
@
@
1333MHz)
1333MHz)
1333MHz)
1333MHz)
1333MHz)
1333MHz)
Version 1.29.1121. Copyright (C) 2009 American Megatrends, Inc.
Press <DEL> or <F2> to enter setup.
5.4.3 Initiating Setup
During BIOS initialization, pressing the F2 or Del key requests that the Setup
utility to be launched when POST completes, before searching for a boot device
(the BDS stage; see section 5.4.2 “BIOS Boot Process” on page 5-12).
If you exit Setup without saving any changes, the boot process continues with the
search for a boot device. If changes are made, the BIOS saves the new settings and
then resets, restarting the BIOS boot process from the beginning.
5.5 BIOS Setup
The BIOS incorporates a Setup capability that allows you to change a variety of
system options. This section describes the operation of Setup by describing the
various options available through its set of hierarchical menus.
The current settings are stored in the SPI Flash NVRAM area and any changes are
saved back to this area by the Exit menu. The operation of the BIOS defaults is
described later in this document.
To start Setup, you must press the F2 or Del key during the early stages of POST
after power-up. Note that this functionality operates with USB keyboards when
enabled, and with the console redirection facility when enabled.
SB-ATCA7300 Installation and Use Guide
5-13
BIOS Configuration
The table below briefly describes the primary menus, most of which have
submenus. The following sections describe the menus in detail.
Table 5-5 Primary Menus
Menu
Options
Main
BIOS information, memory information and date and time
Advanced
CPU, Memory, Chipset-North Bridge, Chipset-South Bridge, SATA,
USB, Super IO, Serial Port Console Redirection Options, Runtime
Error Logging, SMBIOS Event Log, Local IPMI System Event Log
and WHEA.
IPMI
IPMI information, SEL and FRU options.
Boot
Option ROM Execution, boot mode and boot options.
Security
Save & Exit
Administrator and User password options.
Save with or without changes, load/save default settings and boot
device override options.
Aptio BIOS navigation can be accomplished using a combination of keys. These
keys include the Function keys, Enter, Esc, Arrow keys, and so on.
Table 5-6 Aptio BIOS Navigation Keys
Key
Enter
Description
The Enter key allows the user to select an option to edit its value or
access a sub menu.
>< Left/Right The Left and Right arrow keys allow you to select a screen.
^v Up/Down
The Up and Down arrow keys allow you to select an item or sub-screen.
+- Plus/Minus
The Plus and Minus keys allow you to change the field value of a
particular setup item.
For example: Date and Time.
Tab
The Tab key allows you to select fields.
Esc
The Esc key allows you to discard any changes you have made and exit
the Aptio Setup. When you are in a submenu, the Esc key allows you to
exit to the upper menu.
Function keys
When other function keys become available, they are displayed at the
right of the screen along with their intended function.
F1
General Help
F2
Load Previous Values.
F3
Load Optimized Defaults.
F4
Save ESC & Exit
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5-14
BIOS Configuration
5.5.1 BIOS Main Menu
Figure 5-2 BIOS Main Menu
Table 5-7 BIOS Main Menu
Field
Description
BIOS Name
SANBlaze board name SB-ATCA7300
BIOS Version
BIOS version
Build Date
BIOS build date
Current System Hardware variant of the board
FPGA Version
Version of the FPGA image currently installed
Boot Flash
Selection
Which boot flash image was used for this boot 1 (primary) or 2
(backup)
Total Memory
Total memory installed
System Date
Sets the time and date (month/day/year format).
To change these values, go to each field and enter the desired value.
Press the Tab key to move from hour to minute to second, or from
month to day to year. There is no default value.
System Time
Access Level
If password protection was configured for the BIOS, the security
level of the supplied password (Administrator or User)
SB-ATCA7300 Installation and Use Guide
5-15
BIOS Configuration
5.5.2 BIOS Advanced Menu
Figure 5-3 BIOS Advanced Menu
Table 5-8 Advanced Menu
Field
Description
CPU Configuration
CPU Configuration Parameters. See section 5.5.2.1 “CPU
Configuration” on page 5-17.
Memory Configuration
Memory setup. See section 5.5.2.2 “Memory Configuration” on
page 5-18.
Chipset - North Bridge
North Bridge Parameters. See section 5.5.2.3 “Chipset - North
Bridge” on page 5-19.
Chipset - South Bridge
South Bridge Parameters. See section 5.5.2.4 “Chipset - South
Bridge” on page 5-20.
SATA Configuration
SATA Devices Configuration Parameters. See section 5.5.2.5
“SATA Configuration” on page 5-20.
USB Configuration
USB Configuration Parameters. See section 5.5.2.6 “USB
Configuration” on page 5-21.
Super IO Configuration Super IO facility parameters. See section 5.5.2.7 “Super IO
Configuration” on page 5-21.
Serial Port Console
Redirection
Serial Port Console Redirection Configuration Parameters. See
section 5.5.2.8 “Serial Port Console Redirection” on page 5-22.
Runtime Error Logging Runtime Error Logging Support Setup Options. See section
5.5.2.9 “Runtime Error Logging” on page 5-24.
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5-16
BIOS Configuration
Table 5-8 Advanced Menu (Continued)
Field
Description
SMBIOS Event Log
View or Change the SMBIOS Event Log Configuration. See
section 5.5.2.10 “SMBIOS Event Log” on page 5-24.
Local IPMI System
Event Log
View the Local IPMI System Event Log. See section 5.5.2.11
“Local IPMI System Event Log” on page 5-24.
5.5.2.1 CPU Configuration
Table 5-9 CPU Configuration
Field
Description
Socket 0/1 CPU Information
Show the processor module and stepping and microcode
revision
Max Processor Speed
Maximum processor speed possible
Min Processor Speed
Minimum processor speed possible
Processor Speed
Current processor speed
Processor Cores
Current count of enabled processor cores
Intel HT Technology
Intel HT Technology availability status
EMT64
EMT64 availability status
Hyper-threading
Enable for Windows XP (and later) and Linux (OS is
optimized for Hyper-Threading Technology) and disable for
other OS (OS is not optimized for Hyper-Threading
Technology). When Disabled only one thread per enabled core
is enabled. Default is "Disabled".
Active Processor Core
Number of cores to enable in each processor. Options: ALL, 1,
2, 3, 4, 5. Default is ALL.
Limit CPUID Maximum
Limit CPUID Maximum. Options: Disabled and Enabled.
Disabled for Windows XP. Default is "Disabled".
Hardware Prefetcher
To enable/disable the MLC streamer prefetcher. Options:
Disabled and Enabled. Default is "Enabled".
Adjacent Cache Line Prefetch
To enable/disable prefetching of adjacent cache lines. Options:
Disabled and Enabled. Default is "Enabled".
Intel Virtualization Technology When enabled, a VMM can utilize the additional hardware
capabilities provided by Vanderpool Technology. Options:
Disabled and Enabled. Default is "Enabled".
Turbo Mode
Enable/Disable Intel Turbo mode. Options: Disabled and
Enabled. Default is "Enabled".
SB-ATCA7300 Installation and Use Guide
5-17
BIOS Configuration
5.5.2.1.1 CPU Socket 0/1 CPU Information
Table 5-10 CPU Socket 0/1 CPU Information
Field
Description
Processor Module
Processor Module Name: Intel® Xeon® CPU L5638 @2.00GHz
Processor Stepping
Processor stepping (Usually B1 for L5638)
Microcode Revision
Microcode revision
5.5.2.2 Memory Configuration
Table 5-11 Memory Configuration
Field
Description
Total Memory
Total memory installed
Current Memory Mode
Current memory mode
Current Memory Speed Current memory speed
Mirroring
Mirroring support status
Sparing
Sparing support status
DIMM Information
Display DIMM presence and size information. See section 5.5.2.2.1
“Per Processor DIMM Information” on page 5-19.
Memory Mode
Select the mode for memory initialization. Options: Independent,
Mirroring and Lock Step. Default is "Independent".
Channel Interleaving
Select Channel Interleave setting. Options: Auto, 6 Way, 4 Way, 3
Way, 2 Way and 1 Way. Default is "Auto".
Rank Interleaving
Select different rank Interleaving setting. Options: Auto, 4 Way, 3
Way, 2 Way and 1 Way. Default is "Auto".
Patrol Scrub
Enable/Disable Patrol Scrubbing Feature. Options: Disable and Enable.
Default is "Enable".
Demand Scrub
Enable/Disable Demand Scrubbing Feature. Options: Disable and
Enable. Default is "Disable".
SB-ATCA7300 Installation and Use Guide
5-18
BIOS Configuration
5.5.2.2.1 Per Processor DIMM Information
Table 5-12 Per Processor DIMM Information
Field
Description
P01: Channel 0 Slot 0
DIMM status: Present or Not Present.
If Present, memory size and DDR mode is displayed.
P02: Channel 0 Slot 1
P03: Channel 1 Slot 0
P04: Channel 1 Slot 1
P05: Channel 2 Slot 0
P06: Channel 2 Slot 1
P01: Channel 0 Slot 0
P02: Channel 0 Slot 1
P03: Channel 1 Slot 0
P04: Channel 1 Slot 1
P05: Channel 2 Slot 0
P06: Channel 2 Slot 1
Example for Present status:
Present 4096 MB (DDR3).
Example for Not Present status:
Not Present.
DIMM status: Present or Not Present.
If Present, memory size and DDR mode is displayed.
Example for Present status:
Present 4096 MB (DDR3).
Example for Not Present status:
Not Present.
5.5.2.3 Chipset - North Bridge
Table 5-13 Chipset - North Bridge
Field
Description
Tylerburg Revision ID
Tylerburg (Intel 5520) Revision ID and stepping information.
Current QPI Link Freq
Current QPI Link Freq - 5.866 GT/s for example
Connected RTM
Connected RTM Name, such as SanBlaze SB-RTM414 or SBRTM 410
Auto-Detect RTM
If enabled, the RTM is detected and the RTM PCIe parameters
are set for this RTM. If disabled, the RTM PCIe parameters
can be set manually.
RTM PCIe Gen1 Speed This option force RTM PCIe root ports to Gen1 operation. If
disabled, RTM PCIe support both Gen1 and Gen2 devices.
PCIe to RTM
Select PCIe port Bifurcation for Zone3 connector (RTM).
Options: x4x4, x8. Default: x8
Primary Display
Select RTM or Onboard Graphics device as Primary Display.
Default is Auto.
Intel® VT for Directed
I/O Configuration
Intel® Virtual Technology for Directed I/O Configuration.
See section 5.5.2.3.1 “Intel® VT for Directed I/O
Configuration” on page 5-20.
SB-ATCA7300 Installation and Use Guide
5-19
BIOS Configuration
5.5.2.3.1 Intel® VT for Directed I/O Configuration
Table 5-14 Intel® VT for Directed I/O Configuration
Field
Intel(R) VT-d
Description
Enable/Disable Intel(R) Virtualization Technology for
Directed I/O. Options: Disabled and Enabled.
Default is "Disabled".
5.5.2.4 Chipset - South Bridge
Table 5-15 Chipset - South Bridge
Field
Description
Front Panel Ethernet
Enable/Disable Front Panel Ethernet Controller
USB Configuration
USB Configuration Parameters page. See section 5.5.2.4.1
“USB Port Configuration” on page 5-20.
5.5.2.4.1 USB Port Configuration
See also section 5.5.2.6 “USB Configuration” on page 5-21.
Table 5-16 USB Configuration
Field
Description
All USB Devices
Enable/Disable All USB Devices ports. Options: Disabled and
Enabled. Default is "Enabled".
Front Panel USB
Enable/Disable Front Panel USB port 1. This setting is
ignored if the "All USB Devices" option is disabled. Options:
Disabled and Enabled. Default is "Enabled".
Onboard eUSB Flash Disk Enable/Disable Onboard eUSB Flash Disk. This setting is
ignored if the "All USB Devices" option is disabled. Options:
Disabled and Enabled. Default is "Enabled".
ARTM USB
Enable/Disable RTM USB port. This setting is ignored if the
"All USB Devices" option is disabled. Options: Disabled and
Enabled. Default is "Enabled".
5.5.2.5 SATA Configuration
Table 5-17 SATA Configuration
Field
Description
SATA Cube (Onboard) Displays the SSD device (Cube Socket) present status
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5-20
BIOS Configuration
Table 5-17 SATA Configuration (Continued)
Field
Description
SATA Mode
Determines how SATA controllers operate. Options: Disable,
IDE mode, AHCI mode and RAID mode. Default is "IDE".
SATA Controller 0
Enable/Disable Serial-ATA Controller 0. This option is only
valid when SATA Mode is in IDE mode. Options: Disable,
Enhanced and Compatible. Default is "Compatible".
SATA Controller 1
Enable/Disable Serial-ATA Controller 1. This option is only
valid when SATA Mode is in IDE mode. Options: Disable and
Enhanced. Default is "Enhanced".
5.5.2.6 USB Configuration
See also section 5.5.2.4.1 “USB Port Configuration” on page 5-20.
Table 5-18 USB Configuration
Field
Description
USB Devices
Lists the USB devices attached.
EHCI Hand-off
This is a workaround for OSes without EHCI hand-off
support. The EHCI ownership change should be claimed by
the EHCI driver. Default is Disabled.
Mass Storage Devices Lists mass storage devices.
5.5.2.7 Super IO Configuration
Table 5-19 Super IO Configuration
Field
Super IO Chip
Description
The Super IO device is connected to the FPGA serial devices.
Serial Port 0 Configuration Sets parameters of Serial Port 0 (COM A). See section
5.5.2.7.1 “Serial Port 0 (COM A) Configuration” on page 522.
Serial Port 1 Configuration Sets parameters of Serial Port 0 (COM B). See section
5.5.2.7.2 “Serial Port 1 (COM B) Configuration” on page 522.
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5-21
BIOS Configuration
5.5.2.7.1 Serial Port 0 (COM A) Configuration
Table 5-20 Serial Port 0 Configuration
Field
Serial Port
Description
Enable/Disable serial port. Default is "Enabled".
Change Settings Select an optimal setting for Super IO Device. This option is
only valid when the serial port is enabled. Options are:
Auto
IO=3F8h; IRQ=4;
IO=3F8h; IRQ=3,4,5,6,7,10,11,12;
IO=2F8h; IRQ=3,4,5,6,7,10,11,12;
IO=3E8h; IRQ=3,4,5,6,7,10,11,12;
IO=2E8h; IRQ=3,4,5,6,7,10,11,12;
Default is IO=3F8h; IRQ=4
5.5.2.7.2 Serial Port 1 (COM B) Configuration
Table 5-21 Serial Port 1 Configuration
Field
Serial Port
Description
Enable/Disable serial port. Default is "Enabled".
Change Settings Select an optimal setting for Super IO Device. This option is
only valid when the serial port is enabled. Options are:
Auto
IO=3F8h; IRQ=4;
IO=3F8h; IRQ=3,4,5,6,7,10,11,12;
IO=2F8h; IRQ=3,4,5,6,7,10,11,12;
IO=3E8h; IRQ=3,4,5,6,7,10,11,12;
IO=2E8h; IRQ=3,4,5,6,7,10,11,12;
Default is IO=2F8h; IRQ=3,4,5,6,7,10,11,12
5.5.2.8 Serial Port Console Redirection
Table 5-22 Serial Port Console Redirection
Field
Description
COM0: Console
Redirection
Enable/Disable console redirection. Default is "Enabled".
COM0: Console
Redirection Settings
See section 5.5.2.8.1 “COM0/1 Console Redirection Settings”
on page 5-23.
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5-22
BIOS Configuration
Table 5-22 Serial Port Console Redirection (Continued)
Field
Description
COM1: Console
Redirection
Enable/Disable console redirection. To use COM1, COM0
must be disabled due to a Console Redirection limitation.
Default is "Disabled".
COM1: Console
Redirection Settings
See section 5.5.2.8.1 “COM0/1 Console Redirection Settings”
on page 5-23.
5.5.2.8.1 COM0/1 Console Redirection Settings
Table 5-23 COM0/1 Console Redirection Settings
Field
Description
Terminal Type
Emulation type:
ANSI: Extended ASCII char set.
VT100: ASCII char set.
VT100+: Extends VT100 to support color, function keys, etc.
VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1
or more bytes.
Options: VT100, VT100+, VT-UTF8 and ANSI.
Default is VT100.
Bits per second Selects serial port transmission speed. The speed must be
matched on the other side. Long or noisy lines may require
lower speeds. Options: 9600,19200, 57600 and 115200.
Default is 9600.
Data Bits
Data Bits. Options: 7 and 8. Default is 8.
Parity
A parity bit can be sent with the data bits to detect some
transmission errors.
None: No parity bit sent.
Even: Parity bit is 0 if the number of 1s in the data bits is even.
Odd: Parity bit is 0 if number of 1s in the data bits is odd.
Mark: Parity bit is always 1.
Space: Parity bit is always 0.
Mark and Space Parity do not allow for error detection. They
can be used as an additional data bit.
Options: None, Even, Odd, Mark and Space. Default is None.
Stop Bits
Stop bits indicates the end of a serial data packet. (A start bit
indicates the beginning of a packet.) The standard setting is 1
stop bit. Communication with slow devices may require 2 stop
bits. Options: 1 and 2. Default is 1.
SB-ATCA7300 Installation and Use Guide
5-23
BIOS Configuration
5.5.2.9 Runtime Error Logging
Table 5-24 Runtime Error Logging
Field
Description
Runtime Error Logging Enable/Disable Runtime Error Logging Support. Options: Disabled
and Enabled. Default is "Enabled".
PCI Error Logging
Enable/Disable PCI Error Logging. Options: Disabled, Enabled,
Default is "Enabled".
Error Threshold
Enter the correctable error threshold value to use if Runtime Error
Logging option is enabled. Range: 1 - 1000. Default is 10.
Error Logging Limit
Enter the Error Logging Limit value if Runtime Error Logging
option is enabled. Range: 1 - 20. Default is "10".
5.5.2.10 SMBIOS Event Log
Table 5-25 SMBIOS Event Log
Field
Description
SMBIOS Event Log Setting Change the SMBIOS Event Log configuration
View SMBIOS Event Log
View the SMBIOS Event Log records
5.5.2.11 Local IPMI System Event Log
Table 5-26 Local IPMI System Event Log
Field
Description
Erase Local SEL
Choose options for erasing local SEL
View Local IPMI
System Event Log
View the System Event Log from local IPMC records.
SB-ATCA7300 Installation and Use Guide
5-24
BIOS Configuration
5.5.3 BIOS IPMI Menu
Figure 5-4 BIOS IPMI Menu
Table 5-27 BIOS IPMI Menu
Field
Description
IPMC Version
IPMC version
ATCA Power Level
ATCA power level information
P-State Limitation
P-State limitation information
Available Power levels Available power levels for the blade
Connected RTM
Connected RTM type
RTM IPMC Version
RTM IPMC version
IPMI Watchdog
Configuration
Sel IPMI Watchdog configuration page. See section 5.5.3.1
“IPMI Watchdog Configuration” on page 5-26.
System Event Log
Sel Event Log configuration page. See section 5.5.3.2
“System Event Log” on page 5-26.
View FRU information FRU information page. See section 5.5.3.3 “View FRU
information” on page 5-26.
SB-ATCA7300 Installation and Use Guide
5-25
BIOS Configuration
5.5.3.1 IPMI Watchdog Configuration
Table 5-28 IPMI Watchdog Configuration
Field
Description
POST Timer (FRB2)
Enable or Disable FRB2 timer (POST/BIOS). Option: Disabled and
Enabled. Default is Enabled.
FRB2 Timer timeout
Set the Timeout value for the FRB2 Timer expiration. Options:
3,4,5 or 6 minutes, Default is 6 minutes.
FRB2 Timer Action
Specify how the system should respond if the FRB2 Timer expires.
Options: Do Nothing, Reset Power Down or Power Cycle. Default
is Reset.
O/S Watchdog Timer
Enable or Disable OS Watchdog Timer. Option: Disabled and
Enabled. Default is Disabled.
O/S Wtd Timer Timeout
Set the timeout value for the OS Boot Watchdog Timer. Options: 1,
2, 3, 5, 7, 10, 15 or 20 minutes, Default is 5 minutes.
O/S Wtd Timeout Action Specify the action after OS Watchdog Timer expiration. Options:
Do Nothing, Reset Power Down or Power Cycle. Default is Reset.
5.5.3.2 System Event Log
Table 5-29 System Event Log
Field
Description
Log EFI Status Codes
Disable the logging of EFI Status Codes, or log only error code or
only progress code or both. Options: Disabled, Both, Error code
and Progress code. Default is Both.
NOTE: A new value will not take effect until the system is reset.
5.5.3.3 View FRU information
Table 5-30 View FRU information
Field
Description
Product Manufacturer
"SANBlaze"
Product Name
Refer to IPMC FRU for the values.
Product Part Number
Refer to IPMC FRU for the values.
Product Version
Refer to IPMC FRU for the values.
Product Serial Number Refer to IPMC FRU for the values.
Manufacturing Date
Refer to IPMC FRU for the values.
Board Manufacturer
Refer to IPMC FRU for the values.
SB-ATCA7300 Installation and Use Guide
5-26
BIOS Configuration
Table 5-30 View FRU information (Continued)
Field
Description
Board Product Name
Refer to IPMC FRU for the values.
Board Serial Number
Refer to IPMC FRU for the values.
Board Part Number
Refer to IPMC FRU for the values.
5.5.4 BIOS Boot Menu
Figure 5-5 BIOS Boot Menu
Table 5-31 BIOS Boot Menu
Field
Description
Option ROM Execution
Option ROM Execution Configuration page. See section
5.5.4.1 “Boot Option ROM Execution” on page 5-28.
Setup Prompt Timeout
The number of seconds to delay waiting for the setup
activation key to be prompted (Del or F2).
A value of 65535 (0xFFFF) means the system will wait
indefinitely. Setting of 0 means the system will not wait (not
recommended). Default is 3.
Bootup NumLock State
Select the keyboard NumLock state. Options: On and Off.
Default is On.
Wait AMC/RTM Timeout Wait time in seconds for PCIe device detection before system
times out. Range: 0-255, Default is 3.
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BIOS Configuration
Table 5-31 BIOS Boot Menu (Continued)
Field
Description
Wait AMC/RTM Policy
Options: Force or Auto. If set to "Force", BIOS waits for the
value specified in Timeout; If set to "Auto", BIOS ignores the
value specified in Timeout . Default is "Auto."
Boot Option #1
Boot group option #1.
Boot Option #2
Boot group option #2.
Boot Option #3
Boot group option #3.
Boot Option #4
Boot group option #4.
Boot Option #5
Boot group option #5.
Boot Option #6
Boot group option #6.
5.5.4.1 Boot Option ROM Execution
Figure 5-6 BIOS Boot Option ROM Execution
Table 5-32 BIOS Boot Option ROM Execution
Field
Description
Front Panel PXE Boot
Controls execution of the Option ROM for the Front Panel Ethernet
controller. Options: Disabled and Enabled. Default is "Disabled".
Base Network PXE Boot
Controls execution of the Option ROM for the Base Interface
Ethernet. Options: Disabled and Enabled. Default is "Enabled".
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BIOS Configuration
Table 5-32 BIOS Boot Option ROM Execution (Continued)
Field
Description
ARTM Network PXE Boot Controls execution of the Option ROM for the Ethernet on the
ARTM. Options: Disabled and Enabled. Default is "Disabled".
ARTM SAS Boot
Controls execution of the Option ROM for the SAS controller on
the ARTM. Options: Disabled and Enabled. Default is "Disabled".
Fabric Network Boot
Controls execution of the Option ROM for the Fabric Interface
Ethernet. Options: Disabled, PXE and iSCSI. Default is "PXE".
ATCA Power Level Limit
Enable/Disable Spread Spectrum Clock to the ARTM. Option:
Disabled and Enabled. Default is "Enabled".
5.5.5 BIOS Security Menu
Figure 5-7 BIOS Security Menu
Table 5-33 BIOS Security Menu
Field
Description
Setup Administrator Password Set the Setup Administrator password
User Password
SB-ATCA7300 Installation and Use Guide
Set the Setup User password
5-29
BIOS Configuration
5.5.6 Save and Exit Menu
Figure 5-8 Save and Exit Menu
Table 5-34 Save and Exit Menu
Field
Description
Save Changes and Exit
Exits system setup after saving the changes.
Discard Changes and Exit
Exits system setup without saving any changes.
Save Changes and Reset
Resets the system after saving the changes.
Discard Changes and Reset Resets system setup without saving any changes.
Save Changes
Saves changes done to any of the setup options.
Discard Changes
Discard changes done to any of the setup options.
Restore Defaults
Restore/Load default values for all the setup options. This
option is the same as pressing F3.
Boot Override
Overrides the boot device order from the Boot menu and
selects the specific device from which the system will boot on
a one-time basis.
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6 Maps and Registers
6.1 Interrupt Structure
The SB-ATCA7300 supports both APIC and non-APIC (legacy PIC Mode)
modes for interrupt delivery to the CPUs. The 8259 PIC Mode Interrupt
Concentrator inside the ICH10R supports 16 interrupts (eight external signal
inputs). The IO-APIC device inside the ICH10R supports 24 interrupt sources.
In APIC mode the ICH10R supports only front side bus interrupt delivery (not the
serial APIC mode). The following figure and tables summarize the interrupt
sources and mappings for the SB-ATCA7300. APIC mode is configured through
BIOS after boot-up phase which is done in legacy PIC mode.
Figure 6-1 Interrupt Structure of the SB-ATCA7300
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6-1
Maps and Registers
6.1.1 APIC Mode Interrupts
In APIC Mode the PCI Interrupts A:H are mapped to IRQ[16:23].
If an interrupt is used for PCI IRQ[A:H], SCI or TCO, it must not be used for ISA
(legacy)-style interrupts (using SERIRQ).
Table 6-1 APIC Mode Interrupt Mapping
IRQ
0
Interrupt Source
Cascade from 8259 1
1
2
8254 Counter 0, Timer 0 (legacy mode)
3
4
5
6
7
8
RTC, Timer 1 (legacy mode)
9
Option for TCI, TCO
10
Option for TCI, TCO
11
Timer 2, Option for TCI, TCO
12
Timer 3
13
FERR# logic
14
SATA Primary (legacy mode)
15
SATA Secondary (legacy mode)
16
PIRQ[A]#
17
PIRQ[B]#
18
PIRQ[C]#
19
PIRQ[D]#
20
PIRQ[E]# (GPIO)
21
PIRQ[F]# (GPIO)
22
PIRQ[G]# (GPIO)
23
PIRQ[H]# (GPIO)
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Maps and Registers
6.1.2 Non-APIC Mode Interrupts
The non-APIC (legacy mode) interrupt map is shown in the table below.
Table 6-2 Non-APIC (PIC mode / 8259 Mode) Interrupt Mapping
Type
Master
8259
IRQ
Typical Interrupt
Source
Interrupt Source
0
Internal
8254 Counter 0, Timer 0 (HPET)
1
Keyboard
IRQ1 via SERIRQ
2
Internal
Slave 8259 INTR output
3
Serial Port A
IRQ3 via SERIRQ, PIRQ#
4
Serial Port B
IRQ4 via SERIRQ, PIRQ#
5
Parallel/Generic
IRQ5 via SERIRQ, PIRQ#
6
Floppy
IRQ6 via SERIRQ, PIRQ#
7
Parallel/Generic
IRQ7 via SERIRQ, PIRQ#
8
Internal RTC
Internal RTC, Timer 1 (HPET)
9
Generic
IRQ9 via SERIRQ, SCI, TCO, or PIRQ#
10
Generic
IRQ10 via SERIRQ, SCI, TCO, or PIRQ#
11
Generic
IRQ11 via SERIRQ, SCI, TCO, or PIRQ# or
Timer#2 (HPET)
12
PS/2 Mouse
IRQ11 via SERIRQ, SCI, TCO, or PIRQ# or
Timer#3 (HPET)
13
Internal
State Machine output based on processor FERR#
assertion. May optionally be used for SCI or TCO
interrupt if FERR# not needed.
14
SATA
SATA Primary (legacy mode), or via SERIRQ or
PIRQ#
15
SATA
SATA Secondary (legacy mode), or via SERIRQ
or PIRQ#
Slave
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Maps and Registers
6.2 PCI Express Lane Mapping
The Xeon 5520 (Tylersburg IOH36D) PCI Express lanes use the naming
convention shown in Table 6-3 below, and are grouped as shown in Figure 6-2.
Table 6-3 PCI Express Lane Naming
Lane
1
2
3
4
5
6
7
8
9
10
x2
x2
x4
x4
x4
x4
x4
x4
x4
x4
x8
x4
x8
x8
x16
x8
x16
Figure 6-2 IOH36D PCIe Lane Mapping on SB-ATCA7300
6.3 Configuration Registers
The configuration register descriptions in this chapter use the conventions shown
below in Table 6-4 and in Table 6-5.
Table 6-4 Register Default Value Conventions
Default
0 or 1
Description
Not applicable or undefined
Default value after PWR_GOOD is valid or after ICH_PLTRST
deassertion
Ext.
External Reset Source; default depends on external logic level
reset: 0 or 1
Default value after deassertion of the reset signal named reset
Undef.
Undefined value
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Maps and Registers
Table 6-5 Register Access Type Conventions
Access
Description
r
Read only
w
Write only
r/w
Read and write
w1c
Write-1-to-clear, ignore bit while reading
r/w1c
Read and write-1-to-clear, write 0 has no effect
r/w1s
Read and write-1-to-set, write 0 has no effect
r/w1t
Read and write-1-to-toggle, write 0 has no effect
LPC:
The prefix “LPC:” signals that the access is made using the LPC interface.
For example, LPC: r/w means that the register bit is read/writable from the LPC
interface
IPMC:
The prefix “IPMC:” signals that the access is made using the IPMC SPI interface.
For example, IPMC: r/w means that the register bit is read/writable from IPMC SPI
interface
6.3.1 FPGA Register Access and Addresses
The FPGA registers may be accessed from the host or the IPMC. From the host,
the LPC bus interface is used. The IPMC uses an SPI interface.
6.3.1.1 LPC Addresses
The LPC bus supports three different access protocols, but only one is
mplemented.
6.3.1.1.1 LPC I/O Addresses
The LPC interface responds to LPC I/O accesses listed in Table 6-6 below. All
other LPC I/O accesses are ignored.
Table 6-6 LPC I/O Register Map Overview
Base
Address
Address
Size
Address
Range Name
Description
0x4E
2
SIW
Super IO Configuration Registers for Index and
Date
0x80
1
POSTCODE
POST Code Register
BASE1
8
COM1
UART1. Serial Port 1 (Logical Device 4). BASE1
address is set up during Super IO configuration
BASE2
8
COM2
UART2. Serial Port 2. (Logical Device 4). BASE2
address is set up during Super IO configuration
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Maps and Registers
Table 6-6 LPC I/O Register Map Overview (Continued)
Base
Address
0x600
Address
Size
128
Address
Range Name
REGISTERS
Description
FPGA Registers
All LPC I/O accesses to address POSTCODE, within the address range
REGISTERS and within the address ranges of COM1 or COM2 (only when
enabled during Super IO configuration) are decoded by the LPC core.
6.3.1.1.2 LPC Memory Addresses
The LPC interface never responds to LPC Memory accesses.
6.3.1.1.3 LPC Firmware Addresses
The LPC interface never responds to LPC Firmware accesses.
6.3.1.2 SPI Register Access and Addresses
All SPI accesses from the IPMC to the FPGA with the SPI select signal
IPMC_SPI_SS_FPGA_ asserted are accepted.
Table 6-7 IPMC SPI Register
SPI Address Range Address Range Name
0x00 – 0x7F
REGISTERS
Description
FPGA Registers
6.3.2 POST Code Register
The FPGA provides an 8 bit wide register to store POST codes at LPC I/O address
0x80. The two nibbles of the register are converted to 7 segment codes and are
displayed as two hex values by two 7 segment LED displays at the bottom of the
SB-ATCA7300 board..
The IPMC can read the POST code using the SPI interface (with the signal
IPMC_SPI_SS_FPGA_ asserted) using SPI address 0x7F.
Table 6-8 POST Code Register
LPC I/O Address: 0x80
IPMC SPI Address: 0x7f
Bit
Description
Default
Access
7:0
POST codes from host
0
LPC: r/w
IPMC: r
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Maps and Registers
6.3.3 Super IO Functionality Configuration Register
After a LPC Reset (ICH_PLTRST_ is asserted) or “Power On Reset,” the Super
IO is in Run Mode with the UARTs disabled. These may be configured using the
LPC IO Address Range SIW (INDEX and DATA) by placing the Super IO into
Configuration State.
The BIOS uses these configuration addresses to initialize the logical devices
during POST. The INDEX and DATA addresses are only valid and effective
when the Super IO is in Configuration State. When the Super IO is not in
Configuration State, all reads return 0xFF and any write data is ignored.
Table 6-9 Super IO Configuration Index Register
LPC I/O Address: 0x4E
Bit
Description
7:0 INDEX. Configuration Index
Default
Access
0xff
LPC: r/w
Table 6-10 Super IO Configuration Data Register
LPC I/O Address: 0x4F
Bit
Description
Default
Access
0xff
LPC: r/w
7:0 DATA Configuration Data
6.3.3.1 Entering Configuration State
The Super IO device enters Configuration State after the following contiguous
sequence.
1. Write 68 to Configuration Index Port.
2. Write 08 to Configuration Index Port.
6.3.3.2 Configuration State
Only two states are defined (Run and Configuration). In the Run State the Super
IO is always ready to enter the Configuration State.
The system sets the logical device information and activates desired logical
devices through the INDEX and DATA ports.
The configuration registers are accessed in two steps:
1. Write the index of the Logical Device Number Configuration Register (07) to
the INDEX PORT, and then write the number of the desired logical device to the
DATA PORT.
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Maps and Registers
2. Write the address of the desired configuration register within the logical
device to the INDEX PORT, and then write or read the configuration register
through the DATA PORT.
Note - If accessing the Global Configuration Registers, step (1) is not required.
The Super IO returns to the RUN State.
6.3.3.3 Super IO Functionality Configuration Registers
The SB-ATCA7300 implements only the subset of Super I/O functions required
for serial communication.
Note - Address locations that are not listed are considered reserved register
locations. Reads to reserved registers may return non-zero values. Writes to
reserved locations may cause system failure.
6.3.3.3.1 Global Control Configuration Registers
The Super IO Global Registers lie in the address range 0x00-0x2F. All eight bits
of the ADDRESS Port are used for register selection. All unimplemented registers
and bits ignore writes and return zero when read. The INDEX PORT is used to
select a configuration register in the chip. The DATA PORT is then used to access
the selected register. These registers are accessible only in Configuration State.
Table 6-11 Global Configuration Register Summary
Index Address
Description
0x07
Super IO Logical Device Number
0x20
Super IO Device ID
0x21
Super IO Device Revision
0x28
Super IO LPC Control
0x29
Super IO SERIRQ and Pre-divide Control
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Maps and Registers
Table 6-12 Super IO Logical Device Number Register
Index Address: 0x07
Bit
Description
Default
Access
0
LPC: r/w
Logical Device Number:
0x04: Logical Device 4 (UART 1Serial Port 1)
0x05: Logical Device 5 (UART2 Serial Port 2)
7:0
A write to this register selects the current logical
device. This allows access to the control and
configuration registers for each logical device.
Table 6-13 Super IO Device Identification Register
Index Address: 0x20
Bit Description Default Access
7:0 Device ID
0
LPC: r
Table 6-14 Super IO Device Revision Register
Index Address: 0x21
Bit
Description
7:0 Device Revision
Default Access
0x01
LPC: r
Table 6-15 Super IO LPC Control Register
Index Address: 0x28
Bit
Description
Default Access
0
LPC Bus Wait States:
1: Long wait states (sync 6)
1
LPC: r
1
Reserved
0
LPC: r
Table 6-16 Global Super IO SERIRQ and Pre-divide Control Register
Index Address: 0x29
Bit
Description
Default
Access
0
SERIRQ enable:
0: disabled. Serial interrupts disabled.
1: enabled. Logical devices participate in interrupt generations.
0
LPC: r/w
1
SERIRQ Mode:
1: Continuous Mode
1
LPC: r
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Maps and Registers
Table 6-16 Global Super IO SERIRQ and Pre-divide Control Register
Index Address: 0x29
Bit
Description
Default
Access
UART Clock pre-divide
00: divide by 1
3:2 01: divide by 8
10: divide by 26 (CLK_UART is 48 MHz)
11: reserved
0
LPC: r/w
7:4 Reserved
0
LPC: r
6.3.3.3.2 Logical Device Configuration Registers
These registers are used to access the configuration registers assigned to each
logical unit. The Super IO supports two logical units and has two sets of logical
device registers.
The two logical devices are UART1 (Logical Number 4) and UART2 (Logical
Number 5). A separate set (bank) of control and configuration registers exists for
each logical device and is selected with the Logical Device Number Register.
The INDEX PORT is used to select a specific logical device register. These
registers are then accessed through the DATA PORT. The Logical Device
registers are accessible only when the device is in the Configuration state.
Table 6-17 Logical Device Configuration Register Summary
Index Address
Description
0x30
Enable
0x60
Base IO Address MSB
0x61
Base IO Address LSB
0x70
Primary Interrupt Select
0x74
Reserved
0x75
Reserved
0xF0
Reserved
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Maps and Registers
The logical register addresses are shown in the tables below.
Table 6-18 Logical Device Enable Register
Index Address: 0x30
Bit
0
Description
Default
Access
Logical Device Enable:
0: disabled. Currently selected device is inactive.
1: enabled. . The currently selected device is enabled.
1
LPC: r/w
0
LPC: r
7:1 Reserved
Table 6-19 Logical Device Base IO Address MSB Register
Index Address: 0x60
Bit
Description
Default
Access
0
LPC: r/w
7:0 Logical Device Base IO Address MSB
Table 6-20 Logical Device Base IO Address LSB Register
Index Address: 0x61
Bit
Description
Default
Access
2:0 Bits 0 to 2 are read only. Address is on an 8 byte boundary.
0
LPC: r
7:3 Logical Device Base IO Address LSB.
0
LPC: r/w
Registers 0x60 (MSB) and 0x61 (LSB) set the Logical Device Base IO address for
the logical device. For example, to specify Base IO address 0x3F8, the content of
Register 0x60 is 0x03, and the content of Register 0x61 is 0xF8.
See the table below for Common Decode Ranges:
Table 6-21 Logical Device Common Decode Ranges
IO Address Range Description
0x3F8 – 0x3FF
COM1
0x2F8 – 0x2FF
COM2
0x2E8 – 0x2EF
COM3
0x3E8 – 0x3EF
COM4
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Maps and Registers
Table 6-22 Logical Device Primary Interrupt Register
Index Address: 0x70
Bit
Description
Default
Access
Interrupt level is used for Primary Interrupt.:
0x0: no interrupt selected
0x1: IRQ1
0x2: IRQ2
0x3: IRQ3
0x4: IRQ4
0x5: IRQ5
0x6: IRQ6
3:0 0x7: IRQ7
0x8: IRQ8
0x9: IRQ9
0xA: IRQ10
0xB: IRQ11
0xC: IRQ12
0xD: IRQ13
0xE: IRQ14
0xF: IRQ15
1
LPC: r/w
7:4 Reserved
0
LPC: r
An Interrupt is activated by enabling the device (at offset 0x30), setting this
register to a non-zero value, then setting any combination of bits 0-4 in the
corresponding UART IER and the occurrence of the corresponding UART event
(i.e. Modem Status Change, Receiver Line Error Condition, Transmit Data
Request, Receiver Data Available or Receiver Time Out), and setting the OUT2
bit in the MCR.
Table 6-23 Logical Device 0x74 Reserved Register
Index Address: 0x74
Bit Description Default Access
7:0 Reserved
0x04
LPC: r
Table 6-24 Logical Device 0x75 Reserved Register
Index Address: 0x75
Bit Description Default Access
7:0 Reserved
SB-ATCA7300 Installation and Use Guide
0x04
LPC: r
6-12
Maps and Registers
Table 6-25 Logical Device 0xF0 Reserved Register
Index Address: 0xF0
Bit Description Default Access
7:0 Reserved
0x04
LPC: r
6.3.4 UART1 and UART2 Register Map
The LPC IO Base addresses BASE1 for UART1 and BASE2 for UART2 are set
up during BIOS configuration.
6.3.4.1 UART Register Overview
Table 6-26 below shows the registers and their addresses as offsets of a base
address for one of the two UARTs.
The state of the Divisor Latch Bit (DLAB), which is the MOST significant bit of
the Serial Line Control Register (SCR), affects the selection of certain of the
UART registers. The DLAB bit must be set high by the system software to access
the Baud Rate Generator Divisor Latches (DLL and DLM).
Table 6-26 UART Register Overview
LPC IO
Address
DLAB Bit
Value
Base
0
Receiver Buffer (RBR). Read Only
Base
0
Transmitter Holding (THR). Write Only
Base + 1
0
Interrupt Enable Register (IER)
Base + 2
X
Interrupt Identification Register (IIR). Read Only
Base + 2
X
FIFO Control Register (FCR). Write Only
Base + 3
X
Line Control Register (LCR)
Base + 4
X
Modem Control Register (MCR)
Base + 5
X
Line Status Register (LSR). Read Only
Base + 6
X
Modem Status Register (MSR). Read Only
Base + 7
X
Scratch Pad Register (SCR)
Base
1
Divisor Latch LSB (DLL)
Base + 1
1
Divisor Latch MSB (DLM)
Description
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Maps and Registers
6.3.4.2 UART Registers DLAB=0
6.3.4.2.1 Receiver Buffer Register (RBR)
In non-FIFO mode, this register holds the character received by the UART's
Receive Shift Register. If fewer than eight bits are received, the bits are rightjustified and the leading bits are zeroed. Reading the register empties the register
and resets the Data Ready (DR) bit in the Line Status Register to zero. Other
(error) bits in the Line Status Register are not cleared. In FIFO mode, this register
latches the value of the data byte at the top of the FIFO.
Table 6-27 Receiver Buffer Register (RBR) if DLAB=0
LPC IO Address: Base
Bit
Description
Default Access
7:0 Receiver Buffer register(RBR) Undef.
LPC: r
6.3.4.2.2 Transmitter Holding Register (THR)
This register holds the next data byte to be transmitted. When the Transmit Shift
Register becomes empty, the contents of the Transmit Holding Register are
loaded into the shift register and the transmit data request (TDRQ) bit in the Line
Status Register is set to one.
Table 6-28 Transmitter Holding Register (THR) if DLAB=0
LPC IO Address: Base
Bit
Description
Default Access
7:0 Transmitter Holding register(THR) Undef.
LPC: w
In FIFO mode, writing to THR moves data to the top of the FIFO. The data at the
bottom of the FIFO is loaded into the shift register when it is empty.
6.3.4.2.3 Interrupt Enable Register (IER)
This register controls the four types of interrupts which independently activate the
int signal and set a value in the Interrupt Identification Register. Each of the four
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Maps and Registers
interrupt types can be disabled by resetting the appropriate bit of the IER register.
Similarly, by setting the appropriate bits, the selected interrupts can be enabled.
Table 6-29 Interrupt Enable Register (IER), if DLAB=0
LPC IO Address: Base + 1
Bit
Description
Default
Access
0
Receive data interrupt enable/disable:
1: receive data interrupt enabled
0: receive data interrupt disabled
0
LPC: r/w
1
Transmitter holding register empty (THRE) interrupt enable/disable
1: THRE interrupt enabled
0: THRE interrupt disabled
0
LPC: r/w
2
Receiver line status interrupt enable/disable
1: receiver line status interrupt enabled
0: receiver line status interrupt disabled
0
LPC: r/w
3
Modem status interrupt enable/disable:
1: modem status interrupt enabled
0: modem status interrupt disabled
0
LPC: r/w
0
LPC: r
7:4 Reserved
6.3.4.2.4 Interrupt Identification Register (IIIR)
In order to minimize software overhead during data character transfers, the UART
prioritizes interrupts into four levels (as shown in Table 6-29 above) and indicates
these in the Interrupt Identification Register. The Interrupt Identification Register
(IIR) stores information indicating that a prioritized interrupt is pending and the
source of that interrupt.
Table 6-30 UART Interrupt Priorities
Priority Level
1 (highest)
Interrupt Source
Receiver Line Status. One or more error bits were set.
2
Received Data is available. In FIFO mode, trigger level was reached; in
non-FIFO mode, RBR has data.
2
Receiver Time out occurred. It happens in FIFO mode only, when there is
data in the receive FIFO but no activity for a time period.
3
Transmitter requests data. In FIFO mode, the transmit FIFO is half or
more than half empty; in non-FIFO mode, THR is read already
4
Modem Status: one or more of the modem input signals has changed state
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Maps and Registers
Table 6-31 Interrupt Identification Register (IIR)
LPC IO Address: Base + 1
Bit
Description
Default Access
Interrupt status bit:
1: no interrupt pending
0: interrupt pending
0
1
LPC: r
0
LPC: r
0
LPC: r
5:4 Reserved
0
LPC: r
FIFO Mode Enable bits:
00: Default mode
7:6 01: Reserved
10: Reserved
11: FIFO mode
0
LPC: r
Interrupt priority level and source:
11: Receiver line status
2:1 10: Receiver data available
01: Transmitter holding register empty
00: Modem status
Time Out Detected:
0: No time out interrupt is pending
1: Character time-out indication (FIFO mode only)
3
6.3.4.2.5 FIFO Control Register (FCR)
The FCR is a write-only register that is located at the same address as the IIR (the
IIR is a read-only register). The FCR enables, disables and ckears the transmitter
and receiver FIFOs, and sets the receiver FIFO trigger level.
Table 6-32 FIFO Control Register (FCR)
LPC IO Address: Base + 2
Bit
Description
Default Access
0
FIFO enable/disable:
1: Transmitter and Receiver FIFO enabled
0: FIFO disabled
0
LPC: w
1
Receiver FIFO reset:
1: Bytes in receiver FIFO and counter are reset.
Shift register is not reset (bit is self-clearing)
0: No effect
0
LPC: w
2
Transmit FIFO reset:
1: Bytes in receiver FIFO and counter are reset.
Shift register is not reset (bit is self-clearing)
0: No effect
0
LPC: w
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Maps and Registers
Table 6-32 FIFO Control Register (FCR) (Continued)
LPC IO Address: Base + 2
Bit
3
Description
Default Access
Receiver/Transmitter ready. Not supported.
0
LPC: w
5:4 Reserved
0
LPC: w
Receiver FIFO interrupt trigger level:
00: 1 byte
7:6 01: 4 bytes
10: 8 bytes
11: 14 bytes
0
LPC: w
6.3.4.2.6 Line Control Register (LCR)
The Line Control Register (LCR) specifies the format of the asynchronous data
communications exchange. The serial data format consists of a start bit (logic 0),
five to eight data bits, an optional parity bit, and one or two stop bits (logic 1). The
LCR has bits for accessing the Divisor Latch and causing a break condition.
The programmer can also read the contents of the Line Control Register. The read
capability simplifies programming and eliminates the need for separate storage in
system memory.
Table 6-33 Line Control Register (LCR)
LPC IO Address: Base + 3
Bit
Description
Default
Access
0
LPC: r/w
2
Stop bit length.
1: 1.5 stop bits for 5 bit WORD length
1: 2 stop bits for 6, 7, and 8 bit WORD length
0: 1 stop bit for any serial character WORD length
0
LPC: r/w
3
Parity enable/disable
When bit 3 is set, a parity bit is generated in transmitted data
between the last data WORD bit and the first stop bit. In
received data, if bit 3 is set, parity is checked. When bit 3 is
cleared, no parity is generated or checked.
1: Parity enabled
0: Parity disabled
0
LPC: r/w
Serial character WORD length.
00: 5 bits
1:0 01: 6 bits
10: 7 bits
11: 8 bits
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Maps and Registers
Table 6-33 Line Control Register (LCR) (Continued)
LPC IO Address: Base + 3
Bit
Description
Default
Access
4
Parity even/odd
When parity is enabled and bit 4 is set, even parity (an even
number of logic ones in the data and parity bits) is selected.
When parity is disabled and bit 4 is cleared, odd parity (an odd
number of logic ones) is selected.
1: Even parity
0: Odd parity
0
LPC: r/w
5
Stick parity
When bits 3, 4, and 5 are set, the parity bit is transmitted and
checked as cleared. When bits 3 and 5 are set and bit 4 is
cleared, the parity bit is transmitted and checked as set. If bit 5
is cleared, stick parity is disabled.
1: Stick parity enabled
0: Stick parity disabled
0
LPC: r/w
6
Break control bit
Bit 6 is set to force a break condition, i.e. a condition where
TXD is forced to the spacing (cleared) state. When bit 6 is
cleared, the break condition is disabled and has no affect on the
transmitter logic. It only effects TXD.
1: Break condition enabled
0: Break condition disabled
0
LPC: r/w
7
Divisor latch access bit (DLAB)
Bit 7 must be set to access the divisor latches of the baud
generator during a read or write. Bit 7 must be cleared during a
read or write to access the RBR, THR, or IER.
1: Access to DLL and DLM registers
0: Access to RBR, THR and IER registers
0
LPC: r/w
6.3.4.2.7 Modem Control Register (MCR)
This 8-bit register controls the interface with the modem or data set (or a
peripheral device emulating a modem).
Table 6-34 Modem Control Register (MCR)
LPC IO Address: Base + 4
Bit
0
Description
Data terminal ready (DTR#) output control
1: DTR# output in low (active) state
0: DTR# output in high state
SB-ATCA7300 Installation and Use Guide
Default
Access
0
LPC: r/w
6-18
Maps and Registers
Table 6-34 Modem Control Register (MCR) (Continued)
LPC IO Address: Base + 4
Bit
Description
Default
Access
1
Request to send (RTS#) output control
1: RTS# output in low (active) state
0: RTS# output in high state
0
LPC: r/w
2
User output control signal (OUT1#)
1: OUT1# output in high state
0: OUT1# output in low state
Not supported
0
LPC: r/w
3
User output control signal (OUT2#)
1: OUT2# output in high state
0: OUT2# output in low state
Not supported
0
LPC: r/w
4
Local loop back diagnostic control
When loop back is activated: Transmitter TXD is set high.
Receiver RXD is disconnected. Output of Transmitter Shift
register is looped back into the receiver shift register input.
Modem control inputs are disconnected Modem control outputs
are internally connected to modem control inputs. Modem
control outputs are forced to the inactive (high) levels.
1: Loop back mode activated
0: Normal operation
0
LPC: r/w
5
Autoflow control enable (AFE)
1: Autoflow control enabled (auto-RTS# and auto-CTS# or autoCTS# only enabled)
0: Autoflow control disabled
0
LPC: r/w
0
LPC: r
7:6 Reserved
6.3.4.2.8 Line Status Register (LSR)
This register provides status information to the processor concerning the data
transfers. Bits 5 and 6 provide information about the transmitter section. The rest
of the bits contain information about the receiver.
In non-FIFO mode, three of the LSR register bits, parity error, framing error, and
break interrupt, show the error status of the character that has just been received.
In FIFO mode, these three bits of status are stored with each received character in
the FIFO. The LSR shows the status bits of the character at the top of the FIFO.
When the character at the top of the FIFO has errors, the LSR error bits are set and
are not cleared until software has read the LSR, even if the character in the FIFO
is read and a new character is now at the top of the FIFO.
SB-ATCA7300 Installation and Use Guide
6-19
Maps and Registers
Bits one through four are the error conditions that produce a receiver line status
interrupt when any of the corresponding conditions are detected and the interrupt
is enabled. These bits are not cleared by reading the erroneous byte from the FIFO
or receive buffer. They are cleared only by reading the LSR. In FIFO mode, the
line status interrupt occurs only when the erroneous byte is at the top of the FIFO.
If the erroneous byte being received is not at the top of the FIFO, an interrupt is
generated only after the previous bytes are read and the erroneous byte is moved
to the top of the FIFO.
Table 6-35 Line Control Register (LCR)
LPC IO Address: Base + 5
Bit
Description
0
Receiver data ready (DR) indicator
DR is set whenever a complete incoming character has been
received and transferred into the RBR or the FIFO. DR is cleared
by reading all of the data in the RBR or the FIFO.
1: New data received
0: No new data
0
LPC: r
1
Overrun error (OE) indicator
When OE is set, it indicates that before the character in the RBR
was read, it was overwritten by the next character transferred into
the register. OE is cleared every time the CPU reads the contents
of the LSR. If the FIFO mode data continues to fill the FIFO
beyond the trigger level, an overrun error occurs only after the
FIFO is full and the next character has been completely received in
the shift register. An overrun error is indicated to the CPU as soon
as it happens. The character in the shift register is overwritten but
it is not transferred to the FIFO.
1: Overrun error occurred
0: No overrun error
0
LPC: r
2
Parity Error (PE) indicator
When PE is set, it indicates that the parity of the received data
character does not match the parity selected in the LCR (bit 4). PE
is cleared every time the CPU reads the contents of the LSR. In the
FIFO mode, this error is associated with the particular character in
the FIFO to which it applies. This error is revealed to the CPU
when its associated character is at the top of the FIFO.
1: Parity error occurred
0: No parity error
0
LPC: r
SB-ATCA7300 Installation and Use Guide
Default Access
6-20
Maps and Registers
Table 6-35 Line Control Register (LCR) (Continued)
LPC IO Address: Base + 5
Bit
Description
3
Framing Error (FE) indicator
When FE is set, it indicates that the received character did not have
a valid (set) stop bit. FE is cleared every time the CPU reads the
contents of the LSR. In the FIFO mode, this error is associated
with the particular character in the FIFO to which it applies. This
error is revealed to the CPU when its associated character is at the
top of the FIFO. The ACE tries to resynchronize after a framing
error. To accomplish this, it is assumed that the framing error is
due to the next start bit. The ACE samples this start bit twice and
then accepts the input data.
1: Framing error occurred
0: No framing error
0
LPC: r
4
Break Interrupt (BI) indicator
When BI is set, it indicates that the received data input was held
low for longer than a full-word transmission time. A full-word
transmission time is defined as the total time to transmit the start,
data, parity, and stop bits. BI is cleared every time the CPU reads
the contents of the LSR. In the FIFO mode, this error is associated
with the particular character in the FIFO to which it applies. This
error is revealed to the CPU when its associated character is at the
top of the FIFO. When a break occurs, only one 0 character is
loaded into the FIFO. The next character transfer is enabled after
RXD goes to the marking state for at least two Receiver CLK
samples and then receives the next valid start bit.
1: Full WORD transmission time exceeded
0: Normal operation
0
LPC: r
5
Transmit Holding Register Empty (THRE) indicator
THRE is set when the THR is empty, indicating that the ACE is
ready to accept a new character. If the THRE interrupt is enabled
when THRE is set, an interrupt is generated. THRE is set when the
contents of the THR are transferred to the TSR. THRE is cleared
concurrent with the loading of the THR by the CPU. In FIFO
mode, THRE is set when the transmit FIFO is empty; it is cleared
when at least one byte is written to the transmit FIFO.
1: THR/Transmit FIFO empty
0: THR/Transmit FIFO contains data
0
LPC: r
SB-ATCA7300 Installation and Use Guide
Default Access
6-21
Maps and Registers
Table 6-35 Line Control Register (LCR) (Continued)
LPC IO Address: Base + 5
Bit
Description
Default Access
6
Transmitter Empty (TEMT) indicator
TEMT bit is set when the THR and the TSR are both empty. When
either the THR or the TSR contains a data character, TEMT is
cleared. In FIFO mode, TEMT is set when both the transmitter
FIFO and shift register are empty.
1: THR/Transmit FIFO/TSR empty
0: THR/Transmit FIFO/TSR contains data
0
LPC: r
7
FIFO data error
In the FIFO mode, LSR7 is set when there is at least one parity,
framing, or break error in the FIFO. It is cleared when the
microprocessor reads the LSR and there are no subsequent errors
in the FIFO. If the FIFO is not used, this bit always reads 0.
1: FIFO data error encountered
0: No FIFO error encountered
0
LPC: r
6.3.4.2.9 Modem Status Register (MSR)
This 8-bit register provides the current state of the control lines from the modem
or data set (or a peripheral device emulating a modem) to the processor. In
addition to this current state information, four bits of the Modem Status register
provide change information. Bits 03:00 are set to a logic 1 when a control input
from the Modem changes state. They are reset to a logic 0 when the processor
reads the Modem Status register.
When bits 0, 1, 2, or 3 are set to logic 1, a Modem Status interrupt is generated if
bit 3 of the Interrupt Enable Register is set.
Table 6-36 Modem Status Register (MSR)
LPC IO Address: Base + 6
Bit
Description
Default
Access
0
Change in clear-to-send (DCTS) indicator
DCTS indicates that the CTS# input has changed state since the
last time it was read by the CPU. When DCTS is set (autoflow
control is not enabled and the modem status interrupt is enabled),
a modem status interrupt is generated. When autoflow control is
enabled (DCTS is cleared), no interrupt is generated.
1: Change in state of CTS# input since last read
0: No change in state of CTS# input since last read
0
LPC: r/w
SB-ATCA7300 Installation and Use Guide
6-22
Maps and Registers
Table 6-36 Modem Status Register (MSR) (Continued)
LPC IO Address: Base + 6
Bit
Description
Default
Access
1
Change in data set ready (DDSR) indicator
DDSR indicates that the DSR# input has changed state since the
last time it was read by the CPU. When DDSR is set and the
modem status interrupt is enabled, a modem status interrupt is
generated.
1: Change in state of DSR# input since last read
0: No change in state of DSR# input since last read
0
LPC: r/w
2
Trailing edge of the ring indicator (TERI) detector
TERI indicates that the RI# input to the chip has changed from a
low to a high level. When TERI is set and the modem status
interrupt is enabled, a modem status interrupt is generated. Not
supported.
0
LPC: r/w
3
Change in data carrier detect (DDCD) indicator
DDCD indicates that the DCD# input to the chip has changed
state since the last time it was read by the CPU. When DDCD is
set and the modem status interrupt is enabled, a modem status
interrupt is generated. Not supported.
0
LPC: r/w
4
Complement of the clear-to-send (CTS#) input
When the Asynchronous Communications Element (ACE) is in
diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to
MCR bit 1 (RTS#).
Ext.
LPC: r
5
Complement of the data set ready (DSR#) input
When the ACE is in the diagnostic test mode (LOOP [MCR4] =
1), this bit is equal to MCR bit 0 (DTR#).
Ext.
LPC: r
6
Complement of the ring indicator (RI#) input
When the ACE is in the diagnostic test mode (LOOP [MCR4] =
1), this bit is equal to MCR bit 2 (OUT1#). Not supported.
Ext.
LPC: r
7
Complement of the data carrier detect (DCD#) input
When the ACE is in the diagnostic test mode (LOOP [MCR4] =
1), this bit is equal to MCR bit 3 (OUT2#). Not supported.
Ext.
LPC: r
SB-ATCA7300 Installation and Use Guide
6-23
Maps and Registers
6.3.4.2.10 Scratch Register (SCR)
This 8-bit read/write register has no effect on the UART. It is intended as a
scratchpad register for use by the programmer.
Table 6-37 Scratch Register (SCR))
LPC IO Address: Base + 7
Bit
Description
Scratch Register (SCR)
The scratch register is an 8 bit register that is intended for the
7:0
programmer's use as a scratch pad; it temporarily holds data
without affecting any other ACE operation.
Default
Access
Undef.
LPC: r/w
6.3.4.3 Programmable Baud Rate Generator
The UART contains a programmable Baud Rate Generator that is capable of
taking the UART_CLK input and dividing it by any divisor from 1 to (216-1). The
output frequency of the Baud Rate Generator is 16 times the baud rate. Two 8-bit
latches store the divisor in a 16-bit binary format. These Divisor Latches must be
loaded during initialization to ensure proper operation of the Baud Rate
Generator.
If both Divisor Latches are loaded with 0, the 16X output clock is stopped. Upon
loading either of the Divisor latches, a 16-bit baud counter is immediately loaded.
This prevents long counts on initial load. Access to the Divisor latch can be made
with a word write.
The UART_CLK is the CLK_UART (48MHz) input divided by the pre-divider
set by the Super IO Configuration Register (Offset 0x29).
The baud rate of the data shifted in and out of the UART is given by:
Baud Rate = UART_CLK / (16X Divisor)
For example, if the pre-divider is 26, the UART_CLK is 1.8461538 MHz. When
the divisor is 12, the baud rate is 9600.
A Divisor value of 0 in the Divisor Latch Register is not allowed.
Table 6-38 Divisor Latch LSB Register (DLL), if DLAB=1
LPC IO Address: Base
Bit
Description
7:0 Divisor Latch LSB (DLL)
SB-ATCA7300 Installation and Use Guide
Default
Access
Undef.
LPC: r/w
6-24
Maps and Registers
Table 6-39 Divisor Latch MSB Register (DLM), if DLAB=1
LPC IO Address: Base + 1
Bit
Description
7:0 Divisor Latch MSB (DLM)
Default
Access
Undef.
LPC: r/w
6.4 FPGA Register Mapping
6.4.1 LPC I/O Register Map
The FPGA registers may be accessed using LPC I/O cycles in the I/O address
range REGISTERS. See Table 6-40 below. For LPC access, use the base address
0x600 and add the Address Offset. An LPC I/O write access to an address not
listed in this table or not marked with an “X” in the LPC I/O column is ignored. A
corresponding read access always returns zero.
6.4.2 IPMC SPI Register Map
The FPGA registers may be accessed via IPMC SPI transactions (with the signal
IPMC_SPI_SS_FPGA_ asserted). A SPI write access to an address not listed in
this table or not marked with an “X” in the IPMC SPI column is ignored. A
corresponding read access delivers always zero.
Table 6-40 FPGA Register Map Overview
Address Offset1 LPC I/O IPMC SPI
Description
0x00
x
x
Module Identification Register
0x01
x
x
FPGA Version Register
0x03 - 0x05
x
x
Serial Line Routing Registers
0x06
x
x
IPMC Power Level Register
0x08
x
x
SPD PROM MUX Control Register
0x10
x
x
BIOS Reset Source Register
0x11
x
x
Reset Mask Register
0x12
x
x
BIOS IPMC Watch dog timeout Register
0x13
x
-
BIOS Push Button Enable Register
0x14
x
x
OS Reset Source Register
0x15
x
x
OS IPMC Watch dog timeout Register
0x16
-
x
IPMC Watch dog timeout Register
0x17
-
x
IPMC Reset Source Register
0x18 - 0x19
x
-
RTM SPI Interface
SB-ATCA7300 Installation and Use Guide
6-25
Maps and Registers
Table 6-40 FPGA Register Map Overview (Continued)
Address Offset1 LPC I/O IPMC SPI
Description
0x20
x
-
External Interrupt Status Register
0x21
x
x
Processor Hot Status/Control Register
0x22
x
-
Telecom Status/Control Register
0x23 – 0x2D
x
-
Interrupt Mask and Map Registers
0x40
x
-
Flash Control and Status Register
0x41 – 0x42
x
-
Boot Flash Write Enable Registers
0x43
x
x
BIOS Boot Mode Register
0x45
x
x
SFMMOD Module Configuration Register
0x48
x
x
Update Channel Equalization Control
0x49
x
-
IPMC E-Keying Status Register
0x4A
x
x
IPMC E-Keying Control Register
0x4B
x
-
IPMC GPIO Register
0x50
x
x
LED Status and Control Register
0x58
x
x
NMI Status and Control Register
0x60 - 0x66
x
-
Telecom Clocking Registers
0x6F
x
x
Miscellaneous Status/Control Register
0x7D
x
x
LPC Scratch Register
0x7E
x
x
IPMC Scratch Register
0x7F
x
x
POST codes from host
1.For LPC I/O accesses add the LPC I/O Base Address 0x600
Note - For LPC I/O address 0x80 is used.
6.4.3 Module Identification Register
The Module Identification Register identifies the SB-ATCA7300 Blade.
Table 6-41 Module Identification Register
Address Offset: 0x00
Bit
Description
7:0 SB-ATCA7300 Blade Module Identification
SB-ATCA7300 Installation and Use Guide
Default Access
0x60
r
6-26
Maps and Registers
6.4.4 Version Register
The version register identifies the version of the FPGA bit stream. The initial
value starts at 0x01 and is incremented with each new release.
Table 6-42 Version Register
Address Offset: 0x01
Bit
Description
Default
Access
7:0 Specifies FPGA version 1 (Initial Value) r
6.4.5 Serial Redirection Control Register
The BIOS sets the corresponding bit, which is used for serial port redirection. The
IPMC uses this information to route the appropriate port to the serial IPMC
interface in case of SOL.
Note - The BIOS should never set both status bits.
Table 6-43 Serial Redirection Control Register
Address Offset: 0x03
Bit
Description
Default
Access
0
COM1 used for serial redirection:
0: COM1 not used for serial redirection
1: COM1 used for serial redirection
0
LPC: r/w
IPMC: r
COM2 use for serial redirection
0: COM2 not used for serial redirection
1: COM2 used for serial redirection
0
LPC: r/w
IPMC: r
0
r
1
7:2 Reserved
6.4.6 Serial Over LAN (SOL) Control Register
The IPMC software can route serial data from serial port 1 (COM1) or serial port
2 (COM2) to the IPMC. This register identifies which serial port is redirected.
SB-ATCA7300 Installation and Use Guide
6-27
Maps and Registers
Note - When both control bits are enabled, bit 1 is ignored.
Table 6-44 Serial over LAN Control Register
Address Offset: 0x04
Bit
Description
Default
Access
0
SOL over COM1 enable:
LPC: r/w
0: disabled
PWR_GOOD: 0
IPMC: r
1: enabled. COM1 is forwarded to IPMC
1
SOL over COM2 enable:
LPC: r/w
0: disabled
PWR_GOOD: 0
IPMC: r
1: enabled. COM2 is forwarded to IPMC
7:2 Reserved
0
r
6.4.7 Serial Line Routing Register
This register contains the inverted level of signals SEL_SERIAL[1:0], which are
controlled by blade switches SW2.2 and SW2.1 (see section 3.4 “Board Control
Switch Settings” on page 3-5). The switch settings may be overwritten by IPMC
software.
Table 6-45 Serial Line Routing Register
Address Offset: 0x05
Bit
Description
Default
Access
Ext.
00: COM1 to Front Panel and COM2 to RTM
01: COM1 to RTM and COM2 to Front Panel
1:0
10: Reserved
11: Reserved
7:2 Reserved
(SW2.21, SW2.1)
00: (OFF,OFF)
r
01: (OFF,ON)
10: (ON,OFF)
11: (ON,ON)
0
r
1.The Signal SEL_SERIAL[1] is reserved. Switch SW2.2 should always be
“OFF” for normal oepration, and the IPMC should not override the default
value.
SB-ATCA7300 Installation and Use Guide
6-28
Maps and Registers
6.4.8 IPMC Power Level Register
This register is used to set the power level at which the blade runs. See section
2.2.1 “Processor Speeds” on page 2-2 for its effect.
Table 6-46 IPMC Power Level Register
Address Offset: 0x06
Bit
7:0
Description
IPMC Power Level. IPMC writes a value,
which correspond to a defined power level.
Default
Access
PWR_GOOD:0
IPMC: r/w
LPC: r
6.4.9 SPD PROM MUX Control Register
Table 6-47 SPD PROM MUX Control Registerr
Address Offset: 0x08
Bit
Description
Default
Access
0
Signal Level of SMBUS_MUX0_IN
Ext.
r
1
Signal Level of SMBUS_MUX1_IN
Ext.
r
2
Signal Level of BIOS_POST_CMPLT_IN
Ext.
r
3
Reserved
0
r
4
SMBUS_MUX0_OUT.1
0: SMBUS_MUX0_OUT is driven low
1: SMBUS_MUX0_OUT is driven high
Ext.:
SMBUS_MUX0_IN
LPC: r
IPMC: r/w
5
SMBUS_MUX1_OUT. 2
0: SMBUS_MUX1_OUT is driven low
1: SMBUS_MUX1_OUT is driven high
Ext.:
SMBUS_MUX1_IN
LPC: r
IPMC: r/w
6
BIOS_POST_CMPLT_OUT. 3
0: BIOS_POST_CMPLT_IN is driven low
1: BIOS_POST_CMPLT_IN is driven high
7
SPD PROM MUX locked by BIOS
1: The output signals XXX_OUT are directly
controlled by the corresponding input signals
XXX_IN.
0: The output signals XXX_OUT are
controlled by register bits 4 to 6.
Ext.:
LPC: r
BIOS_POST_CMPLT_IN IPMC: r/w
0
LPC: r/w
IPMC: r
1.When the SPD PROM MUX is locked by BIOS (Bit 7 is set) the signal level of SMBUS_MUX0_IN is
read.Write transactions are ignored.
2.When the SPD PROM MUX is locked by BIOS (Bit 7 is set) the signal level of SMBUS_MUX1_IN is
read. Write transactions are ignored.
SB-ATCA7300 Installation and Use Guide
6-29
Maps and Registers
3.When the SPD PROM MUX is locked by BIOS (Bit 7 is set) the signal level of
BIOS_POST_CMPLT_IN is read. Write transactions are ignored.
6.4.10 Reset Registers
6.4.10.1 BIOS Reset Source Register
The BIOS Reset Source Register indicates the cause of the most recent reset. A
one in a register bit indicates that the associated reset has occurred. If more than
one reset occurs from different sources without clearing the corresponding
register bits, it is not possible to determine the most recent reset cause as more
than one bit will be set. This will also happen when two or more reset sources go
active at the same time.
Note - The OS should never write to this register.
Table 6-48 BIOS Reset Source Register
Address Offset: 0x10
Bit
Description
Default
Access
PWR_GOOD:1
LPC: r/w1c
IPMC: r
0
PWR_GOOD Payload Power-on reset
1: Reset occurred
1
XDP0_BRD_PWROK CPU debugger system reset
request
1: Reset occurred
2
PB_RST_ Front panel push button reset
1: Reset occurred
PWR_GOOD:0
LPC: r/w1c
IPMC: r
3
XDP1_DBRST_ CPU debugger reset
1: Reset occurred
PWR_GOOD:0
LPC: r/w1c
IPMC: r
4
RTM_PB_RST_ Reset key from RTM
1: Reset occurred
PWR_GOOD:0
LPC: r/w1c
IPMC: r
5
CPU_RST_ CPU Reset signal from CPU
1: Reset occurred
PWR_GOOD:0
LPC: r/w1c
IPMC: r
6
XDP0_DBRST_ CPU Debugger reset
1: Reset occurred
PWR_GOOD:0
LPC: r/w1c
IPMC: r
7
IPMC_RST_ REQ_ Payload reset from IPMC
1: Reset occurred
PWR_GOOD:0
LPC: r/w1c
IPMC: r
SB-ATCA7300 Installation and Use Guide
LPC: r/w1c
PWR_GOOD:0 IPMC: r
6-30
Maps and Registers
6.4.10.2 Reset Mask Register
The reset mask register allows or disallows a reset cause to assert the reset signal.
Only Push Button reset requests are affected by the reset mask register. The
register default values are latched when PWR_GOOD is asserted. This register
can be read or written by the host CPU. A one in the register bit indicates that the
associated reset is enabled. A zero indicates that the associated reset source is
masked.
Table 6-49 Reset Mask Register
Address Offset: 0x11
Bit
Description
Default
Access
0
Reserved
PWR_GOOD:1 r
1
Spare switch SW3.4
PWR_GOOD:0 r
2
PB_RST_ Front panel push button reset
PWR_GOOD:0 r/w
1: enabled
0: disabled
3
Reserved
PWR_GOOD:0 r
4
RTM_PB_RST_ Reset key at RTM
1: enabled
0: disabled
PWR_GOOD:0 r/w
7:5 Reserved
PWR_GOOD:0 r
6.4.10.3 BIOS IPMC Watchdog Timeout Register
When one of the IPMC Watchdog Timeout register bits is set, the corresponding
BIOS IPMC Watchdog Timeout bit is set. The BIOS clears this status bit, writing
one.
Note - The OS should never write to this register.
Table 6-50 BIOS IPMC Watchdog Timeout Register
Address Offset: 0x12
Bit
Description
Default
Access
0
BIOS IPMC Watchdog Timeout:
LPC: r/w1c
PWR_GOOD:0
1: IPMC Watchdog Timeout occurred
IPMC: r
1
BIOS IPMC Pre-Timeout
1: IPMC Pre-Timeout occurred
7:2 Reserved
SB-ATCA7300 Installation and Use Guide
PWR_GOOD:0
0
LPC: r/w1c
IPMC: r
r
6-31
Maps and Registers
6.4.10.4 BIOS Push Button Enable Register
The BIOS must write to this register to enable the Front Panel push button reset,
the RTM push button reset, and the IPMC reset.
Note - After a timeout of 8 seconds, the resets are armed again in any case.
Table 6-51 BIOS Push Button Enable Register
Address Offset: 0x13
Bit
Description
Default Access
7:0 BIOS Push Button Enable Register
-
LPC: w
6.4.10.5 OS Reset Source Register
The OS Reset Source Register identifies the cause of the most recent reset, just as
in the BIOS Reset Source Register. A one in a register bit indicates that the
corresponding reset has occurred. If more than one reset occurs from different
causes without clearing the corresponding register bits, it is not possible to
determine the most recent reset cause as more than one bit will be set. This will
also happen when two or more reset sources go active at the same time.
Note - The BIOS should never write to this register.
Table 6-52 Reset Source Register
Address Offset: 0x14
Bit
Description
Default
Access
0
PWR_GOOD Payload Power-on reset
1: Reset occurred
PWR_GOOD:1
LPC: r/w1c
IPMC: r
1
XDP0_BRD_PWROK CPU debugger system reset
request
1: Reset occurred
PWR_GOOD:0
LPC: r/w1c
IPMC: r
2
PB_RST_ Front panel push button reset
1: Reset occurred
PWR_GOOD:0
LPC: r/w1c
IPMC: r
3
XDP1_DBRST_ CPU debugger reset
1: Reset occurred
PWR_GOOD:0
LPC: r/w1c
IPMC: r
4
RTM_PB_RST_ Reset key from RTM
1: Reset occurred
PWR_GOOD:0
LPC: r/w1c
IPMC: r
SB-ATCA7300 Installation and Use Guide
6-32
Maps and Registers
Table 6-52 Reset Source Register (Continued)
Address Offset: 0x14
Bit
Description
Default
Access
5
CPU_RST_ CPU Reset signal from CPU
1: Reset occurred
PWR_GOOD:0
LPC: r/w1c
IPMC: r
6
XDP0_DBRST_ CPU debugger reset
1: Reset occurred
PWR_GOOD:0
LPC: r/w1c
IPMC: r
7
IPMC_RST_ REQ_ Payload reset from IPMC
1: Reset occurred
PWR_GOOD:0
LPC: r/w1c
IPMC: r
6.4.10.6 OS IPMC Watchdog Timeout Register
When the IPMC Watchdog Timeout bit of IPMC Watchdog Timeout Register is
set, the OS IPMC Watchdog Timeout bit is set. The OS clears this status bit by
writing one.
Note - The BIOS should never write to this register.
Table 6-53 OS IPMC Watchdog Timeout Register
Address Offset: 0x15
Bit
Description
Default
Access
0
OS IPMC Watchdog Timeout:
LPC: r/w1c
PWR_GOOD:0
1: IPMC Watchdog Timeout occurred
IPMC: r
1
OS IPMC Pre-Timeout
1: IPMC Pre-Timeout occurred
7:2 Reserved
PWR_GOOD:0
0
LPC: r/w1c
IPMC: r
r
6.4.10.7 IPMC Watchdog Timeout Register
The IPMC sets the corresponding bit to signal an IPMC watchdog timeout event.
When the IPMC Watchdog Timeout bit is set from low to high, the corresponding
bits in the registers in Table 6-54 and Table 6-53 are set.
SB-ATCA7300 Installation and Use Guide
6-33
Maps and Registers
Note - The IPMC must clear the IPMC watchdog timeout bit to arm IPMC
watchdog timeout event recognition.
Table 6-54 IPMC Watchdog Timeout Register
Address Offset: 0x16
Bit
Description
Default
Access
0
IPMC Watchdog Timeout:
0: No IPMC Watchdog Timeout
PWR_GOOD:0 IPMC: r/w
1: IPMC Watchdog Timeout occurred
1
IPMC Pre-Timeout
0: No IPMC Pre-Timeout
1: IPMC Pre-Timeout occurred
PWR_GOOD:0 IPMC: r/w
7:2 Reserved
0
r
6.4.10.8 IPMC Reset Source Register
The IPMC Reset Source Register identifies the cause of the most recent reset. A
one in the register bit indicates that the corresponding reset has occurred. If more
than one reset occurs from different sources without clearing the corresponding
register bits, it is not possible to determine the most recent reset cause as more
than one bit will be set. This will also happen when two or more reset sources go
active at the same time.
Table 6-55 IPMC Reset Source Register
Address Offset: 0x17
Bit
Description
Default
Access
0
PWR_GOOD Payload Power-on reset
1: Reset occurred
PWR_GOOD:1 IPMC: r/w1c
1
XDP0_BRD_PWROK CPU debugger system reset
request
1: Reset occurred
PWR_GOOD:0 IPMC: r/w1c
2
PB_RST_ Front panel push button reset
1: Reset occurred
PWR_GOOD:0 IPMC: r/w1c
3
XDP1_DBRST_ CPU debugger reset
1: Reset occurred
PWR_GOOD:0 IPMC: r/w1c
4
RTM_PB_RST_ Reset key at RTM
1: Reset occurred
PWR_GOOD:0 IPMC: r/w1c
5
CPU_RST_ CPU Reset signal from CPU
1: Reset occurred
PWR_GOOD:0 IPMC: r/w1c
SB-ATCA7300 Installation and Use Guide
6-34
Maps and Registers
Table 6-55 IPMC Reset Source Register (Continued)
Address Offset: 0x17
Bit
Description
Default
Access
6
XDP0_DBRST_ CPU debugger reset
1: Reset occurred
PWR_GOOD:0 IPMC: r/w1c
7
IPMC_RST_ REQ_ Payload reset from IPMC
1: Reset occurred
PWR_GOOD:0 IPMC: r/w1c
6.4.11 RTM SPI Interface Registers
The signals RTM_SPI_SCK, RTM_SPI_SS_, RTM_SPI_MISO and
RTM_SPI_MOSI. are used to support a SPI master protocol. The signal
RTM_SPI_MISO is used to signal the a RTM interrupt. See section 6.4.12.2
“External Interrupt Status Register” on page 6-36.
A write access to the RTM SPI Address/Command Register starts the SPI
transaction. The write access terminates when the SPI transaction has finished.
Table 6-56 RTM SPI Address/Command Register
Address Offset: 0x18
Bit
0
Description
Default
Access
0
IPMC: r/w
Command bit
0: Write
1: Read
7:1 RTM SPI Address bits [6:0] PWR_GOOD:0 IPMC: r/w
A write access to the RTM SPI Address/Command Register with the Command
Bit 0 (Write) set starts a SPI write transaction. The RTM SPI Write Register
content is written to the SPI device.
Table 6-57 RTM SPI Write Register
Address Offset: 0x19
Bit
Description
7:0 RTM SPI write data
SB-ATCA7300 Installation and Use Guide
Default Access
-
LPC: w
6-35
Maps and Registers
A write access to the RTM SPI Address/Command Register with the Command
Bit 1 (Read) set starts a SPI read transaction. The RTM SPI Read Register
contains the data read from the SPI device.
Table 6-58 RTM SPI Read Register
Address Offset: 0x19
Bit
Description
Default Access
7:0 RTM SPI read data
-
LPC: r
6.4.12 Interrupt Control and Status Registers
The interrupt status registers described in this section indicate the status of the
interrupt input signals. They are all read-only registers. When an interrupt is
active, the corresponding status bit is read 1. Write access to these register bits
does not have any effect.
6.4.12.1 RTM Interrupt Status Register
The RTM Interrupt Status Register will be located in the RTM SPI address space.
The host can access the RTM register using the RTM SPI Master Interface.
No RTM interrupt sources are defined yet.
6.4.12.2 External Interrupt Status Register
Table 6-59 External Interrupt Status Register
Address Offset: 0x20
Bit
Signal1
Description
Default Access
0
IPMC2HOST_INT_ IPMC signals interrupt
Ext.
LPC: r
1
LM75_INT_
Interrupt input from payload temp sensor
Ext.
LPC: r
2
SFMMOD_IRQ_
Interrupt from SFMMOD Module
Ext.
LPC: r
3
THERM_SEN0
IRQ request from 82599 therm sensor 0
Ext.
LPC: r
4
THERM_SEN1
IRQ request from 82599 therm sensor 1
Ext.
LPC: r
5
THERM_ALERT_
IRQ request from IOH therm sensor
Ext.
LPC: r
6
APB_ALARM
An 48V input alarm (low voltage, etc)
Ext.
LPC: r
SB-ATCA7300 Installation and Use Guide
6-36
Maps and Registers
Table 6-59 External Interrupt Status Register (Continued)
Address Offset: 0x20
Signal1
Bit
7
Description
RTM_SPI_MISO
Default Access
RTM interrupt sources
0: RTM_SPI_MISO is high. No RTM
interrupt.
1: RTM_SPI_MISO is low. One or more
RTM interrupt sources are active. When
the RTM SPI Master interface is active
the current level is latched.
Ext.
LPC: r
Default
Access
1.When an interrupt is active the corresponding status bit is read 1.
6.4.12.3 Processor Hot Status/Control Register
Table 6-60 Processor Hot Status/Control Register
Address Offset: 0x21
Bit
Signal
Description
0
CPU0_PRCHT_ IPMC signals interrupt
Ext.
LPC: r
1
CPU1_PRCHT_ Interrupt input from payload temp sensor
Ext.
LPC: r
2
CPU0_PRCHT_ Interrupt from SFMMOD Module
0
LPC: r/w
3
CPU1_PRCHT_ IRQ request from 82599 therm sensor 0
0
LPC: r/w
-
r
7:4 -
Reserved
6.4.12.4 Telecom Status/Control Register
Table 6-61 Telecom Status/Control Register
Address Offset: 0x22
Bit
Signal
0
CH1_CLK1A_IN
1
CH1_CLK1B_IN
2
Description
Default
Access
Clock CLK1A of Chassis 1 has changed state
from static to toggle or toggle to static.
0
LPC: r/w1c
Clock CLK1A of Chassis 1 has changed state
from static to toggle or toggle to static.
0
LPC: r/w1c
-
Telecom timeout occurred
0
LPC: r/w1c
3
-
Reserved
-
r
7:4
-
Counter of Telecom timeouts that have
occurred. Clearing bit 2 of this register also
clears this counter.
0
LPC: r
SB-ATCA7300 Installation and Use Guide
6-37
Maps and Registers
6.4.12.5 Interrupt Mask and Map Registers
Each interrupt signal of the External Interrupt Status Register, Processor Hot
Status/Control Register or Telecom Status/Control Register can be mapped to one
of the CPU_IRQ_X_ interrupts or any IRQ Frame number of the serialized IRQ
protocol.
Multiple interrupt sources may share the same CPU_IRQ_X_ or the same IRQ
Frame. In this case all interrupt sources need to be of type “level active low”.
Each Interrupt source has an Interrupt Mask and Map Register. See the table
below.
Table 6-62 Address Map of Interrupt Mask and Map Registers
Interrupt Source
Description
Address
Offset of
Interrupt
Mask
APB_ALARM
A 48V input alarm (low voltage, etc)
0x29
CPU0_PRCHT_ CPU0
“Processor hot” interrupt
0x2B
CPU1_PRCHT_ CPU1
“Processor hot” interrupt
0x2C
IPMC2HOST_INT_
IPMC signals interrupt
0x23
LM75_INT_
Interrupt input from payload temp sensor
0x24
RTM_SPI_MISO
RTM interrupt sources
0x2A
SFMMOD_IRQ_
Interrupt from SFMMOD Module
0x25
Telecom Status/
Control Register
Active when at least one Status bit (bit 0,
1 or 2) is set.
0x2D
THERM_ALERT_
IRQ request from IOH Thermo-sensor
0x28
THERM_SEN0
IRQ request from 82599 Thermsen0
0x26
THERM_SEN1
IRQ request from 82599 Thermsen1
0x27
SB-ATCA7300 Installation and Use Guide
6-38
Maps and Registers
Each Interrupt Mask and Map Register has the same layout. See the table below
for more details.
Table 6-63 Interrupt Mask and Map Registers
Address Offset: 0x23 – 0x2D
Bit
Description
Default
Access
IRQ Frame Number of Serialized IRQ protocol. Any
valid Frame number enables the interrupt.
0x00: Interrupt is mapped to CPU_IRQ_X_. See bits 7:5
of this register.
0x01: Frame number 1. IRQ0
0x02: Frame number 2. IRQ1
0x03: Frame number 3. IRQ2 (SMI_)
0x04: Frame number 4. IRQ3
0x05: Frame number 5. IRQ4
0x06: Frame number 6. IRQ5
0x07: Frame number 7. IRQ6
0x08: Frame number 8. IRQ7
0x09: Frame number 9. IRQ8
4:0 0x0A: Frame number 10. IRQ9
0x0B: Frame number 11. IRQ1
0x0C: Frame number 12. IRQ11
0x0D: Frame number 13. IRQ12
0x0E: Frame number 14. IRQ13
0x0F: Frame number 15. IRQ14
0x10: Frame number 16. IRQ15
0x11: Frame number 17. IOCHK_
0x12: Frame number 18. INTA_
0x13: Frame number 19. INTB_
0x14: Frame number 20. INTC_
0x15: Frame number 21. INTD_
0x16 – 0x1F: Frame number 22-31. IRQ Frame Number
not valid. Value is ignored.
0
LPC:r/ w
An external Interrupt Signal CPU_IRQ_X_ is used.
Only used when IRQ Frame Number is 0x00.
0x0: Interrupt is masked (disabled).
0x1: Map Interrupt to CPU_IRQ_A_
0x2: Map Interrupt to CPU_IRQ_B_
7:5
0x3: Map Interrupt to CPU_IRQ_C_
0x4: Map Interrupt to CPU_IRQ_D_
0x5: Map Interrupt to CPU_IRQ_F_
0x6: Map Interrupt to CPU_IRQ_G_
0x7: Map Interrupt to CPU_IRQ_H_
0
LPC:r/ w
SB-ATCA7300 Installation and Use Guide
6-39
Maps and Registers
6.4.13 Flash Status and Write Protection Registers
The Flash Status Register indicates the actual setting of mechanical switches
SW1.1 (Signal BOOT_DEF_WP_), SW1.2 (Signal BOOT_REC_WP_), SW1.3
(Signal BOOT_TSOP), SW3.1 (Signal BOOT_SEL_EN_) and SW3.2 (Signal
BOOT_DEFAULT) and the status of IPMC signal BOOT_SELECT. (See section
3.4 “Board Control Switch Settings” on page 3-5 for information on the switches.)
Table 6-64 Flash Status Register
Address Offset: 0x040
Bit
Description
Default
Access
0
Default Boot SPI Flash Write protection Status. See Table
6-65 on page 6-41 for how to disable write protection.
0: Default Boot SPI Flash is unprotected
1: Default Boot SPI Flash is protected
Ext.
BOOT_DEF_WP_1
0: SW1.1 OFF
1: SW1.1 ON
LPC: r
1
Recovery Boot SPI Flash Write protection Status. See Table
6-66 on page 6-41 for how to disable write protection.
0: Recovery Boot SPI Flash is unprotected
1: Recovery Boot SPI Flash is protected
Ext.
BOOT_REC_WP_2
0: SW1.2 OFF
1: SW1.2 ON
LPC: r
0
LPC: r
3:2 Reserved
4
TSOP or PLCC Boot select. Signal BOOT_TSOP.
0: TSOP selected
1: PLCC selected
Ext.
0: SW1.3 OFF
1: SW1.3 ON
LPC: r
5
Manual Boot Flash select enable. Signal BOOT_SEL_EN_. Ext.
0: Signal BOOT_SELECT selects active boot flash
0: SW3.1 OFF
1: Switch SW3.2 selects the active Boot Flash.
1: SW3.1 ON
LPC: r
6
Manual Boot Flash select. Signal BOOT_DEFAULT. Used
when SW3.1 is ON:
0: Selects Default Boot SPI Flash.
1: Selects Recover Boot SPI Flash.
Ext.
0: SW3.2 OFF
1: SW3.2 ON
LPC: r
7
IPMC signal BOOT_SELECT. Boot Flash Select.
0: Selects Default Boot SPI Flash
1: Selects Recovery Boot SPI Flash
Ext.
LPC: r
1.The default is latched from SW1.1 when ICH_PLTRST_ is deasserted.
2.The default is latched from SW1.2 when ICH_PLTRST_ is deasserted
6.4.13.1 Flash Write Protection Registers
The write protection status signals for the Boot SPI flashes are determined by
external switch settings SW1.1 and SW1.2. Software can overwrite this write
SB-ATCA7300 Installation and Use Guide
6-40
Maps and Registers
protection status by writing a “magic word” to the Boot SPI Flash Write Enable
Registers.
Table 6-65 Default Boot SPI Flash Write Enable
Address Offset: 0x41
Bit
Description
Default Access
Default Boot SPI Flash image write enable/disable.
7:0 A write of value 0xC3 enables write access to the Boot Block.
All other values disable write access to the Boot Block.
-
LPC: w
Table 6-66 Recovery Boot SPI Flash Write Enable
Address Offset: 0x42
Bit
Description
Default Access
Recovery Boot SPI Flash image enable/disable.
7:0 A write of value 0xC3 enables write access to the image.
All other values disable write access to the image.
-
LPC: w
6.4.14 BIOS Boot Mode Register
Table 6-67 BIOS Boot Mode Register
Address Offset: 0x43
Bit
Description
The switch signals SW_BIOS[1:0] controls the BIOS
Boot Mode:
0:1
7:2 Reserved
SB-ATCA7300 Installation and Use Guide
Default
Access
-Ext.
1: SW4.3 ON r
0: SW4.3 OFF
Ext.
1: SW4.4 ON
0: SW4.4 OF
r
0
r
6-41
Maps and Registers
6.4.15 SFMMOD Module Configuration Register
Table 6-68 SFMMOD Module Configuration Register
Address Offset: 0x45
Bit
Description
Default
Access
3:0 Control output signals SFMMOD_CONF[3:0] PWR_GOOD:0
LPC: r/w
IPMC: r
7:4 Reserved
r
0
6.4.16 IPMC E-Keying Status Register
Table 6-69 IPMC E-Keying Status Register
Address Offset: 0x49
Bit
Description
4:0 IPMC_UPDCH_[4:0]. IPMC electronic key signals
Default Access
Ext.
LPC: r
5
IPMC_FAB1_10G_SEL_
Ext.
LPC: r
6
IPMC_FAB2_10G_SEL_
Ext.
LPC: r
7
Reserved
0
r
6.4.17 IPMC E-Keying Control Register
Table 6-70 IPMC E-Keying Control Register
Address Offset: 0x4A
Bit
Description
Default
Access
0
Shut off the Intel 82567 Front Panel GB Eth PHY.
0: FP_LAN_DISABLE_ driven low. Disabled
1: FP_LAN_DISABLE_ driven high. Enabled
1
LPC: r/w
IPMC: r/w
1
Shut off the Intel I350 BASE-Eth Controller
0: BASEIF_DEV_OFF_ driven low. Device is off
1: BASEIF_DEV_OFF_ driven high. Device is on
1
LPC: r/w
IPMC: r/w
2
Enable/Disable Base-IF#0.
0: BASEIF_LAN0_DIS_ driven low. Disabled
1: BASEIF_LAN0_DIS_ driven high. Enabled
1
LPC: r/w
IPMC: r/w
3
Enable/Disable Base-IF#1.
0: BASEIF_LAN1_DIS_ driven low. Disabled
1: BASEIF_LAN1_DIS_ driven high. Enabled
1
LPC: r/w
IPMC: r/w
SB-ATCA7300 Installation and Use Guide
6-42
Maps and Registers
Table 6-70 IPMC E-Keying Control Register
Address Offset: 0x4A
Bit
Description
Default
Access
4
Enable/Disable Fabric-IF#0.
0: FABIF_LAN0_DIS_ driven low. Disabled
1: FABIF_LAN0_DIS_ driven high. Enabled
1
LPC: r/w
IPMC: r/w
5
Enable/Disable Fabric-IF#1.
0: FABIF_LAN1_DIS_ driven low. Disabled
1: FABIF_LAN1_DIS_ driven high. Enabled
1
LPC: r/w
IPMC: r/w
6
Reserved
0
r
7
Disable/Enable USB Port 7/8 to RTM.
0: RTMUSB_ENABLE_ driven low. Enabled
1: RTMUSB_ENABLE_ driven high. Disabled
PWR_GOOD: 1
LPC: r/w
IPMC: r/w
6.4.18 IPMC GPIO Register
Table 6-71 IPMC GPIO Register
Address Offset: 0x4B
Bit
Description
Default Access
0
IPMC_GPIO1
Ext.
LPC: r
1
IPMC_GPIO2
Ext.
LPC: r
2
IPMC_GPIO2
Ext.
LPC: r
7:3 Reserved
-
6.4.19 LED Status and Control Register
Table 6-72 LED Status and Control Register
Address Offset: 0x50
Bit
Description
Default
Access
0
Control green LED output signal of U3
0: LED_GREEN_ is driven high.
1: LED_GREEN_ is driven low.
0
LPC: r/w
IPMC: r
1
Control red LED output signal of U3
0: LED_RED_ is driven high.
1: LED_RED_ is driven low.
0
LPC: r/w
IPMC: r
2
Control red LED output signal of U1
0: LED_USER1_ is driven high.
1: LED_USER1 is driven low.
0
LPC: r/w
IPMC: r
SB-ATCA7300 Installation and Use Guide
6-43
Maps and Registers
Table 6-72 LED Status and Control Register (Continued)
Address Offset: 0x50
Bit
3
Description
Default
Access
0
LPC: r/w
IPMC: r
0
r
Control red LED output signal of U2
0: LED_USER2_ is driven high.
1: LED_USER2 is driven low.
5:4 Reserved
6
Signal level of ME_DISABLE_
(Connected to SW1.4 and ICH10 GP33)
Ext.
r
7
FPGA PROM select signal FPGA_PROM_SEL
controlled by IPMC
Ext.
r
6.4.20 NMI Status and Control Register
Table 6-73 NMI Status and Control Register
Address Offset: 0x58
Bit
0
1
2
3
Description
Diagnostic NMI Status
Diagnostic NMI Status
Watchdog NMI Status
Watchdog NMI Status
7:4 Reserved
SB-ATCA7300 Installation and Use Guide
Default
Access
0
LPC: r/w1c
IPMC: r/w
0
LPC: r
IPMC: r/w
0
LPC: r/w1c
IPMC: r/w
0
LPC: r
IPMC: r/w
0
r
6-44
Maps and Registers
6.4.21 Telecom Clock Supervision Registers
6.4.21.1 Telecom Clocking Status Registers
The telecom backplane clocking status register indicates when the backplane
input clock signals are toggling.
Table 6-74 Telecom Backplane Clocking Status Register
Address Offset: 0x66
Bit
Description
Default
Access
0
0: CH1_CLK1A_IN is static or period is not in the correct range.
PWR_GOOD:0 LPC: r
1: CH1_CLK1A_IN is toggling
1
0: CH1_CLK1B_IN is static or period is not in the correct range.
1: CH1_CLK1B_IN is toggling
7:2
PWR_GOOD:0 LPC: r
Reserved
0
r
Table 6-75 Telecom Backplane Clocking Latch Register
Address Offset: 0x67
Bit
Description
Default Access
7:0
Latch clock period measurements for CH1_CLK1A and CH1_CLK1B.
Write data is discarded.
-
LPC: w
The Clock period of CH1_CLK1A is measured periodically. The result of the
measurement (number of LPC clock cycles) is latched with a write access to the
Telecom Backplane Clocking Latch Register. The 16 bit value is stored in the
registers Telecom CH1_CLK1A Clock Period MSB Register and Telecom
CH1_CLK1A Clock Period LSB Register . When the clock is static or the period
is higher than a 16 bit value the result is always 0xFFFF.
Table 6-76 Telecom CH1_CLK1A Clock Period MSB Register
Address Offset: 0x61
Bit
Description
Default
Access
7:0 MSB of CH1_CLK1A clock period PWR_GOOD: 0xFF LPC: r
Table 6-77 Telecom CH1_CLK1A clock period LSB Register
Address Offset: 0x60
Bit
Description
Default
Access
7:0 LSB of CH1_CLK1A clock period PWR_GOOD: 0xFF LPC: r
SB-ATCA7300 Installation and Use Guide
6-45
Maps and Registers
The Clock period of CH1_CLK1B is measured periodically. The result of the
measurement (number of LPC clock cycles) is latched with a write access to the
Telecom Backplane Clocking Latch Register. The 16 bit value is stored in the
register Telecom CH1_CLK1B Clock Period MSB Register and Telecom
CH1_CLK1B Clock Period LSB Register. When the clock is static or the period is
higher than a 16 bit value the result is always 0xFFFF.
Table 6-78 Telecom CH1_CLK1B Clock Period MSB Register
Address Offset: 0x63
Bit
Description
Default
Access
7:0 MSB of CH1_CLK1B clock period PWR_GOOD: 0xFF LPC: r
Table 6-79 Telecom CH1_CLK1B Clock Period LSB Register
Address Offset: 0x62
Bit
Description
7:0 LSB of CH1_CLK1B clock period
Default
Access
PWR_GOOD: 0xFF LPC: r
6.4.21.2 Telecom Timer Registers
The Telecom Timer is decremented on each rising edge of the input clock.
The Telecom Timer is disabled when loaded with 0 (both the MSB and LSB
Timer registers are 0). The Telecom Timer value can be set to values from 1 to
65535, which allows timeout values from 125 usec to 8.191875 sec (based on an 8
KHz input clock).
When a timeout occurs (the timer is 0), the timeout bit is set. See Table 6-61
Telecom Status/Control Register. The Telecom Timer is reloaded with the timer
start value stored in the Telecom Timer LSB Register and Telecom Timer MSB
Register and armed again, waiting for a rising edge of the input clock.
A write access to the Telecom Timer MSB Register loads the 16 bit Telecom
timer with the write data from the current access and the content of the Telecom
Timer LSB Register.
Table 6-80 Telecom Timer MSB Register
Address Offset: 0x65
Bit
Description
7:0 MSB of Telecom Timer start value
SB-ATCA7300 Installation and Use Guide
Default
Access
PWR_GOOD: 0 LPC: r/w
6-46
Maps and Registers
Table 6-81 Telecom Timer LSB Register
Address Offset: 0x64
Bit
Description
Default
7:0 LSB of Telecom Timer start value
Access
PWR_GOOD: 0 LPC: r/w
6.4.22 Miscellaneous Status/Control Registers
Table 6-82 CPLD Version and Spare Signal Status Register
Address Offset: 0x6F
Bit
Description
Default Access
2:0 CPLD Version. The CPLD uses the signals CPLD_SPARE[3:1]
Ext.
r
3
Ext.
r
0
r
CPLD_SPARE[4]
7:4 Reserved
6.4.23 Scratch Registers
Table 6-83 LPC Scratch Register
Address Offset: 0x45
Bit
Description
Default
7:0 LPC Scratch bits PWR_GOOD:0
Access
LPC: r/w
IPMC: r
Table 6-84 IPMC Scratch Register
Address Offset: 0x45
Bit
Description
Default
7:0 IPMC Scratch bits PWR_GOOD:0
SB-ATCA7300 Installation and Use Guide
Access
LPC: r
IPMC: r/w
6-47
Maps and Registers
SB-ATCA7300 Installation and Use Guide
6-48
7 Serial Over LAN
7.1 Overview
Serial Over LAN (SOL) is a IPMI mechanism that you can use to redirect the
serial console of the SB-ATCA7300 blade to an IPMI session that is accessible
over the network. (This is the only IPMI v2 feature supported by the blade.)
The SB-ATCA7300 blade’s IPMC is used to establish and manage the SOL
session. SOL access is only available through the base network interfaces. The
sideband port of the Intel I350 Powerville Ethernet device (in pass-through mode)
is used for SOL sessions.
You must first configure the IPMC, as it does not have an IP address, user name or
password by default.
The board’s SOL data path goes from the CPU to the FPGA serial port, then to the
IPMC (H8S chip), then to the Ethernet NC-SI interface and the base network.
CPU
LPC
F
a
c
e
p
l
a
t
e
QPI
FPGA
Serial
Intel IOH36D
Serial
PCI Express
H8S
I2C
Intel I350
(Powerville)
Ethernet
Serial
Figure 7-1 SOL On-Blade Data Path
Note - Only a blade console data rate of 9600 baud is supported.
You can configure the IPMC SOL parameters using direct IPMI commands or by
using an open source IPMI utility such as ipmitool or OpenIPMI.
7.1.1 SOL Configuration Steps
There are three different sets of SOL parameters that can be configured.
 SOL facility availability and configuration


The user accounts used for SOL access
The IPMC network configuration
The configuration of these parameters are discussed in the following sections.
SB-ATCA7300 Installation and Use Guide
7-1
Serial Over LAN
7.2 Installing ipmitool
You can download ipmitool from http://sourceforge.net/projects/ipmitool. At the
time this manual was published, the current version of ipmitool was 1.8.11.
Documentation for ipmitool is also available at this site.
To install ipmitool, do the following.
1. Download the ipmitool tar file from http://sourceforge.net/projects/
ipmitooll to your blade or workstation.
2. Extract the tar file.
prompt> tar -xjf ipmitool-1.8.11.tar.bz2
prompt> bzcat ipmitool-1.8.11.tar.bz2 | tar -xf -
3. Change to the directory into which you have extracted ipmitool.
prompt> cd <path>/ipmitool-1.8.11
4. Build ipmitool. It is installed by default in /usr/local/bin.
prompt> ./configure && make && make install
7.3 Configuring the IPMC SOL Parameters
There are many SOL parameters that can be configured for an IPMC, which are
used to manage SOL access security and set its IP configuration. All of them can
be set using ipmitool from an OS running on the blade; from ipmitool
running against the Shelf Manager; and some can be set automatically.
7.3.1 Configuring the SOL Facility
The SOL facility itself has a number of properties that can be set. Use the
ipmitool sol set command to change their values.
Table 7-2 SOL Facility Properties
Property
Values
Meaning
character-accumulate-level count (5 ms units)
How long to hold characters
before sending them
character-send-threshold
count
How many characters to hold
before sending them
enabled
true | false
Whether the SOL facility is
available
force-authentication
true | false
Whether a user password is
required
force-encryption
true | false
Whether network traffic
encryption is required
SB-ATCA7300 Installation and Use Guide
7-2
Serial Over LAN
Table 7-2 SOL Facility Properties
Property
Values
Meaning
non-volatile-bit-rate
serial
9.6
Expected serial port data rate
privilege-level
user
operator
admin
oem
IPMI user privilege level
required to use SOL
retry-count
count
How many times to retry a
lost network packet
retry-interval
count (10 ms units)
Lost network packet retry
interval
set-in-progress
set-complete
Advisory IPMC LAN
set-in-progress configuration state
commit-write
volatile-bit-rate
serial
9.6
Expected serial port data rate
Note - Remember that, for the SB-ATCA7300, IPMI channel 5 corresponds to
Base interface 0, and channel 6 to interface 1.
Any IPMC parameter changes are persistent, even across IPMC firmware updates.
They will need to be restored if the blade is replaced.
To display these properties, use the ipmitool sol info command, run from
the blade OS. These are the default values.
# ipmitool sol info 5
Set in progress
Enabled
Force Encryption
Force Authentication
Privilege Level
Character Accumulate Level (ms)
Character Send Threshold
Retry Count
Retry Interval (ms)
Volatile Bit Rate (kbps)
Non-Volatile Bit Rate (kbps)
Payload Channel
Payload Port
#
:
:
:
:
:
:
:
:
:
:
:
:
:
set-complete
true
true
false
USER
150
200
7
480
9.6
9.6
5 (0x05)
623
SB-ATCA7300 Installation and Use Guide
7-3
Serial Over LAN
7.3.2 Configuring the IPMI SOL User
The IPMI SOL implementation supports only two users, a mandatory null user
with user ID 1, and a second user with user ID 2. The second user’s name,
password, and other characteristics can be changed if desired. These configuration
commands can be run from the host OS on the target blade.
The default user name and password for user ID 2 are soluser and
solpasswd, respectively. These can be changed with the following commands.
ipmitool user set name 2 admin
ipmitool user set password 2 new_password
Ensure that the second user is activated for logins if you will use it.
ipmitool user enable 2
You can display the user ID 2 account configuration using this command.
ipmitool user list 2
7.3.3 Configuring the IPMC Network Environment
There are several different ways to configure IP address information for an IPMC.
 Shelf Manager configuration file



DHCP data requested by the Shelf Manager
ipmitool run on the blade OS
ipmitool run against the Shelf Manager
There are other options, such as placing the network information into the board’s
FRU data or using raw IPMI commands passed through ipmitool, but these are
not suitable for most users and so are not shown.
The IPMC has two network connection points, known as LAN Channels,
connected to the base network. Each LAN Channel can be assigned a different IP
address. These LAN Channels are identified as IPMI channel addresses 5 and 6.
LAN Channel 5 should be configured for base network 0, and LAN Channel 6 for
base network 1.
7.3.3.1 Using the Shelf Manager Configuration File
This is a very convenient mechanism, where a board IPMC in a specific slot
always has the same IP address, regardless of the board serial number. If a board
is replaced, the new board’s PMC will have the same IP address(es) as the
previous board in the slot. The IPMC addresses are set during M3 state
processing. (This requires Pigeon Point Shelf Manager version 2.6.4 or higher.)
To use this configuration file, you must set the /etc/shelfman.conf
parameter BOARD_LAN_PARAMETERS_CHANNEL_LIST parameter to identify
SB-ATCA7300 Installation and Use Guide
7-4
Serial Over LAN
the channels to be assigned. The value of this parameter applies to all boards in
the shelf. If this parameter is not set (the default), the configuration file is ignored.
The file name is /var/nvdata/subsidiary_lan_param, which does not
exist by default. It is an ASCII text file.
Note - Remember to set the parameter and place the file on each ShMM, and
restore them after a ShMM replacement.
This file will be preserved across a Shelf Manager update.
The format of each line is:
slot_num = ip-address, netmask, default-gateway
For example, to assign an address to LAN Channel 6 of the IPMC in physical slot
one, in /etc/shelfman.conf, set:
BOARD_LAN_PARAMETERS_CHANNEL_LIST=6
and place the following in the configuration file:
1 = 192.168.8.81, 255.255.255.0, 192.168.8.1
To assign addresses to more than one LAN Channel of an IPMC, add the
parameter line(s) for the additional channels following immediately after the first.
You must group parameters for the same slot together.
For example, to set IP addresses for LAN Channels 5 and 6 of the IPMC in the
board in slot 1, in /etc/shelfman.conf, set:
BOARD_LAN_PARAMETERS_CHANNEL_LIST=5,6
and put the following in the /var/nvdata/subsidiary_lan_param file.
1 = 192.168.8.81, 255.255.255.0, 192.168.8.1
1 = 192.168.9.81, 255.255.255.0, 192.168.9.1
Blank lines are ignored. Comment lines (starting with #) are accepted and
ignored.
This file can be compressed using gzip if desired.
See section 4.10 of the Shelf Manager User’s Guide for more information.
7.3.3.2 Using DHCP
To configure the board IPMC IP addresses using DHCP, set the
BOARD_LAN_PARAMETERS_USE_DHCP parameter to True in the
/etc/shelfman.conf file. (This requires Pigeon Point Shelf Manager
version 2.7 or higher.)
SB-ATCA7300 Installation and Use Guide
7-5
Serial Over LAN
The AN Channels for which IP addresses are requested are either those set in the
BOARD_LAN_PARAMETERS_CHANNEL_LIST parameter (see section 7.3.3
“Configuring the IPMC Network Environment” on page 7-4), or, by default,
channel 0, meaning the first LAN Channel on the IPMC (channel 5), then channel
1 (second LAN Channel, channel 6) and so on.
The information returned to the IPMC is based on the DHCP Client ID built for
the IPMC. This is a three byte value, consisting of:
 Slot number + 0x2f (slot 1 = 0x30)


AMC Site number (0 for a board IPMC)
LAN Channel number (0 default)
Parameters for all slots are retrieved in parallel, with an infinite lease. The data
obtained is persistently saved by the Shelf Manager. If the board is removed, the
Shelf Manager will delete its internal record and send a Release to the DHCP
manager to free the IP address.
You can pre-configure the DHCP server to assign data based on the client ID, if
desired. Note that there is no indication of the specific shelf ID in the Client ID.
To identify the IP address(es) assigned to the blade, you can either query the
DHCP server or run ipmitool lan print command.
7.3.3.3 Using ipmitool From the Blade OS
Note - ipmitool command privilege levels are managed by the Shelf Manager
or IPMC, not the host OS. However, when used to configure the blade on which it
is running, it usually must be run as root.
The example below shows how to set a LAN configuration parameter for a later
SOL session with ipmitool for base interface 0 (LAN Channel 5). This
command must be run on the blade to which the SOL session will be directed.
n0s70:~# ipmitool lan set 5 ipaddr 192.168.100.97
Setting LAN IP Address to 192.168.100.97
n0s70:~#
Related commands are:
ipmitool
ipmitool
ipmitool
ipmitool
ipmitool
lan
lan
lan
lan
lan
set
set
set
set
set
5
5
5
5
5
netmask 255.255.255.0
defgw ipaddr 192.168.100.1
ipsrc static
access on
arp response on
The example below shows how to display the LAN configuration parameters that
are currently set for SOL sessions to base interface 0 (IPMI channel 5) and base
interface 1 (IPMI channel 6):
SB-ATCA7300 Installation and Use Guide
7-6
Serial Over LAN
root@localhost:~# ipmitool lan print 5
Set in Progress
Auth Type Support
Auth Type Enable
IP Address Source
IP Address
Subnet Mask
MAC Address
Default Gateway IP
Default Gateway MAC
RMCP+ Cipher Suites
Cipher Suite Priv Max
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Set Complete
Callback :
User
:
Operator :
Admin
:
OEM
:
Unspecified
192.168.100.97
255.255.255.0
00:00:00:00:00:00
192.168.100.1
00:00:00:00:00:00
1,2,3,0
Not Available
root@localhost:~# ipmitool lan print 6
Set in Progress
Auth Type Support
Auth Type Enable
IP Address Source
IP Address
Subnet Mask
MAC Address
Default Gateway IP
Default Gateway MAC
RMCP+ Cipher Suites
Cipher Suite Priv Max
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Set Complete
Callback :
User
:
Operator :
Admin
:
OEM
:
Unspecified
192.168.100.98
255.255.255.0
00:00:00:00:00:00
192.168.100.1
00:00:00:00:00:00
1,2,3,0
Not Available
root@localhost:~#
A MAC Address of 00:00:00:00:00:00 means that the MAC address is shared
between the OS base interface and the IPMC SOL interface. The actual address
can be found in the MAC address record of the blade.
7.3.3.4 Using ipmitool Through the Shelf Manager
Note - ipmitool need not be run by root when running remotely (using -I lan
or -I lanplus); command privilege levels are managed by the Shelf Manager
or IPMC, not the host OS.
You can send an IPMI command for a blade’s IPMC to the Shelf Manager, to
have the Shelf Manager pass the command on to the blade.
SB-ATCA7300 Installation and Use Guide
7-7
Serial Over LAN
All of the other IPMI commands shown can be executed using this mechanism.
Just add the appropriate Shelf Manager access information in front of the
command.
For example:
ipmitool lan print 5
becomes
ipmitool -I lan -H shelfm_b2 -t 0x92 -b 0 -U root -f pwfile lan print 5
where:

-I lan – Send the IPMI command across the network, using the RMCP
protocol. (-I lanplus is only supported for IPMI version 2, but may
work depending on your Shelf Manager.)

-H shelfm_b2 – The host name or IP address of the active Shelf
Manager.

-t 0x8e – The IPMB address of the blade with the IPMC against which
the command is to be run. In the range 0x82 - 0x9C. The value is assumed
to be in decimal if not otherwise indicated.


-b 0 – Use IPMB 0 to access the blade. (Required)

-f pwfile – The name of a file containing the -U user’s password.
Either the -E operand (to retrieve the password from the
IPMI_PASSWORD environment variable) or -P password operand
could be used instead.
-U root – The Shelf Manager user to be used to run the command. The
user must have the appropriate privilege level to run the command.
7.4 Establishing a SOL Session
To start a SOL session, the following requirements must be met.
 It must be possible to reach the Base Ethernet network interface on the
target blade from the client system.

The blade is powered on and the IPMC has been initialized.
Remember that you can have only one SOL session per IPMC active at a time.
To establish a SOL session, do the following.
1. Make sure that the session requirements given above are met.
2. Compile and install ipmitool on your target which is destined for opening
the SOL session on the SB-ATCA7300. For details refer to section 7.2 “Installing
ipmitool” on page 7-2.
3. If necessary, change the SOL user name and password. The default user is
soluser and password is solpasswd. See section 7.3.2 “Configuring the
IPMI SOL User” on page 7-4.
SB-ATCA7300 Installation and Use Guide
7-8
Serial Over LAN
4. Set an IP address for the SB-ATCA7300 IPMC. Refer to section 7.3.3
“Configuring the IPMC Network Environment” on page 7-4.
5. Start the SOL session for your target with ipmitool using the configured IP
address for the appropriate SB-ATCA7300 IPMC LAN Channel and user
information. (-H is the IP address or host name assigned to the target IPMC.)
The -k operand specifies the BMC key, used to create the network Session
Integrity Key. The default value is gkey.
ipmitool -I lanplus -H 172.16.0.221 -U soluser -P solpasswd -k gkey sol
activate
6. When done, exit your SOL session using ~. (Tilde - period), like tip.
7. You can deactivate SOL using the following command.
ipmitool -I lanplus -H 172.16.0.221 -U soluser -P solpasswd -k gkey sol
deactivate
For details on the command parameters, refer to the ipmitool documentation
available on http://ipmitool.sourceforge.net.
Note - To access the BIOS setup screens, you must reset the blade after the SOL
session has been established to enter BIOS setup.
SB-ATCA7300 Installation and Use Guide
7-9
Serial Over LAN
SB-ATCA7300 Installation and Use Guide
7-10
8 FRU Information and Sensor
Data Records
8.1 FRU ID Information
The SB-ATCA7300 provides the following FRU ID information in FRU ID 0.
Table 8-1 FRU ID Definition
Area
Internal use
Board information
Product information
Description
Value
Access
Not used
Mfg date/time
According to Platform
Management FRU
information Storage
Definition v1.01
r
Board manufacturer
SANBlaze Technology, Inc. r
Board product name
SB-ATCA7300
r
Board serial number
Defined by SANBlaze
r
Board part number
Defined by SANBlaze
r
Product manufacturer
SANBlaze Technology, Inc. r
Product name
SB-ATCA7300
r
Product serial number Defined by SANBlaze
r
Product part number
SB-ATCA7300
r
Board Point-To-Point
Connectivity Records
This Multi-Record area
contains the ATCA Blade
Point to Point Connectivity
Records according to
PICMG 3.0, Rev.1.0. These
contents are described in
section 8.2 “E-Keying” on
page 8-4.
r
Multi-Record
information
User Info Area
r/w
Custom usage
r/w
The following is a formatted version of the SB-ATCA7300 FRU ID data.
CLI> fruinfo -v board 12
94: FRU # 0, FRU Info
Common Header:
Format Version = 1
SB-ATCA7300 Installation and Use Guide
8-1
FRU Information and Sensor Data Records
Board Info Area:
Version
= 1
Language Code
Mfg Date/Time
Board Manufacturer
Board Product Name
Board Serial Number
Board Part Number
FRU Programmer File ID
Custom Board Info
=
=
=
=
=
=
=
=
25
Apr 20 00:00:00 2011 (8046720 minutes since 1996)
SANBlaze Technology,Inc.
SB-ATCA7300
703E1040001
600-730000
7106825L
Product Info Area:
Version
= 1
Language Code
Manufacturer Name
Product Name
Product Part / Model#
Product Version
Product Serial Number
Asset Tag
FRU Programmer File ID
Custom Product Info
=
=
=
=
=
=
=
=
=
25
SANBlaze Technology,Inc.
SB-ATCA7300
SB-ATCA7300
00
703E1040001
Multi Record Area:
PICMG Board Point-to-Point
Version = 0
OEM GUID Count
=
OEM GUID 000
= 00
Link Descriptor:
Link Grouping ID
=
Link Type
=
Link Type Extension =
Link Designator
=
Link Descriptor:
Link Grouping ID
=
Link Type
=
Link Type Extension =
Link Designator
=
Link Descriptor:
Link Grouping ID
=
Link Type
=
Link Type Extension =
Link Designator
=
Link Descriptor:
Link Grouping ID
=
Link Type
=
Link Type Extension =
Link Designator
=
Link Descriptor:
Link Grouping ID
=
Link Type
=
Link Type Extension =
Link Designator
=
Link Descriptor:
Link Grouping ID
=
Link Type
=
Link Type Extension =
Link Designator
=
Link Descriptor:
Connectivity Record (ID=0x14)
1
00 00 73 CA A7 00 00 00 00 00 20 20 20 CA A7
0x00
0x01 PICMG 3.0 Base 10/100/1000 Base-T
0x0 10/100/1000BASE-T Link (four-pair)
0x101 Channel1/BaseInterface/Ports0
0x00
0x01 PICMG 3.0 Base 10/100/1000 Base-T
0x0 10/100/1000BASE-T Link (four-pair)
0x102 Channel2/BaseInterface/Ports0
0x00
0x02 PICMG 3.1 Ethernet Fabric
0x1
0xF41 Channel1/FabricInterface/Ports0123
0x00
0x02 PICMG 3.1 Ethernet Fabric
0x0
0x141 Channel1/FabricInterface/Ports0
0x00
0x02 PICMG 3.1 Ethernet Fabric
0x1
0xF42 Channel2/FabricInterface/Ports0123
0x00
0x02 PICMG 3.1 Ethernet Fabric
0x0
0x142 Channel2/FabricInterface/Ports0
SB-ATCA7300 Installation and Use Guide
8-2
FRU Information and Sensor Data Records
Link
Link
Link
Link
Grouping ID
Type
Type Extension
Designator
=
=
=
=
0x00
0xF0 E-Keying OEM GUID Definition
0x0
0x181 Channel1/UpdateInterface/Ports0
AMC Carrier Information Table Record (ID=0x1a)
Version = 0
Site Count = 1
Site Numbers: 0x0f
AMC Carrier Activation and Current Management Record (ID=0x17)
Version = 0
Maximum Internal Current Draw = 3.0 Amps at 12V Payload
Allowance for Module Activation Readiness = 5 seconds
Module Activation and Power Descriptor count = 1
Local IPMB-L 0x8e, Max Module Current 3.0 Amps, Config Value: 0xff
AMC Carrier Point-to-Point Connectivity Record (ID=0x18)
Version = 0
Resource: 1 "AMC", ID 15, P2P Port count = 8
Local port # 20, Remote Port # 0, Resource: 0 "on-Carrier
Local port # 21, Remote Port # 1, Resource: 0 "on-Carrier
Local port # 22, Remote Port # 2, Resource: 0 "on-Carrier
Local port # 23, Remote Port # 3, Resource: 0 "on-Carrier
Local port # 24, Remote Port # 4, Resource: 0 "on-Carrier
Local port # 25, Remote Port # 5, Resource: 0 "on-Carrier
Local port # 26, Remote Port # 6, Resource: 0 "on-Carrier
Local port # 27, Remote Port # 7, Resource: 0 "on-Carrier
device",
device",
device",
device",
device",
device",
device",
device",
AMC Point-to-Point Connectivity Record (ID=0x19)
Version = 0
OEM GUID Count = 0
Type: On-Carrier Device # 0
AMC Channel Descriptors:
Lane 3: Port 3, Lane 2: Port 2, Lane 1: Port 1, Lane 0: Port 0
Lane 3: Port 7, Lane 2: Port 6, Lane 1: Port 5, Lane 0: Port 4
AMC Link Descriptors:
Channel: 0x00, Link Type: 0x02 ("AMC.1 PCI Express"), Ext: 0x0
Asym Match: 0x2, Link Group ID: 0x01
Lane 3: Included, Lane 2: Included, Lane 1: Included, Lane
Included
Channel: 0x01, Link Type: 0x02 ("AMC.1 PCI Express"), Ext: 0x0
Asym Match: 0x2, Link Group ID: 0x01
Lane 3: Included, Lane 2: Included, Lane 1: Included, Lane
Included
Channel: 0x00, Link Type: 0x02 ("AMC.1 PCI Express"), Ext: 0x2
Asym Match: 0x2, Link Group ID: 0x02
Lane 3: Included, Lane 2: Included, Lane 1: Included, Lane
Included
Channel: 0x01, Link Type: 0x02 ("AMC.1 PCI Express"), Ext: 0x2
Asym Match: 0x2, Link Group ID: 0x02
Lane 3: Included, Lane 2: Included, Lane 1: Included, Lane
Included
ID
ID
ID
ID
ID
ID
ID
ID
0
0
0
0
0
0
0
0
0:
0:
0:
0:
CLI>
SB-ATCA7300 Installation and Use Guide
8-3
FRU Information and Sensor Data Records
8.2 E-Keying
The following table lists the E-Keying information provided by the
SB-ATCA7300. This information is contained in the point-to-point connectivity
record area. This data is shown formatted in the previous section.
Table 8-2 Contents of the Blade Point-to-Point Connectivity Record Area
#
1
2
3
4
5
6
Link
Grouping
ID
0
Interface
0 (Base
Interface)
0
0 (Base
Interface)
0
1 (Fabric
Interface)
0
0
0
1 (Fabric
Interface)
1 (Fabric
Interface)
1 (Fabric
Interface)
Link
Link
Type
Descriptor
Extension
Value
Channel
Number
Ports
Link
Type
1
0 -SET
1 - NOT SET
2 - NOT SET
3 - NOT SET
0x01
0
2
0 -SET
1 - NOT SET
2 - NOT SET
3 - NOT SET
0x01
1
1
0 -SET
1 - SET
2 -SET
3 -SET
0x02
1
1
0 -SET
1 - NOT SET
2 - NOT SET
3 - NOT SET
0x02
0
2
0 - SET
1 - SET
2 - SET
3 - SET
0x02
1
2
0 -SET
1 - NOT SET
2 - NOT SET
3 - NOT SET
0x02
0
SB-ATCA7300 Installation and Use Guide
8-4
FRU Information and Sensor Data Records
8.3 Power Configuration
This table describes the blade’s power level and power management information.
Table 8-3 Power Configuration
Item
Value
Description
Dynamic power
reconfiguration
support
No
While the blade is powered, it
supports only one power
level.
Dynamic power
configuration
No
The power level is fixed and
does not change once set.
Number of power
draw levels
2
The amount of possible power
levels
Early Power Draw
Levels, Watt
-
Complete early power level
including IPMC
Steady state Power
Draw Levels, Watt
Level 1 - 195 Watts
Level 2 - 260 Watts
Entire blade slot steady-state
power consumption
0 seconds
How long blade power usage
takes to settle after power on.
Transition from early
to steady levels
8.4 Sensor Data Record Types
The sensors available on the SB-ATCA7300 are shown in the table below. See
section 8.5 “Detailed Sensor Data Records” on page 8-8 for a detailed description
of the Sensor Data Records.
Table 8-4 SDR Record Types
Sensor Type
Sensor
Number
MC Locator
Management Controller Locator Record
N/A
Hot Swap Carrier
PICMG 3.0:FRU HotSwap
0
Hotswap_RTM
PICMG 3.0:FRU HotSwap
1
Version Change
Version Change
2
IPMB Physical
IPMB Physical Link Good
3
BMC Watchdog
Watchdog 2 [OS boot timer]
4
12.0V
Voltage
5
3.3V
Voltage
6
3.3V Mgmt
Voltage
7
1.8V Eth
Voltage
8
Sensor Name
SB-ATCA7300 Installation and Use Guide
8-5
FRU Information and Sensor Data Records
Table 8-4 SDR Record Types (Continued)
Sensor Name
Sensor Type
Sensor
Number
1.5V
Voltage
9
1.2V
Voltage
10
VCC CPU0
Voltage
11
1.5V DDR3
Voltage
12
Bottom Edge Temp
Temperature
13
Top Edge Temp
Temperature
14
IPMC POST
Management Subsystem Health
15
Boot Bank
SANBlaze-specific Discrete Digital
16
Fw Progress
System Firmware [Upgrade] Progress
17
OS Boot
OS booting
18
Boot Error
Boot Error
19
Boot Initiated
System Boot Initiated
20
SB-ATCA7300 IPMC
SANBlaze IPMC Status
21
Power Good
Entity Presence
22
POST Code
SANBlaze-specific Discrete Digital
23
Reset Source
SANBlaze-specific Discrete Digital
24
DDR 1 temp
Temperature
25
DDR 2 temp
Temperature
26
DDR 3 temp
Temperature
27
DDR 4 temp
Temperature
28
DDR 5 temp
Temperature
29
DDR 6 temp
Temperature
30
DDR 7 temp
Temperature
31
DDR 8 temp
Temperature
32
DDR 9 temp
Temperature
33
DDR 10 temp
Temperature
34
DDR 11 temp
Temperature
35
DDR 12 temp
Temperature
36
IPMC temp
Temperature
37
CPU Status
Processor
38
CPU0 temp
Temperature
39
SB-ATCA7300 Installation and Use Guide
8-6
FRU Information and Sensor Data Records
Table 8-4 SDR Record Types (Continued)
Sensor Name
Sensor Type
Sensor
Number
CPU1 temp
Temperature
40
-48v A Volts
Voltage
41
-48v B Volts
Voltage
42
-48v Amps
Current
43
HoldUp Cap Volts
Voltage
44
PWR Entry Status
PWR Entry Status Sensor
45
Memory
Memory event (presence, ECC error)
46
Critical IRQ
PCIe error information
47
Battery
Blade battery status
48
48V A Supply
Power supply status
49
48V B Supply
Power supply status
50
+3.3V
Voltage
51
+5V
Voltage
52
+12V
Voltage
53
Inlet Temp
Temperature
54
Board Temp
Temperature
55
+1.5V
Voltage
56
+1.2V
Voltage
57
+1V
Voltage
58
+1.8V
Voltage
59
Version Change
RTM MMC FW Version Change
60
SB-ATCA7300 Installation and Use Guide
8-7
FRU Information and Sensor Data Records
8.5 Detailed Sensor Data Records
The sensors available on the SB-ATCA7300 are described in detail in the table below.
Table 8-5 Sensor Data Records
#
0
1
2
Sensor
Name
Sensor
Type
Event
Reading
Type
Event DataByte
1
2
3
Event
Threshold
Description
Sensorspecific
discrete
0x6F
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Hotswap_RTM
Hot Swap
0xF0
Sensorspecific
discrete
0x6F
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
[7:4] = Cause
[3:0] = Previous
State
FRU ID
0x0: M0
0x1: M1
0x2: M2
0x3: M3
0x4: M4
0x5: M5
0x6: M6
0x7: M7
Version change
Version
Change
0x2B
Sensorspecific
discrete
0x6F
0x7
Change type
0xFF
0x7: Software or
F/W change
successful
Hot Swap
Carrier
Asrt: Assertion
Deass: Deassertion
Hot Swap
0xF0
Unr: Upper non-recoverable threshold
Lnr: Lower non-recoverable threshold
SB-ATCA7300 Installation and Use Guide
[7:4] = Cause
[3:0] = Previous
State
Uc: Upper critical threshold
Lc: Lower critical threshold
Assertion
Rearm
Deassertion
FRU ID
0x0: M0
0x1: M1
0x2: M2
0x3: M3
0x4: M4
0x5: M5
0x6: M6
0x7: M7
Asrt
Auto
Asrt
Auto
Asrt
Auto
Unc: Upper non-critical threshold
Lnc: Lower non-critical threshold
8-8
FRU Information and Sensor Data Records
Table 8-5 Sensor Data Records (Continued)
#
Sensor
Name
Sensor
Type
Event
Reading
Type
Event DataByte
1
2
3
Event
Threshold
Description
Assertion
Rearm
Deassertion
reading
0x0: IPMB-A
disabled, IPMB-B
disabled
0x1: IPMB-A
enabled, IPMB-B
disabled
0x2: IPMB-A
disabled, IPMB-B
enabled
0x3: IPMB-A
enabled, IPMB-B
enabled
Asrt
Auto
See IPMI Spec
0xFF
0x0: Timer expired
0x1: Hard Reset
0x2: Power Down
0x3: Power Cycle
0x8: Timer Interrupt
Asrt
Auto
3
IPMB Physical
Sensorspecific
discrete
0x6F
0x0
0x1
0x2
0x3
4
SensorWatchdog 2 specific
BMC Watchdog
discrete
0x23
0x6F
0x0
0x1
0x2
0x3
0x8
5
12.0V
Voltage
0x02
Threshold
0x01
reading
threshold
unr uc lnr lc
Asrt / Deass
Auto
6
3.3V
Voltage
0x02
Threshold
0x01
reading
threshold
unr uc lnr lc
Asrt / Deass
Auto
7
3.3V Mgmt
Voltage
0x02
Threshold
0x01
reading
threshold
unr uc lnr lc
Asrt / Deass
Auto
8
1.8V Eth
Voltage
0x02
Threshold
0x01
reading
threshold
unr uc lnr lc
Asrt / Deass
Auto
Asrt: Assertion
Deass: Deassertion
Physical
IPMB-0
0xF1
Unr: Upper non-recoverable threshold
Lnr: Lower non-recoverable threshold
SB-ATCA7300 Installation and Use Guide
[7:4] = Channel
Number
[3:0] = Reserved
Uc: Upper critical threshold
Lc: Lower critical threshold
Unc: Upper non-critical threshold
Lnc: Lower non-critical threshold
8-9
FRU Information and Sensor Data Records
Table 8-5 Sensor Data Records (Continued)
#
Sensor
Name
Sensor
Type
Event
Reading
Type
Event DataByte
1
2
3
Event
Threshold
Description
Assertion
Rearm
Deassertion
9
1.5V
Voltage
0x02
Threshold
0x01
reading
threshold
unr uc lnr lc
Asrt / Deass
Auto
10
1.2V
Voltage
0x02
Threshold
0x01
reading
threshold
unr uc lnr lc
Asrt / Deass
Auto
11
VCC CPU0
Voltage
0x02
Threshold
0x01
reading
threshold
unr uc lnr lc
Asrt / Deass
Auto
12
1.5V DDR3
Voltage
0x02
Threshold
0x01
reading
threshold
unr uc lnr lc
Asrt / Deass
Auto
13
Bottom Edge
Temp
Temp
0x01
Threshold
0x01
reading
threshold
unr uc unc
Asrt / Deass
Auto
14
Top Edge Temp
Temp
0x01
Threshold
0x01
reading
threshold
unr uc unc
Asrt / Deass
Auto
IPMC POST
Manageme
nt
Subsystem
Health
0x28
digital
Discrete
0x06
0x0
0x1
0xFF
0xFF
0x0: Performance
Met
0x1: Performance
Lags
Asrt
Auto
Boot Bank
OEM
0xD2
Sensorspecific
discrete
0x6F
0x0
0xFF
0xFF
0x0: Boot Bank A
Asrt
Auto
15
16
Asrt: Assertion
Deass: Deassertion
Unr: Upper non-recoverable threshold
Lnr: Lower non-recoverable threshold
SB-ATCA7300 Installation and Use Guide
Uc: Upper critical threshold
Lc: Lower critical threshold
Unc: Upper non-critical threshold
Lnc: Lower non-critical threshold
8-10
FRU Information and Sensor Data Records
Table 8-5 Sensor Data Records (Continued)
#
17
18
Sensor
Name
Sensor
Type
Fw Progress
System
Firmware
Progress
0x0F
OS Boot
Asrt: Assertion
Deass: Deassertion
OS Boot
0x1F
Event
Reading
Type
Sensorspecific
discrete
0x6F
Sensorspecific
discrete
0x6F
Unr: Upper non-recoverable threshold
Lnr: Lower non-recoverable threshold
SB-ATCA7300 Installation and Use Guide
Event DataByte
1
0x0
0x1
0x2
0x0
0x1
0x2
0x3
0x4
0x5
0x6
2
See IPMI Spec
0xFF
Uc: Upper critical threshold
Lc: Lower critical threshold
3
Event
Threshold
Description
Assertion
Rearm
Deassertion
See IPMI
Spec
0x0: System
Firmware Error
0x1: System
Firmware Hang
0x2: System
Firmware Progress
Asrt
Auto
0xFF
0x0: A: boot
completed
0x1: C: boot
completed
0x2: PXE boot
completed
0x3: Diagnostic boot
completed
0x4: CD_ROM boot
completed
0x5: ROM boot
completed
0x6: boot completed
- boot device not
specified
Asrt
Auto
Unc: Upper non-critical threshold
Lnc: Lower non-critical threshold
8-11
FRU Information and Sensor Data Records
Table 8-5 Sensor Data Records (Continued)
#
19
20
Sensor
Name
Boot Error
0x1E
Boot Error
Boot Initiated
Asrt: Assertion
Deass: Deassertion
Sensor
Type
System
Boot
Initiated
0x1D
Event
Reading
Type
Sensorspecific
discrete
0x6F
Sensorspecific
discrete
0x6F
Unr: Upper non-recoverable threshold
Lnr: Lower non-recoverable threshold
SB-ATCA7300 Installation and Use Guide
Event DataByte
1
0x0
0x1
0x2
0x3
0x4
0x0
0x1
0x2
0x3
0x4
2
0xFF
0xFF
Uc: Upper critical threshold
Lc: Lower critical threshold
3
Event
Threshold
Description
Assertion
Rearm
Deassertion
0xFF
0x0: No Bootable
media
0x1: Non-bootable
diskette left in drive
0x2: PXE Server not
found
0x3: Invalid boot
sector
0x4: Timout waiting
for user selection of
boot source
Asrt
Auto
0xFF
0x0: Initiated by
power up
0x1: Initiated by
hard reset
0x2: Initiated by
warm reset
0x3: User requested
PXE boot
0x4: Automatic boot
to diagnostic
Asrt
Auto
Unc: Upper non-critical threshold
Lnc: Lower non-critical threshold
8-12
FRU Information and Sensor Data Records
Table 8-5 Sensor Data Records (Continued)
#
21
22
23
Sensor
Name
Sensor
Type
Event
Reading
Type
Event DataByte
1
SB-ATCA7300
IPMC
OEM
0xD5
Sensorspecific
discrete
0x6F
0x0
0x1
0x2
0x3
0x4
0x5
0x6
Power Good
Entity
Presence
0x25
Sensorspecific
discrete
0x6F
0x0
0x1
Sensorspecific
discrete
0x6F
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
POST Code
Asrt: Assertion
Deass: Deassertion
OEM
0xD2
Unr: Upper non-recoverable threshold
Lnr: Lower non-recoverable threshold
SB-ATCA7300 Installation and Use Guide
2
-
0xFF
-
Uc: Upper critical threshold
Lc: Lower critical threshold
3
Event
Threshold
Description
Assertion
Rearm
Deassertion
-
0x0: Watchdog
Reset
0x1: Software Reset
0x2: Power Failure
0x3: Hard Boot
0x4: Cold Boot
0x5: Warm Boot
0x6: Reserved
Asrt
Auto
0xFF
0x0: Entity Present
0x1: Entity Absent
Asrt
Auto
-
0x0: No events for
this sensor. Read
according to EFI
BIOS port 80 status
codes. (See
Appendix B, "BIOS
Status Codes".)
Asrt
Auto
Unc: Upper non-critical threshold
Lnc: Lower non-critical threshold
8-13
FRU Information and Sensor Data Records
Table 8-5 Sensor Data Records (Continued)
#
Sensor
Name
Sensor
Type
Event
Reading
Type
Sensorspecific
discrete
0x6F
Event DataByte
1
2
3
0x0
[7] =
IPMC_RST_REQ
_Payload
[6] =
XDP0_DBRST_C
PU
[5] =
CPU_RST_CPU
[4]
RTM_PB_RST_R
eset
[3] =
XDP1_DBRST_C
PU
[2] =
PB_RST_Face
[1]
XDP0_BRD_PW
ROK
[0] =
PWR_GOOD
[7:2] =
Reserved
[1] = IPMC
Pre-Timout
[0] = IPMC
Watchdog
Timeout
0x0: Payload Reset
detected. Cause
delivered in Event
Byte 2/3
24
Reset Source
OEM
0xD2
25
DDR 1 temp
Temp
0x01
Threshold
0x01
reading
threshold
26
DDR 2 temp
Temp
0x01
Threshold
0x01
reading
threshold
Asrt: Assertion
Deass: Deassertion
Unr: Upper non-recoverable threshold
Lnr: Lower non-recoverable threshold
SB-ATCA7300 Installation and Use Guide
Event
Threshold
Description
Uc: Upper critical threshold
Lc: Lower critical threshold
Assertion
Rearm
Deassertion
Asrt
Auto
unr uc unc
Asrt / Deass
Auto
unr uc unc
Asrt / Deass
Auto
Unc: Upper non-critical threshold
Lnc: Lower non-critical threshold
8-14
FRU Information and Sensor Data Records
Table 8-5 Sensor Data Records (Continued)
Event DataByte
Event
Threshold
Description
#
27
DDR 3 temp
Temp
0x01
Threshold
0x01
reading
threshold
unr uc unc
Asrt / Deass
Auto
28
DDR 4 temp
Temp
0x01
Threshold
0x01
reading
threshold
unr uc unc
Asrt / Deass
Auto
29
DDR 5 temp
Temp
0x01
Threshold
0x01
reading
threshold
unr uc unc
Asrt / Deass
Auto
30
DDR 6 temp
Temp
0x01
Threshold
0x01
reading
threshold
unr uc unc
Asrt / Deass
Auto
31
DDR 7 temp
Temp
0x01
Threshold
0x01
reading
threshold
unr uc unc
Asrt / Deass
Auto
32
DDR 8 temp
Temp
0x01
Threshold
0x01
reading
threshold
unr uc unc
Asrt / Deass
Auto
33
DDR 9 temp
Temp
0x01
Threshold
0x01
reading
threshold
unr uc unc
Asrt / Deass
Auto
34
DDR 10 temp
Temp
0x01
Threshold
0x01
reading
threshold
unr uc unc
Asrt / Deass
Auto
35
DDR 11 temp
Temp
0x01
Threshold
0x01
reading
threshold
unr uc unc
Asrt / Deass
Auto
36
DDR 12 temp
Temp
0x01
Threshold
0x01
reading
threshold
unr uc unc
Asrt / Deass
Auto
37
IPMC temp
Temp
0x01
Threshold
0x01
reading
threshold
unr uc unc
Asrt / Deass
Auto
Asrt: Assertion
Deass: Deassertion
Sensor
Type
Event
Reading
Type
Sensor
Name
Unr: Upper non-recoverable threshold
Lnr: Lower non-recoverable threshold
SB-ATCA7300 Installation and Use Guide
1
2
Uc: Upper critical threshold
Lc: Lower critical threshold
3
Assertion
Rearm
Deassertion
Unc: Upper non-critical threshold
Lnc: Lower non-critical threshold
8-15
FRU Information and Sensor Data Records
Table 8-5 Sensor Data Records (Continued)
#
Sensor
Name
Sensor
Type
38
CPU Status
Processor
0x07
39
CPU0 temp
Temp
0x01
40
CPU1 temp
41
Event
Reading
Type
Sensorspecific
discrete
0x6F
Event DataByte
1
3
0xFF
0xFF
0x1: Thermal Trip
Threshold
0x01
reading
threshold
Temp
0x01
Threshold
0x01
reading
-48v A Volts
Voltage
0x02
Threshold
0x01
42
-48v B Volts
Voltage
0x02
43
-48v Amps
44
HoldUp Cap
Volts
Asrt: Assertion
Deass: Deassertion
Assertion
Rearm
Deassertion
Asrt
Auto
unr uc unc
Asrt / Deass
Auto
threshold
unr uc unc
Asrt / Deass
Auto
reading
threshold
unr uc lnr lc
Asrt / Deass
Auto
Threshold
0x01
reading
threshold
unr uc lnr lc
Asrt / Deass
Auto
Current
0x03
Threshold
0x01
reading
threshold
No Thresholds
N/A
N/A
Voltage
0x02
Threshold
0x01
reading
threshold
unr uc lnr lc
Asrt / Deass
Auto
Unr: Upper non-recoverable threshold
Lnr: Lower non-recoverable threshold
SB-ATCA7300 Installation and Use Guide
0x1
2
Event
Threshold
Description
Uc: Upper critical threshold
Lc: Lower critical threshold
Unc: Upper non-critical threshold
Lnc: Lower non-critical threshold
8-16
FRU Information and Sensor Data Records
Table 8-5 Sensor Data Records (Continued)
#
45
Sensor
Name
PWR Entry
Status
Asrt: Assertion
Deass: Deassertion
Sensor
Type
OEM
0xD7
Event
Reading
Type
Sensorspecific
discrete
0x6F
Unr: Upper non-recoverable threshold
Lnr: Lower non-recoverable threshold
SB-ATCA7300 Installation and Use Guide
Event DataByte
1
2
3
0x0
Synchor Pwr Entr
Module:
[6] = VOUT_low
[5] = Hotswap
[4] = Holdup
[2] = Alarm
[1] = Enable_B
[0] Enable_A
SANBlaze Pwr
Entry Module:
[7] = DIG_Fault
[6] =
HUCapEngage
[5] =
Hotswap_Enable
[4] =
HUCap_Switch
[3] =
Alarm_Control
[1] = DIG_Alarm
[0] =
Sec_MCU_Fault
All other bits are
reserved
[7:6] = Pwr
Entry
Module
0=
Synchor
1=
SANBlaze
Pwr Entry
Module:
[2] =
DIG_Enabl
eA
[1] =
DIG_Enabl
eB
[0] =
Mcu_Fault
All other
bits are
reserved
Uc: Upper critical threshold
Lc: Lower critical threshold
Event
Threshold
Description
0x0: Pwr Entry
Module Status
Change detected
Assertion
Rearm
Deassertion
Asrt
Auto
Unc: Upper non-critical threshold
Lnc: Lower non-critical threshold
8-17
FRU Information and Sensor Data Records
Table 8-5 Sensor Data Records (Continued)
#
46
47
Sensor
Name
Sensor
Type
Event
Reading
Type
Memory
Memory
0x0C
Sensorspecific
discrete
0x6F
Critical IRQ
Critical
Interrupt
0x13
Sensorspecific
discrete
0x6F
Asrt: Assertion
Deass: Deassertion
Unr: Upper non-recoverable threshold
Lnr: Lower non-recoverable threshold
SB-ATCA7300 Installation and Use Guide
Event DataByte
1
2
3
0x0
0x1
0x4
0x5
0x6
0x7
0xFF
[7] = CPU
Socket 0/1
[6:5] =
DIMM
channel
0..2
[4] =
DIMM
number per
Channel
0/1
[3:0] =
DIMM
number
1..12
0xF in
DIMM
number
means
unknown
number
0x4
0x5
0xFF
0xFF
Uc: Upper critical threshold
Lc: Lower critical threshold
Event
Threshold
Description
Assertion
Rearm
Deassertion
0x0: Correctable
ECC
0x1: Uncorrectable
ECC
0x4: Memory Device
Disabled
0x5: Correctable
ECC
0x6: Presence
detected
0x7: Configuration
error.
Asrt
Auto
0x4: PCI PERR
0x5: PCI SERR
Asrt
Auto
Unc: Upper non-critical threshold
Lnc: Lower non-critical threshold
8-18
FRU Information and Sensor Data Records
Table 8-5 Sensor Data Records (Continued)
#
Sensor
Name
Sensor
Type
Event
Reading
Type
Event DataByte
1
Battery
Battery
0x29
Sensorspecific
discrete
0x6F
0x1
48V A Supply
Power
Supply
0x08
Sensorspecific
discrete
0x6F
0x0
0x1
50
48V B Supply
Power
Supply
0x08
Sensorspecific
discrete
0x6F
0x0
0x1
51
+3.3V
Voltage
0x02
52
+5V
53
48
2
Assertion
Rearm
Deassertion
0xFF
0x1: Battery failed
Asrt
Auto
0xFF
0x0: Presence
detected
0x1: Power Supply
Failure detected
Asrt / Deass
Auto
See IPMI Spec
0xFF
0x0: Presence
detected
0x1: Power Supply
Failure detected
Asrt / Deass
Auto
Threshold
0x01
reading
threshold
unr uc unc lnr lc lnc
Asrt / Deass
Auto
Voltage
0x02
Threshold
0x01
reading
threshold
unr uc unc lnr lc lnc
Asrt / Deass
Auto
+12V
Voltage
0x02
Threshold
0x01
reading
threshold
unr uc unc lnr lc lnc
Asrt / Deass
Auto
54
Inlet Temp
Temp
0x01
Threshold
0x01
reading
threshold
unr uc unc
Asrt / Deass
Auto
55
Board Temp
Temp
0x01
Threshold
0x01
reading
threshold
unr uc unc
Asrt / Deass
Auto
56
+1.5V
Voltage
0x02
Threshold
0x01
reading
threshold
unr uc unc lnr lc lnc
Asrt / Deass
Auto
49
Asrt: Assertion
Deass: Deassertion
Unr: Upper non-recoverable threshold
Lnr: Lower non-recoverable threshold
SB-ATCA7300 Installation and Use Guide
0xFF
3
Event
Threshold
Description
See IPMI Spec
Uc: Upper critical threshold
Lc: Lower critical threshold
Unc: Upper non-critical threshold
Lnc: Lower non-critical threshold
8-19
FRU Information and Sensor Data Records
Table 8-5 Sensor Data Records (Continued)
#
Sensor
Name
Sensor
Type
Event
Reading
Type
Event DataByte
1
2
3
Event
Threshold
Description
Assertion
Rearm
Deassertion
57
+1.2V
Voltage
0x02
Threshold
0x01
reading
threshold
unr uc unc lnr lc lnc
Asrt / Deass
Auto
58
+1V
Voltage
0x02
Threshold
0x01
reading
threshold
unr uc unc lnr lc lnc
Asrt / Deass
Auto
59
+1.8V
Voltage
0x02
Threshold
0x01
reading
threshold
unr uc unc lnr lc lnc
Asrt / Deass
Auto
Version Change
[RTM MMC]
Version
Change
0x2B
Sensorspecific
discrete
0x6F
Change type
0xFF
0x7: Software or
F/W change
successful
Asrt
Auto
60
Asrt: Assertion
Deass: Deassertion
Unr: Upper non-recoverable threshold
Lnr: Lower non-recoverable threshold
SB-ATCA7300 Installation and Use Guide
0x7
Uc: Upper critical threshold
Lc: Lower critical threshold
Unc: Upper non-critical threshold
Lnc: Lower non-critical threshold
8-20
9 SB-ATCA7300 Firmware Updates
9.1 Firmware Update Mechanisms
Updatable firmware components of the SB-ATCA7300 include the BIOS, FPGA,
and IPMC flash images. These images are updated either by a specially-designed
DOS utility or by using the ipmitool utility.
Table 9-1 SB-ATCA7300 Firmware Update Methods
Component
Update Method
DOS Utility
BIOS
X
FPGA
X
IPMC
HPM.1
X
HPM.1 updates, based on the PICMG Hardware Platform Management 1
specification, are performed using IPMI, connecting either through the Shelf
Manager or directly to a properly configured IPMC.
Note - HPM.1 commands are always directed to the inactive image, including the
commands which read firmware image properties. As a result, the HPM.1
interface cannot provide information about the active firmware image.
9.1.1 Obtaining Updates
You can obtain updates for the SB-ATCA7300 from the SANBlaze web site. If
you are already a registered SANBlaze user, go to http://www.sanblaze.com/user/
login. Otherwise, you will need to create an account at http://www.sanblaze.com/
user/register.
9.2 Updating the BIOS and FPGA Firmware
Both the BIOS and FPGA have two separate boot images, an active and a backup
or inactive image. The BIOS and FPGA updates are run from a DOS utility
running on the blade to be updated.
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9-1
SB-ATCA7300 Firmware Updates
9.2.1 The Update Package
The BIOS update package will contain the following update files:
Table 9-2 BIOS Update Package
Filename
Description
atca7300_bios_xx_xx_xxxx_xxxx.bin
BIOS update image
atca7300_fpga_xx_xx_xxxx_xxxx.bin FPGA update image
The update packages contain the new image (such as AMIBIOS.BIN), the
update utility (afudos.exe) and a README file (readme.txt).
9.2.2 Determining the Current BIOS and FPGA Firmware Versions
There are several ways to determine version of the blade’s currently installed
BIOS and FPGA images.
 Access the BIOS; see section 5.3.15.1 “Board Information Display” on
page 5-8 and section 5.5.1 “BIOS Main Menu” on page 5-15.

From the BIOS boot messages; see section 5.4.2 “BIOS Boot Process” on
page 5-12.

Using ipmitool hpm check; see section 9.3.2.2 “Using ipmitool” on
page 9-5.

Depending on your OS, the BIOS and FPGA version information may be
displayed and recorded in a system log file as part of the boot process.
Note that most OS-provided utilities do not return the FPGA version, only the
BIOS version.
9.2.3 Performing the Update
CAUTION - Please do not turn off or reboot the blade during a BIOS update.
This can cause the need for a long recovery process with multiple blade reboots.
Note - To update the BIOS or FPGA images, you will need to copy the update
images and utility onto a bootable device, initialized with a DOS image. This
utility will not run in a Windows command window nor DOS prompt window.
The flags for the afudos.exe utility are displayed when you run the utility with
no flags.
C:\7300>afudos
+---------------------------------------------------------------------------+
|
AMI Firmware Update Utility(APTIO) Ver.2.23
|
|
Copyright (C)2007 American Megatrends Inc. All Rights Reserved.
|
+---------------------------------------------------------------------------+
| Usage: AFUDOS <ROM File Name> [Option 1] [Option 2]...
|
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9-2
SB-ATCA7300 Firmware Updates
|
or
|
|
AFUDOS <Input or Output File Name> <Command>
|
|
or
|
|
AFUDOS <Command>
|
| ------------------------------------------------------------------------- |
| Commands:
|
|
/O - Save current BIOS into file
|
|
/U - Display ROM file's ROMID
|
|
/D - Verification test of given ROM File without flashing BIOS.
|
| Options:
|
|
/P - Program main BIOS image
|
|
/B - Program Boot Block
|
|
/N - Program NVRAM
|
|
/E - Program Embedded Controller Block
|
|
/K - Program all non-critical blocks
|
|
/Kn - Program n'th non-critical block only(n=0-7)
|
|
/Q - Silent execution
|
|
/REBOOT - Reboot after programming
|
|
/X - Don't Check ROM ID
|
|
/S - Display current system's ROMID
|
|
/R - Preserve ALL SMBIOS structure during NVRAM programming
|
|
/Rn - Preserve SMBIOS type N during BB programming(n=0-255)
|
|
/ECUF - Update EC BIOS when newer version is detected.
|
| /SHUTDOWN - Shutdown after programming.
|
+---------------------------------------------------------------------------+
C:\7300>
9.2.3.1 BIOS Update Example
Normally, you would run the update using the flags shown below.
A:\afudos AMIBIOS.BIN /P /B /N /R
AMI Firmware Update Utility Ver.2.23
Copywrite C(2007) American Megatrends Inc. All Rights reserved
-
Bootblock checksum ....
Module checksum .......
Erasing flash..........
writing flash .........
verifying flash .......
Erasing NVRAM .........
Writing NVRAM .........
Verifying NVRAM .......
Erasing bootblock .....
writing bootblock .....
verifying bootblock ...
CMOS checksum destroyed
program ended normally
ok
ok
done
done
done
done
done
done
done
done
done
A:
SB-ATCA7300 Installation and Use Guide
9-3
SB-ATCA7300 Firmware Updates
If a BIOS update fails, you can just rerun the update operation. Do not power off
the blade; this may leave a corrupted BIOS image on the blade. While the blade
has a backup BIOS image, it is always best to have two functional images. (For
imformation on the backup image, see section 5.3.23 “Dual BIOS Flash Devices”
on page 5-10 and section 5.3.1 “BIOS Update and Recovery” on page 5-2 for
more information on BIOS recovery.)
If the BIOS update continually fails, or the blade is no longer able to boot, contact
your support provider.
9.3 Updating the IPMC Firmware
The SB-ATCA7300 IPM Controller (IPMC) is fully HPM.1 compatible and
contains three firmware components as shown in the figure below.
Figure 9-1 IPMC Component Elements
These components are the boot loader, which loads the IPMC operational
firmware, and two copies of the operational firmware, the active and backup
images. The active and backup images may be identical or different, depending on
the blade’s firmware update history.
The boot loader itself does not perform any update action. The boot loader is used
to boot either of the two copies of the operational firmware in the flash PROM,
based on a status byte that is stored in the IPMC’s EEPROM. It is also responsible
for detecting if the active firmware is invalid or has failed. If the active firmware
failed or is invalid, the boot loader will try to load the backup image.
Note - If necessary, you can manually force the blade to use the firmware image
from a specific flash PROM location. See the descriptions of switches SW2-2 and
SW2-3 (FPGA) and SW3-1 and SW3-2 (BIOS) in section 3.4 “Board Control
Switch Settings” on page 3-5.
When updating, the new firmware is loaded into the current backup firmware
location, then booted. If the new image boots successfully, the prior active image
is marked as the backup image, and the newly updated image is set active.
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9-4
SB-ATCA7300 Firmware Updates
9.3.1 Installing ipmitool
You will need to use ipmitool to update the IPMC firmware images.
Install the ipmitool utility as shown in section 7.2 “Installing ipmitool” on
page 7-2.
9.3.2 Determining the Current IPMC Firmware Version
There are two different ways to determine the current IPMC firmware version.
9.3.2.1 From the Shelf Manager
You can determine the current IPMC firmware version by using the board -v
(or fru -v) command.
CLI> board -v 9
Physical Slot # 9
88: Entity: (0xa0, 0x60) Maximum FRU device ID: 0x01
PICMG Version 2.3
Hot Swap State: M4 (Active), Previous: M3 (Activation In Process),
Last State Change Cause: Normal State Change (0x0)
Device ID: 0x00, Revision: 0, Firmware: 2.01, IPMI ver 1.5
Manufacturer ID: 0076a4, Product ID: 0730, Auxiliary Rev: 00000004
Device ID String: "SB-ATCA7300"
CLI>
The underlined text above identifies the IPMC firmware as version 2.0.1 (from the
2.01). The IPMI ver. field identifies the IPMC as supporting the IPMI version
1.5 specification.
9.3.2.2 Using ipmitool
You can also obtain the version of the currently active IPMC firmware by using
ipmitool hpm check.
$ ipmitool hpm check
PICMG HPM.1 Upgrade Agent 1.0.2:
-------Target Information------Device Id
: 0x0
Device Revision
: 0x80
Product Id
: 0x0730
Manufacturer Id
: 0x76a4 (Unknown (0x76A4))
--------------------------------|ID | Name
|
Versions
|
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9-5
SB-ATCA7300 Firmware Updates
|
|
| Active| Backup|
--------------------------------|*0 |H8S-AMCc F/| 2.02 |127.ff |
| 1 |H8S-AMCc B/| 2.02 | --.-- |
| 2 |H8S-AMCc F/| 0.00 | --.-- |
| 3 |H8S-AMCc F/| 0.00 | --.-- |
| 4 |FPGA
| 0.00 | --.-- |
| 5 |BIOS
| 1.00 | --.-- |
| 6 |BIOS
| 0.00 | --.-- |
--------------------------------(*) Component requires Payload Cold Reset
$
9.3.3 HPM.1 Firmware Update of the IPMC
To update the SB-ATCA7300 IPMC flash images, it is recommended that you use
the Pigeon Point Systems modified ipmitool. The firmware images are
packaged following the PICMG HPM.1 standard.
9.3.4 Update Package
The HPM.1-format IPMC update package contains the following files:
Table 9-3 IPMC HPM.1 Update Package
Filename
Description
atca7300_boot_xx_xx_xxxx_xxxx.hpm
HPM file contains only the boot loader image
atca7300_ipmc_xx_xx_xxxx_xxxx.hpm
HPM file contains only the firmware image
There are firmware update images provided for both the boot loader and the
operational firmware. There is also a combined image containing both the boot
loader and the operational firmware. A boot loader update is rarely needed, and it
should be updated only if required, as directed in the firmware version’s Release
Notes.
9.3.5 Basic Update Commands
ipmitool uses a two-step process for an HPM.1 update:
1. Update the IPMC backup firmware image.
prompt> ipmitool hpm upgrade fw_file
2. Reboot the IPMC to activate the new firmware image, switching the backup
and active images.
prompt> ipmitool hpm activate
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9-6
SB-ATCA7300 Firmware Updates
9.3.5.1 IPMC Update Example
Both steps can be performed in one command.
prompt> ipmitool hpm upgrade fw_file activate
Here is an example showing separate upgrade and activate commands.
$ ipmitool hpm upgrade atca7300_ipmc_02_02_00ff_B00ff.hpm
PICMG HPM.1 Upgrade Agent 1.0.2:
Validating firmware image integrity...OK
Performing preparation stage...OK
Performing upgrade stage:
------------------------------------------------------------------------------|ID | Name
|
Versions
|
Upload Progress | Upload| Image |
|
|
| Active| Backup| File |0%
50%
100%| Time | Size |
|---|-----------|-------|-------|-------||----+----+----+----||-------|-------|
|*0 |H8S-AMCc F/| 2.02 |127.ff | 2.02 ||...................|| 02.40 | 35f85 |
------------------------------------------------------------------------------(*) Component requires Payload Cold Reset
Firmware upgrade procedure successful
$ ipmitool hpm activate
PICMG HPM.1 Upgrade Agent 1.0.2:
Performing activation stage:
Firmware upgrade procedure successful
$
9.3.6 ipmitool Update Interfaces
The HPM.1 update mechansim can use three different interfaces to update blade
firmware. These are the KCS (Keyboard Controller Style) interface, the Shelf
Manager, and using Ethernet directly to the blade’s IPMC.
The Ethernet interface is only supported if the blade is fully powered on. (The
blade must be in state M4.) The shelf’s switch (hub) blade(s) must also be active..
9.3.6.1 Using the Local KCS Interface
The common way to update the firmware of the payload is through the KCS
interface running on the blade itself. Update through this interface is the fastest
HPM.1 update. This method requires the blade OS to be running; it cannot be
performed from the BIOS.
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9-7
SB-ATCA7300 Firmware Updates
ipmitool must be installed on the blade to be updated, the firmware images
must be present, and the OS IPMI driver must be active.
prompt> ipmitool hpm upgrade fw_file
prompt> ipmitool hpm activate
9.3.6.2 Using the Shelf Manager
This interface uses the shelf IPMI bus between the Shelf Manager and the bladed,
and allows remote firmware update. The number of simultaneous updates is
limited because of the limited IPMB bus speed.
Running ipmitool on the Shelf Manager itself.
prompt> ipmitool -t 0x92 hpm upgrade fw_file
Example using RMCP from a remote client to the Shelf Manager. The IP address
(-H), the user ID (-U), and password (-P) are those of the Shelf Manager. The
-t operand designates the address of the blade being updated (in this example,
slot 3.)
prompt> ipmitool -I lan -H 192.168.34.8 -U root -P smpass -t 0x92 hpm
upgrade fw_file
prompt> ipmitool -I lan -H 192.168.34.8 -U root -P smpass -t 0x92 hpm
activate
9.3.6.3 Using IPMI over Ethernet (Base Network)
The IPMI over Ethernet interface uses the Base Ethernet network to perform the
firmware updates. The blade IPMC’s SOL environment must already be
configured. Configuring this interface is described in Chapter 7, "Serial Over
LAN".
The IP address (-H), the user ID (-U), and password (-P) are those for the
IPMC’s null user.
This example combines the upgrade and activate commands.
prompt> ipmitool -I lan -H 172.16.0.221 -U "" -P "" hpm upgrade fw_file
activate
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9-8
Appendix A Replacing the Blade Battery
A.1 Replacing the Battery
The SB-ATCA7300 has an on-board battery. Its location is shown in the
following figure.
Battery
Figure A-1 Location of On-board Battery
The battery type is CR-2032.
The battery provides configuration data retention for up to seven years, including
all periods of actual blade use. There is usually no need to replace the battery
except, for example, in case of long-term spare part storage.
WARNING - Incorrect replacement of lithium batteries can result in a
hazardous explosion. Ensure that the battery is replaced as described in this
appendix.
CAUTION - If the battery does not provide enough power, the Real Tiem Clock
is reset and the configuration data in the NVRAM is lost. To avoid this, replace
the battery before seven years of actual battery use have elapsed.
CAUTION - Replacing the battery always results in data loss of the data which
uses battery power for retention. Back up ant affected data before replacing the
battery.
SB-ATCA7300 Installation and Use Guide
A-1
Replacing the Blade Battery
The figure below shows the battery placement. Note that the positive side of the
battery is facing up.
Figure A-2 Battery Location Detail
A.2 Replacement Procedure
To replace the CR-2032 battery, proceed as follows:
1. Remove the VGA module. See section 3.6.4.2 “Removing the VGA Module”
on page 3-17.
1. Remove the installed battery by pushing down on the battery retainer button at
the bottom of the battery container and lifting out the old battery.
CAUTION - Improperly removing the battery may damage the circuit board or
the battery holder. To prevent this damage, do not use a screwdriver to remove the
battery from its holder.
2. Pop the new battery into position with the + side facing up.
3. Reinstall the VGA module. See section 3.6.4.1 “Installing the VGA Module”
on page 3-17.
4. Dispose of the old battery properly.
SB-ATCA7300 Installation and Use Guide
A-2
Appendix B BIOS Status Codes
B.1 BIOS Status Codes
The following tables list the BIOS status codes applicable to the AMI Aptio UEFI
(Unified Extensible Firmware Interface) BIOS. The BIOS status codes are
written to the blade's I/O Port 80 register and can be obtained by reading the
POST code on-board IPMI sensor.
The reading of the POST code sensor is only valid when the board is in the BIOS
initialization phase. The sensor value can be used to locate the cause of a board
hang during BIOS initialization. When the blade has booted an OS, the POST
code sensor’s status code value is invalid.
B.1.1 Status Code Ranges
The BIOS status codes are subdivided into ranges, which indicate which BIOS
component has issued the code.
Table B-1 Status Code Ranges
Range
Description
0x01 - 0x0F
SEC Status Codes & Errors
0x10 - 0x2F
PEI execution up to and including memory detection
0x30 - 0x4F
PEI execution after memory detection
0x50 - 0x5F
PEI errors
0x60 - 0xCF
DXE execution up to BDS
0xD0 - 0xDF DXE errors
0xE0 - 0xE8
S3 Resume (PEI)
0xE9 - 0xEF
S3 Resume errors (PEI)
0xF0 - 0xF8
Recovery (PEI)
0xF9 - 0xFF
Recovery errors (PEI)
Table Location
Table B-2 on page 2
Table B-3 on page 2
Table B-5 on page 5
Table B-3 on page 2
For information on the BIOS components, see Chapter 5, "BIOS Configuration".
SB-ATCA7300 Installation and Use Guide
B-1
BIOS Status Codes
B.1.2 Standard Status Codes
B.1.2.1 Security (SEC) Status Codes
Table B-2 SEC Status Codes
Status Code
0x0
Description
Not used
Progress Codes
0x1
Power on. Reset type detection (soft/hard)
0x2
AP initialization before microcode loading
0x3
North Bridge initialization before microcode loading
0x4
South Bridge initialization before microcode loading
0x5
OEM initialization before microcode loading
0x6
Microcode loading
0x7
AP initialization after microcode loading
0x8
North Bridge initialization after microcode loading
0x9
South Bridge initialization after microcode loading
0xA
OEM initialization after microcode loading
0xB
Cache initialization
SEC Error Codes
0xC - 0xD
Reserved for future AMI SEC error codes
0xE
Microcode not found
0xF
Microcode not loaded
B.1.2.2 Security (SEC) Beep Codes
None
B.1.2.3 PEI Status Codes
Table B-3 PEI Status Codes
Status Code
Description
Progress Codes
0x10
PEI Core is started
0x11
Pre-memory CPU initialization is started
0x12
CPU pre-memory initialization (CPU module specific)
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B-2
BIOS Status Codes
Table B-3 PEI Status Codes (Continued)
Status Code
Description
0x13
CPU pre-memory initialization (CPU module specific)
0x14
CPU pre-memory initialization (CPU module specific)
0x15
Pre-memory North Bridge initialization is started
0x16
Pre-Memory North Bridge initialization (North Bridge module specific)
0x17
Pre-Memory North Bridge initialization (North Bridge module specific)
0x18
Pre-Memory North Bridge initialization (North Bridge module specific)
0x19
Pre-memory South Bridge initialization is started
0x1A
Pre-memory South Bridge initialization (South Bridge module specific)
0x1B
Pre-memory South Bridge initialization (South Bridge module specific)
0x1C
Pre-memory South Bridge initialization (South Bridge module specific)
0x1D - 0x2A
OEM pre-memory initialization codes
0x2B
Memory initialization. Serial Presence Detect (SPD) data reading
0x2C
Memory initialization. Memory presence detection
0x2D
Memory initialization. Programming memory timing information
0x2E
Memory initialization. Configuring memory
0x2F
Memory initialization (other).
0x30
Reserved for ASL (see ASL Status Codes section below)
0x31
Memory Installed
0x32
CPU post-memory initialization is started
0x33
CPU post-memory initialization. Cache initialization
0x34
CPU post-memory initialization. Application Processor(s) (AP)
initialization
0x35
CPU post-memory initialization. Boot Strap Processor (BSP) selection
0x36
CPU post-memory initialization. System Management Mode (SMM)
initialization
0x37
Post-Memory North Bridge initialization is started
0x38
Post-Memory North Bridge initialization (North Bridge module specific)
0x39
Post-Memory North Bridge initialization (North Bridge module specific)
0x3A
Post-Memory North Bridge initialization (North Bridge module specific)
0x3B
Post-Memory South Bridge initialization is started
0x3C
Post-Memory South Bridge initialization (South Bridge module specific)
0x3D
Post-Memory South Bridge initialization (South Bridge module specific)
SB-ATCA7300 Installation and Use Guide
B-3
BIOS Status Codes
Table B-3 PEI Status Codes (Continued)
Status Code
Description
0x3E
Post-Memory South Bridge initialization (South Bridge module specific)
0x3F-0x4E
0x4F
OEM post memory initialization codes
DXE IPL is started
PEI Error Codes
0x50
Memory initialization error. Invalid memory type or incompatible
memory speed
0x51
Memory initialization error. SPD reading has failed
0x52
Memory initialization error. Invalid memory size or memory modules do
not match.
0x53
Memory initialization error. No usable memory detected
0x54
Unspecified memory initialization error.
0x55
Memory not installed
0x56
Invalid CPU type or Speed
0x57
CPU mismatch
0x58
CPU self test failed or possible CPU cache error
0x59
CPU micro-code is not found or micro-code update is failed
0x5A
Internal CPU error
0x5B
reset PPI is not available
0x5C-0x5F
Reserved for future AMI error codes
S3 Resume Progress Codes
0xE0
S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)
0xE1
S3 Boot Script execution
0xE2
Video repost
0xE3
OS S3 wake vector call
0xE4-0xE7
0xE0
Reserved for future AMI progress codes
S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)
S3 Resume Error Codes
0xE8
S3 Resume Failed in PEI
0xE9
S3 Resume PPI not Found
0xEA
S3 Resume Boot Script Error
0xEB
S3 OS Wake Error
0xEC-0xEF
Reserved for future AMI error codes
SB-ATCA7300 Installation and Use Guide
B-4
BIOS Status Codes
Table B-3 PEI Status Codes (Continued)
Status Code
Description
Recovery Progress Codes
0xF0
Recovery condition triggered by firmware (Auto recovery)
0xF1
Recovery condition triggered by user (Forced recovery)
0xF2
Recovery process started
0xF3
Recovery firmware image is found
0xF4
Recovery firmware image is loaded
0xF5 - 0xF7
Reserved for future AMI progress codes
Recovery Error Codes
0xF8
Recovery PPI is not available
0xF9
Recovery capsule is not found
0xFA
Invalid recovery capsule
0xFB - 0xFF
Reserved for future AMI error codes
B.1.2.4 PEI Beep Codes
Table B-4 PEI Beep Codes
# of
Beeps
Description
1
Memory not Installed
1
Memory was installed twice (InstallPeiMemory routine in PEI
Core called twice)
3
DXEIPL was not found
3
DXE Core Firmware Volume was not found
7
Reset PPI is not available
4
Recovery failed
4
S3 Resume failed
B.1.2.5 DXE Status Codes
Table B-5 DXE Status Codes
Status Code
Description
0x60
DXE Core is started
0x61
NVRAM initialization
SB-ATCA7300 Installation and Use Guide
B-5
BIOS Status Codes
Table B-5 DXE Status Codes (Continued)
Status Code
Description
0x62
Installation of the South Bridge Runtime Services
0x63
CPU DXE initialization is started
0x64
CPU DXE initialization (CPU module specific)
0x65
CPU DXE initialization (CPU module specific)
0x66
CPU DXE initialization (CPU module specific)
0x67
CPU DXE initialization (CPU module specific)
0x68
PCI host bridge initialization
0x69
North Bridge DXE initialization is started
0x6A
North Bridge DXE SMM initialization is started
0x6B
North Bridge DXE initialization (North Bridge module specific)
0x6C
North Bridge DXE initialization (North Bridge module specific)
0x6D
North Bridge DXE initialization (North Bridge module specific)
0x6E
North Bridge DXE initialization (North Bridge module specific)
0x6F
North Bridge DXE initialization (North Bridge module specific)
0x70
South Bridge DXE initialization is started
0x71
South Bridge DXE SMM initialization is started
0x72
South Bridge devices initialization
0x73
South Bridge DXE Initialization (South Bridge module specific)
0x74
South Bridge DXE Initialization (South Bridge module specific)
0x75
South Bridge DXE Initialization (South Bridge module specific)
0x76
South Bridge DXE Initialization (South Bridge module specific)
0x77
South Bridge DXE Initialization (South Bridge module specific)
0x78
ACPI module initialization
0x79
CSM initialization
0x7A - 0x7F
Reserved for future AMI DXE codes
0x80 - 0x8F
OEM DXE initialization codes
0x90
Boot Device Selection (BDS) phase is started
0x91
Driver connecting is started
0x92
PCI Bus initialization is started
0x93
PCI Bus Hot Plug Controller Initialization
0x94
PCI Bus Enumeration
0x95
PCI Bus Request Resources
SB-ATCA7300 Installation and Use Guide
B-6
BIOS Status Codes
Table B-5 DXE Status Codes (Continued)
Status Code
Description
0x96
PCI Bus Assign Resources
0x97
Console Output devices connect
0x98
Console input devices connect
0x99
Super IO Initialization
0x9A
USB initialization is started
0x9B
USB Reset
0x9C
USB Detect
0x9D
USB Enable
0x9E - 0x9F
Reserved for future AMI codes
0xA0
Reserved for ASL (see ASL Status Codes section below)
0xA1
IDE initialization is started
0xA2
IDE Reset
0xA3
IDE Detect
0xA4
IDE Enable
0xA5
SCSI initialization is started
0xA6
SCSI Reset
0xA7
SCSI Detect
0xA8
SCSI Enable
0xA9
Setup Verifying Password
0xAA
Reserved for ASL (see ASL Status Codes section below)
0xAB
Start of Setup
0xAC
Setup Input Wait
0xAD
Ready To Boot event
0xAE
Legacy Boot event
0xAF
Exit Boot Services event
0xB0
Runtime Set Virtual Address MAP Begin
0xB1
Runtime Set Virtual Address MAP End
0xB2
Legacy Option ROM Initialization
0xB3
System Reset
0xB4
USB hot plug
0xB5
PCI bus hot plug
0xB6
Clean-up of NVRAM
SB-ATCA7300 Installation and Use Guide
B-7
BIOS Status Codes
Table B-5 DXE Status Codes (Continued)
Status Code
0xB7
Description
Configuration Reset (reset of NVRAM settings)
0xB8 - 0xBF
Reserved for future AMI codes
0xC0 - 0xCF
OEM BDS initialization codes
DXE Error Codes
0xD0
CPU initialization error
0xD1
North Bridge initialization error
0xD2
South Bridge initialization error
0xD3
Some of the Architectural Protocols are not available
0xD4
PCI resource allocation error. Out of Resources
0xD5
No Space for Legacy Option ROM
0xD6
No Console Output Devices are found
0xD7
No Console Input Devices are found
0xD8
Invalid password
0xD9
Error loading Boot Option (LoadImage returned error)
0xDA
Boot Option is failed (StartImage returned error)
0xDB
Flash update is failed
0xDC
Reset protocol is not available
B.1.2.6 DXE Beep Codes
Table B-6 DXE Beep Codes
# of Beeps
Description
1
Invalid password
4
Some of the Architectural Protocols are not available
5
No Console Output Devices are found
5
No Console Input Devices are found
6
Flash update is failed
7
Reset protocol is not available
SB-ATCA7300 Installation and Use Guide
B-8
BIOS Status Codes
B.1.2.7 CPU Exception Status Codes
Table B-7 CPU Exception Status Codes
Status Code
Description
0x00
Divide error
0x01
CPU Debug exception
0x02
Non Maskable hardware Interrupt occurred
0x03
INT 3 breakpoint
0x04
Overflow, INT 0 instruction
0x05
Bound Range Exceeded
0x06
Invalid OpCode (undefined OpCode)
0x07
Device Not Available ( No Math Co-Processor)
0x08
Double Fault. Any instruction to the CPU that can Generate an NMI or INTR
0x09
Co-Processor Segment Overrun
0x0A
Invalid Task Switch Access
0x0B
Segment not present. Occurs after a load segment
0x0C
Stack Segment Fault. Relations to Stack operations
0x0D
General Protection fault. Any memory reference and other protection checks
0x0E
Page Fault.
0x0F
Reserved by Intel
0x10
Floating Point Error
0x11
Alignment Check
0x12
Machine Check
0x13
SIMD Floating point exception
B.1.2.8 CPU Exception Beep Codes
None
B.1.2.9 ASL Status Codes
Table B-8 ASL Status Codes
Status Code
Description
0x01
System is entering S1 sleep state
0x02
System is entering S2 sleep state
0x03
System is entering S3 sleep state
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B-9
BIOS Status Codes
Table B-8 ASL Status Codes (Continued)
Status Code
Description
0x04
System is entering S4 sleep state
0x05
System is entering S5 sleep state
0x10
System is waking up from the S1 sleep state
0x20
System is waking up from the S2 sleep state
0x30
System is waking up from the S3 sleep state
0x40
System is waking up from the S4 sleep state
0xAC
System has transitioned into ACPI mode. Interrupt controller is in PIC mode.
0xAA
System has transitioned into ACPI mode. Interrupt controller is in APIC
B.1.2.10 OEM-Reserved Status Code Ranges
Table B-9 OEM-Reserved Status Code Ranges
Status Code
Description
0x5
OEM SEC initialization before microcode loading
0xA
OEM SEC initialization after microcode loading
0x1D - 0x2A
OEM pre-memory initialization codes
0x3F - 0x4E
OEM PEI post memory initialization codes
0x80 - 0x8F
OEM DXE initialization codes
0xC0 - 0xCF
OEM BDS initialization codes
B.1.3 Network Device PCIe Addresses
All vendor device types are Ethernet controller.
Table B-10 Network Device PCIe Addresses
PHY_NAME
NIC
Bus
Dev
Func
Branding String
frontnet
1
00:19.0 8086-10CC Intel 82567LM-2 Gigabit Network
base1
2
01:00.0 8086-1521
Intel I350 device 1521 (rev 01)
base2
3
01:00.1 8086-1521
Intel I350 device 1521 (rev 01)
rtm1
4
01:00.2 8086-1521
Intel I350 device 1521 (rev 01)
rtm2
5
01:00.3 8086-1523
Intel I350 device 1523 (rev 01)
fabric1
6
04:00.0 8086-10FC
Intel 82599EB 10-Gigabit XAUI/BX4
Network Connection (rev 01)
SB-ATCA7300 Installation and Use Guide
B-10
BIOS Status Codes
Table B-10 Network Device PCIe Addresses (Continued)
PHY_NAME
NIC
fabric2
Bus
7
Dev
Func
04:00.1 8086-10FC
SB-ATCA7300 Installation and Use Guide
Branding String
Intel 82599EB 10-Gigabit XAUI/BX4
Network Connection (rev 01)
B-11
BIOS Status Codes
SB-ATCA7300 Installation and Use Guide
B-12
Appendix C Supported IPMI Commands
C.1 Standard IPMI Commands
The SB-ATCA7300 IPMC is fully compliant with the Intelligent Platform
Management Interface (IPMI) version 1.5 specification. This section provides
information about the IPMI commands supported by the blade IPMC.
C.1.1 Global IPMI Commands
The IPMC supports the following global IPMI commands.
Table C-1 Supported Global IPMI Commands
NetFn
(Request/Response)
CMD
Comments
Get Device ID
0x06/0x07
0x01
-
Cold Reset
0x06/0x07
0x02
-
Warm Reset
0x06/0x07
0x03
-
Get Self Test Results
0x06/0x07
0x04
-
Get Device GUID
0x06/0x07
0x08
-
Master Write-Read
0x06/0x07
0x52
Only for accessing private I2C buses.
Command
C.1.2 System Interface
The system interface commands control IPMC access configuration information.
Table C-2 Supported System Interface Commands
Command
NetFn
CMD
(Request/Response)
Set BMC Global Enables
0x06/0x07
0x2E
Get BMC Global Enables
0x06/0x07
0x2F
Clear Message Flags
0x06/0x07
0x30
Get Message Flags
0x06/0x07
0x31
Get Message
0x06/0x07
0x33
Send Message
0x06/0x07
0x34
Set Channel Access
0x06/0x07
0x40
Get Channel Access
0x06/0x07
0x41
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C-1
Supported IPMI Commands
Table C-2 Supported System Interface Commands (Continued)
NetFn
CMD
(Request/Response)
Command
Get Channel Info
0x06/0x07
0x42
Set User Access
0x06/0x07
0x43
Get User Access
0x06/0x07
0x44
Set User Name
0x06/0x07
0x45
Get User Name
0x06/0x07
0x46
Set User Password
0x06/0x07
0x47
Set User Payload Access
0x06/0x07
0x4C
Get User Payload Access
0x06/0x07
0x4D
Set Channel Security Keys
0x06/0x07
0x5C
C.1.3 Watchdog Commands
The watchdog commands are supported by blades providing a system interface
and a watchdog type 2 sensor.
The options pre-timeout and power-cycle are not supported.
Table C-3 Supported Watchdog Commands
Command
NetFn
(Request/Response)
CMD
Reset Watchdog Timer
0x06/0x07
0x22
Set Watchdog Timer
0x06/0x07
0x24
Get Watchdog Timer
0x06/0x07
0x25
C.1.4 SEL Device Commands
The SEL device commands manage the System Event Log (SEL).
Table C-4 Supported SEL Device Commands
Command
NetFn
(Request/Response)
CMD
Get SEL Info
0x0A/0x0B
0x40
Reserve SEL
0x0A/0x0B
0x42
Get SEL Entry
0x0A/0x0B
0x43
Add SEL Entry
0x0A/0x0B
0x44
SB-ATCA7300 Installation and Use Guide
C-2
Supported IPMI Commands
Table C-4 Supported SEL Device Commands (Continued)
NetFn
Command
(Request/Response)
CMD
Clear SEL
0x0A/0x0B
0x47
Get SEL Time
0x0A/0x0B
0x48
Set SEL Time
0x0A/0x0B
0x49
C.1.5 FRU Data Commands
Table C-5 Supported FRU Data Commands
NetFn
Command
(Request/Response)
CMD
Get FRU Inventory Area Info
0x0A/0x0B
0x10
Read FRU Data
0x0A/0x0B
0x11
Write FRU Data
0x0A/0x0B
0x12
C.1.6 Sensor Device Commands
Table C-6 Supported Sensor Device Commands
Command
NetFn
(Request/Response)
CMD
Comments
Get Device SDR Info
0x04/0x05
0x20
-
Get Device SDR
0x04/0x05
0x21
-
Reserve Device SDR
Repository
0x04/0x05
0x22
-
Get Sensor Reading Factors
0x04/0x05
0x23
-
Set Sensor Hysteresis
0x04/0x05
0x24
-
Get Sensor Hysteresis
0x04/0x05
0x25
-
Set Sensor Threshold
0x04/0x05
0x26
Most of the thresholdbased sensors have fixed
thresholds. Before using
this command, check
whether threshold setting is
supported by using the Get
Device SDR command.
Get Sensor Threshold
0x04/0x05
0x27
-
Set Sensor Event Enable
0x04/0x05
0x28
-
SB-ATCA7300 Installation and Use Guide
C-3
Supported IPMI Commands
Table C-6 Supported Sensor Device Commands (Continued)
NetFn
Command
(Request/Response)
CMD
Comments
Get Sensor Event Enable
0x04/0x05
0x29
-
Get Sensor Event Status
0x04/0x05
0x2B
-
Get Sensor Reading
0x04/0x05
0x2D
-
Get Sensor Type
0x04/0x05
0x2F
-
Set Event Receiver
0x04/0x05
0x00
-
Get Event Receiver
0x04/0x05
0x01
-
Platform Event
0x04/0x05
0x02
-
C.1.7 Chassis Device Commands
Table C-7 Supported Chassis Device Commands
Command
NetFn (Request/Response)
CMD
Set System Boot Options
0x00/0x01
0x08
Get System Boot Options
0x00/0x01
0x09
C.1.7.1 System Boot Options Commands
The IPMI system boot options commands allow you to control the boot process of
a blade by sending boot parameters to the blade’s boot firmware (for example
BIOS, U-Boot, Linux or VxWorks). The boot firmware interprets the provided
boot parameters and executes the boot process accordingly. Each boot parameter
addresses a particular functionality and consists of a sequence of one or more
bytes. The IPMI specification assigns numbers to boot parameters. Boot
parameters 0 to 7 are standard parameters whose structure and functionality is
defined by the IPMI specification. Boot parameters 96 to 127 are OEM-specific
which can be used for different purposes.
When using the Get/Set System Boot Options commands, except for parameter
100, use the response/request data fields with the Set Selector and the Block
Selector both set to 0x00. When using the Get/Set System Boot Option for the
parameter 100, the Set Selector and the Block Selector have specific meanings.
Details are given in section C.1.7.1.4 “System Boot Options Parameter #100” on
page C-7 for details.
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C-4
Supported IPMI Commands
The following table lists which boot properties can be configured and the
corresponding boot parameter number.
Table C-8 Configurable System Boot Option Parameters
Configurable Boot Property
Corresponding Boot
Parameter Number
Selection between default and backup boot flash as device to
boot
Selection between the default and backup EEPROM as
device where the on-board FPGA loads its configuration
stream
96
IPMC POST Type
97
Timeout for graceful shutdown
98
BIOS boot parameters as defined in Table C-15 on page C10
100
C.1.7.1.1 System Boot Options Parameter #96
This boot parameter is a SANBlaze-specific OEM boot parameter. Its definition is
given in the following table.
Table C-9 System Boot Options Parameter #96
Data Byte
Description
Bits 7..2: Reserved
1
Bit 1: FPGA configuration stream load
0: Load configuration stream from default boot flash
1: Load configuration stream from backup boot flash
Note: The new FPGA configuration stream is loaded into the FPGA at
the next power-up of the payload.
Bit 0: Default/backup boot flash selection
0: Boot from default boot flash
1: Boot from backup boot flash
The newly selected boot flash is connected to the payload immediately,
that means writing to the flash is possible. Its image is executed after the
next power-up or cold reset of the payload.
System Boot Options parameter #96 is non-volatile. During blade production, its
data is initialized to 0xFF and its state is set to invalid. This parameter data
remains preserved after IPMC power cycles and firmware updates.
SB-ATCA7300 Installation and Use Guide
C-5
Supported IPMI Commands
C.1.7.1.2 System Boot Options Parameter #97
This boot parameter is a SANBlaze-specific OEM parameter. Its definition is
given in the following table.
Table C-10 System Boot Options Parameter #97
Data Byte
Description
1
IPMC POST Type
Data 1 - Set Selector. This is the processor ID for which the boot
option is to be set.
2
Data 2 - IPMC POST Type Selector. This parameter is used to
specify the IPMC POST Type that the IPMC will execute.
0x00: Short POST
0x01: Long POST
0x02 to 0xFF: Not used
System Boot Options parameter #97 is non-volatile. During blade production, its
data is initialized to 0xFF and its state is set to invalid. Its parameter data is
preserved after IPMC power cycles and firmware updates.
The System Boot Options parameter #97 is only valid for the IPMC.
C.1.7.1.3 System Boot Options Parameter #98
This boot parameter is a SANBlaze-specific OEM parameter.
This timer specifies how long the IPMC waits for the payload to shut down
gracefully. If the payload software does not configure its OpenIPMI library to be
notified for graceful shutdown requests, the IPMC shuts down the payload when
the timer expires.
Table C-11 System Boot Options Parameter #98
Bit
Description
15:8 Timeout for GRACEFUL_SHUTDOWN, LSB (given in 100 msec)
7:0
Timeout for GRACEFUL_SHUTDOWN, MSB (given in 100 msec)
System Boot Options parameter #98 is non-volatile. During blade production its
data is initialized to 0xFF and its state is set to invalid. Its parameter data is
preserved after IPMC power cycles and firmware updates.
SB-ATCA7300 Installation and Use Guide
C-6
Supported IPMI Commands
C.1.7.1.4 System Boot Options Parameter #100
System boot options parameter #100 allows you to send multiple boot options to
the blade’s boot firmware and thus control the boot process. The boot options
which you can configure using this parameter are typically a subset of the boot
options which you can configure in the boot firmware directly, for example, using
a setup menu.
The IPMC contains a storage area where the boot parameters are stored. When the
blade boots, the boot firmware reads out the storage area, interprets the parameters
and executes the boot process accordingly. Note that the boot parameters in the
IPMC storage area have higher priority than the same boot options which may be
configured in the firmware itself, for example, using the setup menu.
The storage area is divided into two parts: the default area and the user area. The
user area can be read and written by an IPMI user and by default is, the area which
the boot firmware reads out and uses during the boot process. The default area can
only be read by both the IPMI user and the boot firmware. Its purpose is to store
factory-programmed default boot options which can be used to restore the
standard settings. If you want the boot firmware to read out and use the boot
parameters stored in the default area and thus use the factory settings, you need to
configure the blade accordingly. This is typically done by an on-board switch (for
example, "Clear CMOS RAM"). It depends on the blade and firmware which
settings are stored in the default area. Details are given in the following sections.
Changing a boot parameter in the firmware setup menu will usually change the
boot parameter in the user area as well, if the same parameter is defined both in
the user area and the set-up menu. Details are given below.
The following figure summarizes the previously explained basic information flow
related to the system boot options parameter #100.
Figure C-3 System Boot Options Parameter #100 - Information Flow Overview
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C-7
Supported IPMI Commands
The boot options need to be stored as a sequence of zero terminated strings. The
following table describes in detail the format of the boot options to be used when
setting or reading the System Boot Options parameter #100.
Table C-12 System Boot Options - Parameter #100 - Data Format
Byte
Description
0..1
Number of bytes used for boot parameters (LSB first)
The number of bytes must be calculated and written into these two bytes
by the software which writes into the storage area. The values 0x0000 and
0xFFFF indicate that no data has been written to the storage area. When
reading from the storage area and you find any of these two values, your
software should assume that no user-specific boot options have previously
been written to the storage area.
2 .. n
Boot parameters data
The boot parameters are stored as ASCII text with the following general
format: <name>=<value>, where all name/value pairs are separated by
a zero byte. The end of the boot parameter data is indicated by two zero
bytes. Allowed and supported name/value pairs are blade-specific. Details
are given below.
n + 1 .. n + 2 16 byte checksum over the boot parameters data section. (LSB first)
For backward compatibility reasons, the checksums 0x0000 and 0xFFFF
are accepted as valid. They indicate that no checksum has been calculated
and stored.
When writing to or reading from the storage area, you can only read or write
chunks of 16 bytes at a time. For this reason, the default and user area are divided
into numbered blocks of 16 bytes which need to be addressed individually. For
this purpose, the "Block Selector" field in the request data field is used. The "Set
Selector" field, on the other hand, is used to select either the default or user area.
The following two tables describe in detail how the request and response data
fields need to be filled and interpreted when performing SET and GET accesses.
Table C-13 System Boot Options Parameter #100 - SET Command Usage
Byte
Description
Request Data
1
Bit 7: when set to "1", the storage area on the IPMC is locked, i.e. no
other software can access it. This should be set, before doing any
modifications and cleared again after the final access.
Bits 6..0: must contain the value: "100", indicating this OEM system
boot option.
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C-8
Supported IPMI Commands
Table C-13 System Boot Options Parameter #100 - SET Command Usage (Continued)
Byte
Description
2
Set Selector
Must be set to "0" (user area). You can only write to the user area,
therefore no other values are supported.
3
Block Selector
Zero based index of the 16-byte block which you want to write to.
Index 0 refers to the first block of 16 bytes, which includes the first
two bytes that indicate the boot parameter data size.
Depending on the total length of the boot option data, the software
may need to write several blocks of 16 bytes in a row, each
individually addressed using the block selector.
4 .. n (n <= 19) Data that you want to write into the addressed block. This will be a
chunk of the boot parameter data. If less than 16 bytes are written,
then only the provided data is written, the remaining bytes in the
addressed storage area block are left unchanged.
Response Data
1
0x00: Write successful
0x80: Boot parameter storage not supported by the IPMC
0x81: Storage area is locked by another software entity
0x82: Illegal write-access
0xC9: Block selector is outside of the allowed range.
Use the following command to retrieve parameter 100 data.
Table C-14 System Boot Options Parameter #100 - GET Command Usage
Byte
Description
Request Data
1
Bit 7: reserved. Set to "0".
Bits 6..0: must contain the value: "100", indicating this OEM
system boot option.
2
Set Selector
0: User area
1: Default area
3
Block Selector
Zero based index of the 16-byte block which you want to read
from. Index 0 refers to the first block of 16 bytes, which includes
the first two bytes which indicate the boot parameter data size.
Response Data
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C-9
Supported IPMI Commands
Table C-14 System Boot Options Parameter #100 - GET Command Usage (Continued)
Byte
Description
1
0x00: Read successful
0x80: Boot parameter storage not supported by the IPMC
0xC9: Block selector is outside of the allowed range
2
Reserved. Set to "1".
3
Bit 7: If set to "1", the addressed storage area is locked
Bits 6 ..0: value "100", indicating this OEM boot option command
4 .. 19
The content of the read 16-byte block
In order to detect the maximum size of writable storage area, the software can
perform a series of read accesses while incrementing the block selector with each
access. Once the error code C9 is returned, the limit has been reached and the total
available space in the writable storage area can be easily determined by the
number of previously performed successful read accesses.
This is supported by HPI, for details refer to the System Management Interface
Based on HPI-B User’s Guide related to your system environment.
The following table lists boot parameters which can be configured for the SBATCA7300 blade, using the system boot option parameter #100.
When used in System Boot Options parameter #100, the boot parameters and their
values are case-sensitive.
All boot options listed in the following table are set by the BIOS setup menu and
can be configured using the System Boot options command #100. The IPMC and
BIOS software automatically synchronize the settings made in the BIOS setup
menu and the settings specified using the System Boot Options command #100.
Changing a parameter in either of these places automatically changes the
corresponding value in the other.
Table C-15 System Boot Options Parameter #100 - Supported Parameters
Parameter
Description
Values
artm_fc_boot
Boot from ARTM
FC device
off/on
artm_net_boot
Boot from ARTM
Network
off/on
artm_sas_boot
Boot from ARTM
SAS device
off/on
basenet_boot
Boot from Base
Network
off/on
baudrate
Console baud rate
9600/19200/57600/115200
SB-ATCA7300 Installation and Use Guide
C-10
Supported IPMI Commands
Table C-15 System Boot Options Parameter #100 - Supported Parameters (Continued)
Parameter
Description
Values
boot_order
Boot priority order
device1,device2,..device8
See Table C-16 on page C-11
frontnet_boot
Boot from Front
Panel interface
off/on
os_boot_watchdog
OS boot Watchdog
(IPMI)
on/off,timout in minutes,action
Timeout range 1,2,3,5,7,10,15,20
action: noaction/reset/poweroff/powercycle
Example: os_boot_watchdog=on,10,reset
-> watchdog is on, 10 minutes timeout, action=reset
rtm_auto
Auto detect ARTM
If enabled (on), the
parameter for 'Force
Gen1' and RTM
PCIe configuration
is set correctly.
on/off: auto detect on/off
gen1on/gen1off: Force Gen1 on/off
x4x4x4x4/x4x4x8/x8x4x4/x8x8/x16: PCIe bifurcation
uefi#
UEFI Media path
Format: NAME=DevicePath
This paramter contains a UEFI Device path in text
form. This parameter is saved at boot time. The
Installer from a UEFI compatible OS writes this
parameter to NVRAM and after the next reboot
BIOS stores this to IPMI boot parameter
usb
USB support
fp_on/fp_off,rtm_on/rtm_off,onboard_on/onboard_off
Example: rtm_auto=off,gen1on,x4x4x8
-> RTM auto detect on, Force Gen1 on, PCIe x4x4x8
Example: usb=fp_off,rtm_off,onboard_on
-> Front panel USB off, RTM USB off, Onboard
Flash USB on
The devices which can be specified from which the SB-ATCA7300 can boot are
listed in the table below.
Table C-16 boot_order Devices
Device
Description
basenet0
Base0 Network
basenet1
Base1 Network
efishell
Built in UEFI shell
frontnet
Front Panel Network
sas0_nn
SAS Controller nn = SCSI ID
(use this when a SAS array is connected to the ARTM)
sashdd
SAS HDD mounted on the RTM
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C-11
Supported IPMI Commands
Table C-16 boot_order Devices (Continued)
Device
Description
sata0
SATA device 0 (Debug SATA)
sata1
SATA device 1 (RTM Debug SATA)
sata5
SATA device 5 (Onboard SATA)
sataonboard
SATA device 5 (Onboard SATA)
uefi#
UEFI Media path place holder which points to the corresponding uefi#
parameter
uefibasenet0 UEFI Base Network 1
uefibasenet1 UEFI Base Network 2
uefifrontnet UEFI Front Panel Network
uefirtmnet1
UEFI RTM 1 Network
uefirtmnet2
UEFI RTM 2 Network
uefirtmnet3
UEFI RTM 3 Network
uefirtmnet4
UEFI RTM 4 Network
uefirtmnet5
UEFI RTM 5 Network
uefirtmnet6
UEFI RTM 6 Network
usb1
USB frontpanel 1
usb2
USB frontpanel 2
usbartm
USB artm
usbcdrom
USB cdrom
usbfdd
USB floppy disk
usbhdd
USB hdd
usbkey
USB key
usbonboard
USB onboard HDD
Up to 10 boot devices are supported.
Example: boot_order=sas0_03,basenet0,usbkey,sata1
Note: uefi network devices are only available when Network Stack in the Advanced Setup Menu is
set to enabled.
SB-ATCA7300 Installation and Use Guide
C-12
Supported IPMI Commands
C.1.8 LAN Device Commands
Table C-17 Supported LAN Device Commands
NetFn
CMD
(Request/Response)
Command
Set LAN Configuration Parameters
0x0C/0x0D
0x01
Get LAN Configuration Parameters
0x0C/0x0D
0x02
Set SOL Configuration Parameters
0x0C/0x0D
0x21
Get SOL Configuration Parameters
0x0C/0x0D
0x22
C.2 PICMG 3.0 Commands
The SANBlaze IPMC is a fully compliant AdvancedTCA IPMC. It supports all
required and mandatory AdvancedTCA commands as defined in the PICMG 3.0
R3.0 and AMC.0 R2.0 specifications.
Table C-18 Supported PICMG 3.0 Commands
Command
NetFn
CMD
(Request/Response)
Comments
Get PICMG Properties
0x2C/0x2D
0x00
-
Get Address Info
0x2C/0x2D
0x01
-
FRU Control
0x2C/0x2D
0x04
The blade supports the
cold reset and graceful
reboot options.
Get FRU LED Properties
0x2C/0x2D
0x05
-
Get FRU LED Color
Capabilities
0x2C/0x2D
0x06
-
Set FRU LED State
0x2C/0x2D
0x07
-
Get FRU LED State
0x2C/0x2D
0x08
-
Set IPMB State
0x2C/0x2D
0x09
-
Set FRU Activation Policy
0x2C/0x2D
0x0A
-
Get FRU Activation Policy
0x2C/0x2D
0x0B
-
Set FRU Activation
0x2C/0x2D
0x0C
-
Get Device Locator Record ID
0x2C/0x2D
0x0D
The SANBlaze IPMC
support the standard
PICMG 3.0 and the
extended AMC.0 R2.0
versions of this
command.
SB-ATCA7300 Installation and Use Guide
C-13
Supported IPMI Commands
Table C-18 Supported PICMG 3.0 Commands (Continued)
Command
NetFn
CMD
(Request/Response)
Comments
Set Port State
0x2C/0x2D
0x0E
-
Get Port State
0x2C/0x2D
0x0F
-
Compute Power Properties
0x2C/0x2D
0x10
-
Set Power Level
0x2C/0x2D
0x11
-
Get Power Level
0x2C/0x2D
0x12
-
Get IPMB Link Info
0x2C/0x2D
0x18
-
Set AMC Port State
0x2C/0x2D
0x19
-
Get AMC Port State
0x2C/0x2D
0x1A
-
Get FRU Control Capabilities
0x2C/0x2D
0x1E
-
Get target upgrade capabilities
0x2C/0x2D
0x2E
-
Get component properties
0x2C/0x2D
0x2F
-
Abort firmware upgrade
0x2C/0x2D
0x30
-
Initiate upgrade action
0x2C/0x2D
0x31
-
Upload firmware block
0x2C/0x2D
0x32
-
Finish firmware upload
0x2C/0x2D
0x33
-
Get upgrade status
0x2C/0x2D
0x34
-
Activate firmware
0x2C/0x2D
0x35
-
Query self-test results
0x2C/0x2D
0x36
-
Query rollback status
0x2C/0x2D
0x37
-
Initiate manual rollback
0x2C/0x2D
0x38
-
The firmware update commands supported by the blade are implemented
according to the PICMG HPM.1 Revision 1.0 specification.
The boot block can be updated with PICMG HPM.1 specific commands.
C.2.1 Set/Get Power Level
The blade supports two power levels. In case of a shelf which only allows 200 W
per slot the P-States of the blade will be restricted to match this requirement. The
second power level has no such restrictions.
For more information, refer to section 2.2.1 “Processor Speeds” on page 2-2 and
section 3.2.2 “Power Requirements” on page 3-3..
SB-ATCA7300 Installation and Use Guide
C-14
Supported IPMI Commands
C.3 SANBlaze Specific Commands
The SANBlaze IPMC supports several commands which are not defined in the
IPMI or PICMG 3.0 specification but are introduced by SANBlaze: serial output
commands.
 Before sending any of these commands, the shelf management software
must check whether the receiving IPMI controller supports SANBlaze
specific IPMI commands by using the IPMI command 'Get Device ID'.
Sending SANBlaze specific commands to IPMI controllers which do not
support these IPMI commands will lead to no or undefined results.

Proper use of these commands is required to write a portable application.
C.3.1 Serial Output Commands
Table C-19 Serial Output Commands
Command Name
NetFn
CMD
(Request/Response)
Description
Set Serial Output
0x2E/0x2F
0x15
See section C.3.1.1 “Set Serial
Output Command” on page C-15
Get Serial Output
0x2E/0x2F
0x16
See section C.3.1.2 “Get Serial
Output Command” on page C-16
C.3.1.1 Set Serial Output Command
The Set Serial Output command selects the serial port output source for a serial
port connector.
C.3.1.1.1 Request Data
The following table lists the request data applicable to the Set Serial Output
command.
Table C-20 Request Data of Set Serial Output Command
Byte
Data Field
1
LSB of SANBlaze IANA Enterprise number. A value of 0xCD must be used.
2
Second byte of SANBlaze IANA Enterprise number. A value of 0x65 must be
used.
3
MSB of SANBlaze IANA Enterprise number. A value of 0x00 must be used.
SB-ATCA7300 Installation and Use Guide
C-15
Supported IPMI Commands
Table C-20 Request Data of Set Serial Output Command (Continued)
Byte
Data Field
4
Serial connector type
0: Face plate connector
1: Backplane connector
All other values are reserved.
Note: Only the faceplate connector is supported. No connector on the RTM
available.
5
Serial connector instance number. A sequential number that starts from "0".
6
Serial output selector
0: BIOS
2: IPMC debug console
All other values are reserved.
C.3.1.1.2 Response Data
The following table lists the response data applicable to the Set Serial Output
command.
Table C-21 Response Data of Set Serial Output Command
Byte
Data Field
1
Completion code
2
LSB of SANBlaze IANA Enterprise number.
3
Second byte of SANBlaze IANA Enterprise number.
4
MSB of SANBlaze IANA Enterprise number.
C.3.1.2 Get Serial Output Command
The Get Serial Output Command provides a way to determine which serial output
source goes to a particular serial port connector.
Currently, only BIOS output is supported.
SB-ATCA7300 Installation and Use Guide
C-16
Supported IPMI Commands
C.3.1.2.1 Request Data
The following table lists the request data applicable to the Get Serial Output
command.
Table C-22 Request Data of Get Serial Output Command
Byte
Data Field
1
LSB of SANBlaze IANA Enterprise number. A value of 0xCD must be used.
2
Second byte of SANBlaze IANA Enterprise number. A value of 0x65 must be
used.
3
MSB of SANBlaze IANA Enterprise number. A value of 0x00 must be used.
4
Serial connector type
0: Face plate connector
1: Backplane connector
All other values are reserved.
Note: Only the faceplate connector is supported. No connector on the RTM
available.
5
Serial connector instance number. A sequential number that starts from 0.
C.3.1.2.2 Response Data
The following table lists the response data applicable to the Get Serial Output
command.
Table C-23 Response Data of Get Serial Output Command
Byte
Data Field
1
Completion code
2
LSB of SANBlaze IANA Enterprise number.
3
Second byte of SANBlaze IANA Enterprise number.
4
MSB of SANBlaze IANA Enterprise number.
5
Serial output selector
SB-ATCA7300 Installation and Use Guide
C-17
Supported IPMI Commands
C.4 Pigeon Point Specific Commands
The IPMC supports additional IPMI commands that are specific to Pigeon Point.
This section provides detailed descriptions of those extensions:
Table C-24 Pigeon Point Extension Commands
Command
NetFn
CMD
(Request/Response)
Get Status (Table C-26 on page C-19)
0x2E/0x2F
0x00
Get Serial Interface Properties (Table C-27 on page C-21)
0x2E/0x2F
0x01
Set Serial Interface Properties (Table C-28 on page C-22)
0x2E/0x2F
0x02
Get Debug Level (Table C-29 on page C-23)
0x2E/0x2F
0x03
Set Debug Level (Table C-30 on page C-24)
0x2E/0x2F
0x04
Get Hardware Address (Table C-31 on page C-25)
0x2E/0x2F
0x05
Set Hardware Address (Table C-32 on page C-25)
0x2E/0x2F
0x06
Get Handle Switch (Table C-33 on page C-26)
0x2E/0x2F
0x07
Set Handle Switch (Table C-34 on page C-26)
0x2E/0x2F
0x08
Get Payload Communication Time-Out (Table C-35 on
page C-27)
0x2E/0x2F
0x09
Set Payload Communication Time-Out (Table C-36 on
page C-27)
0x2E/0x2F
0x0A
Enable Payload Control (Table C-37 on page C-28)
0x2E/0x2F
0x0B
Disable Payload Control (Table C-38 on page C-28)
0x2E/0x2F
0x0C
Reset IPMC (Table C-39 on page C-28)
0x2E/0x2F
0x0D
Hang IPMC (Table C-40 on page C-29)
0x2E/0x2F
0x0E
Graceful Reset (Table C-41 on page C-30)
0x2E/0x2F
0x11
Get Payload Shutdown Time-Out (Table C-42 on page C30)
0x2E/0x2F
0x15
Set Payload Shutdown Time-Out (Table C-43 on page C-31)
0x2E/0x2F
0x16
Get Module State (Table C-44 on page C-31)
0x2E/0x2F
0x27
Enable Module Site (Table C-45 on page C-32)
0x2E/0x2F
0x28
Disable Module Site (Table C-46 on page C-33)
0x2E/0x2F
0x29
Reset Carrier SDR repository (Table C-47 on page C-33)
0x2E/0x2F
0x33
SB-ATCA7300 Installation and Use Guide
C-18
Supported IPMI Commands
Some of the following commands refer to IPMC modes which are defined as
follows:
Table C-25 IPMC Modes
Mode
Description
Standalone
In standalone mode, the carrier IPMC disconnects from IPMB-0
but keeps on listening to the serial debug and payload interfaces
and serving requests coming from them, as well as managing the
modules, AMC point-to-point (P2P) and clock E-keying.
Standalone mode is intended for debugging purposes and/or
operation in a non-ATCA environment. In standalone mode, the
carrier IPMC automatically activates and deactivates the oncarrier payload and modules whenever it does not violate any
carrier limitations.
Manual
standalone
Manual standalone mode is equivalent to standalone mode with
only one exception: carrier IPMC control over the on-carrier
payload is automatically disabled in manual standalone mode.
C.4.1 Get Status Command
The Get Status command can be used by the payload software to retrieve the
status of the IPMC.
Table C-26 Get Status Command Description
Type
Request Data
Byte
1:3
Response Data 1
2:4
Data Field
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
Completion Code
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
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C-19
Supported IPMI Commands
Table C-26 Get Status Command Description (Continued)
Type
Byte
Data Field
5
Bit [7] Graceful Reboot Request
If set to 1, indicates that the payload is requested to initiate the
graceful reboot sequence.
Bit [6] Diagnostic Interrupt Request
If set to 1, indicates that a payload diagnostic interrupt request has
arrived.
Bit [5] Shutdown Alert
If set to 1, indicates that the payload is going to be shutdown.
Bit [4] Reset Alert
If set to 1, indicates that the payload is going to be reset.
Bit [3] Sensor Alert
If set to 1, indicates that at least one of the IPMC sensors detects a
threshold crossing.
Bits [2:1] Mode
The current IPMC modes are defined as:
0: Normal
1: Standalone, for a description refer to Table C-25 on page C-19
2: Manual Standalone, for a description refer to Table C-25 on
page C-19
Bit [0] Control
If set to 0, the IPMC control over the payload is disabled.
6
Bits [4:7] Metallic Bus 2 Events
These bits indicate pending Metallic Bus 2 requests arrived from the
shelf manager:
0: Metallic Bus 2 Query
1: Metallic Bus 2 Release
2: Metallic Bus 2 Force
3: Metallic Bus 2 Free
Bits [0:3] Metallic Bus 1 Events
These bits indicate pending Metallic Bus 1 requests arrived from the
shelf manager:
0: Metallic Bus 1 Query
1: Metallic Bus 1 Release
2: Metallic Bus 1 Force
3: Metallic Bus 1 Free
SB-ATCA7300 Installation and Use Guide
C-20
Supported IPMI Commands
Table C-26 Get Status Command Description (Continued)
Type
Byte
Data Field
7
Bits [4:7] Clock Bus 2 Events
These bits indicate pending Clock Bus 2 requests arrived from the
shelf manager:
0: Clock Bus 2 Query
1: Clock Bus 2 Release
2: Clock Bus 2 Force
3: Clock Bus 2 Free
Bits [0:3] Clock Bus 1 Events
These bits indicate pending Clock Bus 1 requests arrived from the
shelf manager:
0: Clock Bus 1 Query
1: Clock Bus 1 Release
2: Clock Bus 1 Force
3: Clock Bus 1 Free
8
Bits [4:7] Reserved
Bits [0:3] Clock Bus 3 Events
These bits indicate pending Clock Bus 3 requests arrived from the
shelf manager:
0: Clock Bus 3 Query
1: Clock Bus 3 Release
2: Clock Bus 3 Force
3: Clock Bus 3 Free
C.4.2 Get Serial Interface Properties Command
The Get Serial Interface Properties command is used to get the properties of a
particular serial interface.
Table C-27 Get Serial Interface Properties Command Description
Type
Request Data
Byte
Data Field
1:3
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
4
Interface ID
0: Serial Debug Interface
Response Data 1
2:4
Completion Code
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
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C-21
Supported IPMI Commands
Table C-27 Get Serial Interface Properties Command Description (Continued)
Type
Byte
5
Data Field
Bit [7] Echo On
If this bit is set, the IPMC enables echo for the given serial interface.
Bits [6:4] Reserved
Bits [3:0] Baud Rate ID
The baud rate ID defines the interface baud rate as follows:
0: 9600 bps
1: 19200 bps
2: 38400 bps
3: 57600 bps (unsupported)
4: 115200 bps (unsupported)
C.4.3 Set Serial Interface Properties Command
The Set Serial Interface Properties command is used to set the properties of a
particular serial interface.
Table C-28 Set Serial Interface Properties Command Description
Type
Request Data
Byte
Data Field
1:3
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
4
Interface ID
0: Serial Debug Interface
5
Bit [7] Echo On
If this bit is set, the IPMC enables echo for the given serial interface.
Bits [6:4] Reserved
Bits [3:0] Baud Rate ID
The baud rate ID defines the interface baud rate as follows:
0: 9600 bps
1: 19200 bps
2: 38400 bps
3: 57600 bps (unsupported)
4: 115200 bps (unsupported)
Response Data 1
2:4
Completion Code
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
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C-22
Supported IPMI Commands
C.4.4 Get Debug Level Command
The Get Debug Level command gets the current debug level of the IPMC
firmware.
Table C-29 Get Debug Level Command Description
Type
Request Data
Byte
1:3
Response Data 1
Data Field
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
Completion Code
2:4
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
5
Bit [7] IPMB-L Dump Enable
If set to "1", the IPMC provides a trace of IPMB-L messages that are
arriving to/going from the IPMC via IPMB-L.
Bit [6] n/a
Bit [5] KCS Dump Enable
If set to "1", the IPMC provides a trace of KCS messages that are
arriving to/going from the IPMC via KCS.
Bit [4] IPMB Dump Enable
If set to "1", the IPMC provides a trace of IPMB messages that are
arriving to/going from the IPMC via IPMB-O.
Bit [3] n/a
Bit [2] Alert Logging Enable
If set to "1", the IPMC outputs important alert messages onto the
serial debug interface.
Bit [1] Low-level Error Logging Enable
If set to "1", the IPMC outputs low-level error/diagnostic messages
onto the serial debug interface.
Bit [0] Error Logging Enable
If set to "1", the IPMC outputs error/diagnostic messages onto the
serial debug interface.
SB-ATCA7300 Installation and Use Guide
C-23
Supported IPMI Commands
C.4.5 Set Debug Level Command
The Set Debug Level command sets the current debug level of the IPMC
firmware.
Table C-30 Set Debug Level Command Description
Type
Request Data
Byte
Data Field
1:3
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
4
Bit [7] IPMB-L Dump Enable
If set to "1", the IPMC provides a trace of IPMB-L messages that are
arriving to/going from the IPMC via IPMB-L.
Bit [6] n/a
Bit [5] KCS Dump Enable
If set to "1", the IPMC provides a trace of KCS messages that are
arriving to/going from the IPMC via KCS.
Bit [4] IPMB Dump Enable
If set to "1", the IPMC provides a trace of IPMB messages that are
arriving to/going from the IPMC via IPMB-O.
Bit [3] n/a
Bit [2] Alert Logging Enable
If set to "1", the IPMC outputs important alert messages onto the
serial debug interface.
Bit [1] Low-level Error Logging Enable
If set to "1", the IPMC outputs low-level error/diagnostic messages
onto the serial debug interface.
Bit [0] Error Logging Enable
If set to "1", the IPMC outputs error/diagnostic messages onto the
serial debug interface.
Response Data 1
2:4
Completion Code
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
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C-24
Supported IPMI Commands
C.4.6 Get Hardware Address Command
The Get Hardware Address command reads the hardware address of the IPMC.
Table C-31 Get Hardware Address Command Description
Type
Request Data
Byte
1:3
Response Data 1
Data Field
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
Completion Code
2:4
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
5
Hardware Address
C.4.7 Set Hardware Address Command
The Set Hardware Address command allows to override the hardware address
read from hardware when the IPMC operates in (manual) standalone mode (for a
description refer to Table C-25 on page C-19).
Table C-32 Set Hardware Address Command Description
Type
Request Data
Byte
Data Field
1:3
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
4
Hardware Address
If set to 00, the ability to override the hardware
address is disabled.
NOTE: A hardware address change only takes effect
after an IPMC reset.
Response Data 1
2:4
Completion Code
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
C.4.8 Get Handle Switch Command
The Get Handle Switch command reads the state of the hot-swap handle of the
IPMC. Overriding of the handle switch state is allowed only if the IPMC operates
SB-ATCA7300 Installation and Use Guide
C-25
Supported IPMI Commands
in manual standalone mode (for a description refer to Table C-25 on page C-19).
Table C-33 Get Handle Switch Command Description
Type
Byte
Request Data
1:3
Response Data 1
Data Field
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
Completion Code
2:4
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
5
Handle Switch Status
0x00: The handle switch is open.
0x01: The handle switch is closed.
0x02: The handle switch state is read from hardware.
C.4.9 Set Handle Switch Command
The Set Handle Switch command sets the state of the hot-swap handle switch in
manual standalone mode (for a description refer to Table C-25 on page C-19).
Table C-34 Set Handle Switch Command Description
Type
Request Data
Byte
Data Field
1:3
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
4
Handle Switch Status
0x00: The handle switch is open.
0x01: The handle switch is closed.
0x02: The handle switch state is read from hardware.
Response Data 1
2:4
Completion Code
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
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C-26
Supported IPMI Commands
C.4.10 Get Payload Communication Time-Out Command
The Get Payload Communication Time-Out command reads the payload
communication time-out value.
Table C-35 Get Payload Communication Time-Out Command Description
Type
Request Data
Byte
1:3
Response Data 1
Data Field
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
Completion Code
2:4
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
5
Payload Time-out
Payload communication time-out measured in
hundreds of milliseconds. Thus, the payload
communication time-out may vary from 0.1 to 25.5
seconds.
C.4.11 Set Payload Communication Time-Out Command
The Set Payload Communication Time-Out command sets the payload
communication time-out value.
Table C-36 Set Payload Communication Time-Out Command Description
Type
Request Data
Byte
Data Field
1:3
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
4
Payload Time-out
Payload communication time-out measured in
hundreds of milliseconds. Thus, the payload
communication time-out may vary from 0.1 to 25.5
seconds.
Response Data 1
2:4
Completion Code
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
SB-ATCA7300 Installation and Use Guide
C-27
Supported IPMI Commands
C.4.12 Enable Payload Control Command
The Enable Payload Control command enables payload control from the serial
debug interface.
Table C-37 Enable Payload Control Command Description
Type
Byte
Request Data
1:3
Data Field
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
Response Data 1
Completion Code
2:4
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
C.4.13 Disable Payload Control Command
The Disable Payload Control command disables payload control from the serial
debug interface.
Table C-38 Disable Payload Control Command Description
Type
Byte
Request Data
1:3
Response Data 1
2:4
Data Field
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
Completion Code
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
C.4.14 Reset IPMC Command
The Reset IPMC command allows the payload to reset the IPMC over the KCS
host interface.
Table C-39 Reset IPMC Command Description
Type
Request Data
Byte
1:3
Data Field
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
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C-28
Supported IPMI Commands
Table C-39 Reset IPMC Command Description (Continued)
Type
Byte
4
Data Field
Reset Type Code
0x00: Cold IPMC reset to the current mode
0x01: Cold IPMC reset to the Normal mode
0x02: Cold IPMC reset to the Standalone mode, for a
description refer to Table C-25 on page C-19
0x03: Cold IPMC reset to the Manual Standalone mode, for a
description refer to Table C-25 on page C-19
0x04: Reset the IPMC and enter Upgrade mode
Response Data 1
Completion Code
2:4
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
C.4.15 Hang IPMC Command
The IPMC provides a way to test the watchdog timer support by implementing the
Hang IPMC command, which simulates firmware hanging by entering an endless
loop.
Table C-40 Hang IPMC Command Description
Type
Request Data
Byte
1:3
Response Data 1
2:4
Data Field
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
Completion Code
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
C.4.16 Graceful Reset Command
The IPMC supports the Graceful Reboot option of the FRU Control command. On
receiving such a command, the IPMC sets the Graceful Reboot Request bit of the
IPMC status, sends a status update notification to the payload, and waits for the
Graceful Reset command from the payload. If the IPMC receives such a
command before the payload communication time-out time, it sends the 0x00
completion code (Success) to the shelf manager. Otherwise, the 0xCC completion
code is sent.
The IPMC does not reset the payload upon receiving the Graceful Reset command
or time-out. If the IPMC participation is necessary, the payload must request the
SB-ATCA7300 Installation and Use Guide
C-29
Supported IPMI Commands
IPMC to perform a payload reset. The Graceful Reset command is also used to
notify the IPMC about the completion of the payload shutdown sequence.
Table C-41 Graceful Reset Command Description
Type
Byte
Request Data
1:3
Response Data 1
2:4
Data Field
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
Completion Code
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
C.4.17 Get Payload Shutdown Time-Out Command
When the shelf manager commands the IPMC to shut down the payload (i.e. sends
the Activate FRU (Deactivate) command), the IPMC notifies the payload by
forwarding the command Activate FRU (Deactivate) to the KCS interface.
Provided the OpenIPMI driver has registered this command for notification, the
payload gets notified. Upon receiving this notification, the payload software is
expected to initiate the payload shutdown sequence. After performing this
sequence, the payload should send the Graceful Reset command to the IPMC over
the payload Interface to notify the IPMC that the payload shutdown is complete.
To avoid deadlocks that may occur if the payload software does not respond, the
IPMC provides a special time-out for the payload shutdown sequence. If the
payload does not send the Graceful Reset command within a definite period of
time, the IPMC assumes that the payload shutdown sequence is finished, and
resets the payload.
Table C-42 Get Payload Shutdown Time-Out Command Description
Type
Request Data
Byte
1:3
Response Data 1
Data Field
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
Completion Code
2:4
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
5:6
Time-Out measured in hundreds of milliseconds, LSB first
SB-ATCA7300 Installation and Use Guide
C-30
Supported IPMI Commands
C.4.18 Set Payload Shutdown Time-Out Command
The Set Payload Shutdown Time-Out command is defined as follows.
Table C-43 Set Payload Shutdown Time-Out Command Description
Type
Byte
Request Data
Data Field
1:3
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
4:5
Time-Out measured in hundreds of milliseconds, LSB first
Response Data 1
Completion Code
2:4
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
C.4.19 Get Module State Command
The Get Module State command is used to query the state of a module (RTM with
site ID1) using any of the external interfaces.
Table C-44 Get Module State Command Description
Type
Request Data
Byte
Data Field
1:3
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
4
Module Site ID
Response Data 1
2:4
Completion Code
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
SB-ATCA7300 Installation and Use Guide
C-31
Supported IPMI Commands
Table C-44 Get Module State Command Description (Continued)
Type
Byte
5
Data Field
Module Status
Bit [0]
0: Module site is enabled.
1: Module site is disabled.
Bit [1]
0: Module is not present.
1: Module is present.
Bit [2]
0: Management power is disabled.
1: Management power is enabled.
Bit [3]
0: Management power is bad.
1: Management power is good.
Bit [4]
0: Payload power is disabled.
1: Payload power is enabled.
Bit [5]
0: Payload power is bad.
1: Payload power is good.
Bit [6]
0: IPMB-L buffer is not attached.
1: IPMB-L buffer is attached.
Bit [7]
0: IPMB-L buffer is not ready.
1: IPMB-L buffer is ready.
C.4.20 Enable Module Site Command
The Enable Module Site command is used to enable a module site.
Table C-45 Enable Module Site Command Description
Type
Request Data
Byte
Data Field
1:3
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
4
Module Site ID
Response Data 1
2:4
Completion Code
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
SB-ATCA7300 Installation and Use Guide
C-32
Supported IPMI Commands
C.4.21 Disable Module Site Command
The Disable Module Site command is used to disable a module site. If a module
site is disabled, the IPMC firmware ignores the module inserted and acts as if the
module is not present.
Table C-46 Disable Module Site Command Description
Type
Request Data
Byte
Data Field
1:3
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
4
Module Site ID
Response Data 1
2:4
Completion Code
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
C.4.22 Reset Carrier SDR Repository Command
The Reset Carrier SDR Repository command is used to clear and rebuild the
carrier SDR repository.
Table C-47 Reset Carrier SDR Repository Command Description
Type
Request Data
Byte
1:3
Response Data 1
2:4
Data Field
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00
Completion Code
PPS IANA Private Enterprise ID
0x00400A = 16394 (Pigeon Point Systems)
LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00
SB-ATCA7300 Installation and Use Guide
C-33
Supported IPMI Commands
SB-ATCA7300 Installation and Use Guide
C-34
Index
Symbols
/var/nvdata/subsidiary_lan_pa
ram 7-4
Numerics
5520
Intel I/O hub 2-4
PCIe
initialization 5-10
QPI
initialization 5-9
82599 2-5
A
abbreviations About-2
about
manual About-1
accessory
installation 3-11
part numbers 1-5
ACPI
3.0 5-1
P states 5-9
activate
ipmitool 9-6
address
PCIe
network device B-10
AFUDOS.exe 9-2
afudos.exe 9-2
American Megatrends 5-1
SB-ATCA7300 Installation and Use Guide
AMI 5-1
APIC 6-1
Aptio BIOS 5-1
aufdos
syntax 9-2
B
backplane
connector 4-7
BAID
device 5-4
battery
caution A-1
location A-2
Real Time Clock 2-9
replacing A-1
warning Safety-3, A-1
BEV 5-4
device 5-4
BIOS 5-1
5520 5-2
ACPI 3.0 5-1
afudos 9-2
AMI 5-1
ARTM
SAS boot 5-5
ASL
status codes B-9
BDS 5-12
board information 5-8
boot
messages 5-12
Index-1
Index
options 5-4
order 5-4
stages 5-12
support 5-4
Boot Specification 5-4
copies 5-10
CPU
exception status codes B-9
initialization 5-9
defaults 5-8
DRAM
autosizing 5-3
DRAM support 5-2
DXE 5-12
status codes B-5
firmware
package 9-2
flash memory 2-6
Hyper-threading 5-17
ICH10R 5-2
SATA controller 5-4
image switch 5-11
initialization 5-11
Intel VT 5-10
interrupt routing 5-3
IOH36D 5-2
IPMI support 5-6
Legacy Free 5-8
memory 5-2
channels 5-2
ECC 5-3
menu 5-14
advanced 5-16
boot 5-27
IPMI 5-25
main 5-15
option ROM
execution 5-28
save and exit 5-30
security 5-29
navigation 5-14
network
boot 5-5
OEM reserved
status codes B-10
overview 5-1
Index-2
PCI 5-3
PCIe width 5-10
PEI 5-12
status codes B-2
POST 5-11
processor 5-2
PXE PROM 5-5
QPI speed 5-9
recovery 5-2
register
boot mode 6-41
SB-ATCA7300 2-6
SEC 5-12
status codes B-2
serial
redirection 5-5
Serial Over LAN 5-6
serial ports 5-4
setup 5-13
SFMMOD 5-9
SMBIOS
support 5-7
SOL 5-6
SPI flash 5-10
status code
display 5-11
ranges B-1
status codes B-1
switch image 5-11
update 5-2, 9-1
afudos 9-2
example 9-3
failure 9-4
running 9-2
USB ports 5-8
version 5-12, 5-15, 9-2
watchdog timer 5-6
blade
BIOS information 5-8
connectors 4-3
insertion 3-8
switches 3-5
block diageram
SB-ATCA7300 2-1
BOARD_LAN_PARAMETERS_
CHANNEL_LIST 7-4
SB-ATCA7300 Installation and Use Guide
Index
boot 5-10
BIOS
messages 5-12
stages 5-12
IPMC options
boot devices C-11
commands C-4
parameter 100 C-7
parameter 100 format C-8
parameter 100 get C-9
parameter 100 set C-8
parameter 100 values C-10
parameter 96 C-5
parameter 97 C-6
parameter 98 C-6
parameter storage C-7
IPMC properties C-5
watchdog timer 5-6
watchdog timers 2-7
button
reset 4-3
C
caution
battery A-1
installation Safety-3
operation Safety-3
power 3-4
xontrol switches 3-6
CE notice Safety-2
channel
IPMC 7-3
characteristics
Intel L5638 2-2
clock 6-45
RTC
battery 2-9
codes
BIOS
ASL B-9
CPU exception B-9
display 5-11
DXE B-5
OEM reserved B-10
PEI B-2
SB-ATCA7300 Installation and Use Guide
ranges B-1
SEC B-2
BIOS status B-1
commands
IPMC
ATCA C-13
boot options C-4
chassis device C-4
FRU data C-3
global C-1
IPMI C-1
LAN device C-13
PICMG 3.0 C-13
Pigeon Point C-18
power level C-14
SANBlaze C-15
SEL device C-2
sensor device C-3
serial output C-15
system interface C-1
watchdog C-2
compliance 1-2
notes 1-3
component
locations 3-5
conditions
environmental 3-2
configuration 6-4
IPMC
network 7-4
SOL 7-1
switches 3-5
watchdog timers 5-26
connector
backplane 4-7
blade 4-3
Ethernet 4-3
J30 4-9
J32 4-9
J33 4-9
on-board 4-5
P10 4-8
P20 4-8
P23 4-8
serial port 4-4
SFMMOD 4-5
Index-3
Index
SSD module 4-5
USB 4-4
Flash module 4-7
VGA 4-4
video 4-5
zone 1 4-8
zone 2 4-8
zone 3 4-9
console
IPMC 2-8
redirection 5-5
serial
redirection 2-7
Serial Over LAN 2-8
content
BIOS
update 9-2
firmware
update 9-6
control
front panel 2-8
switches 3-5
controller
Ethernet
types 2-5
memory
L5638 2-4
conventions About-5
copy
BIOS 5-10
CPLD
version
register 6-47
CPU
BIOS
initialization 5-9
microcode 5-8
D
data record
sensor
detail 8-8
types 8-5
DB15
pinout 4-5
Index-4
DDR3
Intel
L5638 2-4
memory 2-4
device 5-4
BAID 5-4
boot
order 5-4
supported 5-4
IPL 5-4
network
boot 5-5
DHCP
IPMC configuration 7-5
dimensions 1-4
DIMM 3-11
insertion 3-13
installation 3-11
order 3-12
location 3-12
removal 3-11, 3-13
sizes 3-11
speeds 3-11
disk
eUSB 2-6
eUSB flash 2-6
SATA-Cube 2-4
display
POST code 6-6
document Safety-4
DOS
update utility 9-1
DRAM
BIOS
autosizing 5-3
E
ECC
BIOS 5-3
ejector
handle 3-9
E-Keying
data 8-4
EMC Safety-2
enable
SB-ATCA7300 Installation and Use Guide
Index
Hyper-threading 5-17
VT-d 5-20
Enterprise Southbridge
Interface 2-4, 5-2
environment
conditions 3-2
requirements 3-1
temperatures 3-2
ESI 2-4, 5-2
Ethernet
connector 4-3
controller
types 2-5
PCIe
device addresses B-10
SB-ATCA7300 2-5
eUSB
disk module 2-6
Flash module 3-15
eUSB Flash module
location 3-15
Exit 5-30
F
F2
BIOS setup 5-13
features
Intel
ICH10R 2-4
L5638 2-3
IPMC 2-6
SB-ATCA7300 1-1
file
IPMC
network configuration 7-4
fimrware
update 9-1
firmware
BIOS
update 9-1
FPGA
update 9-1
IPMC 2-7
backup 9-4
layout 9-4
SB-ATCA7300 Installation and Use Guide
update 9-4
version 9-5
update
ipmitool 9-6
obtaining 9-1
package 9-6
flammability Safety-2
flash
eUSB 2-6
memory
BIOS 2-6
register
status 6-40
write protection 6-40
FPGA
register 6-25
LPC access 6-25
SPI access 6-25
register access 6-5
update 9-1
version 9-2
front panel 2-8, 4-1
componenets 4-1
LEDs 4-2
FRU
power data 8-5
FRU ID
data 8-1
H
handle
blade 3-9
ejector 3-9
hot swap 4-2
HPM.1 9-6
Hyper-threading 2-3
BIOS 5-17
I
I/O hub
Intel
Xeon 5520 2-4
I350 2-5
ICH10R 2-4
interrupts 6-1
Index-5
Index
USB ports 2-8
icons
manual About-5
initialization
BIOS 5-11
insertion
SB-ATCA7300 3-8
installation
accessory 3-11
cautions Safety-3
DIMM 3-11, 3-13
order 3-12
ipmitool 7-2
SFMMOD 3-14
SSD module 3-13, 3-14
USB
Flash module 3-16
VGA
module 3-17
VGA module 3-17
Intel 2-4
83599 2-5
I350 2-5
sideband port 7-1
L5638
features 2-3
QPI 2-3
speeds 2-2
L5638 processor 2-2
QPI 2-3
Quick Path Interconnect 2-3
UCH10R 2-4
VT
BIOS 5-10
Xeon 5520
I/O Hub 2-4
interface
front panel 2-8
ipmitool 9-7
interrupt 6-1
APIC 6-2
BIOS routing 5-3
control register 6-36
non-APIC 6-3
register
external status 6-36
Index-6
mask and map 6-38
RTM status 6-36
IO-APIC 6-1
IPL device 5-4
IPMC
boot options
boot devices C-11
parameter 100 C-7
parameter 100 format C-8
parameter 100 get C-9
parameter 100 set C-8
parameter 100 values C-10
parameter 96 C-5
parameter 97 C-6
parameter 98 C-6
parameter storage C-7
boot properties C-5
channel 7-3
commands C-1
ATCA C-13
boot options C-4
chassis device C-4
FRU data C-3
global C-1
LAN device C-13
PICMG C-13
Pigeon Point C-18
power level C-14
SANBlaze C-15
SEL device C-2
sensor device C-3
serial output C-15
system iinterface C-1
watchdog C-2
console 2-8
firmware 2-7
backup 9-4
layout 9-4
package 9-6
graceful shutdown 2-7
image
switching 9-4
ipmitool 9-8
MAC address 7-7
network
configuration 7-4
SB-ATCA7300 Installation and Use Guide
Index
configuration file 7-4
DHCP configuration 7-5
ipmitool configuration 7-6
OS boot
control 5-7
power level
register 6-29
register
E-Keying control 6-42
E-Keying status 6-42
GPIO 6-43
scratch 6-47
SB-ATCA7300 2-6
sensors 2-7
Serial Over LAN 7-1
status 2-7
update 9-4
example 9-7
version 9-5
watchdog timer 2-7, 5-6
IPMI
BIOS support 5-6
debug output 5-4
IPMC
commands C-1
Serial Over LAN 2-8, 7-1
ipmibpar 5-10
ipmitool
activate 9-6
firmware
upgrade 9-6
hpm check 9-5
-I lan 7-7
installiation 7-2
interface 9-7
IPMC 9-8
network configuration 7-6
KCS interface 9-7
remote interface 9-8
RMCP 9-8
IRQ 6-3
J
J30
connector 4-9
SB-ATCA7300 Installation and Use Guide
J32
connector 4-9
J33
connector 4-9
L
L5638
memory controller 2-4
labels
SB-ATCA7300 1-4
LAN
channel 7-3
lane
PCIe 6-4
LED 4-2
during POST 5-7
register
status and control 6-43
SB-ATCA7300 4-2
Legacy Free BIOS 5-8
location
battery A-2
DIMM 3-12
eUSB
flash module 3-15
updates 9-1
VGA module 3-17
xomponent 3-5
LPC
register
addresses 6-5
scratch 6-47
M
MAC address
IPMC 7-7
manual
about About-1
mapping
interrupts 6-2
memory
BIOS
ECC 5-3
controller
L5638 2-4
Index-7
Index
DDR3 2-4
flash
BIOS 2-6
POST
tests 5-3
menus
BIOS 5-14
microcode
CPU 5-8
model
DIMM 3-11
module
disk
eUSB 2-6
eUSB Flash 3-15
USB Flash 3-15
VGA 3-16
module indentification
register 6-26
N
navigation
BIOS 5-14
network
IPMC
configuration 7-4
NMI
register
status and control 6-44
notice
CE Safety-2
safety Safety-1
number
part 1-5
number format 1-5
O
operation
warning Safety-3
organization
manual About-1
OS
graceful shutdown 2-7
watchdog timer 2-7, 5-6
overview
Index-8
SB-ATCA7300 1-1
P
P states
ACPI 5-9
P10
connector 4-8
P20
connector 4-8
P23
connector 4-8
parameter
Serial Over LAN 7-2
parameters
ipimibpar 5-10
part numbers 1-5
password
Serial Over LAN 7-4
PCI
BIOS 5-3
PCIe
BIOS initialization 5-10
lane mapping 6-4
network device
addresses B-10
PCIe ports 6-4
PIC mode 6-1
pinout
backplane connectors 4-7
DB15 4-5
Ethernet 4-3
serial port 4-4
SFMMOD 4-5
SSD module 4-5
USB 4-4
Flash module 4-7
VGA 4-4
video 4-5
point-to-point connectivity
data 8-4
port
Ethernet 2-5
PCIe 6-4
serial
redirection 2-7
SB-ATCA7300 Installation and Use Guide
Index
USB 2-8
POST
BIOS 5-11
code register 6-6
LED usage 5-7
memory tests 5-3
power
caution 3-4
FRU data 8-5
level 2-2, 3-3
requirements 3-3
Power On Self-Test 5-11
processor
Intel L5638 2-2
L5628
speeds 2-2
L5638
features 2-3
microcode 5-8
register
thermal 6-37
Q
QPI 2-3
BIOS initialization 5-9
Quick Path Interconnect 2-3
R
Real Time Clock
battery 2-9
record
sensor data
detail 8-8
types 8-5
recovery
BIOS 5-2
redirection 5-5
serial I/O 5-5
serial port 2-7
register 6-27
BIOS
boot mode 6-41
conventions 6-4
CPLD version 6-47
flash
SB-ATCA7300 Installation and Use Guide
write protection 6-40
flash status 6-40
FPGA 6-25
access 6-5
LPC access 6-25
SPI access 6-25
interrupt
external status 6-36
mask and map 6-38
RTM status 6-36
interrupt control 6-36
IPMC
E-Keying control 6-42
E-Keying status 6-42
GPIO 6-43
scratch 6-47
IPMC power level 6-29
LED status and control 6-43
LPC
addresses 6-5
scratch 6-47
module identification 6-26
NMI status and control 6-44
POST code 6-6
processor
thermal 6-37
reset 6-30
BIOS pushbutton 6-32
BIOS source 6-30
IPMC source 6-34
IPMC watchdog 6-31, 6-33
mask 6-31
OS IPMC watchdog 6-33
OS source 6-32
RTM SPI interface 6-35
serial line routing 6-28
Serial Over LAN control 6-27
serial redirection control 6-27
SFMMOD configuration 6-42
SPD PROM MUX control 6-29
SPI
addresses 6-6
Super IO 6-7, 6-8
device interrupt 6-12
global 6-8
logical device 6-10
Index-9
Index
telecom 6-45
clock status 6-45
status 6-37
timer 6-46
UART 6-13
baud rate generator 6-24
FIFO control 6-16
interrupt enable 6-14
interrupt
identification 6-15
line control 6-17
line status 6-19
modem control 6-18
modem status 6-22
overview 6-13
receiver buffer 6-14
scratch 6-24
transmitter holding 6-14
version 6-27
removal
blade 3-10
DIMM 3-13
SB-ATCA7300 3-10
SFMMOD 3-13, 3-15
SSD module 3-15
USB
Flash module 3-16
replace
battery A-1
requirements
environmental 3-1
power 3-3
reset
button 4-3
register 6-30
BIOS pushbutton 6-32
BIOS source 6-30
IPMC source 6-34
IPMC watchdog 6-31, 6-33
mask 6-31
OS IPMC watchdog 6-33
OS source 6-32
RTM
register
interrupt status 6-36
SPI interface 6-35
Index-10
S
safety Safety-1
safety-extra-low-voltage 3-4
SAS
BIOS
boot 5-5
SATA-Cube SSD 2-4
SB-ATCA7300 1-2
BIOS 2-6
defaults 5-8
block diagram 2-1
compliance 1-2
component
locations 3-5
connectors 4-3
dimensions 1-4
Ethernet 2-5
features 1-1
front panel 2-8, 4-1
components 4-1
insertion 3-8
IPMC 2-6
labels 1-4
LEDs 4-2
overview 1-1
part numbers 1-5
removal 3-10
serial number 1-5
unpacking 3-1
weight 1-4
SDR
detail 8-8
types 8-5
SELV 3-4
sensor
data record
detail 8-8
types 8-5
IPMC 2-7
serial 1-5
line routing
register 6-28
Serial Over LAN 2-8, 7-1
control register 6-27
serial port
BIOS 5-4
SB-ATCA7300 Installation and Use Guide
Index
connector 4-4
redirection 2-7
serial redirection
control 6-27
session
SOL
create 7-8
quit 7-9
settings
switches 3-7
setup
BIOS 5-13
SFMMOD 2-4
BIOS 5-9
connector 4-5
descrption 3-14
installation 3-13, 3-14
register
configuration 6-42
removal 3-15
Shelf Manager
ipmitool 9-8
shutdown
IPMC graceful 2-7
size
DIMM 3-11
SMBIOS 5-1
support 5-7
SOL 2-8, 7-1
BIOS 5-6
configuration 7-1
ipmitool 7-2
parameters 7-2
session
create 7-8
quit 7-9
user account 7-4
SPD PROM Mux control
register 6-29
speed
DIMM 3-11
processor
L5638 2-2
SPI
flash
BIOS 5-10
SB-ATCA7300 Installation and Use Guide
register addresses 6-6
SSD module
connector 4-5
installation 3-13, 3-14
removal 3-15
SATA-Cube 2-4
standards
compliance 1-2
status
IPMC 2-7
subsidiary_lan_param 7-4
Super IO
configuration state 6-7
register 6-7, 6-8
device interrupt 6-12
global 6-8
logical device 6-10
Super-IO 2-5
switch
BIOS image 5-11
caution 3-6
configuration 3-5
control 3-5
IPMC image 9-4
T
telecom
register
clock 6-45
clock status 6-45
timer 6-46
status register 6-37
temperature
maximums 3-2
timer
watchdog 5-6
typographical
conventions About-5
U
U LEDs 4-2
POST 5-7
UART
register
baud rate generator 6-24
Index-11
Index
Index-12
FIFO control 6-16
interrupt enable 6-14
interrupt
identification 6-15
line control 6-17
line status 6-19
modem control 6-18
modem status 6-22
overview 6-13
receiver buffer 6-14
scratch 6-24
transmitter holding 6-14
registers 6-13
UEFI
BIOS 5-1
update
BIOS 5-2, 9-1
afudos 9-2
example 9-3
failure 9-4
firmware 9-1
FPGA 9-1
IPMC 9-4
example 9-7
obtaining 9-1
upgrade
firmware 9-1
ipmitool 9-6
USB
connector 4-4
flash disk 2-6
Flash module 3-15
connector 4-7
installation 3-16
removal 3-16
ports 2-8
power limit 5-9
user
Serial Over LAN 7-4
utility
ipmipbar 5-10
version
BIOS 5-12, 5-15
CPLD register 6-47
FPGA 9-2
IPMC 9-5
register 6-27
VGA
connector 4-4
module 3-16
installation 3-17
VGA module
installation 3-17
location 3-17
video
pinout 4-5
virtualization
connectivity 2-5
VT-c 2-5
VT-d 2-3
VT-c 2-5
VT-d 2-3
V
Z
verion
BIOS 9-2
zone 1
connector 4-8
W
warning Safety-1
battery Safety-3, A-1
operation Safety-3
watchdog
timer 5-6
configuration 5-26
IPMC 2-7
OS 2-7
weight 1-4
Westmere-EP
L5638 2-2
X
Xeon
5520 2-4
PCIe ports 6-4
L5638 2-2
SB-ATCA7300 Installation and Use Guide
Index
zone 2
connectors 4-8
zone 3
connectors 4-9
SB-ATCA7300 Installation and Use Guide
Index-13
Index
Index-14
SB-ATCA7300 Installation and Use Guide
SANBlaze Technology, Inc. is a leading provider of storage, networking and
multifunction solutions for embedded systems. SANBlaze embedded
computing products include a complete line of ATCA storage and compute
blades, multifunction RTMs for ATCA blades, and AMC storage and
networking controllers and modules. Additionally, the company provides fully
configured and integrated ATCA systems and services.
SANBlaze Technology Inc.
The Industry's Most Innovative Embedded Products
and Storage Emulation Solutions
© 2011 SANBlaze Technology Inc.
www.SANBlaze.com
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