Department of Electrical and Computer Engineering University of

Department of Electrical and Computer Engineering University of
Department of Electrical and Computer Engineering
University of Minnesota
EE2301
Introduction to Digital System Design
Fall 2008
L. L. Kinney
Problem Set V Solutions
1.
(a) Using two 74LS157 multiplexers and no additional logic, design a circuit that selects
one of three 4-bit numbers a3a2a1a0, b3b2b1b0 and c3c2c1c0 and routes that number to
the outputs y3y2y1y0. The select lines are labeled s1s0 and the table below shows how
they select the inputs.
(b) Can this function be realized using two 74LS158 multiplexers and no additional
logic? Explain your answer.
s1 s0
00
01
10
y3y2y1y0
a3 a2 a1 a0
b3b2b1b0
c3 c2 c1 c0
(a) With s1as a select use one 74LS157 to select between c3c2c1c0 and the output of a
second 74LS157. The second 74LS157 selects between a3a2a1a0 and b3b2b1b0 using
s0 as the select.
(b) The 74LS158 does not work because it has active low outputs so the c3c2c1c0 inputs
would be inverted.
1
2.
Realize the function f(A, B, C, D) = ∑ m(2, 5, 6, 7, 10, 12, 13, 14) in the following two
ways where f is the output of the multiplexer.
(a) Use a 8-to-1 multiplexer where the select inputs S2, S1 and S0 are connected to inputs
A, B, and D, respectively. No additional gates are required. Assume the inputs are
available complemented and uncomplemented.
(b) Use a 4-to-1 multiplexer where the select inputs S1 and S0 are connected to inputs B
and D, respectively.
(a) For S2 = A, S1 = B and S0 = D, the regions corresponding to the multiplexer inputs
are marked on the Karnaugh map below. From the regions, I0 = C, I1 = 0, I2 = C, I3 =
1, I4 = C, I5 = 0, I6 = 1 and I7 = C′.
Alternatively, express f algebraically and evaluate for the different values of A, B and
D. For example,
f(A, B, C, D) = A′BD + ABC′ + CD′
I0 = f(0, 0, C, 0) = C
I1 = f(0, 0, C, 1) = 0
I2 = f(0, 1, C, 0) = C
I3 = f(0, 1, C, 1) = 1
I4 = f(1, 0, C, 0) = C
I5 = f(1, 0, C, 1) = 0
I6 = f(1, 1, C, 0) = C′ + C = 1
I7 = f(1, 1, C, 1) = C′
(b) For S1 = B and S0 = D, the regions corresponding to the multiplexer inputs are
marked on the Karnaugh map below. From the regions, I0 = C, I1 = 0, I2 = A + C and
I3 = A′ + C′.
2
Alternatively, express f algebraically and evaluate for the different values of B and D.
For example,
f(A, B, C, D) = A′BD + ABC′ + CD′
I0 = f(A, 0, C, 0) = C
I1 = f(A, 0, C, 1) = 0
I2 = f(A, 1, C, 0) = AC′ + C = A + C
I3 = f(A, 1, C, 1) = A′ + AC′ = A′ + C′
3.
Design a 5-to-32 decoder with enable using only 2-to-4 decoders with an enable. All
outputs and enables are active high. Label the inputs s4, s3, s2, s1, s0 and the outputs
y31, y30, …, y0.
3
4
4.
Design a circuit to implement the function f = ∑ m(1, 3, 7, 9, 15) using a 3-to-8 decoder
with active low outputs and an active low enable and
(a) one NAND gate
(b) one AND gate.
(a) f (A, B, C, D) = ∑ m(1, 3, 7, 9, 15) = A'B'C'D + A'B'CD + A'BCD + AB'C'D + ABCD
= (A'B'C' + A'B'C + A'BC + AB'C' + ABC)D
Use D' as the enable and A, B and C as the selects. Then OR (using a NAND for the
active low outputs) minterms 0, 1, 3, 4, and 7 of A, B and C.
(b) Use the decoder of Part (a) and obtain f by ANDing (with an AND gate) the
maxterms 2, 5 and 6 of A, B and C.
5.
Design a circuit that will supply the signals to a seven segment LED display for
displaying decimal digits when the input digits are encoded using an excess-3 code.
Label the excess-3 inputs M, N, O, and P. Assume that a logic 1 turns on a display
segment and logic 0 turns it off and assume the display is a don′t care for illegal excess-3
combinations. The inputs are available complemented and uncomplemented. (A 1 is
displayed with segments b and c on, a 6 is displayed with all segments but b on, and a 9
is displayed with all segments but c on.)
(a) Design the circuit as a two-level, NAND gate circuit. Use a minimum number of
gates and identify those gates that can be shared between two or more outputs.
(b) Design the circuit using two 74LS153 and three 74LS151 multiplexers. No other
logic is required.
5
(c) Design the circuit using two 74LS138 decoders followed by a minimal number of
gates. All inputs to the decoders are to be connected to M, N, O, P, logic 0, or logic
1. Use one of the 74LS138 decoders to generate all minterms containing the
variables M, O, and P, and use the other decoder to generate all minterms containing
the variables N, O, and P.
(a)
M
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
N
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
O
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
P
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
a
x
x
x
1
0
1
1
0
1
1
1
1
1
x
x
x
b
x
x
x
1
1
1
1
1
0
0
1
1
1
x
x
x
c
x
x
x
1
1
0
1
1
1
1
1
1
1
x
x
x
d
x
x
x
1
0
1
1
0
1
1
0
1
1
x
x
x
e
x
x
x
1
0
1
0
0
0
1
0
1
0
x
x
x
f
x
x
x
1
0
0
0
1
1
1
0
1
1
x
x
x
g
x
x
x
0
0
1
1
1
1
1
0
1
1
x
x
x
Those terms that are shared with other outputs are underlined.)
a = N' + O'P + O P' + M
(two 2-input NANDs, one 4-input NAND)
b = O+N
(one 2-input NAND)
c = P' + O + M or P' + O + N'
(one 3-input NAND)
d = O'P + N'P + M O' + N O P' or O'P + N'P + M O' + M'O P'
(two 2-input NANDs, one 3-input NAND, one 5-input NAND)
e = O'P + N'P
(one 2-input NAND)
f = O P + M O'
(two 2-input NANDs)
g = M P + M O' + N O + O'P or M P + M O' + N O + N P
(two 2-input NANDs, one 4-input NAND)
6
(b)
a =
b =
c =
d =
e =
f =
g =
N' + O'P + O P' + M
O+N
P' + O + M or P' + O + N'
O'P + N'P + M O' + N O P' or O'P + N'P + M O' + M'O P'
O'P + N'P
O P + M O'
M P + M O' + N O + N P or M P + M O' + N O + O'P
b, c, e and f can be realized using the two 74LS153 multiplexers, e.g., O and P can be the select
lines, and then each of b, c, e and f only depend on one additional input.
a, d and g depend on all four inputs so an 8-input multiplexer (74LS151) is needed for each to
realize them without additional logic.
(c) Note that each product in the sums for the outputs depend upon M, O and P or N, O and P or
a subset of those three variables. Hence, all products can be expressed as minterms of M, O and
P or of N, O and P. The choices are not unique.
As an example, consider
d = O'P + N'P + M O' + N O P'
O'P can be obtained as minterms 1 and 5 of either M, O and P or of N, O and P.
N'P can be obtained as minterms 1 and 3 of N, O and P
M O' can be obtained as minterms 4 and 5 of M, O and P
N O P' can be obtained as minterm 6 of N, O and P
Combining these, an optimum choice is realize d as the sum of minterms 1, 4 and 5 of M, O and
P plus minterms 1, 3 and 6 of N, O and P. Since the 74LS138s have active low outputs, the
ORing of minterms requires a NAND gate and d would require a 6-input NAND.
7
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