USB 3.0 SuperSpeed PHY IP for TSMC 40LP

USB 3.0 SuperSpeed PHY IP for TSMC 40LP
USB Datasheet
USB 3.0, DisplayPort Type-C PHY IP
Overview
Cadence® IP Factory delivers custom, synthesizable IP
to support specific design requirements.
The Cadence USB 3.0, DisplayPort Type-C PHY IP is
designed to the USB 3.0 Specification, the USB Type-C ™
Cable and Connector Specification Revision 1.1, and the
VESA® DisplayPort 1.2a Specification. The interface to
the USB 3.0 controller complies with the PHY Interface
for PCI Express® and USB 3.0 Architectures (v3.0)
Specification.
USB 3.0
Dual Role Device
USB 2.0
PHY
DP 1.2
Transmitter
Multi-Protocol PHY
SBU
Switch
USB PD
Software Stack
MCU
Type-C Port
Controller
USB 3.0, DP Type-C PHY IP
Type-C Connector
Combined with the Cadence USB Type-C Port
Figure 1:  Example System-Level Block Diagram
Controller IP, the Cadence USB 3.0, DisplayPort
Type-C PHY IP offers a complete USB 3.0 Type-C PHY subsystem with DisplayPort Alt-Mode and Power Delivery feature.
With its robust architecture and integrated Type-C Alt-Mode and Power Delivery support, the Cadence USB 3.0, DisplayPort
Type-C PHY IP is a perfect solution for high-speed data transmission and video combo applications. The Cadence USB 3.0,
DisplayPort Type-C PHY IP also provides a cost-effective, low-power solution for demanding applications.
Implemented on various advanced process nodes, the Cadence USB 3.0, DisplayPort Type-C PHY IP connects seamlessly to
a Cadence, or third party, UTMI+ or PIPE-compliant controller.
Cadence IP Factory offers a comprehensive IP solution that is in volume production, and has been successfully implemented in
more than 400 applications.
Key Features
• Compliant with DisplayPort v1.2a (RBR, HBR, HBR2)
transmitter with two-lane and four-lane options
• PIPE, UTMI+ Level 3 interfaces, JTAG and ARM®
AMBA® support
• Versatile multi-protocol transceiver with internal PLL
supporting multiple reference frequencies
• Spread-spectrum clock/data recovery system along
with data scrambling to minimize EMI
• Integrated DisplayPort AUX channel
• BIST and scan mode feature for production testing
• Automated calibration of analog components with
offset correction
• System debug with on-chip oscilloscope
Product Details
Common,
USB PLL, DP PLL
USB 3.0 PIPE
Interface
Multi-Protocol Transceiver
Leveraging Cadence multi-protocol transceiver core, the Cadence
USB 3.0, DisplayPort Type-C PHY IP is capable of running
not only a 5Gbps full-duplex USB3.0 SuperSpeed but also a
DisplayPort transmitter at Type-C Alt-Mode, supporting two-lane
and four-lane configuration at a maximum data rate of 5.4Gbps
(HBR2) per lane with the most power, performance, and area
(PPA) efficient configuration.
Both transmit and receive paths support low-frequency periodic
signaling (LFPS) for USB 3.0 compliance testing. A low-speed
bi-directional DisplayPort AUX channel PHY is integrated for
complete DisplayPort feature support.
Controller Interfaces and Test Modes
The Cadence USB 3.0, DisplayPort Type-C PHY IP connects
to a USB controller through an 8-, 16-, or 32-bit PIPE for USB
3.0 interface, at speeds of 500, 250, or 125MHz, respectively. A
separate DisplayPort interface is defined to bridge a DisplayPort
controller.
The Cadence USB 3.0, DisplayPort Type-C PHY IP has flexible
built-in self test (BIST) features and datapath loopback modes for
improved production testing.
DP TX
Interface
Arbitration Logic and Switch Matrix
The Cadence USB 3.0, DisplayPort Type-C PHY IP is a hard PHY
macro with integrated I/O pads and ESD structures available.
USB SSRX, Lane 0
SSRX1P
SSRX1N
USB/DP TX, Lane 0
SSTX1P
SSTX1N
USB SSRX, Lane 1
SSRX2P
SSRX2N
USB/DP TX, Lane 1
SSTX2P
SSTX2N
DP TX, Lane 2
DP TX, Lane 3
DP AUX
Interface
DP AUX PHY
SBU1/AUX+
SBU2/AUX-
Figure 2:  IP-Level Block Diagram
Cadence IP Factory
Cadence IP Factory can deliver various configurations of USB
PHYs to meet your design requirements.
With 10+ years of experience and 400+ successful designs in
process nodes ranging from 180nm to 16nm, Cadence IP has been
proven in everything from low-power MP3 players to leading edge
supercomputers.
For more information, visit ip.cadence.com
Benefits
Deliverables
• Optimized area and low power consumption
• Verilog models for PHY modules
• Multi-protocol PHY enables low-risk silicon development
• Verilog testbench with configuration files and sample tests
• Fully-integrated subsystem available
• Clean, readable, synthesizable Verilog RTL with synthesis/STA
scripts
Related Products
• Liberty timing model
• USB 3.0 Controller IP
• SDF back-annotated timing verification
• DisplayPort Controller IP
• Layout abstract in LEF format
• USB Type-C Port Controller IP
• GDSII with flat netlist for LVS
• USB 2.0 PHY IP
• LVS/DRC log files
• Documentation – specification sheet and integration/user guide
Available Products
• USB 3.0, DisplayPort Type-C PHY IP, TSMC 16FF
• USB 3.0, DisplayPort Type-C PHY IP, TSMC 28HPC
Cadence Design Systems enables global electronic design innovation and plays an essential role in the
creation of today’s electronics. Customers use Cadence software, hardware, IP, and expertise to design
and verify today’s mobile, cloud, and connectivity applications. www.cadence.com
The IP described in this document may only be taped out and manufactured at a TSMC approved manufacturing facility. Any IC developed from
this IP Core must include layer 63 and any other tagging layers (including all tracking tags) as required by TSMC.
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design
Systems, Inc. in the United States and other countries. ARM, AMBA, and AXI are registered trademarks of ARM Limited (or its subsidiaries) in the
EU and/or elsewhere. All rights reserved. USB Type-C™ and USB-C™ are trademarks of USB Implementers Forum. All other trademarks are the
property of their respective owners.
V2.2 10/15, IP no. IP4722C, IP4712C, IP4713C
THIS DOCUMENT IS PROVIDED FOR INFORMATIONAL PURPOSES ONLY, MAY BE CHANGED WITHOUT NOTICE, AND DOES NOT REPRESENT A COMMITMENT ON THE PART OF CADENCE.
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