GS2962 - Semtech

GS2962 - Semtech
GS2962
3G/HD/SD-SDI Serializer with Complete SMPTE Video Support
Key Features
•
•
Operation at 2.970Gb/s, 2.970/1.001Gb/s, 1.485Gb/s,
1.485/1.001Gb/s and 270Mb/s
Supports SMPTE ST 425 (Level A and Level B),
SMPTE ST 424, SMPTE ST 292, SMPTE ST 259-C and
DVB-ASI
Integrated Cable Driver
•
Integrated, low noise VCO
•
Integrated Narrow-Bandwidth PLL
•
Ancillary data insertion
•
Optional conversion from SMPTE ST 425 Level A to
Level B for 1080p 50/60 4:2:2 10-bit
•
Parallel data bus selectable as either 20-bit or 10-bit
•
SMPTE video processing including TRS calculation and
insertion, line number calculation and insertion, line
based CRC calculation and insertion, illegal code
re-mapping, SMPTE ST 352 payload identifier
generation and insertion
EQ
GS2974B
HD-SDI
Deserializer
(GS1559 or
GS2970)
10-bit
10-bit
FIFO
HV F/PCLK
W
3G-SDI
R
HV F/PCLK
HD-SDI
Link B
EQ
HD-SDI
Deserializer
(GS1559 or
GS2970)
GS2962
10-bit
10-bit
FIFO
HV F/PCLK
HV F
W
R
GS4910
X TAL
•
GSPI host interface
•
+1.2V digital core power supply, +1.2V and +3.3V
analog power supplies, and selectable +1.8V or +3.3V
I/O power supply
•
-20ºC to +85ºC operating temperature range
•
Low power operation (typically at 400mW, including
Cable Driver)
•
Small 11mm x 11mm 100-ball BGA package
•
Pb-free and RoHS compliant
10-bit
Link A
GS2960
HV F/PCLK
10-bit
GS2962
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
The integrated narrow-BW PLL allows the device to accept
parallel clocks with high input jitter, and still provide a
SMPTE compliant serial digital output.
The device can operate in four basic user selectable modes:
SMPTE mode, DVB-ASI mode, Data-Through mode, or
Standby mode.
In SMPTE mode, the GS2962 performs all SMPTE
processing features. Both SMPTE ST 425 Level A and Level
B formats are supported with optional conversion from
Level A to Level B for 1080p 50/60 4:2:2 10-bit.
The device can also operate in a lower power Standby
mode. In this mode, no signal is generated at the output.
HD-SDI
GS2962
The GS2962 is a complete SDI Transmitter, generating a
SMPTE ST 424, SMPTE ST 292, SMPTE ST 259-C or DVB-ASI
compliant serial digital output signal.
In Data-Through mode, all SMPTE and DVB-ASI processing
is disabled. The device can be used as a simple parallel to
serial converter.
Application: Single Link (3G-SDI)
to Dual Link (HD-SDI) Converter
HV F/PCLK
Description
In DVB-ASI mode, the device will perform 8b/10b encoding
prior to transmission.
Applications
3G-SDI
HD-SDI
Link A
GS2974B
•
EQ
GS2974
Application: Dual Link (HD-SDI)
to Single Link (3G-SDI) Converter
HD-SDI
Link B
The GS2962 integrates a fully SMPTE-compliant Cable
Driver for SMPTE ST 259-C, SMPTE ST 292 and
SMPTE ST 424 interfaces. It features automatic dual
slew-rate selection, depending on 3Gb/s or HD or SD
operational requirements.
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DVB_ASI
SMPTE_BYPASS
IOPROC_EN/DIS
STANDBY
RESET
IO_GND
IO_VDD
CORE_GND
CORE_VDD
SDIN_TDI
SCLK_TCLK
CS_TMS
SDOUT_TDO
JTAG/HOST
TDO
TDI
TMS
TCK
Dedicated JTAG pins
Shared JTAG and GSPI pins
(for Drop-in Compatibility
with GS1572/82)
Functional Block Diagram
AVDD
JTAG
CONTROLLER
GSPI
Host
Interface
AGND
PLL_VDD
PLL_VDD
VCO_GND
VCO_GND
CD_VDD
CD_GND
ANC_BLANK
F/DE
V/VSYNC
H/HSYNC
TIM_861
20BIT/10BIT
DIN[19:0]
PCLK
RSET
SMPTE ST 425
Input
Mux/
Demux
Level A
Level B
1080p 50/60 4:2:2 10-bit
HANC/
VANC
Blanking
SMPTE ST 352
Generation
and Insertion
ANC Data
Insertion
TRS , Line
Number
and CRC
Insertion
EDH
Packet
Insertion
NRZ/NRZI
SMPTE
Scrambler
Mux
Parallel to Serial
Converter
SMPTE
Cable
Driver
SDO
SDO
SDO_EN/DIS
DVB-ASI
8b/10b
Encoder
PLL with Low Noise
VCO
LOCKED
ClockCleaner™
LF
RATE_SEL[1:0]
VBG
Figure A: GS2962 Functional Block Diagram
Revision History
Version
ECO
PCN
Date
8
014806
−
September 2013
7
155080
56059
October 2010
6
153717
−
March 2010
5
152224
−
July 2009
4
151319
−
January 2009
3
150802
−
December 2008
2
150720
−
October 2008
1
148587
−
September 2008
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
Changes and/or Modifications
Updates throughout the document.
Revised power rating in standby mode. Documented
CSUM behaviour in Section 4.7, Section 4.8.4 and
Configuration and Status Registers.
Updates throughout entire document. Added Figure 4-2,
Figure 4-3 and Figure 4-4. Correction to registers 040h to
13Fh in Table 4-17: Configuration and Status Registers.
Updated Device Latency numbers in 2.4 AC Electrical
Characteristics. Updates to 4.7 ANC Data Insertion.
Replaced 7.3 Marking Diagram.
Correction to timing values in Table 4-1: GS2962 Digital
Input AC Electrical Characteristics.
Conversion to Data Sheet.
Conversion to Preliminary Data Sheet.
New Document.
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Contents
Key Features ........................................................................................................................................................1
Applications.........................................................................................................................................................1
Description...........................................................................................................................................................1
Functional Block Diagram ..............................................................................................................................2
Revision History .................................................................................................................................................2
1. Pin Out...............................................................................................................................................................7
1.1 Pin Assignment ..................................................................................................................................7
1.2 Pin Descriptions ................................................................................................................................8
2. Electrical Characteristics ......................................................................................................................... 16
2.1 Absolute Maximum Ratings ....................................................................................................... 16
2.2 Recommended Operating Conditions .................................................................................... 16
2.3 DC Electrical Characteristics ..................................................................................................... 17
2.4 AC Electrical Characteristics ..................................................................................................... 19
3. Input/Output Circuits ............................................................................................................................... 22
4. Detailed Description.................................................................................................................................. 26
4.1 Functional Overview .................................................................................................................... 26
4.2 Parallel Data Inputs ....................................................................................................................... 27
4.2.1 Parallel Input in SMPTE Mode....................................................................................... 29
4.2.2 Parallel Input in DVB-ASI Mode................................................................................... 29
4.2.3 Parallel Input in Data-Through Mode......................................................................... 30
4.2.4 Parallel Input Clock (PCLK) ............................................................................................ 30
4.3 SMPTE Mode ................................................................................................................................... 31
4.3.1 H:V:F Timing ....................................................................................................................... 31
4.3.2 CEA 861 Timing.................................................................................................................. 33
4.4 DVB-ASI Mode ............................................................................................................................... 41
4.5 Data-Through Mode ..................................................................................................................... 41
4.6 Standby Mode ................................................................................................................................. 41
4.7 ANC Data Insertion ....................................................................................................................... 42
4.7.1 ANC Insertion Operating Modes .................................................................................. 42
4.7.2 3G ANC Insertion............................................................................................................... 44
4.7.3 HD ANC Insertion.............................................................................................................. 45
4.7.4 SD ANC Insertion............................................................................................................... 46
4.8 Additional Processing Functions .............................................................................................. 47
4.8.1 Video Format Detection .................................................................................................. 47
4.8.2 3G Format Detection ........................................................................................................ 50
4.8.3 ANC Data Blanking ........................................................................................................... 52
4.8.4 ANC Data Checksum Calculation and Insertion..................................................... 52
4.8.5 TRS Generation and Insertion ....................................................................................... 52
4.8.6 HD and 3G Line Number Calculation and Insertion.............................................. 53
4.8.7 Illegal Code Re-Mapping................................................................................................. 53
4.8.8 SMPTE ST 352 Payload Identifier Packet Insertion ................................................ 54
4.8.9 Line Based CRC Generation and Insertion (HD/3G) .............................................. 55
4.8.10 EDH Generation and Insertion ................................................................................... 55
4.8.11 SMPTE ST 372 Conversion ........................................................................................... 56
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
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4.8.12 Processing Feature Disable.......................................................................................... 56
4.9 Serial Digital Output ..................................................................................................................... 57
4.9.1 Output Signal Interface Levels...................................................................................... 57
4.9.2 Overshoot/Undershoot.................................................................................................... 59
4.9.3 Slew Rate Selection........................................................................................................... 59
4.9.4 Serial Digital Output Mute.............................................................................................. 59
4.10 Serial Clock PLL ........................................................................................................................... 60
4.10.1 PLL Bandwidth................................................................................................................. 60
4.10.2 Lock Detect........................................................................................................................ 61
4.11 GSPI Host Interface ..................................................................................................................... 62
4.11.1 Command Word Description ...................................................................................... 63
4.11.2 Data Read or Write Access........................................................................................... 63
4.11.3 GSPI Timing....................................................................................................................... 64
4.12 Host Interface Register Maps .................................................................................................. 66
4.13 JTAG ID Codeword ..................................................................................................................... 75
4.14 JTAG Test Operation .................................................................................................................. 75
4.15 Device Power-Up ........................................................................................................................ 75
4.16 Device Reset .................................................................................................................................. 75
5. Application Reference Design ............................................................................................................... 76
5.1 Typical Application Circuit ........................................................................................................ 76
6. References & Relevant Standards ......................................................................................................... 77
7. Package & Ordering Information .......................................................................................................... 78
7.1 Package Dimensions ..................................................................................................................... 78
7.2 Packaging Data ............................................................................................................................... 79
7.3 Marking Diagram ........................................................................................................................... 79
7.4 Solder Reflow Profiles .................................................................................................................. 80
7.5 Ordering Information ................................................................................................................... 80
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
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List of Figures
Figure 3-1: Differential Output Stage (SDO/SDO) .............................................................................. 22
Figure 3-2: Digital Input Pin ........................................................................................................................ 22
Figure 3-3: Digital Input Pin with Schmitt Trigger (RESET) .............................................................. 23
Figure 3-4: Digital Input Pin with weak pull-down - maximum pull-down current ............... 23
Figure 3-5: Digital Input Pin with weak pull-up - maximum pull-up current ........................... 23
Figure 3-6: Bidirectional Digital Input/Output Pin with programmable drive strength......... 24
Figure 3-7: Bidirectional Digital Input/Output Pin with programmable drive strength......... 24
Figure 3-8: VBG .............................................................................................................................................. 25
Figure 3-9: Loop Filter .................................................................................................................................. 25
Figure 4-1: GS2962 Video Host Interface Timing Diagrams ............................................................ 27
Figure 4-2: H:V:F Output Timing - 3G Level A and HDTV 20-bit Mode ...................................... 32
Figure 4-3: H:V:F Output Timing - 3G Level A and HDTV 10-bit Mode
3G Level B 20-bit Mode, each 10-bit stream ......................................................................................... 32
Figure 4-4: H:V:F Output Timing - 3G Level B 10-bit Mode ............................................................. 32
Figure 4-5: H:V:F Input Timing - HD 20-bit Input Mode ................................................................... 32
Figure 4-6: H:V:F Input Timing - HD 10-bit Input Mode ................................................................... 33
Figure 4-7: H:V:F Input Timing - SD 20-bit Mode ............................................................................... 33
Figure 4-8: H:V:F Input Timing - SD 10-bit Mode ............................................................................... 33
Figure 4-9: H:V:DE Input Timing 1280 x 720p @ 59.94/60 (Format 4) ........................................ 35
Figure 4-10: H:V:DE Input Timing 1920 x 1080i @ 59.94/60 (Format 5) ..................................... 35
Figure 4-11: H:V:DE Input Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) ....................... 36
Figure 4-12: H:V:DE Input Timing 1280 x 720p @ 50 (Format 19) ................................................ 36
Figure 4-13: H:V:DE Input Timing 1920 x 1080i @ 50 (Format 20) ............................................... 37
Figure 4-14: H:V:DE Input Timing 720 (1440) x 576 @ 50 (Format 21&22) ................................ 38
Figure 4-15: H:V:DE Input Timing 1920 x 1080p @ 59.94/60 (Format 16) ................................. 38
Figure 4-16: H:V:DE Input Timing 1920 x 1080p @ 50 (Format 31) .............................................. 39
Figure 4-17: H:V:DE Input Timing 1920 x 1080p @ 23.94/24 (Format 32) ................................. 39
Figure 4-18: H:V:DE Input Timing 1920 x 1080p @ 25 (Format 33) .............................................. 40
Figure 4-19: H:V:DE Input Timing 1920 x 1080p @ 29.97/30 (Format 34) ................................. 40
Figure 4-20: ORL Matching Network, BNC and Coaxial Cable Connection ............................... 57
Figure 4-21: GSPI Application Interface Connection ........................................................................ 62
Figure 4-22: Command Word Format ..................................................................................................... 63
Figure 4-23: Data Word Format ................................................................................................................ 63
Figure 4-24: Write Mode .............................................................................................................................. 64
Figure 4-25: Read Mode ............................................................................................................................... 64
Figure 4-26: GSPI Time Delay .................................................................................................................... 64
Figure 4-27: Reset Pulse ............................................................................................................................... 75
Figure 5-1: Typical Application Circuit .................................................................................................. 76
Figure 7-1: Package Dimensions ............................................................................................................... 78
Figure 7-2: Marking Diagram ..................................................................................................................... 79
Figure 7-3: Pb-free Solder Reflow Profile .............................................................................................. 80
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
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5 of 81
List of Tables
Table 1-1: Pin Descriptions ............................................................................................................................ 8
Table 2-1: Absolute Maximum Ratings................................................................................................... 16
Table 2-2: Recommended Operating Conditions................................................................................ 16
Table 2-3: DC Electrical Characteristics ................................................................................................. 17
Table 2-4: AC Electrical Characteristics ................................................................................................. 19
Table 4-1: GS2962 Digital Input AC Electrical Characteristics....................................................... 27
Table 4-2: GS2962 Input Video Data Format Selections................................................................... 27
Table 4-3: GS2962 PCLK Input Rates....................................................................................................... 30
Table 4-4: CEA861 Timing Formats ......................................................................................................... 34
Table 4-5: Supported Video Standards................................................................................................... 48
Table 4-6: SMPTE ST 352 Packet Data..................................................................................................... 51
Table 4-7: IOPROC Register Bits................................................................................................................ 56
Table 4-8: Serial Digital Output - Serial Output Data Rate............................................................... 57
Table 4-9: RSET Resistor Value vs. Output Swing................................................................................. 58
Table 4-10: Serial Digital Output - Overshoot/Undershoot ............................................................. 59
Table 4-11: Serial Digital Output - Rise/Fall Time............................................................................... 59
Table 4-12: PCLK and Serial Digital Clock Rates ................................................................................. 60
Table 4-13: GS2962 PLL Bandwidth......................................................................................................... 61
Table 4-14: GS2962 Lock Detect Indication .......................................................................................... 61
Table 4-15: GSPI Time Delay...................................................................................................................... 64
Table 4-16: GSPI AC Characteristics........................................................................................................ 65
Table 4-17: Configuration and Status Registers................................................................................... 66
Table 7-1: Packaging Data........................................................................................................................... 79
Table 7-2: Ordering Information............................................................................................................... 80
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
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1. Pin Out
1.1 Pin Assignment
1
2
A
DIN17
DIN18
B
DIN15
C
3
4
5
6
7
8
9
10
F/DE
H/HSYNC
CORE
_VDD
PLL_
VDD
LF
VBG
RSV
A_VDD
DIN16
DIN19
PCLK
CORE
_GND
PLL_
VDD
VCO_
VDD
VCO_
GND
A_GND A_GND
DIN13
DIN14
DIN12
V/VSYNC
CORE
_GND
PLL_
GND
PLL_
GND
PLL_
GND
CD_GND
SDO
D
DIN11
DIN10
STANDBY
SDO_
EN/DIS
CORE
_GND
RSV
RSV
RSV
CD_GND
SDO
E
CORE
_VDD
CORE
_GND
RATE_
SEL0
RATE_
SEL1
CORE
_GND
CORE
_GND
TDI
TMS
CD_GND CD_VDD
F
DIN9
DIN8
DETECT
_TRS
CORE
_GND
CORE
_GND
CORE
_GND
CORE
_GND
TDO
CD_GND
RSET
CORE
_GND
CORE
_VDD
G
IO_VDD IO_GND TIM_861
SMPTE_ IOPROC
20bit/
DVB_ASI
RESET
BYPASS _EN/DIS
10bit
CORE
_GND
CORE
_GND
RSV
JTAG/
HOST
IO_GND IO_VDD
RSV
RSV
RSV
RSV
TCK
SDOUT_ SCLK_
TDO
TCK
RSV
RSV
RSV
RSV
CORE
_VDD
ANC_
LOCKED
BLANK
H
DIN7
DIN6
J
DIN5
DIN4
DIN1
K
DIN3
DIN2
DIN0
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
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CS_
TMS
SDIN_
TDI
7 of 81
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
Name
Timing
Type
Description
PARALLEL DATA BUS.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
20-bit mode
20BIT/10BIT = HIGH
B3, A2, A1,
B2, B1, C2,
C1, C3, D1,
D2
DIN[19:10]
Input
10-bit mode
20BIT/10BIT = LOW
Data Stream 1/Luma data input in
SMPTE mode (SMPTE_BYPASS = HIGH)
Data input in data through mode
(SMPTE_BYPASS = LOW)
Multiplexed Data Stream 1/Luma and
Data Stream 2/Chroma data input in
SMPTE mode
(SMPTE_BYPASS = HIGH)
Data input in data through mode
(SMPTE_BYPASS = LOW)
DVB-ASI data input in DVB-ASI mode
(SMPTE_BYPASS = LOW)
(DVB_ASI = HIGH)
PARALLEL DATA TIMING.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
A3
F/DE
Synchronous
with
PCLK
Input
TIM_861 = LOW:
Used to indicate the ODD / EVEN field of the video signal when
DETECT_TRS is set LOW. The device will set the F bit in all outgoing
TRS signals for the entire period that the F input signal is HIGH
(IOPROC_EN/DIS must also be HIGH).
The F signal should be set HIGH for the entire period of field 2 and
should be set LOW for all lines in field 1 and for all lines in
progressive scan systems.
The F signal is ignored when DETECT_TRS = HIGH.
TIM_861 = HIGH:
The DE signal is used to indicate the active video period when
DETECT_TRS is set LOW. DE is HIGH for active data and LOW for
blanking. See Section 4.3 and Section 4.3.2 for timing details.
The DE signal is ignored when DETECT_TRS = HIGH.
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
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8 of 81
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
PARALLEL DATA TIMING.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
TIM_861 is LOW:
The H signal is used to indicate the portion of the video line
containing active video data, when DETECT_TRS is set LOW.
A4
H/HSYNC
Synchronous
with
PCLK
Input
Active Line Blanking
The H signal should be LOW for the active portion of the video line.
The signal goes LOW at the first active pixel of the line, and then
goes HIGH after the last active pixel of the line.
The H signal should be set HIGH for the entire horizontal blanking
period, including both EAV and SAV TRS words, and LOW otherwise.
TRS Based Blanking (H_CONFIG = 1h)
The H signal should be set HIGH for the entire horizontal blanking
period as indicated by the H bit in the received TRS ID words, and
LOW otherwise.
TIM_861 = HIGH:
The HSYNC signal indicates horizontal timing. See Section 4.3.
When DETECT_TRS is HIGH, this pin is ignored at all times.
If DETECT_TRS is set HIGH and TIM_861 is set HIGH, the DETECT_TRS
feature will take priority.
A5, E1, G10,
K8
CORE_VDD
Input Power
Power supply connection for digital core logic. Connect to 1.2V DC
digital.
A6, B6
PLL_VDD
Input Power
Power supply pin for PLL. Connect to 1.2V DC analog.
A7
LF
Analog
Output
Loop Filter component connection.
A8
VBG
Output
Bandgap voltage filter connection.
A9, D6, D7,
D8, H7, J4,
J5, J6, J7,
K4, K5, K6,
K7
RSV
−
A10
A_VDD
Input Power
These pins are reserved and should be left unconnected.
VDD for sensitive analog circuitry. Connect to +3.3VDC analog.
PARALLEL DATA BUS CLOCK.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
B4
PCLK
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
Input
3G 20-bit mode
PCLK @ 148.5MHz
3G 10-bit mode DDR
PCLK @ 148.5MHz
HD 20-bit mode
PCLK @ 74.25MHz
HD 10-bit mode
PCLK @ 148.5MHz
SD 20-bit mode
PCLK @ 13.5MHz
SD 10-bit mode
PCLK @ 27MHz
DVB-ASI mode
PCLK @ 27MHz
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
B5, C5, D5,
E2, E5, E6,
F4, F5, F6,
F7, G9, H5,
H6
CORE_GND
Input Power
Reserved. Connect to CORE_GND.
B7
VCO_VDD
Input Power
Power pin for VCO. Connect to 1.2V DC analog followed by an RC
filter (see Typical Application Circuit on page 76). VCO_VDD is
nominally 0.7V.
B8
VCO_GND
Input Power
Ground connection for VCO. Connect to analog GND.
B9, B10
A_GND
Input Power
GND pins for sensitive analog circuitry. Connect to analog GND.
Timing
Type
Description
PARALLEL DATA TIMING.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
TIM_861 = LOW:
C4
V/VSYNC
Synchronous
with
PCLK
The V signal is used to indicate the portion of the video field/frame
that is used for vertical blanking, when DETECT_TRS is set LOW.
Input
The V signal should be set HIGH for the entire vertical blanking
period and should be set LOW for all lines outside of the vertical
blanking interval.
The V signal is ignored when DETECT_TRS = HIGH.
TIM_861 = HIGH:
The VSYNC signal indicates vertical timing. See Section 4.3 for
timing details.
The VSYNC signal is ignored when DETECT_TRS = HIGH.
C6, C7, C8
PLL_GND
Input Power
Ground connection for PLL. Connect to analog GND.
C9, D9, E9,
F9
CD_GND
Input Power
Ground connection for the serial digital cable driver. Connect to
analog GND.
Serial Data Output Signal.
C10, D10
SDO, SDO
Output
D3
STANDBY
Input
Serial digital output signal operating at 2.97Gb/s, 2.97/1.001Gbs,
1.485Gb/s, 1.485 /1.001Gb/s or 270Mb/s.
The slew rate of the output is automatically controlled to meet
SMPTE ST 424, SMPTE ST 292 and SMPTE ST 259 specifications
according to the setting of the RATE_SEL0 and RATE_SEL1 pins.
Standby input.
HIGH to place the device in Standby mode.
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
D4
SDO_EN/DIS
Input
Used to enable or disable the serial digital output stage.
When SDO_EN/DIS is LOW, the serial digital output signals SDO and
SDO are disabled and become high impedance.
When SDO_EN/DIS is HIGH, the serial digital output signals SDO and
SDO are enabled.
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
www.semtech.com
10 of 81
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to configure the operating data rate.
E3, E4
RATE_SEL0,
RATE_SEL1
Input
RATE_SEL0
RATE_SEL1
Data Rate
0
0
1.485 or 1.485/1.001Gb/s
0
1
2.97 or 2.97/1.001Gb/s
1
X
270Mb/s
COMMUNICATION SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
E7
TDI
Input
Dedicated JTAG pin.
Test data in.
This pin is used to shift JTAG test data into the device when the
JTAG/HOST pin is LOW.
COMMUNICATION SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
E8
TMS
Input
Dedicated JTAG pin.
Test mode start.
This pin is JTAG Test Mode Start, used to control the operation of the
JTAG test when the JTAG/HOST pin is LOW.
E10
CD_VDD
Input Power
Power for the serial digital cable driver. Connect to +3.3V DC analog.
PARALLEL DATA BUS.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
In 10-bit mode, these pins are not used.
F1, F2, H1,
H2, J1, J2,
K1, K2, J3,
K3
Data Stream 2/Chroma data input in
SMPTE mode SMPTE_BYPASS = HIGH
DVB_ASI = LOW
DIN[9:0]
Input
20-bit mode
20BIT/10BIT = HIGH
Data input in data through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
Not Used in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
10-bit mode
20BIT/10BIT = LOW
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
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Not used.
11 of 81
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
F3
DETECT_TRS
Input
Used to select external HVF timing mode or TRS extraction timing
mode.
When DETECT_TRS is LOW, the device extracts all internal timing
from the supplied H:V:F or CEA-861 timing signals, dependent on
the status of the TIM861 pin.
When DETECT_TRS is HIGH, the device extracts all internal timing
from TRS signals embedded in the supplied video stream.
COMMUNICATION SIGNAL OUTPUT.
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
F8
TDO
Output
Dedicated JTAG pin.
JTAG Test Data Output.
This pin is used to shift results from the device when the JTAG/HOST
pin is LOW.
An external 1% resistor connected to this input is used to set the
SDO/SDO output signal amplitude.
F10
RSET
Input
G1, H10
IO_VDD
Input Power
Power connection for digital I/O. Connect to +3.3V or +1.8V DC
digital.
G2, H9
IO_GND
Input Power
Ground connection for digital I/O. Connect to digital GND.
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select external CEA-861 timing mode.
G3
TIM_861
Input
When DETECT_TRS is LOW and TIM-861 is LOW, the device extracts
all internal timing from the supplied H:V:F timing signals.
When DETECT_TRS is LOW and TIM-861 is HIGH, the device extracts
all internal timing from the supplied HSYNC, VSYNC, DE timing
signals.
When DETECT_TRS is HIGH, the device extracts all internal timing
from TRS signals embedded in the supplied video stream.
CONTROL SIGNAL INPUT.
G4
20bit/10bit
Input
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select the input bus width.
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to enable/disable the DVB-ASI data transmission.
G5
DVB_ASI
Input
When DVB_ASI is set HIGH and SMPTE_BYPASS is set LOW, then the
device will carry out DVB-ASI word alignment, I/O processing and
transmission.
When SMPTE_BYPASS and DVB_ASI are both set LOW, the device
operates in data-through mode.
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
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12 of 81
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to enable / disable all forms of encoding / decoding, scrambling
and EDH insertion.
G6
SMPTE_BYPASS
Input
When set LOW, the device operates in data through mode
(DVB_ASI= LOW), or in DVB-ASI mode (DVB_ASI = HIGH).
No SMPTE scrambling takes place and none of the I/O processing
features of the device are available when SMPTE_BYPASS is set LOW.
When set HIGH, the device carries out SMPTE scrambling and I/O
processing.
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
G7
IOPROC_EN/DIS
Input
Used to enable or disable the I/O processing features.
When IOPROC_EN/DIS is HIGH, the I/O processing features of the
device are enabled. When IOPROC_EN/DIS is LOW, the I/O processing
features of the device are disabled.
Only applicable in SMPTE mode.
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to reset the internal operating conditions to default settings
and to reset the JTAG sequence.
Normal mode (JTAG/HOST = LOW).
G8
RESET
Input
When LOW, all functional blocks will be set to default conditions
and all input and output signals become high impedance.
When HIGH, normal operation of the device resumes.
JTAG test mode (JTAG/HOST = HIGH).
When LOW, all functional blocks will be set to default and the JTAG
test sequence will be reset.
When HIGH, normal operation of the JTAG test sequence resumes.
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
H3
ANC_BLANK
Input
When ANC_BLANK is LOW, the Luma and Chroma input data is set
to the appropriate blanking levels during the H and V blanking
intervals.
When ANC_BLANK is HIGH, the blanking function is disabled.
Only applicable in SMPTE mode.
STATUS SIGNAL OUTPUT.
H4
LOCKED
Output
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
PLL lock indication.
HIGH indicates PLL is locked.
LOW indicates PLL is not locked.
GS2962 3G/HD/SD-SDI Serializer with Complete
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13 of 81
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
H8
JTAG/HOST
Input
Used to select JTAG test mode or host interface mode.
When JTAG/HOST is HIGH, the host interface port is configured for
JTAG test.
When JTAG/HOST is LOW, normal operation of the host interface
port resumes and the separate JTAG pins become the JTAG port.
COMMUNICATION SIGNAL INPUT.
J8
TCK
Input
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
JTAG Serial Data Clock Signal.
This pin is the JTAG clock when the JTAG/HOST pin is LOW.
COMMUNICATION SIGNAL OUTPUT.
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Shared JTAG/HOST pin. Provided for compatibility with the GS1582.
Serial Data Output/Test Data Output.
J9
SDOUT_TDO
Output
Host Mode (JTAG/HOST = LOW)
This pin operates as the host interface serial output, used to read
status and configuration information from the internal registers of
the device.
JTAG Test Mode (JTAG/HOST = HIGH)
This pin is used to shift test results and operates as the JTAG test
data output, TDO (for new designs, use the dedicated JTAG port).
Note: If the host interface is not being used leave this pin
unconnected.
IO_VDD = +3.3V
Drive Strength = 12mA
IO_VDD = +1.8V
Drive Strength = 4mA
COMMUNICATION SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Shared JTAG/HOST pin. Provided for pin compatibility with GS1582.
Serial data clock signal.
J10
SCLK_TCK
Input
Host Mode (JTAG/HOST = LOW)
SCLK_TCK operates as the host interface burst clock, SCLK.
Command and data read/write words are clocked into the device
synchronously with this clock.
JTAG Test Mode (JTAG/HOST = HIGH)
This pin is the TEST MODE START pin, used to control the operation
of the JTAG test clock, TCK (for new designs, use the dedicated JTAG
port).
Note: If the host interface is not being used, tie this pin HIGH.
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
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14 of 81
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
COMMUNICATION SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Chip select / test mode start.
K9
CS_TMS
Input
JTAG Test mode (JTAG/HOST = HIGH)
CS_TMS operates as the JTAG test mode start, TMS, used to control
the operation of the JTAG test, and is active HIGH (for new designs,
use the dedicated JTAG port).
Host mode (JTAG/HOST = LOW), CS_TMS operates as the host
interface Chip Select, CS, and is active LOW.
COMMUNICATION SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Shared JTAG/HOST pin. Provided for pin compatibility with GS1582.
K10
SDIN_TDI
Input
Serial data in/test data in.
In JTAG mode, this pin is used to shift test data into the device (for
new designs, use the dedicated JTAG port).
In host interface mode, this pin is used to write address and
configuration data words into the device.
GS2962 3G/HD/SD-SDI Serializer with Complete
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Final Data Sheet Rev. 8
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15 of 81
2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Table 2-1: Absolute Maximum Ratings
Parameter
Value/Units
Supply Voltage, Digital Core (CORE_VDD)
-0.3V to +1.5V
Supply Voltage, Digital I/O (IO_VDD)
-0.3V to +3.6V
Supply Voltage, Analog +1.2V (PLL_VDD, VCO_VDD)
-0.3V to +1.5V
Supply Voltage, Analog +3.3V (CD_VDD, A_VDD)
-0.3V to +3.6V
Input Voltage Range (RSET)
-0.3V to (CD_VDD + 0.3)V
Input Voltage Range (VBG)
-0.3V to (A_VDD + 0.3)V
Input Voltage Range (LF)
-0.3V to (PLL_VDD + 0.3)V
Input Voltage Range (digital inputs)
-2.0V to +5.25V
Storage Temperature Range
-40°C to +125°C
Peak Reflow Temperature (JEDEC J-STD-020C)
260°C
ESD Sensitivity, HBM (JESD22-A114)
2kV
Note: Absolute Maximum Ratings are those values beyond which damage may occur. Functional operation
outside of the ranges shown in Table 2-1 is not implied.
2.2 Recommended Operating Conditions
Table 2-2: Recommended Operating Conditions
Parameter
Operating Temperature Range,
Ambient
Supply Voltage, Digital Core
Symbol
Conditions
Min
Typ
Max
Units
Notes
TA
–
-20
−
85
°C
−
CORE_VDD
–
1.14
1.2
1.26
V
−
+1.8V mode
1.71
1.8
1.89
V
−
+3.3V mode
3.13
3.3
3.47
V
−
Supply Voltage, Digital I/O
IO_VDD
Supply Voltage, PLL
PLL_VDD
–
1.14
1.2
1.26
V
–
Supply Voltage, VCO
VCO_VDD
–
−
0.7
−
V
1
A_VDD
–
3.13
3.3
3.47
V
–
CD_VDD
–
3.13
3.3
3.47
V
–
–
–
-20
–
85
°C
2
Supply Voltage, Analog
Supply Voltage, CD
Operating Temperature Range
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Table 2-2: Recommended Operating Conditions (Continued)
Parameter
Functional Temperature Range
Symbol
Conditions
Min
Typ
Max
Units
Notes
–
–
-40
–
85
°C
2
Notes:
1. This is 0.7V rather than 1.2V because there is a voltage drop across an external 105Ω resistor. See Typical Application Circuit on page 76.
2. Operating Temperature Range guarantees the parameters given in the DC Electrical Characteristics and AC Electrical Characteristics.
Functional Temperature Range guarantees a device start-up.
2.3 DC Electrical Characteristics
Table 2-3: DC Electrical Characteristics
VCC = +3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
10bit 3G
−
110
170
mA
−
20bit 3G
−
110
170
mA
−
10/20bit HD
−
90
150
mA
−
10/20bit SD
−
75
120
mA
−
DVB_ASI
−
75
120
mA
−
10bit 3G
−
10
15
mA
−
20bit 3G
−
10
15
mA
−
10/20bit HD
−
10
25
mA
−
10/20bit SD
−
3
10
mA
−
DVB_ASI
−
3
10
mA
−
10bit 3G
−
80
100
mA
−
20bit 3G
−
80
100
mA
−
10/20bit HD
−
80
100
mA
−
10/20bit SD
−
70
90
mA
−
DVB_ASI
−
70
90
mA
−
10bit 3G
−
350
510
mW
−
20bit 3G
−
350
510
mW
−
10/20bit HD
−
330
490
mW
−
10/20bit SD
−
300
450
mW
−
DVB_ASI
−
300
410
mW
−
Reset
−
200
−
mW
−
Standby
−
100
180
mW
1
System
+1.2V Supply Current
+1.8V Supply Current
+3.3V Supply Current
Total Device Power
(IO_VDD = 1.8V)
I1V2
I1V8
I3V3
P1D8
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17 of 81
Table 2-3: DC Electrical Characteristics (Continued)
VCC = +3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown
Parameter
Total Device Power
(IO_VDD = +3.3V)
Symbol
P3D3
Conditions
Min
Typ
Max
Units
Notes
10bit 3G
−
370
510
mW
−
20bit 3G
−
380
520
mW
−
10/20bit HD
−
370
500
mW
−
10/20bit SD
−
320
450
mW
−
DVB_ASI
−
320
450
mW
−
Reset
−
230
−
mW
−
Standby
−
110
180
mW
1
Digital I/O
Input Logic LOW
VIL
+3.3V or +1.8V operation
IO_VSS-0.3
−
0.3 x IO_VDD
V
−
Input Logic HIGH
VIH
+3.3V or +1.8V operation
0.7 x
IO_VDD
−
IO_VDD+0.3
V
−
Output Logic LOW
VOL
IOL=5mA, +1.8V operation
−
−
0.2
V
−
IOL=8mA, +3.3V operation
−
−
0.4
V
−
IOH=-5mA, +1.8V
operation
1.4
−
–
V
−
IOH=-8mA, +3.3V
operation
2.4
−
–
V
−
−
CD_VDD (VSDD/2)
−
V
−
Output Logic HIGH
VOH
Serial Output
Serial Output
Common Mode
Voltage
VCMOUT
75Ω load, RSET = 750Ω
SD and HD mode
Note:
1. Devices manufactured prior to April 1, 2011 consume 150mW of power in Standby mode.
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18 of 81
2.4 AC Electrical Characteristics
Table 2-4: AC Electrical Characteristics
VCC = +3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
–
3G bypass
(PCLK = 148.5MHz)
–
54
–
PCLK
–
–
3G SMPTE
(PCLK = 148.5MHz)
–
95
–
PCLK
–
–
3G IOPROC disabled
20-bit mode
(PCLK = 148.5MHz)
–
94
–
PCLK
–
–
HD bypass
(PCLK = 74.25MHz)
–
54
–
PCLK
–
–
HD SMPTE
(PCLK = 74.25MHz)
–
95
–
PCLK
–
–
HD IOPROC disabled
10-bit mode
(PCLK = 74.25MHz)
–
SD bypass
(PCLK = 27MHz)
–
54
–
PCLK
–
–
SD SMPTE
(PCLK = 27MHz)
–
112
–
PCLK
–
–
SD IOPROC disabled
10-bit mode
(PCLK = 27MHz)
–
94
–
PCLK
–
System
Device Latency
98
–
DVB-ASI
–
52
–
PCLK
–
treset
–
1
–
–
ms
–
Parallel Clock Frequency
fPCLK
–
13.5
–
148.5
MHz
–
Parallel Clock Duty Cycle
DCPCLK
–
40
–
60
%
–
Input Data Setup Time
tsu
–
–
ns
1
Input Data Hold Time
50% levels; +3.3V or
1.8V operation
1.2
tih
0.8
–
–
ns
1
–
–
2.97
–
Gb/s
–
Reset Pulse Width
Parallel Input
Serial Digital Output
Serial Output Data Rate
DRSDO
–
–
2.97/1.001
–
Gb/s
–
–
–
1.485
–
Gb/s
–
–
–
1.485/1.001
–
Gb/s
–
–
–
270
–
Mb/s
–
Serial Output Swing
VSDD
RSET = 750Ω
75Ω load
750
800
850
mVpp
–
Serial Output Rise/Fall Time
20% ~ 80%
trfSDO
3G/HD mode
–
120
135
ps
–
trfSDO
SD mode
400
660
800
ps
–
Mismatch in rise/fall time
Δtr,Δtf
–
–
–
35
ps
–
–
–
–
–
5
%
2
Duty Cycle Distortion
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Table 2-4: AC Electrical Characteristics (Continued)
VCC = +3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown
Parameter
Overshoot
Output Return Loss
Serial Output Intrinsic Jitter
Symbol
Conditions
Min
Typ
Max
Units
Notes
–
3G/HD mode
–
5
10
%
2
–
ORL
tOJ
SD mode
–
3
8
%
2
1.485GHz - 2.97GHz
–
-12
–
dB
3
5 MHz - 1.485 GHz
–
-18
–
dB
3
Pseudorandom and
SMPTE Colour Bars 3G
signal
–
40
68
ps
4, 6
Pseudorandom and
SMPTE Colour Bars HD
signal
–
50
95
ps
4, 6
Pseudorandom and
SMPTE Colour Bars SD
signal
–
200
400
ps
5
–
–
80
MHz
–
GSPI
GSPI Input Clock Frequency
fSCLK
50% levels
+3.3V or +1.8V
operation
GSPI Input Clock Duty Cycle
DCSCLK
GSPI Input Data Setup Time
–
GSPI Input Data Hold Time
–
GSPI Output Data Hold Time
–
15pF load
CS low before SCLK rising
edge
t0
50% levels
+3.3V or +1.8V
operation
Time between end of
command word (or data in
Auto-Increment mode) and
the first SCLK of the
following data word - write
cycle
Time between end of
command word (or data in
Auto-Increment mode) and
the first SCLK of the
following data word - read
cycle
t4
t5
GS2962 3G/HD/SD-SDI Serializer with Complete
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Final Data Sheet Rev. 8
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50% levels
+3.3V or +1.8V
operation
50% levels
+3.3V or +1.8V
operation
40
50
60
%
–
1.5
–
–
ns
–
1.5
–
–
ns
–
1.5
–
–
ns
–
1.5
–
–
ns
–
–
–
ns
–
–
–
ns
–
PCLK
(MHz)
ns
unlocked
445
13.5
74.2
27.0
37.1
74.25
13.5
148.5
6.7
PCLK
(MHz)
ns
unlocked
1187
13.5
297
27.0
148.4
74.25
53.9
148.5
27
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Table 2-4: AC Electrical Characteristics (Continued)
VCC = +3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown
Parameter
CS high after SCLK falling
edge
Symbol
t7
Conditions
50% levels
+3.3V or +1.8V
operation
Min
PCLK
(MHz)
ns
unlocked
445
13.5
74.2
27.0
37.1
74.25
13.5
148.5
6.7
Typ
Max
Units
Notes
–
–
ns
–
Notes:
1. Input setup and hold time is dependent on the rise and fall time on the parallel input. Parallel clock and data with rise time or fall time greater
than 500ps require larger setup and hold times.
2. Single Ended into 75Ω external load.
3. ORL depends on board design.
4. Alignment Jitter = measured from 100kHz to serial data rate/10.
5. Alignment Jitter = measured from 1kHz to 27MHz.
6. This is the maximum jitter for a BER of 10-12. The equivalent jitter value as per RP184 is 40ps max.
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3. Input/Output Circuits
SDO
SDO
CD_VDD
IREF
Figure 3-1: Differential Output Stage (SDO/SDO)
IO_VDD
200Ω
Input Pin
Figure 3-2: Digital Input Pin (20bit/10bit, ANC_BLANK, DETECT_TRS, DVB_ASI,
RATE_SEL0, SMPTE_BYPASS, RATE_SEL1, TIM_861, F/DE, H/HSYNC, PCLK,
V/VSYNC)
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IO_VDD
200Ω
Input Pin
Figure 3-3: Digital Input Pin with Schmitt Trigger (RESET)
IO_VDD
200Ω
Input Pin
Figure 3-4: Digital Input Pin with weak pull-down - maximum pull-down
current <110µA (JTAG/HOST, STANDBY, SCLK_TCK, SDIN_TDI, TCK, TDI)
IO_VDD IO_VDD
200Ω
Input Pin
Figure 3-5: Digital Input Pin with weak pull-up - maximum pull-up current
<110µA (CS_TMS, SDO_EN/DIS, TMS)
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IO_VDD
200Ω
Output Pin
Figure 3-6: Bidirectional Digital Input/Output Pin with programmable drive
strength. These pins are configured to input at all times except in test mode.
(DIN0, DIN2, DIN3, DIN4, DIN5, DIN6, DIN7, DIN8, DIN9, DIN10, DIN11, DIN12,
DIN13, DIN14, DIN15, DIN16, DIN17, DIN18, DIN19, DIN1)
IO_VDD
200Ω
Output Pin
Figure 3-7: Bidirectional Digital Input/Output Pin with programmable drive
strength. These pins are configured to output at all times except in reset
mode. (LOCKED, SDOUT_TDO, TDO)
GS2962 3G/HD/SD-SDI Serializer with Complete
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A_VDD
2kΩ
50Ω
VBG
Figure 3-8: VBG
PLL_VDD
30Ω
LF
30Ω
Figure 3-9: Loop Filter
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
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4. Detailed Description
4.1 Functional Overview
The GS2962 is a multi-rate Transmitter with integrated SMPTE digital video processing
and an integrated Cable Driver. It provides a complete transmit solution at 2.970Gb/s,
2.970/1.001Gb/s, 1.485Gb/s, 1.485/1.001Gb/s or 270Mb/s.
The device has four basic modes of operation that must be set through external device
pins: SMPTE mode, DVB-ASI mode, Data-Through mode and Standby mode.
In SMPTE mode, the device will accept 10-bit multiplexed or 20-bit demultiplexed
SMPTE compliant data. By default, the device's additional processing features will be
enabled in this mode.
In DVB-ASI mode, the GS2962 will accept an 8-bit parallel DVB-ASI compliant transport
stream on DIN[17:10]. The serial output data stream will be 8b/10b encoded with
stuffing characters added as per the standard.
Data-Through mode allows for the serializing of data not conforming to SMPTE or
DVB-ASI streams. No additional processing will be done in this mode.
In addition, the device may be put into Standby, to reduce power consumption.
The serial digital output features a high-impedance mode and adjustable signal swing.
The output slew rate is automatically set by the RATE_SEL0 and RATE_SEL1 pin setting.
The GS2962 provides several data processing functions; including generic ANC
insertion, SMPTE ST 352 and EDH data packet generation and insertion, automatic video
standards detection, and TRS, CRC, ANC data checksum, and line number calculation
and insertion. These features are all enabled/disabled collectively using the external I/O
processing pin, but may be individually disabled via internal registers accessible
through the GSPI host interface.
Finally, the GS2962 contains a JTAG interface for boundary scan test implementations.
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4.2 Parallel Data Inputs
Data signal inputs enter the device on the rising edge of PCLK, as shown in Figure 4-1.
DDR interface
Note: DS = Data Stream as per SMPTE ST 425
DS1_* is launched on the
positive edge of PCLK
by the source chip to the
GS2962
DS2_* is launched on the
negative edge of PCLK
by the source chip to the
GS2962
3.36ns
PCLK
TH
DIN[19:0], F_DE,
H_HSYNC, V_VSYNC
TSU
DS1_n-1
transition zone
TH
TSU
DS2_0
transition zone
DS1_n-1
TH
DS1_0
transition zone
DS2_0
DS1_0
SDR interface
DS* is launched on the positive edge of PCLK
by the source chip to the GS2962
PCLK period
PCLK
TH
TSU
DIN[19:0], F_DE,
H_HSYNC, V_VSYNC
data_0
transition zone
TH
TSU
data_1
transition zone
data_0
TH
data_1
Figure 4-1: GS2962 Video Host Interface Timing Diagrams
Table 4-1: GS2962 Digital Input AC Electrical Characteristics
Parameter
Input data set-up time
Symbol
tSU
Input data hold time
tIH
Input data set-up time
tSU
Input data hold time
tIH
Conditions
Min
Typ
Max
Units
1.2
−
−
ns
0.8
−
−
ns
1.3
−
−
ns
0.8
−
−
ns
50% levels; +1.8V operation
50% levels;
+3.3V operation
Table 4-2: GS2962 Input Video Data Format Selections
Pin/Register Bit Settings
Input Data Format
20-bit demultiplexed 3G
format
20-bit data Input
3G format
20-bit demultiplexed
HD format
20-bit data Input
HD format
DIN[9:0]
DIN[19:10]
LOW
Data Stream
Two
Data Stream One
LOW
LOW
DATA
DATA
LOW
HIGH
LOW
Chroma
Luma
LOW
LOW
LOW
DATA
DATA
20BIT
/10BIT
RATE
_SEL0
RATE
_SEL1
SMPTE
_BYPASS
DVB_ASI
HIGH
LOW
HIGH
HIGH
HIGH
LOW
HIGH
HIGH
LOW
HIGH
LOW
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Table 4-2: GS2962 Input Video Data Format Selections (Continued)
Pin/Register Bit Settings
Input Data Format
20-bit demultiplexed SD
format
20-bit data input
SD format
10-bit multiplexed
3G DDR format
10-bit multiplexed
HD format
10-bit data input
HD format
10-bit multiplexed
SD format
10-bit multiplexed
SD format
10-bit ASI input
SD format
DIN[9:0]
DIN[19:10]
LOW
Chroma
Luma
LOW
LOW
DATA
DATA
HIGH
HIGH
LOW
High
Impedance
Data Stream
One/Data Stream
Two
LOW
LOW
HIGH
LOW
High
Impedance
Luma/Chroma
LOW
LOW
LOW
LOW
LOW
High
Impedance
DATA
LOW
HIGH
X
HIGH
LOW
High
Impedance
Luma/Chroma
LOW
HIGH
X
LOW
LOW
High
Impedance
DATA
LOW
HIGH
X
LOW
HIGH
High
Impedance
DVB-ASI data
20BIT
/10BIT
RATE
_SEL0
RATE
_SEL1
SMPTE
_BYPASS
DVB_ASI
HIGH
HIGH
X
HIGH
HIGH
HIGH
X
LOW
LOW
LOW
The GS2962 is a high performance 3Gb/s capable transmitter. In order to optimize the
output jitter performance across all operating conditions, input levels and overshoot at
the parallel video data inputs of the device need to be controlled. In order to do this,
source series termination resistors should be used to match the impedance of the PCB
data trace line. IBIS models can be used to simulate the board effects and then optimize
the output drive strength and the termination resistors to allow for the best transition
(one that produces minimal overshoot). If this is not viable, Semtech recommends
matching the source series resistance to the trace impedance, and then adjusting the
output drive strength to the minimum value that will give zero errors.
The above also applies to the PCLK input line. HVF should also be well terminated,
however due to the lower data rates and transition density, it is not as critical.
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4.2.1 Parallel Input in SMPTE Mode
When the device is operating in SMPTE mode (SMPTE_BYPASS = HIGH), data must be
presented to the input bus in either multiplexed or demultiplexed form, depending on
the setting of the 20BIT/10BIT pin.
When operating in 20-bit mode (20BIT/10BIT = HIGH), the input data format must be
word aligned, demultiplexed Luma and Chroma data (SD or HD), or word aligned
demultiplexed Data Stream One and Data Stream Two data (3G).
In 3G mode, by default, the device takes Data Stream One input from data port
DIN[19:10] and Data Stream Two input from DIN[9:0].
When operating in 10-bit mode (20BIT/10BIT = LOW), the input data format must be
multiplexed Luma (Y) and Chroma (C) data (SD, HD), or multiplexed Data Stream One
and Data Stream Two data (3G). C words precede Y words, and Data Stream 2 words
precede Data Stream 1 words. In this mode, the data must be presented on the
DIN[19:10] pins. The DIN[9:0] inputs are ignored.
In 3G 10-bit mode, the device operates in DDR mode. That is, the input data is sampled
on both the rising and falling edges of the PCLK. In 3G mode, Data Stream Two words
precede Data Stream One words. The Data Stream Two words are sampled on the rising
edge of the input PCLK, and the Data Stream One words are sampled on the following
falling edge. H, V and F timing pulses, if used, are sampled on the rising edge of PCLK.
4.2.1.1 Input Data Format in SDTI Mode
SDTI and HD-SDTI are a sub-set of SDI and HD-SDI formats. They may contain SDTI data
on any line in the frame. Those lines which contain SDTI or HD-SDTI data are identified
with an SDTI or HD-SDTI header packet in the HANC space.
The GS2962 does not differentiate between a signal carrying video and a signal carrying
SDTI or HD-SDTI data in SD or HD formats. The user is responsible for ensuring that the
headers and data are not corrupted.
4.2.2 Parallel Input in DVB-ASI Mode
The GS2962 is in DVB-ASI mode when the SMPTE_BYPASS pin is set LOW, the DVB_ASI
pin is set HIGH, and the RATE_SEL0 pin is set HIGH. In this mode, all SMPTE processing
features are disabled.
When operating in DVB-ASI mode, the device must be set to 10-bit mode by setting the
20BIT/10BIT pin LOW. The device will accept 8-bit data words on DIN[17:10], where
DIN17 = HIN is the most significant bit of the encoded transport stream data and DIN10
= AIN is the least significant bit. In addition, DIN19 and DIN18 will be configured as the
DVB-ASI control signals INSSYNCIN and KIN respectively.
DIN19 = INSSYNCIN
DIN18 = KIN
DIN17~10 = HIN ~ AIN where AIN is the least significant bit of the transport stream data.
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4.2.3 Parallel Input in Data-Through Mode
Data-Through mode is enabled when the SMPTE_BYPASS pin and the DVB_ASI pin are
LOW.
In this mode, data at the input bus is serialized without any encoding, scrambling or
word alignment taking place.
The input data width is controlled by the setting of the 20BIT/10BIT pin as shown in
Table 4-2 above.
Note: When in HD 10-bit mode, asserting the SMPTE_BYPASS LOW to put the device in
SMPTE-BYPASS mode will create video errors. If the user desires to use the device as a
simple serializer in HD 10-bit mode, all video processing features may be disabled by
setting the IOPROC_EN/DIS pin LOW.
4.2.4 Parallel Input Clock (PCLK)
The frequency of the PCLK input signal of the GS2962 is determined by the input data
format and operating mode selection.
Table 4-3 below lists the input PCLK rates and input signal formats according to the
external selection pins for the GS2962.
Table 4-3: GS2962 PCLK Input Rates
Pin Settings
Input Data Format
PCLK Rate
20BIT/10BIT
RATE_
SEL0
RATE_
SEL1
SMPTE_
BYPASS
DVB-ASI
20-bit demultiplexed
3G format
HIGH
LOW
HIGH
HIGH
X
148.5 or 148.5/1.001MHz
20-bit demultiplexed
HD format
HIGH
LOW
LOW
HIGH
X
74.25 or 74.25/1.001MHz
20-bit data Input
3G format
HIGH
LOW
HIGH
LOW
LOW
148.5 or 148.5/1.001MHz
20-bit data input
HD format
HIGH
LOW
LOW
LOW
LOW
74.25 or 74.25/1.001MHz
20-bit demultiplexed
SD format
HIGH
HIGH
X
HIGH
LOW
13.5MHz
20-bit data input
SD format
HIGH
HIGH
X
LOW
LOW
13.5MHz
10-bit multiplexed
3G DDR format
LOW
LOW
HIGH
HIGH
LOW
148.5 or 148.5/1.001MHz
10-bit multiplexed
HD format
LOW
LOW
LOW
HIGH
LOW
148.5 or 148.5/1.001MHz
10-bit data input
HD format
LOW
LOW
LOW
LOW
LOW
148.5 or 148.5/1.001MHz
10-bit multiplexed
SD format
LOW
HIGH
X
HIGH
X
27MHz
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Table 4-3: GS2962 PCLK Input Rates (Continued)
Pin Settings
Input Data Format
PCLK Rate
20BIT/10BIT
RATE_
SEL0
RATE_
SEL1
SMPTE_
BYPASS
DVB-ASI
10-bit data input
SD format
LOW
HIGH
X
LOW
LOW
27MHz
10-bit ASI input
SD format
LOW
HIGH
X
LOW
HIGH
27MHz
4.3 SMPTE Mode
The function of this block is to carry out data scrambling according to
SMPTE ST 424/SMPTE ST 292, and to carry out NRZ to NRZI encoding prior to
presentation to the parallel to serial converter.
These functions are only enabled when the SMPTE_BYPASS pin is HIGH.
In addition, the GS2962 requires the DVB_ASI pin to be set LOW to enable this feature.
4.3.1 H:V:F Timing
In SMPTE mode, the GS2962 can automatically detect the video standard and generate
all internal timing signals. The total line length, active line length, total number of lines
per field/frame and total active lines per field/frame are calculated for the received
parallel video.
When DETECT_TRS is LOW, the video standard and timing signals are based on the
externally supplied H_Blanking, V_Blanking, and F_Digital signals. These signals are
supplied by the H/HSYNC, V/VSYNC and F/DE pins respectively. When DETECT_TRS is
HIGH, the video standard timing signals will be extracted from the embedded TRS ID
words in the parallel input data. Both 8-bit and 10-bit TRS code words will be identified
by the device.
Note: I/O processing must be enabled for the device to remap 8-bit TRS words to the
corresponding 10-bit value for transmission.
The GS2962 determines the video standard by timing the horizontal and vertical
reference information supplied at the H/HSYNC, V/VSYNC, and F/DE input pins, or
contained in the TRS ID words of the received video data. Therefore, full
synchronization to the received video standard requires at least one complete video
frame.
Once synchronization has been achieved, the GS2962 will continue to monitor the
received TRS timing or the supplied H, V, and F timing information to maintain
synchronization. The GS2962 will lose all timing information immediately following loss
of H, V and F.
The H signal timing should also be configured via the H_CONFIG bit of the internal
IOPROC register as either active line based blanking or TRS based blanking.
Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this mode,
the H input should be HIGH for the entire horizontal blanking period, including the EAV
and SAV TRS words. This is the default H timing used by the device.
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The timing of these signals is shown in Figure 4-5, Table 4-3, Table 4-4, Table 4-5,
Table 4-6, Table 4-7 and Table 4-8.
PCLK
LUMA DATA
CHROMA DATA
H
V
F
3FF
000
000
XYZ (EAV)
3FF
000
000
XYZ (SAV)
3FF
000
000
XYZ (EAV)
3FF
000
000
XYZ (SAV)
Figure 4-2: H:V:F Output Timing - 3G Level A and HDTV 20-bit Mode
PCLK (3G DDR)
PCLK (HD)
MULTIPLEXED Y’CbCr DATA (HD)
MULTIPLEXED DS1/DS2 DATA (3G)
H
V
F
3FF
3FF
000
000
000
000
XYZ (EAV) XYZ (EAV)
H VF T IM IN G A T E A V
PCLK (3G DDR)
PCLK (HD)
MULTIPLEXED Y’CbCr DATA (HD)
MULTIPLEXED DS1/DS2 DATA (3G)
3FF
3FF
000
000
000
000
XYZ (SAV) XYZ (SAV)
H
V
F
H VF T IM IN G A T S A V
H S IG N A L T IM IN G :
H _ C O N F IG = L O W
H _ C O N F IG = H IG H
Figure 4-3: H:V:F Output Timing - 3G Level A and HDTV 10-bit Mode
3G Level B 20-bit Mode, each 10-bit stream
PCLK (DDR)
MULTIPLEXED LINKA/LINKB DATA
H
V
F
3FF
3FF 3FF 3FF 000 000 000 000 000 000 000 000
XYZ
(eav)
XYZ
(eav)
XYZ
(eav)
XYZ
(eav)
H VF T IM IN G A T E A V
PCLK (DDR)
MULTIPLEXED LINKA/LINKB DATA
H
V
3FF 3FF
3FF 3FF 000 000 000 000 000 000 000 000
XYZ
(sav)
XYZ
(sav )
XYZ
(sav )
XYZ
(sav )
F
H VF T IM IN G A T S A V
H S IG N A L T IM IN G :
H _ C O N F IG = L O W
H _ C O N F IG = H IG H
Figure 4-4: H:V:F Output Timing - 3G Level B 10-bit Mode
PC LK
L U M A D A T A IN P U T
C H R O M A D A T A IN P U T
H
V
F
3FF
000
000
X Y Z (EAV)
3FF
000
000
X Y Z (SAV)
3FF
000
000
X Y Z (EAV)
3FF
000
000
X Y Z (SAV)
H S IG N A L T IM IN G :
H _ C O N F IG = L O W
H _ C O N F IG = H IG H
Figure 4-5: H:V:F Input Timing - HD 20-bit Input Mode
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
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PC LK
M U L T IP L E X E D Y 'C b C r D A T A IN P U T
3FF
3FF
000
000
000
000
X Y Z (EAV)
X Y Z (EAV)
H
V
F
H V F T IM IN G A T E A V
PC LK
M U L T IP L E X E D Y 'C b C r D A T A IN P U T
3FF
3FF
000
000
000
000
X Y Z (SAV) X Y Z (SAV)
H
V
F
H V F T IM IN G A T S A V
Figure 4-6: H:V:F Input Timing - HD 10-bit Input Mode
P C LK
C H R O M A D A T A IN P U T
L U M A D A T A IN P U T
H
V
F
3FF
000
3FF
000
000
X Y Z (EAV)
000
X Y Z (SAV)
H S IG N A L T IM IN G :
H _ C O N F IG = L O W
H _ C O N F IG = H IG H
Figure 4-7: H:V:F Input Timing - SD 20-bit Mode
PC LK
M U L T IP L E X E D Y 'C b C r D A T A IN P U T
H
V
F
3FF
000
000
H S IG N A L T IM IN G :
X Y Z (EAV)
H _ C O N F IG = L O W
3FF
000
000
X Y Z (SAV)
H _ C O N F IG = H IG H
Figure 4-8: H:V:F Input Timing - SD 10-bit Mode
4.3.2 CEA 861 Timing
The GS2962 extracts timing information from externally provided HSYNC, VSYNC, and
DE signals when CEA 861 timing mode is selected by setting DETECT_TRS = LOW and
TIM_861 = HIGH.
Horizontal sync (H), Vertical sync (V), and Data Enable (DE) timing must be provided via
the H/HSYNC, V/VSYNC and F/DE input pins. The host interface register bit H_CONFIG
is ignored in CEA 861 input timing mode.
The GS2962 determines the EIA/CEA-861 standard and embeds EAV and SAV TRS
words in the output serial video stream.
Video standard detection is not dependent on the HSYNC pulse width or the VSYNC
pulse width and therefore the GS2962 tolerates non-standard pulse widths. In addition,
the device can compensate for up to ±1 PCLK cycle of jitter on VSYNC with respect to
HSYNC and sample VSYNC correctly.
Note 1: The period between the leading edge of the HSYNC pulse and the leading edge
of Data Enable (DE) must follow the timing requirements described in the EIA/CEA-861
specification. The GS2962 embeds TRS words according to this timing relationship to
maintain compatibility with the corresponding SMPTE standard.
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Note 2: When CEA 861 standards 6 & 7 [720(1440)x480i] are presented to the GS2962,
the device embeds TRS words corresponding to the timing defined in SMPTE ST 125 to
maintain SMPTE compatibility.
CEA 861 standards 6 & 7 [720(1440)x480i] define the active area on lines 22 to 261 and
285 to 524 inclusive (240 active lines per field). SMPTE ST 125 defines the active area on
lines 20 to 263 and 283 to 525 inclusive (244 lines on field 1, 243 lines on field 2).
Therefore, in the first field, the GS2962 adds two active lines above and two active lines
below the original active image. In the second field, it adds two lines above and one line
below the original active image.
The CEA 861 Timing Formats are summarized in Table 4-4. and are shown in Figure 4-9
to Figure 4-19.
Table 4-4: CEA861 Timing Formats
Format
Parameters
4
H:V:DE Input Timing 1280 x 720p @ 59.94/60Hz
5
H:V:DE Input Timing 1920 x 1080i @ 59.94/60Hz
6&7
H:V:DE Input Timing 720 (1440) x 480i @ 59.94/60Hz
19
H:V:DE Input Timing 1280 x 720p @ 50Hz
20
H:V:DE Input Timing 1920 x 1080i @ 50Hz
21&22
H:V:DE Input Timing 720 (1440) x 576 @ 50Hz
16
H:V:DE Input Timing 1920 x 1080p @ 59.94/60Hz
31
H:V:DE Input Timing 1920 x 1080p @ 50Hz
32
H:V:DE Input Timing 1920 x 1080p @ 23.94/24Hz
33
H:V:DE Input Timing 1920 x 1080p @ 25Hz
34
H:V:DE Input Timing 1920 x 1080p @ 29.97/30Hz
GS2962 3G/HD/SD-SDI Serializer with Complete
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34 of 81
1660 Total Horizontal Clocks per line
Data
Enable
370
1280 Clocks for Active Video
40
110
220 clocks
HSYNC
~
~
~
720 Active Vertical Lines
~
Progressive Frame: 30 Vertical Blanking Lines
~
~
~
~
Data
Enable
1650 clocks
110
260
745 746 747 748
749
750 1
2
3
4
5
6
25
7
~
~
~
~
HSYNC
745 746
26
750
VSYNC
Figure 4-9: H:V:DE Input Timing 1280 x 720p @ 59.94/60 (Format 4)
2200 Total Horizontal Clocks per line
Data
Enable
280
44
88
1920 Clocks for Active Video
148 clocks
HSYNC
~
~
2
~
192
HSYNC
1123 1124 1125 1
~
2200 clocks
88
~
~
~
Data
Enable
~
540 Active Vertical Lines per field
Field 1: 22 Vertical Blanking Lines
3
4
5
6
7
8
19
20
21
560 561 562
VSYNC
~
~
~
~
540 Active Vertical Lines per field
Field 2: 23 Vertical Blanking Lines
~
~
Data
Enable
2200 clocks
1100
88
192
~
~
HSYNC
560
561
562 563 564 565 566 567 568
569 570
582
583
584
1123 1124 1125
VSYNC
Figure 4-10: H:V:DE Input Timing 1920 x 1080i @ 59.94/60 (Format 5)
GS2962 3G/HD/SD-SDI Serializer with Complete
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1716 Total Horizontal Clocks per line
Data
Enable
276
124
38
1440 Clocks for Active Video
114 clocks
HSYNC
~
~
~
~
~
Data
Enable
240 Active Vertical Lines per field
~
Field 1: 22 Vertical Blanking Lines
1716 clocks
38
238
HSYNC
524 525
1
2
3
4
5
6
7
8
9
21
22
261 262 263
VSYNC
~
~
240 Active Vertical Lines per field
Field 2: 23 Vertical Blanking Lines
~
~
Data
Enable
1716 clocks
38
238
858
HSYNC
284 285
261 262 263 264 265 266 267 268 269 270 271
524 525
1
VSYNC
Figure 4-11: H:V:DE Input Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7)
1980 Total Horizontal Clocks per line
Data
Enable
700
40
440
1280 Clocks for Active Video
220 clocks
HSYNC
~
1980 clocks
260
745 746 747
748 749
750
1
2
3
4
5
6
7
~
~
~
HSYNC
~
~
440
~
~
~
~
Data
Enable
~
720 Active Vertical Lines
Progressive Frame: 30 Vertical Blanking Lines
25
26
745 746
750
VSYNC
Figure 4-12: H:V:DE Input Timing 1280 x 720p @ 50 (Format 19)
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
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36 of 81
2640 Total Horizontal Clocks per line
Data
Enable
720
44
1920 Clocks for Active Video
148 clocks
528
HSYNC
~
~
~
~
~
Data
Enable
~
540 Active Vertical Lines per field
Field 1: 22 Vertical Blanking Lines
2640 clocks
528
192
~
~
HSYNC
1123 1124 1125 1
2
3
4
5
6
7
8
19
20
21
560 561 562
VSYNC
~
~
~
~
540 Active Vertical Lines per field
Field 2: 23 Vertical Blanking Lines
~
~
Data
Enable
2640 clocks
1320
528
192
~
~
HSYNC
560
561
562 563 564 565 566 567 568
569 570
582
583
584
1123 1124 1125
VSYNC
Figure 4-13: H:V:DE Input Timing 1920 x 1080i @ 50 (Format 20)
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
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37 of 81
1728 Total Horizontal Clocks per line
Data
Enable
288
126
24
1440 Clocks for Active Video
138 clocks
HSYNC
~
~
~
~
~
Data
Enable
~
288 Active Vertical Lines per field
Field 1: 24 Vertical Blanking Lines
1728 clocks
264
~~
24
HSYNC
623 624 625
1
2
3
4
5
6
7
22
23
310 311 312
VSYNC
~
~
288 Active Vertical Lines per field
Field 2: 25 Vertical Blanking Lines
~
~
Data
Enable
24
1728 clocks
864
264
HSYNC
310 311 312
313 314 315 316 317 318 319 320
335 336
623 624 625
VSYNC
Figure 4-14: H:V:DE Input Timing 720 (1440) x 576 @ 50 (Format 21&22)
2200 Total Horizontal Clocks per line
Data
Enable
88
280
1920 Clocks for Active Video
44
148 clocks
HSYNC
Progressive Frame: 45 Vertical Blanking Lines
~
~
~
2200 clocks
~
1
2
3
4
5
6
7
41
42
~
~
192
HSYNC
1121 1122 1123 1124 1125
~
88
~
~
Data
Enable
1080 Active Vertical Lines
1121 1122 1123 1124 1125
VSYNC
Figure 4-15: H:V:DE Input Timing 1920 x 1080p @ 59.94/60 (Format 16)
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
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38 of 81
2640 Total Horizontal Clocks per line
Data
Enable
720
44
528
1920 Clocks for Active Video
148 clocks
HSYNC
~
~
1
2
3
4
5
6
7
41
42
~
~
192
HSYNC
1121 1122 1123 1124 1125
~
2640 clocks
528
~
~
~
Data
Enable
~
1080 Active Vertical Lines
Progressive Frame: 45 Vertical Blanking Lines
1121 1122 1123 1124 1125
VSYNC
Figure 4-16: H:V:DE Input Timing 1920 x 1080p @ 50 (Format 31)
2750 Total Horizontal Clocks per line
Data
Enable
830
44
638
1920 Clocks for Active Video
148 clocks
HSYNC
Progressive Frame: 45 Vertical Blanking Lines
~
~
~
~
~
~
Data
Enable
1080 Active Vertical Lines
2750 clocks
192
~
HSYNC
1121 1122 1123 1124 1125
1
2
3
4
5
6
7
41
42
~
~
638
1121 1122 1123 1124 1125
VSYNC
Figure 4-17: H:V:DE Input Timing 1920 x 1080p @ 23.94/24 (Format 32)
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
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39 of 81
2640 Total Horizontal Clocks per line
Data
Enable
720
44
528
1920 Clocks for Active Video
148 clocks
HSYNC
Progressive Frame: 45 Vertical Blanking Lines
~
~
~
2640 clocks
~
1
2
3
4
5
6
7
41
42
~
~
192
HSYNC
1121 1122 1123 1124 1125
~
528
~
~
Data
Enable
1080 Active Vertical Lines
1121 1122 1123 1124 1125
VSYNC
Figure 4-18: H:V:DE Input Timing 1920 x 1080p @ 25 (Format 33)
2200 Total Horizontal Clocks per line
Data
Enable
280
44
88
1920 Clocks for Active Video
148 clocks
HSYNC
Progressive Frame: 45 Vertical Blanking Lines
~
~
~
2220 clocks
~
1
2
3
4
5
6
7
41
42
~
~
192
HSYNC
1121 1122 1123 1124 1125
~
88
~
~
Data
Enable
1080 Active Vertical Lines
1121 1122 1123 1124 1125
VSYNC
Figure 4-19: H:V:DE Input Timing 1920 x 1080p @ 29.97/30 (Format 34)
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
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40 of 81
4.4 DVB-ASI Mode
When operating in DVB-ASI mode, all SMPTE processing features are disabled, and the
device accepts 8-bit transport stream data and control signal inputs on the DIN[19:10]
port.
This mode is only enabled when SMPTE_BYPASS pin is LOW, DVB_ASI pin is HIGH and
the RATE_SEL0 pin is HIGH.
The interface consists of eight data bits and two control signals, INSSYNCIN and KIN.
When INSSYNCIN is set HIGH, the GS2962 inserts K28.5 sync characters into the data
stream. This function is used to assist system implementations where the GS2962 may
be preceded by a data FIFO.
The FIFO can be fed data at a rate somewhat less than 27MHz. The ‘FIFO empty’ signal
could be used to feed the INSSYNCIN pin, causing the GS2962 to pad the data up to the
transmission rate of 27MHz.
When KIN is set HIGH the data input is interpreted as a special character (such as a K28.5
sync character), as defined by the DVB-ASI standard. When KIN is set LOW the input is
interpreted as data.
After sync signal insertion, the GS2962 8b/10b encodes the data, generating a 10-bit
data stream for the parallel to serial conversion and transmission process.
4.5 Data-Through Mode
The GS2962 may be configured to operate as a simple parallel-to-serial converter. In this
mode, the device passes data to the serial output without performing any scrambling or
encoding.
Data-through mode is enabled only when both the SMPTE_BYPASS and DVB_ASI pins
are set LOW.
4.6 Standby Mode
The STANDBY pin reduces power to a minimum by disabling all circuits except for the
register configuration. Upon removal of the signal to the STANDBY pin, the device
returns to its previous operating condition within 1 second, without requiring input
from the host interface.
In addition, the serial digital output signals becomes high-impedance when the device
is powered-down.
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
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41 of 81
4.7 ANC Data Insertion
Horizontal or vertical ancillary data words may be inserted on up to four different lines
per video frame.
Up to 512 data words may be inserted per frame with all Data Words - including the ANC
packet ADF, DBN, DCNT, DID, SDID and CSUM words - being provided by the user via
host interface configuration.
The CSUM word is re-calculated and inserted by the ANC Data Checksum Calculation
and Insertion function.
Note that any value may be used for the CSUM word, provided that it is outside the
protected ranges from 000h to 003h and from 3FCh to 3FFh. If a CSUM value in either of
these ranges is used, it will not be corrected by the device.
The GS2962 does not provide error checking or correction to the ANC data provided by
user via the host interface. It is the responsibility of the user to ensure that all data
provided for insertion is fully standard compliant.
In 3G Level A mode, ancillary data packets are inserted into Data Stream One or Data
Stream Two as selected by the host interface. The default insertion will be in Data Stream
One. See address 02Dh, STREAM_TYPE1_LINE_X.
In 3G Level B mode, ancillary data packets are inserted into the Y or C video stream of
Link A or Link B as selected by the user in the host interface. The default insertion will
be in the Y video stream of Link A. For Link A or Link B, see Register 02Dh. For Y or C, see
Registers 026h, 028h, 02Ah and 02Ch.
In HD mode, ANC data packets are inserted into the Y or C video stream, as selected via
the host interface. The default insertion will be in the Y stream. For Y or C, see Registers
026h, 028h, 02Ah and 02Ch.
In SD mode, the ANC data packets are inserted into the multiplexed CbYCr data stream.
ANC data insertion only takes place if the IOPROC_EN/DIS pin is HIGH and
SMPTE_BYPASS is HIGH.
In addition to this, the GS2962 requires the ANC_INS bit to be set LOW in the IOPROC
register.
4.7.1 ANC Insertion Operating Modes
User selection of one of the two operating modes is provided through host interface
configuration, using the ANC_INS_MODE register bit (see Table 4-17: Configuration and
Status Registers).
The supported operating modes are Concatenated mode and Separate Line operating
mode.
By default (at power up or after system reset), the Separate Line operating mode is
enabled.
Ancillary data packets are programmed into the ANC_PACKET_BANK host register at
addresses 040h to BFFh.
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4.7.1.1 Separate Line Operating Mode
In Separate Line mode, it is possible to insert horizontal or vertical ancillary data on up
to four lines per video frame. In Separate Line Mode, the ANC_PACKET_BANK bits are
separated in four sections. Each section consists of 64x16-bit registers.
ANC_PACKET_BANK_1 uses registers 040h to 07Fh. ANC_PACKET_BANK_2 uses
registers 080h to 0BFh. ANC_PACKET_BANK_3 uses registers 0C0h to 0FFh.
ANC_PACKET_BANK_4 uses registers 100h to 13Fh. HANC or VANC can be specified,
independently of each other, on a per-line basis. 025h FIRST_LINE_NUMBER, 027h
SECOND_LINE_NUMBER, 029h THIRD_LINE_NUMBER and 02Bh
FOURTH_LINE_NUMBER. For each of the four video lines, up to 128 8-bit HANC or
VANC data words can be inserted. Separate Line mode is selected by setting the
ANC_INS_MODE bit in the host interface LOW. By default, at power up, Separate Line
mode is selected.
The lines on which ancillary data is to be inserted is programmed in the host register
addresses 025h to 02Ch.
For HD formats, the stream into which the ancillary data is to be inserted (Luma or
Chroma) is also programmed in these register addresses.
The non-zero video line numbers on which to insert the ancillary data, the ancillary data
type (HANC or VANC), and the total number of words to insert per line must be provided
via the host interface (see Section 4.12). At power up, or after system reset, all ancillary
data insertion line numbers and total number of words default to zero.
If the total number of Data Words specified per line exceeds 128 only the first 128 Data
Words will be inserted, the rest will be ignored.
The data words are programmed as two 8-bit values per address, starting at host
interface address 040h in the ANC_PACKET_BANK register (see Table 4-17).
The device automatically converts the provided 8-bit Data Words into the 10-bit data,
formatted according to SMPTE ST 291 prior to insertion.
4.7.1.2 Concatenated Operating Mode
In Concatenated mode, it is possible to insert up to 512 8-bit horizontal or vertical
ancillary Data Words on one line per video frame. Concatenated Line mode can be
selected by setting the ANC_INS_MODE bit in the host interface HIGH. By default, at
power up, Separate Line mode is selected.
In Concatenated mode, only the FIRST_LINE registers of the host interface need to be
programmed (addresses 025h and 026h). See Table 4-17.
The non-zero video line number on which to insert the ancillary data, the ancillary data
type (HANC or VANC), and the total number of words to insert must be provided via the
host interface. At power up, or after system reset, the ancillary data insertion line
number and total number of words default to zero.
If the total number of data words specified exceeds 512 only the first 512 Data Words
will be inserted, the rest will be ignored.
The data words are programmed as two 8-bit values per address, starting at host
interface address 040h in the ANC_PACKET_BANK register. See Table 4-17.
The device automatically converts the provided 8-bit data words into the 10-bit data
formatted according to SMPTE ST 291 prior to insertion.
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4.7.2 3G ANC Insertion
4.7.2.1 Level A Mode
When operating in 3G (RATE _SEL0 = LOW, RATE_SEL1 = HIGH) Level A mode, the
GS2962 inserts VANC or HANC data packets into Data Stream One (default) or Data
Stream Two.
The data stream for insertion is selectable for each of the ANC insertion lines selected via
the host interface. Data Stream One is selected when the STREAM_TYPE_1 bit in the
register associated with the insertion line is set LOW (default). Data Stream Two is
selected when the STREAM_TYPE_1 bit associated with the insertion line is set HIGH.
ANC data should be placed in DS1 first in Level A mode, and only in DS2 as an overflow
if DS1 is full. Data insertion starts at the first available location in the HANC space
following any pre-existing arbitrary data packets.
All Data Words identified by the user are inserted in a contiguous fashion starting at the
first available data space. HANC data insertion terminates when all Data Words
identified by the user have been inserted; or by the start of the four word TRS SAV code,
regardless of the number of Data Words actually inserted. The rest of the packet will be
ignored.
Vertical Ancillary data (VANC), is inserted into the data stream on the video line(s)
defined by the user. Data insertion starts at the first active pixel immediately following
the last word of the TRS SAV code.
All Data Words identified by the user are inserted in a contiguous fashion, starting at the
first active pixel. VANC data insertion terminates when all data words identified by the
user have been inserted; or by the start of the four word TRS EAV code, regardless of the
number of Data Words actually inserted.
The total number of Data Words to be inserted and the line number on which the ANC
data insertion takes place is provided by the user via the host interface as part of the
configuration of the ANC data insertion function.
The user data for insertion is provided via the host interface register STREAM_TYPE_1
(02Dh).
4.7.2.2 Level B Mode
When operating in 3G (RATE_SEL0 = LOW, RATE_SEL1 = HIGH) Level B mode, the
GS2962 inserts VANC or HANC data packets into either the Y or C data stream of Data
Stream One (default) or Data Stream Two, as selected by the STREAM_TYPE_1 bit in the
host interface on a per line basis.
By default (at power up or after system reset), all ANC data insertion takes place in the Y
data stream of Data Stream One.
The user can select between the Y or C data stream for insertion on a per line basis in
Separate Line mode. The Y data stream is selected when the STREAM_TYPE_0 bit is LOW
(default). The C data stream is selected when the STREAM_TYPE_0 bit is HIGH.
The user can select between the Y or C data stream for insertion on a single line basis in
Concatenated mode. The Y data stream is selected when the STREAM_TYPE_0 bit is
LOW (default). The C data stream is selected when the STREAM_TYPE_0 bit is HIGH.
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44 of 81
Horizontal Ancillary data (HANC), is inserted into the Y or C data stream on the video
line(s) defined by the user.
Data insertion starts at the first available location in the HANC space following any
pre-existing arbitrary data packets. All Data Words identified by the user are inserted in
a contiguous fashion, starting at the first available data space.
HANC data insertion terminates when all Data Words identified by the user have been
inserted; or by the start of the four word TRS SAV code, regardless of the number of data
words actually inserted.
Vertical Ancillary data (VANC), is inserted into the Y or C data stream on the video line(s)
defined by the user.
Data insertion starts at the first active pixel immediately following the last word of the
TRS SAV code. All Data Words identified by the user are inserted in a contiguous fashion
starting at the first active pixel.
VANC data insertion terminates when all Data Words identified by the user have been
inserted; or by the start of the four word TRS EAV code, regardless of the number of Data
Words actually inserted.
The total number of data words to be inserted and line number on which ANC data
insertion takes place is provided by the user via the host interface as part of the
configuration of the ANC data insertion function.
The user data for insertion is provided via the host interface. STREAM_TYPE_1 = address
02Dh, STREAM_TYPE_0 for the four lines of insertion is at addresses 026h (bit 14), 028h
(bit 14), 02Ah (bit 14) and 02Ch (bit 14).
4.7.3 HD ANC Insertion
When operating in HD mode (RATE_SEL0 = LOW, RATE_SEL1 = LOW), the GS2962
inserts VANC or HANC data packets into either the Y data stream or C data stream.
By default (at power up or after system reset), all ANC data insertion takes place in the Y
data stream.
The user can select between Y or C data stream for insertion on a per line basis in
Separate Line mode. The Y data stream is selected when the STREAM_TYPE_0 bit is LOW
(default). The C data stream is selected when the STREAM_TYPE_0 bit is HIGH.
The user can select between Y or C data stream for insertion on a single line basis in
Concatenated mode. The Y data stream is selected when the STREAM_TYPE_0 bit is
LOW (default). The C data stream is selected when the STREAM_TYPE_0 bit is HIGH.
Horizontal Ancillary data (HANC), is inserted into the Y or C data stream on the video
line(s) defined by the user.
Data insertion starts at the first available location in the HANC space, following any
pre-existing arbitrary data packets. All Data Words identified by the user are inserted in
a contiguous fashion starting at the first available data space.
HANC data insertion terminates when all Data Words identified by the user have been
inserted; or by the start of the four word TRS SAV code, regardless of the number of Data
Words actually inserted.
Vertical Ancillary data (VANC), is inserted into the Y or C data stream on the video line(s)
defined by the user.
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
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45 of 81
Data insertion starts at the first active pixel immediately following the last word of the
TRS SAV code. All Data Words identified by the user are inserted in a contiguous
fashion, starting at the first active pixel.
VANC data insertion terminates when all Data Words identified by the user have been
inserted; or by the start of the four word TRS EAV code, regardless of the number of Data
Words actually inserted.
The total number of Data Words to be inserted and the line number on which ANC data
insertion takes place is provided by the user via the host interface as part of the
configuration of the ANC data insertion function.
The user data for insertion is provided via host interface configuration.
STREAM_TYPE_1 = address 02Dh, STREAM_TYPE_0 for the four lines of insertion is at
addresses 026h (bit 14), 028h (bit 14), 02Ah (bit 14) and 02Ch (bit 14).
4.7.4 SD ANC Insertion
When operating in SD mode (RATE_SEL0 = HIGH), the GS2962 inserts VANC or HANC
data packets into the multiplexed CbYCr data stream.
Horizontal Ancillary data (HANC), is inserted on the video line(s) defined by the user.
Data insertion starts at the first available location in the HANC space following any
pre-existing arbitrary data packets. All Data Words identified by the user are inserted in
a contiguous fashion, starting at the first available data space.
HANC data insertion terminates when all Data Words identified by the user have been
inserted; or by the start of the four word TRS SAV code, regardless of the number of Data
Words actually inserted.
For the case where HANC data insertion is required on the same line as the EDH packet,
data insertion is terminated by the start of the EDH packet, regardless of the number of
Data Words actually inserted.
Vertical Ancillary data (VANC), is inserted into the data stream on the video line(s)
defined by the user.
Data insertion starts at the first active Cb pixel immediately following the last word of
the TRS SAV code. All data words identified by the user are inserted in a contiguous
fashion, starting at the first active pixel.
VANC data insertion terminates when all Data Words identified by the user have been
inserted; or by the start of the four word TRS EAV code, regardless of the number of Data
Words actually inserted.
The total number of data words to be inserted and the line number on which ANC data
insertion takes place is provided by the user via the host interface as part of the
configuration of the ANC data insertion function.
The user data for insertion is provided via host interface configuration.
STREAM_TYPE_1 = address 02Dh, STREAM_TYPE_0 for the four lines of insertion is at
addresses 026h (bit 14), 028h (bit 14), 02Ah (bit 14) and 02Ch (bit 14).
ANC data checksum insertion only takes place if the IOPROC_EN/DIS pin is HIGH, the
SMPTE_BYPASS is HIGH and the ANC_CSUM_INS bit is set LOW in the IOPROC register.
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46 of 81
4.8 Additional Processing Functions
The GS2962 contains a number of signal processing features. These features are only
enabled in SMPTE mode of operation (SMPTE_BYPASS = HIGH), and when I/O
processing is enabled (IOPROC_EN/DIS = HIGH).
Signal processing features include:
•
TRS generation and insertion
•
Line number calculation and insertion
•
Line based CRC calculation and insertion
•
Illegal code re-mapping
•
SMPTE ST 352 payload identifier packet insertion
•
ANC checksum calculation and correction
•
EDH generation and insertion
•
SMPTE ST 372 conversion
To enable these features in the GS2962, the SMPTE_BYPASS pin must be HIGH, the
IOPROC_EN/DIS pin must be HIGH and the individual feature must be enabled via bits
set in the IOPROC register of the host interface. By default, all of the processing features
are enabled, except for SMPTE ST 372 correction.
4.8.1 Video Format Detection
By using the timing parameters extracted from the received TRS signals, or the supplied
external timing signals, the GS2962 calculates the video format.
The total samples per line, active samples per line, total lines per field/frame, and active
lines per field/frame are measured and reported to the user via the four
RASET_STRUC_X registers in the host interface.
These line and sample count registers are updated once per frame at the end of line 12.
The RASET_STRUC_X registers also contain two status bits: STD_LOCK and INT/PROG.
The STD_LOCK bit is set HIGH whenever the automatic video format detection circuit
has achieved full synchronization.
The INT/PROG bit is set LOW if the detected video standard is Progressive, and is set
HIGH if the detected video standard is Interlaced.
The Gennum video standard code (VD_STD), as used in the GS2972, GS1582 and
GS1572, is included in Table 4-5 for reference purposes.
Note: If proper SMPTE video is applied and then removed from the input, the device
does not flag that the H_LOCK, V_LOCK, VD_SDT etc. has changed (been lost). This is the
case for either TRS detect or HVF modes. This problem occurs only when the video data
is removed, but not the PCLK. Usually, when a video signal is removed, it includes the
clock, the video data, as well as the H, V, F as a whole. So the scenario is not likely to
occur, but the user should be aware of this issue.
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
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Table 4-5: Supported Video Standards
SMPTE
STANDARD
ACTIVE
VIDEO
AREA
LENGTH
OF
HANC
LENGTH
OF ACTIVE
VIDEO
TOTAL
SAMPLES
SMPTE
ST 352
LINES
Gennum
VD_STD
[4:0]
RATE_
SEL1
ST 428.1
2048x1080/24 (1:1)
690
2048
2750
10
1Ch
1
ST 428.1
2048x1080/25 (1:1)
580
2048
2640
10
1Ch
1
1920x1080/60 (1:1)
268
1920
2200
10 (18)1
0Bh
1
1920x1080/50 (1:1)
708
1920
2640
10 (18)1
0Dh
1
1920x1080/60 (2:1)
or
2682
19202
2200
10, 572
0Ah
1
7082
19202
2640
10, 572
0Ch
1
1280x720/60 (1:1)
3582
12802
1650
10 (13)1
00h
1
1280x720/50 (1:1)
6882
12802
1980
10 (13)1
04h
1
1920x1080/30 (1:1)
2682
19202
2200
10 (18)1
0Bh
1
1920x1080/25 (1:1)
7082
19202
2640
10 (18)1
0Dh
1
1280x720/25 (1:1)
26682
12802
3960
10 (13)1
06h
1
1920x1080/24 (1:1)
8182
19202
2750
10 (18)1
10h
1
1280x720/24 (1:1)
28332
12802
4125
10 (13)1
08h
1
ST 260 (HD)
1920x1035/60 (2:1)
268
1920
2200
10, 572
15h
0
ST 295 (HD)
1920x1080/50 (2:1)
444
1920
2376
10, 572
14h
0
1920x1080/60 (2:1)
or
268
1920
2200
10, 572
0Ah
0
708
1920
2640
10, 572
0Ch
0
1920x1080/30 (1:1)
268
1920
2200
10 (18)1
0Bh
0
1920x1080/25 (1:1)
708
1920
2640
10 (18)1
0Dh
0
1920x1080/24 (1:1)
818
1920
2750
10 (18)1
10h
0
1920x1080/24 (PsF)
818
1920
2750
10, 572
11h
0
1920x1080/25 (1:1) –
EM
324
2304
2640
10 (18)1
0Eh
0
1920x1080/25 (PsF) –
EM
324
2304
2640
10, 572
0Fh
0
1920x1080/24 (1:1) –
EM
338
2400
2750
10 (18)1
12h
0
1920x1080/24 (PsF) –
EM
338
2400
2750
10, 572
13h
0
ST 425 (3G)
4:2:2
1920x1080/30 (PsF)
1920x1080/50 (2:1)
or
1920x1080/25 (PsF)
ST 425 (3G)
4:4:4
1920x1080/30 (PsF)
1920x1080/50 (2:1)
or
1920x1080/25 (PsF)
ST 274 (HD)
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Table 4-5: Supported Video Standards (Continued)
LENGTH
OF
HANC
LENGTH
OF ACTIVE
VIDEO
TOTAL
SAMPLES
SMPTE
ST 352
LINES
Gennum
VD_STD
[4:0]
RATE_
SEL1
1280x720/30 (1:1)
2008
1280
3300
10 (13)1
02h
0
1280x720/30 (1:1) –
EM
408
2880
3300
10 (13)1
03h
0
1280x720/50 (1:1)
688
1280
1980
10 (13)1
04h
0
1280x720/50 (1:1) –
EM
240
1728
1980
10 (13)1
05h
0
1280x720/25 (1:1)
2668
1280
3960
10 (13)1
06h
0
1280x720/25 (1:1) –
EM
492
3456
3960
10 (13)1
07h
0
1280x720/24 (1:1)
2833
1280
4125
10 (13)1
08h
0
1280x720/24 (1:1) –
EM
513
3600
4125
10 (13)1
09h
0
1280x720/60 (1:1)
358
1280
1650
10 (13)1
00h
0
1280x720/60 (1:1) –
EM
198
1440
1650
10 (13)1
01h
0
(Or dual link
progressive)
268
1440
1716
13, 276
16h
X
1440x507/60 (2:1)
268
1440
1716
13, 276
17h
X
525-line 487 generic
−
−
1716
13, 276
19h
X
525-line 507 generic
−
−
1716
13, 276
1Bh
X
280
1440
1728
9, 322
18h
X
625-line generic
(EM)
−
−
1728
9, 322
1Ah
X
Unknown HD
RATE_SEL0 = 0
−
−
−
−
1Dh
Unknown SD
RATE_SEL0 = 1
−
−
−
−
1Eh
X
Unknown 3G
RATE_SEL0 = 0
−
−
−
−
1Fh
1
SMPTE
STANDARD
ST 296 (HD)
ACTIVE
VIDEO
AREA
1440x487/60 (2:1)
ST 125 (SD)
1440x576/50 (2:1)
ITU-R BT.656
(SD)
(Or dual link
progressive)
Notes:
1. The Line Numbers in brackets refer to version zero SMPTE ST 352 packet locations, if they are different from version 1.
2. The part may provide full or limited functionality with standards that are not included in this table. Please consult a Semtech technical
representative.
By default (at power up or after system reset), the four RASTER_STRUC_X, STD_LOCK
and INT/PROG registers are set to zero. These registers are also cleared when the
SMPTE_BYPASS pin is LOW, or the LOCKED pin is LOW.
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Note 1: The Line Numbers in brackets refer to Version zero SMPTE ST 352 packet
locations, if they are different from the Version one locations.
Note 2: 3G formats cannot be fully determined from these measurements. Their
detailed information will be derived from SMPTE ST 352 packets, which must be in the
video stream as a mandatory requirement of the SMPTE ST 424 specification, as
described below.
4.8.2 3G Format Detection
Format detection is more difficult for 3G signals, as there are two levels of signal (Level
A and Level B) and multiple mappings within each level. Timing information is not
sufficient to fully decode the video format.
For this reason SMPTE ST 352 video payload identifier packets are mandatory for all
SMPTE ST 424 serial signals.
Note: The only exception is when the SMPTE ST 425 mapping is Level B twin
SMPTE ST 292 streams, and one or both of the SMPTE ST 292 streams carries HD-SDTI
data. In this case the HD-SDTI header packets are used for payload identification.
4.8.2.1 Level A and Level B Signals:
The GS2962 uses SMPTE ST 352 packets to determine the video format. The
SMPTE ST 352 packets used for format detection will either be:
•
When the 352_INS (address 000h bit 6) bit is LOW, then if either bit 6 or 7 of address
20Ah are HIGH, the format is 3G Level B. If both are LOW, then it will look at the
information programmed at address 00Ah VIDEO_FORMAT_OUT_DS1_X. See
SMPTE ST 425 Standard for details.
•
When the bit is HIGH, the format is 3G Level A.
Extraction of ST 352 packets cannot be done in 3G Level B.
The GS2962 uses the programmed SMPTE ST 352 packets if the 352_INS register bit in
the IOPROC register is HIGH.
If there are no SMPTE ST 352 packets embedded in the input signal, and the user does
not embed SMPTE ST 352 packets from the host interface, the GS2962 assumes an input
signal of 1080p/50 or 1080p/59.94. The GS2962 uses information from the
RASTER_STRUC_X registers to select between these two frame rates.
If there are no SMPTE ST 352 packets embedded in the input signal, the GS2962 will raise
an error flag in the “NO_352_ERR” bit.
If there are SMPTE ST 352 packets present in the stream, the GS2962 reports the
extracted SMPTE ST 352 packets in the VIDEO_FORMAT_352_IN registers in the host
interface. The user can use this information, along with the RASTER_STRUC_X registers,
to determine the video format.
If there is a conflict between the numbers in the registers and the format defined in the
SMPTE ST 352 packets, the GS2962 will raise a TIMING_ERROR_352 flag via the host
interface.
Note: SMPTE ST 352 packets will not be present in an HD-SDTI input stream, and will
not be embedded in an output HD-SDTI serial stream. This is controlled by the user as
described in Section 4.8.8.1.
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By default (at power up or after system reset), the VIDEO_FORMAT_352_IN registers are
set to zero (undefined video format). These registers are also cleared when the
SMPTE_BYPASS pin is set LOW, or the LOCKED pin is LOW. The SMPTE ST 352 packet
should be received once per field for interlaced systems and once per frame for
progressive video systems. If the packet is not received for two complete video frames,
the VIDEO_FORMAT_352_IN registers are cleared to zero.
Table 4-6: SMPTE ST 352 Packet Data
Register Name
Bit
Name
15-8
VIDEO_FORMAT_IN
_DS1_4
(Byte 4)
R/W
Default
Data will be available in this register
when Video Payload Identification
Packets are detected in the data stream.
R
0
7-0
VIDEO_FORMAT_IN
_DS1_3
(Byte 3)
Data will be available in this register
when Video Payload Identification
Packets are detected in the data stream.
R
0
15-8
VIDEO_FORMAT_IN
_DS1_2
(Byte 2)
Data will be available in this register
when Video Payload Identification
Packets are detected in the data stream.
R
0
7-0
VIDEO_FORMAT_IN
_DS1_1
(Byte 1)
Data will be available in this register
when Video Payload Identification
Packets are detected in the data stream.
R
0
15-8
VIDEO_FORMAT_IN
_DS2_4
(Byte 4)
Data will be available in this register
when Video Payload Identification
Packets are detected in the data stream.
R
0
7-0
VIDEO_FORMAT_IN
_DS2_3
(Byte 3)
Data will be available in this register
when Video Payload Identification
Packets are detected in the data stream.
R
0
15-8
VIDEO_FORMAT_IN
_DS2_2
(Byte 2)
Data will be available in this register
when Video Payload Identification
Packets are detected in the data stream.
R
0
7-0
VIDEO_FORMAT_IN
_DS2_1
(Byte 1)
Data will be available in this register
when Video Payload Identification
Packets are detected in the data stream.
R
0
VIDEO_FORMAT_352_IN_WORD_2
VIDEO_FORMAT_352_IN_WORD_1
VIDEO_FORMAT_352_IN_WORD_4
VIDEO_FORMAT_352_IN_WORD_3
Description
4.8.2.2 Level B Signals:
For Level B inputs, the GS2962 does not extract the SMPTE ST 352 packets from the
parallel input. The only source of SMPTE ST 352 packets in Level B mode, to be used for
format detection and for embedding in the output data streams, is from the user
programmed registers in the host interface.
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4.8.3 ANC Data Blanking
The GS2962 can blank the video input data during the H and V blanking periods. This
function will be enabled by setting the ANC_BLANK pin LOW.
This function is only available when the device is operating in SMPTE mode
(SMPTE_BYPASS = HIGH).
In this mode, input video data in the horizontal and vertical blanking periods will be
replaced by SMPTE compliant blanking values.
The blanking function will operate only on the video input signal and will remove all
ancillary data already embedded in the input video stream.
In SD mode, SAV and EAV code words already embedded in the input video stream will
be protected and will not be blanked.
In HD and 3G modes, SAV and EAV code words, line numbers and line based CRC's
already embedded in the input video stream will be protected and will not be blanked.
The above two statements are really implementation specific, and are provided only to
ensure that the “Detect TRS” function for timing generation is supported by the device,
even when the blanking function is enabled.
From a system perspective, use of the input blanking function is not recommended
unless TRS, line number and CRC generation and insertion functions are enabled.
The active image area will not be blanked.
The input blanking function will not blank any of the ancillary data, TRS words, line
numbers, CRC's, EDH or SMPTE ST 352 payload identifiers inserted by the device itself.
4.8.4 ANC Data Checksum Calculation and Insertion
The GS2962 calculates checksums for all detected ancillary data packets presented to
the device.
ANC data checksum insertion only takes place if the IOPROC_EN/DIS pin is HIGH, the
SMPTE_BYPASS is HIGH and the ANC_CSUM_INS bit is set LOW in the IOPROC register.
Note: The device will correct any CSUM value outside the protected ranges from 000h
to 003h and from 3FCh to 3FFh. If a CSUM value in either of these ranges is presented to
the device, it will not be corrected.
4.8.5 TRS Generation and Insertion
The GS2962 is capable of generating and inserting TRS codes.
TRS word generation and insertion are performed in accordance with the timing
parameters generated by the timing circuits, which is locked to the externally provided
H:V:F or CEA-861 signals, or the TRS signals embedded in the input data stream. The
GS2962 will overwrite the TRS signals if they're already embedded. When a 3G Level A
signal is applied to the GS2962, and when the CONV_372 (bit 9 address 000h) is set LOW
(Level A to Level B conversion), TRS will be inserted according to 3G Level B format.
10-bit TRS code words are inserted at all times.
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The insertion of TRS ID words only take place if the IOPROC_EN/DIS pin is HIGH and the
SMPTE_BYPASS pin is HIGH.
In addition to this, the GS2962 requires the TRS_INS bit to be set LOW in the IOPROC
register.
If the TIM_861 pin is HIGH, then the timing circuits are locked to CEA-861 timing.
4.8.6 HD and 3G Line Number Calculation and Insertion
The GS2962 is capable of line number generation and insertion, in accordance with the
relevant HD video standard, as determined by the automatic video standard detector.
Line numbers are inserted into both the Y and C channels.
Note: Line number generation and insertion only occurs in HD and 3G modes
(RATE_SEL0 = LOW).
The insertion of line numbers only take place if the IOPROC_EN/DIS pin is HIGH and
SMPTE_BYPASS pin is HIGH.
In addition to this, the GS2962 requires the LNUM_INS bit to be set LOW in the IOPROC
register.
4.8.7 Illegal Code Re-Mapping
The GS2962 detects and corrects illegal code words within the active picture area.
All codes within the active picture (outside the horizontal and vertical blanking periods),
between the values of 3FCh and 3FFh are re-mapped to 3FBh. All codes within the active
picture area between the values of 000h and 003h are remapped to 004h.
8-bit TRS code words are re-mapped to 10-bit values.
The illegal code re-mapping will only take place if the IOPROC_EN/DIS pin is HIGH and
SMPTE_BYPASS is HIGH.
In addition to this, the GS2962 requires the ILLEGAL_REMAP bit to be set LOW in the
IOPROC register.
Note: Due to the architecture of the GS2962 serializer, illegal code words appearing in
the middle of a line that look like TRS sequences will be treated as such by the device.
For example, any sequence in the middle of a line that produces 3FFh 000h 000h
followed by another 10-bit word will be treated as a TRS, even if that following word
does not match the XYZh code words allowed by SMPTE.
To avoid this issue, any groupings of words that look like TRS sequence must be kept out
of the active picture portion of the video line or it will not be remapped.
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4.8.8 SMPTE ST 352 Payload Identifier Packet Insertion
When enabled by the 352M_INS bit in the IOPROC register, new SMPTE ST 352 payload
identifier packets are inserted into the data stream. These packets are supplied by the
user via the host interface. Setting the 352M_INS bit LOW enables this insertion.
The device will automatically calculate the checksum and generate Version One
compliant ST 352 ancillary data preambles: DID, SDID, DBN, DC.
The SMPTE ST 352 packet is inserted into the data stream according to the line number
and sample position rules defined in the 2002 standard.
For HDTV video systems the SMPTE ST 352 packet is placed in the Y channel only.
By default (at power up or after system reset), the four VIDEO_FORMAT_IN_DS1
registers and the four VIDEO_FORMAT_OUT_DS1 registers are set to zero.
4.8.8.1 3G SMPTE ST 352 Payload Identifier Packet Insertion
When enabled by the 352M_INS bit in the IOPROC register (000h), new SMPTE ST 352
payload identifier packets are inserted into the data streams. Setting this bit LOW
enables insertion.
Insertion of SMPTE ST 352 packets into each data stream is controlled by the status
format describing bit, SDTI_TDM_DS1 and SDTI_TDM_DS2 for Data Stream One and
Data Stream Two. If SDTI_TDM_DS1 (default LOW) is set HIGH by the user, the GS2962
does not insert SMPTE ST 352 packets into Data Stream One. Similarly, SMPTE ST 352
packets are inserted in Data Stream Two only if SDTI_TDM_DS2 is set LOW. This allows
the user to individually disable SMPTE ST 352 packets where the data stream is carrying
an HD-SDTI or TDM signal, which must not have SMPTE ST 352 packets embedded.
Note: The user must ensure that there is sufficient space in the horizontal blanking
interval for the insertion of the SMPTE ST 352 packets. If the FIRST_AVAIL_POSITION bit
in the host interface registers is set HIGH (by default), the SMPTE ST 352 packets are
inserted in the first available position following any existing ancillary data. If the
FIRST_AVAIL_POSITION CSR bit is set LOW, then the packets are inserted immediately
after the EAV/CRC1.
If there are pre-existing ST 352 packets, they will be overwritten if the
FIRST_AVAIL_POSITION CSR bit is HIGH. If the FIRST_AVAIL_POSITION CSR bit is
LOW, the pre-existing ST 352 packet will be overwritten only if it is contiguous to the
EAV/CRC1 sequence.
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4.8.9 Line Based CRC Generation and Insertion (HD/3G)
When operating in HD mode (RATE_SEL0 pin = LOW, RATE_SEL1 pin = LOW), the
GS2962 generates and inserts line based CRC words into both the Y and C channels of
the data stream.
When operating in 3G (RATE_SEL0 pin = LOW, RATE_SEL1 pin = HIGH) Level A mode,
the GS2962 generates and inserts line based CRC words into both Data Stream One and
Data Stream Two.
When operating in 3G (RATE_SEL0 pin = LOW, RATE_SEL1 pin = HIGH) Level B mode,
the GS2962 generates and inserts line based CRC words into both Y and C channels of
both Link A and Link B.
The line based CRC insertion only takes place if the IOPROC_EN/DIS pin is HIGH and
SMPTE_BYPASS is HIGH.
In addition to this, the GS2962 requires the CRC_INS bit to be set LOW in the IOPROC
register.
4.8.10 EDH Generation and Insertion
When operating in SD mode, the GS2962 generates and inserts EDH packets into the
data stream.
The EDH packet generation and insertion only takes place if the IOPROC_EN/DIS pin is
HIGH, SMPTE_BYPASS pin is HIGH, the RATE_SEL0 pin is HIGH and the EDH_CRC_INS
bit is set LOW in the IOPROC register.
Calculation of both Full Field (FF) and Active Picture (AP) CRCs is carried out by the
device.
EDH error flags EDH, EDA, IDH, IDA and UES for ancillary data, full field and active
picture are also inserted.
•
When the EDH_CRC_UPDATE bit of the host interface is set LOW, these flags are
sourced from the ANC_EDH_FLAG, FF_EDH_FLAG and AP_EDH_FLAG registers of
the device, where they are programmed by the application layer
•
When the EDH_CRC_UPDATE bit of the host interface is set HIGH, incoming EDH
flags are preserved and inserted in the outgoing EDH packets. In this mode the
ANC_EDH_FLAG, FF_EDH_FLAG and AP_EDH_FLAG registers contain the
incoming EDH flags, and will be read only
The GS2962 generates all of the required EDH packet data including all ancillary data
preambles: DID, DBN, DC, reserved code words and checksum.
The prepared EDH packet is inserted at the appropriate line of the video stream (in
accordance with RP165). The start pixel position of the inserted packet is based on the
SAV position of that line, such that the last byte of the EDH packet (the checksum) is
placed in the sample immediately preceding the start of the SAV TRS word.
Note 1: When the EDH_CRC_UPDATE bit of the host interface is set LOW, it is the
responsibility of the application interface to ensure that the EDH flag registers are
updated regularly (once per field).
Note 2: It is also the responsibility of the application interface to ensure that there is
sufficient space in the horizontal blanking interval for the EDH packet to be inserted.
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4.8.11 SMPTE ST 372 Conversion
When the IOPROC_EN/DIS pin is HIGH and the CONV_372 bit in the IOPROC register is
LOW, the GS2962 converts SMPTE ST 425 Level A mapping 1 (1080P 4:2:2) to Level B
SMPTE ST 372 dual link prior to serialization.
4.8.12 Processing Feature Disable
The GS2962 contains an IOPROC register. This register contains one bit for each
processing feature, allowing the user to enable/disable each process individually.
By default (at power up or after system reset), all of the IOPROC register bits are LOW,
except for the SMPTE ST 372 conversion.
To disable an individual processing feature, the application interface must set the
corresponding bit HIGH in the IOPROC register. To enable these features, the
IOPROC_EN/DIS pin must be HIGH, and the individual feature must be enabled by
setting bits LOW in the IOPROC register of the host interface.
The I/O processing functions supported by the GS2962 are shown in Table 4-7 below.
Table 4-7: IOPROC Register Bits
I/O Processing Feature
IOPROC Register Bit
TRS insertion
TRS_INS (000h Bit 0)
Y and C line number insertion
LNUM_INS (000h Bit 1)
Y and C line based CRC insertion
CRC_INS (000h Bit 2)
Ancillary data checksum correction
ANC_CSUM_INS (000h Bit 3)
EDH CRC error calculation and insertion
EDH_ CRC_INS (000h Bit 4)
Illegal word re-mapping
ILLEGAL_WORD_REMAP (000h Bit 5)
SMPTE ST 352 packet insertion
SMPTE_352M_INS (000h Bit 6)
SMPTE ST 372 conversion
CONV_372 (000h Bit 9)
Ancillary data insertion
ANC_INS (000h Bit 11)
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4.9 Serial Digital Output
The GS2962 has a single, low-impedance current mode differential output driver,
capable of driving at least 800mV into a 75Ω single-ended load.
The output signal amplitude, or swing, will be user-configurable using an external
resistor on the RSET pin.
The serial digital output data rate supports SMPTE ST 424, SMPTE ST 292 and
SMPTE ST 259 operation. This is summarized in Table 4-8 below.
Table 4-8: Serial Digital Output - Serial Output Data Rate
Parameter
Symbol
Serial Output Data Rate
BRSDO
Conditions
Min
Typ
Max
Units
SMPTE ST 424 signal
−
2.97, 2.97/1.001
−
Gb/s
SMPTE ST 292 signal
−
1.485, 1.485/1.001
−
Gb/s
SMPTE ST 259 signal
−
270
−
Mb/s
The SDO and SDO pins of the device provide the serial digital output.
Compliance with all requirements defined in Section 4.9.1 through Section 4.9.4 is
guaranteed when measured across a 75Ω terminated load at the output of 1m of Belden
1694A cable, including the effects of the Semtech recommended ORL matching
network, BNC and coaxial cable connection, except where otherwise stated.
Figure 4-20 illustrates this requirement, which is in accordance with the measurement
methodology defined in SMPTE ST 424, SMPTE ST 292 and SMPTE ST 259.
Measuring Device
DUT
GS2962
ORL
Matching
Network
BNC
1m Belden 1694A 75Ω
Coaxial Cable
BNC
75Ω
Resistive
Load
Figure 4-20: ORL Matching Network, BNC and Coaxial Cable Connection
4.9.1 Output Signal Interface Levels
The Serial Digital Output signals (SDO and SDO pins), of the device meet the amplitude
requirements as defined in SMPTE ST 424 for an unbalanced generator (single-ended).
The signal amplitude is controlled to better than +/-7% of the nominal level defined in
SMPTE ST 424, when an external 750Ω 1% resistor is connected between the RSET pin
of the device and VCC.
The output signal amplitude can be reduced to less than 1/10th of the nominal
amplitude, defined above, by increasing the value of the resistor connected between the
RSET pin of the device and VCC.
These requirements are met across all ambient temperature and power supply
operating conditions described in the Electrical Characteristics on page 16.
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The output amplitude of the GS2962 can be adjusted by changing the value of the RSET
resistor as shown in Table 4-9. For a 800mVpp output a value of 750Ω is required.
A ±1% SMT resistor should be used.
The RSET resistor is part of the high speed output circuit of the GS2962. The resistor
should be placed as close as possible to the RSET pin. In addition, an anti-pad should be
used underneath the resistor.
Table 4-9: RSET Resistor Value vs. Output Swing
RSET Resistor Values (Ω)
Output Swing (mVpp)
995
608
824
734
750
800
680
884
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4.9.2 Overshoot/Undershoot
The serial digital output signal overshoot and undershoot is controlled to be less that 7%
of the output signal amplitude, when operating as an unbalanced generator
(single-ended).
This requirement is met for nominal signal amplitudes as defined by SMPTE ST 292.
This requirement is met regardless of the output slew rate setting of the device.
This requirement is met across all ambient temperature and power supply operating
conditions described in the Electrical Characteristics on page 16.
This requirement is summarized in Table 4-10:
Table 4-10: Serial Digital Output - Overshoot/Undershoot
Parameter
Symbol
Conditions
Min
Typ
Max
Units
−
−
−
0
7
%
Serial output overshoot /undershoot
4.9.3 Slew Rate Selection
The GS2962 supports two user-selectable output slew rates.
Control of the slew rate is determined by the setting of the RATE_SEL0 input pin.
When this pin is set HIGH, the output slew rate matches the requirements as defined by
the SMPTE ST 259 standard.
When this pin is set LOW, the output slew rate is better than the requirements as defined
by the SMPTE ST 424 standard.
These requirements is met across all ambient temperature and power supply operating
conditions described in the Electrical Characteristics on page 16.
This requirement is summarized in Table 4-11:
Table 4-11: Serial Digital Output - Rise/Fall Time
Parameter
Serial Output Rise/Fall Time
20% ~ 80%
Symbol
SDOTR
Conditions
Min
Typ
Max
Units
SMPTE ST 292/ST 424
signal
−
−
135
ps
SMPTE ST 259 signal
400
−
800
ps
4.9.4 Serial Digital Output Mute
When the SDO_EN/DIS pin is LOW, the serial digital output signals of the device become
high-impedance, reducing system power.
The serial digital output is also placed in the high-impedance state when the LOCKED
pin is LOW, or when the STANDBY pin is HIGH.
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4.10 Serial Clock PLL
An internal VCO provides the transmission clock rates for the GS2962.
The power supply to the VCO is provided to the VCO_VDD/VCO_GND pins of the
device.
This VCO is locked to the input PCLK via an on-chip PLL and Charge Pump.
Internal division ratios for the PCLK are determined by the setting of the RATE_SEL0 pin,
the RATE_SEL1 pin and the 20BIT/10BIT pin as shown in Table 4-12:
Table 4-12: PCLK and Serial Digital Clock Rates
External Pin Setting
Supplied PCLK
Rate
Serial Digital
Output Rate
RATE_SEL0
RATE_SEL1
20BIT/10BIT
LOW
HIGH
HIGH
148.5 or
148.5/1.001MHz
2.97 or
2.97/1.001 Gb/s
LOW
HIGH
LOW
148.5 or
148.5/1.001MHz
(DDR)
2.97 or
2.97/1.001 Gb/s
LOW
LOW
HIGH
74.25 or
74.25/1.001MHz
1.485 or
1.485/1.001Gb/s
LOW
LOW
LOW
148.5 or
148.5/1.001MHz
1.485 or
1.485/1.001Gb/s
HIGH
X
HIGH
13.5MHz
270Mb/s
HIGH
LOW
LOW
27MHz
270Mb/s
As well as generating the serial digital output clock signals, the PLL is also responsible
for generating all internal clock signals required by the device.
4.10.1 PLL Bandwidth
Table 4-13 shows the GS2962 PLL loop bandwidth variations. PLL bandwidth is a
function of the external loop filter resistor and the charge pump current. We
recommend using a 200Ω loop filter resistor, however, this value can be varied from
100Ω to 380Ω, depending on application. Values other than 200Ω are not guaranteed.
As the resistor is changed, the bandwidth will scale proportionately (for example, a
change from a 200Ω to 300Ω resistor will cause a 50% increase in bandwidth). The
charge pump current is preset to 100μA and should not be changed. The external loop
filter capacitor does not affect the PLL loop bandwidth. The external loop filter capacitor
affects PLL loop settling time, phase margin and noise. It is selectable from 1μF to 33μF.
However, it should be kept at 10μF for optimal performance. A smaller capacitor results
in shorter lock time but less stability. A larger capacitor results in longer lock time but
more stability. Narrower loop bandwidths require a larger capacitor to be stable. In other
words, a small loop filter resistor requires a larger loop capacitor.
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Table 4-13: GS2962 PLL Bandwidth
Mode
PCLK Frequency
(MHz)
Filter Resistor
(Ω)
Charge Pump
Current (μA)
Bandwidth
(kHz)
SD
13.50
200
100
4.78
SD
27.00
200
100
9.57
HD
74.25
200
100
26.32
HD
148.50
200
100
52.63
3G
148.50
200
100
52.63
4.10.2 Lock Detect
The Lock Detect block controls the serial digital output signal and indicates to the
application layer the lock status of the device.
The LOCKED output pin is provided to indicate the device operating status.
The LOCKED output signal is set HIGH by the lock detect block under the following
conditions (see Table 4-14):
Table 4-14: GS2962 Lock Detect Indication
RESET
PLL Lock
SMPTE_BYPASS
DVB_ASI
RATE_SEL0
HIGH
HIGH
HIGH
LOW
X
HIGH
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
LOW
LOW
X
Any other combination of signal states not included in the above table results in the
LOCKED pin being LOW.
Note: When the LOCKED pin is LOW, the serial digital output is in the muted state.
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4.11 GSPI Host Interface
Note: When using more than one Semtech serializer or deserializer (SerDes) in the same
design, carefully read this section to see how the GSPI ports of multiple ICs should be
connected to each other. Unlike some previous devices, the SDOUT pin of these SerDes
ICs is a non-clocked, loop-through of SDIN (allowing for multiple devices to be
connected to the GSPI chain). The SDOUT pins of multiple SerDes ICs should not be
bussed together, as was the case with some older generations of SerDes ICs.
The GSPI, or Gennum Serial Peripheral Interface, is a 4-wire interface provided to allow
the application layer to access additional status information through configuration
registers in the GS2962.
The GSPI comprises a Serial Data Input signal (SDIN), Serial Data Output signal (SDOUT),
an active low Chip Select (CS) and a Burst Clock (SCLK).
Because these pins can be shared with the JTAG interface port for compatibility with the
GS1582, an additional control signal pin JTAG/HOST is provided.
When JTAG/HOST is LOW, the GSPI interface is enabled. When JTAG/HOST is HIGH, the
JTAG interface is enabled.
When operating in GSPI mode, the SCLK, SDIN, and CS signals are provided by the
application interface. The SDOUT pin is a non-clocked loop-through of SDIN, and may
be connected to the SDIN of another device, allowing multiple devices to be connected
to the GSPI chain. The interface is illustrated in Figure 4-21 below.
Application Host
GS2962
SCLK
CS1
SDOUT
SCLK
CS
SDIN
SDOUT
GS2962
SCLK
CS2
CS
SDIN
SDOUT
SDIN
Figure 4-21: GSPI Application Interface Connection
All read or write access to the GS2962 is initiated and terminated by the application host
processor. Each access always begins with a Command/Address Word followed by a
data read to or written from the GS2962.
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4.11.1 Command Word Description
The Command Word consists of a 16-bit word transmitted MSB first and contains a
read/write bit, an Auto-Increment bit and a 12-bit address. Figure 4-22 shows the
command word format and bit configurations.
Command Words are clocked into the GS2962 on the rising edge of the Serial Clock
SCLK, which operates in a burst fashion.
When the Auto-Increment bit is set LOW, each Command Word must be followed by
only one Data Word to ensure proper operation. If the Auto-Increment bit is set HIGH,
the following Data Word will be written into the address specified in the Command
Word, and subsequent data words will be written into incremental addresses from the
previous Data Word. This facilitates multiple address writes without sending a
Command Word for each Data Word.
MSB
R/W
LSB
RSV
RSV
AutoInc
A11
A9
A10
A8
A7
A6
A5
A4
A3
A2
A1
A0
Figure 4-22: Command Word Format
4.11.2 Data Read or Write Access
Serial data is transmitted or received MSB first synchronous with the rising edge of the
Serial Clock, SCLK. The Chip Select (CS) signal must be active LOW a minimum of 1.5ns
(t0 in Figure 4-24) before the first clock edge to ensure proper operation.
During a Read sequence (Command Word R/W bit set HIGH), a wait state of 148ns (4 x
1/fPCLK, t5 in Figure 4-24) is required between writing the Command Word and reading
the following Data Word. The read bits are clocked out on the negative edges of SCLK.
Note 1: Where several devices are connected to the GSPI chain, only one CS_TMS may
be asserted during a read sequence.
During a Write sequence (Command Word R/W bit set LOW), a wait state of 37ns (1 x
1/fPCLK, t4 in Figure 4-24) is required between the Command Word and the following
Data Word. This wait state must also be maintained between successive Command
Word/Data Word write sequences. When Auto-increment mode is selected (AutoInc =
1), the wait state must be maintained between successive Data Words after the initial
Command Word/Data Word sequence.
During the write sequence, all command and following Data Words input at the SDIN
pin are output at the SDOUT pin as is.
When several devices are connected to the GSPI chain, data can be written
simultaneously to all the devices which have CS set LOW.
Note 2: If the application interface performs a Read or Write access after power-up,
prior to the application of a valid serial video input signal, the SCLK frequency must not
exceed 10MHz.
MSB
D15
LSB
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4-23: Data Word Format
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4.11.3 GSPI Timing
Write and Read Mode timing for the GSPI interface is as shown in the following
diagrams:
t
t
0
1
t
t
4
7
SCLK_TCK
t
t
3
t
2
8
CS_TMS
SDIN_TDI
R/W
RSV
RSV
Auto
_Inc
A11
A10
SDOUT_TDO
R/W
RSV
RSV
Auto
_Inc
A11
A10
A9
A9
A8
A7
A6
A8
A7
A5
A6
A4
A3
A2
A1
A3
A2
A1
A4
A5
A0
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D5
D4
D3
D2
D1
D0
D4
D3
D2
D1
D0
Figure 4-24: Write Mode
t
5
SCLK_TCK
t
CS_TMS
SDIN_TDI
R/W
RSV
RSV
Auto
_Inc
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SDOUT_TDO
R/W
RSV
RSV
Auto
_Inc
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
6
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4-25: Read Mode
SDIN_TDI to SDOUT_TDO combinational path for daisy chain connection of multiple GS2962 devices.
T DELAY
SDIN_TDI
data_0
SDOUT_TDO
data_0
Figure 4-26: GSPI Time Delay
Table 4-15: GSPI Time Delay
Parameter
Symbol
Delay time
tDELAY
Delay time
tDELAY
GS2962 3G/HD/SD-SDI Serializer with Complete
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Final Data Sheet Rev. 8
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Conditions
Min
Typ
Max
Units
50% levels; +1.8V operation
−
−
10.5
ns
50% levels; +3.3V operation
−
−
8.7
ns
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Table 4-16: GSPI AC Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Units
CS low before SCLK rising
edge
t0
1.5
−
−
ns
SCLK period
t1
12.5
−
−
ns
SCLK duty cycle
t2
40
50
60
%
Input data setup time
t3
1.5
−
−
ns
−
−
−
−
ns
−
−
ns
−
−
ns
−
−
ns
Time between end of
Command Word (or data in
Auto-Increment mode) and
the first SCLK of the
following Data Word – write
cycle.
Time between end of
Command Word (or data in
Auto-Increment mode) and
the first SCLK of the
following Data Word – read
cycle.
Output hold time (15pF load)
CS HIGH after last SCLK
falling edge
Input data hold time
PCLK
(MHz)
ns
unlocked
445
13.5
74.2
27.0
37.1
74.25
13.5
148.5
6.7
PCLK
(MHz)
ns
unlocked
1187
13.5
297
27.0
148.5
74.25
53.9
148.5
27
t4
50% levels; +3.3V or +1.8V
operation
t5
t6
1.5
PCLK
(MHz)
ns
unlocked
445
74.2
74.2
37.10
37.1
74.25
13.5
148.5
6.7
t7
t8
1.5
ns
Note: If the application interface performs a Read or Write access after power-up, prior to the application of a valid serial video input
signal, the SCLK frequency must not exceed 10MHz.
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4.12 Host Interface Register Maps
Table 4-17: Configuration and Status Registers
Address
Register Name
Bit Name
Bit
Description
RSVD
15
Reserved.
DELAY_LINE_ENABLE
14
HIGH - enables the delay line
delay.
RSVD
13
Reserved.
12
HIGH - preserve incoming EDH
flags and insert into outgoing
EDH packets.
LOW - embed flags from 003 in
EDH packet.
EDH_CRC_UPDATE
000h
HIGH - disable ancillary data
insertion.
R/W
Default
R
0
R/W
0
R
0
R/W
0
R
0
ANC_INS
11
RSVD
10
Reserved.
R/W
0
CONV_372
9
HIGH - disable Level A-B
conversion.
LOW - enable Level A-B
conversion.
R/W
1
H_CONFIG
8
LOW - Active Picture timing
HIGH - SMPTE H timing
R/W
0
RSVD
7
Reserved.
R/W
0
SMPTE_352M_INS
6
HIGH - disables insertion of
SMPTE ST 352 packets.
R/W
0
ILLEGAL_WORD_REMAP
5
HIGH - disables illegal word
remapping.
R/W
0
EDH_CRC_INS
4
HIGH - disables EDH CRC error
correction and insertion.
R/W
0
ANC_CSUM_INS
3
HIGH - disables insertion of
ancillary data checksums.
R/W
0
CRC_INS
2
HIGH - disables insertion of HD/3G
CRC words.
R/W
0
LNUM_INS
1
HIGH - disables insertion of HD/3G
line numbers.
R/W
0
TRS_INS
0
HIGH - disables insertion of TRS
words.
R/W
0
IOPROC
LOW - enable ancillary data
insertion.
Chooses H configuration;
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Table 4-17: Configuration and Status Registers (Continued)
Address
Register Name
Bit Name
Bit
Description
RSVD
15-7
Reserved.
R/W
Default
R
0
R
0
R
0
R
0
TRS protection error.
001h
TRS_PERR
6
Y1_EDH_CS_ERR
5
LOW - No errors in TRS.
HIGH - Errors in TRS.
Same as CS_ERR but only updates
its state when packet being
inspected is an EDH packet.
HIGH indicates that a checksum
error is detected. It is updated
every time a CS word is present on
the output.
Y1_CS_ERR
4
FORMAT_ERR
3
HIGH indicates standard is not
recognized for 861D conversion.
R
0
TIMING_ERR
2
HIGH indicates that the RASTER
measurements do not line up with
the extracted ST 352 packet
information.
R
0
NO_352M_ERR
1
HIGH indicates no ST 352 packet
embedded in incoming video.
R
0
LOCK_ERR
0
HIGH indicates PLL lock error
indication.
R
0
ERROR_STAT
GS2962 3G/HD/SD-SDI Serializer with Complete
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Note: This bit will not be set for
CSUM values in the protected
ranges (from 000h to 003h and
from 3FCh to 3FFh).
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Table 4-17: Configuration and Status Registers (Continued)
Address
002h
Register Name
EDH_FLAG_EXT
Bit Name
Bit
Description
R/W
Default
RSVD
15
Reserved.
R
0
ANC_UES_EXT
14
Ancillary data - unknown error
status flag.
R
0
ANC_IDA_EXT
13
Ancillary data - internal error
detected already flag.
R
0
ANC_IDH_EXT
12
Ancillary data - internal error
detected here flag.
R
0
ANC_EDA_EXT
11
Ancillary data - error detected
already flag.
R
0
ANC_EDH_EXT
10
Ancillary data - error detected
here flag.
R
0
FF_UES_EXT
9
EDH Full Field - unknown error
status flag.
R
0
FF_IDA_EXT
8
EDH Full Field - internal error
detected already flag.
R
0
FF_IDH_EXT
7
EDH Full Field - internal error
detected here flag.
R
0
FF_EDA_EXT
6
EDH Full Field - error detected
already flag.
R
0
FF_EDH_EXT
5
EDH Full Field - error detected
here flag.
R
0
AP_UES_EXT
4
EDH Active Picture - unknown
error status flag.
R
0
AP_IDA_EXT
3
EDH Active Picture - internal error
detected already flag.
R
0
AP_IDH_EXT
2
EDH Active Picture - internal error
detected here flag.
R
0
AP_EDA_EXT
1
EDH Active Picture - error
detected already flag.
R
0
AP_EDH_EXT
0
EDH Active Picture - error
detected here flag.
R
0
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Table 4-17: Configuration and Status Registers (Continued)
Address
003h
Register Name
EDH_FLAG_PGM
Bit Name
Bit
Description
R/W
Default
RSVD
15
Reserved.
R
0
ANC_UES_PGM
14
Ancillary data - unknown error
status flag.
R
0
ANC_IDA_PGM
13
Ancillary data - internal error
detected already flag.
R/W
0
ANC_IDH_PGM
12
Ancillary data - internal error
detected here flag.
R/W
0
ANC_EDA_PGM
11
Ancillary data - error detected
already flag.
R/W
0
ANC_EDH_PGM
10
Ancillary data - error detected
here flag.
R/W
0
FF_UES_PGM
9
EDH Full Field - unknown error
status flag.
R/W
0
FF_IDA_PGM
8
EDH Full Field - internal error
detected already flag.
R/W
0
FF_IDH_PGM
7
EDH Full Field - internal error
detected here flag.
R/W
0
FF_EDA_PGM
6
EDH Full Field - error detected
already flag.
R/W
0
FF_EDH_PGM
5
EDH Full Field - error detected
here flag.
R/W
0
AP_UES_PGM
4
EDH Active Picture - unknown
error status flag.
R/W
0
AP_IDA_PGM
3
EDH Active Picture - internal error
detected already flag.
R/W
0
AP_IDH_PGM
2
EDH Active Picture - internal error
detected here flag.
R/W
0
AP_EDA_PGM
1
EDH Active Picture - error
detected already flag.
R/W
0
AP_EDH_PGM
0
EDH Active Picture - error
detected here flag.
R/W
0
Reserved.
R
0
9-5
Detected video standard.
R
0
INT_PROGB
4
HIGH - interlaced signal
LOW - progressive signal
R
0
CONV_372_LOCKED
3
Convert 372 lock indication. Active
HIGH.
R
0
STD_LOCK
2
Standard lock indication. Active
HIGH.
R
0
V_LOCK
1
Vertical lock indication. Active
HIGH.
R
0
H_LOCK
0
Horizontal lock indication. Active
HIGH.
R
0
RSVD
VD_STD
004h
15-10
DATA_FORMAT
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Table 4-17: Configuration and Status Registers (Continued)
Address
Register Name
005h
RSVD
006h
007h
VSD_FORCE
EDH_STATUS
Bit Name
Bit
Description
RSVD
15-0
RSVD
15-6
VSD_FORCE
5
FIRST_AVAIL_
POSITION
009h
RSVD
00Ah
VIDEO_FORMAT
_352_OUT_
WORD_1
00Bh
00Ch
00Dh
00Eh
00Fh
010h
VIDEO_FORMAT
_352_OUT_
WORD_2
VIDEO_FORMAT
_352_OUT_
WORD_3
VIDEO_FORMAT
_352_OUT_
WORD_4
VIDEO_FORMAT
_352_IN_
WORD_1
VIDEO_FORMAT
_352_IN_
WORD_2
VIDEO_FORMAT
_352_IN_
WORD_3
Default
Reserved.
R
0
Reserved.
R
0
Use the CSR register STD value
rather than the flywheels STD
value. Active HIGH.
R/W
0
R/W
0
VID_STD_FORCE
4-0
Force VID STD CSR.
RSVD
15-2
Reserved.
R
0
FF_CRC_V
1
Full Field extracted V bit.
R
0
AP_CRC_V
0
Active Picture extracted V bit.
R
0
Reserved.
R
0
R/W
1
R
0
RSVD
008h
R/W
15-1
FIRST_AVAIL_POSITION
0
HIGH - ST 352 insertion occurs on
first available ANC space.
LOW - insert ST 352 packets right
after EAV/CRC1.
RSVD
15-0
Reserved.
VIDEO_FORMAT_OUT_DS1_
2
15-8
SMPTE ST 352 DS1 embedded
packet - byte 2.
R/W
0
VIDEO_FORMAT_OUT_DS1_
1
7-0
SMPTE ST 352 DS1 embedded
packet - byte 1.
R/W
0
VIDEO_FORMAT_OUT_DS1_
4
15-8
SMPTE ST 352 DS1 embedded
packet - byte 4.
R/W
0
VIDEO_FORMAT_OUT_DS1_
3
7-0
SMPTE ST 352 DS1 embedded
packet - byte 3.
R/W
0
VIDEO_FORMAT_OUT_DS2_
2
15-8
SMPTE ST 352 DS2 embedded
packet - byte 2.
R/W
0
VIDEO_FORMAT_OUT_DS2_
1
7-0
SMPTE ST 352 DS2 embedded
packet - byte 1.
R/W
0
VIDEO_FORMAT_OUT_DS2_
4
15-8
SMPTE ST 352 DS2 embedded
packet - byte 4.
R/W
0
VIDEO_FORMAT_OUT_DS2_
3
7-0
SMPTE ST 352 DS2 embedded
packet - byte 3.
R/W
0
VIDEO_FORMAT_IN_DS1_2
15-8
SMPTE ST 352 DS1 extracted
packet - byte 2.
R
0
VIDEO_FORMAT_IN_DS1_1
7-0
SMPTE ST 352 DS1 extracted
packet - byte 1.
R
0
VIDEO_FORMAT_IN_DS1_4
15-8
SMPTE ST 352 DS1 extracted
packet - byte 4.
R
0
VIDEO_FORMAT_IN_DS1_3
7-0
SMPTE ST 352 DS1 extracted
packet - byte 3.
R
0
VIDEO_FORMAT_IN_DS2_2
15-8
SMPTE ST 352 DS2 extracted
packet - byte 2.
R
0
VIDEO_FORMAT_IN_DS2_1
7-0
SMPTE ST 352 DS2 extracted
packet - byte 1.
R
0
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70 of 81
Table 4-17: Configuration and Status Registers (Continued)
Address
Register Name
011h
VIDEO_FORMAT
_352_IN_
WORD_4
012h
RASTER_STRUC_
1
013h
RASTER_STRUC_
2
014h
RASTER_STRUC_
3
015h
RASTER_STRUC_
4
016h 023h
RSVD
Bit Name
Bit
Description
VIDEO_FORMAT_IN_DS2_4
15-8
VIDEO_FORMAT_IN_DS2_3
7-0
Default
SMPTE ST 352 DS2 extracted
packet - byte 4.
R
0
SMPTE ST 352 DS2 extracted
packet - byte 3.
R
0
RSVD
15-11
Reserved.
R
0
LINES_PER_FRAME
10-0
Total lines per frame.
R
0
RSVD
15-14
Reserved.
R
0
WORDS_PER_LINE
13-0
Total words per line.
R
0
RSVD
15-13
Reserved.
R
0
ACTIVE_WORDS_PER
_LINE
12-0
Words per active line.
R
0
RSVD
15-11
Reserved.
R
0
ACTIVE_LINES_PER_FIELD
10-0
Active lines per frame.
R
0
RSVD
−
Reserved.
R
0
RSVD
15-2
Reserved.
R
0
R
0
HIGH - one of the addresses from
040h to 13Fh was read and
written to at the same time.
R
0
Reserved.
R
0
R/W
0
PACKET_MISSED
024h
R/W
1
FIRST_LINE_
NUMBER_
STATUS
ANC data packet could not be
inserted in its entirety.
HIGH - ANC packet cannot be
inserted in it’s entirety.
Same RAM address was read and
written to at the same time.
RW_CONFLICT
0
RSVD
15-12
ANC data insertion mode.
025h
FIRST_LINE_
NUMBER
ANC_INS_MODE
11
10-0
First line number to insert ANC
packet on.
R/W
0
FIRST_LINE_NUMBER_ANC_T
YPE
15
ANC region to insert packet in
HIGH - VANC,
LOW - HANC.
R/W
0
FIRST_LINE_NUMBER
_STREAM_TYPE
14
Stream to insert packet in HIGH - C
stream,
LOW - Y stream.
R/W
0
R
0
R/W
0
R
0
R/W
0
FIRST_LINE_NUMBER
026h
FIRST_LINE_
NUMBER_OF_
WORDS
RSVD
13-10
FIRST_LINE_NUMBER
_OF_WORDS
027h
SECOND_LINE_
NUMBER
HIGH - Concatenate
LOW - Separate
9-0
Reserved.
Total number of words in ANC
packet to be inserted in first line.
RSVD
15-11
Reserved.
SECOND_LINE_NUMBER
10-0
Second line number to insert ANC
packet on in Separate Line mode.
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
www.semtech.com
71 of 81
Table 4-17: Configuration and Status Registers (Continued)
Address
028h
Register Name
SECOND_LINE_
NUMBER_OF_
WORDS
Bit Name
Bit
Description
R/W
Default
SECOND_LINE_NUMBER
_ANC_TYPE
15
ANC region to insert packet in
HIGH - VANC,
LOW - HANC.
R/W
0
SECOND_LINE_NUMBER
_STREAM_TYPE
14
Stream to insert packet in HIGH - C
stream,
LOW - Y stream.
R/W
0
R
0
R/W
0
R
0
RSVD
13-10
SECOND_LINE_NUMBER
_OF_WORDS
029h
02Ah
THIRD_LINE_
NUMBER
THIRD_LINE_
NUMBER_OF_
WORDS
15-11
Reserved.
THIRD_LINE_NUMBER
10-0
Third line number to insert ANC
packet on in Separate Line mode.
R/W
0
THIRD_LINE_NUMBER
_ANC_TYPE
15
ANC region to insert packet in.
HIGH - VANC,
LOW - HANC.
R/W
0
THIRD_LINE_NUMBER
_STREAM_TYPE
14
R/W
0
R
0
R/W
0
R
0
Stream to insert packet in.
13-10
THIRD_LINE_NUMBER
_OF_WORDS
02Bh
02Ch
FOURTH_LINE_
NUMBER_OF_
WORDS
Total number of words in ANC
packet to be inserted in second
line.
RSVD
RSVD
FOURTH_LINE_
NUMBER
9-0
Reserved.
9-0
HIGH - C stream,
LOW - Y stream.
Reserved.
Total number of words in ANC
packet to be inserted in third line.
RSVD
15-11
Reserved.
FOURTH_LINE_NUMBER
10-0
Fourth line number to insert ANC
packet on in Seperate Line mode.
R/W
0
FOURTH_LINE_NUMBER
_ANC_TYPE
15
ANC region to insert packet in
HIGH - VANC,
LOW - HANC.
R/W
0
FOURTH_LINE_NUMBER
_STREAM_TYPE
14
Stream to insert packet in 1-C
stream, 0-Y stream.
R/W
0
R
0
R/W
0
RSVD
13-10
FOURTH_LINE_NUMBER
_OF_WORDS
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
9-0
Reserved.
Total number of words in ANC
packet to be inserted in fourth
line.
www.semtech.com
72 of 81
Table 4-17: Configuration and Status Registers (Continued)
Address
Register Name
Bit Name
Bit
Description
RSVD
15-5
Reserved.
EDH_LINE_CHECK_EN
STREAM_TYPE1_LINE_4
02Dh
STREAM_TYPE_
1
STREAM_TYPE1_LINE_3
STREAM_TYPE1_LINE_2
STREAM_TYPE1_LINE_1
02Eh 03Fh
040h 07Fh
RSVD
ANC_PACKET
_BANK_1
RSVD
R/W
Default
R
0
4
HIGH - ANC block will not insert
data into the EDH region of the
HANC space.
LOW - ANC block will insert data
into the EDH region.
R/W
1
3
HIGH - data for the fourth line in
separate mode is inserted into
Data Stream Two.
LOW - Data Stream One.
Parameter only applicable for 3G.
R/W
0
2
HIGH - data for the third line in
separate mode is inserted into
Data Stream Two.
LOW - Data Stream One.
Parameter only applicable for 3G.
R/W
0
1
HIGH - data for the second line in
separate mode is inserted into
Data Stream Two.
LOW - Data Stream One.
Parameter only applicable for 3G.
R/W
0
0
HIGH - data for the first line in
separate mode is inserted into
Data Stream Two.
LOW - Data Stream One.
Parameter only applicable for 3G.
R/W
0
R
0
−
−
−
−
−
−
−
−
R
0
15-0
Reserved.
First bank of user-defined 8-bit
ancillary data.
ANC_PACKET_BANK
15-0
Bit 15 - 8: 2nd byte (MSB to LSB)
Bit 7 - 0: 1st byte (MSB to LSB)
See 4.7 ANC Data Insertion.
080h 0BFh
ANC_PACKET
_BANK_2
Second bank of user-defined 8-bit
ancillary data.
ANC_PACKET_BANK
15-0
Bit 15 - 8: 2nd byte (MSB to LSB)
Bit 7 - 0: 1st byte (MSB to LSB)
See 4.7 ANC Data Insertion.
0C0h 0FFh
ANC_PACKET
_BANK_3
Third bank of user-defined 8-bit
ancillary data.
ANC_PACKET_BANK
15-0
Bit 15 - 8: 2nd byte (MSB to LSB)
Bit 7 - 0: 1st byte (MSB to LSB)
See 4.7 ANC Data Insertion.
100h 13Fh
ANC_PACKET
_BANK_4
Fourth bank of user-defined 8-bit
ancillary data.
ANC_PACKET_BANK
15-0
Bit 15 - 8: 2nd byte (MSB to LSB)
Bit 7 - 0: 1st byte (MSB to LSB)
See 4.7 ANC Data Insertion.
140h 209h
RSVD
RSVD
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
−
Reserved.
www.semtech.com
73 of 81
Table 4-17: Configuration and Status Registers (Continued)
Address
20Ah
20Bh 20Ch
20Dh
Register Name
Bit Name
Bit
Description
RSVD
15-8
Reserved.
LEVELB_
INDICATION
Default
R
0
SDTI_TDM_DS2
7
HIGH indicates an SDTI type signal
on input for Data Stream Two.
R/W
0
SDTI_TDM_DS1
6
HIGH indicates an SDTI type signal
on input for Data Stream One.
R/W
0
SDTI_TDM
RSVD
R/W
RSVD
5-0
Reserved.
R
0
RSVD
15-0
Reserved.
R
0
RSVD
15-9
Reserved.
R
0
HIGH indicates level B detected.
Only relevant for 3G input
streams.
R
0
LEVEL_B
8
RSVD
7-0
Reserved.
R
0
RSVD
15-4
Reserved.
R/W
0
R/W
0
Drive strength value for LOCKED
pin.
LOCKED_DS
20Eh
3-2
DRIVE_
STRENGTH
00: 4mA;
01: 6mA;
10: 8mA(+1.8V), 10mA(+3.3V);
11: 10mA(+1.8V), 12mA(+3.3V)
Drive strength value for
SDOUT_TDO pin.
20Fh
RSVD
SDOUT_TDO_DS
1-0
00: 4mA;
01: 6mA;
10: 8mA(+1.8V), 10mA(+3.3V);
11: 10mA(+1.8V), 12mA(+3.3V)
R/W
2
RSVD
15-0
Reserved.
R/W
0
R/W
0
Drive strength value for TDO pin.
210h
211h 232h
DRIVE_
STRENGTH2
RSVD
00: 4mA;
01: 6mA;
10: 8mA(+1.8V), 10mA(+3.3V);
11: 10mA(+1.8V), 12mA(+3.3V)
TDO_DS
15-14
RSVD
13-0
Reserved.
R/W
0
RSVD
15-0
Reserved.
R
0
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
www.semtech.com
74 of 81
4.13 JTAG ID Codeword
The Platform ID for the 297X family is 0Fh.
The part number field of the JTAG ID codeword for the GS2962 is set to 0F00h.
4.14 JTAG Test Operation
When the JTAG/HOST pin is HIGH, the GSPI host interface port is configured for JTAG
test operation.
In this mode the SCLK, SDIN, SDOUT and CS become TCK, TDI, TDO and TMS. In
addition, the TRST pin becomes active.
Boundary scan testing using the JTAG interface is enabled in this mode. When the
JTAG/HOST pin is LOW, the dedicated JTAG interface is used. In this mode the TCK, TDI,
TDO and TMS pins are active. This is the recommended mode for new designs.
4.15 Device Power-Up
Because the GS2962 is designed to operate in a multi-voltage environment, any
power-up sequence is allowed. The Charge Pump, Phase Detector, Core Logic, Serial
Digital Output and I/O Buffers can all be powered up in any order.
4.16 Device Reset
Note: At power-up, the device must be reset to operate correctly.
In order to initialize all internal operating conditions to their default states, hold the
RESET signal LOW for a minimum of treset = 1ms after all power supplies are stable. There
are no requirements for power supply sequencing.
When held in reset, all device outputs will be driven to a high-impedance state.
Nominal Level
95% of Nominal Level
Supply Voltage
t
RESET
t
reset
Reset
reset
Reset
Figure 4-27: Reset Pulse
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
www.semtech.com
75 of 81
5. Application Reference Design
5.1 Typical Application Circuit
Power Filtering
Power Decoupling
CD_VDD
+3.3V
+1.2V
+1.2V_A
0Ω
10nF
+1.2V
0Ω
1µF
1µF
10nF
10nF
1µF
1µF
10nF
10nF
10nF
10nF
10nF
0Ω
GND_A
GND_A
+3.3V_A
IO_VDD
IO_VDD
0Ω
10nF
1µF
1µF
1µF
10nF
10nF
10nF
GND_A
Place close to GS2962
+1.2V_A
+1.2V_A
CD_VDD
+3.3V_A
105Ω
GND_A
GND_A
Video Data, Clock & Timing Input
A3
F/DE
C4
V/VSYNC
A4
H/HSYNC
PCLK
PCLK
DNP
B4
A10
E10
VBG
F/DE
STANDBY
TIM_861
SMPTE_BYPASS
DVB_ASI
RATE_SEL0
RATE_SEL1
IOPROC_EN/DIS
20bit/10bit
SDO_EN/DIS
DETECT_TRS
ANC_BLANK
V/VSYNC
H/HSYNC
PCLK
DNP
DIN[19:0]
B3
A2
A1
B2
B1
C2
C1
C3
D1
D2
F1
F2
H1
H2
J1
J2
K1
K2
J3
K3
A_VDD
CORE_VDD
CORE_VDD
CORE_VDD
CORE_VDD
A6
B6
LF
DIN 19
DIN 18
DIN 17
DIN 16
DIN 15
DIN 14
DIN 13
DIN 12
DIN 11
DIN 10
DIN 9
DIN 8
DIN 7
DIN 6
DIN 5
DIN 4
DIN 3
DIN 2
DIN 1
DIN 0
CORE_GND
CORE_GND
CORE_GND
RSV
RSV
RSV
RSV
D5
F7
F4
D6
D7
D8
A9
TCK
TDO
TMS
J8
F8
E8
TDI
E7
GS2962-IBE3
STANDBY
TIM_861
SMPTE_BYPASS
DVB_ASI
RATE_SEL0
RATE_SEL1
IOPROC_EN/DIS
20BIT/10BIT
SDO_EN/DIS
DETECT_TRS
ANC_BLANK
TCK
TDO
TMS
TDI
Return Loss Compensation Network
RSET
SDO
SDO
H5
H6
D3
G3
G6
G5
E3
E4
G7
G4
D4
F3
H3
F10
750Ω
5.6nH
4.7µF
1
CD_VDD
SDO
75Ω
C10
SDO
D10
SDO
75Ω
10nF
GND_A
GND_A
75Ω
75Ω
5.6nH
CORE_GND
CORE_GND
CD_VDD
4.7µF
1
SDO
SDI Output
A8
2
3
A7
2
3
200Ω
1µF
GND_A
PLL_VDD
PLL_VDD
100pF
10µF
CD_VDD
B7
VCO_VDD
Close to GS2962.
IO_VDD
A5
E1
K8
G10
+1.2V
Close to
GS2962
GND_A
G1
H10
GND_A
10nF
10nF
10nF
IO_VDD
IO_VDD
10µF
(SUBJECT TO CHANGE)
GND_A
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG/HOST
RESET
LOCKED
IO_GND
IO_GND
K9
J10
K10
J9
H8
G8
H4
G2
H9
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
B5
C5
E2
E5
E6
F5
F6
G9
A_GND
A_GND
VCO_GND
CD_GND
CD_GND
CD_GND
CD_GND
C9
D9
E9
F9
C6
C7
C8
PLL_GND
PLL_GND
PLL_GND
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG/HOST
RESET
LOCKED
B9
B10
B8
K7
J7
J6
K6
H7
K5
J5
J4
K4
GND_A
Notes:
1. DNP (Do Not Populate).
2. The value of the series resistors on video data, clock, and timing
connections should be determined by board signal integrity test. (See Section 4.1.1)
3. For analog power and ground isolation refer to PCB layout guide.
4. For critital 3G signal layout refer to PCB layout guide.
5. For impedance controlled signals refer to PCB layout guide.
Figure 5-1: Typical Application Circuit
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
www.semtech.com
76 of 81
6. References & Relevant Standards
SMPTE ST 125
Component video signal 4:2:2 – bit parallel interface
SMPTE ST 259
10-bit 4:2:2 Component and 4fsc Composite Digital Signals - Serial Digital
Interface
SMPTE ST 260
1125 / 60 high definition production system – digital representation and
bit parallel interface
SMPTE ST 267
Bit parallel digital interface – component video signal 4:2:2 16 x 9 aspect
ratio
SMPTE ST 272
Formatting AES/EBU Audio and Auxiliary Data into Digital Video Ancillary
Data Space
SMPTE ST 274
1920 x 1080 scanning analog and parallel digital interfaces for multiple
picture rates
SMPTE ST 291
Ancillary Data Packet and Space Formatting
SMPTE ST 292
Bit-Serial Digital Interface for High-Definition Television Systems
SMPTE ST 293
720 x 483 active line at 59.94Hz progressive scan production – digital
representation
SMPTE ST 296
1280 x 720 scanning, analog and digital representation and analog
interface
SMPTE ST 305
Serial Data Transport Interface
SMPTE ST 348
High Data-Rate Serial Data Transport Interface (HD-SDTI)
SMPTE ST 352
Video Payload Identification for Digital Television Interfaces
SMPTE ST 372
Dual Link 292M Interface for 1920 x 1080 Picture Raster
SMPTE ST 424
3Gb/s Signal/Data Serial Interface
SMPTE ST 425
3Gb/s Signal/Data Serial Interface - Source Image Format Mapping
SMPTE RP165
Error Detection Checkwords and Status Flags for Use in Bit-Serial Digital
Interfaces for Television
SMPTE RP168
Definition of Vertical Interval Switching Point for Synchronous Video
Switching
CEA 861
Video Timing Requirements
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
www.semtech.com
77 of 81
7. Package & Ordering Information
7.1 Package Dimensions
1.700
(0.366)
0.366
Figure 7-1: Package Dimensions
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
www.semtech.com
78 of 81
7.2 Packaging Data
Table 7-1: Packaging Data
Parameter
Value
Package Type
11mm x 11mm 100-ball LBGA
Package Drawing
Reference
JEDEC M0192 (with exceptions noted in Package Dimensions on
page 78).
Moisture Sensitivity Level
3
Junction to Case Thermal
Resistance, θj-c
10.4°C/W
Junction to Air Thermal
Resistance, θj-a (at zero
airflow)
37.1°C/W
Junction to Board
Thermal Resistance, θj-b
26.4°C/W
Psi, ψ
0.4°C/W
Pb-free and RoHS
Compliant
Yes
7.3 Marking Diagram
Pin 1 ID
GS2962
XXXXXXE3
YYWW
XXXXXX - Last 6 digits (excluding decimal)
of SAP Batch Assembly (FIN) as listed
on Packing Slip.
E3 - Pb-free & Green indicator
YYWW - Date Code
Figure 7-2: Marking Diagram
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
www.semtech.com
79 of 81
7.4 Solder Reflow Profiles
The GS2962 is available in a Pb-free package. It is recommended that the Pb-free
package be soldered with Pb-free paste using the reflow profile shown in Figure 7-3.
Temperature
60-150 sec.
20-40 sec.
260°C
250°C
3°C/sec max
217°C
6°C/sec max
200°C
150°C
25°C
Time
60-180 sec. max
8 min. max
Figure 7-3: Pb-free Solder Reflow Profile
7.5 Ordering Information
Table 7-2: Ordering Information
Part Number
Package
Pb-free
Temperature Range
GS2962-IBE3
100-ball BGA
Yes
-20°C to 85°C
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
GENDOC-048005 September 2013
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80 of 81
DOCUMENT IDENTIFICATION
CAUTION
FINAL DATA SHEET
ELECTROSTATIC SENSITIVE DEVICES
Information relating to this product and the application or design described
herein is believed to be reliable, however such information is provided as a
guide only and Semtech assumes no liability for any errors in this document, or
for the application or design described herein. Semtech reserves the right to
make changes to the product or this document at any time without notice.
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A
STATIC-FREE WORKSTATION
© Semtech 2012
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright
owner. The information presented in this document does not form part of any quotation or contract, is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or
intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected
operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or
electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or
operation outside the specified range.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN
LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH
PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK.
Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall
indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs damages and attorney fees which could arise.
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
Contact Information
Semtech Corporation
Gennum Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Final Data Sheet Rev. 8
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