NXP_06_0198_Internet Radio Solutions

NXP LPC4357based solution for
internet radio
High-performance dual-core LPC4357
MCU for Internet Radio solution
This fully equipped solution provides everything you need to get started with a
design, including a Keil evaluation board, based on the LPC4357 ARM Cortex-M4/M0
microcontroller, and complete source code.
KEY FEATURES
 Internet radio supporting SHOUTcast radio stream
 Full design based on Keil MCB4357 evaluation board
 204-MHz ARM Cortex-M4/M0 LPC4357 microcontroller
 ARM Cortex-M4 core performs
- Audio decoding without an OS
- I/O activities
 ARM Cortex-M0 core implements
- LwIP TCP/IP stack
- emWin-based GUI
- Application processing using FreeRTOS
 LCD interface with touchscreen display
 10/100T Ethernet MAC for network connectivity
 SDRAM interface for buffering music streams
 Support for optional microSD card containing MP3 files
 On-chip High Speed USB device/host/On-The-Go controller
 5 V power supply using on-board USB interface
 Compatible with Keil µVision 4.70
TARGET APPLICATIONS
 Audio entertainment
NXP_06_0198_Internet Radio Solutions Leaflet_939775017497_V2.indd 1
This design example, which highlights the capabilities of the
dual-core LPC4357 microcontroller, can be used as an MP3
player, playing MP3 files from a user-supplied SD card, or as an
internet radio, using a SHOUTcast radio stream.
Application tasks are divided between the two LPC4357 cores.
The ARM Cortex-M4 deals with audio decoding and related
I/O activities, without an OS, while the M0 core runs the LwIP
TCP/IP stack, the emWin-based GUI, and the internet radio
application, using FreeRTOS.
Dividing the tasks between the two cores creates a highly
efficient system, with bandwidth to spare, and also makes the
design easier to manage, from a development standpoint.
Having separate tasks performed by separate cores simplifies
design optimization. The Cortex-M0 core can be configured to
support a more robust GUI or a High Speed USB device/host
function without impacting the job of MP3 decoding. Similarly,
the Cortex-M4 can be programmed to perform extra audio
processing, such as Dolby Surround 5.1, without impacting the
GUI or the TCP/IP stack.
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The application uses only a portion of the dual-core
architecture’s full capabilities, so there’s plenty of bandwidth
for user customization. The design can be modified to take on
extra features, such as added connectivity or additional audio
processing, while maintaining its run-time behavior.
Partitioning the design enables higher performance, because
each core is used to its best advantage. Compared to a singlecore microcontroller operating at the same clock frequency,
the dual-core LPC4357 has more horsepower. It can implement
tasks that require more MIPS and more run time, lowering the
risk of impacting application functionality.
COMPLETE DESIGN
The design example includes all the necessary hardware components
for the application. All that’s needed to run the MP3/WAV
Player is a microSD card and an internet connection for the
Internet Radio.
Source code, developed using the Keil MDK-ARM environment
and µVision version 4.70, is provided with the design.
The project page can be found on LPCware.com:
www.lpcware.com/internet-radio
ABOUT THE LPC4357
The LPC4357 is an ARM Cortex-M4 based digital signal
controller with an ARM Cortex-M0 coprocessor designed
for embedded applications requiring signal processing. The
ARM Cortex-M4 core offers single-cycle Multiply-Accumulate
and SIMD instructions and a hardware floating-point unit to
support signal processing, while the M0 coprocessor handles
I/O and digital control processing. The LPC4357 includes 1 MB
Flash memory, 136 kB of data memory, two High Speed USB
2.0 Host/OTG/Devices, advanced configurable peripherals
such as the State Configurable Timer (SCT), Serial General
Purpose I/O (SGPIO), and SPI Flash Interface (SPIFI) as well as
Ethernet, LCD, an external memory controller, and multiple
digital and analog peripherals.
Design architecture
Feature/Resource
Cortex-M0
Cortex-M4
CPU speed
180 MHz
180 MHz
Memory
 Code execution: Flash bank #B
 Internal SRAM, external SDRAM
 Code execution: Flash bank #A
 Internal SRAM, external SDRAM
Software
components
 Free RTOS
 LwIP Ethernet stack
 emWin graphics library
 SHOUTcast application
 UART debug output
 MP3 decoder
 I2S interface handling
 UART debug output
Peripherals used
 Ethernet
 LCD
 UART
 GPIO
 I 2S
 UART
Possible add-on features
 USB device for connection to PC host
 More sophisticated GUI
 Implementation of AAC+ decoder
 MP3 player from microSD Card
 USB host for MP3 player from USB memory stick
 Audio enhancements (equalizer, 5.1 Surround, etc.)
Figure 1
Figure 2
User interface for Internet Radio
User interface for MP3 Player
www.nxp.com
© 2013 NXP Semiconductors N.V.
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
Date of release: December 2013
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and
Document order number: 9397 750 17497
may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof
Printed in the Netherlands
does not convey nor imply any license under patent- or other industrial or intellectual property rights.
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