Basics of ATE Test

Basics of ATE Test
Basics of ATE Test
Revised 8/8/2007
1
Course Contents
1. Introduction to Semiconductor Testing
Design and manufacturing cycle of an IC
Semiconductor Companies/Staffs
ATE – Automated Test Equipment and its components
Load boards, Probe cards, Handlers, Probers
2. Project Plan, Specifications and Test Program
Project/Test Plan – Introduction, Benefits, Requirement, Sample
Specifications – Design, Test, Device, Sample
Test Program – Types, Consideration, Test Flow, Binning, Summary
Common Categories of Test for Semiconductor Device
Functional, DC, AC Specifications of Device
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Course Contents
3. DC Parameters Test (including Continuity Test)
Continuity Test - Concept, Test Method, Sample Datalog
DC Tests – Concept and Test Method
Power Supply Current Test (IDD)
Leakage Test (IIL/IIH)
IOZL/IOZH, IOS
VOL/IOL, VOH/IOH
ATE DC Subsystem - VI Source, DC Meter, DC Matrix, Relay Control
4. Digital Functional Test
ATE Pin Electronics
Test Concepts – Pattern, Timing, Levels
IO Signals – Input Signal Generation, Output Signal Compare
Functional Testing Basic – Example VIL/VIH, VOL/VOH
Test Vectors
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Course Contents
5. AC Parameters Test
AC Timing Tests - Setup Time, Hold Time, Propagation Delay, etc
ATE Time Measurement Subsystem
Timing Calibration
6. Introduction to Mixed Signal Testing
Sampling Theory – Nyquist Theorem, Coherency Formula
Fast Fourier Transform (FFT) – Frequency Domain Analysis
Generic Mixed Signal Tester Architecture – AWG and Digitizer
7. ADC and DAC Test
ADC and DAC Basic
Static Test – Histogram method (INL, DNL)
Dynamic Test – SNR, THD, SINAD
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Course Contents
8. Debug Tools and Debugging
Tools - Datalog, Histogram, Shmoo, Pattern Debugger, Waveform Tool
Trouble-Shooting Techniques
9. Introduction to Design-For-Testability
DFT consideration
Test Approach – AdHoc, Scan (and Boundary Scan), Self-Test (BIST)
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Introduction to
Semiconductor Testing
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Overview
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•
•
•
•
•
•
•
•
Design and manufacture cycle of an IC
Classification of IC`s
What is ATE ?
Why tester ?
What is test ?
Components of a Test System
Load boards /Probe cards
Typical Test program flow
Handlers /Probers
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IC Design & Manufacturing Cycle
Design
Fabrication Fabrication Facility
Silicon Wafer
Assembly
Facility
Design and
Verification
System Requirement
Die Packaging
Wafer
Processing
Final
Test
Wafer
Probe
Handler
Prober
Circuit die
Final Product
 Devices are tested at two points:
 Wafer Probe – In this the die on the wafers are tested using very
fine needle like probes. The equipment that interfaces with the ATE
at this stage is called a Prober.
 Final Test (or Assembly Test or Package Test) – At this stage the
devices are in packaged form (called chips). Machines used to
interface package parts to
the ATE are called Handlers
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Wafer, Single Die and Package device
Wafer
Die
Package Device
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Standard Packages
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Classification of IC`s
Digital IC
A digital integrated circuit uses digital signaling and is the most popular
type of IC. For example a microprocessor IC.
Analog or Linear IC
An analog integrated circuit contains no digital data path control
functions. All signals are analog. For example an audio amplifier IC.
Mixed Signal IC
A mixed signal IC contains both analog and digital components. It is the
fastest growing segment of the industry. For example a single chip radio
IC,ADC,DAC.
To minimize cost and size of the end product, more and more functions
are being integrated on a single chip and such devices are referred to
as System-On-Chip or SoC devices.
Analog Signal
Digital Signal
Analog Signal
Digital Signal
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Semiconductor Test Companies
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Integrated Device Manufacturer (IDM): Semiconductor companies that have
integrated operations including design and manufacturing. Examples: IBM,
Intel, Texas Instruments, Samsung, STMicroelectronics
Strategic Outsourcing Model: A newly adopted business model that allows
IDMs to outsource leading edge designs, while maintaining process technology
development. Examples: Motorola and ADI
Fabless: A business model whereby a semiconductor company outsources at
least 75 percent of their silicon wafer production to outside sources. Examples:
Qualcomm, Broadcom, Marvell, Nvidia
Foundries: A silicon wafer manufacturer that partners with companies to
manufacturer their silicon wafers. Examples: TSMC, UMC, Chartered, SMIC,
Silterra, 1st Silicon, IBM Microelectronics
Sub-Contractors (SubCon): Companies that provide manufacturing services
on Wafer Testing, Die Assembly, Packaged IC Testing to other semiconductor
companies. Examples: ASE, Amkor, SPIL, StatsChipPAC, KYEC, UTAC
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Test Related Personnel
•
•
•
•
•
•
Test engineers
– Write & debug test programs, correlate with bench (evaluation
boards)
Product engineers
– Monitor the product, set test limits, diagnose failures
Shop operators
– Organize product through the shop floor
Applications engineers
– Help with testing situations, software bugs, new features, give
presentations
Maintenance staff
– Keep machines alive !!
Field service
– Vendor staff who install new machines, and fix tricky problems
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Common ATE Buzz Words
ASP - Average Selling Price
ATE - Automatic Test Equipment
DUT - Device Under Test
DIB - Device Interface Board - or LOAD board
DIE - An individual site on a wafer
HIB - Handler Interface Board - another name for the DIB !!!
PIB - Probe Interface Board - used with wafer probing
PROBE CARD – PCB with needle-like probes used at wafer probing
BINNING - Sorting the DUTs dependant upon test results
MANIPULATOR - Structure that supports the test head and allows it to
move in many directions. This movement allows it to access other pieces
of equipment.
HANDLER - Mechanical assembly for placing DUTs in the test head socket
PROBER - Mechanical unit for moving the wafer under the test probes
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What is ATE ?
 ATE is a collection of high performance computer controlled test
instruments.
 Automated test systems encompass a broad range of such instruments
controlled by a computer . Each system includes all the equipments
used to test a semiconductor device‟s functionality.
 Test program tester computer controls the test hardware by executing a
set of instructions called test program .
 Testers ensure the integrity, quality and reliability of semiconductor
components.
 Testers consist of electronic systems that generate signals, establish
appropriate test patterns, properly set them in sequence and then use
them to drive the semiconductor device itself.
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Why Tester ?
Testing Large no. of devices
More Profitability
 Testers help in automating this task so that it can be done at a
high speed without compromising on the accuracy of the test.
 The same tester can be used to test a wide variety of devices
reducing the overall impact of the capital investment required to
utilize a tester.
 Testers help in achieving a shorter “Time to Market”
 Testers help in achieving repeatable accuracy & correlation of
results
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How Does Test System Work ?
DUT
Signals
010101
Pattern (or Vector)
• Testers can be programmed to generate any
type of signals.
• A no. of signals together make up a test
pattern or test vector.
• A test vector is applied to the device at a point
in time.
• The outputs generated by the DUT are fed into
instruments in the tester to measure their
parameters.
• The results of the measurements are
compared to ―programmed Values‖ stored in
the ATE.
• A device is considered functional if the
measured parameters match the
programmed/golden values within acceptable
tolerances
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progra Output
mmed Values
Values
+
Signal
Generation
Compare
Pass
Yes
Match?
No
Fail
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ATE Machine Types
•
•
•
•
•
•
VLSI Testers
– Period based, Number and Speed of Pins, Signal Integrity.
Memory Testers
– Similar to VLSI tester with Memory Test Pattern Generation and
good Multi-Site capability.
Mixed-Signal Testers
– Frequency Based, Digital and Analog highly synchronized, MultiSite capability.
RF Testers
– RF Generators, RF Ports, Network Analyzers
Power Testers
– High Voltages and High Current Switching
SystemOnChip (SOC) Testers
– Can do it all !!! (Big Advantages)
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Mixed Signal Test System
Main Frame
DC
Instruments
Device Interface Board (DIB)
Tester
CPU
Device Under Test (DUT)
DC
Matrix
User
Workstation
DSP or
Array
Processor
AC
Instruments
Time
Measurement
System
Digital
Subsystem
Test Head
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Mixed-Signal: Tester Requirements
Digital
DC Instruments
AC Instruments
DSP Processing
Sequence Control
Clock data
Digital pattern
Pins
Serial I/O
Power Supplies
DC Matrix
DC meter
Arbitrary Waveform Generator
Digitizers
Video Instruments
Time Measurement
Digital Signal I/O
Array Processing
Synchronization
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Major Test System Elements
Tester MainFrame
To house test instruments, system support instruments (CDU, DSP Processor)
Tester TestHead
House test instruments channels that interface onto DIB.
User Workstation And/Or Tester Computer
For user to load/debug/execute test programs, process, datalog and store test
results
Manipulator
Support structure that enables TestHead to move and dock to handler/prober
DIB (Device Interface Board)
Hold test socket for device, or for interface with probe card.
Handler/Prober
Mechanical Equipment to enable device/wafer
to be positioned for testing/probing
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Components of a Test System
Typical components of a tester.
 Test head
 User/Tester computer
 DC subsystem
 Digital subsystem
 AC subsystem
 Time measurement system
 Channel card electronics
 Timing and formatting Electronics
 Power subsystem to provide adequate stable power to
all of the above.
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Load Boards/ DIB Boards
A Load board or DUT board is a circuit board designed to serve as an 'interface'
board between the automatic test equipment (ATE) and the device under test
(DUT) for packaged devices.
Load boards contain the necessary components to:
1) Set up the DUT for correct testing by the ATE.
2) Route the test and response signals between the DUT and the ATE.
3) Provide additional test capabilities that the ATE may not be able to provide.
There are also load boards designed for the purpose of testing or calibrating the
ATE itself.
Test Sockets
Flex DIB
Catalyst DIB
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J750 DIB
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Probe card
A Probe card is a circuit board designed to serve as an 'interface' board
between the automatic test equipment (ATE) and the Die under test (DUT)
for wafer probing.
Probe cards connect the test head electronics to individual pads of the die.
Relays and external components
Probe pins
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Handlers
What is a handler ?
A handler is a complex machine that moves the packaged
device to the tester so that it can be tested.
Who makes handlers?
Synax
MultiTest
MCT
ASECO
EPSON.. etc
Handler
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Probers
What is a Prober ?
A Prober is a complex machines that moves the whole wafer
(unpackaged devices) so that it can be tested.
Who makes Probers?
TEL
Electroglass
TSK …etc
Test head
Prober
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Self-Assess Questions
1. Which of the below are the elements of a test systems?
Tester, Handler, Prober, Manipulator, Loadboard
2. Which of the below are not part of an ATE tester?
Mainframe, Manipulator, Loadboard, User Workstation, Handler
3. What do the below acronyms stand for?
ATE
DIB
DUT
SOC
4. In IC Manufacturing cycle, testing for the IC functionality is
performed at 2 stages. One is Final/Package Test. What is the
other?
5. Name at least 2 categories/classification of IC Device
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PROJECT PLAN , SPECIFICATIONS,
AND TEST PROGRAM
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WHAT IS TESTING ?
Testing is the process of sorting the defective from nondefective, segregating bad and good units.
We do testing to
 Ensure quality product
• Meet published device specifications
• Characterize to determine device performance and
provide design feedback
 Detect faults at earlier stage to save cost
 Provide feedback on process
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What is Project Plan ?
Formal documentation of test goals
and procedures.
An iterative planning process using
all available data.
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Why do we need Project Plan?
To
define
goal,
scope,
requirements, schedule, cost,
resources, timeline, expected
performance and confidence
level.
To measure the progress of
testing activities by comparing
actual
performance
against
expected performance.
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Benefits of having a Project Plan?
Specify what activities to be part
of testing process
Improve communication among
individuals (engineers)
Reduce chance of failure during
the execution of the test
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What If We Don’t Have Project Plan?
“ we just don’t have time
to do an adequate job
for testing.”
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What If We Don’t Have Project Plan?
“Most of the costs associated with testing are incurred
because we enter testing without a clear idea of
what is to be accomplished and how it is to be
accomplished.”
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When do we start generating Project Plan?
As soon as the project‟s
requirements are defined.
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Requirements for a Project Plan
Some basic knowledge required to generate test plan
are as follow:
I. DUT Requirements
II. Tester
III. DUT Interface
IV. Software Environment
V. Device Test Plan
VI. Project Gantt Chart
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Device Testing Requirement
I. DUT Requirements
- Description of each pin
- Details of parameters to be tested
- DC & AC specifications of the device , etc
- Signals Requirements for input/output
II. Tester
- Availability of instruments
- Accuracy of instruments
- Programmability of instrument
- Specification Manual
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Device Testing Requirement
III. DUT Interface
- The purpose is to connect the DUT pins to the
system to send and receive signals.
- DIB is the hardware interface between the DUT and
the tester .
IV. Software Environment
- Software to generate and run the test
program
- At the end, the test results are
recorded and the binning result sent to
the operator
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Device Testing Requirement
V. Device Test Plan
This is a documentation of the detailed description of
all the tests in the Test List with binning information.
IV. Project Gantt Chart
A chart showing the scheduling Plan of
the project phases.
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Device Test Plan Sample
Test Plan for XXXX Device
Binning info
Test #
Test number
30
40
50
Description
Basic Functional Test
VIL=0.8V, VIH=2.0V,
VOL=0.45, VOH=2.4V
SPEED = 1MHZ
Pattern Used: Func1_pat
At Vccnom
At Vccmin
At Vccmax
Binning
10
FAIL
Test conditions
Test Description;
The functional tests did a write of 1010 to ports 4-7 follows by a read
of 0101 from ports 4-7 at Vcc= min, max and nom.
Test description
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Sample Gantt Chart
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Requirement to Create a Test Program
• To generate a test plan, details of the device specification
should be reviewed
• Test specifications and tests to be executed need to be
prepared.
• Test hardware (Load board and probe card) need to be
designed accordingly
• Test program need to be generated based on the test plan
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Specifications - Overview
Design specification
Test specification
General test methods
Device specification
Sample specification
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Design Specification
VLSI
Designer
 Design Specification is a document which contains the
definition of intended functions and performance
characteristics of a new circuit design
 Design specification will be mostly created by
Sales/Marketing dept or design engineering dept. In some
cases it will be created by end user also.
 After producing the device it must be characterized and the
actual performance of the device will be compared with
Design Specification.
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Test Specification
VLSI Designer
 Test Specification is a document which contains
the detailed step-by-step procedure to test the
circuit fully
Test
Development
Team
 Test specification will be created by combined
effort of design, test and product engineering
departments.
 It defines the exact conditions to be used for Test
Program development
 While testing, if there is any difference in any
parameter, it will be noted and updated in the
published device specification.
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Device Specification
* will be covered in more details in next chapter
 Device specification is a published document by device
manufacturer. It is called Datasheet or Data book
specification.
 It contains the general current, voltage and timing details of
the device which will be used for Test program development.
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To generate a
good test plan?
Study
device specification !!
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WHAT IS THE
PURPOSE
OF A TEST
PROGRAM?
A test program manipulates
tester machinery to
1. Simulate the operating
environment of a DUT
2. Control the DUT to execute
its operational functions
3. Measures its response and
4. Interprets the results to
determine if DUT is good or
bad
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Types of Test Program
Test Programs are divided as follows.
a) Engineering
b) Characterization
c) Production
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Engineering Test Program
 Initial test program is called as Engineering
program which will be used to verify the
functionality of the device.
 Should be flexible for altering voltages, currents
and timings.
 Quick debugging & some characterization
routines should be available.
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Characterization Test program
 Extension of Engineering test program.
 Used to determine the operating limits.
 Tester pre-defined routines should be used to plot the
characterization chart for shmoo, level search and time
search routines.
 Usually after design, Characterization program is used
to completely check if the device meets its
specifications and collect characterization data.
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Production Test Program
 Used to identify the bad devices from the good
devices.
 It will be used for wafer sort, final test or QA test.
 Should be faster.
 Should be able to segregate failures and plot the
summarized report (Yield).
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Program Development Consideration
a)
b)
c)
d)
Hardware Limitations
Throughput
System Availability
Test Costs vs. DUT Cost
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Hardware Limitations
 Test Specification should be reviewed and timing diagram
should be developed to confirm the tester capability
respective to test requirements.
 Test rate, voltage and current requirements should be
accounted.
 Consider wafer probers, handlers and other external
equipments.
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Throughput & System Availability
 Estimation of test time in the target test system
 If the throughput is less, try for alternative test system.
 Availability of test system.
 Availability of support equipments.
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Test Costs vs. DUT Cost
 Cost of the test device should be considered while
selecting the target test system.
 If we use expensive test system for a low cost device, it
will be less profitable to manufacture.
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Creating a Test Program
 Product Data Sheet
Contains Pinout , Functional details , DC & AC
specification of the product.
 Test Plan Matrix
Includes the exact test condition on all device
pins,while performing each test.
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Creating a Test Program
 Tester Resources
Identify required resources within the tester which is
capable of testing the product.
 Load board Design
PCB where tester resources are wired to edge connector of
the DUT directly or through some active/passive
components.
 Writing Test Program
Software coding which forces and measures required
parameter in corresponding test platform.
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Program Flow
 Test program flow is important for a production test .
 It is the sequence at which the test program is executed.
 Most fail tests should be there as firsts in flow.
 Throughput is very important factor in program flow.
 Test procedure for speed grading or multipass binning will
give added advantage.
 Test summaries should be reviewed in period of time and
flow should be modified if necessary.
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TYPICAL TEST PROGRAM FLOW
• Contact (for open & shorts, DUT unpowered)
Check each DUT pin is connected - save failures for retest.
Uses the ESD diodes on the pins - usually test both diodes Vdd and Gnd.
•DC Parametric Tests (with DUT power applied)
Verifies the device DC (current, voltage) parameters
•IDD/Power Supply
Good indication of overall device functionality
Check during an operating mode
• Functional tests
Test out device for full functionality
May do a “quick functional” test first
• AC Parametric tests
Verifies the AC Specifications - includes quality of output signal and signal timing
parameters
• Binning
May have several “good” bins - “Bin 1 is golden”, “happiness is bin 1”
Bin contact failures separately
Sometimes use bin numbers for ease of failure analysis.
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Program Flow Diagram
Fail Bins
Open/Short
DC Parametric Tests
Bin5
Bin6
Bin7
IDD
Functional Test
AC parametric Test
This is a Typical test
Flow with the binning
details for the PASS and
FAIL bins.
Bin8
Bin8
Bin1
Pass Bin
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Program Initialization
 Test options (Wafer sort, final test, QA test, etc)
should be selected by user.
 Additional information like Lot number, Operator ID
and Test System number can also be provided.
 Instruction to setup the hardware may be provided in
the opening menu for operator
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Test Setup Verification
 Load board check should be
there.
 Quick diagnostic should be used
to check the test system.
 Automatic load board
identification should be possible.
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Power-On Sequence
 Care must be taken for CMOS devices to avoid latch
up.
 Latch up can cause excessive currents in flow within
the device.
 Device powering up should be followed as per the
Power On Sequence flow.
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Power-On Sequence Flow
Power up VDD
Power up I/P Levels
Power up O/P Loading
Power up External HW
Device fully powered
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Power-Off Sequence
Test System must be prepared for power down after
binning is completed.
VDD Supply should be the last one in powering down.
Device powering down should be followed as per the
Power Down Sequence flow.
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Power-Off Sequence Flow
Power Down O/P Loading
& External HW
Power Down I/P Levels
Power Down VDD
End of Test
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What is Binning ?
Used for categorizing the tested devices.
Binning is divided as hard binning and soft binning.
Hard binning controls the physical operation where the
DUT should be placed (tube or tray).
Number of hard bins are limited by external handler
whereas soft bins are unlimited which used to track
various pass / fail categories.
Bin7
DUT
Bin8
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Bin1
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Binning Cont …
A bin number is a number which represents the ultimate
rating and performance of the DUT.
After a device is tested in final test, it is physically moved by
the handler to the bin in which it belongs.
The bin number encompasses the gross characteristics of a
device.
Hardware bins are used by the attached handler or prober .
Software bins can be used by the Test Engineer to group failure
modes
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Binning Cont …
Sample binning
Hard Bin Soft bin #Category
1
2
3
4
4
6
7
10
20
30
40
50
60
70
Good Device
Opens and shorts reject
Gross Function fail reject
Functional VIL/VIH reject
Leakage reject
AC test reject
IDD test reject
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Test Summary
Test summary provides statistical
information.
Summary should indicate total tested, total
passing /failing and the number of failures
in each category.
Test summary gives valuable input for yield
issues, so it should include more
information in it.
Summary
Header
xxxxxxxx
xxxxxxx
Total tested
No of device failed
xxxxxxx
300
20
---------------------Bin Pass Fail Yld
1
2
3
0.3%
Partial summary should be able to be
produced during production testing.
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Sample Test Summary
***********************SUMMARY REPORT****************************
TEST TEMP: 85C
LOT NUMBER: 123568 01/23 DATE 24 FEB 2004
TOTAL UNITS TESTED : 1000
TOTAL GOOD UNITS : 800
*********************************************************************
TOTAL UNITS % OF TOTAL
TOTAL TESTED ...............................1000
TOTAL PASSED.BIN 1...................... 300
30
TOTAL PASSED.BIN2........................500
50
TOTAL FAILED.................…..............200
20
Cont_dym_Short......................…….........10
Cont_dym_Open.......................……........00
Cont_Parametric.................………...........00
Functional_Test.................………....….....30
Low_Leakage_Test............…….......….....30
High_Leakage_Test..................…….........00
TristateLow_Leakage.............………........10
Static_Icc..............................………..…....50
Dynamic_Icc....................…………..........50
Freq_counter_Test............………..............20
Scan_Test1......................…………...........00
Falltime..............................…..………......00
Falltime_meas....................………............00
1
0
0
3
3
0
1
5
5
2
0
0
0
Total devices : 1000 Total passed
devices :8/8/2007
800 Total
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Test Program
What we have learnt:
•
•
•
•
•
•
•
Types of test program
Consideration in Program Development
Typical production test program flow
Program flow
Power on/off sequence
Binning
Test summary
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COMMON CATEGORIES OF TEST
Contact/Continuity Test
Checks for open circuits or short circuits in the device pins
DC PARAMETRICS TEST (including IDD)
Verifies the device DC current and voltage parameters
DIGITAL FUNCTIONAL TEST
Tests the logical operations of the DUT
AC TIMING TEST
Verifies the AC specifications which includes quality of
output signal and signal timing parameters
MIXED SIGNAL TEST
Verifies operations on analog and digital circuitries of the
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DUT
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DC Parametric Testing
a)
b)
c)
d)
Testing Input Voltages and currents
Testing Output Voltages and currents
Power Supply currents and voltages
Pass/fail limits for each parameter
Some DC PARAMETERS
- VOL/VOH/VIL/VIH
- IOL/IOH/IIL/IIH
- VDD/VCC
- IDD/ICC
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75
Functional / AC Testing



Functional Test will test the functionality / logic for the
best / worst conditions.
AC Test will check the Timings (Frequency, Pulse
widths, setup and hold times and delays etc)
Pass/fail limits for each parameter
Some AC PARAMETERS
- Propagation Delay
- Duty Cycle
- Rise/Fall time
- Pulse Width
- Frequency
- Setup/Hold time
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76
Device Specifications

Device specification must be clearly understood
before starting to write the test programs.

Various specifications are listed below :
a) Functional Description
b) DC Specification
c) AC Specification
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77
Functional Specification
 Usually Device Specification begins with functional
description and block diagram.
 Functional Logic will be available as truth table if the
logic is simple. For complex devices logic function will
be described in details.
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78
DC Specifications

DC Section defines the following operating
parameters of the device
a)
b)
c)
d)
Maximum Ratings
Operating Range
DC Characteristics
Capacitance
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79
DC Specifications
DC PARAMETERS
VDD
The supply voltage to a CMOS device
VCC
The supply voltage to a TTL device
IDD
The current drawn from the supply for a CMOS device
ICC
The current drawn from the supply for a TTL device
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DC Specifications
VOH
The worst case (min) voltage at the output that drives a logical 1
VOL
The worst case (max) voltage at the output that drives a logical 0
IOH
IOL
The maximum current the output can source when driving a
logic 1
The maximum current the output can sink when driving a
logic 0
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81
DC Specifications
VIH
The worst case (min) voltage at the input that is recognized as
logical 1
VIL
The worst case (max) voltage at the input that is recognized as
logical 0
IIH
The worst case (max) current the input pin can sink to maintain
logic 1 voltage at output of the device it is connected to
IIL
The worst case (max) current the input pin can source to
maintain logic 0 voltage at output of the device it is connected to
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82
DC Specifications
Conventions:
 When current flows OUT of a device, the device is said to
SOURCE current.
 Conversely, when current flows INTO a device, the device
is said to SINK current.
VOH
TESTER
(Reference)
- IOH
Device
VOL
+ IOL
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83
Typical VOL / VOH






VOL is output low voltage
VOH is output high voltage
TTL VOL = 0.4V
TTL VOH = 2.4V
CMOS VOL=0.1V (GND + 0.1) @ No load
CMOS VOH=4.9V (VDD – 0.1) @ No load
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84
IOL / IOH
 IOL is output sink current
 IOH is output source current
 Output pin will source the current when it drive logic
high.
 Output pin will sink the current when it drive logic low.
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85
DC (Current) Parameters
Current Sourcing
+VC
IOH
C
Load
Rout
VI
Load
IIH
GateThen,
Driving
Suppose there are
n loads, each sinking a current of IIH =Load
40uA.
Gate
H
Gate
Gate
VO
Logic 0
IOH = IIH(1st load) + IIH(2nd load)
H + IIH(3rdt load) + …………… + IIH(nth load)
Logic 0
+VC
Current Sinking
Logic 1
Logic 1
Driving
Gate
C
Rou
VO
t
L
Load
Load
Gate
Load
Gate
Gate
IIL
IOL
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VIL
86
VIL / VIH






VIL is input low voltage
VIH is input high voltage
TTL VIL = 0.8V
TTL VIH = 2.0V
CMOS VIL=1.5V (VDD x 0.3)
CMOS VIH=3.5V (VDD x 0.7)
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87
Power Supply Current (IDD)
 IDD is the measure of total current that flow`s into the
power supply pin.
 The IDD static current test ensures that the DUT will not
consume more current than the value stated in the device
specifications
 Generally, two types of current checks are performed:
– IDD Static Current check: DUT is inactive
– IDD Dynamic Current check: DUT is active
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88
Tristate Leakage Current (IOZ)
 IOZ is output high impedance leakage current.
 IOZL is the measure of output impedance leakage
current from the output pin to VDD when the output
pin is in tri state(high impedance state).
 IOZH is the measure of output impedance leakage
current from the output pin to GND when the output
pin is in tri state.
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89
AC Specifications
Propagation Delay
Delay from the time a signal is applied to the time when the output
makes its change
Rise Time
The time required for an edge to go from (typically) 10% to 90% of
its high limit voltage value
Fall Time
The time required for an edge to go from (typically) 90% to 10% of
its low limit voltage value
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AC Specifications
Duty Cycle
The ratio of the positive pulse width to the period (positive duty cycle)
Pulse Width
Positive pulse width is the period of time from the midpoint of a rising edge
to the midpoint of the immediate falling edge.
Negative pulse width is the period of time from the midpoint of a falling edge
to the midpoint of the immediate rising edge.
Frequency
To measure the maximum operating frequency of the device.
(Period = 1/Frequency)
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91
AC Specifications

AC Section contains the timing diagrams and
individual parameter values of the device.

It defines the type of AC load circuit to be used
while testing the output timing parameters

Further pages contain the sample datasheet of a
device.
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92
AC Specifications
87C196CA 18 MHz Microcontroller — Timing diagram
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93
Sample Specifications
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94
Sample Specifications
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95
Self-Assess Questions
1. Which of these below should be included in a Testplan?
Hardware Requirement, List of Test to performed,
Timeline/Schedule
2. What is the difference between Hard Binning and Soft
Binning?
3. Name at least 3 common categories of test performed
on a semiconductor device.
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96
DC Parameters TEST
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97
Continuity/Open-Short Test
The Continuity test checks for :
1. Device problem - Open/Shorted device pins. The cause for
opens or shorts can be due to error in fabrication of die or
problems in the physical packaging of the die like missing
bond wires, shorted pins, pin damaged by static electricity
etc
2. Tester system problem - poor interfacing between DUT and
testing equipment. Poor electrical contact between tester
(ie socket) or bad wafer probe card etc
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98
What is Open/Short Test ?
 This is typically the first test performed (at package and
wafer).
 Open test can identify the missing bond wire problems.
 Short test can identity the illegal short between pins.
 This is very simple test and can be done very faster which
reduce the average test time of bad devices
 Another name for open/short test is continuity test.
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Continuity Test
99
Types of Open/Short Test
 DC Test method/ Serial Static method
 Functional Test method
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Continuity Test
100
MODEL OF 1 DEVICE PIN
Vdd
Pin Circuitry
Vss
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Continuity Test
101
Test Concept
 PMU will be used in Force Current Measure voltage mode
to perform the Open / Short test.
 This test is done by making use of the protection diodes on
the device pins, specifically by forcing a positive or
negative current into the pin and measuring the resultant
voltage across the diodes, it can be determined if the pin
under test is shorted or open.
 This is done repeatedly as each pin is individually tested.
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Continuity Test
102
Test Concept
Input Stimulus:+Current or –Current
Expected Response:Voltage level dropped across protection diode
Test Condition(s):Power supply voltage set to 0V
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Continuity Test
103
Continuity Test Setup
Continuity Test
Vdd = 0V
I
PPMU
V
I
PPMU
V
Vss =0V
Using Pin PMU in force current and measure voltage mode
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104
Test mode: FORCE I, MEASURE V
One pin at a time
0 Volts
Vcc
0 Volts
Pin
Circuitry
I_force
0 Volts
+I
Vss
V_measure
Fail open : V_measure > 1.5 V
Fail Shorts : V_measure < 0.2 V
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105
DC Test method cont…
How to program?
1.
2.
3.
4.
5.
6.
7.
Drive 0.0V at all power pins (VDD, VSS etc…) and
input/output pins except the pin under test of the DUT.
Force current can be 100µA to 500 µA. Let us consider
we are driving 0.1mA for pin under test of the DUT which
will forward bias the VDD diode.
Clamp voltage can be set as 3.0V
If the measured voltage at pin under test is around +0.7V,
it passes for Open/Short Test.
If the measured voltage is 0.0V, pin has illegal Short
If the measured voltage more than 1.5V, pin is Open.
Similarly, all other pins of DUT will be tested.
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Continuity Test
106
Continuity Test
Serial /Static method …
Vdd = 0V
100ua
PMU
Signal
pad
VSS = 0V
VDD Diode test
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Continuity Test
107
VDD Diode Test Results
Positive Voltage Clamp
FAIL
Open Circuit
+1.5V
PASS
+0.2V
FAIL
Short Circuit
0.0V
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108
Continuity Test
Serial /Static method …
Vdd = 0V
PMU
Signal
pad
-100ua
VSS = 0V
GNDRevised
Diode
test
8/8/2007
Continuity Test
109
GND Diode Test
0.0V
FAIL
Short Circuit
- 0.2V
PASS
- 1.5V
FAIL
Open Circuit
Negative Voltage Clamp
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110
Functional Continuity Test Method
 Active Load / Functional Comparator will be used
to perform the Open / Short test.
 Negative or Positive current will forward bias the
VSS or VDD protection diode and received digital
output of each pin will be compared as explained in
following page.
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111
Functional Test Method (cont…)
1. Drive 0.0V at all power pins (VDD, VSS etc…) and
input/output pins except the pin under test of DUT.
2. Set VOH = 1.5V & VOL = 0.2V
3. Isrc = 0.1 mA & Vref = 3.0V
4. If the received vector at pin under test is Z (Hi-Impedance),
it passes for Open/Short Test.
5. If the comparator sense a output low “L” (less than 0.2 V),
pin has Short
6. If the comparator sense a output high “ H” (more than
1.5V ), pin is Open.
7. Similarly, all other pins of DUT will be tested with the
pattern.
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112
DC Continuity Test (sample datalog)
Fail open
Number Site Result
200
201
202
203
204
205
0
0
0
0
0
0
FAIL
PASS
PASS
PASS
FAIL
PASS
Test Name Pin Channel
cont_p2
cont_p2
cont_p2
cont_p2
cont_ctr
cont_ctr
p23
7
p22 31
p21 23
p20 48
cs
4
prg 30
Low limit
-1.5000V
- 1.5000V
- 1.5000V
- 1.5000V
- 1.5000V
- 1.5000V
Measured
-8.630 V
-785.3 mV
-953.0 mV
-877.4 V
-0.0004 mV
-943.96 mV
High limit
-200.0000 mV
-200.0000 mV
-200.0000 mV
-200.0000 mV
-200.0000 mV
-200.0000 mV
Force
-100.0000 uA
-100.0000 uA
-100.0000 uA
-100.0000 uA
-100.0000 uA
-100.0000 uA
Fail shorts
In the above example pin „cs‟ is failed due to Continuity short
& „P23‟ has failed due to Continuity open
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113
Comparison
DC Test
1 Slower
Functional Test
Faster
2 Can write the
Can‟t get detailed log.
detailed data log
for further
failure analysis.
Generally Functional continuity test can be performed first
and “if” functional continuity test fails then immediately the
DC continuity Test can be conducted.
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Continuity Test
114
WHY Continuity test fail?
COMMON DEBUGGING ACTIONS IF DEVICES
CONTINIUITY IN PRODUCTION
FAIL
Retest the device!
The protective diodes are sometimes faulty but such cases
are RARE.
Typically, failure of continuity test results are system not
receiving the part correctly or probe faults.
Hence, always set a limit for prober/handler maximum
consecutive failure number.
If the probes or socket is damaged, halt further testing and
contact the maintenance personnel.
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115
DC Parameters Test - Overview
Power Supply Current (IDD) Test and Test Method
Static IDD ,Dynamic IDD, IDDQ Test method
IIL/IIH and Test Methods
IOZL/IOZH and Test Methods
IOS and Test Methods
VOL/IOL and Test Methods
VOH/IOH and Test Methods
Fanouts
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116
What is DC Test ?
 DC parameters are tested by forcing current and
measuring voltage or forcing voltage and measuring
current.
 In both ways, only resistivity of silicon is being measured.
 Device conductive/resistive specs may differ as fullyconducting, semi-conducting or non-conducting.
 During DC test voltage or current is measured and the
pass fail results are based upon the measured value.
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117
Power Supply Current Test
Purpose / Why test
Impact
Test concepts
Terms
Test methods
IDD Gross Test method
IDD Static /Dynamic Test
method
IDDQ Test method
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118
Why test Power Supply Current
 Measures how much power supply current the DUT consumes
when it is powered up
 The main reason is to guarantee limited power consumption in
the customer‟s end application. Supply current is an important
electrical parameter for the customer who needs to design a
system that consumes as little power as possible.
 The Power Supply Current test checks for catastrophic defects in
the device. The cause for catastrophic defects can be due to
under-etching and/or photo-mask misalignment during fabrication
process.
 Typically, Power Supply Current Test is performed after Continuity
and Leakage Tests, prior to Functional Testing
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Power Supply Current Test
119
Test Concept
•
This test is done by measuring the current flowing from each
voltage source connected to the DUT.
•
The power supply is simply set to the desired voltage and the
current from its output is measured.
•
Gross IDD is a quick check for IDD, before continuing with
further tests.
•
Generally, two types of current checks are performed:
1. IDD Static Current check: DUT is inactive
2. IDD Dynamic Current check: DUT is active
•
The above is done repeatedly for each power supply pin as
each pin is individually tested.
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120
TERMS
VDD
The supply voltage to a CMOS device
VCC
The supply voltage to a TTL device
IDD
The current drawn from the supply for a CMOS device
ICC
The current drawn from the supply for a TTL device
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121
IDD Gross Current
 For the CMOS devices the current flow between
drain to drain is represented as IDD.
 For the TTL devices, it is represented as ICC
(collector to collector current).
 Gross indicates that the measurement made in
relaxed conditions which is defined in Specification.
VDD
G
D
IDD
S
G
S
D
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122
Why Gross IDD Test ?
 Used to measure the impedance between VDD and
GND of the DUT.
 To quickly determine whether it is reasonable to
continue the test.
 Mostly, this test will be performed after Continuity test.
Vdd max
 This is power on Test.
 Test system may get affected if DUT draws
A
excessive current.
If this test fails, test will be aborted and
DUT will be rejected.
Power Supply
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Power Supply Current Test
Vss
123
Gross IDD - Test Method
 Since we are performing this before functional test, test
limits should be relaxed
 Output should not be connected with load.
 Test limit should be 2 to 3 times greater than the device
specification.
 If the IDD is not specified in the specification, number of
devices should be tested and average current should be set
as test limit.
 Use DPS or System PMU for this test.
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124
Gross IDD - Test Method cont..
Gross IDD for troubleshooting
 Used to measure the impedance between VDD and
GND of the DUT.
 After developing the test program, if we come across
with Gross IDD failure, takeout the device from socket
and test it to measure 0ma current.
 If still fails, we can conclude something else is
consuming the current from test system. Load board
can also be removed to confirm the problem.
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125
Static IDD Current & Why ?
 Static indicates that the measurement is made when
DUT is not active.
 To ensure that the DUT will not consume more current
than the available value in the Specification.
 This is important for battery operated devices.
 To identify the processing problems with CMOS devices.
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126
Static IDD - Test Method
Vddmax
Idd
IDD Static
Spec Limit
Measure
Current
FAIL IDD
PASS
Vdd pin
Apply
Preconditioning
Pattern
Gnd
Resultant IDD Static current is measured
and compared against the test limits .
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127
Static IDD - Test Method
 DUT should be exactly preconditioned for the state which
consumes least IDD current.
 If the IDD current is small, additional delay time should
be given.
 External by-pass capacitors should be disconnected
using relays to avoid low IDD current measurement
problems.
 The DUT is held in a static condition and the amount of
current flowing into the supply pin is measured,
compared to the IDD static device specifications.
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128
Dynamic IDD Current & Why ?
 Dynamic IDD is the operating IDD of the device.
 The IDD dynamic current test insures that the DUT will not
consume more current than the value stated in the device
specifications while the DUT is actively performing its functions.
 This test measures total current flow into the power supply pin.
 Performed by executing a test vector pattern, normally at the
maximum operating frequency of the DUT.
 The resultant current measurement is compared to the IDD
dynamic device specifications.
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Power Supply Current Test
129
Dynamic IDD - Test Method
 Dynamic IDD measured when the DUT is driven by
continuous pattern at maximum operating frequency.
 VIL, VIH, VDD, Fmax are influencing the test results.
 Dynamic IDD should produce consistent results when
the test is repeated.
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130
Dynamic IDD - Test Method
Vddmax
IDD Spec Limit
Idd
Apply
Continuous
Pattern at
Fmax
Measure
Current
FAIL IDD
PASS
Vdd pin
Gnd
Resultant IDD dynamic current is measured
and compared against the test limits .
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131
IDDQ Current & Why ?
IDDQ is quiescent current
 A technique for finding shorts in CMOS devices that tests
for quiescent power supply current (Iddq).
 IDDQ testing has become a standard test technique used
to reduce PPM levels and detect reliability defects in
silicon used for high reliability applications.
 IDDQ (Quiescent IDD) testing is a useful to find longterm reliability failures, due to partially functioning logic
that did not fail during standard testing.
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132
IDDQ Test
• This test performs static IDD measurements at unique
points within a functional vector set . (Typically 5 to 10
measurements)
• The test vector sequence for this this test is to toggle on
and off as many transistors as possible and measure at the
different vector sequence stopping points.
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133
IDDQ Test
• Set the VDD to VDDmax.
• Start the IDDQ test vector.
• Stop at the test point and hold the device at the know
state.
• Measure the current flow between the VDD & VSS.
• Typical limits will be in micro_amps for a complex
CMOS device.
.
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134
Advantages of IDDQ
Diagnosing defects using IDDQ offers several advantages because:
 IDDQ is a cost-effective test method indispensable to identify
some defects which are not detectable by the conventional
functional tests.
 IDDQ enhances quality, shortens time-to-market and provides an
efficient SPMC (Statistical Process Monitor and Control) for yield
enhancement.
The types of potential problems detected by IDDQ include:
 Process flaws: bridging, deformed traces, mask problems,
incomplete etching, logically redundant defects.
 Design flaws: Floating gates, logic contention, mask generation
errors.
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135
IDD Test
 IDD tests are often performed with the device in several
different states
• Different power up states
• Power off (or “sleep”) state
• Some devices have different operating modes to
power down different sections
• These provide for ease of identification of sections
that do not properly shutdown
 Device may have several different power pins which go
to separate tester supplies
• IDD value = Sum of DUT(Idd1) + DUT(Idd2) + ...
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136
Leakage Test
Topics to cover:
Purpose / Why test
Impact
Test concepts
IIl/IIH and Test Methods
Serial/Parallel/Ganged Test
Methods
IOZL/IOZH and Test Methods
IOS and Test Methods
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137
Leakage Test: Purpose/Why
The Leakage test checks for :
Leakage in input current. It ensures that the input current
meets the design requirements i.e. the input pins does
not sink/source more than the current specified by the
specifications.
Too high leakage current for certain pins could result from
variations in fabrication process or the pin could be
damaged from static electricity.
The cause of leakage current could be due to presence of
an alternative lower resistive path
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138
Why Leakage Test ?
 Measures the resistance from input pin to VDD/GND.
 Insures that input will not draw more than the specified
IIL/IIH current when it is forced for low or high.
 Identify processing problems in CMOS devices.
 Typically this is one of the earlier tests performed,
usually after Continuity
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139
Test Concepts
Leakage is measured by simply forcing a DC voltage on
the input pin of the device under test and measuring the
small current flowing into or out of the pin.
Leakage is typically measured twice:
– measured once with an input voltage voltage near
the positive power supply voltage, and
– measured again with the input near ground (or
negative supply)
These two currents are referred to as IIH (input current,
logic high) and IIL (input current, logic low) respectively.
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140
Test Concept
The approach to testing for Leakage Current is
straightforward.
 The device specifications states the limits for IIH and IIL for
the device when certain voltage level is forced on the input
pins.
 We take the worst case limit as the limit for our test
program.
 VDDmax is the worst case test condition for these test.
 Before going into the details of the test, a brief section on
the likely causes of leakage current is covered.
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141
What happens if a pin is leaky ?
• Leakage is likely due to the presence of a lower
resistive path
• Overall current flow through the test pin INCREASES
due to the DECREASE in overall (input) resistance of
the test pin
• Leakage Testing tests for leakage of current from a
test pin to adjacent pins
• Eventually, further changes will violate the maximum
IIL/IIH limit
• The result is a failure in the Leakage Test
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142
IIL Test – Serial Method

All input pins are preconditioned for logic high
state except the pin under test.

PMU is connected to pin under test and then forces
this input low and the resultant current is measured
and compared with the specification limits.

The above is repeated for each input pin applicable
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Leakage Test
143
IIL Test – Serial Method
VDD
VDDmax
DUT
VDD
R
High
Impedance
0 volts
R
PPMU
Force 0 Volts
Measure current
VSS
VSS
VSS
 Performed by forcing a Zero voltage on the particular pin under test
 Measure the resulting current into the pin
 If “leaky,” amount of current into or out of the pin under test will be
> Spec Value
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144
IIH Test – Serial Method

All the input pins are set to zero volts except the pin
under test.

PMU is connected to pin under test and forced high.
The resultant current is measured and compared
with the specification limits.
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145
Test Method for IIH
VDD
VDDmax
DUTVDD
R
VDD
VDDmax
High
Impedance
R
PPMU
Force VDDmax Voltage
Measure current
VSS
VSS
VSS
 Performed by forcing the Vddmax voltage to the particular pin under test
 Measure the resulting current into the pin
 If “leaky,” amount of current into or out of the pin under test will be >
Spec Value
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146
IIL/IIH Parallel Test Method
 Some Test Systems are having per Pin PMU.
 Parallel measurement means all inputs will be driven low
simultaneously and measurement will be made for IIL test.
 Similarly, all pins will be driven high and measurement will
be made for IIH test.
 Parallel test method can not identify the leakage between
input pins as we are testing all pins simultaneously.
Revised 8/8/2007
Leakage Test
147
IIL/IIH Parallel Test Method
Vdd
PPMU
Force Voltage
Measure current
Gnd
 Test is performed two time by forcing Vddmax( IIH ) and Vss(IIL) using
PMU
 Program a delay of 1 to 5 ms wait time .
 Resultant current is measured and compared against the test limits .
Revised 8/8/2007
Leakage Test
148
Advantages / Disadvantages
Parallel Test Method
Advantage of this method is the test can be performed
faster and all the device pins are tested for its leakage.
Disadvantage is pin to pin leakage cannot be detected as
all the pins are at same voltage level.
 This method requires the system to have per pin PMU
hardware.
Revised 8/8/2007
Leakage Test
149
IIL/IIH Ganged Test Method
 Ganged Test method is nothing but connecting a single
PMU to all inputs at one time and measuring total current
flow.
 It can be used mainly for high impedance CMOS inputs
not for resistive inputs.
 Ganged testing will not work if different pin consumes
different current.
Revised 8/8/2007
Leakage Test
150
IIL/IIH Ganged Test Method
Vdd
PPMU
Force Voltage
Measure current
 Force Vddmax (to test for IIH) using PMU
 Program delay time of 1 to 5 ms.
 Measure resultant (total) current and compare against the test limits
 Repeat the above with by forcing Vss(IIL)
Revised 8/8/2007
Leakage Test
151
Advantages / Disadvantages
Ganged Test Method
 Advantage of this method is the test can be performed
faster and it doesn`t require per pin PMU.
 Disadvantage is that individual pin leakage current
cannot be measured.
 Both ganged and serial method can be used together. If
ganged-test fails, serial test method will then be
executed, to find the exact failing pin for leakage.
Revised 8/8/2007
Leakage Test
152
Leakage Test (Sample Datalog)
Number Site Result
150
151
152
153
154
155
156
157
158
159
160
161
0
0
0
0
0
0
0
0
0
0
0
0
FAIL
PASS
PASS
PASS
PASS
PASS
FAIL
PASS
FAIL
PASS
PASS
PASS
Test Name Pin
ppmu_loleak_p2 p23
ppmu_loleak_p2 p22
ppmu_loleak_p2 p21
ppmu_loleak_p2 p20
ppmu_loleak_ctr cs
ppmu_loleak_ctr prg
ppmu_hileak_p2 p23
ppmu_hileak_p2 p22
ppmu_hileak_p2 p21
ppmu_hileak_p2 p20
ppmu_hileak_ctr cs
ppmu_hileak_ctr prg
Channel
7
31
23
48
4
30
7
31
23
48
4
30
Low limit
Measured
-10.0000 uA -18.2912 uA
-10.0000 uA 875.1700 pA
-10.0000 uA -5.0839 nA
-10.0000 uA -5.1774 nA
-10.0000 uA 1.6501 nA
-10.0000 uA -1.2792 nA
-10.0000 uA 32.7916 uA
-10.0000 uA 10.9652 nA
-10.0000 uA 12.4392 uA
-10.0000 uA 2.3655 nA
-10.0000 uA 26.8562 nA
-10.0000 uA 18.8714 nA
High limit
10.0000 uA 0.0000 V
10.0000
Fail uA
IIL 0.0000 V
10.0000 uA 0.0000 V
10.0000 uA 0.0000 V
10.0000 uA 0.0000 V
10.0000 uA 0.0000 V
10.0000 uA 5.5000 V
Fail uA
IIH 5.5000 V
10.0000
10.0000 uA 5.5000 V
FailuA
IIH5.5000 V
10.0000
10.0000 uA 5.5000 V
10.0000 uA 5.5000 V
In the above example pin P23 is failed for both IIH and IIL
& P21 has failed for IIH current
Revised 8/8/2007
Leakage Test
Force
153
IOZL/IOZH
 IOZL is the current from high impedance output
when output is forced for logic Low.
 IOZH is the current from high impedance output
when output is forced for logic High.
Revised 8/8/2007
Leakage Test
154
What is a Tristate ?
Tristate is often called as floating or Z state. When an
output is tri-stated it looks like high impedance to another
device.
 Requires an additional control input, typically called an
Enable. The Enable controls whether the output is a LOW
or HIGH (enabled) or Tri-Stated (disabled).
Tri-state outputs are typically used where multiple outputs
share a signal or bus.
Example; data outputs on memory devices are tri-state
outputs. Control circuitry is used to ensure that only one
device is enabled at any given time (to decode logic).
Revised 8/8/2007
Leakage Test
155
Why IOZ Test ?

Measures the resistance from an output pin to
ground / VDD.

To confirm the bi-directional and high impedance
outputs are capable of achieving a high impedance
or off state.

Identify processing problems in CMOS devices.
Revised 8/8/2007
Leakage Test
156
IOZL/IOZH Serial Test Method

All output pins should be preconditioned to High
impedance state.

Use PMU to force High into all tristate pin individually
and measure the current (IOZH) and compare it with
the specification limits.

Use PMU to force Low into all tristate pins individually
and measure the current (IOZL) and compare it with
specification limits.
Revised 8/8/2007
Leakage Test
157
IOZH Serial Test Method
Vdd
D
G Off
S
S
G Off
D
Force VDDmax Voltage
Measure current
Output pin
Current Path
PMU
-IOZH
Vss
Revised 8/8/2007
Leakage Test
158
IOZL Serial Test Method
Vdd
D
G Off
S
IOZL
Current Path
Force VSS Voltage
Measure current
Output pin
S
G Off
D
PMU
Vss
Revised 8/8/2007
Leakage Test
159
IOZL/IOZH Parallel Test Method

Most Test Systems today have per Pin PMU.

Parallel measurements mean all high impedance
outputs will be driven for Low simultaneously and
measurement (IOZL) will be done.

Similarly, all high impedance pins will be driven for
High and measurement (IOZH) will be done.
Revised 8/8/2007
Leakage Test
160
Tri State Leakage Test Sample Datalog
Number Site Result
250
251
252
253
254
255
256
257
258
259
260
261
0
0
0
0
0
0
0
0
0
0
0
0
PASS
PASS
PASS
PASS
PASS
FAIL
PASS
PASS
FAIL
PASS
PASS
PASS
Test Name
Pin
Channel
Low_trileak_p2 p23
7
Low_trileak_p2 p22 31
Low_trileak_p2 p21 23
Low_trileak_p2 p20 48
Low_trileak_ctr cs
4
Low_trileak_ctr prg 30
Hi_Trileak_p2 p23
7
Hi_Trileak_p2 p22 31
Hi_Trileak_p2 p21 23
Hi_Trileak_p2 p20 48
Hi_Trileak_ctr cs
4
Hi_Trileak_ctr prg 30
Low limit
Measured
High limit
Force
-2.0000 uA -2.2912 nA
2.0000 uA 0.0000 V
-2.0000 uA -5.1700 nA
2.0000 uA 0.0000 V
-2.0000 uA -1.0839 nA
2.0000 uA 0.0000 V
-2.0000 uA -523.1774 pA 2.0000 uA 0.0000 V
-2.0000 uA 124.6501 pA 2.0000 uA 0.0000 V
-2.0000 uA -3.7916 uA
2.0000
0.0000 V
FailuA
IOZL
-2.0000 uA 3.7916 nA
2.0000 uA 5.5000 V
-2.0000 uA 10.9652 nA
2.0000 uA 5.5000 V
-2.0000 uA 4.4392 uA
2.0000 uA 5.5000 V
FailuA
IOZH
-2.0000 uA -2.3655 pA
2.0000
5.5000 V
-2.0000 uA 531.6501 pA 2.0000 uA 5.5000 V
-2.0000 uA 124.2792 pA 2.0000 uA 5.5000 V
In the above example, pin PRG failed due to tri state Low
leakage & P21 failed due to tri state High leakage
Revised 8/8/2007
Leakage Test
161
IOS Test
 IOS - Output Short Circuit Current
 This is the current produced by the output during short
circuit condition.
IOS usually specified in the devices specification.
 IOS test is used to measure the output pins steady state
impedance.
 It is the max current measured while the device output is in
logic 1(output High state) and 0 volts applied to the output.
Revised 8/8/2007
Leakage Test
162
IOS Test Method
Vdd
D
G ON
S
S
G Off
D
IOS
Output pin
@ LOGIC HIGH
Force 0.0 Volts
& Measure current
PMU
Vss
 Precondition Output pin to output logic High.
 Force 0 Volt from PMU to this pin. Add delay/wait time of 1 to 5ms
 Measure resultant current and compare against the IOS test limits .
Revised 8/8/2007
Leakage Test
163
IOS Test Method
 All the outputs of DUT should be preconditioned to logic
high.
 PMU will drive 0V and resultant current will be measured
and compared to the specification.
 This is repeated for all output pins.
 Hot switching should be avoided when performing IOS Test.
0
1
Revised 8/8/2007
Leakage Test
164
VOL/IOL
 VOL represents the maximum output voltage when the
output is low.
 IOL represents the maximum sinking current capability
when the output is in low state
Revised 8/8/2007
165
Why VOL/IOL Test ?
 Measures the resistance of an output pin when the
logic is 0.
 Insures that output will provide IOL without
exceeding the VOL voltage.
 Device output pin must sink at least the specified
current and stay in correct logic state.
Revised 8/8/2007
166
VOL/IOL
Input Logic 0
Output Logic 0
Logic 1
Load
Gate
Rout
VOL
Rin
Load
Load
LoadGate
Gate
Gate
IIL
Logic 1
IOL
+VCC
VIL
Current Sinking
Revised 8/8/2007
167
Test Method for VOL/IOL
 Device output pins are preconditioned for logic low state.
 PMU is connected to pin under test and IOL current is
injected and the resultant voltage is measured and
compared with the specification.
 Typical specification
VOL @vddmin = 0.4 V @ IOL = 8.0 ma
Revised 8/8/2007
168
Test Method for VOL/IOL
Vdd
G DOff
S
G SON
Output pin
@ Logic LOW
IOL
PMU
Force IOL max current
& Measure VOL voltage
D
Vss
Vdd minimum is the worst case for this test.
Revised 8/8/2007
169
VOH/IOH

VOH represents the minimum output voltage when
the output is high.

IOH represents the maximum sourcing current
capability when the output is in high state.
Revised 8/8/2007
170
Why VOH/IOH Test ?

Measures the resistance of an output pin when the
logic is 1.

Insures that output will provide IOH without
exceeding the VOH limit.

Device output pins must source at least the
specified current and stay in correct logic state.
Revised 8/8/2007
171
VOH/IOH
+VCC
Logic 0
Logic 0
Rout
Driving
Gate
IOH
Input Logic 1
IIH
VOH
VIH
Rin
Load
Load
Gate
Load
Gate
Gate
Output Logic 1
Current Sourcing
Revised 8/8/2007
172
Test Method for VOH/IOH
 Device output pins are preconditioned for logic high
state.
 PMU is connected to pin under test and IOH current
is injected and the resultant voltage is measured and
compared with the specification.
 Typical specification
VOH @vddmin = 2.4 V @ IOH = - 5.0 ma
Revised 8/8/2007
173
Test Method for VOH/IOH
Vdd
G DON
S
G SOff
IOH
Output pin
@ LOGIC
HIGH
PMU
Force IOH max current
& Measure VOH voltage
D
Vss
Vdd minimum is the worst case for this test.
Revised 8/8/2007
174
Output Fanout
 The fanout of a logic gate is the number of inputs
that the gate can drive without exceeding its worstcase loading specifications.
 CMOS devices fanout is mostly depending on the
speed we operate as it is high input impedance
device.
Revised 8/8/2007
175
Output Fanout
Fanout must be examined for both possible output states.
• IOLMAX
The maximum current that the output can sink in the LOW
state while still maintaining an output voltage no greater
then VOLMAX.
• IOHMAX
The maximum current that the output can source in the
HIGH state while still maintaining an output voltage no less
then VOHMIN.
Revised 8/8/2007
176
ATE DC SUBSYSTEM
VOLTAGE/CURRENT (VI) SOURCE
To generalize DC testing, 2 configurations exist:
If ( stimulus )
Voltmeter
1. FORCE I, MEASURE V
DUT
Vf ( response )
ammeter
2. FORCE V, MEASURE I
Current
source
Ir ( response )
Voltage
source
Vr
( stimulus )
Revised 8/8/2007
DUT
177
VOLTAGE/CURRENT (VI) SOURCE
The 2 configurations of DC tests calls for a DC source capable of
both modes, the Voltage/Current source or VI source.
A generalized form of the VI source in Force V measure I mode:
Force Voltage
Measure Current
force voltage
Vstimulus
V
A
meas
current
DC Measurement
system
Revised 8/8/2007
Imeasure
DUT
178
VOLTAGE/CURRENT (VI) SOURCE
A generalized form of the VI source in Force I measure V mode:
Force Current
Measure Voltage
force current
A
meas
current
DC Measurement
system
V
Vmeasure
DUT
Istimulus
Revised 8/8/2007
179
KELVIN CONNECTION CONCEPT
Inaccuracy of actual voltage delivered across the DUT arise due to inherent
resistance in the connection between the voltage source and the DUT:
Total resistance= r
A
meas
current
DC Measurement
V system
I
Vdut= Vstimulus - Ir
DUT
Vstimulus
Revised 8/8/2007
180
KELVIN CONNECTION CONCEPT
Vdut error is not very apparent for low currents:
Total resistance= 1 ohm
A
meas
current
DC Measurement
V system
Vstimulus
=10v
I=1mA
Vdut= Vstimulus – Ir
= 10 – 1mV
= 9.999V
Or 0.01% error
Revised 8/8/2007
181
KELVIN CONNECTION CONCEPT
Vdut error IS apparent for higher currents:
Total resistance= 1 ohm
A
meas
current
DC Measurement
V system
Vstimulus
=10v
I=1A
Vdut= Vstimulus – Ir
= 10 – 1V
= 9.0V
Or 10% error !
Revised 8/8/2007
182
KELVIN CONNECTION CONCEPT
Ir error is eliminated by employing a separate conductor that provides
feedback to the voltage source‟s error nulling circuitry.
This feedback conductor is called the SENSE line:
SENSE
A
meas
current
DC Measurement
V system
Vadjusted
=Vstimulus
+Ir
Revised 8/8/2007
I=1A
Vdut = Vadjusted – Ir
= Vstimulus
183
KELVIN CONNECTION CONCEPT
The FORCE line is the current carrying line.The SENSE line does NOT
carry current as it feeds-back into a high impedance junction (OpAmp
input). The SENSE and FORCE lines are separate and meet ONLY at the
DUT pin. This is called the KELVIN CONTACT point.
SENSE
I=0
KELVIN
CONTACT
Ir drop
A
meas
current
DC Measurement
V system
Vadjusted
=Vstimulus
+Ir
Revised 8/8/2007
FORCE
Vdut = Vadjusted – Ir
= Vstimulus
184
KELVIN CONNECTION CONCEPT
It is very important that the KELVIN CONTACT point is as close to the
DUT leads as possible to ensure accuracy of required voltage across
the DUT:
KELVIN
CONTACT
Ir drop
A
meas
current
I=1A
IR drop
Vk= Vstimulus =Vdut+IR
Vadjusted
=Vstimulus
+Ir
V
Vdut = Vstimulus – IR
Vdut
IR= Error term !
Revised 8/8/2007
185
KELVIN CONNECTION CONCEPT
The KELVIN connection is also required for FORCE I, MEASURE V
configuration. The Voltmeter measures the SENSE line since it
carries virtually no current. Again, the KELVIN CONTACT point must
be closest to the DUT for accuracy.
SENSE
A
meas
current
FORCE
Vvm = Vdut
V
Vdut
Istimulus
Revised 8/8/2007
186
GUARD CONCEPT
When measuring currents in the micro or nano amp range, the measured
current, Im will include leakage due to leaky currents thru the cable‟s
dielectric to the grounded shield.The dielectric is only a few megaohms.
Ileak
Outer Grounded shield
A
meas
current
V
Vstimulus
Im = Idut + Ileak
Im
Idut
Error term = Ileak
Revised 8/8/2007
187
GUARD CONCEPT
The guard is a floating conductor that surrounds the Force and Sense leads
and is driven by the sense voltage.The Ileak is now contributed by the sense
buffer instead of the VI source.Im will be only Idut.
Outer Grounded shield
Ileak
Guard conductor driven to Vstimulus
by sense buffer.
Sense Buffer
A
meas
current
V
Vstimulus
Revised 8/8/2007
Im = Idut
Im
Idut
Ileak is supplied by the sense buffer
188
VOLTAGE/CURRENT (VI) SOURCE
The Voltage Source: The intercept point between the load line and the VI
Operating line is the operating point of the VI.
I
DUT I/V Characteristics
+High clamp
V/I OPERATING POINT
+Vset
-V
V
-Low clamp
-IRevised 8/8/2007
189
VOLTAGE/CURRENT (VI) SOURCE
The Voltage Source: The VI source can operate in negative Voltage and
negative current mode as well.
I
+High clamp
DUT I/V Characteristics
-V -Vset
V/I OPERATING POINT
V
-Low clamp
-IRevised 8/8/2007
190
VOLTAGE/CURRENT (VI) SOURCE
The Voltage Source: What if the operating point is over the I clamp?
I
V/I OPERATING POINT
+High clamp
+Vprog
-V
V
-Low clamp
Revised 8/8/2007
-I
191
VOLTAGE/CURRENT (VI) SOURCE
The Voltage Source: ALARM in force V mode.
I
+High clamp
ALARM or
OVERLOAD
condition
+Vset
-V
V
-Low clamp
-IRevised 8/8/2007
192
VOLTAGE/CURRENT (VI) SOURCE
The Current Source: The operating point in force I mode.
I
V/I OPERATING POINT
DUT I/V Characteristics
+Iset
-V
-Vset
+Vset
Revised 8/8/2007
-I
V
193
VOLTAGE/CURRENT (VI) SOURCE
The Current Source: Opposite polarity current forcing mode is supported
by the VI source. Current flowing into the source is called sink current.
I
DUT I/V Characteristics
+Vset
-Vset
-V
V
V/I OPERATING POINT
-Iset
Revised 8/8/2007
-I
194
VOLTAGE/CURRENT (VI) SOURCE
The Current Source: What happens when, in force I mode, the operating
point is above Vset?
I
DUT I/V Characteristics
+Iset
-V
-Vset
+Vset
Revised 8/8/2007
-I
V
195
VOLTAGE/CURRENT (VI) SOURCE
The Current Source: ALARM in force I mode.
I
ALARM condition
+Iset
Voltage clamped to Vset
ALARM
-V
-Vset
+Vset
Revised 8/8/2007
-I
V
196
PMU – Parametric Measurement Unit
Some ATE system have a System PMU which allows connection to other
instruments within the system for the purpose of DC measurement
(current/voltage measurement).
The PMU can operate in either Force-Current-Measure-Voltage or
Force-Voltage-Measure-Current modes.
This enables a DC measurement to be performed on your device pins
even if these pins are physically assigned to Digital Pin Electronics or
other Analog instruments.
In addition to this system PMU, some ATE have built-in individual „PMU‟
on each of their Digital Pin Electronics Channel (called PPMU – Pin
Parametric Measurement Unit). In such case, typically the System PMU
would have better current/voltage ranges, while the PPMU has lesser
current/voltage capabilities.
Revised 8/8/2007
197
PPMU – Pin Parametric Measurement Unit
Today PPMU is a common feature in most ATE, that some newer ATE
even comes without the System PMU.
The availability of PPMU enables DC measurement to be done in
parallel for each of this Digital Channel if needed. This PPMU is now
commonly used for performing tests such as Continuity and Leakage.
Pin Parametric Measurement Unit
Revised 8/8/2007
198
DC METER
The Sample and Difference part measures delta voltages that are
very close. If an attempt is made to get the difference between 2
measured voltages at 5.000v and 5.001v in the 20V range, we
cannot get better than the resolution of 2.5mV! For this type of
measurements we use the SAD:
Isense
Sample and
difference
VI sources
(Vsense)
Normal
Inputs
(meas V)
ADC
MUX
Revised 8/8/2007
Data
out to
CPU
bus
199
DC METER
The structure of the SAD is shown below. The Csamp
Samples the first voltage from the dut, V1.The SAD output is at 0V since
The OpAmp‟s input is grounded to charge up Csamp:
V1
0 VOLTS
Csamp
SAMPLE
DIFF
XGAIN
Revised 8/8/2007
200
DC METER
The SAD is switched to DIFF mode and then V2 is applied at
The input.This subtracts from the stored voltage in Csamp to a
resultant of V2-V1:
V2
(V2-V1)xGAIN
VOLTS
Csamp
SAMPLE
DIFF
XGAIN
Revised 8/8/2007
201
DC METER
Consider now using this circuit to measure the difference of the
5.000V and 5.001V mentioned earlier:
V1
=5.000V
0 VOLTS
Csamp
SAMPLE
DIFF
XGAIN=100
Revised 8/8/2007
202
DC METER
The output is gained X100 and goes to the +/-10.24V ADC.
The resolution of measurement now is 1.25mV/100 = 12.5uV which is
much more acceptable for a 1mV difference.:
V2
=5.001V
0.001x100
= 0.1V
Csamp
SAMPLE
DIFF
XGAIN
=100
Revised 8/8/2007
203
DC MATRIX
Here is a general purpose 5X6 matrix. Every instrument can be connected
to any pin which hardwire to the Device Interface Board (DIB). Each
relay and line actually represent the Force,Sense and Guard
connections.
DIB connections
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
VI SOURCE 1
VI SOURCE 2
VI SOURCE 3
VI SOURCE 4
VI SOURCE 5
VOLTMETER
Revised 8/8/2007
204
RELAYS AND RELAY CONTROL BIT
It is often necessary to configure the DUT differently for different
tests.This is typically achieved by mechanical relays.
Relay K1 used to connect/disconnect Rload: OFF
OUTPUT
Relay K1
Rload
Revised 8/8/2007
205
RELAYS AND RELAY CONTROL BIT
Relay K1 used to connect/disconnect Rload: ON
OUTPUT
Relay K1
Rload
Revised 8/8/2007
206
RELAYS AND RELAY CONTROL BIT
The mechanical relay consists of a coil and a switch. The coil need to be
energized for the switch to throw. The coil is energized by a current
flow at the level of the relay‟s specification.
OFF
Relay coil
ENERGIZED
COIL
ON
I
Revised 8/8/2007
207
RELAYS AND RELAY CONTROL BIT
Most ATE have multiple relay control bits that work to energize and
de-energize relays‟ coils.
+12V
OFF
Relay control bit
Control line
Revised 8/8/2007
208
RELAYS AND RELAY CONTROL BIT
A diode is typically connected across the relay coil to minimize the
effects of “kick-back” voltage or back emf when the current through
the coil rises and falls rapidly. This back emf will try to sustain the
current.
+12V
Fly-back diode
OFF
Control line
Revised 8/8/2007
Relay control bit
209
HOT-SWITCHING !!
THE FOLLOWING SEQUENCE ILLUSTRATES HOT-SWITCHING OF
RELAYS.
VI Source
Von
Arcing at contacts
degrades the contact
resistance.
Relay’s life span is
greatly reduced.
Load
VI Source
Load
Von
Revised 8/8/2007
VI Source
Load
210
HOT-SWITCHING !!
THE FOLLOWING SEQUENCE ELIMINATES HOT-SWITCHING.
VI Source
VI source turned on
after switching the
relay, eliminating hotswitching.
Load
VI Source
Load
Von
Revised 8/8/2007
VI Source
Load
211
Self-Assess Questions
1. Which of the following tests you cannot perform with a PMU only?
VOL, VOH, IIL, IOZL, IIH, IOL, VIH
2. Which of this is a common Force-Current-Measure-Voltage Test?
Continuity, Leakage, IDD, VOL, IOZH
3. Let say you use a VI Source in Force Voltage mode, and Alarm is
encountered due to preset clamp being violated. What is exceeding
the allowed limit (clamp), voltage or current?
4. For a VI Source, typically you have a Force, Sense and Guard line. The
Force and Sense line meet at a point as close to the DUT as possible.
What is the main difference between Force and Sense line?
5. For Continuity test, the pin under test is forced a small current and the
resultant voltage is measured. What do you do with the rest of the
device pins during this?
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212
DIGITAL FUNCTIONAL Test
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213
Introduction

To verify that the DUT will correctly perform its intended logical
functions, test vectors or truth tables must be created which can detect
faults within the DUT.

The ability of truth table to detect faults can be measured and is
referred to as fault coverage.

The test pattern (test vectors) combined with test timing, levels and
loading currents is called as a functional test.
Input
Output
= Test Vector + Levels + Test timing + Signal Format.
= Test Vector + Levels + Output Test timing
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Functional Testing Block Diagram
Pattern Data
• Microcodes
• Input states
• I/O control
• Tset
• Output
states
• Output
masking
I/O Timing and
Formatting Controls
Input timing,
formats and
I/O controls
Formatted
I/p data
I/p timing,
format data
Tset control
O/p strobe
timing data
Output
control and
strobe
timing
Pin Electronics
Driver
• Vih
• Vil
DUT
Comparator
•Voh
•Vol
Dynamic
load
•Ioh
•Iol
•Vref
Functional Test Results
PASS/FAIL
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215
Pin Electronics
VDriveHi(VIH)
Drive Hi/Lo
VDriveLo (VIL)
Drive On/Off
Vch
VCompareHi(VOH)
DUT
high
Strobe On/Off
low
Vcl
to / from
Digital
PMU
To
DUT
VCompareLo(VOL)
Isource(IOL)
Subsystem
VThreshold
Isink(IOH)
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Pin Electronics
Pin Electronics is otherwise called as Channel card .
 It is the interface between the digital subsystem and the DUT.
 It contains the following circuitries

Drivers to drive the inputs to the device.

Switching circuits to the drivers On and OFF

Comparators to detect and compare the output levels

Programmable current loads to act as a load to the DUT outputs

Used as a connection point to a PMU
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Test Concepts
Digital Functional Test
 The signal definition of a digital test needs to define all of
the parameters required to generate the stimulus and
response required by the DUT.
 This means more than just defining the sequence of logic1's and logic-0's necessary to test a digital DUT. It is also
necessary to include detailed timing and voltage level
information.
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Test Concepts
A Functional Test consists of below:
1. Pattern
Vectors that contain the drive and compare data
2. Timing
Timesets with Edgesets to provide format, drive and
compare edge timing
3. Levels
For signal pin drive and compare levels, and for the
device power pin
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Test Concepts
Functional Test
Test pattern
Timings
Levels
Tsets
Period
1/F
Formats
Pin levels
Edges
Timings
Drive
levels
Drive &
Compare
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Functional Test
Compare
level
DUT
power
Output
Loading
current
220
Test Concepts
Test pattern
Patterns
 The patterns contain the logic values that are required to
test the DUT.
 The pattern data must be combined with the timing
information to create the correct stimulus and measure the
correct response at the DUT .
 Each logic state needs to be able to indicate if the logic
applies to stimulus or response.
 The pattern values need to include not only logic 1 and 0
data but also High(H), Low(L), Tri-state(Z) and “don‟t care”
(X) for outputs.
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Test Concepts
Timings
Timings
 Pattern supplies a list of logic to be driven-to, or comparedfrom the DUT.
 The timing information indicates when these happen
(Drive/Compare)
 The digital functional test data must explicitly state WHEN
every edge should occur.
 Timesets (Tsets) will have the details of the period (cycle).
 Edgesets (Esets) will indicate format and the timing details of
the edge placements for the drive and compare data .
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Test Concepts
levels
Levels
 The third parameter is the voltage and the currents values
assigned to the logic values in the pattern data .
 These levels may be different for different pins on the DUT.
 Levels include the input voltages for the Logic inputs data
(Login 1 & Logic 0) in the pattern and the output levels
(Logic H & Logic L) and the thresholds response data.
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Test Concepts
Example of Logic Inverter
VCC
Data output
Data input


Input data is defined as a 1 or 0
Output data is defined as an H or L
TRUTH TABLE
Input Output
1
0
L
H
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Functional Truth Table
A
C
B
Truth Table
AND Gate
T0
A
B
0
0
T0
T0
0
1
1
Input Input Output
T0
VIH
1
0
VIL
1
VOH
C
L
L
L
Timing Diagram
H
VOL
A
0
0
1
1
Timing8/8/2007
Format = NRZ
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Functional Test
B
0
1
0
1
C
L
L
L
H
225
Test Concepts
Defining the Operation of a DUT with a Truth Table
Example: AND GATE
IN1
IN2
OUTPUT
Vector 1
0
0
L
Vector 2
0
1
L
Vector 3
1
0
L
Vector 4
1
1
H
Where
• The 1s and 0s are the data.
• A line of 1s and 0s is called a vector.
• The vectors and, therefore, the data are part of what is called the
pattern.
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Test Concepts
Definitions : Voltages
VCC
VIH
Data input
Data output
VOH
VOL
VIL
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Test Concepts
Definitions: Currents
VCC
ICC
IIH
IOL
IIL
IOH
ICC is supply current.
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228
Important Parameters
Important Parameters check during a functional test
VDD Min/Max
VIL/VIH
VOL/VOH
IOL/IOH
:DUT Power Levels
:Input Levels
:Output Levels
:Output Current Loading
Test Frequency
Input Vector
Vector Sequencer
:Cycle Time Used For Test
:Wave Shape Of Input Signal
:Start Or Stop Point Of Signal
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Important Parameters
 Input Signal Timings :
Clocks / Setups /Holds / Controls
 Output Signal Timings:
Output strobe - When Will Output Sampled
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Test Concepts
What is Digital Functional Testing?
Digital Functional Testing is to:
1.
Define input waveforms per DUT requirements; and
2.
Check output waveforms against expected data of
DUT
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Test Concepts
Input Waveform
Input Waveform = Data + Waveshape + Timing +Levels
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Test Concepts
Output Waveform
Output Waveform = Data + Timing + Levels
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Input signal
Input signal waveform is created by
Test Vector Data (Logic Data to DUT)
Input Signal Timing (Edge Placement Points)
Input Wave Shapes (Signal Format )
Input Voltage Levels (VIH/VIL)
Time Set Selection (Vector Frequency)
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Signal Formats
 Signal formats,when combined with vector data,edge
placements and input levels,define the wave shape of
input signals to the DUT.
 Signal format is used to generate proper signal that
required to correctly control any digital logic circuit.
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Types of Signal Formats
NRZ : Non Return to Zero
RZ : Return to Zero
RO : Return to One
SBC : Surround by Compliment
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Timing Edges
•These are signal timings to control drive and compare
circuit of the Pin Electronics
 D0 or Drive On
 D1 or Drive Data
 D2 or Drive Return
 D3 or Drive Off
-
Start of cycle for each channel
Start of drive pulse for each channel
End of drive pulse for each channel
Time of I/O switch
 R0 or Compare Start (On)
- Start of compare window for each channel (window strobe)
 R1 or Compare End (Off)
- End of compare window for each channel (window strobe) or
edge strobe
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Types of Signal Formats
Non Return to Zero
DATA
Logic 0
DATA
Logic 1
VOH
Z STATE
VOL
T0
T0
 NRZ represents the actual data stored in vector memory and
contains no edge timing.
 NRZ data changes only at the beginning of each cycle.
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Types of Signal Formats
Return to Zero
DATA
Logic 0
DATA
Logic 1
VOH
Z STATE
VOL
T0
T0
 RZ provides a positive pulse when vector data is logic1 and no
pulse when vector data is logic 0.
 This signal format can provide a positive clock when all vector
data for the pin is logic 1.
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Types of Signal Formats
Return to One
DATA
Logic 0
DATA
Logic 1
VOH
Z STATE
VOL
T0
T0
 RO provides a negative pulse when vector data is logic 0 and
no pulse when vector data is logic 1(the signal remain in
logic1).
 This format can provide a negative clock when all vector data
for the pin is logic 0.
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Types of Signal Formats
Surround By Compliment
DATA
Logic 0
DATA
Logic 1
VOH
Z STATE
VOL
T0
T0
 In the SBC format, data is inverted at the start of the cycle,
waits a pre-defined “delay”, presents the actual vector data for
the specified pulse width, then inverts the data again for the
remainder of the cycle.
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How Input Signal is generated ?
 Input data from vector memory is combined with timing, format
and voltage level and supplies to DUT via pin electronics.
Vector Data
Timing Edge Placement
Input Levels
Formatting
VIH =2.8
RZ
101
Data 1
DUT
VIL = 0.8
Data 1
Data 0
Vector Data
Edge Timing
Input waveform
RZ Format
T0
T0
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242
Outputs are Tested By
Output signal waveform comprises of
Test Vector Data(Expected State)
Output Strobe Timing (Window strobe, or Edge strobe)
Output levels - VOL/VOH
Output currents - IOL/IOH(Output Loading current)
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Output Signal Testing
Functional Comparator
Strobe Timing
Vector Data
O/P Signal
VOH
DUT
HLH
Strobe Output Here
VOL
Vector Data
Window Strobe Timing
L
H
DUT Output
T0
T0
H
T0
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T0
244
Output Signal Testing
 Output data from DUT monitored via comparator circuit
available in pin electronics, and compared with vector
memory data at the defined strobe time.
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245
How Outputs Tested ?
Vddmax
PASS
VOH LEVEL
LOGIC HIGH (H )
2.4V
FAIL
VOL LEVEL
0.4V
PASS
LOGIC ZERO ( L)
0.0V
Comparator outputs
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Output Test – Strobes
There are two types of strobe markers available for testing the
Logic state of the outputs and determine the PASS or FAIL result.
 Edge strobe
 Window strobe
VOH
Edge strobe
Edge strobe checks for the output logic state at a single point in time .
Strobe timings are programmed relative to the T0
Window strobe
Window strobe checks for the output logic state during the entire
width of the window timing.
Window strobe testing are sensitive for output signals with noise.
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Output Test – Edge Strobe
A
C
B
T0
T0
T0
T0
AND Gate
A
0
1
0
VIH
1
VIL
B
0
C
L
0
PASS
1
1
VOH
L
L
H
VOL
Actual output
waveform
Timing Diagram
Timing Format = NRZ
EDGE STROBING
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Output Test – Window Strobe
A
C
B
T0
T0
T0
T0
AND Gate
A
B
0
1
0
VIH
1
VIL
0
0
FAIL
1
1
H
VOH
C
L
L
L
VOL
Actual output
waveform
Timing Diagram
Timing Format = NRZ
WINDOW STROBING
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249
Current Loading
• Programmable current loads are used to apply proper
IOL/IOH.This helps to measure the DUT‟s sinking and
sourcing capacity.
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250
How Functional Test Works ?
 The Digital subsystem supplies data to the input pins of
DUT and monitors its output pins on a cycle by cycle,pin by
pin basis.
 If any output pin fails to meet the expected logic
state,voltage or timing within the user set tolerance level,
the result of the functional test is a failure.
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251
Sequence of Operation
Define VDD level
Define input,output levels(VIL/VIH/VOL/VOH)
Define output Current Loading(IOL/IOH)
Define Test Cycle Time (Frequency)
Define timings and formats for all input pins
Define output strobe timing for all output pins
Define start and stop locations for memory
Execute the test
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252
Test Concepts
 There are two methods used to functionally verify
device specifications:
1. Gross functional test
2. Standard functional test
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253
Gross Functional Test
 Gross functional test or wiggle test performs a functional
test with relaxed conditions.
 Frequency, timings, voltages and current loading are
generally relaxed.
 This test indicates whether or not the DUT is functionally
„alive‟.
 It is often executed early in the test program flow and is
used to verify correct functionality of all test vectors which
will be throughout the entire test program.
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254
Standard Functional Test
 Standard functional test is used to functionally verify a
given parameter.
 Each unique circuit design requires an unique set of
functional test conditions.
 These tests may be executed at different VDD levels,
VDDmin, VDDmax, VDDnom levels specified in the data
sheet
 Most of the tests are done at the maximum operating
frequency of the device .
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255
Test Concepts
Input Stimulus:– Pattern data per DUT input requirements
Expected Response:– Pattern data per DUT output requirements
Test Condition(s):– Required power supply voltage setting as defined in
datasheets
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256
VIL/VIH Functional Test
 VIL is the max-voltage applied to an input to represent logic
0, while VIH is the min-voltage to represent logic 1
 VIL/VIH test guarantees that the input pins can correctly
sense/differentiate the proper logic levels
 This test is performed by applying the specification-defined
input levels, and then executing a functional pattern.
Parameter
Description
VIH
I/P High
voltage
VIL
I/P Low
voltage
Test
conditions
Min
Max
2.2
V
0.8
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Units
V
257
VIL/VIH Level Test
Set the input levels as per the spec
Execute the functional test relaxing all the other parameters and frequency.
Output levels also need to be relaxed
Functional pattern outputs will fail if the input level does meet the specification
Test can be executed at VDDmax and VDDmin
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258
VIL/VIH Troubleshooting
 Relax VIL values towards 0 and VIH values towards
VDD and try different permutation combinations
 It may be necessary to eliminate all output loading
and to reduce the test frequency and test it in a noise
free environment.
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VIL/VIH Key points…
 Purpose:To verify that the input buffers will properly
detect VIL,VIH voltage levels
 VIL,VIH can only be verified by executing a dynamic
functional test
 Test limits are defined in device specification (often
as DC spec)
 Output pins fails as a result of improper operation of
input circuitry
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260
VOL/IOL, VOH/IOH Testing
 VOL/IOL ,VOH/IOH test guarantees that the output pins
can correctly maintain their Output logic level at the
specified sink/source current.
 During functional test execution, output pins are loaded
(apply IOL/IOH) to check their sink/source capacity. The
resultant voltage is compared to the set VOL/VOH
Parameter
Description Test
conditions
Min
VOH
O/P High
voltage
2.4
VOL
O/P Low
voltage
Max Units
V
0.4
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V
261
Functional VOL/VOH Test
Vdd
VCompareHi(VOH)
G D
S
high
IOH
low
VCompareLo(VOL)
G S
(IOL)
IOL
D
Vref
Vss
(IOH)
Set the VOL/VOH, IOL/IOH to the specification‟s values
Execute the functional pattern, and check the outputs
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262
VOL/IOL, VOH/IOH Troubleshooting
 With the help of datalog identify the device pin tat
failed and the failing state. Relax the VOL/VOH levels.
IOL/IOH levels can also be relaxed to make the
device pass
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263
VOL/VOH Key Points…
 Purpose is to verify that the output buffers will properly
supply the correct amount of output current and
voltages
 Dynamic functional test is executed
 Test limits are defined as in device specification
 Test requires current load on output pins
 It may not be possible to test all output pins
simultaneously when fully loaded, due to noise
produced by high currents
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264
Test Vectors
 Test vectors represents the input and output states
which represents the logical functions that the DUT
has to perform.
 Input data are represented by character 0 / 1.
 Test vectors are called as test patterns or truth tables.
 Output data are represented by L / H / Z and X.
 Test vectors are stored in Vector memory
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265
Test Vectors
 Input data from vector memory is combined with timing, format
and voltage level and supplies to DUT via pin electronics.
 Output data from DUT monitored via comparator circuit available
in pin electronics, and compared with vector memory data at the
defined strobe time. This type of testing is called stored
response
 In addition to DUT data, instructions to the test systems are also
available in test vector sequence.
 Timing settings and signal formats may change on a vector by
vector basis.
 Most ATE systems support microcode instructions to perform
looping, jumping and subroutines etc.
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266
Sample Vector File
// Functional Patterns
import tset time_ANDPattern;
vector ($tset, A,B,C)
{
global func_start_ANDPattern:
>time_pattern
>
>
>
-
00L
01L
10L
11H
;
;
;
;
Func_stop_ANDPattern: halt
}
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267
Roles in Creating Vectors
 Design engineer will be most familiar with functions of
device and mostly responsible for vector generation also.
 Test engineer has to discuss with designer about the
detail of testing, review of timing and voltage
requirements and discuss about the length/depth of test
vector.
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268
Roles in Creating Vectors
 Test vectors for complex devices are typically extracted
from simulation data created during the design process.
 These are typically created by design/test/simulation
engineer with the help of simulation tools
 Simulation data may need to be reformatted for use on
test system.
 Using macros, engineer should try to automate the test
vector generation rather than manual.
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269
Tester Memory
 Test Vectors are stored in Vector/Pattern Memory.
 The size of the test vector memory determines the
number of vectors that can be executed at any one time.
 If the memory is small, Test Vectors need to be reloaded
many times - increase the overall test time.
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270
Self-Assess Questions
1. Name at least 3 Digital Input Signal Format
2. How many timing edges do you need if you want to do a window strobe?
3. Which of the below refer to inputs on your test vectors?
1, 0, H, L, Z
4. When an engineer says the vector frequency is 30MHz. You would expect
this value defined in Timeset or Edgeset? What is the period then?
5. In Digital Functional Testing, input stimulus, and output compare is
performed by the Digital Subsystem. These will in turn control the
levels and timing affecting the test. What is another aspect that will
affect the Functional Testing other than Levels and Timings?
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271
AC PARAMETERS TEST
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272
Purpose / Why
The purpose of the AC Parameters test is to guarantee that
the device meets all its timing specification specified in
the device datasheet.
The AC Timing Test verifies the following timing parameters:
1. Period, Frequency, Rise Time, Fall Time, Setup time,
Hold time, Pulse Width, Propagation Delay, etc
2. These parameters are tested under recommended
conditions listed by the Datasheet and compared against
the Datasheet values.
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273
Test Method
AC Parameters can be verified functionally.
For high speed devices, AC timing parameters can be set to
their worst case conditions and a functional test executed .
This Go/No-Go test, is a faster, and usually used in
production testing, to check that the device meets the design
specification.
To measure the operating limits of the AC parameters,
Characterization methods can be used
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274
AC Timing Parameters
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275
Setup Time
Setup Time
The time needed by the signal/data to remain stable before the clock is
triggered in order to guarantee proper output data
3.5V
0.3V
Clock
Ts
3.5V
Data
•
V in
0.3V
Performed only on input pins
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276
Hold Time
Hold Time
The time needed by the signal/data to remain stable after the clock is
triggered in order to guarantee proper output data
3.5V
0.3V
Clock
Th
3.5V
V in
•
0.3V
Performed only on input pins
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Propagation Delay
Propagation Delay
Propagation delay time is the amount of time that it takes for a change in an input
signal to produce a change in the output signal measured at a specific voltage level.
Input
V in
Tp
Output
•
V out
Propagation delay measurements are made from an input pin to an
output pin.
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278
Transition Time
The time that the output logic take to change from one
state to another is called transition time.
Transition time has two components…
 Rise time (tr)
 Fall time (tf)
The rise and fall times of CMOS outputs depend on the resistance of
the “on” transistor and the load capacitance.
The load capacitance comes from…
• Input capacitance of load device
• Wire connecting the output to its inputs
• Board capacitance.
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279
Transition Time
Rise Time
The time required for an edge to go from (typically) 10% to 90% of
its high limit voltage value
Fall Time
The time required for an edge to go from (typically) 90% to 10% of
its low limit voltage value
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280
Transition Time
Rise Time / Fall Time
Ideal
Realistic
tf
tr
High
Vih min
Actual
Vil max
Low
tf
tr
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281
Rise Time / Fall Time
Vt
Voh
90%
90%
½(Vol+Voh)
50%
10%
10%
Vol
t
Tf
Tr
Vt
Voh
Tphl
Tplh
90%
½(Vol+Voh)
Vol
50%
10%
t
Tthl
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Ttlh
282
Maximum Frequency
Max Frequency
The maximum operating frequency is usually the inverse of the sum of
the minimum clock low and clock high times
T L = 5ns
Clock
T H= 5ns
Freq = 100 MHz
•
It guarantee the maximum device operating frequency.
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283
Output Enable Time
Output Enable time
Output enable time is the time it takes an output to switch from high
impedance state to driving valid logic levels.
ENABLE
TE
V out
•
DATA
Z state
Z state
This test is done on high impedance outputs and bi-directional
device pins.
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284
Output Disable Time
Output Disable time
Output disable time is the time it takes an output to switch from
driving valid logic level to a high impedance state.
ENABLE
TD
Z state
V out
•
DATA
Z state
This test is done on high impedance outputs and bi-directional
device pins.
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285
AC Specification – Data sheet
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286
TIME MEASUREMENT SUBSYSTEM (TMS)
Vth1
ZIN
ACTIVE LO
COUNTER
SLOPE
DET
OR
Vth2
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287
TMS OPERATION
(RiseTime/SlewRate)
Vth1
HI
Vlo
ZIN
ACTIVE LO
COUNTER
SLOPE
DET
OR
LO
+VE
Vth2
Revised 8/8/2007
288
TMS OPERATION
(RiseTime/SlewRate)
Vth1
LO
Vth1
Vlo
ZIN
ACTIVE LO
COUNTER
SLOPE
DET
OR
LO
+VE
Vth2
Revised 8/8/2007
START
TIMER
289
TMS OPERATION
(RiseTime/SlewRate)
Vth1
Vth2
LO
Vth1
Vlo
ZIN
ACTIVE LO
COUNTER
SLOPE
DET
OR
HI
+VE
Tslew
Vth2
Revised 8/8/2007
START
TIMER
STOP
TIMER
290
TMS OPERATION
(Propagation Delay)
High amplitude fast edge at input of OpAmp drives the OpAmp to slew
limiting. In this condition, the response is a linear rise in voltage.
IN
OUT
tprop
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291
TMS OPERATION (2-channel TMS)
(Propagation Delay)
Vth1
Vth1
ZIN
CH1
SLOPE
DET
ACTIVE LO
COUNTER
OR
Vth2
ZIN
SLOPE
DET
CH2
Vth2
Revised 8/8/2007
292
PATTERN DATA SEQUENCER
SOURCE
MEM
PATTERN
MEM
CAPTURE
MEM
USER CPU
TIMING AND
FORMATTING
TESTER
CPU
+ DSP
PROC
CLOCKS +
SYNC
DC
METER
V/I
SOURCES
DUT
RELAY MATRIX AND
OTHER CONNECTION
PATHS TO DUT
TIME MEAS
SUB-SYSTEM
VOLTMETER
AC DIG
AC SRC
Revised 8/8/2007
293
TIMING CALIBRATION
PATH SKEW / DE-SKEW
Tprop
Tdutin
IN
OUT
Td1
Tstart = Tdutin + Td1
Td2
Tstart
Tstop
Tstop = Tdutin +Tprop + Td2
TMS
Time interval = Tstop – Tstart
= (Tdutin + Tprop +Td2) – (Tdutin + Td1)
= Tprop + (Td2 – Td1)
Skew = Td2 – Td1
Revised 8/8/2007
294
PATH SKEW / DE-SKEW
Measure
path delay
by calibration
Td1
Td2
Tstart
Tstop
TMS
Measure path
delay by calibration
From cal data
Tprop + (Td2 – Td1)
Path de-skew is done by measuring Td1 and Td2 or Td2-Td1 via tester calibration if the
paths are tester internal paths. If the paths are user designed paths (DIB traces), then
either a TDR (if these are HSD paths) is done to get Td1 and Td2, or the traces are
Revisedso
8/8/2007
designed to match in exact dimensions,
as to make Td1=Td2.
295
PATH DELAY (TDR calibration)
Tpd
DUT
Zo = 50 ohm
Zs = 50 ohm
Zl = 50 ohm
There is a finite time between an edge occuring at the driver in the channel
card, and at the DUT. It takes Tpd time for the edge above to reach the DUT.
When assigning edge values to the tester, we need to compensate for this Tpd.
The path delay are made up of the channel coax cables, the tester to DIB contact,
the DIB trace to DUT socket. It is important that this path have a characteristic
impedance of 50 ohm to prevent reflections
along the path.
Revised 8/8/2007
296
PATH DELAY (TDR calibration)
Zo = 50 ohm
8
Zl=
Zs=50 ohm
The typical technique used by most ATEs to measure out the path delay is
called Time Domain Reflectometry or TDR. Here, the DUT is not part of
the setup, so the line is open circuit at the end. This causes the edge sent
by the driver to get reflected back at 0 phase shift.
Revised 8/8/2007
8
Vref/Vinc = (Zl – Zo) / (Zl + Zo).For Zl=
, Vref = Vinc.
297
PATH DELAY (TDR calibration)
Zo = 50 ohm
8
Zl=
Zs=50 ohm
The total path of the signal from source to open end and back to the
source is called the round-trip delay.The reflected edge superimposes
with the voltage at the source at time = 2xTpd:
Revised 8/8/2007
Measured time= 2xTpd
298
PATH DELAY (TDR calibration)
The Tpd of all channels are measured by the tester during TDR calibration.
This results are typically stored as a calibration file which the tester uses to
compensate for the edge timing setup:
User setup
t0
t0
Tester compensates
Drvedge=t1
Drvedge = t1 - Tpd
The edge arrives at the DUT pin at programmed edge time.
So, timing setup is DUT referenced and not tester referenced.
Revised 8/8/2007
299
PATH DELAY (TDR calibration)
Similarly, the compare edges are also compensated for:
User setup
t0
t0
Tester compensates
Window cmpedges
at t1 and t2
Window cmp edges
at t1+Tpd and t2+Tpd
The edge from the DUT arrives at the channel board pin at
programmed compare edges
time.
Revised 8/8/2007
300
Self-Assess Questions
1. Which of this is measured within the same signal (on the same pin)?
Propagation Delay, Rise time, Period, Duty Cycle
2. Digital Timing is said to be DUT-referenced, and not Tester-reference.
For this, which of the below needed to be presence (ideally) when timing
calibration is performed?
LoadBoard, Socket, Device, none of these
3. What is the difference between a DC and an AC test?
4. One typical timing calibration performed by the ATE is the Path
Skew/Deskew. What is the other?
Revised 8/8/2007
301
Introduction to
MIXED SIGNAL Testing
Digital Input
ADC/DAC
Analog Output
DAC
Analog Input
ADC
Revised 8/8/2007
Digital Output
302
MIXED SIGNAL TEST
Test signals required by the DUT are analog and digital
DC Input
VCC
DUT
DUT STIMULUS
DUT RESPONSES
Analog
Output
Analog
Inputs
PGA
ADC
DAC
Digital
Inputs
Revised 8/8/2007
Digital
Output
Analog
Output
303
Basics – Sampling Theory
Analog Signals
• Signals we use in the real world
• Signal is continuous in both time and amplitude
• Example: our voices
Digital Signals
• To process analog signals in computers, need to convert them
to "digital" form
• Signal is discrete in both time and amplitude
Sample
Each measurement or number
Sample Set
• The series of samples which represent the analog signal
• Also known as the numerical replica of the analog signal.
Revised 8/8/2007
304
Basics – Sampling Theory
Revised 8/8/2007
305
Basics – Sampling Theory
What is the sampling rate to use to ensure we are preserving the
information contained in the signal?
If the signal contains high frequency components, need to sample
at a higher rate to avoid losing information that is in the signal.
To be able to recreate a signal from its samples, one must sample
at a rate higher than twice the highest frequency of interest, Fi (or
frequency of test Ft), contained in the signal.
This is the famous Nyquist Theorem.
Fs  2Fi
Revised 8/8/2007
306
Basics – Sampling Theory
What happens if we sample the signal at a frequency that
is lower that the Nyquist rate?
When the signal is converted back into a continuous time
signal, it will exhibit a phenomenon called aliasing. Aliasing
is the presence of unwanted components in the
reconstructed signal.
These components were not present when the original
signal was sampled.
In addition, some of the frequencies in the original signal
may be lost in the reconstructed signal.
Revised 8/8/2007
307
Basics – Sampling Theory
Aliasing occurs because signal frequencies can overlap if
the sampling frequency is too low.
Frequencies "fold" around half the sampling frequency
(Nyquist Frequency).
Nyquist Freq
Fs = 100KHz
DC
fix = input freq of interest
fax = alias freq
f(Hz)
-20K 0
20K
25K
40K
-fa4 fa3
fa4
fa2
fa1
50K
60K
75K
fi1
fi2
Revised 8/8/2007
100K 120K
fi3
fi4
308
Basics – Sampling Theory
How to minimize aliasing problem?
To minimize aliasing problem, we need to remove frequency
components greater than Fs/2 from the signal being digitalized.
Achievable by using an anti-aliasing filter; i.e. a low-pass-filter.
Revised 8/8/2007
309
Coherency Formula
#of cycle
Frequency
of Interest
#of sample
Sampling
Frequency
where
Fs = sample frequency
Fi = frequency of interest
N = number of samples
M = number of Fi cycles over which samples are taken
Revised 8/8/2007
310
Practical Sampling Theory
1. Let's assume, we have a continuous repeating sinewave with a frequency of 1 kHz.
Amplitude
2. We take a part of the sinewave, and scale it. We are in the Time Domain.
Time
Revised 8/8/2007
311
Practical Sampling Theory
3. Next, we take 16 measurements (samples), and store them in an array
Revised 8/8/2007
312
Practical Sampling Theory
To make calculations for sourcing & capturing, we use the following:
Fi the frequency of interest = 1khz
Fs the sample frequency = ??
M the number of cycles = 3
N the number of samples =16 Revised 8/8/2007
313
Practical Sampling Theory
#of cycle
Frequency
of Interest
#of sample
Sampling
Frequency
5.333kHz
Revised 8/8/2007
314
Coherent Sampling
Considerations in using variables in the balanced ratio
Fi, Fs, M, N
Increasing M and/or N will increase accuracy and test time
M needs to be a whole number to have a coherent waveform (a
whole number of cycles or complete/full cycles)
N has to be a whole number because there is no such thing as half
a sample
N needs to be a power of 2 to ensure you can use a Fast Fourier
Transform (FFT)
M and N must be "mutually prime" otherwise you waste test time
because in each cycle you sample the same points over and over.
Minimum Fs = >2*Fi (Nyquist Theorm)
Revised 8/8/2007
315
Coherent Sampling
Why M and N must be "Mutually Prime"
Above M=3 and N= 12 so they are not mutually prime or lowest common denominator.
In every cycle, samples are taken at the same position, there is no new information.
In this case M=3 and N=16, so they are mutually prime and every sample is discrete,
that is it gives unique information, sampling a different point in time.
Revised 8/8/2007
316
Example
If you want to generate a 10 MHz sinewave that repeats after every 256
samples, you must select a sampling frequency at least twice the frequency of
the desired Fi.
Choosing a Fs of 8 x Fi gives 80 MHz, so that at first pass the equation
becomes
N/M = 256/M = 80 MHz/10 MHz
(2)
M = 256*(10 MHz/80 MHz) = 32
(3)
You can see from equation (3) that M satisfies the requirement of being an
integer number of cycles, but it places the samples in exactly the same position
on the sinewave for all 32 cycles. (Not mutually prime)
For converter testing this means the same eight codes are tested over the
sample window as shown below.
Revised 8/8/2007
317
Basics – Sampling Theory
Periodic Sample Generation, but not mutually prime
Revised 8/8/2007
318
Basics – Sampling Theory
A better approach is to uniquely distribute the 256 samples across the
windows. To do this, use an integer prime number for M close to the
desired value that still satisfies the other conditions.
In this case, use M=31 so equation (2) becomes
N/M = 256/31 = Fs/Fi = 82.58064516 MHz /10 MHz
Revised 8/8/2007
(4)
319
Basics – Sampling Theory
A better approach is to uniquely distribute the 256 samples across the sample
window as shown below.
Revised 8/8/2007
320
Basics – Sampling Theory
Frequency Resolution (Fres), resolution of the spectrum
Fres = Fs/N
(5)
Acquisition Time (UTP), time required to take all samples
Tacq = 1/Fres
In equation (5), the Fres = Fs/N = 82.5 MHz/256 = 322.265 kHz.
Revised 8/8/2007
321
Basics – Sampling Theory
Why sample coherently?
When digitizing a waveform, coherent sampling eliminates
the need for any time windowing by guaranteeing that the
sample set contains a complete, periodic waveform
representation.
FFT output from a set of coherent samples puts the
relevant information about the fundamental and harmonics
into specific, well defined frequency ranges, called bins.
When generating a waveform, there is no leakage because
coherent sampling guarantees that there will be exactly a
complete set of samples for one or more signal cycles.
Revised 8/8/2007
322
Basics – Sampling Theory
What happens if we do not have a complete sample set?
If the time sample set does not form a complete set, leakage occurs.
Discontinuity occurs where 2 sample sets join, causing a sharp edge
within a sinusoid.
A sharp edge in time has high frequency components.
To minimize the effects of leakage, use time window
functions.Examples of window function: Hann, Hamming and
Blackman
To eliminate the effects of leakage, use coherent sample set.
Revised 8/8/2007
323
What does the FFT see?
PERIODIC
SAMPLE SET
NONPERIODIC
SAMPLE SET
SINGLE
REPEATED
DISCONTINUITY
Revised 8/8/2007
324
Basics – FFT
Coherent capture is a prerequisite to successful FFT operations.
Non integer period capture will cause spectral smearing:
Fs/Fi=N/M
M=2
M=1.25
Revised 8/8/2007
325
Fundamental of FFT
Time Domain
Frequency Domain
||
||
Fundamental
+
+
Third Harmonic
+
+
Revised 8/8/2007
Fifth Harmonic
326
Basics – FFT
• Fourier Transform (FT)
- Continuous-time signals – possible only theoretically.
- Cannot be implemented using a computer.
• Discrete Fourier Transform (DFT)
- Sampled signals – finite number of samples.
- Extensive math – time consuming – n2 mathematical
iterations.
- Ex: 4,000 samples ~ 16,000,000 iterations
• Fast Fourier Transform (FFT)
- Sampled signals – 2n number of samples. Ex: 4, 16, 32, ...
- Simplified math – nlog2n mathematical iterations.
- Ex: 4,096 samples ~ 49,152 iterations
Revised 8/8/2007
327
Basics – FFT
The Fast Fourier Transform (FFT) is an algorithm for transforming
data from the time domain to the frequency domain.
A time-record is defined to be N (sample size) consecutive, equally
spaced samples of the input.
N is restricted to be a multiple of 2 as it makes our transform algorithm
simpler and much faster.
Revised 8/8/2007
328
Basics – FFT
FFT assumes periodicity in all cases.
FFT is a linear transform whereby two or more waveforms
can be summed in the time domain to give a third function.
Likewise, the frequency domain of this new function is the
sum of the frequency domains of the original functions.
Any multi-tone signal is actually made up of multiple singletone signals.
Revised 8/8/2007
329
Basics – FFT
FI_M1 = 8,750 Hz (M = 35)
+
FI_M2 = 10,750Hz (M = 43)
=
FI_M3 = 12,750Hz (M = 51)
+
FS_M = 256 KHz
Revised 8/8/2007
330
Basics – FFT
Test time increases with increasing sampling size as the number of
operations required for computation increases.
The output of FFT is usually in rectangular coordinates.
Need to convert to polar form to obtain magnitude and phase
information.
Revised 8/8/2007
331
Basics – FFT (Amplitude Spectrum)
Magnitude
•
•
•
Amplitude Spectrum
For N (power of 2) time domain
samples, there will be N
frequency domain values.
The N values are grouped in
pairs called bins (0,1 -> bin 0;
2,3 -> bin 1; 4,5 -> bin 2; ...) that
represent one frequency
component (magnitude and
phase).
The two values are a real and
imaginary component that
represent a sinusoidal
component with a given phase
and amplitude
Real Component
Imaginary Component
Array Index 0
1
2
3
4
5
k k+1
N-2 N-1
Bin Number
0
1
2
M
N/2-1
Frequency
dc
Fres
2*Fres
Fi
Fs/2-Fres
Vector Representation
of a Sinsusoid
Fi / Fs = M / N
Fres = Fs / N
Imaginary
= A Sin θ
Revised 8/8/2007
A
θ
Real =
A Cos θ
M = Fi × N / F s
= Fi / Fres
332
Basics – FFT (Power Spectrum)
Power Spectrum
Magnitude
•
•
•
Frequency Component
For N time-domain signal samples
There are N frequency-domain
signal values
There are N/2 frequency-domain –
Power Spectrum values
Array Index 0
1
2
k
N/2-1
Bin Number 0
1
2
Fbin
N/2-1
Frequency
Fres
2*Fres
Fi
Fs/2-Fres
Revised 8/8/2007
dc
333
Frequency Domain Signal Definitions
Frequency Bin
The frequency spectrum contains signal amplitudes at discrete
frequencies normally called frequency bins.
DC Component
The first frequency bin resulting from the FFT is the DC
component of the signal.
Fundamental
This is the frequency of interest. The input signal to the A/D.
Spectrum
The entire array of frequencies represented by the FFT.
Harmonics
Odd and even multiples of the fundamental signal.
Noise
The frequency components represented in a given bandwidth
other than the DC component, fundamental, and harmonics.
RMS
Root Mean Squared.
Revised 8/8/2007
334
Frequency Analysis
Common Frequency Analysis Algorithms
• Signal To Noise Ratio (SNR)
• Total Harmonic Distortion (THD)
• Signal to Noise and Distortion (SINAD)
• Spurious Free Dynamic Range (SFDR)
Revised 8/8/2007
335
What are the Spectral Components?
v2
• Captured sine wave with N samples
• Power spectrum has N/2 samples
Fundamental
DC Component
Second
Harmonic
Third
Harmonic
Noise
Components
ƒ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Power Spectrum
Revised 8/8/2007
336
Signal to Noise Ratio (SNR)
v2
Store the value of the fundamental
This is the signal power
ƒ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Power Spectrum
Revised 8/8/2007
337
Signal to Noise Ratio (SNR)
v2
Stride through the array and zero out fundamental,
harmonics (usually up to 5), and the DC component
ƒ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Power Spectrum
Revised 8/8/2007
338
Signal to Noise Ratio (SNR)
v2
Sum all bins of the remaining power spectrum
This gives the noise power
ƒ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Power Spectrum
Revised 8/8/2007
339
Signal to Noise Ratio (SNR)
• Expressed in decibels (dB)
• The signal to noise ratio is a positive value (assuming the
fundamental power is greater than the noise power)
SNRdB = 10 log10
Fundamental
Noise Power
Revised 8/8/2007
340
Total Harmonic Distortion (THD)
v2
Store the value of the fundamental tone.
This is the signal power
ƒ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Power Spectrum
Revised 8/8/2007
341
Total Harmonic Distortion (THD)
Stride through the array and keep a running sum of
the total harmonic power (usually only the first five
harmonics).
v2
Start at the second harmonic.
sum
sum
sum
ƒ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Power Spectrum
Revised 8/8/2007
342
Total Harmonic Distortion (THD)
• Expressed in decibels (dB)
• The THD is a negative value (assuming the fundamental
power is greater than the noise power)
THDdB = 10 log10
Harmonic Power
Fundamental
Revised 8/8/2007
343
Signal to Noise and Distortion (SINAD)
• This is the same methodology as computing SNR. However, now
power of the harmonics is added to the noise power.
• Only zero out the DC component.
S
SNR 
N
D
S
THD 
SINAD 
S
ND
N D ND
1
SNR  THD   
 SINAD 1
S S
S
1
SINAD  ( SNR  THD )
Revised 8/8/2007
1
344
Spurious Free Dynamic Range (SFDR)
v2
Store the value of the fundamental
This is the signal power
ƒ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Power Spectrum
Revised 8/8/2007
345
Spurious Free Dynamic Range (SFDR)
v2
Stride through ALL array elements. Find the highest
element (ignoring the fundamental and DC component).
Note that the highest element may or may not be a
harmonic! Store the value of this component.
For this example, the highest
element other than the
fundamental is the second
harmonic.
ƒ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Power Spectrum
Revised 8/8/2007
346
Spurious Free Dynamic Range (SFDR)
•Expressed in decibels (dB)
•The spurious free dynamic range is a positive value
(assuming the fundamental is greater than the next
highest spur power)
SFDRdB = 10 log10
Fundamental
Next Highest
Revised 8/8/2007
347
Generic Mixed Signal
Tester Architecture
PATTERN DATA SEQUENCER
SOURCE
MEM
PATTERN
MEM
CAPTURE
MEM
WAVEFORM DATA TO
TESTER CPU / DSP PROC
WAVEFORM
DATA FROM
TESTER CPU
USER CPU
TIMING AND
FORMATTING
CLOCKS +
SYNC
TESTER
CPU
+ DSP
PROC
DIGITAL HSD
DC
METER
V/I
SOURCES
AC SRC
DUT
RELAY MATRIX AND
OTHER CONNECTION
PATHS TO DUT
TIME MEAS
SUB-SYSTEM
VOLTMETER
AC DIG
PATTERN DATA SEQUENCER
WAVEFORM
DATA FROM
TESTER CPU
SOURCE
MEM
PATTERN
MEM
CAPTURE
MEM
WAVEFORM DATA TO
TESTER CPU / DSP PROC
USER CPU
TIMING AND
FORMATTING
CLOCKS +
SYNC
TESTER
CPU
+ DSP
PROC
DRIVE AND
COMPARATOR
CHANNELS
Arbitrary Waveform
Generator
V/I
SOURCES
AC SRC
DC
METER
DUT
RELAY MATRIX AND
OTHER CONNECTION
PATHS TO DUT
TIME MEAS
SUB-SYSTEM
VOLTMETER
AC DIG
ARBITRARY WAVEFORM GENERATOR
ANALOG
CLK
Sampling clock
providing sample rate
to src mem and DAC
Single-ended
Or differential
output
Programmable
Gain amp for
Amplitude setting
WAVEFORM
SOURCE
MEMORY
OUT_HI
DAC
LOW PASS
FILTER
PGA
OUT_LO
DAC
Digital sample
Data that represent
a wave-form
Stepped voltage
for each input sample
is produced by the DAC
Smoothed signal
after Low Pass Filtering
Revised 8/8/2007
Provides
DC-offset
350
IMPORTANT PARAMETERS OF AN AWG
Maximum Peak to Peak Voltage output
Waveform resolution (DAC resolution)
Band-width
Waveform source memory depth
Output Impedance
Noise, THD, SNR
Revised 8/8/2007
351
PATTERN DATA SEQUENCER
WAVEFORM
DATA FROM
TESTER CPU
SOURCE
MEM
PATTERN
MEM
CAPTURE
MEM
WAVEFORM DATA TO
TESTER CPU / DSP PROC
USER CPU
TIMING AND
FORMATTING
CLOCKS +
SYNC
TESTER
CPU
+ DSP
PROC
DRIVE AND
COMPARATOR
CHANNELS
DC
METER
V/I
SOURCES
AC SRC
DUT
RELAY MATRIX AND
OTHER CONNECTION
PATHS TO DUT
TIME MEAS
SUB-SYSTEM
VOLTMETER
AC DIG
Waveform
Digitizer
WAVEFORM DIGITIZER
This analog clock provides the sampling
Rate for the ADC and capture memory
DUT Signal
+ noise
ANALOG
CLK
OUT_HI
LOW PASS
FILTER
OUT_LO
ADC
WAVEFORM
CAPTURE
MEMORY
PGA
Amplified
DUT signal
Filtered
DUT signal
Revised 8/8/2007
Sampled DUT signal
353
IMPORTANT PARAMETERS OF A
WAVEFORM DIGITIZER
Maximum Peak to Peak input Voltage range
Waveform resolution (ADC resolution)
Band-width
Waveform capture memory depth
Input Impedance
Noise, THD, SNR, spur
Revised 8/8/2007
354
PATTERN DATA SEQUENCER
Digital-Analog
Synchronization
SOURCE
MEM
PATTERN
MEM
CAPTURE
MEM
USER CPU
TIMING AND
FORMATTING
CLOCKS +
SYNC
TESTER
CPU
+ DSP
PROC
ac src trigger
from sequencer
DC
METER
V/I
SOURCES
AC SRC
DUT
TIME MEAS
SUB-SYSTEM
Ac dig trigger
from sequencer
RELAY MATRIX AND
OTHER CONNECTION
PATHS TO DUT
VOLTMETER
AC DIG
WHY SYNCHRONIZATION?
Digital signal
Analog signal
t
If this alignment is crucial for DUT operations, the
digital sub-system must have the capability to send a
trigger to the analog sub-system source at a precise t0
cycle.
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356
REPEATABILITY
1.
The analog clock that
provides the sample rate
to the AC src is seen to
not have a fixed phase
relationship to t0.Rather,
it will have a random
phase shift with respect
to t0. This causes the
run to run Sync error by
one analog clock cycle
which can be multiples
of t0.
2.
Lead
3.
Lag
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357
REPEATABILITY
1.
SYNC
2.
SYNC
To ensure that the
analog clock and the
t0 is at a known
phase relation-ship at
every run, a syncing
routine between the
t0 and analog clock
must be done prior to
starting the signals.
This syncing routine
actually aligns the
clocks together.
SYNC
3.
Revised 8/8/2007
358
PATTERN DATA SEQUENCER
SOURCE
MEM
PATTERN
MEM
CAPTURE
MEM
Waveform Data To Tester
CPU / DSP Proc
USER CPU
TIMING AND
FORMATTING
TESTER
CPU
+ DSP
PROC
CLOCKS +
SYNC
DC
METER
V/I
SOURCES
DUT
TIME MEAS
SUB-SYSTEM
RELAY MATRIX AND
OTHER CONNECTION
PATHS TO DUT
AC DIG
AC SRC
Revised 8/8/2007
Digital Signal
Processing
Captured analog
Waveform data
Moved to DSP proc
359
Test Flow
DUT Set-up
Apply signal stimulus
Capture DUT Response
Move Captured DUT data to DSP Processor
To extract test parameters
Compare test parameters against test limits
Revised 8/8/2007
360
Self-Assess Questions
• What is the definition of a mixed signal circuit?
• What is the difference between FFT and DFT algorithm?
• How can leakage be avoided that may be caused by the test
system?
• What is coherent sampling?
• If 128 samples are taken at 50usec intervals from 7 complete
cycles,
– What is the UTP?
– What is the Fres?
– What is the signal frequency?
Revised 8/8/2007
361
ADC TESTING
Revised 8/8/2007
362
Analog-to-Digital Converter
An ADC is used to convert analog signals to digital data
0101
V
1011
t
LPF
ADC
1111
0111
0011
Revised 8/8/2007
363
Analog-to-Digital Converter
111
110
101
3 bit ADC
Digital 100
Output
011
010
001
Analog
Input
000
Revised 8/8/2007
364
ADC STATIC PARAMETERS
The ideal transfer function for an ADC is a straight line but the actual
ideal result is a uniform staircase where the number of steps corresponds
to the number of digital output codes. Since analog is continuous and
digital is discrete this results in quantization process which introduces an
error (quantization error).
The width of one step is 1 LSB (least significant bit). The resolution of an
ADC is normally expressed as number of bits (digital output code). An
ADC with an n-bit resolution has 2n possible digital codes which define 2n
step levels. But the first (zero) step and the last (all ones) are only one
half of a full width thus the full-scale range (FSR) is divided into 2n –1
step widths. Thus one LSB is:
1 LSB = FSR /(2n-1) for an n-bit converter
Revised 8/8/2007
365
ADC STATIC PARAMETERS
Digital Output
Code
Analog
Input
Values
5.5-6.5
Digital
Output
Code
0…110
4.5-5.5
0…101
3.5-4.5
0…100
2.5-3.5
0…011
1.5-2.5
Ideal Straight Line
0…110
0…101
Center
0…100
1 LSB = FSR/ (2n – 1)
0…011
Note: FSR (Full Scale Range)
LSB (Least Significant Bit)
0…010
0…010
0.5-1.5
0…001
0.0-0.5
0…000
0…001
Step Width (1 LSB)
Analog Input
Value
0…000
0
1
Quantization
Error
+1/2
LSB
0
-1/2
LSB
1
2
2
3
3
4
4
5
5
Revised 8/8/2007
6
6
Analog Input
Value
366
ADC STATIC PARAMETERS
Offset Error
Digital Output Code
0…011
Ideal
Steps
0…010
Actual
Steps
0…001
0…000
Ideal Offset
Point
0
1
2
3
Analog Input Value
Actual
Offset Point
Offset Error
Offset Error (also called zero-scale error) is the difference between
ideal and actual offset (initial) points. For the ADC the offset error is
measured from the midpoint of the zero step (ideal to actual).
Revised 8/8/2007
367
ADC STATIC PARAMETERS
For ADC the gain point is the middle of the full scale output step.
Digital Output Code
Actual
Steps
actual value
111
ideal value
110
Gain
Error
101
Ideal
Steps
000
0
5
6
7
Analog Input Value
Gain Error is the difference between ideal and actual gain points on
the transfer function after the offset error has been corrected to zero.
Revised 8/8/2007
368
ADC STATIC PARAMETERS
DNL Error is the difference between an actual step width and an
ideal step width (1 LSB). If DNL Error is too large, there can be missing
codes, where one or more of the codes never receive an output.
Digital Output Code
0…011
1 LSB
0…010
0…001
Differential
Linearity Error
1 LSB
0…000
0
1
2
3
4
Analog Input Value
Differential Non Linearity (DNL)
Revised 8/8/2007
369
ADC STATIC PARAMETERS
INL Error is the deviation of the values of the actual step function to
the ideal straight line function. For ADC, the deviations are measured at
the transition points from one step to the next.
Ideal Straight Line
Digital Output Code
0…110
Ideal
Transition
0…101
Actual
Transition
0…100
Deviation
0…011
Linearity Error = sum of all deviations
0…010
INL = S DNL[i]
0…001
Analog Input Value
0…000
0
1
2
3
4
5
6
Integral Revised
Non8/8/2007
Linearity (INL)
370
ADC TEST SETUP
AC Source should be
2-4 bits more resolution
than the ADC under test
Device Under Test
(DUT)
ADC
AC-SRC
Data
In
01011
Data
Out
Digital
System
clk
Analog
Clock
Generator
Clock Reference
Revised 8/8/2007
Digital
Clock
Generator
371
ADC STATIC TEST METHODOLOGY
The ADC voltage-to-code transfer curve is a many-to-one mapping function.
15
Fundamental measurement : measure the voltage
corresponding to the transition from one digital code to
the next (decision level, code edge).
ADC Output Code
10
5
Practical test technique: linear ramp histogram method
(code width measurement). The input ramp is slow
enough to give a statistically relevant “number of hits per
code”.
35
30
25
0
20
0
0.5
1.0
ADC Input Voltage
1.5
15
10
5
0
0
Revised 8/8/2007
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
372
ADC STATIC TEST METHODOLOGY
Digital Output Code
011
# of Digital
Capture data hits
010
001
1 LSB
Analog Input
Value
000
0
1
2
3
4
Samples per Digital Code Graph
16
Average
width
12
LSB
width
8
Missed Code
4
000
001
010
011
Revised 8/8/2007
Histogram Graph
100
101
373
ADC STATIC TEST METHODOLOGY
Histogram Method
Make a ramp wave segment for ACSRC. The input ramps goes
above and below +Fs/-Fs to assure that all codes are covered.
Input voltage
+Fs
n number of ADC‟s bits
N number of additional bits (=4)
-Fs
2(n+N)
Samples
Resolution of ac source  1/16 (resolution of ADC)
Linearity of ac source = 1/16 (resolution of ADC)
Revised 8/8/2007
374
ADC STATIC TEST METHODOLOGY
Histogram Method
Block diagram of signal setup
+peak
2n-1 max_code
-peak
0 min_code
ACsrc
Fs = 2(n+N) • Ramp_freq
A/D
n-bit
dig_cap
Fs = 2(n) •Ramp_freq •hits_per_code
Samples_captured = 2(n) . hits_per_code
Revised 8/8/2007
375
ADC STATIC TEST METHODOLOGY
Histogram Method
Capture the Ramp wave
Revised 8/8/2007
376
ADC STATIC TEST METHODOLOGY
Histogram Method
Use DSP algorithm to generate a histogram plot of the
captured ramp
Histo-plot
Revised 8/8/2007
377
ADC STATIC TEST METHODOLOGY
Histogram Method
Take data between the start of ramp (min+1 code [0…01]),
to the end of the ramp (max-1 code [1…10]).
This gives you 2n – 2 codes‟ worth of data.
Hits/Code
Ideal Hits/code width
16
12
………
8
4
00..1
00..1
0…10
0…11
0..100
0…101
……..
Code
Histogram Graph
Revised 8/8/2007
378
ADC STATIC TEST METHODOLOGY
Histogram Method
Calculate for DNL[i] = Hits[i] - ∑ Hits[i]
2n - 2
∑ Hits[i]
2n - 2
Hits/Code
Ideal Hits/code width
16
Mean hits/code
12
………
8
4
00..1
00..1
0…10
0…11
0..100
0…101
……..
Code
Histogram Graph
Revised 8/8/2007
379
ADC STATIC TEST METHODOLOGY
Histogram Method
Find max DNL and min DNL values:
DNL
Max DNL
0.200
0.00
-0.200
Min DNL
Codes
Revised 8/8/2007
380
ADC STATIC TEST METHODOLOGY
Histogram Method
Calculate INL[i] = DNL[i]+DNL[i-1]+…..+DNL[0] for every i.
Get Max INL and Min INL
INL
Max INL
Min INL
Revised 8/8/2007
Codes
381
ADC DYNAMIC TEST METHODOLOGY
It is common practice to ensure the analog clock and the
digital clock are referenced to a common master clock so
that phase relation-ship of the clock sources are fixed and
synchronized, making test results highly repeatable.
Fi
ACsrc
n-bit
A/D
Fs
dig_cap
Fsdut
Master Clock
Ref
Revised 8/8/2007
ADC Dynamic Testing
382
ADC DYNAMIC TEST METHODOLOGY
The ACSRC is used to supply a sinewave input to the ADC.
The output from the ADC (digital representation of the sinewave)
is captured/sampled by the dig_cap.
Coherency of source and capture is important.
Fi
ACSRC
n-bit
A/D
Fs
dig_cap
Fsdut
Master Clock
Ref
Revised 8/8/2007
383
ADC DYNAMIC TEST METHODOLOGY
For digital capture:
Fsdut/Fi = Ncap/M
where,
Fsdut = ADC sampling rate= dig_cap sample rate
Ncap = # of samples captured (2x number)
Mc = # of integer cycles (odd)
Fi = signal frequency
Fi
ACsrc
Fs
A/D
n-bit
dig_cap
Fsdut
Master Clock
Ref Revised 8/8/2007
384
ADC DYNAMIC TEST METHODOLOGY
For AC source:
Fs
Ns
---- = ---Fi
Ms
where,
Fs = AC src sampling rate
Ns = # of samples in src mem
(does not have to be a 2x number)
Ms = # of integer cycles (does not have to be odd)
Fi = signal frequency
Fi
ACsrc
Fs
A/D
n-bit
dig_cap
Fsdut
Master Clock
Ref Revised 8/8/2007
385
ADC DYNAMIC TEST METHODOLOGY
Dynamic tests: Signal to Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Signal to Noise+Harmonics ratio (SINAD)
The ADC has a theoretical best ever SNR of:
SNR = (6.02N + 1.76) dB, where N= number of ADC bits.
Example: Theoretical SNR of a 10 bit ADC is:
(6.02x10 + 1.76) ~ 62 dB.
Revised 8/8/2007
386
ADC DYNAMIC TEST METHODOLOGY
Dynamic ADC tests requirements:
•
•
•
•
•
Resolution of ACsrc should be at least 2 to 4 bits better
than DUT
Capture MUST be coherent
Larger Ncap size improves SNR measurement by
lowering the noise floor of captured spectrum
Noise floor of AC src MUST be lower than measured
noise floor.
Higher Fsdut and utilizing a smaller spectrum bandwidth
for measurements improves SNR results.
Revised 8/8/2007
387
ADC DYNAMIC TEST METHODOLOGY
Spectrum of captured data: the more Ncap the better
Revised 8/8/2007
388
ADC DYNAMIC TEST METHODOLOGY
ADC capture spectrum analysis: fundamental is at Bin=Mc.
Fi = (Fsdut/Ncap) x Mc = Fresdut x Mc.
Amp
Fund
2nd Harm
3rd Harm
BW=Fsdut/2 or Ncap/2
Bin=0
DC
Bin = Mc
F= Fresdut x Mc
Bin = 2xMc
F=Revised
2xFresdut
x Mc
8/8/2007
Bin= 3xMc
F = 3x Fresdut x Mc
389
ADC DYNAMIC TEST METHODOLOGY
SNR, THD, SINAD tests:
Step 1. Store Fund Bin amplitude:
 Fundamental_amp.
Amp
Fundamental_amp
Fundamental
2nd Harmonic
3rd Harmonic
BW=Fsdut/2 or Ncap/2
Bin=0
DC
Bin = Mc
Bin = 2xMc
Bin= 3xMc
F= FresdutxMc F= Revised
2xFresdutxMc
8/8/2007 F = 3x FresdutxMc
390
ADC DYNAMIC TEST METHODOLOGY
SNR, THD, SINAD tests:
Step 2. Store 2nd and 3rd Harmonic amplitudes:
 2nd_Harm_amp
rd _Harm_amp

3
Amp
Fund_amp
2nd_Harm_amp
3rd_Harm_amp
Fund
2nd Harm
3rd Harm
BW=Fsdut/2 or Ncap/2
Bin=0
DC
Bin = Mc
Bin = 2xMc
Bin= 3xMc
F= FresdutxMc F= Revised
2xFresdutxMc
8/8/2007 F = 3x FresdutxMc
391
ADC DYNAMIC TEST METHODOLOGY
SNR, THD, SINAD tests:
Step 3. Zero out the DC,Fund and Harmonics:
Amp
BW=Fsdut/2 or Ncap/2
Bin=0
DC
Bin = Mc
Bin = 2xMc
Bin= 3xMc
F= FresdutxMc F= Revised
2xFresdutxMc
8/8/2007 F = 3x FresdutxMc
392
ADC DYNAMIC TEST METHODOLOGY
SNR, THD, SINAD tests:
Step 4. Sum all remaining Bins. Store results as Noise
 Noise_amp
Amp
BW=Fsdut/2 or Ncap/2
Bin=0
DC
Bin = Mc
Bin = 2xMc
Bin= 3xMc
F= FresdutxMc F= Revised
2xFresdutxMc
8/8/2007 F = 3x FresdutxMc
393
ADC DYNAMIC TEST METHODOLOGY
SNR, THD, SINAD tests:
Step 5. Compute results:
Signal-to-Noise Ratio (in dB)
= 10log [(Fund_amp)/(Noise_amp)]
Total Harmonic Distortion (in dB)
= 10log[(2nd_Harm_amp + 3rd_Harm_amp)/(Fund_amp)]
Signal-to-Noise+Distortion (in dB)
= 10log[(2nd_Harm_amp + 3rd_Harm_amp +
Noise_amp)/(Fund_amp)]
Revised 8/8/2007
394
DAC TESTING
Revised 8/8/2007
395
Digital-to-Analog Converter
Vfs
Analog Output
(Volts)
Digital code input ―n‖
Vzs
0
0
0
0
0
0
0
0
1
0 0 0 0 0
0 0 1 1 1
1Revised
1 0 8/8/2007
0 1
0 1 0 1 0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
396
Digital-to-Analog Converter
A DAC is used to convert digital data to analog signal
0101
V
1011
1111
DAC
LPF
t
0111
0011
Revised 8/8/2007
397
Digital-to-Analog Converter
3.50v
3.00v
2.50v
3 bit DAC
with 3.5v Ref
Analog 2.00v
Output
1.50v
1.00v
0.50v
0.00v
111
110
101
100
011
010
001
000
Revised 8/8/2007
Digital
input
398
DAC Static Parameters
FSR - Full Scale Range is defined as the difference between
the minimum and maximum voltages of a DAC output.
Actual full scale output
• Vfsr = Vfs+ - Vfs-
Vfs
Analog
Output
(Volts)
Device
FSR
Vzs
Digital code input ―n‖
Offset 8/8/2007
Revised
Error
399
DAC Static Parameters
•
•
LSBcalculated = FSR/(2n-1)
LSBDevice= (Vfs - Vzs )/(2n-1)
Actual full scale output
Vfs
Analog
Output
(Volts)
Actual LSB step
Device LSB=(Vfs-Vzs)/(2n-1)
Calculated Device LSB size
Ideal LSB=FSR/(2n-1)
Vzs
Digital code input ―n‖
Offset 8/8/2007
Revised
Error
400
DAC Static Parameters
• INL = Vactual - Videal at a given point
Actual full scale
output
Vfs
Analog
Output
(Volts)
Actual output
Optimum output
INL = Actual output - Optimum output
Vzs
Digital code input ―n‖
Offset 8/8/2007
Revised
Error
401
DAC Static Parameters
• DNL = LSBactual - LSBcalculated at a given point
Actual full scale output
Vfs
Analog
Output
(Volts)
Actual LSB step
Device LSB=(Vfs-Vzs)/(2n-1)
Calculated Device LSB size
Ideal LSB=FSR/(2n-1) V
zs
DNL = Actual step - Calculated size
Digital code input ―n‖
Offset 8/8/2007
Revised
Error
402
DAC ERRORS
Gain Error = Vfs - Vzs - VFSR
Ideal full scale output
Vfs(ideal)
Actual full scale output
Vfs
Actual full scale - offset error
Analog
Output
(Volts)
Nonmonotonic
Actual output
INL = Actual output -Optimum output
Optimum output
Device
FSR
Straight line
between endpoints
Actual LSB step
DNL = Actual step - Calculated size
Calculated Device LSB size
Digital code input ―n‖
Vzs
0
Ideal LSB=FSR/(2n-1)
Offset
Device LSB=(Vfs-Vzs)/(2n-1) Error
0
0
0
0
0
0
0
1
0 0 0 0 0
0 0 1 1 1
1Revised
1 0 8/8/2007
0 1
0 1 0 1 0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
403
DAC TEST SETUP
Digital
Source
01011
(DUT)
AC Digitizer should be
2-4 bits more resolution
than the DAC under test
DAC
Data
In
Signal
Out
AC-DIG
clk
Digital
Clock
Generator
Clock Reference
Revised 8/8/2007
Analog
Clock
Generator
404
DAC STATIC TEST METHODOLOGY
Ramp Method
Make a ramp wave segment for dig_src (as input to DAC)
Codes
n number of DAC‟s bits
2n-1
0
2n
Samples
Revised 8/8/2007
405
DAC STATIC TEST METHODOLOGY
Ramp Method
Block diagram of signal setup
2n-1
+ peak
0
- peak
Dig_src
n-bits
Fs = 2n • Ramp_freq
D/A
ACdig
Fs = 2n • Ramp_freq • samples_per_code
Samples = Fs x (1/Ramp_freq)
Revised 8/8/2007
406
DAC STATIC TEST METHODOLOGY
Ramp Method
Capture output of DAC using ACdig
samples per code
Voltage
Vn
V4
V3
V2
V1
Total Samples=2n x samples per code
Captured/Digitized Ramp
Revised 8/8/2007
407
DAC STATIC TEST METHODOLOGY
Ramp Method
Calculate average LSB size to make ideal ramp
LSB = (+peak – (-peak))/ (2n – 1)
Make an ideal ramp
Ideal straight line; y=mx+c where, m= LSB and c= -peak
+peak
x
-peak
sample # 0
Revised 8/8/2007
sample # 2n-1
408
DAC STATIC TEST METHODOLOGY
Ramp Method
Average-out the voltage levels for each code.
samples per code=N
Voltage
Va
Averaged
Codes
V4a
V3a
V2a
V1a
Samples=2n
Revised 8/8/2007
409
DAC STATIC TEST METHODOLOGY
Ramp Method
Calculate INL=“Capture wave - ideal wave”
INL[i] = Averaged_ramp[i] – Ideal_ramp[i]
Find INLmax
+peak
Averaged ramp
Ideal ramp
-peak
sample # 0
Code
sample # 2n-1
Revised 8/8/2007
410
DAC STATIC TEST METHODOLOGY
Ramp Method
Calculate DNL:
DNL[i] = Averaged_ramp[i+1] – Averaged_ramp[i]
Find DNLmax
Offset
Ramp
DNL
Revised 8/8/2007
411
DAC DYNAMIC TEST METHODOLOGY
It is common practice to ensure the analog clock and the
digital clock are referenced to a common master clock so
that phase relationship of the clock sources are fixed and
synchronized, making test results highly repeatable.
dig_src
Fi
n-bit
D/A
Fsdut
DAC Dynamic testing
ACdig
Fs
Master Clock
Ref
Revised 8/8/2007
412
DAC DYNAMIC TEST METHODOLOGY
A dig_src is used to input discrete sinewave data to the DAC.
The converted analog levels (sinewave) from the DAC output
is digitized/ captured by the AC digitizer.
Coherency of source and capture is important.
dig_src
Fi
n-bit
D/A
Fsdut
ACdig
Fs
Master Clock
Ref
Revised 8/8/2007
413
DAC DYNAMIC TEST METHODOLOGY
For dig_src:
where
Fsdut
N
-------- = ----Fi
M
Fsdut = DAC sampling rate= dig_src sample rate
N = # of samples stored
M = # of integer cycles
Fi = signal frequency
dig_src
Fi
n-bit
D/A
Fsdut
ACdig
Fs
Master Clock
Ref
Revised 8/8/2007
414
DAC DYNAMIC TEST METHODOLOGY
For AC digitizer:
where
Fs
Ncap
---- = -----Fi
M
Fs = AC digitizer sampling rate
Ncap = # of samples in src memory
(has to be a 2x number)
Mc = # of integer cycles (has to be odd)
Fi = signal frequency
dig_src
n-bit
Fi
D/A
Fsdut
ACdig
Fs
Master Clock
Revised 8/8/2007 Ref
415
DAC DYNAMIC TEST METHODOLOGY
Dynamic tests:
Signal to Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Signal to Noise+Harmonics ratio (SINAD)
The digitizer can be thought of as an ADC device with a
theoretical SNR = (6.02N + 1.76) dB, where N is the
resolution of the digitizer.
Revised 8/8/2007
416
DAC DYNAMIC TEST METHODOLOGY
Dynamic DAC tests requirements:
•
•
•
•
•
Resolution of AC dig must be 2 to 4 bits better than DUT
Capture MUST be coherent
Larger Ncap size improves SNR measurement by
lowering the noise floor of captured spectrum
Noise floor of AC digitizer MUST be lower than measured
noise floor.
Higher Fs and utilizing a smaller spectrum bandwidth for
measurements improves SNR results.
Revised 8/8/2007
417
DAC DYNAMIC TEST METHODOLOGY
Spectrum of captured data: the higher Ncap the better
Revised 8/8/2007
418
DAC DYNAMIC TEST METHODOLOGY
DAC captured-spectrum analysis:
Fundamental is at Bin=Mc.
Fi = (Fs/Ncap) x M = Fres x M
Amp
Fund
2nd Harm
3rd Harm
BW=Fs/2 or Ncap/2
Bin=0
DC
Bin = M
F= Fres x M
Bin = 2xM
Bin= 3xM
F= 2xFres
M
F = 3x Fres x M
Revisedx8/8/2007
419
DAC DYNAMIC TEST METHODOLOGY
SNR, THD, SINAD tests:
Step 1. Store Fundamental Bin amplitude:
 Fund_amp.
Amp
Fund_amp
Fund
2nd Harm
3rd Harm
BW=Fsdut/2 or Ncap/2
Bin=0
DC
Bin = M
F= FresxM
Bin = 2xM
Bin= 3xM
F= 2xFresxM
Revised 8/8/2007 F = 3x FresxM
420
DAC DYNAMIC TEST METHODOLOGY
SNR, THD, SINAD tests:
Step 2. Store 2nd and 3rd Harmonic amplitudes:
 2nd_Harm_amp
 3rd _Harm_amp
Amp
Fund_amp
Fund
2nd Harm
2nd_Harm_amp
3rd_Harm_amp
3rd Harm
BW=Fsdut/2 or Ncap/2
Bin=0
DC
Bin = M
F= FresxM
Bin = 2xM
Bin= 3xM
F= 2xFresxM
Revised 8/8/2007 F = 3x FresxM
421
DAC DYNAMIC TEST METHODOLOGY
SNR, THD, SINAD tests:
Step 3. Zero out the DC, Fund and Harmonics:
Amp
BW=Fsdut/2 or Ncap/2
Bin=0
DC
Bin = M
F= FresxM
Bin = 2xM
Bin= 3xM
F= 2xFresxM
Revised 8/8/2007 F = 3x FresxM
422
DAC DYNAMIC TEST METHODOLOGY
SNR, THD, SINAD tests:
Step 4. Sum all remaining Bins.
Store results as Noise
Amp
 Noise_amp
BW=Fsdut/2 or Ncap/2
Bin=0
DC
Bin = M
F= FresxM
Bin = 2xM
Bin= 3xM
F= 2xFresxM
Revised 8/8/2007 F = 3x FresxM
423
DAC DYNAMIC TEST METHODOLOGY
SNR, THD, SINAD tests:
Step 5. Compute results
Signal-to-Noise Ratio (in dB)
= 10log [(Fund_amp)/(Noise_amp)]
Total Harmonic Distortion (in dB)
= 10log[(2nd_Harm_amp + 3rd_Harm_amp)/(Fund_amp)]
Signal-to- Noise+Distortion (in dB)
= 10log[(2nd_Harm_amp + 3rd_Harm_amp +
Noise_amp)/(Fund_amp)]
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Self-Assess Questions
What does the below parameters stand for:
FSR, INL, DNL, SINAD
What is the input signal (DC, ramp, sinewave etc) used for testing
ADC, DAC
Which needs to have lower Noise Floor?
Digitizer or DUT (for DAC test)
AC source or DUT (for ADC test)
You have a 11-bit AC Src. This instrument should be suitable to
generate an input signal to test which of the below?
8-bit ADC, 11-bit ADC, 8-bit DAC, 14-bit DAC
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Debug Tools
AND DEBUGGING
Debugging Tools
Basic Tester Debugging Tools are:
Datalog
Histograms
Characterization : - Shmoo , Margin
Pattern Debug
Waveform
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Debugging Tools
DataLog
 Provides information on what tests are passing and what tests
are failing
 Helpful in determining if failure is gross or marginal
• Gross: Failed multiple or successive tests
• Marginal: Failed one or few tests with reading close the limit
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Debugging Tools
Histogram
Provides:
 Distribution of results/readings for specific test
 Information on how much yield recovery can be achieved
when the limit is changed
- Derive optimum limit adjustment to maximize yield
 Information of rejects test results with respect to limits.
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Histogram Plot
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Characterization
• The purpose of characterizing a device is to determine the extremes
at which the device will still be operational.
• It involves experimenting with the DUT (different operating
environment) to investigate its behavior using varying input
conditions.
• Certain combinations of input parameters can cause the DUT to
pass/fail. Analyzing these pass/fail regions can tell a lot about the
manufacturing process and the suitability of the chosen test limits.
• Characterization can be performed as part of the regular testing
process, or interactively while trapped at a breakpoint.
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Characterization Tools
The following Characterization Tools are commonly used:
– Shmoo
• 1-Dimensional Shmoo (X-axis only)
Vary one parameter or spec over a range while recording Pass/Fail/Error results
and if the tests provides, the measured value for each point
• 2-Dimensional Shmoo (X and Y-axis)
Vary 2 parameters or specs over a specified ranges
• 3-Dimensional Shmoo (X, Y and Z-axis)
Vary 3 parameters or specs over a specified ranges
– Margin
Vary one parameter or spec over a range. Similar to 1- Dimensional Shmoo.
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Generating Characterization Data
• The following steps are used to setup and execute a
Characterization Event:
1. For each Characterization Event ,
• Create Setup
– Name
– Mode
– Parameters to Vary
– Range
– Point Generation
2. Execute the Characterization Setup either
• from Test Flow
• Interactively
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Characterization Editor Entries
• Mode Selection
• Type of Parameter to Vary
– Spec (AC Spec, DC Spec)
– Level
– Edge
– Period
• Search Range
– Search From
– Search To
• Test Method
– Retest (execute instance)
– Reburst (execute pattern burst)
• Output Selection
– Worksheet
– File
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Shmoo
Shmoo

Shmoo is a utility to debug and characterize devices.

Shmoo is useful for determining the passing limits of
voltage, current, timing or other device parameters while
fine tuning the test program for its specific application.

Shmoo produces a graphical plot or view of the behavior
of a device under test (DUT) while the value (settings) of
control parameters are changed.
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Shmoo Result
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Shmoo Setup - Tracking Parameters
• A Shmoo Plot can allow multiple
parameters to be varied along an
axis.
• The first parameter is generally
defined for an axis as the ‘Primary’
parameter. All other parameters
for that axis are ‘Tracking’
parameters.
• A Tracking parameter will always
use a Linear Search Algorithm.
Each Tracking parameter will
have its own range but will change
in ‘lock step’ with the Primary
parameter.
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Debugging Tools
Pattern Debug
 History Ram (HRAM) provides information on Pass/Fail
vector (first failing vector, failing vector count etc) and
device pin information (which pin fail, how many pins
fail etc).
 Logic Analyzer provides information on expected logic
state as well as actual device pin state with respect to
voltage levels / timing edges.
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Pattern Tool
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Debugging Tools
Waveform Tool
 The waveform tool is a very useful tool for debugging,
especially in analog/mixed-signal tests
 Display actual waveform of input and output signals,
amplitude, timing, frequency information.
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Waveform Tool
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Possible Cause for a Failure
The possible cause for a test failure could be any of these
DUT failure
Test hardware interface problem
(Loadboard, socket, pogo pins)
Test system
Test program
Trouble-shooting is needed to identify the exact cause of the
failure
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Basic Troubleshooting Techniques
• Run the test and get the Test Datalog.
• Finding out what is failing from Datalog.
• Check if Failure Continuity, DC, Functional or Leakage
The following slides will explain “what to check?” and the
“Purpose of these checks”
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Basic Troubleshooting Techniques
Continuity Failure
What to Check
1. Identify failing pin from datalog.
2. Check the failure pin reading.
Trace circuit path along the
connection (Testhead up to DUT pin)
using an external meter.
3. Verify if a problematic contact is at
receptacle, socket or DUT itself.
Purpose
• Isolate failing DUT pin
• Check for open or short failure.
• Identify specific area of
problem (Testhead, loadboard,
receptacle, socket, DUT pin)
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Basic Troubleshooting Techniques
Purpose
What to Check
4. Verify Loadboard for any wire
disconnected.
• identify wiring/loadboard problem
5. Test a known good device.
• isolate if it is a device problem.
6. Restart and recalibrate the
tester (if known-good device also
fails)
• Check if it is a test system problem
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Basic Troubleshooting Techniques
Leakage Failure
What to Check
1. Identify failing pin from datalog
2. If marginal:
- Try adding/increasing settling time prior to meter measurement.
- Try relaxing input level (VIL/VIH) prior to pattern run.
- Recommend for limit relaxation.
3. If gross failure:
- Verify if precondition pattern is passing.
- Try adjusting input or output timing.
Purpose
- Determine whether the failure is gross or marginal.
- Recommend probable fix for gross and marginal failures.
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Basic Troubleshooting Techniques
Digital Functional Failure
What to Check
1. Identify VDD level failure using datalog (Continue-on-fail).
2. If marginal, check „ringing‟ at supply, check filter capacitors.
3. Do functional debug using tools like Pattern Debug, Logic Analyzer and
Shmoo plot.
4. Adjust timing/levels/mask transition points whichever is applicable based
from item 3 analysis.
Purpose
- Determine failure is at which VDD level (min, max or nom), check for
marginality.
- Ensure that filter capacitors are in place and good.
- Determine if it is timing/levels related. Check critical transition points.
- Check criticality of input levels.
- Determine impact of Program change
if the problem can be resolved.
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Basic Troubleshooting Techniques
Other Functional Failure
What to Check
1. Identify failing DUT pin and test.
2. Check if precondition pattern fails using digital debug tools.
3. Using waveform tool, check waveform at Input and Output.
4. Using a scope, trace signal from input to output at different points along
the path.
Purpose
- Determine specific test and DUT pins failing.
- Determine whether failure is caused by pattern.
- Determine if tester is supplying, and capturing the expected signals
- Determine at which point along the path, the signal is degrading or missing.
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Production-Ready Test Program
• Customer‟s Approval
• Repeatability check
• Test Program Backup
• Test Plan Matrix
• Loadboard Schematic
• Test Program Revision Number, Date and History
• Full Datalog for 10 Good units
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Self-Assess Questions
•
What is the purpose of doing device characterization?
•
What is the different between Shmoo and Margin Tool?
•
State 3 possible causes of a test failure
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Introduction to
Design-For-Testability (DFT)
Design For Test or DFT
Delay-inducing defects are causing increasing concern in the
semiconductor industry today, particularly at the leading-edge
130nm and 90nm nodes. To effectively test for such defects, the
at-speed behavior of the logic has to be emulated in the most
cost-effective way possible.
Design for test is the test concept with which ,while designing a
chip, a small module is added to test its functionality.
DFT refers the design technique that make test generation and
test application cost effective.
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Design For Test
Chip with DFT Module
Input pin for
DFT
DFT
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Output pin from
DFT
453
Testability - DFT
An internal fault can be very difficult to check if there is no
specific structure.
It can only be tested if the input of the structure can be
controlled and the output can be observed.
An ideal case would require that all nodes can be controlled
and observed.
Is this node ok ?
Logic
Controlling
The node
Logic
Propagating
The fault
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Why Design For Test
High speed testers are very costly
Reducing test time can help increase throughput of tester, this
impacts (lowers) testing cost
Testing must be considered at early phases of the design
process
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Cost of Testing
Design for testability (DFT)
– Chip area overhead
– Performance overhead
Software processes of test
– Test generation and fault simulation
– Test programming and debugging
Manufacturing test
– Automatic test equipment (ATE) capital cost
– Test center operational cost
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Advantages of DFT
Directly observable internal nodes.
Direct controllability of internal nodes.
Enables combinational ATPG.
Multiple balanced scan chain results in very efficient test
vectors.
Efficient diagnostic capability.
Enables testing of both timing and structure.
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Disadvantages of DFT
Scan hardware increases chip size.
Compressed scan vectors increases the chips power
consumption.
Design rules may require bypass clock inputs.
May have a large impact on total design budget.
Requires additional control logic to guarantee safe scan
shifting and sampling.
Requires more concern about clock-delay and clock-skew.
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Benefits and Trade-offs of DFT
The major benefits of using Design for Testability are:
– Shorter time to market
– Reduced test time
– Inexpensive test equipment
– Yield learning, which is often overlooked
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Benefits and Trade-offs of DFT
The implementation of DFT involves some sacrifices
– Increased area of components
– More pins on the PCB
– Increased PCB area
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Test Approaches
Three approaches
Ad-hoc testing
Scan-based testing
Self-test
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Ad-hoc Test
data
address
data
test
select
address
Memory
Memory
Processor
Processor
I/O bus
I/O bus
Inserting multiplexer improves testability
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Ad-hoc Test
For Ad-hoc test ,Good design practices learnt through
experience are used as guide lines
Avoid Asynchronous (un-clocked) feedback
Make flip-flop initialize
Avoid redundant gates. Avoid large fan-in gates
Avoid gated clocks
Design reviews conducted by experts or design auditing
tools.
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Disadvantages of Adhoc testing
Experts and tools not always available
Test generation is often manual with no guarantee of high
fault coverage
Difficult to estimate/guarantee fault coverage
Design iterations may be necessary
These techniques can be used for small designs
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Scan-based Test
ScanIn
Combinational
Logic
A
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Register
Register
In
ScanOut
Combinational
Out
Logic
B
465
Introduction to Scan
A typical device, without scan cells, processes data through
the functional logic as usual.
+5v
VCC
GND
DUT
AIN
AOUT
0
BIN
BOUT
1
CIN
COUT
0
DIN
DOUT
1
NC
NC
functional
logic
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Scan Cells
Likewise, device with scan cells can process data through the
functional logic as usual, bypassing the scan chain.
Here, data passes between device pins and the functional logic
through scan cells.
+5v
VCC
GND
DUT
AIN
BIN
CIN
DIN
scan cell
scan cell
AOUT
0
scan cell
scan cell
BOUT
1
scan cell
scan cell
COUT
0
scan cell
scan cell
DOUT
1
TDI
TDO
scan chain
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Scan Chain
■
However, a device with scan also allows data to be loaded
through the scan chain and stored in the scan cells.
The data is then processed through the functional logic,
changing the values stored in the output scan chains.
The output scan data can then be checked by shifting the
data out the scan chain.
+5v
0
VCC
0
AIN
1
GND
DUT
scan cell
0 1
scan cell
1
AOUT
scan cell
1
scan cell
0
BOUT
CIN
scan cell0
0
scan cell
1
COUT
DIN
1
scan cell
1 1
scan cell
0
DOUT
BIN
0
TDI
10101010
input data
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TDO
10100101
output
data
468
Microcircuit Testing
Device designer develops scan vectors automatically using
fault coverage and test simulation tools.
Scan reduces test program development time.
Scan allows direct access to the device registers reducing
test time by removing unnecessary overhead though
functional test methods.
Scan improves fault coverage and diagnostics at device and
board test.
scan pins
SN74BCT245
octal bus transceiver
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DFT & Scan
scan pins
SN74BCT8245A
octal bus transceiver with scan
469
SN74BCT8245A With Scan
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Why Scan Test
In a sequential circuit it is difficult to form test vectors for
stuck-at-faults because the sequential depth of the design
easily makes the test vectors to large.
The main idea with scan design is to obtain control and
observe flip-flops and thus making it easier to form test
vectors.
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Scan Design
Circuit is designed using pre-specified design rules.
Test structure (hardware) is added to the verified design.
•
Replace flip flops by scan flip flops (SFF) and connect to form one or
more shift registers in the test mode
• Make input/output of each scan shift register controllable or
observable from PI/PO
• Use ATPG tools to obtain tests for all testable faults in the
combinational logic
• Add shift register tests and convert ATPG tests into scan sequences
for use in manufacturing test
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A fault model : Stuck @ 0/1
The fault model is commonly used for Logic device
It is applied on primitive elements such as Nand/Nor gates…
The model can be extended to Nodes
– Stuck at zero or node stuck at logic 0
– Stuck at one or node stuck at logic 1
Set input condition
Look for faulty output
A
&
Out
B
A
B
Out
FAULT
0
0
1
0
0
1
1
0
1
0
1
0
1
1
0
1
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Design Example
1
1
1
Is this node stuck at 1?
0
1
0
0
0
0
0
To check the node, Ain, Bin and Cin should be at the following
values 0,1,1. If it is stuck at 1, the fault propagates to OUT0.
How to do that if the inputs are not easily accessible ?
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Design Example (cont..)
Scan flip-flop
(scan cell)
Stuck @ 1 ?
Normal Mode of Operation
Add a multiplexer to every flip-flops, chain them together
Add a Scan_sel signal to select the mode and a Scan_in to provide
data
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Design Example (cont..)
1
1
1
1
0
Scan in data =1110
Select the scan mode and scan data in. (4 clocks needed)
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More about Scan
Scan is the most popular DFT technique
– Rule based design
– Automated DFT hardware insertion
– Combinational ATPG
Advantages
– Design automation
– High fault coverage;helpful in diagnosis
– Hierarchical-scan testable modules are easily combined into large
scan-testable systems
– Moderate area (~10%) and speed (~5%) overheads
Disadvantages
– Large test data volume and long test time
– Basically a slow speed(DC) test
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Boundary Scan
Printed-circuit board
Logic
Scan-out
si
so
scan path
normal interconnect
Scan-in
Packaged IC
Bonding Pad
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Boundary-Scan Architecture
Device
Logic
functional
input pins
functional
output pins
Bypass Register
scan cells
Instruction Register
Test Access Port (TAP)
TDI
TCK
TMS
TRST*
TDO
scan pins
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Boundary-Scan
Boundary-scan testing is controlled by a Test Access Port (TAP)
Controller.
The TMS, TRST, and TCK pins operate the TAP controller, and
the TDI and TDO pins provide the serial path for the data
registers. The TDI pin also provides data to the instruction
register, which then generates control logic for the data
registers.
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Scan Standard
The IEEE Std. 1149.1 was approved by the Joint Test Action
Group (JTAG) on February 19, 1990.
As a result, IEEE Std. 1149.1 is often referred to as JTAG
1149.1 boundary scan.
The scan interface uses a block of control logic called a test
access port (TAP).
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Scan Standard
Scan architecture uses five signals;
1. Test Clock (TCK)
2. Test mode select (TMS)
3. Test Data in (TDI )
4. Test data out (TDO)
5. Test reset (TRST)
Test bus uses both clock edges of the TCK:
1) TMS and TDI are sampled on the rising edge of TCK
2) TDO changes on the falling edge of TCK
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TAP Signals
Test Clock (TCK): The test clock input provides the clock for the test
logic. TCK is a dedicated input that allows the serial test data path to be
used independent of component-specific system clocks. It also permits
shifting of test data concurrently with normal component operation.
Test Data Input (TDI): TDI provides serial input for test instructions
shifted into the Instruction Register and for data shifted through the
Boundary Register or other data registers. Values are clocked into the
selected register on a rising edge of TCK.
Test Data Output (TDO): TDO is the serial output for test
instructions and data from the Boundary Register or other data registers.
The contents of the selected register (instruction or data) are shifted out on
the falling edge of TCK.
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TAP Signals (Cont..)
Test Mode Select (TMS): The logic level of TMS, along with a rising
edge applied to TCK, cause the movement from one state to another through
the TAP controller. This, in turn, allows movement of data and TAP
instructions through the state machine.
Test Reset (TRST*): This optional input provides asynchronous
initialization of the TAP Controller, which in turn causes asynchronous
initialization of other test logic included in the design. The reset places the
device in the normal operating mode and makes the Boundary Register
inactive.
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PROS and CONS of Boundary Scan
Less overhead than Scan design
Less expensive test equipment
IC‟s tested at their complete, interconnected
environment.
Circuits with boundary scan are expensive and they can be hard
to find
Requires quite expensive software and equipment
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Built-in Self-Test (BIST)
(Sub)-Circuit
Stimulus Generator
Under
Response Analyzer
Test
Test Controller
Rapidly becoming more important with increasing
chip-complexity and larger modules
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WHY BIST
Since circuits today are more dense, faster, with smaller size,
and that the logic-to-pin ratio on chips is increasing, it makes the
testing of logic difficult.
It takes longer time to generate test patterns and the patterns
consume lot of memory.
Therefore it has becoming important to implement different kind
of logic into the design so it can test itself, which is what we
called BIST.
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PROS and CONS of BIST
High fault coverage
Able to run test at full speed
All response analyzers have aliasing probability
Requires quite much hardware to get good fault coverage.
It is difficult to get a good BIST with less overhead to the
circuit.
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DFT Summary
Main DFT techniques used today are Scan design,
Built-in- Self-Test and Boundary scan.
The choice of a DFT depends largely on its benefit-tocost ratio.
There are cost models used to help in this DFT decision,
where factors like quality and volume are considered.
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Self-Assess Questions
•
A Full Scan Design replaces all normal flip-flops with Scan flip-flops.
(True / False)
•
Adding Scan design to a circuit will generally result in a decrease in
pin count. (True / False)
•
DFT logic improves the ability to observe and debug circuit
performance (True / False)
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