Datasheet - STMicroelectronics

Datasheet - STMicroelectronics
STM32F303x6/x8
ARM®Cortex®-M4 32b MCU+FPU, up to 64KB Flash, 16KB SRAM
2 ADCs, 3 DACs, 3 comp., op-amp 2.0 - 3.6 V
Datasheet - production data
Features
• Core: ARM® Cortex®-M4 32-bit CPU with FPU
(72 MHz max), single-cycle multiplication and
HW division, 90 DMIPS (from CCM), DSP
instruction
• Memories
– Up to 64 Kbytes of Flash memory
– 12 Kbytes of SRAM with HW parity check
– Routine booster: 4 Kbytes of SRAM on
instruction and data bus with HW parity
check (CCM)
• CRC calculation unit
• Reset and supply management
– Low-power modes: Sleep, Stop, Standby
– VDD,VDDA voltage range: 2.0 to 3.6 V
– Power-on/Power-down reset (POR/PDR)
– Programmable voltage detector (PVD)
– VBAT supply for RTC and backup registers
• Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC (up to 64 MHz with PLL
option)
– Internal 40 kHz oscillator
• Up to 51 fast I/O ports, all mappable on
external interrupt vectors, several 5 V-tolerant
• Interconnect Matrix
• Up to two ADC 0.20 µs (up to 21 channels) with
selectable resolution of 12/10/8/6 bits, 0 to
3.6 V conversion range, singleended/differential mode, separate analog
supply from 2.0 to 3.6 V
• Temperature sensor
• Up to three 12-bit DAC channels with analog
supply from 2.4 V to 3.6 V
This is information on a product in full production.
LQFP48 (7 x 7 mm)
LQFP64 (10 x 10 mm)
• Three ultra-fast rail-to-rail analog comparators
with analog supply from 2 V to 3.6 V
• One operational amplifiers that can be used in
PGA mode, all terminals accessible with
analog supply from 2.4 to 3.6 V
• Up to 18 capacitive sensing channels
supporting touchkeys, linear and rotary touch
sensors
• Up to 11 timers
– One 32-bit timer and one 16-bit timer with
up to 4 IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– One 16-bit 6-channel advanced-control
timer, with up to 6 PWM channels,
deadtime generation and emergency stop
– One 16-bit timer with 2 IC/OCs,
1 OCN/PWM, deadtime generation,
emergency stop
– Two 16-bit timers with IC/OC/OCN/PWM,
deadtime generation and emergency stop
– Two watchdog timers (independent,
window)
– SysTick timer: 24-bit downcounter
– Up to two 16-bit basic timers to drive DAC
• Calendar RTC with alarm, periodic wakeup
from Stop
• 7-channel DMA controller
October 2016
LQFP32 (7 x 7 mm)
• Communication interfaces
– CAN interface (2.0 B Active) and one SPI
– One I2C with 20 mA current sink to support
Fast mode plus, SMBus/PMBus
– Up to 3 USARTs, one with ISO/IEC 7816
interface, LIN, IrDA, modem control
• Debug mode: serial wire debug (SWD), JTAG
DocID025083 Rev 5
1/115
www.st.com
STM32F303x6/x8
• 96-bit unique ID
• All packages ECOPACK®2
Table 1. Device summary
2/115
Reference
Part number
STM32F303x6
STM32F303K6/C6/R6
STM32F303x8
STM32F303K8/C8/R8
DocID025083 Rev 5
STM32F303x6/x8
Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
ARM® Cortex®-M4 core with FPU with embedded Flash
and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.3
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14
3.4
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4.1
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5
Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.8
Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10
3.9.1
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 19
3.9.2
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 19
Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10.3
VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10.4
OPAMP2 reference voltage (VOPAMP2) . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12
Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.13
Ultra-fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DocID025083 Rev 5
3/115
5
Contents
STM32F303x6/x8
3.14.1
Advanced timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.2
General-purpose timers (TIM2, TIM3, TIM15, TIM16, TIM17) . . . . . . . . 23
3.14.3
Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.4
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.14.5
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.14.6
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.15
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 24
3.16
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.16.1
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.16.2
Universal synchronous / asynchronous
receivers / transmitters (USARTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.16.3
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.16.4
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.17
Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.19
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.19.1
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 30
4
Pinout and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1
4/115
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.5
Input voltage on a pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.6
Power-supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.1.7
Measurement of the current consumption . . . . . . . . . . . . . . . . . . . . . . . 46
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 50
6.3.3
Characteristics of the embedded reset and power-control block . . . . . . 50
6.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DocID025083 Rev 5
STM32F303x6/x8
7
Contents
6.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3.6
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.7
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.8
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.9
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.10
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.12
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.15
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.16
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.17
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.18
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.19
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3.20
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.21
Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3.22
Temperature sensor (TS) characteristics . . . . . . . . . . . . . . . . . . . . . . . 100
6.3.23
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.2
LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.3
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.4
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.5
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.5.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.5.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 111
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
DocID025083 Rev 5
5/115
5
List of tables
STM32F303x6/x8
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
6/115
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32F303x6/8 family device features and peripherals count . . . . . . . . . . . . . . . . . . . . . 11
VDDA ranges for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STM32F303x6/8 peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32F303x6/8 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM32F303x6/8 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Capacitive sensing GPIOs available on STM32F303x6/8 devices . . . . . . . . . . . . . . . . . . . 28
Capacitive sensing GPIO available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
No. of capacitive sensing channels available on STM32F303x6/8 devices . . . . . . . . . . . . 30
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32F303x6/8 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STM32F303x6/8 peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . 42
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 50
Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Typical and maximum current consumption from VDD supply at VDD = 3.6V . . . . . . . . . . . 53
Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 54
Typical and maximum VDD consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 54
Typical and maximum VDDA consumption in Stop and Standby modes. . . . . . . . . . . . . . . 55
Typical and maximum current consumption from VBAT supply. . . . . . . . . . . . . . . . . . . . . . 55
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Typical current consumption in Run mode, code with data processing
running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 59
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Wakeup time using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DocID025083 Rev 5
STM32F303x6/x8
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
List of tables
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
IWDG min./max. timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
WWDG min./max. timeout value at 72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
I2C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
ADC accuracy at 1MSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Temperature sensor (TS) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Temperature sensor (TS) calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
LQFP48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
DocID025083 Rev 5
7/115
7
List of figures
STM32F303x6/x8
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
8/115
STM32F303x6/8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM32F303x6/8 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Power-supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Scheme of the current-consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’) . . . . . . . . . . . 56
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 70
TC and TTa I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5V- tolerant (FT and FTf) I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . 77
5V-tolerant (FT and FTf) I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . 77
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ADC typical current consumption in single-ended and differential modes . . . . . . . . . . . . . 88
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Maximum VREFINT scaler startup time from power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 97
OPAMP Voltage Noise versus Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Recommended footprint for the LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Recommended footprint for the LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Recommended footprint for the LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
DocID025083 Rev 5
STM32F303x6/x8
1
Introduction
Introduction
This datasheet provides the ordering information and the mechanical device characteristics
of the STM32F303x6/8 microcontrollers.
This document should be read in conjunction with the STM32F303xx, STM32F358xx and
STM32F328xx advanced ARM®-based 32-bit MCUs reference manual (RM00316)
available from the STMicroelectronics website www.st.com.
For information on the Cortex®-M4 core with FPU, refer to:
•
ARM® Cortex®-M4 Processor Technical Reference Manual available from the
www.arm.com website.
•
STM32F3xxx and STM32F4xxx Cortex®-M4 programming manual (PM0214) available
from the www.st.com website.
DocID025083 Rev 5
9/115
43
Description
2
STM32F303x6/x8
Description
The STM32F303x6/8 family incorporates the high-performance ARM® Cortex®-M4 32-bit
RISC core operating at up to 72 MHz frequency embedding a floating point unit (FPU),
high-speed embedded memories (up to 64 Kbytes of Flash memory, 12 Kbytes of SRAM),
and an extensive range of enhanced I/Os and peripherals connected to two APB buses.
The STM32F303x6/8 microcontrollers offer up to two fast 12-bit ADCs (5 Msps), up to three
ultra-fast comparators, an operational amplifier, three DAC channels, a low-power RTC, one
general-purpose, 32-bit timer, one timer dedicated to motor control, and four
general-purpose, 16-bit timers. They also feature standard and advanced communication
interfaces: one I2C, one SPI, up to three USARTs and one CAN.
The STM32F303x6/8 family operates in the –40 to +85 °C and –40 to +105 °C temperature
ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes
allows the design of low-power applications.
The STM32F303x6/8 family offers devices in 32, and 64-pin packages.
Depending on the device chosen, different sets of peripherals are included.
10/115
DocID025083 Rev 5
STM32F303x6/x8
Description
Table 2. STM32F303x6/8 family device features and peripherals count
Peripheral
Flash (Kbytes)
STM32F303Kx
STM32F303Cx
STM32F303Rx
32
32
32
64
64
SRAM on data bus (Kbytes)
12
Core coupled memory SRAM on
instruction bus (CCM SRAM) (Kbytes)
4
Timers
Comm. interfaces
Advanced control
1 (16-bit)
General purpose
4 (16-bit)
1 (32 bit)
Basic
2 (16-bit)
SysTick timer
1
Watchdog timers
(independent,
window)
2
PWM channels
(all)(1)
20
22
22
PWM channels
(except
complementary)
14
16
16
SPI
1
2C
1
I
USART
2
CAN
GPIOs
3
3
1
Normal I/Os (TC,
TTa)
10
20
26
5-Volt tolerant I/Os
(FT,FTf)
15
17
25
14
17
18
Capacitive sensing channels
DMA channels
12-bit ADCs
Number of channels
7
2
9
12-bit DAC channels
Ultra-fast analog comparator
2
2
21
3
1
CPU frequency
72 MHz
Operating voltage
Operating temperature
2
15
3
Operational amplifiers
Packages
64
2.0 to 3.6 V
Ambient operating temperature: - 40 to 85 °C / - 40 to 105 °C
Junction temperature: - 40 to 125 °C
LQFP32
LQFP48
LQFP64
1. This total considers also the PWMs generated on the complementary output channels.
DocID025083 Rev 5
11/115
43
Description
STM32F303x6/x8
Figure 1. STM32F303x6/8 block diagram
#9''
6:-7$*
)38
2EO
)ODVK
LQWHUIDFH
73,8
,EXV
&257(;0&38
'EXV
)
PD[
0+]
6\VWHP
EXV
19,&
%XV0DWUL[
-7567
-7',
-7&.6:&/.
-7066:'$7
-7'275$&(6:2
DV$)
'EXV
32:(5
9''
)ODVK.%
ELWV
92/75(*
9729
9 ''
WR9
9
66
#9''$
65$0
.%
#9''$
&&065$0
.%
6833/<
683(59,6,21
325
5HVHW
,QW
3253'5
5&+60+]
39'
5&/6
*3'0$
FKDQQHOV
#9''
;7$/26&
0+]
3//
15(6(7
9''$
966$
26&B,1
26&B287
,QG:'*.
7HPSVHQVRU
ELW$'& ,)
,)
ELW$'& ,)
,)
$+%'(&2'(5
95()
95()
5(6(7
&/2&.
&75/
#9''$
3$>@
*3,23257$
3%>@
*3,23257%
3&>@
*3,23257&
3'
*3,23257'
3)>@
*URXSVRI
&KDQQHOVDV$)
;7$/N+]
57&
$:8
%DFNXS
UHJ%
9%$7
WR9
26&B,1
26&B287
$17,7$03
%DFNXSLQWHUIDFH
7,0ELW3:0
&5&
*3,23257)
7RXFK6HQVLQJ
&RQWUROOHU
&KDQQHOV(75
DV$)
&KDQQHOV(75
DV$)
86$57
5;7;&76576
6PDUW&DUGDV$)
86$57
5;7;&76576
6PDUW&DUGDV$)
,&
6&/6'$60%$
DV$)
$+%
$3%
(;7,7
:.83
FKDQQHO
FRPSOFKDQQHO
%5.DV$)
7,0
FKDQQHO
FRPSOFKDQQHO
%5.DV$)
7,0
FKDQQHOV
FRPSOFKDQQHO
(75%5.DV$)
7,0
026,0,62
6&.166DV$)
63,
$3%)PD[ 0+]
7,0
$3%)PD[ 0+]
:LQ:$7&+'2*
FKDQQHOV
FRPSOFKDQQHO
%5.DV$)
5;7;&76576
6PDUW&DUGDV$)
6WDQGE\
LQWHUIDFH
7,0
$+%
$3%
8SWROLQHV
$+%3&/.
$3%3&/.
$3%3&/.
+&/.
)&/.
86$57&/.
&(&&/.
$'&$'&
7,0
%[&$1
,)
ELW'$&
FKDQQHO ,)
'$&B287DV$)
,)
ELW'$&
FKDQQHO ,)
'$&B287DV$)
,)
ELW'$&
FKDQQHO
'$&B287DV$)
7,0
86$57
6<6&)*&7/
#9''$
&$1B7;
&$1B5;
,)
2SDPS,)
,10,13287DV$)
#9''$
*3&RPSDUDWRU
*3&RPSDUDWRU
*3&RPSDUDWRU
,10,13287DV$)
1. AF: alternate function on I/O pins.
12/115
DocID025083 Rev 5
06Y9
STM32F303x6/x8
Functional overview
3
Functional overview
3.1
ARM® Cortex®-M4 core with FPU with embedded Flash
and SRAM
The ARM Cortex-M4 processor with FPU is the latest generation of ARM processors for
embedded systems. It has been developed to provide a low-cost platform that meets the
needs of MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The ARM 32-bit Cortex-M4 RISC processor with FPU features exceptional code-efficiency,
delivering the high performance expected from an ARM core, with memory sizes usually
associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allows efficient signal processing
and complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded ARM core, the STM32F303x6/8 family is compatible with all ARM tools
and software.
Figure 1 shows the general block diagram of the STM32F303x6/8 family devices.
3.2
Memories
3.2.1
Embedded Flash memory
All STM32F303x6/8 devices feature up to 64 Kbytes of embedded Flash memory available
for storing programs and data. The Flash memory access time is adjusted to the CPU clock
frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states
above).
3.2.2
Embedded SRAM
The STM32F303x6/8 devices feature 12 Kbytes of embedded SRAM with hardware parity
check. The memory can be accessed in read/write at CPU clock speed with 0 wait states,
allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz when running code from CCM
(core coupled memory) RAM.
The SRAM is organized as follows:
•
4 Kbytes of SRAM on instruction and data bus with parity check (core coupled memory
or CCM) and used to execute critical routines or to access data
•
12 Kbytes of SRAM with parity check mapped on the data bus.
DocID025083 Rev 5
13/115
43
Functional overview
3.2.3
STM32F303x6/x8
Boot modes
At startup, BOOT0 pin and BOOT1 option bit are used to select one of the three boot
options:
•
Boot from user Flash memory
•
Boot from System Memory
•
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1 (PA9/PA10), USART2 (PA2/PA3), I2C1 (PB6/PB7).
3.3
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
3.4
Power management
3.4.1
Power supply schemes
•
VSS, VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is
provided externally through VDD pins.
•
VSSA, VDDA = 2.0 to 3.6 V: external analog power supply for ADC, DACs, comparators
operational amplifiers, reset blocks, RCs and PLL.The minimum voltage to be applied
to VDDA differs from one analog peripherals to another. See the Table 3 below,
summarizing the VDDA ranges for analog peripherals. The VDDA voltage level must be
always greater or equal to the VDD voltage level and must be provided first.
•
VDD18 = 1.65 to 1.95 V (VDD18 domain): power supply for digital core, SRAM and Flash
memory. VDD18 is internally generated through an internal voltage regulator.
Table 3. VDDA ranges for analog peripherals
Analog peripheral
Min VDDAsupply
Max VDDAsupply
ADC/COMP
2V
3.6 V
DAC/OPAMP
2.4 V
3.6 V
•
3.4.2
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Power supply supervisor
The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
14/115
DocID025083 Rev 5
STM32F303x6/x8
Functional overview
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
•
The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
•
The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.4.3
Voltage regulator
The regulator has three operation modes: main (MR), low-power (LPR), and power-down.
•
The MR mode is used in the nominal regulation mode (Run)
•
The LPR mode is used in Stop mode.
•
The power-down mode is used in Standby mode: the regulator output is in high
impedance, and the kernel circuitry is powered down thus inducing zero consumption.
The voltage regulator is always enabled after reset. It is disabled in Standby mode.
3.4.4
Low-power modes
The STM32F303x6/8 supports three low-power modes to achieve the best compromise
between low power consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm, COMPx,
I2C or USARTx.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
DocID025083 Rev 5
15/115
43
Functional overview
3.5
STM32F303x6/x8
Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Table 4. STM32F303x6/8 peripheral interconnect matrix
Interconnect source
Interconnect
destination
Interconnect action
TIMx
Timers synchronization or chaining
ADCx
DACx
Conversion triggers
DMA
Memory to memory transfer trigger
COMPx
Comparator output blanking
COMPx
TIMx
Timer input: ocrefclear input, input capture
ADCx
TIM1
Timer triggered by analog watchdog
GPIO
RTCCLK
HSE/32
MC0
TIM16
Clock source used as input channel for HSI and
LSI calibration
CSS
CPU (hard fault)
RAM (parity error)
COMPx
PVD
GPIO
TIM1
TIM15, 16, 17
Timer break
TIMx
External trigger, timer break
GPIO
ADCx
DACx
Conversion external trigger
DACx
COMPx
Comparator inverting input
TIMx
Note:
For more details about the interconnect actions, refer to the corresponding sections in the
RM0364 reference manual.
3.6
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
Several prescalers allow to configure the AHB frequency, the high-speed APB (APB2) and
the low-speed APB (APB1) domains. The maximum frequency of the AHB and the
16/115
DocID025083 Rev 5
STM32F303x6/x8
Functional overview
high-speed APB domains is 72 MHz, while the maximum allowed frequency of the lowspeed APB domain is 36 MHz.
TIM1 maximum frequency is 144 MHz.
DocID025083 Rev 5
17/115
43
Functional overview
STM32F303x6/x8
Figure 2. Clock tree
&>/d&><
ƚŽ&ůĂƐŚƉƌŽŐƌĂŵŵŝŶŐŝŶƚĞƌĨĂĐĞ
,^/
ƚŽ/Ϯϭ
^z^><
ϴD,nj
,^/
,^/Z
ͬϮ
,><
W>>^Z
ƚŽĐŽƌƚĞdž^LJƐƚĞŵƚŝŵĞƌ
ͬϴ
^t
W>>Dh>
ƚŽ,ďƵƐ͕ĐŽƌĞ͕
ŵĞŵŽƌLJĂŶĚD
&,><ŽƌƚĞdžĨƌĞĞ
,^/
džϮ͕džϯ͕͘͘
,
,
ƉƌĞƐĐĂůĞƌ
ƉƌĞƐĐĂůĞƌ
džϭϲ
ͬϭ͕Ϯ͕͘͘ϱϭϮ
ͬϭ͕Ϯ͕ϰ͕ϴ͕ϭϲ
W>>
W>>><
,^
Wϭ
ƌƵŶŶŝŶŐĐůŽĐŬ
W><ϭ
ƚŽWϭƉĞƌŝƉŚĞƌĂůƐ
^z^><
/Ĩ;WϭƉƌĞƐĐĂůĞƌ
^^
ͬϮ͕ͬϯ͕͘͘͘
сϭͿdžϭĞůƐĞdžϮ
ͬϭϲ
ƚŽd/DϮ͕ϯ͕ϲ͕ϳ
W><ϭ
^z^><
,^/
K^ͺKhd
ϰͲϯϮD,nj
K^ͺ/E
>^
,^K^
WϮ
W><Ϯ
ƉƌĞƐĐĂůĞƌ
K^ϯϮͺKhd
Zd><
>^K^
ϯϮ͘ϳϲϴŬ,nj
ƚŽWϮƉĞƌŝƉŚĞƌĂůƐ
ͬϭ͕Ϯ͕ϰ͕ϴ͕ϭϲ
ͬϯϮ
K^ϯϮͺ/E
ƚŽh^Zdϭ
ƚŽZd
/Ĩ;WϮƉƌĞƐĐĂůĞƌ
>^
ƚŽd/Dϭϱ͕ϭϲ͕ϭϳ
сϭͿdžϭĞůƐĞdžϮ
Zd^>΀ϭ͗Ϭ΁
>^/Z
>^/
/t'><
ƚŽ/t'
ϰϬŬ,nj
W>>EK/s
DKWZ
ͬϮ
DK
W>>><
džϮ
,^/
ͬϭ͕Ϯ͕ϰ͕
͘͘͘ϭϮϴ
d/Dϭͬ
,Zd/Dϭ
>^/
,^
^z^><
DĂŝŶĐůŽĐŬ
ŽƵƚƉƵƚ
DK
WƌĞƐĐĂůĞƌ
ͬϭ͕Ϯ͕ϰ
ƚŽdž
;džсϭ͕ϮͿ
WƌĞƐĐĂůĞƌ
ͬϭ͕Ϯ͕ϰ͕ϲ͕ϴ͕ϭϬ͕ϭϮ͕ϭϲ͕
ϯϮ͕ϲϰ͕ϭϮϴ͕Ϯϱϲ
06Y9
18/115
DocID025083 Rev 5
STM32F303x6/x8
3.7
Functional overview
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed, following a specific
sequence to avoid spurious writing to the I/Os registers.
Fast I/O handling allows I/O toggling up to 36 MHz.
3.8
Direct memory access (DMA)
The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-tomemory and memory-to-peripheral transfers. The DMA controller supports circular buffer
management, avoiding the generation of interrupts when the controller reaches the end of
the buffer.
Each of the 7 DMA channels is connected to dedicated hardware DMA requests, with
software trigger support for each channel. Configuration is done by software and transfer
sizes between source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers,
DAC and ADC.
3.9
Interrupts and events
3.9.1
Nested vectored interrupt controller (NVIC)
The STM32F303x6/8 devices embed a nested vectored interrupt controller (NVIC) able to
handle up to 60 interrupt channels, that can be masked and 16 priority levels.
The NVIC benefits are the following:
•
Closely coupled NVIC gives low latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Closely coupled NVIC core interface
•
Allows early processing of interrupts
•
Processing of late arriving higher priority interrupts
•
Support for tail chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.9.2
Extended interrupt/event controller (EXTI)
The external interrupt/event controller consists of 27 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
DocID025083 Rev 5
19/115
43
Functional overview
STM32F303x6/x8
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 51
GPIOs can be connected to the 16 external interrupt lines.
3.10
Fast analog-to-digital converter (ADC)
Two 5 MSPS fast analog-to-digital converters, with selectable resolution between 12 and 6
bit, are embedded in the STM32F303x6/8 family devices. The ADCs have up to 21 external
channels. Some of the external channels are shared between ADC1 and ADC2, performing
conversions in single-shot or scan modes. The channels can be configured to be either
single-ended input or differential input. In scan mode, automatic conversion is performed on
a selected group of analog inputs.
The ADCs also have internal channels: temperature sensor connected to ADC1 channel 16,
VBAT/2 connected to ADC1 channel 17, voltage reference VREFINT connected to both ADC1
and ADC2 channel 18 and VOPAMP2 connected to ADC2 channel 17.
Additional logic functions embedded in the ADC interface allow:
•
Simultaneous sample and hold
•
Interleaved sample and hold
•
Single-shunt phase current reading techniques.
Three analog watchdogs are available per ADC. The ADC can be served by the DMA
controller.
The analog watchdog feature allows very precise monitoring of the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIM2, TIM3, TIM6, TIM15) and the
advanced-control timer (TIM1) can be internally connected to the ADC start trigger and
injection trigger, respectively, to allow the application to synchronize A/D conversion and
timers.
3.10.1
Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC1_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
3.10.2
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC1_IN18 and ADC2_IN18
20/115
DocID025083 Rev 5
STM32F303x6/x8
Functional overview
input channels. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
3.10.3
VBAT battery voltage monitoring
This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC1_IN17. As the VBAT voltage may be higher than VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 2. As a consequence, the converted digital value is half the VBAT voltage.
3.10.4
OPAMP2 reference voltage (VOPAMP2)
OPAMP2 reference voltage can be measured using ADC2 internal channel 17.
3.11
Digital-to-analog converter (DAC)
One 12-bit buffered DAC channel (DAC1_OUT1) and two 12-bit unbuffered DAC channels
(DAC1_OUT2 and DAC2_OUT1) can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in inverting configuration.
This digital interface supports the following features:
3.12
•
Three DAC output channels
•
8-bit or 12-bit monotonic output
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave generation (only on DAC1)
•
Triangular-wave generation (only on DAC1)
•
Dual DAC channel independent or simultaneous conversions
•
DMA capability for each channel
•
External triggers for conversion
Operational amplifier (OPAMP)
The STM32F303x6/8 embeds an operational amplifier (OPAMP2) with external or internal
follower routing and PGA capability (or even amplifier and filter capability with external
components). When an operational amplifier is selected, an external ADC channel is used
to enable output measurement.
The operational amplifier features:
•
8 MHz GBP
•
0.5 mA output capability
•
Rail-to-rail input/output
•
In PGA mode, the gain can be programmed to 2, 4, 8 or 16.
DocID025083 Rev 5
21/115
43
Functional overview
3.13
STM32F303x6/x8
Ultra-fast comparators (COMP)
The STM32F303x6/8 devices embed three ultra-fast rail-to-rail comparators (COMP2/4/6)
which offer the features below:
•
Programmable internal or external reference voltage
•
Selectable output polarity.
The reference voltage can be one of the following:
•
External I/O
•
DAC output
•
Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 24: Embedded
internal reference voltage for values and parameters of the internal reference voltage.
All comparators can wake up from STOP mode, generate interrupts and breaks for the
timers.
3.14
Timers and watchdogs
The STM32F303x6/8 includes advanced control timer, 5 general-purpose timers, basic
timer, two watchdog timers and a SysTick timer. The table below compares the features of
the advanced control, general purpose and basic timers.
Table 5. Timer feature comparison
Timer type
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
Channels
Complementary
outputs
Advanced
control
TIM1(1)
16-bit
Up, Down,
Up/Down
Any integer
between 1
and 65536
Yes
4
Yes
Generalpurpose
TIM2
32-bit
Up, Down,
Up/Down
Any integer
between 1
and 65536
Yes
4
No
Generalpurpose
TIM3
16-bit
Up, Down,
Up/Down
Any integer
between 1
and 65536
Yes
4
No
Generalpurpose
TIM15
16-bit
Up
Any integer
between 1
and 65536
Yes
2
1
Generalpurpose
TIM16,
TIM17
16-bit
Up
Any integer
between 1
and 65536
Yes
1
1
Basic
TIM6, TIM7
16-bit
Up
Any integer
between 1
and 65536
Yes
0
No
1. TIM1 can be clocked from the PLL x 2 running at up to 144 MHz when the system clock source is the PLL and AHB or
APB2 subsystem clocks are not divided by more than 2 cumulatively.
22/115
DocID025083 Rev 5
STM32F303x6/x8
3.14.1
Functional overview
Advanced timer (TIM1)
The advanced-control timer can be seen as a three-phase PWM multiplexed on 6 channels.
They have complementary PWM outputs with programmable inserted dead-times. They can
also be seen as complete general-purpose timers. The 4 independent channels can be
used for:
•
Input capture
•
Output compare
•
PWM generation (edge or center-aligned modes) with full modulation capability
(0-100%)
•
One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIM timers (described in
Section 3.14.2 using the same architecture, so the advanced-control timers can work
together with the TIM timers via the Timer Link feature for synchronization or event chaining.
3.14.2
General-purpose timers (TIM2, TIM3, TIM15, TIM16, TIM17)
There are up to three general-purpose timers embedded in the STM32F303x6/8 (see
Table 5 for differences), that can be synchronized. Each general-purpose timer can be used
to generate PWM outputs, or act as a simple time base.
•
TIM2 and TIM3
They are full-featured general-purpose timers:
–
TIM2 has a 32-bit auto-reload up/down counter and 32-bit prescaler
–
TIM3 has a 16-bit auto-reload up/down counter and 16-bit prescaler
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
•
TIM15, 16 and 17
They are three general-purpose timers with mid-range features.
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–
TIM15 has two channels and one complementary channel
–
TIM16 and TIM17 have one channel and one complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.14.3
Basic timers (TIM6 and TIM7)
The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
DocID025083 Rev 5
23/115
43
Functional overview
3.14.4
STM32F303x6/x8
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
3.14.5
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.14.6
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
3.15
•
A 24-bit down counter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0.
•
Programmable clock source
Real-time clock (RTC) and backup registers
The RTC and the 5 backup registers are supplied through a switch that takes power from
either the VDD supply when present or the VBAT pin. The backup registers are five 32-bit
registers used to store 20 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
The RTC is an independent BCD timer/counter. It supports the following features:
24/115
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
•
Two programmable alarms with wake up from Stop and Standby mode capability.
•
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
Two anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes on tamper event detection.
•
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
DocID025083 Rev 5
STM32F303x6/x8
Functional overview
woken up from Stop and Standby modes on timestamp event detection.
•
17-bit Auto-reload counter for periodic interrupt with wakeup from STOP/STANDBY
capability.
The RTC clock sources can be:
•
A 32.768 kHz external crystal
•
A resonator or oscillator
•
The internal low-power RC oscillator (typical frequency of 40 kHz)
•
The high-speed external clock divided by 32.
3.16
Communication interfaces
3.16.1
Inter-integrated circuit interface (I2C)
The devices feature an I2C bus interface which can operate in multimaster and slave mode.
It can support standard (up to 100 kHz), fast (up to 400 kHz) and fast mode + (up to 1 MHz)
modes.
It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses,
1 with configurable mask). It also includes programmable analog and digital noise filters.
Table 6. Comparison of I2C analog and digital filters
-
Analog filter
Digital filter
Pulse width of
suppressed spikes
≥ 50 ns
Programmable length from 1 to 15
I2C peripheral clocks
Benefits
Available in Stop mode
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Drawbacks
Variations depending on
temperature, voltage, process
Wakeup from Stop on address
match is not available when digital
filter is enabled.
In addition, it provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. It also has a clock domain independent from the CPU clock,
allowing the I2C1 to wake up the MCU from Stop mode on address match.
The I2C interface can be served by the DMA controller.
The features available in I2C1 are showed below in Table 7.
Table 7. STM32F303x6/8 I2C implementation
I2C features(1)
I2C1
7-bit addressing mode
X
10-bit addressing mode
X
Standard mode (up to 100 kbit/s)
X
Fast mode (up to 400 kbit/s)
X
DocID025083 Rev 5
25/115
43
Functional overview
STM32F303x6/x8
Table 7. STM32F303x6/8 I2C implementation (continued)
I2C features(1)
I2C1
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
X
Independent clock
X
SMBus
X
Wakeup from STOP
X
1. X = supported.
3.16.2
Universal synchronous / asynchronous
receivers / transmitters (USARTs)
The STM32F303x6/8 devices have three embedded universal synchronous
receivers/transmitters (USART1, USART2 and USART3).
The USART interfaces are able to communicate at speeds of up to 9 Mbits/s.
USART1 provides hardware management of the CTS and RTS signals. It supports IrDA SIR
ENDEC, the multiprocessor communication mode, the single-wire half-duplex
communication mode and has LIN Master/Slave capability.
All USART interfaces can be served by the DMA controller.
The features available in the USART interfaces are showed below in Table 8.
Table 8. USART features
USART1
USART2
USART3
Hardware flow control for modem
X
X
Continuous communication using DMA
X
X
Multiprocessor communication
X
X
Synchronous mode
X
X
Smartcard mode
X
-
Single-wire half-duplex communication
X
X
IrDA SIR ENDEC block
X
-
LIN mode
X
-
Dual clock domain and wakeup from Stop mode
X
-
Receiver timeout interrupt
X
-
Modbus communication
X
-
Auto baud rate detection
X
-
Driver Enable
X
X
USART modes/features(1)
1. X = supported.
26/115
DocID025083 Rev 5
STM32F303x6/x8
3.16.3
Functional overview
Serial peripheral interface (SPI)
A SPI interface allows to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
The features available in SPI1 are showed below in Table 9.
Table 9. STM32F303x6/8 SPI implementation
SPI features(1)
SPI1
Hardware CRC calculation
X
Rx/Tx FIFO
X
NSS pulse mode
X
TI mode
X
1. X = supported.
3.16.4
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
3.17
Infrared transmitter
The STM32F303x6/8 devices provide an infrared transmitter solution. The solution is based
on internal connections between TIM16 and TIM17 as shown in the figure below.
TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be
sent. The infrared output signal is available on PB9 or PA13.
To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must
be properly configured to generate correct waveforms. All standard IR pulse modulation
modes is obtained by programming the two timers of the output compare channels (see
Figure 3).
DocID025083 Rev 5
27/115
43
Functional overview
STM32F303x6/x8
Figure 3. Infrared transmitter
7,0(5
2&
IRUHQYHORS
7,0(5
3%3$
2&
IRUFDUULHU
06Y9
3.18
Touch sensing controller (TSC)
The STM32F303x6/8 devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 18 capacitive sensing channels
distributed over 6 analog I/Os group.
Capacitive sensing technology is able to detect the presence of a finger near an electrode
which is protected from direct touch by a dielectric (glass, plastic,...). The capacitive
variation introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the electrode capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
Table 10. Capacitive sensing GPIOs available on STM32F303x6/8 devices
Group
1
2
28/115
Capacitive sensing group name
Pin name
TSC_G1_IO1
PA0
TSC_G1_IO2
PA1
TSC_G1_IO3
PA2
TSC_G1_IO4
PA3
TSC_G2_IO1
PA4
TSC_G2_IO2
PA5
TSC_G2_IO3
PA6
TSC_G2_IO4
PA7
DocID025083 Rev 5
STM32F303x6/x8
Functional overview
Table 10. Capacitive sensing GPIOs available on STM32F303x6/8 devices (continued)
Group
3
4
5
6
Capacitive sensing group name
Pin name
TSC_G3_IO1
PC5
TSC_G3_IO2
PB0
TSC_G3_IO3
PB1
TSC_G3_IO4
PB2
TSC_G4_IO1
PA9
TSC_G4_IO2
PA10
TSC_G4_IO3
PA13
TSC_G4_IO4
PA14
TSC_G5_IO1
PB3
TSC_G5_IO2
PB4
TSC_G5_IO3
PB6
TSC_G5_IO4
PB7
TSC_G6_IO1
PB11
TSC_G6_IO2
PB12
TSC_G6_IO3
PB13
TSC_G6_IO4
PB14
Table 11. Capacitive sensing GPIO available
Group
1
2
3
Capacitive sensing group
name
Pin name
TSC_G1_IO1
PA0
TSC_G1_IO2
PA1
TSC_G1_IO3
PA2
TSC_G1_IO4
PA3
TSC_G2_IO1
PA4
TSC_G2_IO2
PA5
TSC_G2_IO3
PA6
TSC_G2_IO4
PA7
TSC_G3_IO1
PC5
TSC_G3_IO2
PB0
TSC_G3_IO3
PB1
TSC_G3_IO1
PC5
DocID025083 Rev 5
29/115
43
Functional overview
STM32F303x6/x8
Table 11. Capacitive sensing GPIO available (continued)
Group
Capacitive sensing group
name
Pin name
TSC_G4_IO1
PA9
TSC_G4_IO2
PA10
TSC_G4_IO3
PA13
TSC_G4_IO4
PA14
TSC_G5_IO1
PB3
TSC_G5_IO2
PB4
TSC_G5_IO3
PB6
TSC_G5_IO4
PB7
TSC_G6_IO1
PB11
TSC_G6_IO2
PB12
TSC_G6_IO3
PB13
TSC_G6_IO4
PB14
4
5
6
Table 12. No. of capacitive sensing channels available on STM32F303x6/8 devices
Number of capacitive sensing channels
Analog I/O group
STM32F303xRx
STM32F303xCx
STM32F303xKx
G1
3
3
3
G2
3
3
3
G3
3
2
2
G4
3
3
3
G5
3
3
3
G6
3
3
0
Number of capacitive
sensing channels
18
17
14
3.19
Development support
3.19.1
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
30/115
DocID025083 Rev 5
STM32F303x6/x8
Pinout and pin descriptions
3$
3%
3%
3%
3%
3%
%227
966B
Figure 4. LQFP32 pinout
9''B
3)26&B,1
3$
3$
3)26&B287
3$
1567
3$
9''$95()
3$
3$
/4)3
3$
3$
9''B
966B
3%
3%
3$
3$
3$
3$
3$
3$
3$
069
Wϳ
Wϲ
Wϱ
ϰϱ
ϰϰ
ϰϯ
ϰϮ
ϰϭ
ϰϬ
ϯϵ
ϯϴ
Wϭϰ
KKdϬ
ϰϲ
Wϭϱ
Wϴ
ϰϳ
Wϯ
Wϵ
ϰϴ
Wϰ
sͺϭ
s^^ͺϭ
Figure 5. LQFP48 pinout
ϯϳ
sd
ϭ
ϯϲ
sͺϯ
Wϭϯ
Ϯ
ϯϱ
s^^
WϭϰͬK^ϯϮͺ/E
ϯ
ϯϰ
Wϭϯ
WϭϱͬK^ϯϮͺKhd
ϰ
ϯϯ
WϭϮ
W&ϬͬK^ͺ/E
ϱ
ϯϮ
W&ϭͬK^ͺKhd
ϲ
ϯϭ
Wϭϭ
WϭϬ
EZ^d
ϳ
ϯϬ
Wϵ
s^^ͬsZ&Ͳ
ϴ
Ϯϵ
Wϴ
sͬsZ&н
ϵ
Ϯϴ
Wϭϱ
WϬ
ϭϬ
Ϯϳ
Wϭϰ
Wϭ
ϭϭ
Ϯϲ
Wϭϯ
WϮ
ϭϮ
Ϯϱ
WϭϮ
ϭϲ
ϭϳ
ϭϴ
ϭϵ
ϮϬ
Ϯϭ
Wϲ
Wϳ
WϬ
Wϭ
WϮ
WϭϬ
DocID025083 Rev 5
ϮϮ
Ϯϯ
ͺϯ
Ϯϰ
sͺϮ
ϭϱ
s^^ͺϮ
ϭϰ
Wϭϭ
ϭϯ
Wϱ
>Y&Wϰϴ
Wϰ
Wϯ
4
Pinout and pin descriptions
06Y9
31/115
43
Pinout and pin descriptions
STM32F303x6/x8
0!
0!
0#
0#
0#
0$
0"
0"
0"
0"
0"
"//4
0"
0"
6$$?
633?
Figure 6. LQFP64 pinout
6"!4
6$$?
0#
633?
0#/3#?).
0!
0#/3#?/54
0!
0&/3#?).
0!
0&/3#?/54
.234
0!
0#
0!
0#
,1&0
0!
0#
0#
0#
0#
0#
633!62%&
0#
6$$!62%&
0"
0!
0"
0!
0"
0!
0"
6$$?
633?
0"
0"
0"
0"
0"
0#
0#
0!
0!
0!
0!
633?
6$$?
0!
069
32/115
DocID025083 Rev 5
STM32F303x6/x8
Pinout and pin descriptions
Table 13. Legend/abbreviations used in the pinout table
Name
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during and
after reset is the same as the actual pin name
Pin name
Pin type
I/O structure
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
FTf
5 V tolerant I/O, FM+ capable
TTa
3.3 V tolerant I/O directly connected to ADC
TT
3.3 V tolerant I/O
TC
Standard 3.3 V I/O
B
Dedicated BOOT0 pin
RST
Bi-directional reset pin with embedded weak pull-up resistor
POR
External power-on reset pin with embedded weak pull-up resistor,
powered from VDDA.
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
reset
Notes
Alternate
functions
Pin
functions
Definition
Functions selected through GPIOx_AFR registers
Additional
Functions directly selected/enabled through peripheral registers
functions
Table 14. STM32F303x6/8 pin definitions
I/O structure
Pin functions
Pin type
Pin Number
-
1
1
VBAT
S
-
-
2
2
PC13(1)
I/O
TC
TIM1_CH1N
RTC_TAMP1/RTC_TS/
RTC_OUT/WKUP2
-
3
3
PC14 / OSC32_IN(1)
I/O
TC
-
OSC32_IN
-
4
4
PC15 / OSC32_OUT(1)
I/O
TC
-
OSC32_OUT
2
5
5
PF0 / OSC_IN
I/O
FT
TIM1_CH3N
OSC_IN
LQFP LQFP LQFP
32
48
64
Pin name (function
after reset)
DocID025083 Rev 5
Alternate
functions
Additional functions
Backup power supply
33/115
43
Pinout and pin descriptions
STM32F303x6/x8
Table 14. STM32F303x6/8 pin definitions (continued)
I/O structure
Pin functions
Pin type
Pin Number
3
6
6
PF1 / OSC_OUT
I/O
FT
4
7
7
NRST
I/O
RST
-
-
8
PC0
I/O
TTa
EVENTOUT, TIM1_CH1
ADC12_IN6
-
-
9
PC1
I/O
TTa
EVENTOUT, TIM1_CH2
ADC12_IN7
-
-
10
PC2
I/O
TTa
EVENTOUT, TIM1_CH3
ADC12_IN8
-
-
11
PC3
I/O
TTa
EVENTOUT, TIM1_CH4,
TIM1_BKIN2
ADC12_IN9
-
8
12
VSSA/VREF-
S
-
Analog ground/Negative reference voltage
5
9
13
VDDA/VREF+
S
-
Analog power supply/Positive reference voltage
LQFP LQFP LQFP
32
48
64
6
7
8
10
11
12
14
15
16
Pin name (function
after reset)
PA0
PA1
PA2
I/O
I/O
I/O
Alternate
functions
Additional functions
-
OSC_OUT
Device reset input / internal reset output
(active low)
TTa
TIM2_CH1/
TIM2_ETR,
TSC_G1_IO1,
USART2_CTS,
EVENTOUT
ADC1_IN1(2),
RTC_TAMP2/WKUP1
TTa
TIM2_CH2,
TSC_G1_IO2,
USART2_RTS_DE,
TIM15_CH1N,
EVENTOUT
ADC1_IN2(2), RTC_REFIN
TTa
TIM2_CH3,
TSC_G1_IO3,
USART2_TX,
COMP2_OUT,
TIM15_CH1,
EVENTOUT
ADC1_IN3(2), COMP2_INM
ADC1_IN4(2)
9
13
17
PA3
I/O
TTa
TIM2_CH4,
TSC_G1_IO4,
USART2_RX,
TIM15_CH2,
EVENTOUT
-
-
18
VSS
S
-
-
-
-
-
19
VDD
S
-
-
ADC2_IN1(2), DAC1_OUT1,
COMP2_INM4, COMP4_INM4,
COMP6_INM4
ADC2_IN2(2), DAC1_OUT2,
OPAMP2_VINM
10
14
20
PA4(3)
I/O
TTa
TIM3_CH2,
TSC_G2_IO1,
SPI1_NSS,
USART2_CK,
EVENTOUT
11
15
21
PA5(3)
I/O
TTa
TIM2_CH1/
TIM2_ETR,
TSC_G2_IO2,
SPI1_SCK, EVENTOUT
34/115
DocID025083 Rev 5
STM32F303x6/x8
Pinout and pin descriptions
Table 14. STM32F303x6/8 pin definitions (continued)
LQFP LQFP LQFP
32
48
64
12
16
22
Pin name (function
after reset)
PA6
(3)
I/O
I/O structure
Pin functions
Pin type
Pin Number
Alternate
functions
Additional functions
TTa
TIM16_CH1, TIM3_CH1,
TSC_G2_IO3,
SPI1_MISO,
TIM1_BKIN, ,
EVENTOUT
ADC2_IN3(2), DAC2_OUT1,
OPAMP2_VOUT
ADC2_IN4(2), COMP2_INP,
OPAMP2_VINP
13
17
23
PA7
I/O
TTa
TIM17_CH1, TIM3_CH2,
TSC_G2_IO4,
SPI1_MOSI,
TIM1_CH1N,
EVENTOUT
-
-
24
PC4
I/O
TTa
EVENTOUT, TIM1_ETR,
USART1_TX
ADC2_IN5(2)
-
-
25
PC5
I/O
TTa
EVENTOUT,
TIM15_BKIN,
TSC_G3_IO1,
USART1_RX
ADC2_IN11, OPAMP2_VINM
14
18
26
PB0
I/O
TTa
TIM3_CH3,
TSC_G3_IO2,
TIM1_CH2N,
EVENTOUT
ADC1_IN11, COMP4_INP,
OPAMP2_VINP
ADC1_IN12
15
19
27
PB1
I/O
TTa
TIM3_CH4,
TSC_G3_IO3,
TIM1_CH3N,
COMP4_OUT,
EVENTOUT
-
20
28
PB2
I/O
TTa
TSC_G3_IO4,
EVENTOUT
ADC2_IN12, COMP4_INM
-
21
29
PB10
I/O
TT
TIM2_CH3, TSC_SYNC,
USART3_TX,
EVENTOUT
-
-
22
30
PB11
I/O
TTa
TIM2_CH4,
TSC_G6_IO1,
USART3_RX,
EVENTOUT
COMP6_INP
16
23
31
VSS
S
-
Digital ground
17
24
32
VDD
S
-
Digital power supply
-
25
33
PB12
I/O
TTa
TSC_G6_IO2,
TIM1_BKIN,
USART3_CK,
EVENTOUT
ADC2_IN13
-
26
34
PB13
I/O
TTa
TSC_G6_IO3,
TIM1_CH1N,
USART3_CTS,
EVENTOUT
ADC1_IN13
TTa
TIM15_CH1,
TSC_G6_IO4,
TIM1_CH2N,
USART3_RTS_DE,
EVENTOUT
ADC2_IN14, OPAMP2_VINP
-
27
35
PB14
I/O
DocID025083 Rev 5
35/115
43
Pinout and pin descriptions
STM32F303x6/x8
Table 14. STM32F303x6/8 pin definitions (continued)
I/O structure
Pin functions
Pin type
Pin Number
-
28
36
PB15
I/O
TTa
TIM15_CH2,
TIM15_CH1N,
TIM1_CH3N,
EVENTOUT
ADC2_IN15, COMP6_INM,
RTC_REFIN
-
-
37
PC6
I/O
FT
EVENTOUT, TIM3_CH1,
COMP6_OUT
-
-
-
38
PC7
I/O
FT
EVENTOUT, TIM3_CH2,
-
-
-
39
PC8
I/O
FT
EVENTOUT, TIM3_CH3,
-
-
-
40
PC9
I/O
FT
EVENTOUT, TIM3_CH4,
-
18
29
41
PA8
I/O
FT
MCO, TIM1_CH1,
USART1_CK,
EVENTOUT
-
FT
TSC_G4_IO1,
TIM1_CH2,
USART1_TX,
TIM15_BKIN,
TIM2_CH3, EVENTOUT
-
FT
TIM17_BKIN,
TSC_G4_IO2,
TIM1_CH3,
USART1_RX,
COMP6_OUT,
TIM2_CH4, EVENTOUT
-
FT
TIM1_CH1N,
USART1_CTS,
CAN_RX, TIM1_CH4,
TIM1_BKIN2,
EVENTOUT
-
FT
TIM16_CH1,
TIM1_CH2N,
USART1_RTS_DE,
COMP2_OUT, CAN_TX,
TIM1_ETR, EVENTOUT
-
-
LQFP LQFP LQFP
32
48
64
19
20
21
22
30
31
32
33
42
43
44
45
Pin name (function
after reset)
PA9
PA10
PA11
PA12
I/O
I/O
I/O
I/O
Alternate
functions
Additional functions
23
34
46
PA13
I/O
FT
JTMS/SWDAT,
TIM16_CH1N,
TSC_G4_IO3, IR_OUT,
USART3_CTS,
EVENTOUT
-
35
47
VSS
S
-
-
-
-
36
48
VDD
S
-
-
-
FTf
JTCK/SWCLK,
TSC_G4_IO4,
I2C1_SDA, TIM1_BKIN,
USART2_TX,
EVENTOUT
-
24
36/115
37
49
PA14
I/O
DocID025083 Rev 5
STM32F303x6/x8
Pinout and pin descriptions
Table 14. STM32F303x6/8 pin definitions (continued)
LQFP LQFP LQFP
32
48
64
Pin name (function
after reset)
I/O structure
Pin functions
Pin type
Pin Number
Alternate
functions
Additional functions
-
25
38
50
PA15
I/O
FTf
JTDI,
TIM2_CH1/TIM2_ETR,
TSC_SYNC, I2C1_SCL,
SPI1_NSS,
USART2_RX,
TIM1_BKIN,
EVENTOUT
-
-
51
PC10
I/O
FT
EVENTOUT,
USART3_TX
-
-
-
52
PC11
I/O
FT
EVENTOUT,
USART3_RX
-
-
-
53
PC12
I/O
FT
EVENTOUT,
USART3_CK
-
-
-
54
PD2
I/O
FT
EVENTOUT, TIM3_ETR
-
FT
JTDO/TRACE
SWO, TIM2_CH2,
TSC_G5_IO1,
SPI1_SCK,
USART2_TX,
TIM3_ETR, EVENTOUT
-
FT
NJTRST, TIM16_CH1,
TIM3_CH1,
TSC_G5_IO2,
SPI1_MISO,
USART2_RX,
TIM17_BKIN,
EVENTOUT
-
FT
TIM16_BKIN,
TIM3_CH2,
I2C1_SMBA,
SPI1_MOSI,
USART2_CK,
TIM17_CH1,
EVENTOUT
-
FTf
TIM16_CH1N,
TSC_G5_IO3,
I2C1_SCL,
USART1_TX,
EVENTOUT
-
-
26
27
28
29
39
40
41
42
55
56
57
58
PB3
PB4
PB5
PB6
I/O
I/O
I/O
I/O
30
43
59
PB7
I/O
FTf
TIM17_CH1N,
TSC_G5_IO4,
I2C1_SDA,
USART1_RX,
TIM3_CH4, EVENTOUT
31
44
60
BOOT0
I
B
-
-
FTf
TIM16_CH1,
TSC_SYNC, I2C1_SCL,
USART3_RX, CAN_RX,
TIM1_BKIN,
EVENTOUT
-
-
45
61
PB8
I/O
DocID025083 Rev 5
37/115
43
Pinout and pin descriptions
STM32F303x6/x8
Table 14. STM32F303x6/8 pin definitions (continued)
I/O structure
Pin functions
Pin type
Pin Number
-
46
62
PB9
I/O
FTf
TIM17_CH1, I2C1_SDA,
IR_OUT, USART3_TX,
COMP2_OUT, CAN_TX,
EVENTOUT
-
32
47
63
VSS
S
-
-
-
1
48
64
VDD
S
-
-
-
LQFP LQFP LQFP
32
48
64
1.
Pin name (function
after reset)
Alternate
functions
Additional functions
PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current (3 mA), the use of
GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the Backup
registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the Battery backup domain and BKP
register description sections in the reference manual.
2. Fast ADC channel.
3.
These GPIOs offer a reduced touch sensing sensitivity. It is thus recommended to use them as sampling capacitor I/O.
38/115
DocID025083 Rev 5
AF0
Port
Port A
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
SYS_AF
TIM2/TIM15/
TIM16/TIM17/
EVENT
TIM1/TIM3/
TIM15/
TIM16
TSC
I2C1/TIM1
SPI1/Infrared
TIM1/Infrared
USART1/USA
RT2/USART3/
GPCOMP6
GPCOMP2/
GPCOMP4/
GPCOMP6
CAN/TIM1/
TIM15
TIM2/TIM3
/TIM17
TIM1
PA0
-
TIM2_CH1/TI
M2_ETR
-
TSC_G1_IO1
-
-
-
USART2_CTS
-
-
-
PA1
-
TIM2_CH2
-
TSC_G1_IO2
-
-
-
USART2_RTS
_DE
-
TIM15_CH1N
PA2
-
TIM2_CH3
-
TSC_G1_IO3
-
-
-
USART2_TX
COMP2_OUT
PA3
-
TIM2_CH4
-
TSC_G1_IO4
-
-
-
USART2_RX
-
PA4
-
-
TIM3_CH2
TSC_G2_IO1
-
SPI1_NSS
-
USART2_CK
PA5
-
TIM2_CH1/TI
M2_ETR
-
TSC_G2_IO2
-
SPI1_SCK
-
-
AF12
AF13
AF14
AF15
-
EVENT
-
-
EVENTOUT
-
-
-
EVENTOUT
-
-
-
-
EVENTOUT
-
-
-
-
EVENTOUT
-
-
-
-
-
EVENTOUT
-
-
-
-
-
EVENTOUT
TIM1
OPAMP2
-
-
-
-
TIM15_CH1
-
TIM15_CH2
-
-
-
-
-
PA6
-
TIM16_CH1
TIM3_CH1
TSC_G2_IO3
-
SPI1_MISO
TIM1_BKIN
-
-
-
-
-
-
-
-
EVENTOUT
PA7
-
TIM17_CH1
TIM3_CH2
TSC_G2_IO4
-
SPI1_MOSI
TIM1_CH1N
-
-
-
-
-
-
-
-
EVENTOUT
DocID025083 Rev 5
PA8
MCO
-
-
-
-
-
TIM1_CH1
USART1_CK
-
-
-
-
-
v
EVENTOUT
PA9
-
-
-
TSC_G4_IO1
-
-
TIM1_CH2
USART1_TX
-
TIM15_BKIN
TIM2_CH3
-
-
-
EVENTOUT
-
TIM17_BKIN
-
TSC_G4_IO2
-
-
TIM1_CH3
USART1_RX
COMP6_OUT
-
TIM2_CH4
-
-
-
EVENTOUT
PA11
-
-
-
-
-
-
TIM1_CH1N
USART1_CTS
-
CAN_RX
-
TIM1_CH4
TIM1_BKIN2
-
EVENTOUT
PA12
-
TIM16_CH1
-
-
-
-
TIM1_CH2N
USART1_RTS
_DE
COMP2_OUT
CAN_TX
-
TIM1_ETR
-
-
EVENTOUT
PA13
JTMS/SWDAT
TIM16_CH1N
-
TSC_G4_IO3
-
IR_OUT
-
USART3_CTS
-
-
-
-
-
-
-
EVENTOUT
PA14
JTCK/SWCLK
-
-
TSC_G4_IO4
I2C1_SDA
-
TIM1_BKIN
USART2_TX
-
-
-
-
-
-
-
EVENTOUT
PA15
JTDI
TIM2_CH1/
TIM2_ETR
-
TSC_SYNC
I2C1_SCL
SPI1_NSS
-
USART2_RX
-
TIM1_BKIN
-
-
-
-
EVENTOUT
PB0
-
-
TIM3_CH3
TSC_G3_IO2
-
-
TIM1_CH2N
-
-
-
-
-
-
-
EVENTOUT
PB1
-
-
TIM3_CH4
TSC_G3_IO3
-
-
TIM1_CH3N
-
COMP4_OUT
-
-
-
-
-
EVENTOUT
PB2
-
-
-
TSC_G3_IO4
-
-
-
-
-
-
-
-
-
-
EVENTOUT
PB3
JTDO/TRACE
SWO
TIM2_CH2
-
TSC_G5_IO1
-
SPI1_SCK
-
USART2_TX
-
-
TIM3_ETR
-
-
EVENTOUT
PB4
NJTRST
TIM16_CH1
TIM3_CH1
TSC_G5_IO2
-
SPI1_MISO
-
USART2_RX
-
-
TIM17_BK
IN
-
-
-
EVENTOUT
PB5
-
TIM16_BKIN
TIM3_CH2
-
I2C1_SMBA
SPI1_MOSI
-
USART2_CK
-
-
TIM17_CH
1
-
-
-
EVENTOUT
PB6
-
TIM16_CH1N
-
TSC_G5_IO3
I2C1_SCL
-
-
USART1_TX
-
-
-
-
-
EVENTOUT
PB7
-
TIM17_CH1N
-
TSC_G5_IO4
I2C1_SDA
-
-
USART1_RX
-
-
TIM3_CH4
-
-
-
EVENTOUT
PB8
-
TIM16_CH1
-
TSC_SYNC
I2C1_SCL
-
-
USART3_RX
-
CAN_RX
-
-
TIM1_BKIN
-
EVENTOUT
PB9
-
TIM17_CH1
-
-
I2C1_SDA
-
IR_OUT
USART3_TX
COMP2_OUT
CAN_TX
-
-
-
-
EVENTOUT
Port B
-
39/115
Pinout and pin descriptions
PA10
STM32F303x6/x8
Table 15. Alternate functions
AF0
Port
SYS_AF
Port B
AF1
TIM2/TIM15/
TIM16/TIM17/
EVENT
AF2
TIM1/TIM3/
TIM15/
TIM16
AF3
AF4
AF5
AF6
AF7
GPCOMP2/
GPCOMP4/
GPCOMP6
CAN/TIM1/
TIM15
TIM2/TIM3
/TIM17
TIM1
TSC
I2C1/TIM1
SPI1/Infrared
TIM1/Infrared
USART1/USA
RT2/USART3/
GPCOMP6
AF8
AF9
AF10
AF11
AF12
TIM1
AF13
OPAMP2
AF14
AF15
-
EVENT
DocID025083 Rev 5
PB10
-
TIM2_CH3
-
TSC_SYNC
-
-
-
USART3_TX
-
-
-
-
-
-
EVENTOUT
PB11
-
TIM2_CH4
-
TSC_G6_IO1
-
-
-
USART3_RX
-
-
-
-
-
-
EVENTOUT
PB12
-
-
-
TSC_G6_IO2
-
-
TIM1_BKIN
USART3_CK
-
-
-
-
-
-
EVENTOUT
PB13
-
-
-
TSC_G6_IO3
-
-
TIM1_CH1N
USART3_CTS
-
-
-
-
-
-
EVENTOUT
PB14
-
TIM15_CH1
-
TSC_G6_IO4
-
-
TIM1_CH2N
USART3_RTS
_DE
-
-
-
-
-
-
EVENTOUT
PB15
-
TIM15_CH2
TIM15_CH1
N
-
TIM1_CH3N
-
-
-
-
-
-
-
-
-
EVENTOUT
PC0
-
EVENTOUT
TIM1_CH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PC2
-
EVENTOUT
TIM1_CH3
-
-
-
-
-
-
-
-
-
-
-
-
-
PC3
-
EVENTOUT
TIM1_CH4
-
-
-
TIM1_BKIN2
-
-
-
-
-
-
-
-
-
PC4
-
EVENTOUT
TIM1_ETR
-
-
-
-
USART1_TX
-
-
-
-
-
-
-
-
PC5
-
EVENTOUT
TIM15_BKIN
TSC_G3_IO1
-
-
-
USART1_RX
-
-
-
-
-
-
-
-
PC6
-
EVENTOUT
TIM3_CH1
-
-
-
COMP6_OUT
-
-
-
-
-
-
-
-
PC7
-
EVENTOUT
TIM3_CH2
-
-
-
-
-
-
-
-
-
-
-
-
PC8
-
EVENTOUT
TIM3_CH3
-
-
-
-
-
-
-
-
-
-
-
-
PC9
-
EVENTOUT
TIM3_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART3_TX
-
-
-
-
-
-
-
-
-
-
-
USART3_RX
-
-
-
-
-
-
-
-
Pinout and pin descriptions
40/115
Table 15. Alternate functions (continued)
Port C
Port D
PC10
-
EVENTOUT
-
PC11
-
EVENTOUT
-
-
PC12
-
EVENTOUT
-
-
-
-
USART3_CK
-
-
-
-
-
-
-
-
PC13
-
-
-
-
TIM1_CH1N
-
-
-
-
-
-
-
-
-
-
-
PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PD2
-
EVENTOUT
TIM3_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
PF0
-
-
-
-
-
-
TIM1_CH3N
-
-
-
-
-
-
-
-
-
PF1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port F
STM32F303x6/x8
STM32F303x6/x8
5
Memory mapping
Memory mapping
Figure 7. STM32F303x6/8 memory map
[))
$+%
[))))))))
&RUWH[0
ZLWK)38
,QWHUQDO
3HULSKHUDOV
[(
[
5HVHUYHG
[
$+%
[
5HVHUYHG
[))
$+%
[&
[
5HVHUYHG
[&
$3%
[$
[
5HVHUYHG
[$
$3%
[
[
[)))))))
2SWLRQE\WHV
[
[))))
6\VWHPPHPRU\
[
[)))'
3HULSKHUDOV
[
5HVHUYHG
&&05$0
[
[
[
65$0
5HVHUYHG
)ODVKPHPRU\
[
&2'(
5HVHUYHG
[
[
5HVHUYHG
[
)ODVKV\VWHP
PHPRU\RU65$0
GHSHQGLQJRQ%227
FRQILJXUDWLRQ
06Y9
DocID025083 Rev 5
41/115
43
Memory mapping
STM32F303x6/x8
-
Table 16. STM32F303x6/8 peripheral register boundary addresses
Bus
Size
(bytes)
Peripheral
AHB3
0x5000 0000 - 0x5000 03FF
1K
-
0x4800 1800 - 0x4FFF FFFF
~132 M
AHB2
0x4800 1400 - 0x4800 17FF
1K
GPIOF
-
0x4800 1000 - 0x4800 13FF
1K
Reserved
0x4800 0C00 - 0x4800 0FFF
1K
GPIOD
0x4800 0800 - 0x4800 0BFF
1K
GPIOC
0x4800 0400 - 0x4800 07FF
1K
GPIOB
0x4800 0000 - 0x4800 03FF
1K
GPIOA
0x4002 4400 - 0x47FF FFFF
~128 M
0x4002 4000 - 0x4002 43FF
1K
TSC
0x4002 3400 - 0x4002 3FFF
3K
Reserved
0x4002 3000 - 0x4002 33FF
1K
CRC
0x4002 2400 - 0x4002 2FFF
3K
Reserved
0x4002 2000 - 0x4002 23FF
1K
Flash interface
0x4002 1400 - 0x4002 1FFF
3K
Reserved
0x4002 1000 - 0x4002 13FF
1K
RCC
0x4002 0400 - 0x4002 0FFF
3K
Reserved
0x4002 0000 - 0x4002 03FF
1K
DMA1
0x4001 8000 - 0x4001 FFFF
32 K
Reserved
0x4001 4C00 - 0x4001 73FF
12 K
Reserved
0x4001 4800 - 0x4001 4BFF
1K
TIM17
0x4001 4400 - 0x4001 47FF
1K
TIM16
0x4001 4000 - 0x4001 43FF
1K
TIM15
0x4001 3C00 - 0x4001 3FFF
1K
Reserved
0x4001 3800 - 0x4001 3BFF
1K
USART1
0x4001 3400 - 0x4001 37FF
1K
Reserved
0x4001 3000 - 0x4001 33FF
1K
SPI1
0x4001 2C00 - 0x4001 2FFF
1K
TIM1
0x4001 0800 - 0x4001 2BFF
9K
Reserved
0x4001 0400 - 0x4001 07FF
1K
EXTI
0x4001 0000 - 0x4001 03FF
1K
SYSCFG + COMP + OPAMP
0x4000 9C00 - 0x4000 FFFF
25 K
Reserved
AHB2
-
AHB1
-
APB2
-
42/115
Boundary address
DocID025083 Rev 5
ADC1 - ADC2
Reserved
Reserved
STM32F303x6/x8
Memory mapping
Table 16. STM32F303x6/8 peripheral register boundary addresses (continued)
Bus
APB1
Boundary address
Size
(bytes)
Peripheral
0x4000 9800 - 0x4000 9BFF
1K
DAC2
0x4000 7800 - 0x4000 97FF
8K
Reserved
0x4000 7400 - 0x4000 77FF
1K
DAC1
0x4000 7000 - 0x4000 73FF
1K
PWR
0x4000 6800 - 0x4000 6FFF
2K
Reserved
0x4000 6400 - 0x4000 67FF
1K
bxCAN
0x4000 5800 - 0x4000 63FF
3K
Reserved
0x4000 5400 - 0x4000 57FF
1K
I2C1
0x4000 4C00 - 0x4000 53FF
2K
Reserved
0x4000 4800 - 0x4000 4BFF
1K
USART3
0x4000 4400 - 0x4000 47FF
1K
USART2
0x4000 3400 - 0x4000 43FF
2K
Reserved
0x4000 3000 - 0x4000 33FF
1K
IWDG
0x4000 2C00 - 0x4000 2FFF
1K
WWDG
0x4000 2800 - 0x4000 2BFF
1K
RTC
0x4000 1800 - 0x4000 27FF
4K
Reserved
0x4000 1400 - 0x4000 17FF
1K
TIM7
0x4000 1000 - 0x4000 13FF
1K
TIM6
0x4000 0800 - 0x4000 0FFF
2K
Reserved
0x4000 0400 - 0x4000 07FF
1K
TIM3
0x4000 0000 - 0x4000 03FF
1K
TIM2
-
0x2000 3000 - 3FFF FFFF
-
0x2000 0000 - 0x2000 2FFF
12 K
SRAM
-
0x1FFF F800 - 0x1FFF FFFF
2K
Option bytes
-
0x1FFF D800 - 0x1FFF F7FF
8K
System memory
-
0x1000 2000 - 0x1FFF D7FF
~256 M
Reserved
-
0x1000 0000 - 0x1000 0FFF
4K
CCM RAM
-
0x0804 0000 - 0x0FFF FFFF
~128 M
Reserved
-
0x0800 0000 - 0x0800 FFFF
64 K
-
0x0004 0000 - 0x07FF FFFF
~128 M
-
0x0000 000 - 0x0000 FFFF
DocID025083 Rev 5
~512 M
64 K
Reserved
Main Flash memory
Reserved
Main Flash memory, system
memory or SRAM depending
on BOOT configuration
43/115
43
Electrical characteristics
STM32F303x6/x8
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3 σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V, VDDA =
3.3 V. They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
6.1.5
Input voltage on a pin
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 8. Pin loading conditions
Figure 9. Pin input voltage
0&8SLQ
0&8SLQ
& S)
9,1
069
44/115
DocID025083 Rev 5
069
STM32F303x6/x8
6.1.6
Electrical characteristics
Power-supply scheme
Figure 10. Power-supply scheme
9%$7
*3,2V
,1
9''
[9''
9''$
/HYHOVKLIWHU
287
[Q)
[—)
%DFNXSFLUFXLWU\
/6(57&
:DNHXSORJLF
%DFNXSUHJLVWHUV
3RZHU
VZLWFK
9
,2
/RJLF
.HUQHOORJLF
&38
'LJLWDO
0HPRULHV
5HJXODWRU
[9
66
9''$
Q)
—)
9
5()
95()
$'&
'$&
$QRORJ5&V3//
FRPSDUDWRUV23$03
966$
069
Caution:
Each power-supply pair (VDD/VSS, VDDA/VSSA etc..) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.
DocID025083 Rev 5
45/115
100
Electrical characteristics
6.1.7
STM32F303x6/x8
Measurement of the current consumption
Figure 11. Scheme of the current-consumption measurement
, ''B9%$7
9%$7
,''
9''
,''$
9''$
069
46/115
DocID025083 Rev 5
STM32F303x6/x8
6.2
Electrical characteristics
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 17: Voltage characteristics,
Table 18: Current characteristics, and Table 19: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 17. Voltage characteristics(1)
Symbol
Ratings
Min.
VDD–VSS
External main supply voltage (including VDDA, VBAT
and VDD)
-0.3
VDD–VDDA
VIN(2)
|ΔVDDx|
|VSSX − VSS|
VESD(HBM)
Allowed voltage difference for VDD > VDDA
Max.
-
0.4
Input voltage on FT and FTf pins
VSS −0.3
VDD + 4.0
Input voltage on TTa
VSS −0.3
4.0
Input voltage on any other pin
VSS − 0.3
4.0
Input voltage on Boot0 pin
0
9
Variations between different VDD power pins
-
50
Variations between all the different ground pins(3)
-
50
Electrostatic discharge voltage (human body
model)
Unit
V
mV
see Section 6.3.12: Electrical
sensitivity characteristics
-
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range. The following relationship must be respected between VDDA and VDD:
VDDA must power on before or at the same time as VDD in the power up sequence.
VDDA must be greater than or equal to VDD.
2. VIN maximum must always be respected. Refer to Table 18: Current characteristics for the maximum allowed injected
current values.
3. Include VREF- pin.
DocID025083 Rev 5
47/115
100
Electrical characteristics
STM32F303x6/x8
Table 18. Current characteristics
Symbol
Ratings
Max.
ΣIVDD
Total current into sum of all VDD_x power lines (source)(1)
140
ΣIVSS
(1)
Total current out of sum of all VSS_x ground lines (sink)
-140
IVDD
Maximum current into each VDD_x power line (source)
(1)
100
IVSS
Maximum current out of each VSS _x ground line (sink)(1)
100
Output current sunk by any I/O and control pin
25
IIO(PIN)
ΣIIO(PIN)
Output current source by any I/O and control pin
Total output current sunk by sum of all I/Os and control pins
Injected current on TC and RST
Injected current on TTa pins
ΣIINJ(PIN)
80
Total output current sourced by sum of all I/Os and control pins(2)
Injected current on TT, FT, FTf and B
IINJ(PIN)
-25
(2)
Unit
mA
-80
pins(3)
-5 /+0
±5
±5
±25
pin(4)
(5)
Total injected current (sum of all I/O and control pins)(6)
1. All main power (VDD, VDDA) and ground (VSS and VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins.The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be
exceeded. Refer to Table 17: Voltage characteristics for the maximum allowed input voltage values.
5. A positive injection is induced by VIN > VDDA while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 17: Voltage characteristics for the maximum allowed input voltage values. Negative injection
disturbs the analog performance of the device. See note 2. below Table 61.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 19. Thermal characteristics
Symbol
TSTG
TJ
48/115
Ratings
Storage temperature range
Maximum junction temperature
DocID025083 Rev 5
Value
Unit
–65 to +150
°C
150
°C
STM32F303x6/x8
Electrical characteristics
6.3
Operating conditions
6.3.1
General operating conditions
Table 20. General operating conditions
Symbol
Parameter
Conditions
Min.
Max.
Unit
fHCLK
Internal AHB clock frequency
-
0
72
fPCLK1
Internal APB1 clock frequency
-
0
36
fPCLK2
Internal APB2 clock frequency
-
0
72
Standard operating voltage
-
2
3.6
2
3.6
2.4
3.6
1.65
3.6
TC I/O
–0.3
VDD+0.3
TT I/O
-0.3
3.6
–0.3
VDDA+0.3
–0.3
5.5
0
5.5
-
444
mW
-
364
mW
–40
85
–40
105
–40
105
–40
125
6 suffix version
–40
105
7 suffix version
–40
125
VDD
VDDA
VBAT
VIN
Analog operating voltage
(OPAMP and DAC not used)
Must have a potential equal to
or higher than VDD
Analog operating voltage
(OPAMP and DAC used)
Backup operating voltage
-
TTa I/O
I/O input voltage
(1)
FT and FTf I/O
BOOT0
PD
PD
Power dissipation at TA = 85 °C for
LQFP64
suffix 6 or TA = 105 °C for suffix
7(2)
Power dissipation at TA = 85 °C for
suffix 6 or TA = 105 °C for suffix
LQFP48
7(3)
Ambient temperature for 6 suffix
version
Maximum power dissipation
Ambient temperature for 7 suffix
version
Maximum power dissipation
TA
TJ
Junction temperature range
Low power dissipation
Low power dissipation
(4)
(4)
MHz
V
V
V
°C
°C
°C
1. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.5: Thermal characteristics).
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.5: Thermal characteristics).
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.5:
Thermal characteristics).
DocID025083 Rev 5
49/115
100
Electrical characteristics
6.3.2
STM32F303x6/x8
Operating conditions at power-up / power-down
The parameters given in Table 21 are derived from tests performed under the ambient
temperature condition summarized in Table 20.
Table 21. Operating conditions at power-up / power-down
Symbol
Parameter
VDD rise time rate
tVDD
-
VDD fall time rate
VDDA rise time rate
tVDDA
6.3.3
Conditions
Max.
Unit
0
∞
∞
∞
∞
µs/V
20
0
-
VDDA fall time rate
Min.
20
Characteristics of the embedded reset and power-control block
The parameters given in Table 22 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 20.
Table 22. Embedded reset and power control block characteristics
Symbol
VPOR/PDR(1)
VPDRhyst
(1)
tRSTTEMPO(3)
Parameter
Conditions
Power on/power down
reset threshold
Min.
Typ. Max.
Falling edge
1.8(2) 1.88
1.96
V
Rising edge
1.84
1.92
2.0
V
PDR hysteresis
-
-
40
-
mV
POR reset
temporization
-
1.5
2.5
4.5
ms
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Guaranteed by design, not tested in production.
50/115
Unit
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
Table 23. Programmable voltage detector characteristics
Symbol
Parameter
VPVD0
PVD threshold 0
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
Conditions
Min.(1)
Typ.
Max.(1)
Rising edge
2.1
2.18
2.26
Falling edge
2
2.08
2.16
Rising edge
2.19
2.28
2.37
Falling edge
2.09
2.18
2.27
Rising edge
2.28
2.38
2.48
Falling edge
2.18
2.28
2.38
Rising edge
2.38
2.48
2.58
Falling edge
2.28
2.38
2.48
Rising edge
2.47
2.58
2.69
Falling edge
2.37
2.48
2.59
Rising edge
2.57
2.68
2.79
Falling edge
2.47
2.58
2.69
Rising edge
2.66
2.78
2.9
Falling edge
2.56
2.68
2.8
Rising edge
2.76
2.88
3
Falling edge
2.66
2.78
2.9
Unit
V
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
VPVD7
PVD threshold 7
VPVDhyst(2)
PVD hysteresis
-
-
100
-
mV
IDD(PVD)
PVD current
consumption
-
-
0.15
0.26
µA
1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.
6.3.4
Embedded reference voltage
The parameters given in Table 24 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 20.
Table 24. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VREFINT
Internal reference voltage
–40 °C < TA < +105 °C
1.20
1.23
1.25
V
TS_vrefint
ADC sampling time when
reading the internal
reference voltage
-
2.2
-
-
µs
VRERINT
Internal reference voltage
spread over the
temperature range
VDD = 31.8 V ±10 mV
-
-
10(1)
mV
-
-
-
100(1) ppm/°C
TCoeff
Temperature coefficient
1. Guaranteed by design, not tested in production.
DocID025083 Rev 5
51/115
100
Electrical characteristics
STM32F303x6/x8
Table 25. Internal reference voltage calibration values
Calibration value name
VREFINT_CAL
6.3.5
Description
Raw data acquired at
temperature of 30 °C
VDDA= 3.3 V
Memory address
0x1FFF F7BA - 0x1FFF F7BB
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Scheme of the currentconsumption measurement.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
Note:
The total current consumption is the sum of IDD and IDDA.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in input mode with a static value at VDD or VSS (no load)
•
All peripherals are disabled except when explicitly mentioned
•
The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0
to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz)
•
Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
•
When the peripherals are enabled fPCLK2 = fHCLK and fPCLK1 = fHCLK/2
•
When fHCLK > 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or
HSE (8 MHz) in bypass mode.
The parameters given in Table 26 to Table 30 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 20.
52/115
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
Table 26. Typical and maximum current consumption from VDD supply at VDD = 3.6V
All peripherals enabled
Symbol Parameter Conditions
Supply
current in
Run mode,
executing
from Flash
External
clock (HSE
bypass)
Internal
clock (HSI)
IDD
Supply
current in
Run mode,
executing
from RAM
External
clock (HSE
bypass)
Internal
clock (HSI)
IDD
Supply
current in
Sleep
mode,
executing
from Flash
or RAM
External
clock (HSE
bypass)
Internal
clock (HSI)
fHCLK
Typ.
Max. @ TA
All peripherals disabled
(1)
25 °C
85 °C
105 °C
Typ.
Max. @ TA(1)
25 °C
85 °C
105 °C
72 MHz
71.4
77.9
79.1
80.0
27.1
32.2
32.4
32.4
64 MHz
63.9
70.6
71.3
71.5
24.2
27.0
27.5
27.7
48 MHz
49.5
56.6
57.1
57.7
18.7
21.4
21.6
21.9
32 MHz
34.0
38.6
38.9
39.2
12.9
14.6
14.9
15.9
24 MHz
25.9
30.2
30.4
30.6
10.0
11.1
11.2
12.3
8 MHz
9.3
14.1
14.3
14.4
3.3
4.0
4.4
5.1
1 MHz
3.5
8.9
9.1
9.5
0.7
0.9
1.0
1.2
64 MHz
61.6
68.1
68.8
70.1
24.1
27.0
27.1
27.2
48 MHz
48.1
54.6
54.8
55.1
18.6
21.6
21.7
21.9
32 MHz
33.3
37.8
37.9
38.0
12.7
14.4
14.9
16.0
24 MHz
25.7
29.8
29.8
30.0
10.0
11.1
11.2
12.3
8 MHz
9.7
12.2
12.3
12.8
3.4
3.8
4.2
5.0
72 MHz
71.3
77.8(2)
78.7
78.9(2)
27.6
32.1(2)
32.2
32.3(2)
64 MHz
63.8
70.5
70.7
70.9
24.5
27.2
27.6
27.7
48 MHz
49.3
56.5
56.9
57.4
18.1
21.6
21.8
21.8
32 MHz
33.9
37.7
37.9
38.0
12.9
14.9
14.9
15.9
24 MHz
25.8
28.8
29.0
29.2
9.8
11.1
11.3
11.5
8 MHz
9.0
13.2
13.3
13.8
3.2
3.6
4.0
4.6
1 MHz
3.2
7.6
7.8
8.0
0.3
0.4
0.8
1.2
64 MHz
61.3
66.9
67.3
67.8
24.1
26.9
27.0
27.1
48 MHz
48.0
52.4
52.6
53.1
19.1
21.6
21.6
22.1
32 MHz
33.1
35.6
35.8
36.6
12.6
14.8
14.9
15.9
24 MHz
25.6
28.5
28.7
28.8
9.8
11.1
11.3
11.5
8 MHz
9.7
11.6
11.6
11.7
3.0
3.1
4.1
4.7
61.1
61.9(2)
7.0
7.3(2)
8.4
8.5(2)
(2)
72 MHz
55.5
58.7
64 MHz
49.8
52.7
54.5
54.8
6.3
6.7
7.0
7.8
48 MHz
38.5
40.6
41.7
41.8
4.6
5.1
5.6
5.9
32 MHz
26.9
28.8
29.2
29.5
3.0
3.3
4.0
4.5
24 MHz
19.1
23.2
23.7
23.9
2.4
2.5
3.2
3.8
8 MHz
7.1
11.5
11.7
11.9
0.6
0.9
1.2
2.1
1 MHz
3.0
7.4
7.7
7.9
0.3
0.3
0.4
1.2
64 MHz
47.7
52.4
52.6
52.8
5.4
6.5
6.8
7.5
48 MHz
35.0
40.4
40.6
40.8
4.3
4.7
5.2
5.7
32 MHz
23.7
27.7
28.3
28.8
2.9
3.1
3.2
4.4
24 MHz
18.5
23.8
24.0
24.2
1.3
1.7
2.2
2.7
8 MHz
7.5
9.6
9.7
9.7
0.5
0.7
1.1
2.0
Unit
mA
mA
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production with code executing from RAM.
DocID025083 Rev 5
53/115
100
Electrical characteristics
STM32F303x6/x8
Table 27. Typical and maximum current consumption from the VDDA supply
VDDA = 2.4 V
Symbol Parameter
IDDA
Supply
current in
Run/Sleep
mode,
code
executing
from Flash
or RAM
Conditions
(1)
HSE
bypass
HSI clock
fHCLK
Typ.
Max. @
VDDA = 3.6 V
TA(2)
25 °C
85 °C 105 °C
(3)
(3)
Typ.
Max. @ TA(2)
25 °C
85 °C 105 °C
288
295(3)
243
257
263
159
186
196
201
135
109
133
142
145
108
85
108
113
116
5
6
4
6
6
7
5
5
6
3
5
6
6
259
288
304
309
285
315
332
338
208
239
251
254
230
258
271
277
32 MHz
162
190
198
202
179
206
216
219
24 MHz
140
168
175
178
155
181
188
191
8 MHz
62
85
88
89
71
94
96
98
252
265
269
245
72 MHz
224
64 MHz
196
225
237
241
214
48 MHz
147
174
183
186
32 MHz
100
126
133
24 MHz
79
102
107
8 MHz
3
5
1 MHz
3
64 MHz
48 MHz
(3)
Unit
272
µA
1. Current consumption from the VDDA supply is independent of whether the peripherals are on or off. Furthermore when the
PLL is off, IDDA is independent from the frequency.
2. Data based on characterization results, not tested in production.
3. Data based characterization results and tested in production with code executing from RAM.
Table 28. Typical and maximum VDD consumption in Stop and Standby modes
Max.(1)
Typ. @VDD (VDD=VDDA)
Symbol Parameter
Conditions
2.0
V
Regulator in run mode,
all oscillators OFF
IDD
Supply
current in Regulator in low-power
Stop mode mode, all oscillators
OFF
Supply
current in
Standby
mode
2.4
V
2.7
V
3.0
V
3.3
V
3.6
V
17.5 17.6 17.8 18.1 18.5 19.3
1
8
4
7
7
9
30.6 232.5 612.2
6.44 6.51 6.60 6.73 6.96 7.20
20.0 246.4 585.0
µA
LSI ON and IWDG ON
0.73 0.89 1.02 1.14 1.28 1.44
-
-
-
LSI OFF and IWDG
OFF
0.55 0.66 0.75 0.85 0.93 1.01
4.9
7.0
7.9
1. Data based on characterization results, not tested in production unless otherwise specified.
54/115
TA = Unit
TA = TA =
105 °
25 °C 85 °C
C
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
Table 29. Typical and maximum VDDA consumption in Stop and Standby modes
Max.(1)
Typ. @VDD (VDD = VDDA)
Supply
current in
Stop mode
IDDA
Supply
current in
Standby
mode
Supply
current in
Stop mode
Supply
current in
Standby
mode
Conditions
VDDA supervisor OFF VDDA supervisor ON
Symbol Parameter
2.0
V
Regulator in run/lowpower mode, all
oscillators OFF
2.4
V
2.7
V
3.0
V
3.3
V
3.6
V
1.67 1.79 1.91 2.04 2.19 2.35
LSI ON and IWDG ON 2.06 2.24 2.41 2.60 2.80 3.04
LSI OFF and IWDG
OFF
1.54 1.68 1.78 1.92 2.06 2.22
TA = Unit
TA = TA =
105 °
25 °C 85 °C
C
2.5
5.9
6.2
-
-
-
2.6
3.0
3.8
µA
Regulator in run/lowpower mode, all
oscillators OFF
0.97 0.99 1.03 1.07 1.14 1.22
-
-
-
LSI ON and IWDG ON 1.36 1.44 1.52 1.62 1.76 1.91
-
-
-
LSI OFF and IWDG
OFF
-
-
-
0.86 0.88 0.91 0.95 1.03 1.09
1. Data based on characterization results, not tested in production.
Table 30. Typical and maximum current consumption from VBAT supply
Max.
@VBAT= 3.6V(2)
[email protected]
Symbol
Para
meter
Conditions(1)
LSE & RTC
ON; “Xtal
mode” lower
driving
capability;
Backup LSEDRV[1:0]
domain = '00'
IDD_VBAT
supply LSE & RTC
current ON; “Xtal
mode” higher
driving
capability;
LSEDRV[1:0]
= '11'
1.65
V
1.8V
0.42
0.44 0.47 0.54
2V
2.4V 2.7V
3V
TA=
3.3V 3.6V
25°C
0.60 0.66 0.74 0.82
-
TA=
TA=
85°
105°C
C
-
Unit
-
µA
0.71
0.74 0.77 0.85
0.91 0.98 1.06 1.16
-
-
-
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Data based on characterization results, not tested in production.
DocID025083 Rev 5
55/115
100
Electrical characteristics
STM32F303x6/x8
Figure 12. Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’)
9
, 9%$7 —$
9
9
9
9
9
9
9
ƒ&
ƒ&
ƒ&
ƒ&
7$ ƒ&
069
Typical current consumption
The MCU is placed under the following conditions:
56/115
•
VDD = VDDA = 3.3 V
•
All I/O pins available on each package are in analog input configuration
•
The Flash access time is adjusted to fHCLK frequency (0 wait states from 0 to 24 MHz,
1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz), and Flash
prefetch is ON
•
When the peripherals are enabled, fAPB1 = fAHB/2, fAPB2 = fAHB
•
PLL is used for frequencies greater than 8 MHz
•
AHB prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz,
500 kHz and 125 kHz respectively.
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
Table 31. Typical current consumption in Run mode, code with data processing
running from Flash
Typ.
Symbol
IDD
Parameter
Conditions
Supply current in
Run mode from
VDD supply
Running from HSE
crystal clock 8 MHz,
code executing from
Flash
IDDA(1) (2)
Supply current in
Run mode from
VDDA supply
fHCLK
Peripherals
enabled
Peripherals
disabled
72 MHz
47.2
25.2
64 MHz
39.5
22.6
48 MHz
30.4
17.3
32 MHz
20.9
12.0
24 MHz
17.3
9.3
16 MHz
11.0
6.5
8 MHz
5.8
3.55
4 MHz
3.45
2.21
2 MHz
2.16
1.52
1 MHz
1.50
1.17
500 kHz
1.18
0.94
125 kHz
0.88
0.82
72 MHz
240.0
234.0
64 MHz
209.9
208.6
48 MHz
154.5
153.5
32 MHz
104.1
103.6
24 MHz
80.2
80.0
16 MHz
56.8
56.6
8 MHz
1.14
1.14
4 MHz
1.14
1.14
2 MHz
1.14
1.14
1 MHz
1.14
1.14
500 kHz
1.14
1.14
125 kHz
1.14
1.14
Unit
mA
µA
1. VDDA supervisor is OFF.
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.
DocID025083 Rev 5
57/115
100
Electrical characteristics
STM32F303x6/x8
Table 32. Typical current consumption in Run mode, code with data processing
running from Flash memory
Typ.
Symbol
IDD
Parameter
Conditions
Supply current in
Run mode from
VDD supply
Running from HSE
crystal clock 8 MHz,
code executing from
Flash
IDDA(1) (2)
Supply current in
Run mode from
VDDA supply
fHCLK
Peripherals
enabled
Peripherals
disabled
72 MHz
70.6
25.2
64 MHz
60.3
22.6
48 MHz
46.0
17.3
32 MHz
31.3
12.0
24 MHz
25.0
9.3
16 MHz
16.2
6.5
8 MHz
8.4
3.55
4 MHz
4.75
2.21
2 MHz
2.81
1.52
1 MHz
1.82
1.17
500 kHz
1.34
0.94
125 kHz
0.93
0.82
72 MHz
240.0
234.0
64 MHz
209.9
208.6
48 MHz
154.5
153.5
32 MHz
104.1
103.6
24 MHz
80.2
80.0
16 MHz
56.8
56.6
8 MHz
1.14
1.14
4 MHz
1.14
1.14
2 MHz
1.14
1.14
1 MHz
1.14
1.14
500 kHz
1.14
1.14
125 kHz
1.14
1.14
Unit
mA
µA
1. VDDA supervisor is OFF.
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.
58/115
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
Table 33. Typical current consumption in Sleep mode, code running from Flash or RAM
Typ.
Symbol
IDD
Parameter
Conditions
Supply current in
Sleep mode from
VDD supply
Running from HSE
crystal clock 8 MHz,
code executing from
Flash or RAM
IDDA(1) (2)
Supply current in
Sleep mode from
VDDA supply
fHCLK
Peripherals
enabled
Peripherals
disabled
72 MHz
28.5
6.3
64 MHz
25.6
5.7
48 MHz
19.5
4.40
32 MHz
13.3
3.13
24 MHz
10.2
2.49
16 MHz
7.1
1.85
8 MHz
3.63
0.99
4 MHz
2.38
0.88
2 MHz
1.61
0.80
1 MHz
1.23
0.76
500 kHz
1.04
0.74
125 kHz
0.85
0.72
72 MHz
239.0
236.7
64 MHz
209.4
207.8
48 MHz
154.0
152.9
32 MHz
103.7
103.2
24 MHz
80.1
79.8
16 MHz
56.7
56.6
8 MHz
1.14
1.14
4 MHz
1.14
1.14
2 MHz
1.14
1.14
1 MHz
1.14
1.14
500 kHz
1.14
1.14
125 kHz
1.14
1.14
Unit
mA
µA
1. VDDA supervisor is OFF.
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 52: I/O static characteristics.
DocID025083 Rev 5
59/115
100
Electrical characteristics
STM32F303x6/x8
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 35: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
I SW = V DD × f SW × C
where:
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT+CS
60/115
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
Table 34. Switching output I/O current consumption
Symbol
Parameter
Conditions(1)
VDD =3.3 V
Cext = 0 pF
C = CINT + CEXT+ CS
VDD = 3.3 V
Cext = 10 pF
C = CINT + CEXT +CS
ISW
I/O current
consumption
VDD = 3.3 V
Cext = 22 pF
C = CINT + CEXT +CS
VDD = 3.3 V
Cext = 33 pF
C = CINT + CEXT+ CS
VDD = 3.3 V
Cext = 47 pF
C = CINT + CEXT+ CS
I/O toggling
frequency (fSW)
Typ.
2 MHz
0.90
4 MHz
0.93
8 MHz
1.16
18 MHz
1.60
36 MHz
2.51
2 MHz
0.93
4 MHz
1.06
8 MHz
1.47
18 MHz
2.26
36 MHz
3.39
2 MHz
1.03
4 MHz
1.30
8 MHz
1.79
18 MHz
3.01
36 MHz
5.99
2 MHz
1.10
4 MHz
1.31
8 MHz
2.06
18 MHz
3.47
36 MHz
8.35
2 MHz
1.20
4 MHz
1.54
8 MHz
2.46
18 MHz
4.51
36 MHz
9.98
Unit
mA
1. CS = 5 pF (estimated value).
DocID025083 Rev 5
61/115
100
Electrical characteristics
STM32F303x6/x8
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in analog input configuration
•
All peripherals are disabled unless otherwise mentioned
•
The given value is calculated by measuring the current consumption:
•
–
With all peripherals clocked off
–
With only one peripheral clocked on
Ambient operating temperature at 25°C and VDD = VDDA = 3.3 V
Table 35. Peripheral current consumption
Typical consumption(1)
Peripheral
Unit
IDD
BusMatrix (2)
11.1
µA/MHz
DMA1
8.0
-
CRC
2.1
-
GPIOA
8.7
-
GPIOB
8.4
-
GPIOC
8.4
-
GPIOD
2.6
-
GPIOF
1.7
-
TSC
4.7
-
ADC1&2
17.4
-
APB2-Bridge (3)
3.3
-
SYSCFG
4.2
-
TIM1
32.3
-
USART1
20.3
-
TIM15
13.8
-
TIM16
9.7
-
10.3
-
5.3
-
TIM2
43.4
-
TIM3
34.0
-
TIM6
9.7
-
TIM7
10.3
-
WWDG
6.9
-
USART2
18.8
-
USART3
19.1
-
I2C1
13.3
-
TIM17
APB1-Bridge
62/115
(3)
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
Table 35. Peripheral current consumption (continued)
Typical consumption(1)
Peripheral
Unit
IDD
CAN
31.3
-
PWR
4.7
-
DAC
15.4
-
DAC2
8.6
-
SPI1
8.2
-
1. The power consumption of the analog part (IDDA) of peripherals such as ADC, DAC, Comparators, OpAmp
etc. is not included. Refer to the tables of characteristics in the subsequent sections.
2. BusMatrix is automatically active when at least one master is ON (CPU or DMA1).
3. The APBx bridge is automatically active when at least one peripheral is ON on the same bus.
DocID025083 Rev 5
63/115
100
Electrical characteristics
6.3.6
STM32F303x6/x8
Wakeup time from low-power mode
The wakeup times given in Table 36 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•
For Stop or Sleep mode: the wakeup event is WFE.
•
WKUP1 (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 20.
Table 36. Low-power mode wakeup timings
Symbol
Parameter
Wakeup from
Stop mode
tWUSTOP
Typ. @VDD, VDD = VDDA
Conditions
Max.
2.0 V
2.4 V
2.7 V
3V
3.3 V
3.6 V
Regulator in
run mode
4.3
4.1
4.0
3.9
3.8
3.7
4.5
Regulator in
low-power
mode
7.8
6.7
6.1
5.9
5.5
5.3
9
74.4
64.3
60.0
56.9
54.3
51.1
103
tWUSTANDBY(1)
Wakeup from LSI and
Standby mode IWDG OFF
tWUSLEEP
Wakeup from
Sleep mode
-
6
-
Unit
µs
CPU
clock
cycles
1. Data based on characterization results, not tested in production.
Table 37. Wakeup time using USART
6.3.7
Symbol
Parameter
Conditions
Typ
Max
Stop mode with
main regulator in
low power mode
-
13.125
tWUUSART
Wakeup time needed to
calculate the maximum
USART baudrate allowing
to wakeup up from stop
mode when USART clock
source is HSI
Stop mode with
main regulator in
run mode
-
Unit
µs
3.125
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the
recommended clock input waveform is shown in Figure 13.
64/115
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
Table 38. High-speed external user clock characteristics
Symbol
Parameter
Conditions
fHSE_ext
User external clock source
frequency(1)
VHSEH
OSC_IN input pin high-level voltage
VHSEL
OSC_IN input pin low-level voltage
tw(HSEH)
tw(HSEL)
tr(HSE)
tf(HSE)
Min.
Typ.
Max.
Unit
1
8
32
MHz
0.7VDD
-
VDD
VSS
-
0.3VDD
15
-
-
-
OSC_IN high or low time(1)
V
ns
OSC_IN rise or fall time
(1)
-
-
20
1. Guaranteed by design, not tested in production.
Figure 13. High-speed external clock source AC timing diagram
WZ+6(+
9+6(+
9+6(/
WU+6(
WI+6(
W
WZ+6(/
7+6(
069
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the
recommended clock input waveform is shown in Figure 14
Table 39. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
fLSE_ext
User External clock source
frequency(1)
VLSEH
OSC32_IN input pin high-level
voltage
VLSEL
OSC32_IN input pin low-level
voltage
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time(1)
tr(LSE)
tf(LSE)
Min.
Typ.
Max.
Unit
-
32.768
1000
kHz
0.7VDD
-
VDD
V
-
VSS
-
0.3VDD
450
-
ns
OSC32_IN rise or fall
time(1)
-
-
50
1. Guaranteed by design, not tested in production.
DocID025083 Rev 5
65/115
100
Electrical characteristics
STM32F303x6/x8
Figure 14. Low-speed external clock source AC timing diagram
WZ/6(+
9/6(+
9/6(/
WU/6(
WI/6(
W
WZ/6(/
7/6(
069
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 40. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins to minimize output distortion and startup stabilization time. Refer to the
crystal resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 40. HSE oscillator characteristics
Conditions(1)
Min.(2)
Typ.
Max.(2)
Unit
Oscillator frequency
-
4
8
32
MHz
Feedback resistor
-
-
200
-
kΩ
During startup(3)
-
-
8.5
VDD= 3.3 V, Rm= 30Ω,
CL=10 [email protected] MHz
-
0.4
-
VDD= 3.3 V, Rm= 45Ω,
CL=10 [email protected] MHz
-
0.5
-
VDD= 3.3 V, Rm= 30Ω,
CL=5 [email protected] MHz
-
0.8
-
VDD= 3.3 V, Rm= 30Ω,
CL=10 [email protected] MHz
-
1
-
VDD= 3.3 V, Rm= 30Ω,
CL=20 [email protected] MHz
-
1.5
-
Startup
10
-
-
mA/V
VDD is stabilized
-
2
-
ms
Symbol
Parameter
fOSC_IN
RF
IDD
gm
tSU(HSE)(4)
HSE current consumption
Oscillator transconductance
Startup time
mA
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.
66/115
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 15). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 15. Typical application with an 8 MHz crystal
5HVRQDWRUZLWKLQWHJUDWHG
FDSDFLWRUV
&/
26&B,1
0+]
UHVRQDWRU
&/
5(;7 I+6(
5)
%LDV
FRQWUROOHG
JDLQ
26&B287
069
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 41. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins to minimize output distortion and startup stabilization time. Refer to the
crystal resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
DocID025083 Rev 5
67/115
100
Electrical characteristics
STM32F303x6/x8
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
IDD
gm
Conditions(1)
Parameter
LSE current consumption
Oscillator
transconductance
Min.
Max.(
(2)
Typ.
LSEDRV[1:0]=00
lower driving capability
-
0.5
0.9
LSEDRV[1:0]=10
medium low driving
capability
-
-
1
LSEDRV[1:0]=01
medium high-driving
capability
-
-
1.3
LSEDRV[1:0]=11
higher-driving capability
-
-
1.6
LSEDRV[1:0]=00
lower-driving capability
5
-
-
LSEDRV[1:0]=10
medium low-driving
capability
8
-
-
LSEDRV[1:0]=01
medium high-driving
capability
15
-
-
LSEDRV[1:0]=11
higher-driving capability
25
-
-
VDD is stabilized
-
2
-
tSU(LSE)(3) Startup time
2)
Unit
µA
µA/V
s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3.
Note:
68/115
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly
with the crystal manufacturer.
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
Figure 16. Typical application with a 32.768 kHz crystal
5HVRQDWRUZLWKLQWHJUDWHG
FDSDFLWRUV
&/
26&B,1
I+6(
0+]
UHVRQDWRU
5(;7 &/
5)
%LDV
FRQWUROOHG
JDLQ
26&B287
069
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
6.3.8
Internal clock source characteristics
The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 20.
High-speed internal (HSI) RC oscillator
Table 42. HSI oscillator characteristics(1)
Symbol
fHSI
TRIM
DuCy(HSI)
ACCHSI
Parameter
Frequency
Conditions
Min.
Typ.
Max.
Unit
-
-
8
-
MHz
%
%
HSI user trimming step
-
-
-
1(2)
Duty cycle
-
45(2)
-
55(2)
TA = –40 to 105 °C
–2.8(3)
-
3.8(3)
TA = –10 to 85 °C
–1.9(3)
-
2.3(3)
TA = 0 to 85 °C
-1.9(3)
-
2(3)
TA = 0 to 70 °C
-1.3(3)
-
2(3)
TA = 0 to 55 °C
–1(3)
-
2(3)
–1
-
1
Accuracy of the HSI
oscillator (factory
calibrated)
TA = 25 °C(4)
%
tsu(HSI)
HSI oscillator startup
time
-
1(2)
-
2(2)
µs
IDDA(HSI)
HSI oscillator power
consumption
-
-
80
100(2)
µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
4. Factory calibrated, parts not soldered
DocID025083 Rev 5
69/115
100
Electrical characteristics
STM32F303x6/x8
Figure 17. HSI oscillator accuracy characterization results for soldered parts
."9
.*/
5<$>
"
069
Low-speed internal (LSI) RC oscillator
Table 43. LSI oscillator characteristics(1)
Symbol
Min.
Typ.
Max.
Unit
30
40
50
kHz
LSI oscillator startup time
-
-
85
µs
LSI oscillator power consumption
-
0.75
1.2
µA
Frequency
fLSI
tsu(LSI)
Parameter
(2)
IDD(LSI)(2)
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
6.3.9
PLL characteristics
The parameters given in Table 44 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 20.
Table 44. PLL characteristics
Value
Symbol
fPLL_IN
fPLL_OUT
tLOCK
Jitter
Parameter
Unit
Min.
Typ.
Max.
1(2)
-
24(2)
MHz
PLL input clock duty cycle
(2)
40
-
60(2)
%
PLL multiplier output clock
16(2)
-
72
MHz
-
-
200(2)
µs
-
(2)
ps
PLL input clock(1)
PLL lock time
Cycle-to-cycle jitter
-
300
1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
2. Guaranteed by design, not tested in production.
70/115
DocID025083 Rev 5
STM32F303x6/x8
6.3.10
Electrical characteristics
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 45. Flash memory characteristics
Min.
Typ.
Max.(1)
Unit
16-bit programming time TA = –40 to +105 °C
40
53.5
60
µs
Page (2 KB) erase time
TA = –40 to +105 °C
20
-
40
ms
tME
Mass erase time
TA = –40 to +105 °C
20
-
40
ms
IDD
Supply current
Write mode
-
-
10
mA
Erase mode
-
-
12
mA
Symbol
tprog
tERASE
Parameter
Conditions
1. Guaranteed by design, not tested in production.
Table 46. Flash memory endurance and data retention
Value
Symbol
NEND
tRET
Parameter
Endurance
Data retention
Conditions
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
10
1 kcycle(2) at TA = 85 °C
30
(2)
1 kcycle
10
at TA = 105 °C
kcycles(2)
at TA = 55 °C
Unit
Min.(1)
10
kcycles
Years
20
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
6.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 47. They are based on the EMS levels and classes
defined in “EMC design guide for ST microcontrollers” application note (AN1709).
DocID025083 Rev 5
71/115
100
Electrical characteristics
STM32F303x6/x8
Table 47. EMS characteristics
Symbol
Parameter
Conditions
Level/
Class
VFESD
VDD = 3.3 V, LQFP100, TA =
Voltage limits to be applied on any I/O pin to +25°C,
induce a functional disturbance
fHCLK = 72 MHz
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP100, TA =
+25°C,
fHCLK = 72 MHz
conforms to IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note “Software techniques for
improving microcontrollers EMC performance” AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
72/115
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
Table 48. EMI characteristics
Symbol Parameter
SEMI
6.3.12
Max vs. [fHSE/fHCLK]
Monitored
frequency band
Conditions
VDD = 3.6 V, TA =25 °C,
LQFP100 package
Peak level
compliant with IEC
61967-2
Unit
8/72 MHz
0.1 to 30 MHz
5
30 to 130 MHz
9
130 MHz to 1GHz
31
SAE EMI Level
4
dBµV
-
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 49. ESD absolute maximum ratings
Class
Maximum
value(1)
TA = +25 °C,
VESD(HBM Electrostatic discharge
conforming to JESD22voltage (human body model)
)
A114
2
2000
TA = +25 °C,
conforming to JESD22C101
II
Symbol
Ratings
Conditions
Electrostatic discharge
VESD(CD
voltage (charge device
M)
model)
Unit
V
250
1. Data based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 50. Electrical sensitivities
Symbol
LU
Parameter
Static latch-up class
Conditions
TA = +105 °C conforming to JESD78A
DocID025083 Rev 5
Class
II level A
73/115
100
Electrical characteristics
6.3.13
STM32F303x6/x8
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator
frequency deviation). The test results are given in Table 51: I/O current injection
susceptibility.
Table 51. I/O current injection susceptibility
Functional susceptibility
Symbol
IINJ
74/115
Description
Negative
injection
Positive
injection
Injected current on BOOT0
–0
NA
Injected current on PC0, PC1, PC2, PC3 (TTa pins)
and PF1 pin (FT pin)
-0
+5
Injected current on PA0, PA1, PA2, PA3, PA4, PA5,
PA6, PA7, PC4, PC5, PB0, PB1, PB2, PB12, PB13,
PB14, PB15 with induced leakage current on other
pins from this group less than -100 µA or more than
+900 µA
-5
+5
Injected current on PB11, other TT, FT, and FTf pins
–5
NA
Injected current on all other TC, TTa and RESET
pins
–5
+5
DocID025083 Rev 5
Unit
mA
STM32F303x6/x8
Electrical characteristics
Table 51. I/O current injection susceptibility (continued)
Functional susceptibility
Symbol
Description
Negative
injection
Positive
injection
–5
-
-
+5
Injected current on any other FT and FTf pins
–5
NA
Injected current on any other pins
–5
+5
Injected current on PB0, PB1, PB2, PB12, PB13,
PB14, PB15 with induced leakage current on other
pins from this group less than -50 µA
IINJ
Injected current on PC0, PC1, PC2, PC3, PA0, PA1,
PA2, PA3, PA4, PA5, PA6, PA7, PC4, PC5, PB2,
PB0, PB1, PB12, PB13, PB14, PB15 with induced
leakage current on other pins from this group less
than 400 µA
Unit
mA
Note:
It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
6.3.14
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under the conditions summarized in Table 20. All I/Os are CMOS and TTL
compliant.
Table 52. I/O static characteristics
Symbol
VIL
VIH
Parameter
Low-level input
voltage
High-level input
voltage
Conditions
Vhys
Typ.
Max.
Unit
(1)
TT, TC and TTa I/O
-
-
0.3 VDD+0.07
FT and FTf I/O
-
-
0.475 VDD-0.2 (1)
BOOT0
-
-
0.3 VDD–0.3 (1)
All I/Os except BOOT0
-
-
0.3 VDD (2)
TTa and TT I/O
0.445 VDD+0.398 (1)
-
-
FT and FTf I/O
0.5 VDD+0.2 (1)
-
-
BOOT0
0.2 VDD+0.95 (1)
-
-
All I/Os except BOOT0
Schmitt trigger
hysteresis
Min.
0.7 VDD
TT, TC and TTa I/O
-
(2)
-
-
200
(1)
-
(1)
-
FT and FTf I/O
-
100
BOOT0
-
300 (1)
DocID025083 Rev 5
V
mV
75/115
100
Electrical characteristics
STM32F303x6/x8
Table 52. I/O static characteristics (continued)
Symbol
Ilkg
Parameter
Input leakage
current (3)
Conditions
Min.
Typ.
Max.
TC, FT, TT, FTf and TTa
I/O in digital mode
VSS ≤VIN ≤VDD
-
-
±0.1
TTa I/O in digital mode
VDD ≤VIN ≤VDDA
-
-
1
TTa I/O in analog mode
VSS ≤VIN ≤VDDA
-
-
±0.2
FT and FTf I/O(4)
VDD ≤VIN ≤5 V
-
-
10
Unit
µA
RPU
Weak pull-up
equivalent resistor(5)
VIN = VSS
25
40
55
kΩ
RPD
Weak pull-down
equivalent resistor(5)
VIN = VDD
25
40
55
kΩ
CIO
I/O pin capacitance
-
-
5
-
pF
1. Data based on design simulation.
2. Tested in production.
3. Leakage could be higher than the maximum value. If negative current is injected on adjacent pins. Refer to Table 51: I/O
current injection susceptibility.
4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 18 and Figure 19 for standard I/Os.
Figure 18. TC and TTa I/O input characteristics - CMOS port
9,/9,+9
''
HQWV9
9,+PLQ
9
,+PLQ
9
FWLRQ
,+PLQ
%D
SURGX
LQ
7HVWHG
QV
ODWLR
9 ''
LJQVLPX
HV
G
Q
VHGR
GDUG
6VWDQ
&02
HP
UHTXLU
QV
LPXODWLR
'
9 'HVLJQV
QG
R
G
VH
9 ,/PD[
%D
$UHDQRWGHWHUPLQHG
&026VWDQGDUGUHTXLUHPHQWV9,/PD[ 9''
9,/PD[
Q
URGXFWLR
S
7HVWHGLQ
9''9
069
76/115
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
Figure 19. TC and TTa I/O input characteristics - TTL port
9,/9,+9
WLRQV
OD
9 ''
QVLPX
9 ,+PLQ RQGHVLJ
G
%DVH
77/VWDQGDUGUHTXLUHPHQWV9,+PLQ 9
9,+PLQ
V
XODWLRQ
'
9 ' VLJQVLP
H
QG
VHGR
9 ,/PD[
%D
$UHDQRWGHWHUPLQHG
9,/PD[
77/VWDQGDUGUHTXLUHPHQWV9,/PD[ 9
9''9
069
Figure 20. 5V- tolerant (FT and FTf) I/O input characteristics - CMOS port
9,/9,+9
9 ,+PLQ
'
9 '
UHT
QGDUG
6VWD
&02
HQWV
XLUHP
XODWLRQV
'
9 'VLJQVLP
H
RQG
DVHG
9 ,+PLQ
%
ODWLRQV
''
X
9
LJQVLP
9 ,/PD[ RQGHV
G
H
V
D
%
$UHDQRWGHWHUPLQHG
HQWV9,/PD[
UGUHTXLUHP
&026VWDQGD
9''
9''9
-36
Figure 21. 5V-tolerant (FT and FTf) I/O input characteristics - TTL port
9,/9,+9
77/VWDQGDUGUHTXLUHPHQWV9,+PLQ 9
$UHDQRWGHWHUPLQHG
QV
'
ODWLR
9 ' QVLPX
9 ,+PLQ QGHVLJ
GR
%DVH
XODWLRQV
9 ''
HVLJQVLP
LQ
P
G
9 ,/ GRQ
%DVH
77/VWDQGDUGUHTXLUHPHQWV9,/PD[ 9
9''9
069
DocID025083 Rev 5
77/115
100
Electrical characteristics
STM32F303x6/x8
Output driving current
The GPIOs (general-purpose input/output) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 18).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 18).
Output voltage levels
Unless otherwise specified, the parameters given in Table 49: ESD absolute maximum
ratings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 20. All I/Os (FT, TTa and TC unless otherwise
specified) are CMOS and TTL compliant.
Table 53. Output voltage characteristics
Symbol
Parameter
VOL(1)
Low-level output voltage for an I/O pin
VOH(3)
High- level output voltage for an I/O pin
VOL (1)
Low-level output voltage for an I/O pin
VOH (3)
High-level output voltage for an I/O pin
VOL(1)(4)
Low-level output voltage for an I/O pin
VOH(3)(4)
High-level output voltage for an I/O pin
VOL(1)(4)
Low-level output voltage for an I/O pin
VOH(3)(4)
High-level output voltage for an I/O pin
VOLFM+(1)(4)
Low-level output voltage for an FTf I/O pin
in FM+ mode
Conditions
Min.
Max.
CMOS port(2)
IIO = +8 mA
2.7 V < VDD < 3.6 V
-
0.4
VDD–0.4
-
-
0.4
2.4
-
-
1.3
VDD–1.3
-
-
0.4
VDD–0.4
-
-
0.4
TTL port(2)
IIO = +8 mA
2.7 V < VDD < 3.6 V
IIO = +20 mA
2.7 V < VDD < 3.6 V
IIO = +6 mA
2 V < VDD < 2.7 V
IIO = +20 mA
2.7 V < VDD < 3.6 V
Unit
V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 18 and the sum of
IIO (I/O ports and control pins) must not exceed ΣIIO(PIN).
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 18 and the sum
of IIO (I/O ports and control pins) must not exceed ΣIIO(PIN).
4. Data based on design simulation.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 22 and
Table 63, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 20.
78/115
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
Table 54. I/O AC characteristics(1)
OSPEEDRy
[1:0] value(1)
x0
01
Symbol
Parameter
fmax(IO)out
Maximum frequency(2)
tf(IO)out
Output high to low-level
fall time
tr(IO)out
Output low to high-level
rise time
fmax(IO)out
Maximum frequency(2)
tf(IO)out
Output high to low-level
fall time
tr(IO)out
Output low to high-level
rise time
Conditions
CL = 50 pF, VDD = 2 V to 3.6 V
fmax(IO)out
11
tf(IO)out
tr(IO)out
FM+
configuration(4)
-
Maximum
Output high to low-level
fall time
Output low to high-level
rise time
fmax(IO)out
Maximum frequency(2)
tf(IO)out
Output high to low-level
fall time
tr(IO)out
Output low to high-level
rise time
tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
Max.
Unit
-
12(3)
MHz
-
125(3)
-
125(3)
-
410(3)
CL = 50 pF, VDD = 2 V to 3.6 V
CL = 50 pF, VDD = 2 V to 3.6 V
ns
CL = 50 pF, VDD = 2 V to 3.6 V
-
MHz
25
(3)
25
ns
(3)
-
50(3)
MHz
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
30(3)
MHz
CL = 50 pF, VDD = 2 V to 2.7 V
-
20(3)
MHz
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
-
12(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
-
12(3)
-
2(4)
-
12(4)
-
(4)
CL = 30 pF, VDD = 2.7 V to 3.6 V
frequency(2)
Min.
CL = 50 pF, VDD = 2 V to 3.6 V
-
ns
MHz
ns
10(3)
34
-
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0364 reference manual for a description of
GPIO Port configuration register.
2. The maximum frequency is defined in Figure 22.
3. Guaranteed by design, not tested in production.
4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F30x and STM32F301xx reference manual
RM0364 for a description of FM+ I/O mode configuration.
DocID025083 Rev 5
79/115
100
Electrical characteristics
STM32F303x6/x8
Figure 22. I/O AC characteristics definition
(;7(51$/
287387
21&/
WU,2RXW
WI,2RXW
7
0D[LPXPIUHTXHQF\LVDFKLHYHGLIWUWI”7DQGLIWKHGXW\F\FOHLV
ZKHQORDGHGE\&/VSHFLILHGLQWKHWDEOH³,2$&FKDUDFWHULVWLFV´
6.3.15
DLG
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 52).
Unless otherwise specified, the parameters given in Table 55 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 20.
Table 55. NRST pin characteristics
Symbol
Parameter
VIL(NRST)(1) NRST Input low level voltage
VIH(NRST)(1)
NRST Input high-level voltage
Vhys(NRST)
NRST Schmitt trigger voltage hysteresis
RPU
VF(NRST)(1)
VNF(NRST)(1)
Weak pull-up equivalent resistor
NRST Input filtered pulse
NRST Input not filtered pulse
(2)
Conditions
Min.
Typ.
Max.
-
-
-
0.3VDD+
0.07(1)
-
0.445VDD+
0.398(1)
-
-
-
-
200
-
mV
VIN = VSS
25
40
55
kΩ
-
-
-
100(1)
ns
-
-
ns
-
(1)
500
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
80/115
DocID025083 Rev 5
Unit
V
STM32F303x6/x8
Electrical characteristics
Figure 23. Recommended NRST pin protection
([WHUQDO
UHVHWFLUFXLW
9''
1567
538
,QWHUQDOUHVHW
)LOWHU
—)
069
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 55. Otherwise the reset will not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
4. Place the external capacitor 0.1u F on NRST as close as possible to the chip.
DocID025083 Rev 5
81/115
100
Electrical characteristics
6.3.16
STM32F303x6/x8
Timer characteristics
The parameters given in Table 56 are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 56. TIMx(1)(2) characteristics
Symbol
tres(TIM)
fEXT
ResTIM
tCOUNTER
Parameter
Timer resolution time
Timer external clock
frequency on CH1 to CH4
Timer resolution
16-bit counter clock period
tMAX_COUN Maximum possible count
with 32-bit counter
T
Conditions
Min.
Max.
Unit
-
1
-
tTIMxCL
fTIMxCLK = 72 MHz
13.9
-
ns
fTIM1CLK = 144 MHz
6.95
-
ns
-
0
fTIMxCLK/2
MHz
fTIMxCLK = 72 MHz
0
36
MHz
TIMx (except TIM2)
-
16
TIM2
-
32
-
1
65536
tTIMxCL
fTIMxCLK = 72 MHz
0.0139
910
µs
fTIM1CLK = 144 MHz
0.0069
455
µs
-
-
65536 × 65536
tTIMxCL
fTIMxCLK = 72 MHz
-
59.65
s
fTIM1CLK = 144 MHz
-
29.825
s
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3,TIM15, TIM16 and TIM17 timers.
2. Guaranteed by design, not tested in production.
82/115
DocID025083 Rev 5
K
bit
K
K
STM32F303x6/x8
Electrical characteristics
Table 57. IWDG min./max. timeout period at 40 kHz (LSI) (1)
Prescaler divider
PR[2:0] bits
Min. timeout (ms) RL[11:0]=
0x000
Max. timeout (ms) RL[11:0]=
0xFFF
/4
0
0.1
409.6
/8
1
0.2
819.2
/16
2
0.4
1638.4
/32
3
0.8
3276.8
/64
4
1.6
6553.6
/128
5
3.2
13107.2
/256
7
6.4
26214.4
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Table 58. WWDG min./max. timeout value at 72 MHz (PCLK)(1)
Prescaler
WDGTB
Min. timeout value
Max. timeout value
1
0
0.05687
3.6409
2
1
0.1137
7.2817
4
2
0.2275
14.564
8
3
0.4551
29.127
1. Guaranteed by design, not tested in production.
6.3.17
Communication interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
•
Standard-mode (Sm): with a bit rate up to 100 Kbit/s
•
Fast-mode (Fm): with a bit rate up to 400 Kbit/s
•
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present. Only FTf I/O pins
support Fm+ low-level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/O characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
DocID025083 Rev 5
83/115
100
Electrical characteristics
STM32F303x6/x8
Table 59. I2C analog filter characteristics(1)
Symbol
Parameter
Min.
Max.
Unit
tAF
Maximum pulse width of spikes that are
suppressed by the analog filter.
50(2)
260(3)
ns
1. Guaranteed by design, not tested in production.
2. Spikes with width below tAF(min.) are filtered.
3. Spikes with width above tAF(max.) are not filtered.
SPI characteristics
Unless otherwise specified, the parameters given in Table 55 for SPI are derived from tests
performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
summarized in Table 20: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 60. SPI characteristics(1)
Symbol
fSCK
1/tc(SCK)
Parameter
SPI clock frequency
Conditions
Master mode 2<VDD<3.6
18
Slave mode 2<VDD<3.6
NSS setup time
th(NSS)
NSS hold time
SCK high and low time
tsu(SI)
th(MI)
th(SI)
-
-
Slave mode transmitter/full
duplex
2<VDD<3.6
tsu(NSS)
tsu(MI)
Data input setup time
Data input hold time
Max
24
Slave mode
tw(SCKH)
tw(SCKL)
Typ
Master mode 2.7<VDD<3.6
Duty cycle of SPI clock
frequency
DuCy(SCK)
Min
24
30
50
70
Slave mode, SPI presc = 2
4*Tpclk
-
-
Slave mode, SPI presc = 2
2*Tpclk
-
-
Master mode
Tpclk-2
Tpclk
Tpclk+2
Master mode
0
-
-
Slave mode
3
-
-
Master mode
5
-
-
Slave mode
1
-
-
Data output access time
Slave mode
10
-
40
tdis(SO)
Data output disable time
Slave mode
10
-
17
Slave mode 2.7<VDD<3.6V
-
12
20
Slave mode 2<VDD<3.6V
-
12
27.5
Master mode
-
1.5
5
Slave mode
7.5
-
-
Master mode
0
-
-
Data output valid time
tv(MO)
th(SO)
th(MO)
Data output hold time
MHz
18(2)
ta(SO)
tv(SO)
Unit
1. Data based on characterization results, not tested in production.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK
low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a
master having tsu(MI) = 0 while Duty(SCK) = 50%.
84/115
DocID025083 Rev 5
%
ns
STM32F303x6/x8
Electrical characteristics
Figure 24. SPI timing diagram - slave mode and CPHA = 0
166LQSXW
6&.,QSXW
W68166
WK166
WF6&.
&3+$ &32/ WZ6&.+
WZ6&./
&3+$ &32/ W962
WD62
0,62
287387
WU6&.
WI6&.
WK62
06%287
%,7287
06%,1
%,7,1
WGLV62
/6%287
WVX6,
026,
,1387
/6%,1
WK6,
DLF
Figure 25. SPI timing diagram - slave mode and CPHA = 1(1)
166LQSXW
6&.LQSXW
W68166
&3+$ &32/ &3+$ &32/ WZ6&.+
WZ6&./
WK62
WY62
WD62
0,62
287387
06%287
%,7287
WU6&.
WI6&.
WGLV62
/6%287
WK6,
WVX6,
026,
,1387
WK166
WF6&.
06%,1
%,7,1
/6%,1
DLE
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
DocID025083 Rev 5
85/115
100
Electrical characteristics
STM32F303x6/x8
Figure 26. SPI timing diagram - master mode(1)
+LJK
166LQSXW
6&.2XWSXW
6&.2XWSXW
WF6&.
&3+$ &32/ &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX0,
0,62
,13 87
WZ6&.+
WZ6&./
WU6&.
WI6&.
%,7,1
06%,1
/6%,1
WK0,
026,
287387
% , 7287
06%287
WY02
/6%287
WK02
DLF
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
CAN (controller area network) interface
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
6.3.18
ADC characteristics
Unless otherwise specified, the parameters given in Table 61 to Table 64 are guaranteed by
design, with conditions summarized in Table 20.
Table 61. ADC characteristics
Symbol
VDDA
IDDA
86/115
Parameter
Analog supply voltage for
ADC
ADC current consumption
(Figure 27)
Conditions
Min.
Typ.
Max.
Unit
-
2
-
3.6
V
Single ended mode, 5
MSPS,
-
1011.3
1172.0
Single ended mode, 1
MSPS
-
214.7
322.3
Single ended mode, 200
KSPS
-
54.7
81.1
Differential mode,5
MSPS,
-
1061.5
1243.6
Differential mode, 1
MSPS
-
246.6
337.6
Differential mode, 200
KSPS
-
56.4
83.0
DocID025083 Rev 5
µA
STM32F303x6/x8
Electrical characteristics
Table 61. ADC characteristics (continued)
Symbol
Parameter
VREF-
Negative reference voltage
fADC
ADC clock frequency
fS
fTRIG
Sampling rate
External trigger frequency
Conditions
Min.
Typ.
Max.
0
Unit
V
-
0.14
-
72
MHz
Resolution = 12 bits,
Fast Channel
0.01
-
5.14
Resolution = 10 bits,
Fast Channel
0.012
-
6
Resolution = 8 bits,
Fast Channel
0.014
-
7.2
Resolution = 6 bits,
Fast Channel
0.0175
-
9
fADC = 72 MHz
Resolution = 12 bits
-
-
5.14
MHz
Resolution = 12 bits
-
-
14
1/fADC
MSPS
VAIN
Conversion voltage range
-
0
-
VDDA
V
RAIN
External input impedance
-
-
-
100
κΩ
CADC
Internal sample and hold
capacitor
-
-
5
-
pF
tCAL
Calibration time
tlatr
Trigger conversion latency
Regular and injected
channels without
conversion abort
tlatrinj
tS
Trigger conversion latency
Injected channels aborting
a regular conversion
Sampling time
tADCVREG ADC Voltage Regulator
Start-up time
_STUP
tSTAB
Power-up time
fADC = 72 MHz
1.56
µs
-
112
1/fADC
CKMODE = 00
1.5
2
2.5
1/fADC
CKMODE = 01
-
-
2
1/fADC
CKMODE = 10
-
-
2.25
1/fADC
CKMODE = 11
-
-
2.125
1/fADC
CKMODE = 00
2.5
3
3.5
1/fADC
CKMODE = 01
-
-
3
1/fADC
CKMODE = 10
-
-
3.25
1/fADC
CKMODE = 11
-
-
3.125
1/fADC
fADC = 72 MHz
0.021
-
8.35
µs
-
1.5
-
601.5
1/fADC
-
-
-
10
µs
-
DocID025083 Rev 5
1
conver
sion
cycle
87/115
100
Electrical characteristics
STM32F303x6/x8
Table 61. ADC characteristics (continued)
Symbol
tCONV
CMIR
Parameter
Total conversion time
(including sampling time)
Common Mode Input
signal
Conditions
Min.
Typ.
Max.
Unit
fADC = 72 MHz
Resolution = 12 bits
0.19
-
8.52
µs
14 to 614 (tS for sampling + 12.5 for
successive approximation)
Resolution = 12 bits
ADC differential mode
(VSSA+VREF+)/2 (VSSA +
-0.18
VREF+)/2
1/fADC
(VSSA +
VREF+)/2
+ 0.18
V
$'&FXUUHQWFRQVXPSWLRQ—$
Figure 27. ADC typical current consumption in single-ended and differential modes
&ORFNIUHTXHQF\0636
069
Table 62. Maximum ADC RAIN(1)
Resolution
12 bits
88/115
RAIN max. (kΩ)
Sampling
cycle @
72 MHz
Sampling
time [ns] @
72 MHz
Fast channels(2)
Slow
channels
Other
channels(3)
1.5
20.83
0.018
NA
NA
2.5
34.72
0.150
NA
0.022
4.5
62.50
0.470
0.220
0.180
7.5
104.17
0.820
0.560
0.470
19.5
270.83
2.70
1.80
1.50
61.5
854.17
8.20
6.80
4.70
181.5
2520.83
22.0
18.0
15.0
601.5
8354.17
82.0
68.0
47.0
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
Table 62. Maximum ADC RAIN(1) (continued)
Resolution
10 bits
8 bits
6 bits
RAIN max. (kΩ)
Sampling
cycle @
72 MHz
Sampling
time [ns] @
72 MHz
Fast channels(2)
Slow
channels
Other
channels(3)
1.5
20.83
0.082
NA
NA
2.5
34.72
0.270
0.082
0.100
4.5
62.50
0.560
0.390
0.330
7.5
104.17
1.20
0.82
0.68
19.5
270.83
3.30
2.70
2.20
61.5
854.17
10.0
8.2
6.8
181.5
2520.83
33.0
27.0
22.0
601.5
8354.17
100.0
82.0
68.0
1.5
20.83
0.150
NA
0.039
2.5
34.72
0.390
0.180
0.180
4.5
62.50
0.820
0.560
0.470
7.5
104.17
1.50
1.20
1.00
19.5
270.83
3.90
3.30
2.70
61.5
854.17
12.00
12.00
8.20
181.5
2520.83
39.00
33.00
27.00
601.5
8354.17
100.00
100.00
82.00
1.5
20.83
0.270
0.100
0.150
2.5
34.72
0.560
0.390
0.330
4.5
62.50
1.200
0.820
0.820
7.5
104.17
2.20
1.80
1.50
19.5
270.83
5.60
4.70
3.90
61.5
854.17
18.0
15.0
12.0
181.5
2520.83
56.0
47.0
39.0
601.5
8354.17
100.00
100.0
100.0
1. Data based on characterization results, not tested in production.
2. All fast channels, expect channel on PA6.
3. Channels available on PA6.
DocID025083 Rev 5
89/115
100
Electrical characteristics
STM32F303x6/x8
Table 63. ADC accuracy - limited test conditions(1)(2)
Symbol Parameter
ET
Single ended
Total
unadjusted
error
Differential
Single ended
EO
Offset error
Differential
Single ended
EG
Gain error
Differential
ED
EL
ENOB
(4)
SINAD
(4)
90/115
Differential
linearity
error
Integral
linearity
error
Effective
number of
bits
Signal-tonoise and
distortion
ratio
Min
Conditions
ADC clock freq. ≤ 72 MHz
Sampling freq. ≤ 5 Msps
VDDA = 3.3 V
25°C
Single ended
Differential
Single ended
Differential
Single ended
Differential
Single ended
Differential
DocID025083 Rev 5
Max
(3)
Typ
Fast channel 5.1 Ms
-
±4
±4.5
Slow channel 4.8 Ms
-
±5.5
±6
Fast channel 5.1 Ms
-
±3.5
±4
Slow channel 4.8 Ms
-
±3.5
±4
Fast channel 5.1 Ms
-
±2
±2
Slow channel 4.8 Ms
-
±1.5
±2
Fast channel 5.1 Ms
-
±1.5
±2
Slow channel 4.8 Ms
-
±1.5
±2
Fast channel 5.1 Ms
-
±3
±4
Slow channel 4.8 Ms
-
±5
±5.5
Fast channel 5.1 Ms
-
±3
±3
Slow channel 4.8 Ms
-
±3
±3.5
Fast channel 5.1 Ms
-
±1
±1
Slow channel 4.8 Ms
-
±1
±1
Fast channel 5.1 Ms
-
±1
±1
Slow channel 4.8 Ms
-
±1
±1
Fast channel 5.1 Ms
-
±1.5
±2
Slow channel 4.8 Ms
-
±2
±3
Fast channel 5.1 Ms
-
±1.5 ±1.5
Slow channel 4.8 Ms
-
±1.5
(3)
Unit
LSB
±2
Fast channel 5.1 Ms
10.8 10.8
-
Slow channel 4.8 Ms
10.8 10.8
-
Fast channel 5.1 Ms
11.2 11.3
-
Slow channel 4.8 Ms
11.2 11.3
-
Fast channel 5.1 Ms
66
67
-
Slow channel 4.8 Ms
66
67
-
Fast channel 5.1 Ms
69
70
-
Slow channel 4.8 Ms
69
70
-
bit
dB
STM32F303x6/x8
Electrical characteristics
Table 63. ADC accuracy - limited test conditions(1)(2) (continued)
Symbol Parameter
Min
Conditions
Single ended
SNR(4)
THD(4)
Signal-tonoise ratio
Total
harmonic
distortion
ADC clock freq. ≤ 72 MHz
Sampling freq ≤ 5 Msps
VDDA = 3.3 V
25°C
Differential
Single ended
Differential
Max
(3)
Typ
Fast channel 5.1 Ms
66
67
-
Slow channel 4.8 Ms
66
67
-
Fast channel 5.1 Ms
69
70
-
Slow channel 4.8 Ms
69
70
-
Fast channel 5.1 Ms
-
-80
-80
Slow channel 4.8 Ms
-
-78
-77
Fast channel 5.1 Ms
-
-83
-82
Slow channel 4.8 Ms
-
-81
-80
(3)
Unit
dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Data based on characterization results, not tested in production.
4. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal.
Table 64. ADC accuracy (1)(2)(3)
Symbol Parameter
ET
Single ended
Total
unadjusted
error
Differential
Single ended
EO
Offset error
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 5 Msps
2.0 V ≤ VDDA ≤ 3.6 V
EG
Differential
Single ended
Gain error
Differential
ED
Differential
linearity
error
Min(4)
Max(4)
Unit
Fast channel 5.1 Ms
-
±6.5
LSB
Slow channel 4.8 Ms
-
±6.5
Fast channel 5.1 Ms
-
±4
Slow channel 4.8 Ms
-
±4.5
Conditions
Single ended
Differential
Fast channel 5.1 Ms
-
±3
Slow channel 4.8 Ms
-
±3
Fast channel 5.1 Ms
-
±2.5
Slow channel 4.8 Ms
-
±2.5
Fast channel 5.1 Ms
-
±6
Slow channel 4.8 Ms
-
±6
Fast channel 5.1 Ms
-
±3.5
Slow channel 4.8 Ms
-
±4
Fast channel 5.1 Ms
-
±1.5
Slow channel 4.8 Ms
-
±1.5
Fast channel 5.1 Ms
-
±1.5
Slow channel 4.8 Ms
-
±1.5
DocID025083 Rev 5
91/115
100
Electrical characteristics
STM32F303x6/x8
Table 64. ADC accuracy (1)(2)(3) (continued)
Symbol Parameter
EL
ENOB
(5)
SINAD
(5)
SNR(5)
THD(5)
Single ended
Integral
linearity
error
Effective
number of
bits
Differential
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 5 Msps
2.0 V ≤ VDDA ≤ 3.6 V
Signal-tonoise and
distortion
ratio
Single ended
Differential
Single ended
Differential
Single ended
Signal-tonoise ratio
Total
harmonic
distortion
Min(4)
Max(4)
Fast channel 5.1 Ms
-
±3
Slow channel 4.8 Ms
-
±3.5
Fast channel 5.1 Ms
-
±2
Slow channel 4.8 Ms
-
±2.5
Conditions
ADC clock freq. ≤ 72 MHz,
Sampling freq ≤ 5 Msps,
2.0 V ≤ VDDA ≤ 3.6 V
Differential
Single ended
Differential
Fast channel 5.1 Ms
10.4
-
Slow channel 4.8 Ms
10.4
-
Fast channel 5.1 Ms
10.8
-
Slow channel 4.8 Ms
10.8
-
Fast channel 5.1 Ms
64
-
Slow channel 4.8 Ms
63
-
Fast channel 5.1 Ms
67
-
Slow channel 4.8 Ms
67
-
Fast channel 5.1 Ms
64
-
Slow channel 4.8 Ms
64
-
Fast channel 5.1 Ms
67
-
Slow channel 4.8 Ms
67
-
Fast channel 5.1 Ms
-
-75
Slow channel 4.8 Ms
-
-75
Fast channel 5.1 Ms
-
-79
Slow channel 4.8 Ms
-
-78
Unit
bits
dB
dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
5. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal.
92/115
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
Table 65. ADC accuracy(1)(2) at 1MSPS
Symbol
Parameter
ET
Total unadjusted error
EO
Offset error
Typ
Max(3)
Fast channel
±2.5
±5
Slow channel
±3.5
±5
Fast channel
±1
±2.5
Slow channel
±1.5
±2.5
Fast channel
±2
±3
Slow channel
±3
±4
Fast channel
±0.7
±2
Slow channel
±0.7
±2
Fast channel
±1
±3
Slow channel
±1.2
±3
Test conditions
ADC Freq ≤ 72 MHz
Sampling Freq ≤ 1MSPS
2 V ≤ VDDA = VREF+ ≤ 3.6 V
Single-ended mode
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
Unit
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current
within the limits specified for IINJ(PIN) and ∑IINJ(PIN) in Section 6.3.14: I/O port characteristics does not affect the ADC
accuracy.
3. Data based on characterization results, not tested in production.
Figure 28. ADC accuracy characteristics
9
/6%,'($/ ''$
(*
([DPSOHRIDQDFWXDOWUDQVIHUFXUYH
7KHLGHDOWUDQVIHUFXUYH
(QGSRLQWFRUUHODWLRQOLQH
(7
(2
(/
('
(7 7RWDO 8QDGMXVWHG (UURU PD[LPXP GHYLDWLRQ
EHWZHHQWKHDFWXDODQGWKHLGHDOWUDQVIHUFXUYHV
(2 2IIVHW(UURUGHYLDWLRQEHWZHHQWKHILUVWDFWXDO
WUDQVLWLRQDQGWKHILUVWLGHDORQH
(* *DLQ (UURU GHYLDWLRQ EHWZHHQ WKH ODVW LGHDO
WUDQVLWLRQDQGWKHODVWDFWXDORQH
(' 'LIIHUHQWLDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ
EHWZHHQDFWXDOVWHSVDQGWKHLGHDORQH
(/ ,QWHJUDO /LQHDULW\ (UURU PD[LPXP GHYLDWLRQ
EHWZHHQ DQ\ DFWXDO WUDQVLWLRQ DQG WKH HQG SRLQW
FRUUHODWLRQOLQH
/ 6%,'($/
966$
9''$
DocID025083 Rev 5
069
93/115
100
Electrical characteristics
STM32F303x6/x8
Figure 29. Typical connection diagram using the ADC
9''
6DPSOHDQGKROG$'&
FRQYHUWHU
97
9
5$,1 9$,1
5$'&
$,1[
97
9
&SDUDVLWLF
ELW
FRQYHUWHU
,/“—$
&$'&
069
1. Refer to Table 61 for the values of RAIN.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 10: Power-supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
6.3.19
DAC electrical specifications
Table 66. DAC characteristics
Symbol
VDDA
Parameter
Analog supply voltage
Conditions
Min.
Typ.
Max.
Unit
-
2.4
-
3.6
V
RLOAD(1)
Resistive load
DAC output buffer ON (to VSSA )
5
-
-
kΩ
RLOAD(1)
Resistive load
DAC output buffer ON (to VDDA)
25
-
-
kΩ
Output impedance
DAC output buffer OFF
-
-
15
kΩ
Capacitive load
DAC output buffer ON
-
-
50
pF
0.2
-
VDDA – 0.2
V
-
0.5
-
mV
-
-
VDDA– 1LSB
V
With no load, middle code (0x800)
on the input
-
-
380
µA
With no load, worst code (0xF1C) on
the input.
-
-
480
µA
RO(1)
CLOAD(1)
VDAC_OUT( Voltage on DAC_OUT
1)
output
Corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VDDA = 3.6 V
and (0x155) and (0xEAB) at VDDA =
2.4 V
DAC output buffer OFF
(3)
IDDA
94/115
DAC DC current
consumption in quiescent
mode(2)
DocID025083 Rev 5
STM32F303x6/x8
Electrical characteristics
Table 66. DAC characteristics (continued)
Symbol
Min.
Typ.
Max.
Unit
Given for a 10-bit input code
DAC1 channel 1
-
-
±0.5
LSB
Given for a 12-bit input code
DAC1 channel 1
-
-
±2
LSB
Given for a 10-bit input code
DAC1 channel 2 & DAC2 channel 1
-
-
-0.75/+0.25
LSB
Given for a 12-bit input code
DAC1 channel 2 & DAC2 channel 1
-
-
-3/+1
LSB
Integral non linearity
Given for a 10-bit input code
(difference between
measured value at Code i
and the value at Code i on a Given for a 12-bit input code
line drawn between Code 0
and last Code 4095)
-
-
±1
LSB
-
-
±4
LSB
Offset error
(difference between
Given for a 10-bit input code at
measured value at Code
VDDA = 3.6 V
(0x800) and the ideal value
Given for a 12-bit input code
= VDDA/2)
-
-
±10
mV
-
-
±3
LSB
-
-
±12
LSB
Gain error
-
-
±0.5
%
Settling time (full scale: for
a 12-bit input code
tSETTLING(3 transition between the
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
)
lowest and the highest input
codes when DAC_OUT
reaches final value ±1LSB
-
3
4
µs
Max frequency for a correct
DAC_OUT change when
small variation in the input CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
code (from code i to
i+1LSB)
-
-
1
MS/
s
DAC buffer ON
Output level higher than 0.2 V
100
-
-
µA
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
-
6.5
10
µs
-
–67
–40
dB
DNL(3)
INL(3)
Offset(3)
Gain
error(3)
Update
rate(3)
Iskink
Parameter
Differential non linearity
Difference between two
consecutive code-1LSB)
Output sink current
Wakeup time from off state
tWAKEUP(3) (Setting the ENx bit in the
DAC Control register)
Conditions
Given for a 12-bit input code
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC
No RLOAD, CLOAD = 50 pF
measurement
1. Guaranteed by design, not tested in production.
2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is
involved.
3. Data based on characterization results, not tested in production.
DocID025083 Rev 5
95/115
100
Electrical characteristics
STM32F303x6/x8
Figure 30. 12-bit buffered /non-buffered DAC
%XIIHUHG1RQEXIIHUHG'$&
%XIIHU
5 /
'$&B287[
ELW
GLJLWDOWR
DQDORJ
FRQYHUWHU
& /
AI6
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
6.3.20
Comparator characteristics
Table 67. Comparator characteristics(1)
Symbol
Conditions
Min.
Typ.
Max.
Unit
Analog supply voltage
-
2
-
3.6
V
VIN
Comparator input voltage
range
-
0
-
VDDA
-
VBG
Scaler input voltage
-
-
VREFINIT
-
-
VSC
Scaler offset voltage
-
-
±5
±10
mV
tS_SC
First VREFINT scaler activation
VREFINT scaler startup time after device power on
from power down
Next activations
-
-
1(2)
s
-
-
0.2
ms
VDDA ≥ 2.7 V
-
-
4
VDDA < 2.7 V
-
-
10
Propagation delay for
200 mV step with 100 mV
overdrive
VDDA ≥ 2.7 V
-
25
28
-
28
30
Propagation delay for full
range step with 100 mV
overdrive
VDDA ≥ 2.7 V
-
32
35
-
35
40
-
±5
±10
-
-
±25
-
-
3
mV
-
400
600
µA
VDDA
tSTART
Parameter
Comparator startup time
tD
VDDA < 2.7 V
ns
VOFFSET
Comparator offset error
TVOFFSET
Total offset variation
IDD(COMP)
COMP current
consumption
VDDA < 2.7 V
VDDA ≥ 2.7 V
VDDA < 2.7 V
Full temperature range
-
1. Guaranteed by design, not tested in production.
2. For more details and conditions see Figure 31: Maximum VREFINT scaler startup time from power-down.
96/115
µs
DocID025083 Rev 5
mV
STM32F303x6/x8
Electrical characteristics
Figure 31. Maximum VREFINT scaler startup time from power-down
6.3.21
Operational amplifier characteristics
Table 68. Operational amplifier characteristics(1)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VDDA
Analog supply voltage
-
2.4
-
3.6
V
CMIR
Common mode input range
-
0
-
VDDA
V
-
-
4
-
-
6
25°C, No Load
on output.
-
-
1.6
All
voltage/Temp.
-
-
3
VIOFFSET
Input offset voltage
25°C, No Load
on output.
Maximum
calibration range All
voltage/Temp.
After offset
calibration
ΔVIOFFSET
mV
Input offset voltage drift
-
-
5
-
µV/°C
ILOAD
Drive current
-
-
-
500
µA
IDDOPAMP
Consumption
No load,
quiescent mode
-
690
1450
µA
-
-
90
-
dB
73
117
-
dB
CMRR
Common mode rejection ratio
PSRR
Power supply rejection ratio
GBW
Bandwidth
-
-
8.2
-
MHz
SR
Slew rate
-
-
4.7
-
V/µs
RLOAD
Resistive load
-
4
-
-
kΩ
CLOAD
Capacitive load
-
-
-
50
pF
DC
DocID025083 Rev 5
97/115
100
Electrical characteristics
STM32F303x6/x8
Table 68. Operational amplifier characteristics(1) (continued)
Symbol
VOHSAT
VOLSAT
ϕm
tOFFTRIM
tWAKEUP
Parameter
Condition
High saturation voltage(2)
Low saturation voltage
Min.
Typ.
Rload = min,
Input at VDDA.
VDDA-100
-
Rload = 20K,
Input at VDDA.
VDDA-20
-
Rnetwork
-
-
100
Rload = 20K,
input at 0 V.
-
-
20
Phase margin
-
-
62
-
°
Offset trim time: during calibration,
minimum time needed between two
steps to have 1 mV accuracy
-
-
-
2
ms
-
2.8
5
µs
400
-
-
ns
-
2
-
-
-
4
-
-
-
8
-
-
-
16
-
-
Gain=2
-
5.4/5.4
-
Gain=4
-
16.2/5.4
-
Gain=8
-
37.8/5.4
-
Gain=16
-
40.5/2.7
-
-1%
-
1%
µA
CLOAD ≤50 pf,
RLOAD ≥ 4 kΩ,
Follower
configuration
Wake up time from OFF state.
Non inverting gain value
-
R2/R1 internal resistance values in
PGA mode (3)
PGA gain error PGA gain error
Ibias
PGA BW
98/115
Unit
mV
Rload = min,
input at 0 V
tS_OPAM_VOUT ADC sampling time when reading the OPAMP output
PGA gain
Max.
-
OPAMP input bias current
PGA bandwidth for different non
inverting gain
-
-
-
±0.2(4)
PGA Gain = 2,
Cload = 50pF,
Rload = 4 KΩ
-
4
-
PGA Gain = 4,
Cload = 50pF,
Rload = 4 KΩ
-
2
-
PGA Gain = 8,
Cload = 50pF,
Rload = 4 KΩ
-
1
-
PGA Gain = 16,
Cload = 50pF,
Rload = 4 KΩ
-
0.5
-
DocID025083 Rev 5
kΩ
MHz
STM32F303x6/x8
Electrical characteristics
Table 68. Operational amplifier characteristics(1) (continued)
Symbol
en
Parameter
Voltage noise density
Condition
Min.
Typ.
Max.
@ 1KHz, Output
loaded with
4 KΩ
-
109
-
@ 10KHz,
Output loaded
with 4 KΩ
-
43
-
Unit
nV
----------Hz
1. Guaranteed by design, not tested in production.
2. The saturation voltage can also be limited by the Iload
3. R2 is the internal resistance between OPAMP output and OPAMP inverting input.
R1 is the internal resistance between OPAMP inverting input and ground.
The PGA gain =1+R2/R1
4. Mostly TTa I/O leakage, when used in analog mode.
Figure 32. OPAMP Voltage Noise versus Frequency
DocID025083 Rev 5
99/115
100
Electrical characteristics
6.3.22
STM32F303x6/x8
Temperature sensor (TS) characteristics
Table 69. Temperature sensor (TS) characteristics
Symbol
Parameter
TL(1)
Min.
Typ.
Max.
Unit
-
±1
±2
°C
Average slope
4.0
4.3
4.6
mV/°C
Voltage at 25 °C
1.34
1.43
1.52
V
4
-
10
µs
2.2
-
-
µs
VSENSE linearity with temperature
(1)
Avg_Slope
V25
tSTART(1)
TS_temp(1)(2)
Startup time
ADC sampling time when reading the
temperature
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
Table 70. Temperature sensor (TS) calibration values
Calibration value name
6.3.23
Description
Memory address
TS_CAL1
TS ADC raw data acquired at
temperature of 30 °C,
VDDA= 3.3 V
0x1FFF F7B8 - 0x1FFF F7B9
TS_CAL2
TS ADC raw data acquired at
temperature of 110 °C
VDDA= 3.3 V
0x1FFF F7C2 - 0x1FFF F7C3
VBAT monitoring characteristics
Table 71. VBAT monitoring characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
R
Resistor bridge for VBAT
-
50
-
KΩ
Q
Ratio on VBAT measurement
-
2
-
-
Error on Q
-1
-
+1
%
ADC sampling time when reading the VBAT
1mV accuracy
2.2
-
-
µs
Er(1)
TS_vbat(1)(2)
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
100/115
DocID025083 Rev 5
STM32F303x6/x8
Package information
7
Package information
7.1
Package mechanical data
To meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
DocID025083 Rev 5
101/115
112
Package information
7.2
STM32F303x6/x8
LQFP32 package information
LQFP32 is a 32-pin, 7 x 7mm low-profile quad flat package.
Figure 33. LQFP32 package outline
C
!
!
!
3%!4).'
0,!.%
#
MM
CCC
'!5'%0,!.%
#
+
$
!
,
$
,
$
0).
)$%.4)&)#!4)/.
%
%
%
B
E
[email protected]&@7
1. Drawing is not to scale.
Table 72. LQFP32 mechanical data
Inches(1)
Millimeters
Symbol
102/115
Min.
Typ.
Max.
Min.
Typ.
Max.
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
DocID025083 Rev 5
STM32F303x6/x8
Package information
Table 72. LQFP32 mechanical data (continued)
Inches(1)
Millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
b
0.300
0.370
0.450
0.0118
0.0146
0.0177
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.600
-
-
0.2205
-
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.600
-
-
0.2205
-
e
-
0.800
-
-
0.0315
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0.0°
3.5°
7.0°
0.0°
3.5°
7.0°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 34. Recommended footprint for the LQFP32 package
6?&0?6
1. Drawing is not to scale.
2. Dimensions are expressed in millimeters.
DocID025083 Rev 5
103/115
112
Package information
STM32F303x6/x8
Device marking for LQFP32
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 35. LQFP32 marking example (package top view)
3URGXFW,GHQWLILFDWLRQ
670)
.7
< ::
5HYLVLRQFRGH
5
3LQ
LQGHQWLILHU
06Y9
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
104/115
DocID025083 Rev 5
STM32F303x6/x8
7.3
Package information
LQFP48 package information
LQFP48 is a 48-pin, 7 x 7mm low-profile quad flat package.
Figure 36. LQFP48 package outline
C
!
!
!
3%!4).'
0,!.%
#
MM
'!5'%0,!.%
CCC #
+
!
$
$
,
,
$
0).
)$%.4)&)#!4)/.
%
%
%
B
E
"?-%?6
1. Drawing is not to scale.
Table 73. LQFP48 package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.500
-
-
0.2165
-
DocID025083 Rev 5
105/115
112
Package information
STM32F303x6/x8
Table 73. LQFP48 package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.500
-
-
0.2165
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 37. Recommended footprint for the LQFP48 package
AID
1. Drawing is not to scale.
2. Dimensions are in millimeters.
106/115
DocID025083 Rev 5
STM32F303x6/x8
Package information
Device marking for LQFP48
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 38. LQFP48 marking example (package top view)
3URGXFW,GHQWLILFDWLRQ
670)
&7
< ::
5HYLVLRQFRGH
5
3LQ
LQGHQWLILHU
06Y9
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID025083 Rev 5
107/115
112
Package information
7.4
STM32F303x6/x8
LQFP64 package information
LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package.
Figure 39. LQFP64 package outline
PP
*$8*(3/$1(
F
$
$
$
6($7,1*3/$1(
&
$
FFF &
'
'
'
.
/
/
(
(
(
E
3,1
,'(17,),&$7,21
H
:B0(B9
1. Drawing is not to scale.
Table 74. LQFP64 package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
11.800
12.000
-
-
0.4724
-
D1
9.800
10.000
-
-
0.3937
-
E
-
12.000
-
-
0.4724
-
E1
-
10.000
-
-
0.3937
-
e
-
0.500
-
-
0.0197
-
108/115
DocID025083 Rev 5
STM32F303x6/x8
Package information
Table 74. LQFP64 package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
Number of pins
N
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 40. Recommended footprint for the LQFP64 package
AIC
1. Drawing is not to scale.
2. Dimensions are in millimeters.
DocID025083 Rev 5
109/115
112
Package information
STM32F303x6/x8
Device marking for LQFP64
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 41. LQFP64 marking example (package top view)
5HYLVLRQFRGH
5
(QJLQHHULQJ6DPSOHPDUNLQJ
670)
57
3LQ
LQGHQWLILHU
< ::
06Y9
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
110/115
DocID025083 Rev 5
STM32F303x6/x8
7.5
Package information
Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
•
TA max is the maximum ambient temperature in ° C,
•
ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/O max),
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 75. Package thermal characteristics
Symbol
7.5.1
Parameter
Value
Unit
ΘJA
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
45°C/W
°C/W
ΘJA
Thermal resistance junction-ambient
LQFP32 - 7 × 7 mm / 0.8 mm pitch
60°C/W
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
7.5.2
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 76: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F303x6/8 at maximum dissipation, it is
useful to calculate the exact power consumption and junction temperature to determine
which temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example: high-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
DocID025083 Rev 5
111/115
112
Package information
STM32F303x6/x8
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
mode at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V = 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW
PDmax = 175 + 272 = 447 mW
Thus: PDmax = 447 mW
Using the values obtained in Table 75 TJmax is calculated as follows:
–
For LQFP48, 55 °C/W
TJmax = 82 °C + (55 °C/W × 236.6 mW) = 82 °C + 13.01 °C = 95.01°C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Table 76: Ordering information scheme).
112/115
DocID025083 Rev 5
STM32F303x6/x8
8
Part numbering
Part numbering
Table 76. Ordering information scheme
Example:
STM32
F
303
C
8
T
6
xxx
Device family
STM32 = ARM®-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
303 = STM32F303
Pin count
K = 32 pins
C = 48 pins
R = 64 pins
Flash memory size
6 = 32 Kbytes of Flash memory
8 = 64 Kbytes of Flash memory
Package
T = LQFP
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Options
xxx = programmed parts
TR = tape and reel
DocID025083 Rev 5
113/115
113
Revision history
9
STM32F303x6/x8
Revision history
Table 77. Document revision history
Date
Revision
11-Apr-2014
1
Initial release.
9-Dec-2014
2
Updated:
Table 73: Package thermal characteristics: remove Note 1.
Table 17: Voltage characteristics: added line in VIN
Table 35: Low-power mode wakeup timings: updated Max
values
Table 40: HSI oscillator characteristics (Accuracy of the
oscillator)
Table 40: HSI oscillator characteristics (Accuracy of the
oscillator)
Table 54: TIMx characteristics
Table 59: ADC characteristics
Table 34: Peripheral current consumption
Table 2: STM32F303x6/8 family device features and
peripherals count
Figure 17: HSI oscillator accuracy characterization results for
soldered parts
Updated notes of Table 31: Typical current consumption in
Run mode, code with data processing running from Flash and
Table 32: Typical current consumption in Sleep mode, code
running from Flash or RAM.
09-May-2015
4
Updated Section Table 14.: STM32F303x6/8 pin definitions
and Section Table 15.: Alternate functions
3
Updated:
Figure 1: STM32F303x6/8 block diagram
Table 40: HSE oscillator characteristics
Table 45: Flash memory characteristics
Added Figure 13: High-speed external clock source AC timing
diagram
5
Updated:
Section Table 66.: DAC characteristics, Section Table 61.:
ADC characteristics,Table 55: NRST pin characteristics,
Figure 2: Clock tree,Table 14: STM32F303x6/8 pin
definitions,Table 68: Operational amplifier characteristics,
Figure 20: 5V- tolerant (FT and FTf) I/O input characteristics CMOS port, Table 24: Embedded internal reference voltage,
Table 41: LSE oscillator characteristics (fLSE = 32.768 kHz).
Added:
Table 37: Wakeup time using USART.
2-Feb-2015
05-Oct-2016
114/115
Changes
DocID025083 Rev 5
STM32F303x6/x8
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
DocID025083 Rev 5
115/115
115
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement