Freescale Semiconductor MPC880, MPC885, PowerQUICC MPC870, MPC870, PowerQUICC MPC875, PowerQUICC MPC880, MPC875, PowerQUICC MPC885 Reference manual

Freescale Semiconductor MPC880, MPC885, PowerQUICC MPC870, MPC870, PowerQUICC MPC875, PowerQUICC MPC880, MPC875, PowerQUICC MPC885 Reference manual
MPC885
PowerQUICC™ Family
Reference Manual
Supports:
MPC885
MPC880
MPC875
MPC870
MPC885RM
Rev. 2, 04/2006
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© Freescale Semiconductor, Inc., 2006. All rights reserved.
Document Number: MPC885RM
Rev. 2, 04/2006
Part I—Overview
MPC885 Overview
Memory Map
Part II—MPC8xx Microprocessor Module
The MPC8xx Core
MPC8xx Core Register Set
MPC885 Instruction Set
Exceptions
Instruction and Data Caches
Memory Management Unit
Instruction Execution Timing
Part III—Configuration and Reset
System Interface Unit
Reset
Part IV—Hardware Interface
External Signals
External Bus Interface
Clocks and Power Control
Memory Controller
PCMCIA Interface
Part V—Communications Processor Module
Communications Processor Module and CPM Timers
Communications Processor
SDMA Channels and IDMA Emulation
Serial Interface
Serial Communications Controllers
SCC UART Mode
SCC HDLC Mode
SCC AppleTalk Mode
SCC Asynchronous HDLC Mode and IrDA
SCC BISYNC Mode
SCC Ethernet Mode
SCC Transparent Mode
Serial Management Controllers (SMCs)
Serial Peripheral Interface (SPI)
Universal Serial Bus (USB)
I2C Controller
Parallel Interface Port (PIP)
Parallel I/O Ports
CPM Interrupt Controller
I
1
2
II
3
4
5
6
7
8
9
III
10
11
IV
12
13
14
15
16
V
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I
1
2
II
3
4
5
6
7
8
9
III
10
11
IV
12
13
14
15
16
V
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Part I—Overview
MPC885 Overview
Memory Map
Part II—MPC8xx Microprocessor Module
The MPC8xx Core
MPC8xx Core Register Set
MPC885 Instruction Set
Exceptions
Instruction and Data Caches
Memory Management Unit
Instruction Execution Timing
Part III—Configuration and Reset
System Interface Unit
Reset
Part IV—Hardware Interface
External Signals
External Bus Interface
Clocks and Power Control
Memory Controller
PCMCIA Interface
Part V—Communications Processor Module
Communications Processor Module and CPM Timers
Communications Processor
SDMA Channels and IDMA Emulation
Serial Interface
Serial Communications Controllers
SCC UART Mode
SCC HDLC Mode
SCC AppleTalk Mode
SCC Asynchronous HDLC Mode and IrDA
SCC BISYNC Mode
SCC Ethernet Mode
SCC Transparent Mode
Serial Management Controllers (SMCs)
Serial Peripheral Interface (SPI)
Universal Serial Bus (USB)
I2C Controller
Parallel Interface Port (PIP)
Parallel I/O Ports
CPM Interrupt Controller
Part VI—Asynchronous Transfer Mode (ATM)
ATM Overview
Buffer Descriptors and Connection Tables
ATM Parameter RAM
ATM Controller
ATM Pace Control
ATM Exceptions
Interface Configuration
UTOPIA Interface
AAL2 Implementation
Part VII—Fast Ethernet Controller (FEC)
Fast Ethernet Controller (FEC)
Part VIII—Integrated Security Engine (SEC Lite)
SEC Lite Overview
SEC Lite Address Map
SEC Lite Execution Units
SEC Lite Descriptors
SEC Lite Crypto-Channel
SEC Lite Controller
Fast Ethernet Controller (FEC)
Part IX—System Debugging and Testing Support
System Development and Debugging
IEEE 1149.1 Test Access Port
Byte Ordering
Serial Communications Performance
Register Quick Reference Guide
Instruction Set Listings
MPC880/MPC875/MPC870 Differences
Serial ATM Scrambling, Reception, and SI Programming
Revision History
Glossary of Terms and Abbreviations
Index
VI
36
37
38
39
40
41
42
43
44
VII
45
VIII
46
47
48
49
50
51
52
IX
53
54
A
B
C
D
E–G
H
I
GLOS
INDEX
VI
36
37
38
39
40
41
42
43
44
VII
45
VIII
46
47
48
49
50
51
52
IX
53
54
A
B
C
D
E–G
H
I
GLOS
INDEX
Part VI—Asynchronous Transfer Mode (ATM)
ATM Overview
Buffer Descriptors and Connection Tables
ATM Parameter RAM
ATM Controller
ATM Pace Control
ATM Exceptions
Interface Configuration
UTOPIA Interface
AAL2 Implementation
Part VII—Fast Ethernet Controller (FEC)
Fast Ethernet Controller (FEC)
Part VIII—Integrated Security Engine (SEC Lite)
SEC Lite Overview
SEC Lite Address Map
SEC Lite Execution Units
SEC Lite Descriptors
SEC Lite Crypto-Channel
SEC Lite Controller
Fast Ethernet Controller (FEC)
Part IX—System Debugging and Testing Support
System Development and Debugging
IEEE 1149.1 Test Access Port
Byte Ordering
Serial Communications Performance
Register Quick Reference Guide
Instruction Set Listings
MPC880/MPC875/MPC870 Differences
Serial ATM Scrambling, Reception, and SI Programming
Revision History
Glossary of Terms and Abbreviations
Index
Contents
Paragraph
Number
Title
Page
Number
Contents
About This Book
Before Using This Manual ............................................................................. lxxxiii
Audience ........................................................................................................ lxxxiv
Organization................................................................................................... lxxxiv
Suggested Reading....................................................................................... lxxxviii
MPC8xx Documentation .......................................................................................... lxxxviii
Related Documentation............................................................................................. lxxxviii
Conventions ................................................................................................... lxxxix
Acronyms and Abbreviations ............................................................................... xc
PowerPC Architecture Terminology Conventions............................................ xciii
Part I
Overview
Chapter 1
MPC885 Overview
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
Features ............................................................................................................................ 1-2
Embedded MPC8xx Core .............................................................................................. 1-15
System Interface Unit (SIU) .......................................................................................... 1-16
PCMCIA Controller....................................................................................................... 1-17
Power Management ....................................................................................................... 1-17
Security Engine.............................................................................................................. 1-17
Fast Ethernet Controller (FEC)...................................................................................... 1-18
Universal Serial Bus (USB) ........................................................................................... 1-18
Communications Processor Module (CPM) .................................................................. 1-18
ATM Capabilities ........................................................................................................... 1-19
Chapter 2
Memory Map
Part II
MPC8xx Microprocessor Module
Chapter 3
The MPC8xx Core
3.1
3.2
3.2.1
The MPC885 Core as a PowerPC Implementation ......................................................... 3-1
PowerPC Architecture Overview..................................................................................... 3-2
Levels of the PowerPC Architecture ........................................................................... 3-3
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Contents
Paragraph
Number
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.3.1
3.4.3.2
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.3.1
3.6.3.2
3.6.3.3
3.6.3.4
3.6.3.5
3.6.3.6
3.7
Title
Page
Number
Features ............................................................................................................................ 3-4
Basic Structure of the Core .............................................................................................. 3-5
Instruction Flow........................................................................................................... 3-6
Basic Instruction Pipeline ............................................................................................ 3-7
Instruction Unit ............................................................................................................ 3-7
Branch Operations ................................................................................................... 3-7
Dispatching Instructions .......................................................................................... 3-9
Register Set ...................................................................................................................... 3-9
Execution Units................................................................................................................ 3-9
Branch Processing Unit ............................................................................................... 3-9
Integer Unit .................................................................................................................. 3-9
Load/Store Unit.......................................................................................................... 3-10
Executing Load/Store Instructions......................................................................... 3-11
Serializing Load/Store Instructions ....................................................................... 3-12
Store Accesses ....................................................................................................... 3-12
Nonspeculative Load Instructions ......................................................................... 3-12
Unaligned Accesses ............................................................................................... 3-12
Atomic Update Primitives ..................................................................................... 3-13
The MPC885 and Implementation of the PowerPC Architecture ................................. 3-14
Chapter 4
MPC8xx Core Register Set
4.1
4.1.1
4.1.1.1
4.1.1.1.1
4.1.1.1.2
4.1.1.1.3
4.1.1.1.4
4.1.2
4.1.2.1
4.1.2.2
4.1.2.3
4.1.2.3.1
4.1.2.3.2
4.1.3
4.1.3.1
4.2
MPC885 Register Implementation .................................................................................. 4-1
PowerPC Registers—User Registers ........................................................................... 4-1
PowerPC User-Level Register Bit Assignments ..................................................... 4-2
Condition Register (CR)...................................................................................... 4-2
Condition Register CR0 Field Definition ............................................................ 4-3
XER ..................................................................................................................... 4-3
Time Base Registers ............................................................................................ 4-4
PowerPC Registers—Supervisor Registers ................................................................. 4-4
DAR, DSISR, and BAR Operation.......................................................................... 4-5
Unsupported Registers............................................................................................. 4-6
PowerPC Supervisor-Level Register Bit Assignments............................................ 4-6
Machine State Register (MSR)............................................................................ 4-6
Processor Version Register .................................................................................. 4-8
MPC885-Specific SPRs............................................................................................... 4-9
Accessing SPRs ..................................................................................................... 4-11
Register Initialization at Reset ....................................................................................... 4-12
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Paragraph
Number
Title
Page
Number
Chapter 5
MPC885 Instruction Set
5.1
5.1.1
5.1.2
5.2
5.2.1
5.2.1.1
5.2.1.2
5.2.1.3
5.2.1.4
5.2.2
5.2.2.1
5.2.2.2
5.2.2.3
5.2.2.3.1
5.2.2.3.2
5.2.2.3.3
5.2.3
5.2.4
5.2.4.1
5.2.4.1.1
5.2.4.1.2
5.2.4.1.3
5.2.4.1.4
5.2.4.2
5.2.4.2.1
5.2.4.2.2
5.2.4.2.3
5.2.4.2.4
5.2.4.2.5
5.2.4.2.6
5.2.4.3
5.2.4.3.1
5.2.4.3.2
5.2.4.3.3
5.2.4.4
5.2.4.5
5.2.4.5.1
5.2.4.6
Operand Conventions ...................................................................................................... 5-1
Data Organization in Memory and Data Transfers...................................................... 5-1
Aligned and Misaligned Accesses ............................................................................... 5-1
Instruction Set Summary ................................................................................................. 5-2
Classes of Instructions ................................................................................................. 5-3
Definition of Boundedly Undefined ........................................................................ 5-3
Defined Instruction Class ........................................................................................ 5-3
Illegal Instruction Class ........................................................................................... 5-4
Reserved Instruction Class ...................................................................................... 5-4
Addressing Modes ....................................................................................................... 5-5
Memory Addressing ................................................................................................ 5-5
Effective Address Calculation ................................................................................. 5-5
Synchronization ....................................................................................................... 5-6
Context Synchronization ..................................................................................... 5-6
Execution Synchronization.................................................................................. 5-6
Instruction-Related Exceptions............................................................................ 5-6
Instruction Set Overview ............................................................................................. 5-7
PowerPC UISA Instructions ........................................................................................ 5-7
Integer Instructions .................................................................................................. 5-7
Integer Arithmetic Instructions............................................................................ 5-7
Integer Compare Instructions .............................................................................. 5-8
Integer Logical Instructions................................................................................. 5-9
Integer Rotate and Shift Instructions ................................................................. 5-10
Load and Store Instructions ................................................................................... 5-11
Integer Load and Store Address Generation...................................................... 5-11
Register Indirect Integer Load Instructions ....................................................... 5-11
Integer Store Instructions................................................................................... 5-12
Integer Load and Store with Byte-Reverse Instructions.................................... 5-12
Integer Load and Store Multiple Instructions.................................................... 5-13
Integer Load and Store String Instructions ........................................................ 5-13
Branch and Flow Control Instructions................................................................... 5-14
Branch Instruction Address Calculation............................................................ 5-14
Branch Instructions............................................................................................ 5-15
Condition Register Logical Instructions............................................................ 5-15
Trap Instructions .................................................................................................... 5-15
Processor Control Instructions............................................................................... 5-16
Move to/from Condition Register Instructions.................................................. 5-16
Memory Synchronization Instructions—UISA ..................................................... 5-16
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Contents
Paragraph
Number
5.2.5
5.2.5.1
5.2.5.2
5.2.5.2.1
5.2.5.2.2
5.2.5.3
5.2.6
5.2.6.1
5.2.6.2
5.2.6.2.1
5.2.6.2.2
5.2.6.3
Title
Page
Number
PowerPC VEA Instructions ....................................................................................... 5-18
Processor Control Instructions............................................................................... 5-18
Memory Synchronization Instructions—VEA ...................................................... 5-18
eieio Behavior.................................................................................................... 5-19
isync Behavior ................................................................................................... 5-19
Memory Control Instructions—VEA .................................................................... 5-19
PowerPC OEA Instructions ....................................................................................... 5-20
System Linkage Instructions.................................................................................. 5-20
Processor Control Instructions—OEA .................................................................. 5-20
Move to/from Machine State Register Instructions........................................... 5-21
Move to/from Special-Purpose Register Instructions........................................ 5-21
Memory Control Instructions—OEA .................................................................... 5-21
Chapter 6
Exceptions
6.1
6.1.1
6.1.2
6.1.2.1
6.1.2.2
6.1.2.3
6.1.2.4
6.1.2.5
6.1.2.6
6.1.2.6.1
6.1.2.7
6.1.2.8
6.1.2.9
6.1.2.10
6.1.2.11
6.1.3
6.1.3.1
6.1.3.2
6.1.3.3
6.1.3.4
6.1.3.5
6.1.3.6
6.1.4
6.1.5
Exceptions........................................................................................................................ 6-1
Exception Ordering...................................................................................................... 6-3
PowerPC-Defined Exceptions ..................................................................................... 6-4
System Reset Interrupt (0x00100) ........................................................................... 6-4
Machine Check Interrupt (0x00200) ....................................................................... 6-5
DSI Exception (0x00300) ........................................................................................ 6-6
ISI Exception (0x00400).......................................................................................... 6-6
External Interrupt Exception (0x00500).................................................................. 6-6
Alignment Exception (0x00600) ............................................................................. 6-7
Integer Alignment Exceptions ............................................................................. 6-8
Program Exception (0x00700)................................................................................. 6-8
Decrementer Exception (0x00900).......................................................................... 6-9
System Call Exception (0x00C00) ........................................................................ 6-10
Trace Exception (0x00D00)................................................................................... 6-11
Floating-Point Assist Exception ............................................................................ 6-11
Implementation-Specific Exceptions......................................................................... 6-12
Software Emulation Exception (0x01000) ............................................................ 6-12
Instruction TLB Miss Exception (0x01100) .......................................................... 6-12
Data TLB Miss Exception (0x01200).................................................................... 6-13
Instruction TLB Error Exception (0x01300) ......................................................... 6-13
Data TLB Error Exception (0x014000) ................................................................. 6-14
Debug Exceptions (0x01C00–0x01F00) ............................................................... 6-15
Implementing the Precise Exception Model.............................................................. 6-16
Recoverability After an Exception ............................................................................ 6-16
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Paragraph
Number
6.1.6
6.1.7
Title
Page
Number
Exception Latency ..................................................................................................... 6-18
Partially Completed Instructions ............................................................................... 6-19
Chapter 7
Instruction and Data Caches
7.1
7.2
7.3
7.3.1
7.3.1.1
7.3.1.2
7.3.1.2.1
7.3.1.2.2
7.3.1.2.3
7.3.1.2.4
7.3.1.2.5
7.3.2
7.3.2.1
7.3.2.2
7.3.2.2.1
7.3.2.2.2
7.3.2.2.3
7.3.2.2.4
7.3.2.2.5
7.3.2.2.6
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.6
Instruction Cache Organization ....................................................................................... 7-2
Data Cache Organization ................................................................................................. 7-4
Cache Control Registers .................................................................................................. 7-6
Instruction Cache Control Registers ............................................................................ 7-6
Reading Data and Tags in the Instruction Cache..................................................... 7-8
IC_CST Commands................................................................................................. 7-9
Instruction Cache Enable/Disable Commands .................................................... 7-9
Instruction Cache Load-and-Lock Cache Block Command................................ 7-9
Instruction Cache Unlock Cache Block Command ........................................... 7-10
Instruction Cache Unlock All Command .......................................................... 7-10
Instruction Cache Invalidate All Command ...................................................... 7-11
Data Cache Control Registers.................................................................................... 7-11
Reading Data Cache Tags and Copyback Buffer................................................... 7-14
DC_CST Commands ............................................................................................. 7-15
Data Cache Enable/Disable Commands ............................................................ 7-15
Data Cache Load-and-Lock Cache Block Command........................................ 7-15
Data Cache Unlock Cache Block Command..................................................... 7-16
Data Cache Unlock All Command .................................................................... 7-16
Data Cache Invalidate All Command................................................................ 7-16
Data Cache Flush Cache Block Command........................................................ 7-17
Cache Control Instructions ............................................................................................ 7-17
Instruction Cache Block Invalidate (icbi).................................................................. 7-17
Data Cache Block Touch (dcbt) and
Data Cache BlockTouch for Store (dcbtst) ........................................................... 7-18
Data Cache Block Zero (dcbz) .................................................................................. 7-18
Data Cache Block Store (dcbst) ................................................................................ 7-18
Data Cache Block Flush (dcbf) ................................................................................. 7-19
Data Cache Block Invalidate (dcbi) .......................................................................... 7-19
Instruction Cache Operations......................................................................................... 7-19
Instruction Cache Hit ................................................................................................. 7-21
Instruction Cache Miss .............................................................................................. 7-21
Instruction Fetching on a Predicted Path ................................................................... 7-21
Fetching Instructions from Caching-Inhibited Regions............................................. 7-22
Updating Code and Memory Region Attributes ........................................................ 7-22
Data Cache Operation .................................................................................................... 7-22
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Contents
Paragraph
Number
7.6.1
7.6.2
7.6.3
7.6.3.1
7.6.3.2
7.6.4
7.6.4.1
7.6.4.2
7.6.5
7.6.6
7.7
7.8
7.8.1
7.8.2
Title
Page
Number
Data Cache Load Hit.................................................................................................. 7-23
Data Cache Read Miss............................................................................................... 7-23
Write-Through Mode ................................................................................................. 7-24
Data Cache Store Hit in Write-Through Mode...................................................... 7-24
Data Cache Store Miss in Write-Through Mode ................................................... 7-24
Write-Back Mode....................................................................................................... 7-25
Data Cache Store Hit in Write-Back Mode ........................................................... 7-25
Data Cache Store Miss in Write-Back Mode......................................................... 7-25
Data Accesses to Caching-Inhibited Memory Regions ............................................. 7-26
Atomic Memory References...................................................................................... 7-26
Cache Initialization after Reset...................................................................................... 7-27
Debug Support ............................................................................................................... 7-27
Instruction and Data Cache Operation in Debug Mode............................................. 7-27
Instruction and Data Cache Operation with a Software Monitor Debugger.............. 7-28
Chapter 8
Memory Management Unit
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.4
8.5
8.6
8.7
8.7.1
8.7.2
8.7.3
8.8
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.8.7
8.8.8
8.8.9
Features ............................................................................................................................ 8-1
PowerPC Architecture Compliance ................................................................................. 8-2
Address Translation ......................................................................................................... 8-2
Translation Disabled .................................................................................................... 8-2
Translation Enabled ..................................................................................................... 8-3
TLB Operation............................................................................................................. 8-5
Using Access Protection Groups ..................................................................................... 8-6
Protection Resolution Modes........................................................................................... 8-7
Memory Attributes........................................................................................................... 8-8
Translation Table Structure .............................................................................................. 8-8
Level-One Descriptor ................................................................................................ 8-11
Level-Two Descriptor ................................................................................................ 8-12
Page Size.................................................................................................................... 8-13
Programming Model ...................................................................................................... 8-13
IMMU Control Register (MI_CTR) .......................................................................... 8-14
DMMU Control Register (MD_CTR) ....................................................................... 8-15
IMMU/DMMU Effective Page Number Register (Mx_EPN) .................................. 8-16
IMMU Tablewalk Control Register (MI_TWC) ....................................................... 8-17
DMMU Tablewalk Control Register (MD_TWC) .................................................... 8-18
IMMU Real Page Number Register (MI_RPN) ........................................................ 8-19
DMMU Real Page Number Register (MD_RPN) ..................................................... 8-20
MMU Tablewalk Base Register (M_TWB)............................................................... 8-22
MMU Current Address Space ID Register (M_CASID)........................................... 8-22
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Paragraph
Number
8.8.10
8.8.11
8.8.12
8.8.12.1
8.8.12.2
8.8.12.3
8.8.12.4
8.8.12.5
8.8.13
8.9
8.10
8.10.1
8.10.1.1
8.10.2
8.10.3
8.10.4
Title
Page
Number
MMU Access Protection Registers (MI_AP/MD_AP) ............................................. 8-23
MMU Tablewalk Special Register (M_TW) ............................................................. 8-23
MMU Debug Registers.............................................................................................. 8-24
IMMU CAM Entry Read Register (MI_CAM)..................................................... 8-24
IMMU RAM Entry Read Register 0 (MI_RAM0)................................................ 8-25
IMMU RAM Entry Read Register 1 (MI_RAM1)................................................ 8-26
DMMU CAM Entry Read Register (MD_CAM).................................................. 8-27
DMMU RAM Entry Read Register 0 (MD_RAM0)............................................. 8-28
DMMU RAM Entry Read Register 1 (MD_RAM1)................................................. 8-29
Memory Management Unit Exceptions ......................................................................... 8-31
TLB Manipulation ......................................................................................................... 8-31
TLB Reload................................................................................................................ 8-31
Translation Reload Examples ................................................................................ 8-32
Locking TLB Entries ................................................................................................. 8-33
Loading Locked TLB Entries .................................................................................... 8-33
TLB Invalidation........................................................................................................ 8-33
Chapter 9
Instruction Execution Timing
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.1.7
9.2
9.2.1
9.2.2
9.2.3
Instruction Execution Timing Examples.......................................................................... 9-1
Data Cache Load with a Data Dependency ................................................................. 9-1
Writeback Arbitration .................................................................................................. 9-2
Private Writeback Bus Load ........................................................................................ 9-2
Fastest External Load (Data Cache Miss).................................................................... 9-3
A Full Completion Queue............................................................................................ 9-3
Branch Instruction Handling........................................................................................ 9-4
Branch Prediction ........................................................................................................ 9-5
Instruction Timing List .................................................................................................... 9-5
Load/Store Instruction Timing..................................................................................... 9-7
String Instruction Latency ........................................................................................... 9-8
Accessing Off-Core SPRs............................................................................................ 9-8
Part III
Configuration and Reset
Chapter 10
System Interface Unit
10.1
10.2
Features .......................................................................................................................... 10-1
System Configuration and Protection ............................................................................ 10-2
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Paragraph
Number
10.3
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.5
10.5.1
10.5.2
10.5.3
10.5.3.1
10.5.4
10.5.4.1
10.5.4.2
10.5.4.3
10.5.4.4
10.6
10.7
10.7.1
10.8
10.8.1
10.9
10.9.1
10.9.2
10.9.3
10.10
10.10.1
10.10.2
10.10.3
10.11
10.11.1
Title
Page
Number
Multiplexing SIU Pins ................................................................................................... 10-3
Programming the SIU .................................................................................................... 10-4
Internal Memory Map Register (IMMR)................................................................... 10-4
SIU Module Configuration Register (SIUMCR)....................................................... 10-5
System Protection Control Register (SYPCR) .......................................................... 10-7
Transfer Error Status Register (TESR) ...................................................................... 10-8
Register Lock Mechanism ......................................................................................... 10-9
System Configuration .................................................................................................. 10-11
Interrupt Structure.................................................................................................... 10-11
Priority of Interrupt Sources .................................................................................... 10-12
SIU Interrupt Processing.......................................................................................... 10-13
Nonmaskable Interrupts—IRQ0 and SWT.......................................................... 10-14
Programming the SIU Interrupt Controller.............................................................. 10-14
SIU Interrupt Pending Register (SIPEND).......................................................... 10-15
SIU Interrupt Mask Register (SIMASK) ............................................................. 10-16
SIU Interrupt Edge/Level Register (SIEL) .......................................................... 10-17
SIU Interrupt Vector Register (SIVEC) ............................................................... 10-17
The Bus Monitor .......................................................................................................... 10-19
Software Watchdog Timer ........................................................................................... 10-20
Software Service Register (SWSR) ......................................................................... 10-21
The Decrementer.......................................................................................................... 10-22
Decrementer Register (DEC)................................................................................... 10-22
Timebase ...................................................................................................................... 10-23
Timebase Register (TBU and TBL)......................................................................... 10-23
Timebase Reference Registers (TBREFA and TBREFB) ....................................... 10-24
Timebase Status and Control Register (TBSCR)..................................................... 10-25
Periodic Interrupt Timer (PIT)..................................................................................... 10-25
Periodic Interrupt Status and Control Register (PISCR) ......................................... 10-26
PIT Count Register (PITC) ...................................................................................... 10-27
PIT Register (PITR)................................................................................................. 10-28
General SIU Timers Operation .................................................................................... 10-28
Freeze Operation...................................................................................................... 10-28
Chapter 11
Reset
11.1
11.1.1
11.1.2
11.1.3
11.1.3.1
Types of Reset................................................................................................................ 11-1
Power-On Reset ......................................................................................................... 11-2
External Hard Reset ................................................................................................... 11-2
Internal Hard Reset .................................................................................................... 11-2
Software Watchdog Reset...................................................................................... 11-3
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Contents
Paragraph
Number
11.1.3.2
11.1.4
11.1.5
11.1.6
11.1.7
11.1.8
11.1.9
11.2
11.3
11.3.1
11.3.1.1
11.3.2
11.4
Title
Page
Number
Checkstop Reset..................................................................................................... 11-3
Debug Port Hard or Soft Reset .................................................................................. 11-3
JTAG Reset ................................................................................................................ 11-3
Power-On and Hard Reset Sequence ......................................................................... 11-3
External Soft Reset .................................................................................................... 11-4
Internal Soft Reset ..................................................................................................... 11-4
Soft Reset Sequence................................................................................................... 11-4
Reset Status Register (RSR) .......................................................................................... 11-4
MPC885 Reset Configuration........................................................................................ 11-6
Hard Reset.................................................................................................................. 11-6
Hard Reset Configuration Word ............................................................................ 11-8
Soft Reset................................................................................................................. 11-10
TRST Considerations................................................................................................... 11-10
Part IV
Hardware Interface
Chapter 12
External Signals
12.1
12.1.1
12.1.2
12.2
12.2.1
12.2.2
12.3
12.4
12.5
12.6
12.6.1
12.6.1.1
12.6.2
12.6.3
12.6.4
12.7
MPC885/MPC880 Signals............................................................................................. 12-1
MPC885/MPC880 Signals and Pin Numbers............................................................ 12-1
MPC885/MPC880 System Bus Signals..................................................................... 12-4
MPC875/MPC870 Signals........................................................................................... 12-23
MPC875/MPC870 Signals and Pin Numbers.......................................................... 12-23
MPC875/MPC870 System Bus Signals................................................................... 12-26
Reset Behavior ............................................................................................................. 12-39
Active Pull-Up Buffers ................................................................................................ 12-40
Internal Pull-Up and Pull-Down Resistors ................................................................. 12-42
Recommended Basic Pin Connections ........................................................................ 12-42
Reset Configuration ................................................................................................. 12-42
Bus Control Signals and Interrupts...................................................................... 12-42
JTAG and Debug Ports ............................................................................................ 12-43
Unused Inputs .......................................................................................................... 12-43
Unused Outputs........................................................................................................ 12-43
Signal States During Reset........................................................................................... 12-44
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Paragraph
Number
Title
Page
Number
Chapter 13
External Bus Interface
13.1
13.2
13.3
13.4
13.4.1
13.4.2
13.4.2.1
13.4.2.2
13.4.3
13.4.4
13.4.5
13.4.6
13.4.6.1
13.4.6.2
13.4.6.3
13.4.6.4
13.4.7
13.4.7.1
13.4.7.2
13.4.7.3
13.4.7.3.1
13.4.7.3.2
13.4.7.3.3
13.4.7.3.4
13.4.7.3.5
13.4.8
13.4.8.1
13.4.8.2
13.4.8.3
13.4.8.4
13.4.9
13.4.9.1
13.4.9.2
13.4.10
13.4.10.1
Features .......................................................................................................................... 13-1
Bus Transfer Overview .................................................................................................. 13-1
Bus Interface Signal Descriptions.................................................................................. 13-2
Bus Operations............................................................................................................... 13-6
Basic Transfer Protocol.............................................................................................. 13-6
Single-Beat Transfer .................................................................................................. 13-6
Single-Beat Read Flow .......................................................................................... 13-7
Single-Beat Write Flow ....................................................................................... 13-10
Burst Transfers......................................................................................................... 13-14
Burst Operations ...................................................................................................... 13-14
Alignment and Data Packing on Transfers .............................................................. 13-23
Arbitration Phase ..................................................................................................... 13-25
Bus Request (BR) ................................................................................................ 13-26
Bus Grant (BG).................................................................................................... 13-26
Bus Busy (BB)..................................................................................................... 13-27
External Bus Parking ........................................................................................... 13-29
Address Transfer Phase-Related Signals ................................................................. 13-29
Transfer Start (TS) ............................................................................................... 13-29
Address Bus ......................................................................................................... 13-30
Transfer Attributes ............................................................................................... 13-30
Read/Write (RD/WR) ...................................................................................... 13-30
Burst Indicator (BURST)................................................................................. 13-30
Transfer Size (TSIZ)........................................................................................ 13-30
Address Types (AT) ......................................................................................... 13-30
Burst Data in Progress (BDIP) ........................................................................ 13-33
Termination Signals ................................................................................................. 13-33
Transfer Acknowledge (TA) ................................................................................ 13-33
Burst Inhibit (BI) ................................................................................................. 13-33
Transfer Error Acknowledge (TEA).................................................................... 13-33
Termination Signals Protocol .............................................................................. 13-33
Memory Reservation................................................................................................ 13-35
Cancel Reservation (CR) ..................................................................................... 13-35
Kill Reservation (KR).......................................................................................... 13-36
Bus Exception Control Cycles................................................................................. 13-37
RETRY ................................................................................................................ 13-38
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Paragraph
Number
Title
Page
Number
Chapter 14
Clocks and Power Control
14.1
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.3
14.3.1
14.3.1.1
14.3.1.2
14.3.1.3
14.3.1.4
14.3.1.5
14.3.2
14.3.3
14.4
14.4.1
14.4.2
14.4.3
14.5
14.5.1
14.5.2
14.6
14.6.1
14.6.2
Features .......................................................................................................................... 14-1
Clock Module ................................................................................................................ 14-3
External Reference Clocks......................................................................................... 14-3
Digital Phase Lock Loop and Interface ..................................................................... 14-4
DPLL Reset Configuration ........................................................................................ 14-6
Crystal Oscillator Support (EXTAL and XTAL)....................................................... 14-7
Clock Signals ................................................................................................................. 14-8
Clocks Derived from the DPLL Output..................................................................... 14-9
Internal General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2)........ 14-10
Memory Controller and External Bus Clocks
(GCLK1_50, GCLK2_50, CLKOUT)............................................................. 14-11
CLKOUT Special Considerations: 1:2:1 Mode................................................... 14-13
Baud Rate Generator Clock (BRGCLK) ............................................................. 14-13
Synchronization Clock (SYNCCLK, SYNCCLKS) ........................................... 14-13
PIT Clock (PITCLK) ............................................................................................... 14-14
Time Base and Decrementer Clock (TMBCLK) ..................................................... 14-15
Power Distribution....................................................................................................... 14-15
I/O Buffer Power (VDDH) ...................................................................................... 14-16
Internal Logic Power (VDDL)................................................................................. 14-16
Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1) ................................ 14-16
Power Control ............................................................................................................. 14-17
Normal High Mode.................................................................................................. 14-17
Normal Low Mode................................................................................................... 14-17
Clock and Power Control Registers............................................................................. 14-18
System Clock and Reset Control Register (SCCR) ................................................. 14-18
PLL and Reset Control Register (PLPRCR)............................................................ 14-21
Chapter 15
Memory Controller
15.1
15.2
15.3
15.3.1
15.3.2
15.3.3
15.3.4
15.3.5
Features .......................................................................................................................... 15-1
Basic Architecture.......................................................................................................... 15-4
Chip-Select Programming Common to the GPCM and UPM ....................................... 15-6
Address Space Programming..................................................................................... 15-7
Register Programming Order..................................................................................... 15-7
Memory Bank Write Protection................................................................................. 15-7
Address Type Protection............................................................................................ 15-7
8-, 16-, and 32-Bit Port Size Configuration............................................................... 15-7
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Contents
Paragraph
Number
15.3.6
15.3.7
15.3.8
15.4
15.4.1
15.4.2
15.4.3
15.4.4
15.4.5
15.4.6
15.4.7
15.4.8
15.5
15.5.1
15.5.1.1
15.5.1.2
15.5.1.3
15.5.1.4
15.5.1.5
15.5.1.6
15.5.2
15.5.3
15.5.4
15.6
15.6.1
15.6.1.1
15.6.1.2
15.6.1.3
15.6.1.4
15.6.2
15.6.3
15.6.4
15.6.4.1
15.6.4.2
15.6.4.3
15.6.4.4
15.6.4.5
15.6.4.6
15.6.4.7
15.6.4.8
15.6.4.9
Title
Page
Number
Memory Bank Protection Status ................................................................................ 15-8
UPM-Specific Registers ............................................................................................ 15-8
GPCM-Specific Registers.......................................................................................... 15-8
Register Descriptions ..................................................................................................... 15-8
Base Registers (BRx)................................................................................................. 15-8
Option Registers (ORx) ........................................................................................... 15-11
Memory Status Register (MSTAT) .......................................................................... 15-13
Machine A Mode Register/Machine B Mode Registers (MxMR) .......................... 15-14
Memory Command Register (MCR) ....................................................................... 15-15
Memory Data Register (MDR) ................................................................................ 15-17
Memory Address Register (MAR) .......................................................................... 15-17
Memory Periodic Timer Prescaler Register (MPTPR) ............................................ 15-18
General-Purpose Chip-Select Machine (GPCM)......................................................... 15-18
Timing Configuration .............................................................................................. 15-19
Chip-Select Assertion Timing ............................................................................. 15-20
Chip-Select and Write Enable Deassertion Timing ............................................. 15-21
Relaxed Timing.................................................................................................... 15-23
Output Enable (OE) Timing ................................................................................ 15-26
Programmable Wait State Configuration ............................................................. 15-26
Extended Hold Time on Read Accesses .............................................................. 15-26
Boot Chip-Select Operation..................................................................................... 15-29
External Asynchronous Master Support .................................................................. 15-30
Special Case: Bursting with External Transfer Acknowledge:................................ 15-31
User-Programmable Machines (UPMs)....................................................................... 15-32
Requests ................................................................................................................... 15-33
Internal/External Memory Access Requests........................................................ 15-33
UPM Periodic Timer Requests ............................................................................ 15-34
Software Requests—MCR run Command........................................................... 15-34
Exception Requests.............................................................................................. 15-34
Programming the UPM............................................................................................ 15-34
Control Signal Generation Timing........................................................................... 15-35
The RAM Array....................................................................................................... 15-37
RAM Words......................................................................................................... 15-38
Chip-Select Signals (CSTx)................................................................................. 15-41
Byte-Select Signals (BSTx)................................................................................. 15-42
General-Purpose Signals (GxTx, G0x)................................................................ 15-43
Loop Control (LOOP).......................................................................................... 15-45
Exception Pattern Entry (EXEN)......................................................................... 15-46
Address Multiplexing (AMX) ............................................................................. 15-46
Transfer Acknowledge and Data Sample Control (UTA, DLT3) ........................ 15-51
Disable Timer Mechanism (TODT)..................................................................... 15-52
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Contents
Paragraph
Number
15.6.4.10
15.6.4.11
15.6.4.11.1
15.6.4.11.2
15.7
15.7.1
15.7.2
15.8
15.8.1
15.8.2
15.8.3
15.8.4
15.8.4.1
15.8.4.2
15.8.4.3
15.8.5
15.8.5.1
15.8.5.2
15.9
15.9.1
15.9.2
Title
Page
Number
The Last Word (LAST)........................................................................................ 15-52
The Wait Mechanism (WAEN)............................................................................ 15-52
Internal and External Synchronous Masters .................................................... 15-52
External Asynchronous Masters...................................................................... 15-53
Handling Devices with Slow or Variable Access Times.............................................. 15-54
Hierarchical Bus Interface Example ........................................................................ 15-54
Slow Devices Example ............................................................................................ 15-55
External Master Support .............................................................................................. 15-55
Synchronous External Masters ................................................................................ 15-55
Asynchronous External Masters .............................................................................. 15-55
Special Case: Address Type Signals for External Masters ...................................... 15-56
UPM Features Supporting External Masters ........................................................... 15-56
Address Incrementing for External Synchronous Bursting Masters ................... 15-56
Handshake Mechanism for Asynchronous External Masters.............................. 15-56
Special Signal for External Address Multiplexer Control ................................... 15-56
External Master Examples ....................................................................................... 15-57
External Masters and the GPCM ......................................................................... 15-57
External Masters and the UPM............................................................................ 15-58
Memory System Interface Examples ........................................................................... 15-63
Page-Mode DRAM Interface Example.................................................................... 15-63
Page Mode Extended Data-Out Interface Example................................................. 15-74
Chapter 16
PCMCIA Interface
16.1
16.2
16.2.1
16.2.2
16.2.3
16.2.4
16.3
16.3.1
16.3.2
16.3.3
16.3.4
16.3.5
16.3.6
16.4
16.4.1
16.4.2
System Configuration .................................................................................................... 16-1
PCMCIA Module Signal Definitions ............................................................................ 16-1
PCMCIA Cycle Control Signals................................................................................ 16-3
PCMCIA Input Port Signals ...................................................................................... 16-4
PCMCIA Output Port Signals (OP[0:4]) ................................................................... 16-5
Other PCMCIA Signals ............................................................................................. 16-5
Operation Description.................................................................................................... 16-6
Memory-Only Cards .................................................................................................. 16-6
I/O Cards.................................................................................................................... 16-6
Interrupts.................................................................................................................... 16-7
Power Control ............................................................................................................ 16-7
Reset and Three-State Control ................................................................................... 16-7
DMA .......................................................................................................................... 16-7
Programming Model ...................................................................................................... 16-8
PCMCIA Interface Input Pins Register (PIPR) ......................................................... 16-8
PCMCIA Interface Status Changed Register (PSCR) ............................................. 16-10
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Paragraph
Number
16.4.3
16.4.4
16.4.5
16.4.6
16.5
Page
Number
Title
PCMCIA Interface Enable Register (PER) ............................................................. 16-11
PCMCIA Interface General Control Register (PGCRx).......................................... 16-13
PCMCIA Base Registers 0–7 (PBR0–PBR7).......................................................... 16-14
PCMCIA Option Register 0–7 (POR0–POR7) ....................................................... 16-14
PCMCIA Controller Timing Examples ....................................................................... 16-17
Part V
Communications Processor Module
Chapter 17
Communications Processor Module and CPM Timers
17.1
17.2
17.2.1
17.2.2
17.2.2.1
17.2.2.2
17.2.2.3
17.2.2.4
17.2.2.5
17.2.2.6
17.2.3
17.2.3.1
17.2.4
17.2.4.1
17.2.4.2
17.2.4.3
17.2.4.4
17.2.5
Features .......................................................................................................................... 17-2
CPM General-Purpose Timers ....................................................................................... 17-4
Features...................................................................................................................... 17-5
CPM Timer Operation ............................................................................................... 17-5
Timer Clock Source ............................................................................................... 17-6
Timer Reference Count.......................................................................................... 17-6
Timer Capture ........................................................................................................ 17-6
Timer Gating.......................................................................................................... 17-6
Cascaded Mode...................................................................................................... 17-7
Timer 1 and SPKROUT......................................................................................... 17-7
CPM Timer Register Set............................................................................................ 17-7
Timer Global Configuration Register (TGCR)...................................................... 17-8
Timer Mode Registers (TMR1–TMR4)..................................................................... 17-9
Timer Reference Registers (TRR1–TRR4) ......................................................... 17-10
Timer Capture Registers (TCR1–TCR4) ............................................................. 17-10
Timer Counter Registers (TCN1–TCN4) ............................................................ 17-10
Timer Event Registers (TER1–TER4)................................................................. 17-11
Timer Initialization Examples.................................................................................. 17-11
Chapter 18
Communications Processor
18.1
18.2
18.3
18.4
18.5
18.6
18.6.1
Features .......................................................................................................................... 18-1
Communicating with the Core ....................................................................................... 18-2
Communicating with the Peripherals............................................................................. 18-2
CP Microcode Revision Number ................................................................................... 18-4
CPM Configuration Register (CPMCFG) ..................................................................... 18-4
CP Register Set and CP Commands .............................................................................. 18-5
RISC Controller Configuration Register (RCCR) ..................................................... 18-5
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Paragraph
Number
18.6.2
18.6.3
18.6.4
18.6.4.1
18.6.4.2
18.7
18.7.1
18.7.2
18.7.3
18.8
18.8.1
18.8.2
18.8.3
18.8.3.1
18.8.3.2
18.8.4
18.8.5
18.8.6
18.8.7
18.8.8
Title
Page
Number
RISC Microcode Development Support Control Register (RMDS) ......................... 18-6
CP Command Register (CPCR)................................................................................. 18-7
CP Commands ........................................................................................................... 18-8
CP Command Examples ...................................................................................... 18-10
CP Command Execution Latency........................................................................ 18-10
Dual-Port RAM............................................................................................................ 18-10
System RAM and Microcode Packages................................................................... 18-12
The Buffer Descriptor (BD)..................................................................................... 18-13
Parameter RAM ....................................................................................................... 18-13
The RISC Timer Table................................................................................................. 18-14
RISC Timer Table Scan Algorithm.......................................................................... 18-15
The set timer Command........................................................................................... 18-15
RISC Timer Table Parameter RAM and Timer Table Entries ................................. 18-15
RISC Timer Command Register (TM_CMD) ..................................................... 18-16
RISC Timer Table Entries.................................................................................... 18-17
RISC Timer Event Register (RTER)/Mask Register (RTMR) ................................ 18-17
PWM Mode.............................................................................................................. 18-18
RISC Timer Initialization ........................................................................................ 18-18
RISC Timer Interrupt Handling ............................................................................... 18-19
Using the RISC Timers to Track CP Loading ......................................................... 18-19
Chapter 19
SDMA Channels and IDMA Emulation
19.1
19.1.1
19.1.2
19.2
19.2.1
19.2.2
19.2.3
19.2.4
19.3
19.3.1
19.3.2
19.3.3
19.3.3.1
19.3.3.2
19.3.3.3
19.3.4
19.3.4.1
SDMA Channels ............................................................................................................ 19-1
SDMA Transfers........................................................................................................ 19-2
U-Bus Arbitration and the SDMA Channels ............................................................. 19-3
SDMA Registers ............................................................................................................ 19-4
SDMA Configuration Register (SDCR) .................................................................... 19-4
SDMA Status Register (SDSR) ................................................................................. 19-5
SDMA Mask Register (SDMR)................................................................................. 19-5
SDMA Address Register (SDAR) ............................................................................. 19-6
IDMA Emulation ........................................................................................................... 19-6
IDMA Features .......................................................................................................... 19-6
IDMA Parameter RAM ............................................................................................. 19-7
IDMA Registers......................................................................................................... 19-7
DMA Channel Mode Registers (DCMR) .............................................................. 19-8
IDMA Status Registers (IDSR1 and IDSR2) ........................................................ 19-9
IDMA Mask Registers (IDMR1 and IDMR2)....................................................... 19-9
IDMA Buffer Descriptors (BD)................................................................................. 19-9
Function Code Registers—SFCR and DFCR...................................................... 19-12
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Paragraph
Number
19.3.4.2
19.3.5
19.3.6
19.3.6.1
19.3.6.2
19.3.7
19.3.7.1
19.3.7.2
19.3.7.2.1
19.3.7.2.2
19.3.8
19.3.8.1
19.3.8.2
19.3.9
19.3.10
Title
Page
Number
Auto-Buffering and Buffer-Chaining .................................................................. 19-12
IDMA CP Commands.............................................................................................. 19-13
IDMA Channel Operation ....................................................................................... 19-13
Activating an IDMA Channel.............................................................................. 19-13
Suspending an IDMA Channel............................................................................ 19-13
IDMA Interface Signals—DREQ and SDACK....................................................... 19-14
IDMA Requests for Memory/Memory Transfers ................................................ 19-14
IDMA Requests for Peripheral/Memory Transfers ............................................. 19-14
Level-Sensitive Requests................................................................................. 19-15
Edge-Sensitive Requests.................................................................................. 19-15
IDMA Transfers—Dual-Address and Single-Address ............................................ 19-15
Dual-Address (Dual-Cycle) Transfer................................................................... 19-15
Single-Address (Single-Cycle) Transfer (Fly-By)............................................... 19-16
External Recognition of an IDMA Transfer ............................................................ 19-18
Interrupts During an IDMA Bus Transfer ............................................................... 19-18
Chapter 20
Serial Interface
20.1
20.2
20.2.1
20.2.2
20.2.3
20.2.3.1
20.2.3.2
20.2.3.3
20.2.3.4
20.2.3.5
20.2.3.6
20.2.3.7
20.2.3.8
20.2.4
20.2.4.1
20.2.4.2
20.2.4.3
20.2.4.4
20.2.4.5
20.2.4.6
20.2.5
20.2.5.1
SI Features ..................................................................................................................... 20-2
TSA Implementation...................................................................................................... 20-4
TSA Signals ............................................................................................................... 20-7
Enabling Connections to the TSA ............................................................................. 20-8
SI RAM...................................................................................................................... 20-8
Disabling and Reenabling the TSA ....................................................................... 20-9
One TDM Channel with Static Frames.................................................................. 20-9
Two TDM Channels with Static Frames................................................................ 20-9
SI RAM Dynamic Changes ................................................................................. 20-10
One TDM Channel with Dynamic Frames.......................................................... 20-12
Two TDM Channels with Dynamic Frames ........................................................ 20-12
Programming the SI RAM................................................................................... 20-13
SI RAM Programming Example ......................................................................... 20-15
The SI Registers....................................................................................................... 20-15
SI Global Mode Register (SIGMR) ..................................................................... 20-15
SI Mode Register (SIMODE) .............................................................................. 20-17
SI Clock Route Register (SICR).......................................................................... 20-22
SI Command Register (SICMR).......................................................................... 20-24
SI Status Register (SISTR) .................................................................................. 20-24
SI RAM Pointer Register (SIRP)......................................................................... 20-25
IDL Bus Implementation ......................................................................................... 20-27
ISDN Terminal Adaptor Application................................................................... 20-27
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Paragraph
Number
20.2.5.2
20.2.6
20.2.6.1
20.2.6.2
20.2.6.2.1
20.2.6.2.2
20.2.6.3
20.3
20.4
20.4.1
20.4.2
20.4.3
Title
Page
Number
Programming the IDL Interface........................................................................... 20-30
GCI Bus Implementation ......................................................................................... 20-31
GCI Activation/Deactivation ............................................................................... 20-32
Programming the GCI Interface .......................................................................... 20-32
Normal Mode................................................................................................... 20-32
SCIT Mode ...................................................................................................... 20-33
GCI Interface (SCIT Mode) Programming Example .......................................... 20-33
NMSI Configuration .................................................................................................... 20-34
Baud Rate Generators (BRGs)..................................................................................... 20-36
Baud Rate Generator Configuration Registers (BRGCn)........................................ 20-37
Autobaud Operation on the SCC UART.................................................................. 20-39
UART Baud Rate Examples .................................................................................... 20-40
Chapter 21
Serial Communications Controllers
21.1
21.2
21.2.1
21.2.2
21.2.3
21.2.4
21.3
21.4
21.4.1
21.4.2
21.4.3
21.4.4
21.4.4.1
21.4.4.2
21.4.5
21.4.5.1
21.4.6
21.4.7
21.4.7.1
21.4.7.2
21.4.7.3
21.4.7.4
21.4.7.5
21.4.8
Features .......................................................................................................................... 21-2
SCC Registers ............................................................................................................... 21-3
General SCC Mode Register (GSMR)....................................................................... 21-3
Protocol-Specific Mode Register (PSMR) .............................................................. 21-10
Data Synchronization Register (DSR)..................................................................... 21-10
Transmit-on-Demand Register (TODR) .................................................................. 21-10
SCC Buffer Descriptors (BDs) .................................................................................... 21-11
SCC Parameter RAM................................................................................................... 21-13
Function Code Registers (RFCR and TFCR) .......................................................... 21-15
Handling SCC Interrupts ......................................................................................... 21-15
SCC Initialization .................................................................................................... 21-16
Controlling SCC Timing with RTS, CTS, and CD.................................................. 21-17
Synchronous Protocols ........................................................................................ 21-17
Asynchronous Protocols ...................................................................................... 21-20
Digital Phase-Locked Loop (DPLL) Operation....................................................... 21-21
Encoding Data with a DPLL................................................................................ 21-23
Clock Glitch Detection ............................................................................................ 21-25
Reconfiguring the SCCs .......................................................................................... 21-25
General Reconfiguration Sequence for an SCC Transmitter............................... 21-25
Reset Sequence for an SCC Transmitter.............................................................. 21-26
General Reconfiguration Sequence for an SCC Receiver ................................... 21-26
Reset Sequence for an SCC Receiver.................................................................. 21-26
Switching Protocols ............................................................................................. 21-26
Saving Power ........................................................................................................... 21-26
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Paragraph
Number
Title
Page
Number
Chapter 22
SCC UART Mode
22.1
22.2
22.3
22.4
22.5
22.6
22.7
22.8
22.9
22.10
22.11
22.12
22.13
22.14
22.15
22.16
22.17
22.18
22.19
22.20
22.21
22.22
Features .......................................................................................................................... 22-2
Normal Asynchronous Mode......................................................................................... 22-2
Synchronous Mode ........................................................................................................ 22-3
SCC UART Parameter RAM ......................................................................................... 22-3
Data-Handling Methods: Character- or Message-Based ............................................... 22-5
Error and Status Reporting............................................................................................. 22-6
SCC UART Commands ................................................................................................. 22-6
Multidrop Systems and Address Recognition ............................................................... 22-7
Receiving Control Characters ........................................................................................ 22-7
Hunt Mode (Receiver) ................................................................................................... 22-9
Inserting Control Characters into the Transmit Data Stream......................................... 22-9
Sending a Break (Transmitter)..................................................................................... 22-10
Sending a Preamble (Transmitter) ............................................................................... 22-10
Fractional Stop Bits (Transmitter) ............................................................................... 22-11
Handling Errors in the SCC UART Controller ............................................................ 22-12
UART Mode Register (PSMR).................................................................................... 22-13
SCC UART Receive Buffer Descriptor (RxBD) ......................................................... 22-15
SCC UART Transmit Buffer Descriptor (TxBD) ........................................................ 22-18
SCC UART Event Register (SCCE) and Mask Register (SCCM) .............................. 22-19
SCC UART Status Register (SCCS)............................................................................ 22-22
SCC UART Programming Example ............................................................................ 22-22
S-Records Loader Application..................................................................................... 22-23
Chapter 23
SCC HDLC Mode
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
23.9
23.10
23.11
23.12
SCC HDLC Features ..................................................................................................... 23-1
SCC HDLC Channel Frame Transmission .................................................................... 23-2
SCC HDLC Channel Frame Reception ......................................................................... 23-2
SCC HDLC Parameter RAM......................................................................................... 23-3
Programming the SCC HDLC Controller...................................................................... 23-5
SCC HDLC Commands................................................................................................. 23-5
Handling Errors in the SCC HDLC Controller.............................................................. 23-6
HDLC Mode Register (PSMR)...................................................................................... 23-7
SCC HDLC Receive Buffer Descriptor (RxBD) ........................................................... 23-8
SCC HDLC Transmit Buffer Descriptor (TxBD)........................................................ 23-11
HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ................................. 23-12
SCC HDLC Status Register (SCCS)............................................................................ 23-14
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Paragraph
Number
23.13
23.13.1
23.13.2
23.14
23.14.1
23.14.2
23.14.3
23.14.4
23.14.5
23.14.6
23.14.6.1
23.14.6.2
Title
Page
Number
SCC HDLC Programming Examples .......................................................................... 23-14
SCC HDLC Programming Example #1................................................................... 23-14
SCC HDLC Programming Example #2................................................................... 23-16
HDLC Bus Mode with Collision Detection................................................................. 23-16
HDLC Bus Features................................................................................................. 23-18
Accessing the HDLC Bus ........................................................................................ 23-18
Increasing Performance ........................................................................................... 23-19
Delayed RTS Mode.................................................................................................. 23-20
Using the Time-Slot Assigner (TSA) ...................................................................... 23-21
HDLC Bus Protocol Programming.......................................................................... 23-21
Programming GSMR and PSMR for the HDLC Bus Protocol ........................... 23-21
HDLC Bus Controller Programming Example.................................................... 23-22
Chapter 24
SCC AppleTalk Mode
24.1
24.2
24.3
24.4
24.4.1
24.4.2
24.4.3
24.4.4
Operating the LocalTalk Bus ......................................................................................... 24-1
Features .......................................................................................................................... 24-2
Connecting to AppleTalk ............................................................................................... 24-2
Programming the SCC in AppleTalk Mode................................................................... 24-3
Programming the GSMR ........................................................................................... 24-3
Programming the PSMR............................................................................................ 24-4
Programming the TODR............................................................................................ 24-4
SCC AppleTalk Programming Example.................................................................... 24-4
Chapter 25
SCC Asynchronous HDLC Mode and IrDA
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
25.9
25.9.1
25.9.2
25.10
25.11
Asynchronous HDLC Features ...................................................................................... 25-1
Asynchronous HDLC Frame Transmission Processing................................................. 25-1
Asynchronous HDLC Frame Reception Processing...................................................... 25-2
Transmitter Transparency Encoding .............................................................................. 25-2
Receiver Transparency Decoding .................................................................................. 25-3
Exceptions to RFC 1549 ................................................................................................ 25-4
Asynchronous HDLC Channel Implementation............................................................ 25-4
Asynchronous HDLC Mode Parameter RAM............................................................... 25-5
Configuring GSMR and DSR for Asynchronous HDLC .............................................. 25-6
General SCC Mode Register (GSMR)....................................................................... 25-6
Data Synchronization Register (DSR)....................................................................... 25-6
Programming the Asynchronous HDLC Controller ...................................................... 25-6
Asynchronous HDLC Commands ................................................................................. 25-6
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Paragraph
Number
25.12
25.13
25.13.1
25.13.2
25.13.3
25.14
25.15
25.16
25.17
25.18
Title
Page
Number
Handling Errors in the Asynchronous HDLC Controller .............................................. 25-7
SCC Asynchronous HDLC Registers ............................................................................ 25-8
Asynchronous HDLC Event Register (SCCE)/Asynchronous HDLC Mask
Register (SCCM) ................................................................................................... 25-8
SCC Asynchronous HDLC Status Register (SCCS) ................................................. 25-9
Asynchronous HDLC Mode Register (PSMR) ....................................................... 25-10
SCC Asynchronous HDLC RxBDs ............................................................................. 25-10
SCC Asynchronous HDLC TxBDs ............................................................................. 25-12
Differences between HDLC and Asynchronous HDLC.............................................. 25-13
SCC Asynchronous HDLC Programming Example.................................................... 25-13
IrDA Encoder/Decoder (SCC2 Only).......................................................................... 25-14
Chapter 26
SCC BISYNC Mode
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
26.9
26.10
26.11
26.12
26.13
26.14
26.15
26.16
26.17
Features .......................................................................................................................... 26-2
SCC BISYNC Channel Frame Transmission ................................................................ 26-2
SCC BISYNC Channel Frame Reception ..................................................................... 26-3
SCC BISYNC Parameter RAM ..................................................................................... 26-3
SCC BISYNC Commands ............................................................................................. 26-5
SCC BISYNC Control Character Recognition.............................................................. 26-6
BISYNC SYNC Register (BSYNC).............................................................................. 26-7
SCC BISYNC DLE Register (BDLE) ........................................................................... 26-8
Sending and Receiving the Synchronization Sequence ................................................. 26-8
Handling Errors in the SCC BISYNC ........................................................................... 26-9
BISYNC Mode Register (PSMR)................................................................................ 26-10
SCC BISYNC Receive BD (RxBD) ............................................................................ 26-11
SCC BISYNC Transmit BD (TxBD)........................................................................... 26-13
BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM).......................... 26-14
SCC Status Registers (SCCS)...................................................................................... 26-15
Programming the SCC BISYNC Controller ................................................................ 26-16
SCC BISYNC Programming Example ........................................................................ 26-17
Chapter 27
SCC Ethernet Mode
27.1
27.2
27.3
27.4
27.5
Ethernet on the MPC885................................................................................................ 27-2
Features .......................................................................................................................... 27-3
Learning Ethernet on the MPC885 ................................................................................ 27-4
Connecting the MPC885 to Ethernet ............................................................................. 27-5
SCC Ethernet Channel Frame Transmission ................................................................. 27-6
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Paragraph
Number
27.6
27.7
27.8
27.9
27.10
27.11
27.12
27.13
27.14
27.15
27.16
27.17
27.18
27.19
27.20
27.21
Title
Page
Number
SCC Ethernet Channel Frame Reception....................................................................... 27-7
SCC Ethernet Parameter RAM ...................................................................................... 27-8
Programming the Ethernet Controller.......................................................................... 27-10
SCC Ethernet Commands ............................................................................................ 27-10
SCC Ethernet Address Recognition............................................................................. 27-11
Hash Table Algorithm.................................................................................................. 27-12
Interpacket Gap Time................................................................................................... 27-13
Handling Collisions ..................................................................................................... 27-13
Internal and External Loopback................................................................................... 27-13
Full-Duplex Ethernet Support...................................................................................... 27-14
Handling Errors in the Ethernet Controller.................................................................. 27-14
Ethernet Mode Register (PSMR) ................................................................................. 27-15
SCC Ethernet Receive Buffer Descriptor .................................................................... 27-16
SCC Ethernet Transmit Buffer Descriptor................................................................... 27-19
SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) .................................. 27-20
SCC Ethernet Programming Example ......................................................................... 27-22
Chapter 28
SCC Transparent Mode
28.1
28.2
28.3
28.3.1
28.3.1.1
28.3.1.2
28.3.1.2.1
28.3.1.3
28.3.1.4
28.3.2
28.3.2.1
28.3.2.2
28.4
28.5
28.6
28.7
28.8
28.9
28.10
28.11
Features .......................................................................................................................... 28-1
SCC Transparent Channel Frame Reception Process .................................................... 28-2
Achieving Synchronization in Transparent Mode ......................................................... 28-2
Synchronization in NMSI Mode................................................................................ 28-3
In-Line Synchronization Pattern............................................................................ 28-3
External Synchronization Signals.......................................................................... 28-3
External Synchronization Example ................................................................... 28-4
Transparent Mode without Explicit Synchronization............................................ 28-4
End of Frame Detection......................................................................................... 28-5
Synchronization and the TSA .................................................................................... 28-5
In-line Synchronization Pattern ............................................................................. 28-5
Inherent Synchronization....................................................................................... 28-5
CRC Calculation in Transparent Mode.......................................................................... 28-5
SCC Transparent Parameter RAM................................................................................. 28-6
SCC Transparent Commands......................................................................................... 28-6
Handling Errors in the Transparent Controller .............................................................. 28-7
Transparent Mode and the PSMR.................................................................................. 28-7
SCC Transparent Receive Buffer Descriptor (RxBD) ................................................... 28-8
SCC Transparent Transmit Buffer Descriptor (TxBD).................................................. 28-9
SCC Transparent Event Register (SCCE)/Mask Register (SCCM)............................. 28-10
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Number
28.12
28.13
Title
Page
Number
SCC Status Register in Transparent Mode (SCCS) ..................................................... 28-11
SCC2 Transparent Programming Example.................................................................. 28-12
Chapter 29
Serial Management Controllers (SMCs)
29.1
29.2
29.2.1
29.2.2
29.2.3
29.2.3.1
29.2.4
29.2.4.1
29.2.4.2
29.2.4.3
29.2.4.4
29.2.4.5
29.2.5
29.2.6
29.3
29.3.1
29.3.2
29.3.3
29.3.4
29.3.5
29.3.6
29.3.7
29.3.8
29.3.9
29.3.10
29.3.11
29.3.12
29.3.13
29.4
29.4.1
29.4.2
29.4.3
29.4.4
29.4.5
29.4.6
SMC Features ................................................................................................................ 29-2
Common SMC Settings and Configurations ................................................................. 29-2
SMC Mode Registers (SMCMRn) ............................................................................ 29-2
SMC Buffer Descriptors (BDs) ................................................................................. 29-4
SMC Parameter RAM................................................................................................ 29-5
SMC Function Code Registers (RFCR/TFCR) ..................................................... 29-7
Disabling SMCs On the Fly....................................................................................... 29-8
SMC Transmitter Full Sequence............................................................................ 29-8
SMC Transmitter Shortcut Sequence .................................................................... 29-8
SMC Receiver Full Sequence................................................................................ 29-8
SMC Receiver Shortcut Sequence......................................................................... 29-9
Changing SMC Protocols ...................................................................................... 29-9
Saving Power ............................................................................................................. 29-9
Handling Interrupts in the SMC................................................................................. 29-9
SMC in UART Mode ..................................................................................................... 29-9
SMC UART Features............................................................................................... 29-10
SMC UART-Specific Parameter RAM.................................................................... 29-10
SMC UART Channel Transmission Process ........................................................... 29-11
SMC UART Channel Reception Process................................................................. 29-11
Data Handling Modes: Character- and Message-Oriented ...................................... 29-12
SMC UART Commands .......................................................................................... 29-12
Sending a Break ....................................................................................................... 29-13
Sending a Preamble ................................................................................................. 29-13
Handling Errors in the SMC UART Controller ....................................................... 29-13
SMC UART Receive BD (RxBD) ........................................................................... 29-14
SMC UART Transmit BD (TxBD).......................................................................... 29-17
SMC UART Event Register (SMCE)/Mask Register (SMCM) .............................. 29-18
SMC UART Controller Programming Example...................................................... 29-19
SMC in Transparent Mode........................................................................................... 29-20
SMC Transparent Mode Features ............................................................................ 29-20
SMC Transparent-Specific Parameter RAM ........................................................... 29-21
SMC Transparent Channel Transmission Process ................................................... 29-21
SMC Transparent Channel Reception Process ........................................................ 29-21
Using SMSYN for Synchronization ........................................................................ 29-22
Using TSA for Synchronization .............................................................................. 29-23
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Paragraph
Number
29.4.7
29.4.8
29.4.9
29.4.10
29.4.11
29.4.12
29.4.13
29.5
29.5.1
29.5.2
29.5.2.1
29.5.2.1.1
29.5.3
29.5.3.1
29.5.3.2
29.5.4
29.5.5
29.5.6
29.5.7
29.5.8
29.5.9
Title
Page
Number
SMC Transparent Commands.................................................................................. 29-25
Handling Errors in the SMC Transparent Controller............................................... 29-26
SMC Transparent Receive BD (RxBD)................................................................... 29-26
SMC Transparent Transmit BD (TxBD) ................................................................. 29-27
SMC Transparent Event Register (SMCE)/Mask Register (SMCM)...................... 29-29
SMC Transparent NMSI Programming Example.................................................... 29-29
SMC Transparent TSA Programming Example ...................................................... 29-30
SMC in GCI Mode....................................................................................................... 29-31
SMC GCI Parameter RAM...................................................................................... 29-31
Handling the GCI Monitor Channel ........................................................................ 29-32
SMC GCI Monitor Channel Transmission Process ............................................. 29-32
SMC GCI Monitor Channel Reception Process .............................................. 29-32
Handling the GCI C/I Channel ................................................................................ 29-32
SMC GCI C/I Channel Transmission Process ..................................................... 29-32
SMC GCI C/I Channel Reception Process .......................................................... 29-33
SMC GCI Commands.............................................................................................. 29-33
SMC GCI Monitor Channel RxBD ......................................................................... 29-33
SMC GCI Monitor Channel TxBD.......................................................................... 29-34
SMC GCI C/I Channel RxBD ................................................................................. 29-34
SMC GCI C/I Channel TxBD.................................................................................. 29-35
SMC GCI Event Register (SMCE)/Mask Register (SMCM).................................. 29-35
Chapter 30
Serial Peripheral Interface (SPI)
30.1
30.2
30.3
30.3.1
30.3.2
30.3.3
30.4
30.4.1
30.4.1.1
30.4.1.2
30.4.2
30.4.3
30.5
30.5.1
30.6
30.7
Features .......................................................................................................................... 30-1
SPI Clocking and Signal Functions ............................................................................... 30-2
Configuring the SPI Controller...................................................................................... 30-3
The SPI as a Master Device....................................................................................... 30-3
The SPI as a Slave Device ......................................................................................... 30-4
The SPI in Multi-master Operation ........................................................................... 30-4
SPI Registers.................................................................................................................. 30-6
SPI Mode Register (SPMODE) ................................................................................. 30-6
SPI Transfers with Different Clocking Modes ...................................................... 30-7
SPI Examples with Different SPMODE[LEN] Values.......................................... 30-8
SPI Event/Mask Registers (SPIE/SPIM) ................................................................... 30-8
SPI Command Register (SPCOM) ............................................................................ 30-9
SPI Parameter RAM .................................................................................................... 30-10
Receive/Transmit Function Code Registers (RFCR/TFCR).................................... 30-11
SPI Commands ............................................................................................................ 30-12
The SPI Buffer Descriptor (BD) Table ........................................................................ 30-12
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Number
30.7.1
30.7.1.1
30.7.1.2
30.8
30.9
30.10
Title
Page
Number
SPI Buffer Descriptors (BDs) .................................................................................. 30-12
SPI Receive BD (RxBD) ..................................................................................... 30-13
SPI Transmit BD (TxBD) .................................................................................... 30-14
SPI Master Programming Example ............................................................................. 30-15
SPI Slave Programming Example................................................................................ 30-16
Handling Interrupts in the SPI ..................................................................................... 30-17
Chapter 31
Universal Serial Bus (USB)
31.1
31.2
31.3
31.4
31.5
31.6
31.6.1
31.7
31.7.1
31.7.2
31.8
31.9
31.10
31.10.1
31.10.1.1
31.10.1.2
31.10.2
31.11
31.11.1
31.11.2
31.11.3
31.11.4
31.11.5
31.11.6
31.11.7
31.12
31.12.1
31.12.2
31.12.3
31.13
31.13.1
USB Integration in the MPC885.................................................................................... 31-1
Overview........................................................................................................................ 31-1
USB Controller Key Features ........................................................................................ 31-1
Host Controller Limitations ........................................................................................... 31-2
USB Controller Pin Functions and Clocking................................................................. 31-2
USB Functional Description.......................................................................................... 31-4
USB Function Controller Transmit/Receive.............................................................. 31-5
USB Host Description ................................................................................................... 31-7
USB Host Controller Transmit/Receive .................................................................... 31-8
SOF transmission for USB Host controller ............................................................. 31-11
USB Function and Host Parameter RAM Memory Map............................................. 31-11
Endpoint Parameter Block Pointer (EPxPTR) ............................................................. 31-12
Endpoint Parameter Block ........................................................................................... 31-13
Frame Number (FRAME_N)................................................................................... 31-14
Frame Number in Function Mode ....................................................................... 31-14
Frame Number In Host Mode.............................................................................. 31-14
USB Function Code Registers (RFCR and TFCR) ................................................. 31-15
USB Function Programming Model ........................................................................... 31-16
USB Mode Register (USMOD)............................................................................... 31-16
USB Slave Address Register (USADR) .................................................................. 31-17
USB Endpoint Registers (USEP0–USEP3)............................................................. 31-18
USB Command Register (USCOM)........................................................................ 31-19
USB Event Register (USBER) ................................................................................ 31-20
USB Mask Register (USBMR)................................................................................ 31-20
USB Status Register (USBS) ................................................................................... 31-21
USB Buffer Descriptor Ring........................................................................................ 31-21
USB Receive Buffer Descriptor (RxBD) for Host and Function ............................ 31-23
USB Transmit Buffer Descriptor (TxBD) for Function........................................... 31-25
USB Transmit Buffer Descriptor (TxBD) for Host ................................................. 31-26
USB CP Commands..................................................................................................... 31-28
STOP Tx Command (USBCMD=001).................................................................... 31-28
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Number
31.13.2
31.14
31.15
31.16
31.16.1
Title
Page
Number
RESTART Tx Command (USBCMD=010) ............................................................ 31-28
USB Controller Errors ................................................................................................. 31-29
USB Function Controller Initialization Example ........................................................ 31-30
Programming the USB Host Controller....................................................................... 31-31
USB Host Controller Initialization Example ........................................................... 31-32
Chapter 32
I Controller
2C
32.1
32.2
32.3
32.3.1
32.3.2
32.3.3
32.3.4
32.4
32.4.1
32.4.2
32.4.3
32.4.4
32.4.5
32.5
32.6
32.7
32.7.1
32.7.1.1
32.7.1.2
I2C Features ................................................................................................................... 32-2
I2C Controller Clocking and Signal Functions.............................................................. 32-2
I2C Controller Transfers ................................................................................................ 32-2
I2C Master Write (Slave Read).................................................................................. 32-3
I2C Loopback Testing ................................................................................................ 32-4
I2C Master Read (Slave Write).................................................................................. 32-4
I2C Multi-Master Considerations .............................................................................. 32-5
2
I C Registers .................................................................................................................. 32-5
I2C Mode Register (I2MOD)..................................................................................... 32-6
I2C Address Register (I2ADD).................................................................................. 32-7
I2C Baud Rate Generator Register (I2BRG) ............................................................. 32-7
I2C Event/Mask Registers (I2CER/I2CMR) ............................................................. 32-7
I2C Command Register (I2COM).............................................................................. 32-8
2C Parameter RAM....................................................................................................... 32-9
I
I2C Commands............................................................................................................. 32-11
I2C Buffer Descriptor (BD) Tables .............................................................................. 32-11
I2C Buffer Descriptors (BDs) .................................................................................. 32-12
I2C Receive Buffer Descriptor (RxBD)............................................................... 32-12
I2C Transmit Buffer Descriptor (TxBD) ............................................................. 32-13
Chapter 33
Parallel Interface Port (PIP)
33.1
33.2
33.2.1
33.2.2
33.3
33.3.1
33.3.1.1
33.3.1.2
33.3.2
Features .......................................................................................................................... 33-1
Core Control vs. CP Control.......................................................................................... 33-2
Core Control .............................................................................................................. 33-2
CP Control ................................................................................................................. 33-2
The PIP Parameter RAM ............................................................................................... 33-3
PIP Transmitter Parameter RAM............................................................................... 33-3
PIP Function Code Register (PFCR) ..................................................................... 33-4
Status Mask Register (SMASK) ............................................................................ 33-4
PIP Receiver Parameter RAM ................................................................................... 33-5
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Paragraph
Number
33.3.2.1
33.4
33.4.1
33.4.2
33.4.3
33.4.4
33.4.5
33.5
33.5.1
33.5.2
33.6
33.7
33.7.1
33.7.2
33.7.2.1
33.7.2.2
33.8
33.9
33.9.1
33.9.1.1
33.9.2
33.9.2.1
Title
Page
Number
Control Character Table, RCCM, and RCCR........................................................ 33-6
The PIP Registers........................................................................................................... 33-8
PIP Configuration Register (PIPC)............................................................................ 33-8
PIP Event Register (PIPE) ......................................................................................... 33-9
PIP Mask Register ................................................................................................... 33-10
PIP Timing Parameters Register (PTPR) ................................................................. 33-10
The Port B Registers ................................................................................................ 33-11
PIP Buffer Descriptors ................................................................................................. 33-12
The PIP Tx Buffer Descriptor (TxBD) .................................................................... 33-12
The PIP Rx Buffer Descriptor (RxBD).................................................................... 33-13
PIP CP Commands....................................................................................................... 33-14
Handshaking I/O Modes .............................................................................................. 33-15
Interlocked Handshake Mode .................................................................................. 33-15
Pulsed Handshake Mode.......................................................................................... 33-16
The BUSY Signal ................................................................................................ 33-17
Pulsed Handshake Timing ................................................................................... 33-17
Transparent Transfers................................................................................................... 33-19
Implementing Centronics............................................................................................. 33-19
PIP as a Centronics Transmitter............................................................................... 33-20
Centronics Tx Errors and the PIPE...................................................................... 33-21
PIP as a Centronics Receiver ................................................................................... 33-21
Centronics Rx Errors and the PIPE ..................................................................... 33-22
Chapter 34
Parallel I/O Ports
34.1
34.2
34.2.1
34.2.1.1
34.2.1.2
34.2.1.3
34.2.1.4
34.2.2
34.2.3
34.3
34.3.1
34.3.1.1
34.3.1.2
34.3.1.3
34.3.1.4
Features .......................................................................................................................... 34-2
Port A............................................................................................................................. 34-2
Port A Registers ......................................................................................................... 34-3
Port A Open-Drain Register (PAODR) ................................................................. 34-3
Port A Data Register (PADAT).............................................................................. 34-4
Port A Data Direction Register (PADIR) .............................................................. 34-4
Port A Pin Assignment Register (PAPAR) ............................................................ 34-5
Port A Configuration Examples................................................................................. 34-5
Port A Functional Block Diagrams............................................................................ 34-6
Port B ............................................................................................................................. 34-7
The Port B Registers .................................................................................................. 34-9
Port B Open-Drain Register (PBODR).................................................................. 34-9
Port B Data Register (PBDAT).............................................................................. 34-9
Port B Data Direction Register (PBDIR)............................................................. 34-10
Port B Pin Assignment Register (PBPAR) .......................................................... 34-11
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Paragraph
Number
34.4
34.4.1
34.4.1.1
34.4.1.2
34.4.1.3
34.4.1.4
34.4.1.5
34.5
34.5.1
34.5.1.1
34.5.1.2
34.5.1.3
34.6
34.6.1
34.6.1.1
34.6.1.2
34.6.1.3
34.6.1.4
34.6.2
Title
Page
Number
Port C ........................................................................................................................... 34-11
Port C Registers ....................................................................................................... 34-14
Port C Data Register (PCDAT)............................................................................ 34-14
Port C Data Direction Register (PCDIR)............................................................. 34-14
Port C Pin Assignment Register (PCPAR) .......................................................... 34-15
Port C Special Options Register (PCSO)............................................................. 34-16
Port C Interrupt Control Register (PCINT) ......................................................... 34-17
Port D........................................................................................................................... 34-17
Port D Registers ....................................................................................................... 34-18
Port D Data Register............................................................................................ 34-18
Port D Data Direction Register (PDDIR) ............................................................ 34-19
Port D Pin Assignment Register (PDPAR).......................................................... 34-20
Port E ........................................................................................................................... 34-20
The Port E Registers ................................................................................................ 34-22
Port E Open-Drain Register (PEODR) ................................................................ 34-22
Port E Data Register (PEDAT) ............................................................................ 34-22
Port E Data Direction Register (PEDIR) ............................................................. 34-23
Port E Pin Assignment Register (PEPAR)........................................................... 34-24
Port E Special Options Register (PESO) ................................................................. 34-25
Chapter 35
CPM Interrupt Controller
35.1
35.2
35.2.1
35.2.2
35.2.3
35.3
35.4
35.5
35.5.1
35.5.2
35.5.3
35.5.4
35.5.5
35.6
35.7
Features .......................................................................................................................... 35-1
CPM Interrupt Source Priorities .................................................................................... 35-2
Programming Relative Priority (Grouping and Spreading) ....................................... 35-3
Highest Priority Interrupt........................................................................................... 35-4
Nested Interrupts........................................................................................................ 35-4
Masking Interrupt Sources in the CPM ......................................................................... 35-4
Generating and Calculating Interrupt Vectors ............................................................... 35-5
CPIC Registers............................................................................................................... 35-6
CPM Interrupt Configuration Register (CICR) ......................................................... 35-6
CPM Interrupt Pending Register (CIPR) ................................................................... 35-8
CPM Interrupt Mask Register.................................................................................... 35-9
CPM Interrupt In-Service Register (CISR) ............................................................... 35-9
CPM Interrupt Vector Register (CIVR) ..................................................................... 35-9
Interrupt Handler Example—Single-Event Interrupt Source ...................................... 35-10
Interrupt Handler Example—Multiple-Event Interrupt Source................................... 35-10
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Paragraph
Number
Title
Page
Number
Part VI
Asynchronous Transfer Mode (ATM)
Chapter 36
ATM Overview
36.1
36.2
36.2.1
36.2.2
36.2.3
36.2.4
36.3
36.4
36.5
36.6
36.6.1
36.6.2
36.6.3
36.7
36.7.1
36.7.2
36.7.2.1
36.7.3
36.8
36.9
36.10
36.11
36.12
ATM Capabilities ........................................................................................................... 36-1
MPC885 and MPC860 Differences ............................................................................... 36-1
Parameter RAM Conflicts ......................................................................................... 36-2
IDMA2 Restriction .................................................................................................... 36-2
UTOPIA Conflicts ..................................................................................................... 36-2
ATM Pace Controller (APC), APC Timer, and SCC4 ............................................... 36-2
ATM Features ................................................................................................................ 36-3
MPC885 Application Example...................................................................................... 36-5
Overview of ATM Operation ......................................................................................... 36-6
UTOPIA Operation........................................................................................................ 36-6
UTOPIA Transmit Overview..................................................................................... 36-7
UTOPIA Receive Overview ...................................................................................... 36-7
Expanded Cells .......................................................................................................... 36-8
Serial ATM Operation.................................................................................................... 36-9
Serial ATM Transmit Overview................................................................................. 36-9
Serial ATM Receive Overview .................................................................................. 36-9
Cell Delineation ................................................................................................... 36-10
Cell Payload Scrambling/Descrambling.................................................................. 36-10
ATM Pace Control (APC)............................................................................................ 36-10
Internal and External Channels (Extended Channel Mode) ........................................ 36-11
ATM Port-to-Port (PTP) Cell Switching...................................................................... 36-11
Memory-to-Memory SAR ........................................................................................... 36-12
General ATM Initialization Requirement .................................................................... 36-12
Chapter 37
Buffer Descriptors and Connection Tables
37.1
37.1.1
37.1.2
37.1.3
37.1.4
37.2
37.2.1
37.2.1.1
ATM Buffer Descriptors (BDs) ..................................................................................... 37-1
AAL5 Buffers ............................................................................................................ 37-2
AAL0 Buffers ............................................................................................................ 37-3
ATM Receive Buffer Descriptors (RxBDs)............................................................... 37-3
ATM Transmit Buffer Descriptors (TxBDs).............................................................. 37-6
Receive and Transmit Connection Tables (RCTs and TCTs) ...................................... 37-10
Receive Connection Table (RCT)............................................................................ 37-11
Port-to-Port Protocol-Specific RCT .................................................................... 37-15
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Paragraph
Number
37.2.2
37.2.2.1
37.2.3
Title
Page
Number
Transmit Connection Table (TCT)........................................................................... 37-20
Port-to-Port Protocol-Specific TCT..................................................................... 37-24
Transmit Connection Table Extensions (TCTE)...................................................... 37-27
Chapter 38
ATM Parameter RAM
38.1
38.2
38.3
38.4
38.5
38.6
38.7
38.8
SAR Receive Function Code Register (SRFCR)........................................................... 38-8
SAR Receive State Register (SRSTATE) ...................................................................... 38-9
SAR Transmit Function Code Register (STFCR)........................................................ 38-10
SAR Transmit State Register (STSTATE) ................................................................... 38-11
Address Match Parameters (AM1–AM5).................................................................... 38-11
APC State Register (APCST) ...................................................................................... 38-14
Multi-PHY State Register (MPHYST) (UTOPIA Master Only)................................. 38-15
Serial Cell Synchronization Status Register (ASTATUS) ........................................... 38-16
Chapter 39
ATM Controller
39.1
39.1.1
39.1.1.1
39.1.1.2
39.1.2
39.1.2.1
39.1.2.2
39.1.2.3
39.1.2.4
39.1.2.5
39.1.3
39.2
39.3
39.3.1
39.3.1.1
39.3.2
39.3.3
39.3.4
39.3.5
39.3.5.1
39.3.5.2
39.3.5.3
Address Mapping........................................................................................................... 39-1
Internal Look-up Mechanism (SRSTATE[EXT] = 0)................................................ 39-1
Adding a New Internal Channel ............................................................................ 39-2
Removing an Internal Channel .............................................................................. 39-2
Address Compression (SRSTATE[EXT,ACP] = 11) ................................................. 39-2
First-Level Addressing Table (FLT) ...................................................................... 39-3
Second-Level Addressing Tables (SLTs)............................................................... 39-3
Address Compression Example............................................................................. 39-4
Preventing Channel Aliasing ................................................................................. 39-4
OAM Screening ..................................................................................................... 39-5
CAM Address Mapping (SRSTATE[EXT,ACP] = 10) ............................................. 39-5
Management Cell Filter (MCF) ..................................................................................... 39-5
Performance Monitoring (PM) ...................................................................................... 39-8
Running a Performance Block Test ........................................................................... 39-9
FMC Template ..................................................................................................... 39-10
Terminating FMC Cells ........................................................................................... 39-10
BRC Performance Calculations ............................................................................... 39-12
Performance Monitoring Tables .............................................................................. 39-12
Activating Performance Monitoring........................................................................ 39-14
Activating Unidirectional Transmit PM .............................................................. 39-14
Activating Unidirectional Receive PM................................................................ 39-14
Activating Bidirectional PM................................................................................ 39-14
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Paragraph
Number
39.4
39.4.1
39.4.2
39.4.3
39.4.4
39.4.5
39.5
39.6
39.6.1
39.6.1.1
39.6.1.2
39.6.1.3
39.6.2
39.7
Title
Page
Number
Port-to-Port (PTP) Switching....................................................................................... 39-15
PTP Switching Mechanism...................................................................................... 39-15
PTP Switching and PM ............................................................................................ 39-17
PTP Buffers.............................................................................................................. 39-17
PTP Buffer Descriptors ............................................................................................ 39-17
APC PTP Queues ..................................................................................................... 39-18
Statistical Counters ...................................................................................................... 39-18
Multi-PHY (MPHY) Configuration............................................................................. 39-19
Programming Multi-PHY Mode (Master Only) ...................................................... 39-20
Internal Look-up Table MPHY Support .............................................................. 39-20
Address Compression Multi-PHY Support ......................................................... 39-21
CAM Multi-PHY Support ................................................................................... 39-21
Programming Slave Operation in a Multi-PHY System.......................................... 39-21
ATM Commands.......................................................................................................... 39-21
Chapter 40
ATM Pace Control
40.1
40.1.1
40.1.2
40.1.3
40.1.4
40.1.5
40.1.6
40.1.7
40.1.8
40.1.9
40.1.10
40.2
40.3
40.4
40.5
40.5.1
40.5.2
40.6
40.7
40.8
40.9
40.10
40.11
APC Algorithm .............................................................................................................. 40-1
APC Implementation ................................................................................................. 40-3
APC Parameters......................................................................................................... 40-4
Programming APC Scheduling Table Size and NCITS............................................. 40-5
Defining APC Slot Time............................................................................................ 40-6
Programming Rates for CBR Channels ..................................................................... 40-6
Programming Rates for VBR Channels..................................................................... 40-7
Programming Rates for UBR Channels..................................................................... 40-8
APC Initialization and Operating Considerations ..................................................... 40-9
Modifying Channel Transmit Pace ............................................................................ 40-9
Minimizing Cell Delay Variation............................................................................... 40-9
Direct Scheduling of Cells ........................................................................................... 40-10
Using the APC with Multiple ATM Ports.................................................................... 40-10
Using the APC Without Using SCC4 or UTOPIA ...................................................... 40-11
APC Flux Compensation ............................................................................................. 40-12
Enabling APC Flux Compensation.......................................................................... 40-12
Debugging Overload Conditions ............................................................................. 40-13
APC Scheduling Tables ............................................................................................... 40-13
PHY Transmit Queues ................................................................................................. 40-14
MPHY Pointing Table (Master Only).......................................................................... 40-14
APC Priority Levels..................................................................................................... 40-15
Combined APC and PTP Programming Example ....................................................... 40-20
APC Scheduling Flow ................................................................................................. 40-21
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Number
Title
Page
Number
Chapter 41
ATM Exceptions
41.1
41.1.1
41.1.2
41.2
41.3
ATM Event Registers..................................................................................................... 41-2
UTOPIA Event Register (IDSR1) ............................................................................. 41-2
Serial ATM Event Register (SCCE) .......................................................................... 41-3
Interrupt Queue Entry .................................................................................................... 41-4
Interrupt Queue Mask (IMASK).................................................................................... 41-6
Chapter 42
Interface Configuration
42.1
42.1.1
42.1.2
42.1.3
42.2
42.2.1
42.2.2
42.2.3
42.2.4
42.2.5
42.2.6
42.2.7
42.3
42.3.1
42.3.2
42.3.2.1
42.3.2.1.1
42.3.2.2
42.3.3
General ATM Registers ................................................................................................. 42-1
Port D Pin Assignment Register (PDPAR)................................................................ 42-1
APC Timer (CPM Timer 4) ....................................................................................... 42-2
RISC Timer ................................................................................................................ 42-2
UTOPIA Mode Registers............................................................................................... 42-2
System Clock Control Register (SCCR).................................................................... 42-2
Port B—MasterTxClav/Slave RxClav and PHY Address Signals ............................ 42-3
Port C—MasterRxClav/Slave TxClav Signal............................................................ 42-4
Port D—UTOPIA Data and Control Signals ............................................................. 42-5
PCMCIA Port A Signal Multiplexing ....................................................................... 42-6
RISC Controller Configuration Register (RCCR) ..................................................... 42-6
UTOPIA Mode Initialization ..................................................................................... 42-6
Serial ATM Configuration ............................................................................................. 42-7
RISC Controller Configuration Register (RCCR) ..................................................... 42-7
SCC Configuration for Serial ATM ........................................................................... 42-7
General SCC Mode Register (GSMR) .................................................................. 42-7
Bit-Aligned Cell Delineation............................................................................. 42-7
Serial ATM Mode Register (PSMR)...................................................................... 42-8
SI Configuration for Serial ATM ............................................................................... 42-8
Chapter 43
UTOPIA Interface
43.1
43.2
43.3
43.3.1
43.3.2
UTOPIA Features .......................................................................................................... 43-1
UTOPIA Mode Register (UTMODE) ........................................................................... 43-1
UTOPIA Operation........................................................................................................ 43-5
UTOPIA Split Bus ..................................................................................................... 43-6
UTOPIA Muxed Bus (Master Operation Only) ........................................................ 43-6
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Paragraph
Number
43.3.3
43.3.4
Title
Page
Number
UTOPIA Multi-PHY Master Operation .................................................................... 43-7
UTOPIA Multi-PHY Slave Operation....................................................................... 43-7
Chapter 44
AAL2 Implementation
44.1
44.2
44.2.1
44.2.2
44.3
44.4
44.4.1
44.4.2
44.4.3
44.4.4
44.4.5
44.4.5.1
44.4.5.1.1
44.4.5.1.2
44.4.5.2
44.5
44.5.1
44.5.2
44.5.3
44.5.4
44.6
44.7
44.7.1
44.7.2
44.8
44.9
44.9.1
44.9.2
44.10
44.10.1
44.10.2
44.10.3
44.10.4
44.10.5
44.11
AAL2 Features and Restrictions.................................................................................... 44-1
Overview of the AAL2 Implementation........................................................................ 44-1
AAL2 Transmit Overview ......................................................................................... 44-2
AAL2 Receive Overview........................................................................................... 44-4
AAL2 Interface with the Host ....................................................................................... 44-5
AAL2 Data Structures for Transmit............................................................................... 44-5
Transmit Packet Descriptor (TPD) ............................................................................ 44-5
AAL2_Tx_Queue ...................................................................................................... 44-7
AAL2 Transmit Connection Table (AAL2_TCT) ..................................................... 44-7
Example of AAL2 Transmit .................................................................................... 44-10
Built-in Timer CU Support ...................................................................................... 44-11
Algorithm Description ......................................................................................... 44-11
Starting the Timer for a Partially-Filled Active Buffer ................................... 44-12
Countdown Mechanism and Detection of Expired Buffers............................. 44-12
Example of Timer CU Implementation ............................................................... 44-13
AAL2 Data Structures for Receive .............................................................................. 44-13
Receive Packet Descriptor (RPD)............................................................................ 44-13
AAL2_Rx_Queue .................................................................................................... 44-16
AAL2 Receive Connection Table (AAL2_RCT) .................................................... 44-17
Example of AAL2 Receive...................................................................................... 44-19
Systems Restrictions When Using the AAL2 Functionality ....................................... 44-20
Global AAL2 Data Structures...................................................................................... 44-20
AAL2 Parameter RAM............................................................................................ 44-20
Mapping the AAL2 Connection Tables in External Memory.................................. 44-24
DPRAM Usage for AAL2 ........................................................................................... 44-24
AAL2 Exceptions ........................................................................................................ 44-24
AAL2 Transmit Exceptions ..................................................................................... 44-26
AAL2 Receive Exceptions....................................................................................... 44-26
Initialization of MPC885 for AAL2 Operation ........................................................... 44-26
Initialization of AAL0 Structures for AAL2 Channels ........................................... 44-26
Initialization of Address Translation Mechanism.................................................... 44-27
Initialization of Global AAL2 Structures ................................................................ 44-27
Reconfiguring AAL2 Channels ............................................................................... 44-27
Initialization of Timer CU Mechanism (Optional) .................................................. 44-28
Performance Estimation............................................................................................... 44-28
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Number
44.12
44.13
Title
Page
Number
PHY Interface .............................................................................................................. 44-28
Additional Recommendations...................................................................................... 44-28
Part VII
Fast Ethernet Controller (FEC)
Chapter 45
Fast Ethernet Controller (FEC)
45.1
45.1.1
45.2
45.2.1
45.2.2
45.2.3
45.2.4
45.2.5
45.2.6
45.2.7
45.2.8
45.2.9
45.2.10
45.2.10.1
45.2.10.2
45.2.11
45.2.12
45.2.12.1
45.3
45.3.1
45.3.2
45.3.2.1
45.3.2.2
45.3.2.3
45.3.2.4
45.3.2.5
45.3.2.6
45.3.2.7
45.3.2.8
45.3.2.9
45.3.2.10
45.3.2.11
Features .......................................................................................................................... 45-1
FEC Block Diagram................................................................................................... 45-2
Fast Ethernet Controller Operation................................................................................ 45-3
Transceiver Connection ............................................................................................. 45-3
FEC Frame Transmission .......................................................................................... 45-4
FEC Frame Reception................................................................................................ 45-5
FEC Command Set .................................................................................................... 45-6
Ethernet Address Recognition ................................................................................... 45-6
Hash Table Algorithm................................................................................................ 45-7
Inter-Packet Gap Time ............................................................................................... 45-8
Collision Handling..................................................................................................... 45-8
Internal and External Loopback................................................................................. 45-8
Ethernet Error-Handling Procedure ........................................................................... 45-8
Transmission Errors ............................................................................................... 45-9
Reception Errors .................................................................................................... 45-9
SDMA Bus Arbitration and Transfers ....................................................................... 45-9
The SDMA Registers............................................................................................... 45-10
SDMA Configuration Register (SDCR).............................................................. 45-10
Programming Model .................................................................................................... 45-10
Communications Processor Timing Register (CPTR) ............................................. 45-11
Parameter RAM ....................................................................................................... 45-12
RAM Perfect Match Address Low Register (ADDR_LOW).............................. 45-13
RAM Perfect Match Address High (ADDR_HIGH)........................................... 45-14
RAM Hash Table High (HASH_TABLE_HIGH) ............................................... 45-14
RAM Hash Table Low (HASH_TABLE_LOW)................................................. 45-15
Beginning of RxBD Ring (R_DES_START) ...................................................... 45-16
Beginning of TxBD Ring (X_DES_START) ...................................................... 45-16
Receive Buffer Size Register (R_BUFF_SIZE) .................................................. 45-17
Ethernet Control Register (ECNTRL) ................................................................. 45-18
Interrupt Event (I_EVENT)/Interrupt Mask Register (I_MASK) ....................... 45-19
Ethernet Interrupt Vector Register (IVEC) .......................................................... 45-20
RxBD Active Register (R_DES_ACTIVE)......................................................... 45-21
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Paragraph
Number
45.3.2.12
45.3.2.13
45.3.2.14
45.3.2.15
45.3.2.16
45.3.2.17
45.3.2.18
45.3.2.19
45.3.2.20
45.3.2.21
45.3.2.22
45.3.3
45.3.3.1
45.3.3.2
45.3.3.2.1
45.3.3.2.2
45.3.4
45.3.4.1
45.3.4.2
Title
Page
Number
TxBD Active Register (X_DES_ACTIVE)......................................................... 45-22
MII Management Frame Register (MII_DATA) ................................................. 45-22
MII Speed Control Register (MII_SPEED)......................................................... 45-24
FIFO Receive Bound Register (R_BOUND) ...................................................... 45-25
FIFO Receive Start Register (R_FSTART) ......................................................... 45-26
Transmit Watermark Register (X_WMRK)......................................................... 45-27
FIFO Transmit Start Register (X_FSTART)........................................................ 45-28
DMA Function Code Register (FUN_CODE) .................................................... 45-29
Receive Control Register (R_CNTRL) ............................................................... 45-29
Receive Hash Register (R_HASH)...................................................................... 45-30
Transmit Control Register (X_CNTRL).............................................................. 45-31
Initialization Sequence............................................................................................. 45-32
Hardware Initialization ........................................................................................ 45-32
User Initialization (before Setting ECNTRL[ETHER_EN])............................... 45-33
Descriptor Controller Initialization ................................................................. 45-34
User Initialization (after Setting ECNTRL[ETHER_EN]) ............................. 45-34
Buffer Descriptors (BDs)......................................................................................... 45-34
Ethernet Receive Buffer Descriptor (RxBD)....................................................... 45-35
Ethernet Transmit Buffer Descriptor (TxBD)...................................................... 45-36
Part VIII
Integrated Security Engine (SEC Lite)
Chapter 46
SEC Lite Overview
46.1
46.2
46.3
46.4
46.5
46.6
46.7
46.8
46.9
46.9.1
46.9.2
46.9.3
46.10
Development History ..................................................................................................... 46-1
Features .......................................................................................................................... 46-1
SEC Lite Architecture................................................................................................... 46-2
Architectural Overview.................................................................................................. 46-2
Data Packet Descriptors................................................................................................. 46-3
Master/Slave Interface ................................................................................................... 46-4
SEC Lite Controller ....................................................................................................... 46-4
Crypto-Channel.............................................................................................................. 46-5
Execution Units (EUs) ................................................................................................... 46-5
Data Encryption Standard Execution Unit (DEU)..................................................... 46-5
Advanced Encryption Standard Execution Unit (AESU).......................................... 46-6
Message Digest Execution Unit (MDEU) ................................................................. 46-6
Performance Estimates .................................................................................................. 46-6
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Paragraph
Number
Title
Page
Number
Chapter 47
SEC Lite Address Map
47.1
Address Map .................................................................................................................. 47-1
Chapter 48
SEC Lite Execution Units
48.1
48.1.1
48.1.2
48.1.3
48.1.4
48.1.5
48.1.6
48.1.7
48.1.8
48.1.9
48.1.10
48.1.11
48.1.12
48.2
48.2.1
48.2.2
48.2.2.1
48.2.3
48.2.4
48.2.5
48.2.6
48.2.7
48.2.8
48.2.9
48.2.10
48.2.11
48.2.12
48.3
48.3.1
48.3.2
48.3.3
48.3.4
48.3.5
Data Encryption Standard Execution Units (DEU) ....................................................... 48-2
DEU Register Map..................................................................................................... 48-2
DEU Mode Register................................................................................................... 48-2
DEU Key Size Register ............................................................................................. 48-3
DEU Data Size Register ............................................................................................ 48-4
DEU Reset Control Register...................................................................................... 48-5
DEU Status Register .................................................................................................. 48-6
DEU Interrupt Status Register ................................................................................... 48-7
DEU Interrupt Control Register................................................................................. 48-9
DEU EU_GO Register............................................................................................. 48-11
DEU IV Register...................................................................................................... 48-12
DEU Key Registers.................................................................................................. 48-12
DEU FIFOs .............................................................................................................. 48-12
Message Digest Execution Units (MDEU).................................................................. 48-12
MDEU Register Map ............................................................................................... 48-12
MDEU Mode Register ............................................................................................. 48-13
Recommended settings for MDEU Mode Register ............................................. 48-14
MDEU Key Size Register........................................................................................ 48-15
MDEU Data Size Register....................................................................................... 48-15
MDEU Reset Control Register ................................................................................ 48-16
MDEU Status Register............................................................................................. 48-17
MDEU Interrupt Status Register.............................................................................. 48-18
MDEU Interrupt Control Register ........................................................................... 48-20
MDEU EU_GO Register ......................................................................................... 48-21
MDEU Context Registers ........................................................................................ 48-22
MDEU Key Registers .............................................................................................. 48-23
MDEU FIFOs .......................................................................................................... 48-23
Advanced Encryption Standard Execution Unit (AESU) ............................................ 48-24
AESU Register Map ................................................................................................ 48-24
AESU Mode Register .............................................................................................. 48-24
AESU Key Size Register ......................................................................................... 48-26
AESU Data Size Register ........................................................................................ 48-27
AESU Reset Control Register.................................................................................. 48-28
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Contents
Paragraph
Number
48.3.6
48.3.7
48.3.8
48.3.9
48.3.9.1
48.3.9.2
48.3.9.3
48.3.9.4
48.3.9.5
Title
Page
Number
AESU Status Register .............................................................................................. 48-29
AESU Interrupt Status Register ............................................................................... 48-30
AESU Interrupt Control Register ............................................................................ 48-32
AESU End of Message Register.............................................................................. 48-34
AESU Context Registers ..................................................................................... 48-34
Context for CBC Mode........................................................................................ 48-35
Context for Counter Mode................................................................................... 48-35
AESU Key Registers ........................................................................................... 48-36
AESU FIFOs........................................................................................................ 48-36
Chapter 49
SEC Lite Descriptors
49.1
49.2
49.2.1
49.2.2
49.3
49.3.1
49.4
Data Packet Descriptor Overview.................................................................................. 49-1
Descriptor Structure ....................................................................................................... 49-1
Descriptor Header ...................................................................................................... 49-2
Descriptor Length and Pointer Fields ........................................................................ 49-4
Descriptor Chaining ....................................................................................................... 49-6
Null Fields.................................................................................................................. 49-7
Dynamic Descriptors ..................................................................................................... 49-7
Chapter 50
SEC Lite Crypto-Channel
50.1
50.1.1
50.1.2
50.1.3
50.1.4
50.1.5
50.1.5.1
50.1.5.2
50.1.5.3
50.2
50.2.1
50.2.2
50.2.3
50.2.3.1
50.2.3.2
Crypto-Channel Registers.............................................................................................. 50-2
Crypto-Channel Configuration Register (CCCR)...................................................... 50-2
Crypto-Channel Pointer Status Registers (CCPSR) .................................................. 50-4
Crypto-Channel Current Descriptor Pointer Register (CDPR)................................ 50-10
Fetch Register (FR).................................................................................................. 50-11
Descriptor Buffer (DB) ............................................................................................ 50-12
Descriptor Header................................................................................................ 50-12
Descriptor Length/Pointer Pairs .......................................................................... 50-13
Next Descriptor Pointer ....................................................................................... 50-13
Interrupts ...................................................................................................................... 50-13
Channel Done Interrupt ........................................................................................... 50-13
Channel Error Interrupt............................................................................................ 50-14
Channel Reset .......................................................................................................... 50-14
Hardware Reset.................................................................................................... 50-14
Channel Specific Software Reset......................................................................... 50-14
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Contents
Paragraph
Number
Title
Page
Number
Chapter 51
SEC Lite Controller
51.1
51.1.1
51.1.2
51.1.3
51.1.4
51.1.5
51.1.6
Controller Registers ....................................................................................................... 51-1
Interrupt Mask Registers (IMR) ................................................................................ 51-1
Interrupt Status Registers........................................................................................... 51-2
Interrupt Clear Registers (ICR).................................................................................. 51-3
ID Register................................................................................................................. 51-6
Master Control Register (MCR) ................................................................................ 51-6
Master Error Address Register (MEAR) ................................................................... 51-7
Chapter 52
SEC Lite Master/Slave Interface Module
52.1
52.2
52.2.1
52.2.2
52.2.3
52.2.3.1
52.2.4
52.2.5
52.2.6
Communications Processor Timing Register (CPTR) ................................................... 52-1
Master/Slave Interface ................................................................................................... 52-2
Bus Access................................................................................................................. 52-2
Bus Master ................................................................................................................. 52-2
Master Read ............................................................................................................... 52-2
Target Aborts ......................................................................................................... 52-3
Master Write .............................................................................................................. 52-3
Misaligned Data......................................................................................................... 52-3
Target Access ............................................................................................................. 52-4
Part IX
System Debugging and Testing Support
Intended Audience 1
Contents 1
Suggested Reading 1
MPC8xx Documentation .....................................................................................................1
Conventions 1
Acronyms and Abbreviations 2
Chapter 53
System Development and Debugging
53.1
53.1.1
53.1.2
53.1.3
Tracking Program Flow ................................................................................................. 53-1
Program Trace Functional Description...................................................................... 53-2
Instruction Fetch Show Cycle Control....................................................................... 53-2
Program Trace Signals............................................................................................... 53-3
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Contents
Paragraph
Number
53.1.4
53.1.4.1
53.1.4.2
53.1.4.3
53.1.5
53.1.5.1
53.1.5.2
53.1.5.2.1
53.1.5.3
53.1.5.4
53.1.5.5
53.1.5.6
53.2
53.2.1
53.2.2
53.2.3
53.2.3.1
53.2.3.2
53.2.3.3
53.2.3.4
53.2.4
53.2.4.1
53.2.4.2
53.2.4.2.1
53.2.4.3
53.2.4.4
53.2.4.5
53.2.5
53.3
53.3.1
53.3.1.1
53.3.1.2
53.3.1.3
53.3.1.4
53.3.1.5
53.3.1.6
53.3.1.7
53.3.2
53.3.2.1
53.3.2.1.1
53.3.2.1.2
Title
Page
Number
Program Trace Special Cases..................................................................................... 53-4
Queue Flush Information Special Case ................................................................. 53-4
Program Trace When In Debug Mode................................................................... 53-4
Sequential Instructions Marked as Indirect Branch............................................... 53-5
Reconstructing Program Trace .................................................................................. 53-5
Back Trace ............................................................................................................. 53-5
Window Trace........................................................................................................ 53-5
Synchronizing the Trace Window to Internal Core Events ............................... 53-5
Detecting the Trace Window Start Address........................................................... 53-6
Detecting the Assertion/Negation of VSYNC ....................................................... 53-7
Detecting the Trace Window End Address............................................................ 53-7
Efficient Trace Information Capture...................................................................... 53-7
Watchpoints and Breakpoints Support........................................................................... 53-7
Key Features .............................................................................................................. 53-8
Internal Watchpoints and Breakpoints Logic........................................................... 53-10
Functional Description............................................................................................. 53-10
Instruction Support Detailed Description ............................................................ 53-10
Load/Store Support Detailed Description............................................................ 53-11
The Counters........................................................................................................ 53-13
Trap Enable Programming................................................................................... 53-14
Operation Details ..................................................................................................... 53-14
Restrictions .......................................................................................................... 53-14
Byte and Half Word Working Modes .................................................................. 53-14
Examples ......................................................................................................... 53-14
Context Dependent Filter..................................................................................... 53-16
Ignore First Match ............................................................................................... 53-16
Generating Six Compare Types ........................................................................... 53-16
Load/Store Breakpoint Example.............................................................................. 53-17
Development System Interface.................................................................................... 53-17
Debug Mode Operation ........................................................................................... 53-19
Debug Mode Enable vs. Debug Mode Disable ................................................... 53-20
Entering Debug Mode.......................................................................................... 53-21
Debug Mode Indication ....................................................................................... 53-22
Checkstop State and Debug Mode....................................................................... 53-22
Saving Machine State when Entering Debug Mode............................................ 53-23
Running in Debug Mode ..................................................................................... 53-23
Exiting Debug Mode............................................................................................ 53-23
Development Port Communication ......................................................................... 53-24
Development Port Pins ........................................................................................ 53-24
Development Serial Clock (DSCK) ................................................................ 53-24
Development Serial Data In (DSDI) ............................................................... 53-24
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Paragraph
Number
53.3.2.1.3
53.3.2.1.4
53.3.2.2
53.3.2.2.1
53.3.2.2.2
53.3.2.2.3
53.3.2.3
53.3.2.3.1
53.3.2.3.2
53.3.2.3.3
53.3.2.4
53.3.2.4.1
53.3.2.4.2
53.3.2.5
53.3.2.5.1
53.3.2.5.2
53.3.2.5.3
53.4
53.4.1
53.5
53.5.1
53.5.1.1
53.5.1.2
53.5.1.3
53.5.1.4
53.5.1.5
53.5.1.6
53.5.2
53.5.2.1
53.5.2.2
53.5.2.3
Title
Page
Number
Development Serial Data Out (DSDO) ........................................................... 53-24
Freeze............................................................................................................... 53-25
Development Port Registers ................................................................................ 53-25
Development Port Shift Register ..................................................................... 53-25
Trap Enable Control Register (TECR) ............................................................ 53-25
Development Port Registers Decode ............................................................... 53-26
Development Port Serial Communications–Clock Mode.................................... 53-26
Asynchronous Clocked Mode—Using DSCK ................................................ 53-26
Synchronous Self-Clocked Mode—Using CLKOUT ..................................... 53-27
Selection of Development Port Clock Mode ................................................... 53-27
Development Port Serial Communications–Trap Enable Mode.......................... 53-28
Serial Data Into Development Port.................................................................. 53-28
Serial Data Out of Development Port.............................................................. 53-29
Development Port Serial Communications–Debug Mode .................................. 53-30
Serial Data Into Development Port.................................................................. 53-30
Serial Data Out of Development Port.............................................................. 53-31
Fast Download Procedure................................................................................ 53-32
Software Monitor Debugger Support .......................................................................... 53-33
Freeze Indication...................................................................................................... 53-33
Development Support Programming Model................................................................ 53-33
Development Support Registers .............................................................................. 53-35
Comparator A–H Value Registers (CMPA–CMPH) ........................................... 53-35
Breakpoint Address Register (BAR) ................................................................... 53-36
Instruction Support Control Register (ICTRL).................................................... 53-37
Load/Store Support Comparators Control Register (LCTRL1) .......................... 53-38
Load/Store Support AND-OR Control Register (LCTRL2)................................ 53-40
Breakpoint Counter Value and Control
Registers (COUNTA/COUNTB)..................................................................... 53-42
Debug Mode Registers............................................................................................. 53-42
Interrupt Cause Register (ICR)............................................................................ 53-42
Debug Enable Register (DER)............................................................................. 53-44
Development Port Data Register (DPDR) ........................................................... 53-46
Chapter 54
IEEE 1149.1 Test Access Port
54.1
54.2
54.3
54.4
54.4.1
Overview........................................................................................................................ 54-1
TAP Controller............................................................................................................... 54-2
Boundary Scan Register................................................................................................. 54-3
Instruction Register........................................................................................................ 54-5
EXTEST..................................................................................................................... 54-6
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Paragraph
Number
54.4.2
54.4.3
54.4.4
54.4.5
54.5
54.6
54.7
Title
Page
Number
SAMPLE/PRELOAD ................................................................................................ 54-6
BYPASS..................................................................................................................... 54-6
CLAMP...................................................................................................................... 54-7
HI–Z........................................................................................................................... 54-7
TAP Usage Considerations ............................................................................................ 54-7
Recommended TAP Configuration................................................................................ 54-7
MPC885 BSDL Description .......................................................................................... 54-8
Appendix A
Byte Ordering
A.1
A.2
A.3
A.4
A.4.1
A.5
A.5.1
A.6
Byte Ordering Overview................................................................................................. A-1
Byte-Ordering Mechanisms ............................................................................................ A-1
BE Mode ......................................................................................................................... A-2
TLE Mode....................................................................................................................... A-2
TLE Mode System Examples ..................................................................................... A-4
PPC-LE Mode................................................................................................................. A-5
I/O Addressing in PPC-LE Mode ............................................................................... A-7
Setting the Endian Mode Of Operation .......................................................................... A-7
Appendix B
Serial Communications Performance
Appendix C
Register Quick Reference Guide
C.1
C.2
C.3
User Registers ..................................................................................................................C-1
Supervisor Registers ........................................................................................................C-2
MPC885-Specific SPRs ...................................................................................................C-2
Appendix D
Instruction Set Listings
D.1
D.2
D.3
D.4
D.5
Instructions Sorted by Mnemonic................................................................................... D-1
Instructions Sorted by Opcode........................................................................................ D-9
Instructions Grouped by Functional Categories ........................................................... D-17
Instructions Sorted by Form ......................................................................................... D-27
Instruction Set Legend .................................................................................................. D-39
Appendix E
MPC880
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Contents
Paragraph
Number
E.1
E.2
E.2.1
E.2.2
E.2.3
Title
Page
Number
MPC880 Overview ..........................................................................................................E-1
Implementation Impact of Two SCCs..............................................................................E-2
Unimplemented Signals...............................................................................................E-2
Serial Interface.............................................................................................................E-3
General Set-Up ............................................................................................................E-3
Appendix F
MPC875
F.1
F.2
F.2.1
F.2.2
F.2.3
MPC875 Overview .......................................................................................................... F-1
Implementation Impact of Differences between MPC885 and MPC875 ........................ F-2
Unimplemented Pins.................................................................................................... F-2
Other Unimplemented Signals..................................................................................... F-4
SCC and SMC General Set-Up.................................................................................... F-4
Appendix G
MPC870
G.1
G.2
G.2.1
G.2.2
G.2.3
MPC87066 Overview ..................................................................................................... G-1
Implementation Impact of Differences between MPC885 and MPC870 ....................... G-2
Unimplemented Pins................................................................................................... G-2
Other Unimplemented Signals.................................................................................... G-3
SMC General Set-Up .................................................................................................. G-4
Appendix H
Serial ATM Scrambling, Reception, and SI Programming
H.1
H.2
H.2.1
H.3
H.3.1
H.3.2
ATM Cell Payload Scrambling ....................................................................................... H-1
Receiving Serial ATM Cells ........................................................................................... H-1
HEC Delineation Mechanism ..................................................................................... H-3
Serial Interface Programming Example for Serial ATM ................................................ H-4
Serial Interface RAM.................................................................................................. H-4
Parallel Port Registers................................................................................................. H-5
Appendix I
Revision History
I.1
I.2
Revision Changes from Revision 1 to Revision 2 ............................................................I-1
Revision Changes from Revision 0.1 to Revision 1 ......................................................... I-1
Glossary of Terms and Abbreviations 1
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Contents
Paragraph
Number
Title
Page
Number
Index 1
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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Figures
Figure
Number
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
3-1
3-2
3-3
3-4
3-5
4-1
4-2
4-3
6-1
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
Title
Page
Number
Figures
MPC866P Block Diagram ...................................................................................................... 1-7
MPC885 Block Diagram......................................................................................................... 1-8
MPC866P Block Diagram ...................................................................................................... 1-9
MPC880 Block Diagram....................................................................................................... 1-10
MPC866P Block Diagram .................................................................................................... 1-12
MPC866P Block Diagram .................................................................................................... 1-13
MPC875 Block Diagram....................................................................................................... 1-13
MPC866P Block Diagram .................................................................................................... 1-14
MPC870 Block Diagram....................................................................................................... 1-15
Security Engine Functional Blocks....................................................................................... 1-17
Block Diagram of the Core ..................................................................................................... 3-4
Instruction Flow Conceptual Diagram .................................................................................... 3-6
Basic Instruction Pipeline Timing........................................................................................... 3-7
Sequencer Data Path ............................................................................................................... 3-8
LSU Functional Block Diagram ........................................................................................... 3-11
Condition Register (CR) ......................................................................................................... 4-2
XER Register .......................................................................................................................... 4-3
Machine State Register (MSR) ............................................................................................... 4-7
Exception Latency................................................................................................................. 6-18
MPC885 Instruction Cache Organization ............................................................................... 7-3
MPC885 Data Cache Organization......................................................................................... 7-5
Instruction Cache Control and Status Register (IC_CST) ...................................................... 7-6
Instruction Cache Address Register (IC_ADR)...................................................................... 7-7
Instruction Cache Data Port Register (IC_DAT) .................................................................... 7-8
Data Cache Control and Status Register (DC_CST)............................................................. 7-11
Data Cache Address Register (DC_ADR) ............................................................................ 7-13
Data Cache Data Port Register (DC_DAT)........................................................................... 7-13
Instruction Cache Data Path.................................................................................................. 7-20
Read/Instruction Fetch Flow Diagram .................................................................................... 8-4
Flow of Load/Store Access ..................................................................................................... 8-5
Effective-to-Physical Address Translation for 4-Kbyte Pages Block Diagram ...................... 8-6
Two-Level Translation Table (MD_CTR[TWAM] = 1) ......................................................... 8-9
Two-Level Translation Table (MD_CTR[TWAM] = 0) ....................................................... 8-10
IMMU Control Register (MI_CTR) ..................................................................................... 8-14
DMMU Control Register (MD_CTR) .................................................................................. 8-15
IMMU/DMMU Effective Page Number Register (Mx_EPN).............................................. 8-16
IMMU Tablewalk Control Register (MI_TWC)................................................................... 8-17
DMMU Tablewalk Control Register (MD_TWC)................................................................ 8-18
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Figures
Figure
Number
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
8-20
8-21
8-22
8-23
8-24
8-25
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
10-17
Title
Page
Number
IMMU Real Page Number Register (MI_RPN) ................................................................... 8-19
DMMU Real Page Number Register (MD_RPN) ................................................................ 8-21
MMU Tablewalk Base Register (M_TWB).......................................................................... 8-22
MMU Current Address Space ID Register (M_CASID) ...................................................... 8-22
MMU Access Protection Registers (MI_AP/MD_AP)......................................................... 8-23
MMU Tablewalk Special Register (M_TW)......................................................................... 8-23
IMMU CAM Entry Read Register (MI_CAM) .................................................................... 8-24
IMMU RAM Entry Read Register 0 (MI_RAM0) ............................................................... 8-25
IMMU RAM Entry Read Register 1 (MI_RAM1) ............................................................... 8-26
DMMU CAM Entry Read Register (MD_CAM) ................................................................. 8-27
DMMU RAM Entry Read Register 0 (MD_RAM0) ............................................................ 8-28
DMMU RAM Entry Read Register 1 (MD_RAM1) ............................................................ 8-29
DTLB Reload Code Example ............................................................................................... 8-32
ITLB Reload Code Example................................................................................................. 8-32
Configuring the TLB Replacement Counter ......................................................................... 8-33
Data Cache Load Timing ........................................................................................................ 9-1
Writeback Arbitration Timing—Example 1............................................................................ 9-2
Writeback Arbitration Timing—Example 2............................................................................ 9-2
Private Writeback Bus Load Timing....................................................................................... 9-3
External Load Timing ............................................................................................................. 9-3
Full Completion Queue Timing .............................................................................................. 9-4
Branch Folding Timing ........................................................................................................... 9-4
Branch Prediction Timing ....................................................................................................... 9-5
Bus Latency for String Instructions ........................................................................................ 9-8
System Configuration and Protection Logic ......................................................................... 10-3
Internal Memory Map Register (IMMR) .............................................................................. 10-4
SIU Module Configuration Register (SIUMCR) .................................................................. 10-5
System Protection Control Register (SYPCR)...................................................................... 10-7
Transfer Error Status Register (TESR) ................................................................................. 10-9
Register Lock Mechanism .................................................................................................. 10-11
MPC885 Interrupt Structure................................................................................................ 10-12
SIU Interrupt Processing ..................................................................................................... 10-13
IRQ0 Logical Representation.............................................................................................. 10-14
SIU Interrupt Pending Register (SIPEND) ......................................................................... 10-15
SIU Interrupt Mask Register (SIMASK) ............................................................................ 10-16
SIU Interrupt Edge/Level Register (SIEL) ......................................................................... 10-17
SIU Interrupt Vector Register (SIVEC) .............................................................................. 10-18
Interrupt Table Handling Example...................................................................................... 10-19
Software Watchdog Timer Service State Diagram.............................................................. 10-20
Software Watchdog Timer Block Diagram ......................................................................... 10-21
Software Service Register (SWSR) .................................................................................... 10-21
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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Figures
Figure
Number
10-18
10-19
10-20
10-21
10-22
10-23
10-24
10-25
10-26
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
12-1
12-2
12-3
12-4
12-5
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
13-16
13-17
13-18
13-19
Title
Page
Number
Decrementer Register (DEC) .............................................................................................. 10-22
Timebase Upper Register (TBU) ........................................................................................ 10-23
Timebase Lower Register (TBL) ........................................................................................ 10-24
Timebase Reference Registers (TBREFA and TBREFB)................................................... 10-24
Timebase Status and Control Register (TBSCR) ................................................................ 10-25
Periodic Interrupt Timer Block Diagram ............................................................................ 10-26
Periodic Interrupt Status and Control Register (PISCR)..................................................... 10-26
PIT Count Register (PITC) ................................................................................................. 10-27
PIT Register (PITR) ............................................................................................................ 10-28
Power-On and Hard Reset Sequence .................................................................................... 11-3
Soft Reset Sequence.............................................................................................................. 11-4
Reset Status Register (RSR).................................................................................................. 11-5
Data Bus Configuration Input Circuit ................................................................................... 11-6
Reset Configuration Sampling for Short PORESET Assertion............................................ 11-7
Reset Configuration Sampling for Long PORESET Assertion ............................................ 11-7
Reset Configuration Sampling Timing Requirements .......................................................... 11-8
Hard Reset Configuration Word............................................................................................ 11-8
MPC885 Signals and Pin Numbers (Part 1).......................................................................... 12-2
MPC885 Signals and Pin Numbers (Part 2).......................................................................... 12-3
MPC875 Signals and Pin Numbers (Part 1)........................................................................ 12-24
MPC875 Signals and Pin Numbers (Part 2)........................................................................ 12-25
Three-State Buffers and Active Pull-Up Buffers ................................................................ 12-41
Input Sample Window........................................................................................................... 13-2
MPC885 Bus Signals ............................................................................................................ 13-3
Basic Transfer Protocol......................................................................................................... 13-6
Basic Flow Diagram of a Single-Beat Read Cycle ............................................................... 13-7
Basic Timing: Single-Beat Read Cycle, Zero Wait States .................................................... 13-8
Basic Timing: Single-Beat Read Cycle, One Wait State....................................................... 13-9
Basic Flow of a Single-Beat Write Cycle ........................................................................... 13-10
Basic Timing: Single-Beat Write Cycle, Zero Wait States ................................................. 13-11
Basic Timing: Single-Beat Write Cycle, One Wait State.................................................... 13-12
Basic Timing: Single-Beat, 32-Bit Data Write Cycle, 16-Bit Port Size ............................. 13-13
Basic Flow of a Burst-Read Cycle...................................................................................... 13-16
Burst-Read Cycle: 32-Bit Port Size, Zero Wait State ......................................................... 13-17
Burst-Read Cycle: 32-Bit Port Size, One Wait State .......................................................... 13-18
Burst-Read Cycle: 32-Bit Port Size, Wait States between Beats ........................................ 13-19
Burst-Read Cycle: 16-Bit Port Size, One Wait State between Beats .................................. 13-20
Basic Flow of a Burst Write Cycle...................................................................................... 13-21
Burst-Write Cycle: 32-Bit Port Size, Zero Wait States ....................................................... 13-22
Burst-Inhibit Cycle: 32-Bit Port Size.................................................................................. 13-23
Internal Operand Representation ........................................................................................ 13-24
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
li
Figures
Figure
Number
13-20
13-21
13-22
13-23
13-24
13-25
13-26
13-27
13-28
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15-14
Title
Page
Number
Interface to Different Port Size Devices ............................................................................. 13-24
Basic Bus Arbitration Protocol ........................................................................................... 13-26
Bus Busy (BB) and Transfer Start (TS) Connection Example............................................ 13-27
Bus Arbitration Timing Diagram ........................................................................................ 13-28
Internal Bus Arbitration State Machine .............................................................................. 13-29
Termination Signals Protocol Basic Connection................................................................. 13-34
Termination Signals Protocol Timing Diagram .................................................................. 13-34
Reservation On Local Bus .................................................................................................. 13-36
Reservation on Multilevel Bus Hierarchy........................................................................... 13-37
Retry Transfer Timing–Internal Arbiter.............................................................................. 13-38
Retry Transfer Timing–External Arbiter............................................................................. 13-39
Retry on Burst Cycle........................................................................................................... 13-40
Clock Source and Distribution.............................................................................................. 14-2
Clock Module Components .................................................................................................. 14-3
Crystal Circuit Examples ...................................................................................................... 14-8
Clock Dividers ...................................................................................................................... 14-9
Frequency Dividers for GCLKx.......................................................................................... 14-10
Divided System Clocks (GCLKx) Timing Diagram ........................................................... 14-11
Memory Controller and External Bus Clocks Timing
Diagram for EBDF=0 and EBDF=1 .............................................................................. 14-11
Memory Controller and External Bus Clocks Timing
Diagram for (CSRC=0 and DFNH=1) or (CSRC=1 and DFNL=0) .............................. 14-12
BRGCLK Divider ............................................................................................................... 14-13
SYNCCLK Divider............................................................................................................. 14-14
MPC885 Power Rails.......................................................................................................... 14-15
System Clock and Reset Control Register (SCCR) ............................................................ 14-18
PLL and Reset Control Register (PLPRCR)....................................................................... 14-21
Memory Controller Block Diagram ..................................................................................... 15-3
Memory Controller Machine Selection................................................................................. 15-4
Simple System Configuration ............................................................................................... 15-5
Basic Memory Controller Operation..................................................................................... 15-6
Base Registers (BRx) ............................................................................................................ 15-9
BR0 Reset Defaults ............................................................................................................... 15-9
Option Registers (ORx) ...................................................................................................... 15-11
OR0 Reset Defaults............................................................................................................. 15-11
Memory Status Register (MSTAT) ..................................................................................... 15-13
Machine A Mode Register/Machine B Mode Register (MxMR) ....................................... 15-14
Memory Command Register (MCR) .................................................................................. 15-16
Memory Data Register (MDR) ........................................................................................... 15-17
Memory Address Register (MAR)...................................................................................... 15-17
Memory Periodic Timer Prescaler Register (MPTPR) ....................................................... 15-18
MPC885 PowerQUICC Family Reference Manual, Rev. 2
lii
Freescale Semiconductor
Figures
Figure
Number
15-15
15-16
15-17
15-18
15-19
15-20
15-21
15-22
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15-24
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15-46
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15-48
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15-50
15-51
15-52
15-53
Title
Page
Number
GPCM-to-SRAM Configuration......................................................................................... 15-19
GPCM Peripheral Device Interface .................................................................................... 15-21
GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0) ................................. 15-21
GPCM Memory Device Interface ....................................................................................... 15-22
GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0)....................... 15-22
GPCM Memory Device Basic Timing (ACS ≠ 00, CSNT = 1, TRLX = 0)....................... 15-23
GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1) .................... 15-23
GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1) ................... 15-24
GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 1, TRLX =1) .................... 15-25
GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX =1) .................... 15-25
GPCM Read Followed by Write (EHTR = 0)..................................................................... 15-26
GPCM Read Followed by Write (EHTR = 1)..................................................................... 15-27
GPCM Read Followed by Read from Different Banks (EHTR = 1) .................................. 15-28
GPCM Read Followed by Read from Same Bank (EHTR = 1) ......................................... 15-29
Asynchronous External Master Configuration for
GPCM-Handled Memory Devices ................................................................................. 15-30
Asynchronous External Master, GPCM-Handled
Memory Access Timing (TRLX = 0)............................................................................. 15-31
User-Programmable Machine Block Diagram.................................................................... 15-32
RAM Array Indexing .......................................................................................................... 15-33
Memory Periodic Timer Request Block Diagram .............................................................. 15-34
UPM Clock Scheme One (Division Factor = 1) ................................................................. 15-35
UPM Clock Scheme Two (Division Factor = 2)................................................................. 15-35
UPM Signals Timing Example One (Division Factor = 1, EBDF = 00) ............................ 15-36
UPM Signals Timing Example Two (Division Factor = 2, EBDF = 01) ............................ 15-37
RAM Array and Signal Generation .................................................................................... 15-37
The RAM Word................................................................................................................... 15-38
CSx Signal Selection........................................................................................................... 15-42
BSx Signal Selection........................................................................................................... 15-42
Early GPL5 Control ............................................................................................................ 15-44
Address Multiplex Timing .................................................................................................. 15-47
UPM Read Access Data Sampling...................................................................................... 15-52
Wait Mechanism Timing for Internal and External Synchronous Masters ......................... 15-53
Wait Mechanism Timing for an External Asynchronous Master........................................ 15-54
Synchronous External Master Access................................................................................. 15-57
Asynchronous External Master Access............................................................................... 15-58
Synchronous External Master Interconnect Example ......................................................... 15-59
Synchronous External Master: Burst Read Access to Page Mode DRAM......................... 15-60
Asynchronous External Master Interconnect Example....................................................... 15-61
Asynchronous External Master Timing Example ............................................................... 15-62
Page-Mode DRAM Interface Connection........................................................................... 15-63
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
liii
Figures
Figure
Number
15-54
15-55
15-56
15-57
15-58
15-59
15-60
15-61
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15-63
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17-5
17-6
Title
Page
Number
Single-Beat Read Access to Page-Mode DRAM................................................................ 15-65
Single-Beat Write Access to Page Mode DRAM ............................................................... 15-66
Burst Read Access to Page-Mode DRAM (No LOOP) ...................................................... 15-67
Burst Read Access to Page-Mode DRAM (LOOP)............................................................ 15-68
Burst Write Access to Page-Mode DRAM (No LOOP) ..................................................... 15-69
Burst Write Access to Page-Mode DRAM (LOOP) ........................................................... 15-70
Refresh Cycle (CAS before RAS) to Page-Mode DRAM .................................................. 15-71
Exception Cycle .................................................................................................................. 15-72
Optimized DRAM Burst Read Access................................................................................ 15-73
EDO DRAM Interface Connection..................................................................................... 15-74
EDO DRAM Single-Beat Read Access .............................................................................. 15-76
EDO DRAM Single-Beat Write Access ............................................................................. 15-77
EDO DRAM Burst Read Access ........................................................................................ 15-78
EDO DRAM Burst Write Access........................................................................................ 15-79
EDO DRAM Refresh Cycle (CAS before RAS) ................................................................ 15-80
EDO DRAM Exception Cycle............................................................................................ 15-81
Blank Work Sheet for a UPM ............................................................................................. 15-82
System with Two PCMCIA Sockets ..................................................................................... 16-2
Internal DMA Request Logic................................................................................................ 16-8
PCMCIA Interface Input Pins Register (PIPR) .................................................................... 16-9
PCMCIA Interface Status Changed Register (PSCR) ........................................................ 16-10
PCMCIA Interface Enable Register (PER)......................................................................... 16-11
PCMCIA Interface General Control Register (PGCRx)..................................................... 16-13
PCMCIA Base Register (PBR) ........................................................................................... 16-14
PCMCIA Option Register 0–7 (POR0–POR7)................................................................... 16-14
PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 1 ........................ 16-17
PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 2 PSL = 4 PSHT = 1 ........................ 16-18
PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 0 ........................ 16-19
PCMCIA Single-Beat Write Cycle PRS = 2 PSST = 1 PSL = 3 PSHT = 1 ....................... 16-20
PCMCIA Single-Beat Write Cycle PRS = 3 PSST = 1 PSL = 4 PSHT = 3 ....................... 16-21
PCMCIA Single-Beat Write with Wait PRS = 3 PSST = 1 PSL = 3 PSHT = 0 ................. 16-22
PCMCIA Single-Beat Read with Wait PRS = 3 PSST = 1 PSL = 3 PSHT = 1.................. 16-23
PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0 ................................. 16-24
PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0 .................................. 16-25
PCMCIA DMA Read Cycle PRS = 4 PSST = 1 PSL = 3 PSHT = 0.................................. 16-26
CPM Block Diagram............................................................................................................. 17-2
MPC885 Application Design Example................................................................................. 17-4
CPM Timer Block Diagram .................................................................................................. 17-5
Timer Cascaded Mode Block Diagram................................................................................. 17-7
Timer Global Configuration Register (TGCR) ..................................................................... 17-8
Timer Mode Registers (TMR1–TMR4)................................................................................ 17-9
MPC885 PowerQUICC Family Reference Manual, Rev. 2
liv
Freescale Semiconductor
Figures
Figure
Number
17-7
17-8
17-9
17-10
18-1
18-2
18-3
18-4
18-5
18-6
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20-8
20-9
20-10
20-11
20-12
Title
Page
Number
Timer Reference Registers (TRR1–TRR4)......................................................................... 17-10
Timer Capture Registers (TCR1–TCR4) ............................................................................ 17-10
Timer Counter Registers (TCN1–TCN4)............................................................................ 17-10
Timer Event Registers (TER1–TER4) ................................................................................ 17-11
Communications Processor (CP) Block Diagram................................................................. 18-2
CPM Configuration Register (CPMCFG)............................................................................. 18-4
RISC Controller Configuration Register (RCCR) ................................................................ 18-5
RISC Microcode Development Support Control Register (RMDS)..................................... 18-7
CP Command Register (CPCR)............................................................................................ 18-7
Dual-Port RAM Block Diagram ......................................................................................... 18-11
Dual-Port RAM Memory Map............................................................................................ 18-12
RISC Timer Table RAM Usage .......................................................................................... 18-15
RISC Timer Command Register (TM_CMD) .................................................................... 18-16
RISC Timer Event Register (RTER)/Mask Register (RTMR)............................................ 18-17
MPC885 SDMA Data Paths ................................................................................................. 19-2
SDMA U-Bus Arbitration (Cycle Steal) ............................................................................... 19-4
SDMA Configuration Register (SDCR) ............................................................................... 19-4
SDMA Status Register (SDSR) ............................................................................................ 19-5
DMA Channel Mode Register (DCMR) ............................................................................... 19-8
IDMA Status Registers (IDSR1/IDSR2) .............................................................................. 19-9
IDMAx Channel’s BD Table............................................................................................... 19-10
IDMA Buffer Descriptor Structure ..................................................................................... 19-11
Function Code Registers—SFCR and DFCR ..................................................................... 19-12
SDACK Timing Diagram: Single-Address
Peripheral Write, Externally Generated TA ................................................................... 19-17
SDACK Timing Diagram: Single-Address
Peripheral Write, Internally Generated TA .................................................................... 19-17
SDACK Timing Diagram: Single-Address
Peripheral Read, Internally Generated TA ..................................................................... 19-18
MPC885 SI Block Diagram .................................................................................................. 20-2
Various Configurations of a TDM Channel .......................................................................... 20-5
Dual TDM Channel Example ............................................................................................... 20-6
Enabling Connections through the SI ................................................................................... 20-8
SI RAM Partitioning Using TDMa with Static Frames ........................................................ 20-9
SI RAM—Two TDMs with Static Frames.......................................................................... 20-10
SI RAM Dynamic Changes with TDMa and TDMb .......................................................... 20-11
SI RAM Partitioning Using TDMa with Dynamic Frames ................................................ 20-12
SI RAM Partitioning Using Two TDMs with Dynamic Frames......................................... 20-12
SIRAM Entry ...................................................................................................................... 20-13
Example Using SI RAMn[SWTR] ..................................................................................... 20-14
SI Global Mode Register (SIGMR) .................................................................................... 20-16
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
lv
Figures
Figure
Number
20-13
20-14
20-15
20-16
20-17
20-18
20-19
20-20
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20-22
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Title
Page
Number
SI Mode Register (SIMODE) ............................................................................................. 20-17
One Clock Delay from Sync to Data (xFSD = 01) ............................................................. 20-19
No Delay from Sync to Data (xFSD = 00).......................................................................... 20-19
Falling Edge (FE) Effect When CE = 1 and xFSD = 01..................................................... 20-20
Falling Edge (FE) Effect When CE = 0 and xFSD = 01..................................................... 20-20
Falling Edge (FE) Effect When CE = 1 and xFSD = 00..................................................... 20-21
Falling Edge (FE) Effect When CE = 0 and xFSD = 00..................................................... 20-22
SI Clock Route Register (SICR) ......................................................................................... 20-23
SI Command Register (SICMR) ......................................................................................... 20-24
SI Status Register (SISTR).................................................................................................. 20-24
SI RAM Pointer Register (SIRP) ........................................................................................ 20-26
Dual IDL Bus Application Example................................................................................... 20-27
ISDN Terminal Adaptor Using IDL.................................................................................... 20-28
IDL Bus Signals .................................................................................................................. 20-29
GCI Bus Signals.................................................................................................................. 20-31
Bank-of-Clocks Selection Logic for NMSI ........................................................................ 20-35
Baud Rate Generator (BRG) Block Diagram ..................................................................... 20-37
Baud Rate Generator Configuration Registers (BRGCn) ................................................... 20-38
SCC Block Diagram.............................................................................................................. 21-2
GSMR_H—General SCC Mode Register (High Order)....................................................... 21-4
GSMR_L—General SCC Mode Register (Low Order)........................................................ 21-6
Data Synchronization Register (DSR) ................................................................................ 21-10
Transmit-on-Demand Register (TODR) ............................................................................. 21-10
SCC Buffer Descriptors (BDs)............................................................................................ 21-12
SCCx Buffer Descriptor and Buffer Structure .................................................................... 21-12
Function Code Registers (RFCR and TFCR) ..................................................................... 21-15
Output Delay from RTS Asserted for Synchronous Protocols ........................................... 21-17
Output Delay from CTS Asserted for Synchronous Protocols ........................................... 21-18
CTS Lost in Synchronous Protocols ................................................................................... 21-19
Using CD to Control Synchronous Protocol Reception...................................................... 21-20
DPLL Receiver Block Diagram .......................................................................................... 21-21
DPLL Transmitter Block Diagram...................................................................................... 21-22
DPLL Encoding Examples.................................................................................................. 21-24
UART Character Format ....................................................................................................... 22-1
Two UART Multidrop Configurations.................................................................................. 22-7
Control Character Table, RCCM, and RCCR ....................................................................... 22-8
Transmit Out-of-Sequence Register (TOSEQ) ................................................................... 22-10
Data Synchronization Register (DSR) ................................................................................ 22-11
Protocol-Specific Mode Register for UART (PSMR) ........................................................ 22-13
SCC UART Receiving using RxBDs.................................................................................. 22-16
SCC UART RxBD .............................................................................................................. 22-17
MPC885 PowerQUICC Family Reference Manual, Rev. 2
lvi
Freescale Semiconductor
Figures
Figure
Number
22-9
22-10
22-11
22-12
23-1
23-2
23-3
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26-8
Title
Page
Number
SCC UART Transmit Buffer Descriptor (TxBD) ............................................................... 22-18
SCC UART Interrupt Event Example ................................................................................. 22-20
SCC UART Event Register (SCCE) and Mask Register (SCCM) ..................................... 22-20
SCC Status Register for UART Mode (SCCS) ................................................................... 22-22
HDLC Framing Structure...................................................................................................... 23-2
HDLC Address Recognition ................................................................................................. 23-4
HDLC Mode Register (PSMR)............................................................................................. 23-7
SCC HDLC Receive Buffer Descriptor (RxBD) .................................................................. 23-8
SCC HDLC Receiving using RxBDs.................................................................................. 23-10
SCC HDLC Transmit Buffer Descriptor (TxBD) ............................................................... 23-11
HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ........................................ 23-12
SCC HDLC Interrupt Event Example................................................................................. 23-13
SCC HDLC Status Register (SCCS)................................................................................... 23-14
Typical HDLC Bus Multimaster Configuration.................................................................. 23-17
Typical HDLC Bus Single-Master Configuration............................................................... 23-18
Detecting an HDLC Bus Collision...................................................................................... 23-19
Nonsymmetrical Tx Clock Duty Cycle for Increased Performance ................................... 23-19
HDLC Bus Transmission Line Configuration .................................................................... 23-20
Delayed RTS Mode............................................................................................................. 23-20
HDLC Bus TDM Transmission Line Configuration .......................................................... 23-21
LocalTalk Frame Format....................................................................................................... 24-1
Connecting the MPC885 to LocalTalk.................................................................................. 24-3
Asynchronous HDLC Frame Structure................................................................................. 25-2
Receive Flowchart................................................................................................................. 25-3
TXCTL_TBL/RXCTL_TBL ................................................................................................ 25-5
Asynchronous HDLC Event Register (SCCE)/Asynchronous HDLC Mask Register (SCCM) ..
25-8
SCC Status Register for Asynchronous HDLC Mode (SCCS)............................................. 25-9
Asynchronous HDLC Mode Register (PSMR)................................................................... 25-10
SCC Asynchronous HDLC RxBDs .................................................................................... 25-11
SCC Asynchronous HDLC TxBDs..................................................................................... 25-12
Serial Infrared (SIR) Link ................................................................................................... 25-14
UART and IR Frames ......................................................................................................... 25-15
Classes of BISYNC Frames.................................................................................................. 26-1
Control Character Table and RCCM..................................................................................... 26-6
BISYNC SYNC (BSYNC) ................................................................................................... 26-7
BISYNC DLE (BDLE) ......................................................................................................... 26-8
Protocol-Specific Mode Register for BISYNC (PSMR) .................................................... 26-10
SCC BISYNC RxBD .......................................................................................................... 26-11
SCC BISYNC TxBD .......................................................................................................... 26-13
BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) ................................. 26-15
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
lvii
Figures
Figure
Number
26-9
27-1
27-2
27-3
27-4
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27-6
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30-2
30-3
30-4
30-5
Title
Page
Number
SCC Status Registers (SCCS) ............................................................................................. 26-15
Ethernet Frame Structure ...................................................................................................... 27-1
Ethernet Block Diagram........................................................................................................ 27-2
Connecting the MPC885 to Ethernet .................................................................................... 27-5
Ethernet Address Recognition Flowchart ........................................................................... 27-12
Ethernet Mode Register (PSMR) ........................................................................................ 27-15
SCC Ethernet RxBD ........................................................................................................... 27-16
Ethernet Receiving Using RxBDs....................................................................................... 27-18
SCC Ethernet TxBD............................................................................................................ 27-19
SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) ......................................... 27-20
Ethernet Interrupt Events Example ..................................................................................... 27-21
Sending Transparent Frames between MPC885 ................................................................... 28-4
SCC Transparent Receive Buffer Descriptor (RxBD) .......................................................... 28-8
SCC Transparent Transmit Buffer Descriptor (TxBD) ......................................................... 28-9
SCC Transparent Event Register (SCCE)/Mask Register (SCCM).................................... 28-11
SCC Status Register in Transparent Mode (SCCS) ............................................................ 28-12
SMC Block Diagram............................................................................................................. 29-1
SMC Mode Registers (SMCMRn)........................................................................................ 29-3
SMC Memory Structure........................................................................................................ 29-5
SMC Function Code Registers (RFCR/TFCR)..................................................................... 29-7
SMC UART Frame Format................................................................................................. 29-10
SMC UART Receive BD (RxBD) ...................................................................................... 29-14
SMC UART Receiving using RxBDs ................................................................................. 29-16
SMC UART Transmit BD (TxBD) ..................................................................................... 29-17
SMC UART Event Register (SMCE)/Mask Register (SMCM) ......................................... 29-18
SMC UART Interrupts Example......................................................................................... 29-19
Synchronization with SMSYNx.......................................................................................... 29-23
Synchronization with the TSA............................................................................................ 29-24
SMC Transparent Receive BD (RxBD) .............................................................................. 29-26
SMC Transparent Transmit BD (TxBD)............................................................................. 29-27
SMC Transparent Event Register (SMCE)/Mask Register (SMCM) ................................. 29-29
SMC GCI Monitor Channel RxBD..................................................................................... 29-33
SMC GCI Monitor Channel TxBD..................................................................................... 29-34
SMC C/I Channel RxBD..................................................................................................... 29-34
SMC C/I Channel TxBD..................................................................................................... 29-35
SMC GCI Event Register (SMCE)/Mask Register (SMCM) ............................................. 29-36
SPI Block Diagram ............................................................................................................... 30-1
Single-Master/Multi-Slave Configuration ............................................................................ 30-3
Multimaster Configuration.................................................................................................... 30-5
SPI Mode Register (SPMODE) ............................................................................................ 30-6
SPI Transfer Format with SPMODE[CP] = 0....................................................................... 30-7
MPC885 PowerQUICC Family Reference Manual, Rev. 2
lviii
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Figures
Figure
Number
30-6
30-7
30-8
30-9
30-10
30-11
30-12
31-1
31-2
31-3
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32-10
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32-12
32-13
Title
Page
Number
SPI Transfer Format with SPMODE[CP] = 1....................................................................... 30-7
SPI Event/Mask Registers (SPIE/SPIM) .............................................................................. 30-9
SPI Command Register (SPCOM)........................................................................................ 30-9
Receive/Transmit Function Code Registers (RFCR/TFCR)............................................... 30-11
SPI Memory Structure......................................................................................................... 30-12
SPI Receive BD (RxBD)..................................................................................................... 30-13
SPI Transmit BD (TxBD) ................................................................................................... 30-14
USB Interface........................................................................................................................ 31-3
USB Controller Block Diagram ........................................................................................... 31-5
USB Controller Operating Modes......................................................................................... 31-6
USB Controller (Host Mode)................................................................................................ 31-8
USB Controller Operating Modes......................................................................................... 31-9
SOF Generation................................................................................................................... 31-11
USB Parameter RAM Memory Map .................................................................................. 31-12
Endpoint Pointer Registers (EPxPTR) ................................................................................ 31-12
Frame Number (FRAME_N) in Function mode................................................................. 31-14
Frame Number (FRAME_N) in HOST mode..................................................................... 31-15
USB Function Code Registers (RFCR and TFCR)............................................................. 31-15
USB Mode Register (USMOD) .......................................................................................... 31-16
USB Slave Address Register (USADR) ............................................................................. 31-17
USB Endpoint Registers (USEP0–USEP3) ........................................................................ 31-18
USB Command Register (USCOM) ................................................................................... 31-19
USB Event Register (USBER)............................................................................................ 31-20
USB Status Register (USBS) .............................................................................................. 31-21
USB Memory Structure....................................................................................................... 31-22
USB Receive Buffer Descriptor (RxBD),........................................................................... 31-23
USB Transmit Buffer Descriptor (TxBD),.......................................................................... 31-25
USB Transmit Buffer Descriptor (TxBD),.......................................................................... 31-26
I2C Controller Block Diagram.............................................................................................. 32-1
I2C Master/Slave General Configuration ............................................................................. 32-2
I2C Transfer Timing.............................................................................................................. 32-3
I2C Master Write Timing...................................................................................................... 32-3
I2C Master Read Timing....................................................................................................... 32-4
I2C Mode Register (I2MOD) ................................................................................................ 32-6
I2C Address Register (I2ADD) ............................................................................................. 32-7
I2C Baud Rate Generator Register (I2BRG) ........................................................................ 32-7
I2C Event/Mask Registers (I2CER/I2CMR)......................................................................... 32-8
I2C Command Register (I2COM) ......................................................................................... 32-8
I2C Function Code Registers (RFCR/TFCR)...................................................................... 32-10
I2C Memory Structure......................................................................................................... 32-11
I2C Receive Buffer Descriptor (RxBD) .............................................................................. 32-12
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
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I2C Transmit Buffer Descriptor (TxBD)............................................................................. 32-13
PIP Block Diagram ............................................................................................................... 33-2
PIP Function Code Register (PFCR) .................................................................................... 33-4
Status Mask Register (SMASK) ........................................................................................... 33-4
Control Character Table, RCCM, and RCCR ....................................................................... 33-7
PIP Configuration Register (PIPC) ....................................................................................... 33-8
PIP Event Register (PIPE) .................................................................................................. 33-10
PIP Timing Parameters Register (PTPR) ............................................................................ 33-11
Port B General-Purpose I/O ................................................................................................ 33-11
PIP Tx Buffer Descriptor (TxBD)....................................................................................... 33-12
PIP Rx Buffer Descriptor (RxBD) ...................................................................................... 33-13
Interlocked Handshake Mode Timing................................................................................. 33-15
Pulsed Handshake Full Cycle ............................................................................................. 33-16
Pulsed Handshake BUSY Signal ........................................................................................ 33-17
PIP Transmitter Timing Diagram........................................................................................ 33-18
PIP Receiver Timing—Mode 0........................................................................................... 33-18
PIP Receiver Timing—Mode 1........................................................................................... 33-18
PIP Receiver Timing—Mode 2........................................................................................... 33-18
PIP Receiver Timing—Mode 3........................................................................................... 33-19
PIP Transparent Transfers ................................................................................................... 33-19
The PIP Centronics Interface Signals ................................................................................. 33-20
PIP as a Centronics Transmitter .......................................................................................... 33-21
PIP as a Centronics Receiver .............................................................................................. 33-22
Port A Open-Drain Register (PAODR)................................................................................. 34-4
Port A Data Register (PADAT) ............................................................................................. 34-4
Port A Data Direction Register (PADIR).............................................................................. 34-5
Port A Pin Assignment Register (PAPAR)............................................................................ 34-5
Block Diagram for PA15 (True for all Non-Open-Drain Port Signals) ................................ 34-6
Block Diagram for PA14 (True for all Open-Drain Port Signals) ........................................ 34-7
Port B Open-Drain Register (PBODR) ................................................................................. 34-9
Port B Data Register (PBDAT) ........................................................................................... 34-10
Port B Data Direction Register (PBDIR) ............................................................................ 34-10
Port B Pin Assignment Register (PBPAR).......................................................................... 34-11
Port C Data Register (PCDAT) ........................................................................................... 34-14
Port C Data Direction Register (PCDIR) ............................................................................ 34-15
Port C Pin Assignment Register (PCPAR).......................................................................... 34-15
Port C Special Options Register (PCSO) ............................................................................ 34-16
Port C Interrupt Control Register (PCINT)......................................................................... 34-17
Port D Data Register (PDDAT)........................................................................................... 34-19
Port D Data Direction Register (PDDIR) ........................................................................... 34-19
Port D Pin Assignment Register (PDPAR) ........................................................................ 34-20
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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Figures
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Number
34-19
34-20
34-21
34-22
34-23
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39-5
39-6
Title
Page
Number
Port E Open-Drain Register (PEODR) ............................................................................... 34-22
Port E Data Register (PEDAT)............................................................................................ 34-23
Port E Data Direction Register (PEDIR) ............................................................................ 34-23
Port E Pin Assignment Register (PEPAR) .......................................................................... 34-24
Port E Special Options Register (PESO) ............................................................................ 34-25
MPC885 Interrupt Structure.................................................................................................. 35-2
Interrupt Request Masking.................................................................................................... 35-5
CPM Interrupt Configuration Register (CICR) .................................................................... 35-7
CPM Interrupt Pending/Mask/In-Service Registers (CIPR/CIMR/CISR)............................ 35-8
CPM Interrupt Vector Register (CIVR) .............................................................................. 35-10
MPC885 Application Example ............................................................................................. 36-6
Expanded Cell Structure ....................................................................................................... 36-8
Example PTP Switching Application.................................................................................. 36-12
Transmit Buffer and TxBD Table Example .......................................................................... 37-2
AAL0 Buffer Structure.......................................................................................................... 37-3
ATM RxBD ........................................................................................................................... 37-3
ATM RxBD in Expanded Cell Mode (UTOPIA Only)......................................................... 37-4
ATM TxBD ........................................................................................................................... 37-7
ATM TxBD in Expanded Cell Mode (UTOPIA Only) ......................................................... 37-7
Connection Tables in Dual-port RAM and External Memory ............................................ 37-11
Receive Connection Table (RCT) ....................................................................................... 37-12
PTP Receive Connection Table (PTP RCT)........................................................................ 37-16
Transmit Connection Table (TCT)...................................................................................... 37-20
PTP Transmit Connection Table (PTP TCT)....................................................................... 37-24
TCTE Examples for Internal and External VBR/UBR Channels ....................................... 37-28
Transmit Connection Table Extension (TCTE) .................................................................. 37-28
SAR Receive Function Code Register (SRFCR) .................................................................. 38-8
SAR Receive State Register (SRSTATE).............................................................................. 38-9
SAR Transmit Function Code Register (STFCR)............................................................... 38-10
SAR Transmit State Register (STSTATE) .......................................................................... 38-11
HMASK .............................................................................................................................. 38-12
FLMASK ............................................................................................................................ 38-13
APC State Register (APCST).............................................................................................. 38-14
MPHY State Register (MPHYST) ...................................................................................... 38-15
ASTATUS ........................................................................................................................... 38-16
Address Mapping Tables for Internal Channels.................................................................... 39-2
Address Compression Example ............................................................................................ 39-4
Management Cell Filtering ................................................................................................... 39-6
Performance Monitoring Cell Structure (FMCs and BRCs)................................................. 39-8
FMC Template .................................................................................................................... 39-10
Function-specific Fields of FMCs, Terminated Cells and Optional BRCs......................... 39-10
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
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Figures
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39-7
39-8
39-9
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44-12
Title
Page
Number
Example FMC to BRC Turn-around................................................................................... 39-11
PM Table ............................................................................................................................. 39-12
Host-controlled Switching Serial ATM to a UTOPIA Channel.......................................... 39-15
PTP Switching Serial ATM to a UTOPIA Channel ............................................................ 39-16
PTP Buffer Descriptor......................................................................................................... 39-17
Statistics Table .................................................................................................................... 39-19
Address Mapping Tables for Internal Channels in Multi-PHY Operation ......................... 39-20
CP Command Register (CPCR) (ATM-Specific) ............................................................... 39-22
APC in UTOPIA Mode—Transmit Flow ............................................................................. 40-2
APC Control: PTP Queue and Scheduling Table Combination ............................................ 40-3
MPC885 VBR Credit Mechanism ........................................................................................ 40-8
Example of Single PHY and Single Serial APC Configuration ......................................... 40-11
Example of Maximum Multi-PHY and Multi-Serial APC Configuration.......................... 40-11
APC Scheduling Tables....................................................................................................... 40-13
PHY Transmit Queue .......................................................................................................... 40-14
MPHY Pointing Table and APC Priority Levels ................................................................ 40-15
Example of Three APC Priority Levels Combining
APC Scheduling Tables and APC PTP queues .............................................................. 40-21
ATM Interrupt Queue............................................................................................................ 41-1
UTOPIA Event Register (IDSR1) and Mask Register (IDMR1).......................................... 41-2
Serial ATM Event Register (SCCE) and Mask Register (SCCM)........................................ 41-3
Interrupt Queue Entry ........................................................................................................... 41-4
Interrupt Queue Mask (IMASK)........................................................................................... 41-6
Port D Pin Assignment Register (PDPAR) ........................................................................... 42-1
System Clock Control Register (SCCR) ............................................................................... 42-3
Serial ATM Mode Register (PSMR) ..................................................................................... 42-8
UTOPIA mode register (UTMODE) .................................................................................... 43-2
UTOPIA Slave Interface with Split Bus ............................................................................... 43-6
UTOPIA Master Interface with Muxed Bus ......................................................................... 43-7
Transmit Packet Descriptor (TPD)........................................................................................ 44-6
AAL2_Tx_Queue Example .................................................................................................. 44-7
AAL2 Transmit Connection Table........................................................................................ 44-8
Example of the Transmit Data Flow of an AAL2 Channel................................................. 44-10
Example of the Wait Table .................................................................................................. 44-13
Receive Packet Descriptor (RPD)....................................................................................... 44-14
AAL2_Rx_Queue Example ................................................................................................ 44-16
AAL2 Receive Connection Table ....................................................................................... 44-17
Example of the Receive Data Flow of an AAL2 Channel .................................................. 44-19
AAL2 Parameter RAM ....................................................................................................... 44-21
Example Using the External CT Pointer Table to Allocate AAL2 CTs.............................. 44-24
AAL2-Specific Exception Entry Format ............................................................................ 44-25
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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Number
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48-11
Title
Page
Number
FEC Block Diagrams ............................................................................................................ 45-2
Ethernet Address Recognition Flowchart ............................................................................. 45-7
SDMA Bus Arbitration ....................................................................................................... 45-10
CPTR Register..................................................................................................................... 45-11
ADDR_LOW Register........................................................................................................ 45-13
ADDR_HIGH Register ....................................................................................................... 45-14
HASH_TABLE_HIGH Register ......................................................................................... 45-15
HASH_TABLE_LOW Register.......................................................................................... 45-15
R_DES_START Register .................................................................................................... 45-16
X_DES_START Register.................................................................................................... 45-17
R_BUFF_SIZE Register ..................................................................................................... 45-18
ECNTRL Register............................................................................................................... 45-18
I_EVENT/I_MASK Registers ............................................................................................ 45-19
IVEC Register ..................................................................................................................... 45-20
R_DES_ACTIVE Register ................................................................................................. 45-21
X_DES_ACTIVE Register ................................................................................................. 45-22
MII_DATA Register............................................................................................................ 45-23
MII_SPEED Register .......................................................................................................... 45-24
R_BOUND Register ........................................................................................................... 45-26
R_FSTART Register ........................................................................................................... 45-27
X_WMRK Register............................................................................................................. 45-27
X_FSTART Register ........................................................................................................... 45-28
FUN_CODE Register ......................................................................................................... 45-29
R_CNTRL Register............................................................................................................. 45-30
R_HASH Register............................................................................................................... 45-31
X_CNTRL Register ............................................................................................................ 45-32
Receive Buffer Descriptor (RxBD)..................................................................................... 45-35
Transmit Buffer Descriptor (TxBD) ................................................................................... 45-37
SEC Lite Connected to the MPC885 Internal Bus................................................................ 46-2
SEC Lite Functional Blocks.................................................................................................. 46-3
DEU Mode Register.............................................................................................................. 48-3
DEU Key Size Register......................................................................................................... 48-4
DEU Data Size Register........................................................................................................ 48-5
DEU Reset Control Register ................................................................................................. 48-5
DEU Status Register ............................................................................................................. 48-6
DEU Interrupt Status Register .............................................................................................. 48-8
DEU Interrupt Control Register .......................................................................................... 48-10
DEU EU_GO Register ........................................................................................................ 48-12
MDEU Mode Register ........................................................................................................ 48-13
MDEU Key Size Register ................................................................................................... 48-15
MDEU Data Size Register .................................................................................................. 48-16
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
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Figure
Number
48-12
48-13
48-14
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48-16
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Number
MDEU Reset Control Register ........................................................................................... 48-16
MDEU Status Register........................................................................................................ 48-17
MDEU Interrupt Status Register ......................................................................................... 48-19
MDEU Interrupt Control Register ...................................................................................... 48-20
MDEU EU_GO Register .................................................................................................... 48-22
MDEU Context Register ..................................................................................................... 48-23
AESU Mode Register.......................................................................................................... 48-25
AESU Key Size Register .................................................................................................... 48-27
AESU Data Size Register ................................................................................................... 48-28
AESU Reset Control Register............................................................................................. 48-28
AESU Status Register ......................................................................................................... 48-29
AESU Interrupt Status Register .......................................................................................... 48-31
AESU Interrupt Control Register........................................................................................ 48-33
AESU End of Message Register ......................................................................................... 48-34
AESU Context Register ...................................................................................................... 48-35
Example Data Packet Descriptor .......................................................................................... 49-2
Descriptor Header ................................................................................................................. 49-2
OP_n sub fields ..................................................................................................................... 49-3
Descriptor Length Field ........................................................................................................ 49-5
Descriptor Pointer Field ........................................................................................................ 49-5
Next Descriptor Pointer Field ............................................................................................... 49-6
Chain of Descriptors ............................................................................................................. 49-7
Crypto-Channel Configuration Register ............................................................................... 50-2
Crypto-Channel Pointer Status Register 1 ............................................................................ 50-5
Crypto-Channel Pointer Status Register 2 ............................................................................ 50-5
Crypto-Channel Current Descriptor Pointer Register ......................................................... 50-10
Fetch Register ..................................................................................................................... 50-11
Data Packet Descriptor Buffer ............................................................................................ 50-12
Interrupt Mask Register 1 ..................................................................................................... 51-2
Interrupt Mask Register 2 ..................................................................................................... 51-2
Interrupt Status Register 1..................................................................................................... 51-3
Interrupt Status Register 2..................................................................................................... 51-3
Interrupt Clear Register 1...................................................................................................... 51-4
Interrupt Clear Register 2...................................................................................................... 51-5
ID Register ............................................................................................................................ 51-6
Master Control Register ........................................................................................................ 51-7
Master Error Address Register.............................................................................................. 51-7
CPTR Register....................................................................................................................... 52-1
Data Alignment Example...................................................................................................... 52-4
Watchpoints and Breakpoint Support in the Core................................................................. 53-8
Instruction Support General Structure ................................................................................ 53-11
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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Figures
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53-3
53-4
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A-1
A-2
A-3
E-1
F-1
G-1
H-1
H-2
H-3
Title
Page
Number
Load/Store Support General Structure ................................................................................ 53-12
Partially Supported Watchpoints/Breakpoint Example....................................................... 53-16
Functional Diagram of the MPC885 Debug Mode Support ............................................... 53-18
Debug Mode Logic Diagram .............................................................................................. 53-19
Debug Mode Reset Configuration Timing Diagram........................................................... 53-20
Development Port/BDM Connector Pinout Options .......................................................... 53-25
Asynchronous Clocked Serial Communications................................................................. 53-26
Synchronous Self-Clocked Serial Communications ........................................................... 53-27
Enabling Clock Mode after Reset ....................................................................................... 53-28
Download Procedure Code Example .................................................................................. 53-32
Fast and Slow Download Procedure Loops ........................................................................ 53-33
Comparator A–D Value Register (CMPA–CMPD) ............................................................ 53-35
Comparator E–F Value Registers (CMPE–CMPF)............................................................. 53-36
Comparator G–H Value Registers (CMPG–CMPH) .......................................................... 53-36
Breakpoint Address Register (BAR)................................................................................... 53-36
Instruction Support Control Register (ICTRL) ................................................................... 53-37
Load/Store Support Comparators Control Register (LCTRL1).......................................... 53-39
Load/Store Support AND-OR Control Register (LCTRL2) ............................................... 53-40
Breakpoint Counter Value and Control Registers (COUNTA/COUNTB) ......................... 53-42
Interrupt Cause Register (ICR) ........................................................................................... 53-43
Debug Enable Register (DER) ............................................................................................ 53-44
Test Logic Block Diagram .................................................................................................... 54-2
TAP Controller State Machine .............................................................................................. 54-3
Output Signal Boundary Scan Cell (Output Cell)................................................................. 54-4
Observe-Only Input Signal Boundary Scan Cell (Input Cell) .............................................. 54-4
Input/Output Control Boundary Scan Cell (I/O Control Cell).............................................. 54-5
Bidirectional (I/O) Signal Boundary Scan Cell .................................................................... 54-5
Bypass Register..................................................................................................................... 54-7
TLE Mode Mechanisms......................................................................................................... A-2
Byte Swapping ....................................................................................................................... A-3
PPC-LE Mode Mechanisms................................................................................................... A-6
MPC880 Block Diagram.........................................................................................................E-2
MPC875 Block Diagram......................................................................................................... F-2
MPC870 Block Diagram........................................................................................................ G-2
ATM Cell Payload Scrambling Mechanism........................................................................... H-1
Serial ATM Receive Procedure.............................................................................................. H-2
Cell Delineation State Diagram ............................................................................................. H-3
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
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Tables
Table
Number
1-1
2-1
2-2
3-1
3-2
3-3
3-4
3-5
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
Title
Page
Number
Tables
MPC885 Family ...................................................................................................................... 1-1
MPC885 Internal Memory Map (IMMR[14–15]=00) ............................................................ 2-1
Security Engine Memory Map (IMMR[14–15]=10) ............................................................ 2-14
Static Branch Prediction.......................................................................................................... 3-8
Bus Cycles Needed for Single-Register Load/Store Accesses ............................................. 3-12
UISA-Level Features ............................................................................................................ 3-14
VEA-Level Features ............................................................................................................. 3-16
OEA-Level Features ............................................................................................................. 3-17
User-Level PowerPC Registers............................................................................................... 4-2
MPC885-Specific User-Level SPRs ....................................................................................... 4-2
Bit Settings for CR0 Field of CR ............................................................................................ 4-3
XER Field Definitions ............................................................................................................ 4-4
Supervisor-Level PowerPC Registers ..................................................................................... 4-4
Supervisor-Level PowerPC SPRs ........................................................................................... 4-5
Value Summary of the DAR, BAR, and DSISR Registers ..................................................... 4-6
MSR Field Descriptions.......................................................................................................... 4-7
MPC885-Specific Supervisor-Level SPRs ............................................................................. 4-9
MPC885-Specific Debug-Level SPRs .................................................................................. 4-10
Addresses of SPRs Located Outside of the Core.................................................................. 4-11
Memory Operands................................................................................................................... 5-1
Integer Arithmetic Instructions ............................................................................................... 5-7
Integer Compare Instructions.................................................................................................. 5-9
Integer Logical Instructions .................................................................................................... 5-9
Integer Rotate Instructions .................................................................................................... 5-10
Integer Shift Instructions....................................................................................................... 5-10
Integer Load Instructions ...................................................................................................... 5-11
Integer Store Instructions ...................................................................................................... 5-12
Integer Load and Store with Byte-Reverse Instructions ...................................................... 5-13
Integer Load and Store Multiple Instructions ....................................................................... 5-13
Integer Load and Store String Instructions ........................................................................... 5-13
Branch Instructions ............................................................................................................... 5-15
Condition Register Logical Instructions ............................................................................... 5-15
Trap Instructions ................................................................................................................... 5-16
Move to/from Condition Register Instructions ..................................................................... 5-16
Memory Synchronization Instructions—UISA .................................................................... 5-16
Move from Time Base Instruction ........................................................................................ 5-18
Memory Synchronization Instructions—VEA...................................................................... 5-19
User-Level Cache Instructions.............................................................................................. 5-20
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Tables
Table
Number
5-20
5-21
5-22
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
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8-1
8-2
8-3
8-4
8-5
8-6
Title
Page
Number
System Linkage Instructions ................................................................................................. 5-20
Move to/from Machine State Register Instructions .............................................................. 5-21
Move to/from Special-Purpose Register Instructions ........................................................... 5-21
Offset of First Instruction by Exception Type......................................................................... 6-2
Instruction-Related Exception Detection Order...................................................................... 6-3
Exception Priority ................................................................................................................... 6-4
Register Settings After a System Reset Interrupt Exception .................................................. 6-5
Register Settings After a Machine Check Interrupt Exception............................................... 6-5
Register Settings after an External Interrupt........................................................................... 6-7
Register Settings after an Alignment Exception ..................................................................... 6-7
Register Settings After a Program Exception ......................................................................... 6-9
Register Settings after a Decrementer Exception ................................................................. 6-10
Register Settings After a System Call Exception.................................................................. 6-11
Register Settings After a Trace Exception ............................................................................ 6-11
Register Settings after a Software Emulation Exception ...................................................... 6-12
Register Settings After an Instruction TLB Miss Exception ................................................ 6-13
Register Settings After a Data TLB Miss Exception ............................................................ 6-13
Register Settings after an Instruction TLB Error Exception................................................. 6-14
Register Settings After a Data TLB Error Exception ........................................................... 6-14
Register Settings after a Debug Exception ........................................................................... 6-15
Additional SPRs that Affect MSR Bits................................................................................. 6-17
Exception Latency................................................................................................................ 6-19
Before and After Exceptions................................................................................................. 6-19
MPC885 Family ...................................................................................................................... 7-1
Instruction Cache Control and Status Register—IC_CST ...................................................... 7-7
Instruction Cache Address Register—IC_ADR ..................................................................... 7-8
Instruction Cache Data Port Register—IC_DAT ................................................................... 7-8
IC_ADR Fields for Cache Read Commands .......................................................................... 7-8
IC_DAT Format for a Tag Read (IC_ADR[17] = 0).............................................................. 7-9
Data Cache Control and Status Register—DC_CST ............................................................ 7-12
Data Cache Address Register—DC_ADR............................................................................ 7-13
Data Cache Data Port Register—DC_DAT .......................................................................... 7-14
DC_ADR Fields for Cache Read Commands....................................................................... 7-14
DC_DAT Format for a Tag Read (DC_ADR[18] = 0)......................................................... 7-14
Copyback Buffer Select Field (DC_ADR[20–27]) Encoding .............................................. 7-15
Identical Entries Required in Level-One/Level-Two Tables .................................................. 8-9
Number of Replaced EA Bits per Page Size......................................................................... 8-11
Level-One Segment Descriptor Format ................................................................................ 8-11
Level-Two (Page) Descriptor Format ................................................................................... 8-12
Page Size Selection ............................................................................................................... 8-13
MPC885-Specific MMU SPRs ............................................................................................. 8-13
MPC885 PowerQUICC Family Reference Manual, Rev. 2
lxviii
Freescale Semiconductor
Tables
Table
Number
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
8-20
8-21
8-22
8-23
9-1
9-2
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
10-17
10-18
10-19
10-20
10-21
10-22
Title
Page
Number
MI_CTR Field Descriptions.................................................................................................. 8-15
MD_CTR Field Descriptions ................................................................................................ 8-16
Mx_EPN Field Descriptions ................................................................................................. 8-17
MI_TWC Field Descriptions ................................................................................................ 8-17
MD_TWC Field Descriptions ............................................................................................... 8-19
MI_RPN Field Descriptions.................................................................................................. 8-20
MD_RPN Field Descriptions ................................................................................................ 8-21
M_TWB Field Descriptions.................................................................................................. 8-22
M_CASID Field Descriptions............................................................................................... 8-23
MI_AP/MD_AP Field Descriptions...................................................................................... 8-23
MI_CAM Field Descriptions ................................................................................................ 8-24
MI_RAM0 Field Descriptions .............................................................................................. 8-25
MI_RAM1 Field Descriptions .............................................................................................. 8-26
MD_CAM Field Descriptions............................................................................................... 8-27
MD_RAM0 Field Descriptions............................................................................................. 8-28
MD_RAM1 Field Descriptions............................................................................................. 8-29
MPC885-Specific MMU Exceptions .................................................................................... 8-31
Instruction Execution Timing ................................................................................................. 9-5
Load/Store Instruction Timing ................................................................................................ 9-7
Multiplexing Control............................................................................................................. 10-3
MMR Field Descriptions ...................................................................................................... 10-5
SIUMCR Field Descriptions ................................................................................................. 10-6
SYPCR Field Descriptions.................................................................................................... 10-8
TESR Field Descriptions ...................................................................................................... 10-9
Key Registers ........................................................................................................................ 10-9
Priority of SIU Interrupt Sources ........................................................................................ 10-13
IRQ0 Versus IRQx Operation ............................................................................................. 10-14
SIPEND Field Descriptions ................................................................................................ 10-15
SIMASK Field Descriptions ............................................................................................... 10-16
SIEL Field Descriptions...................................................................................................... 10-17
SIVEC Field Descriptions................................................................................................... 10-18
SWSR Field Descriptions ................................................................................................... 10-21
Decrementer Timeout Values .............................................................................................. 10-22
DEC Field Descriptions ...................................................................................................... 10-23
TBU Field Descriptions ...................................................................................................... 10-23
TBL Field Descriptions....................................................................................................... 10-24
TBREFA/TBREFB Field Descriptions ............................................................................... 10-24
TBSCR Field Descriptions.................................................................................................. 10-25
PISCR Field Descriptions ................................................................................................... 10-26
PITC Field Descriptions...................................................................................................... 10-27
PITR Field Descriptions...................................................................................................... 10-28
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
lxix
Tables
Table
Number
11-1
11-2
11-3
12-1
12-2
12-3
12-4
12-5
13-1
13-2
13-3
13-4
13-5
13-6
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
15-12
15-13
15-14
15-15
15-16
15-17
Title
Page
Number
MPC885 Reset Responses .................................................................................................... 11-1
Reset Status Register Bit Settings ......................................................................................... 11-5
Hard Reset Configuration Word Field Descriptions ............................................................. 11-8
MPC885/MPC880 Signal Descriptions ................................................................................ 12-4
MPC875/MPC870 Signal Descriptions .............................................................................. 12-26
Configuration-Dependent Signal Behavior During Reset .................................................. 12-40
Active Pull-Up Resistors Enabled as Outputs..................................................................... 12-41
General Signal Behavior During Reset ............................................................................... 12-44
MPC885 Signal Overview .................................................................................................... 13-3
Data Bus Requirements for Read Cycles............................................................................ 13-25
Data Bus Contents for Write Cycles ................................................................................... 13-25
BURST/TSIZ Encoding ...................................................................................................... 13-30
Address Types Definition.................................................................................................... 13-31
Termination Signals Protocol.............................................................................................. 13-41
The Input Frequency Requirements...................................................................................... 14-4
Typical System Frequency Generation ................................................................................. 14-6
Power-On Reset DPLL Configuration .................................................................................. 14-7
Functionality Summary of the Clocks .................................................................................. 14-8
PITCLK Configuration at PORESET ................................................................................. 14-14
TMBCLK Configuration..................................................................................................... 14-15
MPC885 Modules vs. Power Rails ..................................................................................... 14-16
SCCR Field Descriptions .................................................................................................... 14-19
PLPRCR Field Descriptions ............................................................................................... 14-21
PLPRCR[CSR] and DER[CHSTPE] Bit Combinations ..................................................... 14-23
Memory Controller Register Usage ...................................................................................... 15-6
Access Granularities for Predefined Port Sizes .................................................................... 15-7
BRx Field Descriptions....................................................................................................... 15-10
ORx Field Descriptions....................................................................................................... 15-12
MSTAT Field Descriptions ................................................................................................. 15-13
MxMR Field Descriptions .................................................................................................. 15-14
MCR Field Descriptions ..................................................................................................... 15-16
MDR Field Descriptions ..................................................................................................... 15-17
MAR Field Description....................................................................................................... 15-18
MPTPR Field Descriptions ................................................................................................. 15-18
GPCM Strobe Signal Behavior ........................................................................................... 15-19
Boot Bank Field Values After Reset ................................................................................... 15-30
UPM Start Address Locations............................................................................................. 15-38
RAM Word Bit Settings ...................................................................................................... 15-38
Enabling Byte-Selects ......................................................................................................... 15-43
GPL_x5 Signal Behavior .................................................................................................... 15-44
MxMR Loop Field Usage ................................................................................................... 15-45
MPC885 PowerQUICC Family Reference Manual, Rev. 2
lxx
Freescale Semiconductor
Tables
Table
Number
15-18
15-19
15-20
15-21
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
16-10
16-11
16-12
16-13
17-1
17-2
17-3
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
19-1
19-2
19-3
19-4
19-5
19-6
19-7
Title
Page
Number
Address Multiplexing.......................................................................................................... 15-47
AMA/AMB Definition for DRAM Interface...................................................................... 15-48
UPMA Register Settings ..................................................................................................... 15-64
UPMB Register Settings ..................................................................................................... 15-75
PCMCIA Cycle Control Signals ........................................................................................... 16-3
PCMCIA Input Port Signals ................................................................................................. 16-4
PCMCIA Output Port Signals............................................................................................... 16-5
Other PCMCIA Signals ........................................................................................................ 16-5
Host Programming for Memory Cards ................................................................................. 16-6
Host Programming For I/O Cards ......................................................................................... 16-6
PCMCIA Registers ............................................................................................................... 16-8
PIPR Field Descriptions........................................................................................................ 16-9
PSCR Field Descriptions .................................................................................................... 16-10
PER Field Descriptions ....................................................................................................... 16-12
PGCRx Field Descriptions.................................................................................................. 16-13
PBR Field Descriptions....................................................................................................... 16-14
POR Field Descriptions ...................................................................................................... 16-15
TGCR Field Descriptions..................................................................................................... 17-8
TMR1–TMR4 Field Descriptions ......................................................................................... 17-9
TER Field Descriptions...................................................................................................... 17-11
Peripheral Prioritization ........................................................................................................ 18-3
CP Microcode Revision Number .......................................................................................... 18-4
CPM Configuration Register (CPMCFG) Bit Settings......................................................... 18-5
RCCR Field Descriptions...................................................................................................... 18-5
RMDS Field Descriptions ..................................................................................................... 18-7
CPCR Field Descriptions ...................................................................................................... 18-8
CP Command Opcodes ......................................................................................................... 18-8
CP Commands....................................................................................................................... 18-9
General BD Structure .......................................................................................................... 18-13
Parameter RAM Memory Map .......................................................................................... 18-13
I2C and SPI Parameter RAM Relocation............................................................................ 18-14
RISC Timer Table Parameter RAM Memory Map ............................................................. 18-16
TM_CMD Field Descriptions ............................................................................................. 18-16
PWM Channel Pin Assignments......................................................................................... 18-18
U-Bus Arbitration IDs........................................................................................................... 19-3
SDCR Bit Settings ................................................................................................................ 19-5
SDSR Field Descriptions ...................................................................................................... 19-5
IDMA Parameter RAM Memory Map.................................................................................. 19-7
DCMR Field Descriptions .................................................................................................... 19-8
IDSR1/IDSR2 Field Descriptions ......................................................................................... 19-9
IDMA BD Status and Control Bits ..................................................................................... 19-11
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
lxxi
Tables
Table
Number
19-8
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
21-9
22-1
22-2
22-3
22-4
22-5
22-6
22-7
22-8
22-9
22-10
22-11
22-12
22-13
22-14
23-1
23-2
23-3
Title
Page
Number
SFCR and DFCR Field Descriptions ................................................................................. 19-12
TSA Signals .......................................................................................................................... 20-7
SIRAM Field Descriptions.................................................................................................. 20-13
Example SI RAM Entry Settings for an IDL Bus............................................................... 20-15
SIGMR Field Descriptions.................................................................................................. 20-16
SIMODE Field Descriptions ............................................................................................... 20-17
SICR Field Descriptions ..................................................................................................... 20-23
SICMR Field Descriptions.................................................................................................. 20-24
SISTR Field Descriptions ................................................................................................... 20-25
SIRP Field Descriptions...................................................................................................... 20-26
SIRP Pointer Values ........................................................................................................... 20-26
SI RAM Settings for IDL Interface..................................................................................... 20-30
SI RAM Settings for GCI Interface (SCIT Mode).............................................................. 20-33
BRGCn Field Descriptions ................................................................................................. 20-38
Typical Baud Rates for Asynchronous Communication..................................................... 20-40
MPC885 Family .................................................................................................................... 21-1
GSMR_H Field Descriptions ................................................................................................ 21-4
GSMR_L Field Descriptions ................................................................................................ 21-7
TODR Field Descriptions ................................................................................................... 21-11
SCC Parameter RAM Map for All Protocols...................................................................... 21-13
RFCRx /TFCRx Field Descriptions.................................................................................... 21-15
SCCx Event, Mask, and Status Registers ........................................................................... 21-16
Preamble Requirements ...................................................................................................... 21-23
DPLL Codings .................................................................................................................... 21-24
UART-Specific SCC Parameter RAM Memory Map ........................................................... 22-4
Transmit Commands ............................................................................................................. 22-6
Receive Commands............................................................................................................... 22-6
Control Character Table, RCCM, and RCCR Descriptions.................................................. 22-8
TOSEQ Field Descriptions ................................................................................................. 22-10
DSR Fields Descriptions ..................................................................................................... 22-11
Transmission Errors ............................................................................................................ 22-12
Reception Errors ................................................................................................................. 22-12
PSMR UART Field Descriptions........................................................................................ 22-13
SCC UART RxBD Status and Control Field Descriptions ................................................. 22-17
SCC UART TxBD Status and Control Field Descriptions ................................................. 22-18
SCCE/SCCM Field Descriptions for UART Mode ............................................................ 22-21
UART SCCS Field Descriptions......................................................................................... 22-22
UART Control Characters for S-Records Example ............................................................ 22-24
HDLC-Specific SCC Parameter RAM Memory Map .......................................................... 23-3
Transmit Commands ............................................................................................................. 23-5
Receive Commands .............................................................................................................. 23-5
MPC885 PowerQUICC Family Reference Manual, Rev. 2
lxxii
Freescale Semiconductor
Tables
Table
Number
23-4
23-5
23-6
23-7
23-8
23-9
23-10
25-1
25-2
25-3
25-4
25-5
25-6
25-7
25-8
25-9
25-10
25-11
26-1
26-2
26-3
26-4
26-5
26-6
26-7
26-8
26-9
26-10
26-11
26-12
26-13
26-14
26-15
27-1
27-2
27-3
27-4
27-5
27-6
Title
Page
Number
Transmit Errors ................................................................................................................... 23-6
Receive Errors....................................................................................................................... 23-6
PSMR HDLC Field Descriptions.......................................................................................... 23-7
SCC HDLC RxBD Status and Control Field Descriptions................................................... 23-9
SCC HDLC TxBD Status and Control Field Descriptions ................................................. 23-11
SCCE/SCCM Field Descriptions ........................................................................................ 23-12
HDLC SCCS Field Descriptions......................................................................................... 23-14
Asynchronous HDLC-Specific SCC Parameter RAM Memory Map .................................. 25-5
Asynchronous HDLC-Specific GSMR Field Descriptions .................................................. 25-6
Transmit Commands ............................................................................................................. 25-7
Receive Commands.............................................................................................................. 25-7
Transmit Errors ..................................................................................................................... 25-7
Receive Errors....................................................................................................................... 25-8
SCCE/SCCM Field Descriptions .......................................................................................... 25-9
Asynchronous HDLC SCCS Field Descriptions ................................................................ 25-10
PSMR Field Descriptions.................................................................................................... 25-10
Asynchronous HDLC RxBD Status
and Control Field Descriptions ...................................................................................... 25-11
Asynchronous HDLC TxBD Status
and Control Field Descriptions ...................................................................................... 25-12
SCC BISYNC Parameter RAM Memory Map ..................................................................... 26-3
Transmit Commands ............................................................................................................. 26-5
Receive Commands............................................................................................................... 26-5
Control Character Table and RCCM Field Descriptions ...................................................... 26-7
BSYNC Field Descriptions ................................................................................................... 26-8
BDLE Field Descriptions...................................................................................................... 26-8
Receiver SYNC Pattern Lengths of the DSR........................................................................ 26-9
Transmit Errors ..................................................................................................................... 26-9
Receive Errors....................................................................................................................... 26-9
PSMR Field Descriptions.................................................................................................... 26-10
SCC BISYNC RxBD Status and Control Field Descriptions ............................................. 26-12
SCC BISYNC TxBD Status and Control Field Descriptions ............................................. 26-13
SCCE/SCCM Field Descriptions ........................................................................................ 26-15
SCCS Field Descriptions .................................................................................................... 26-16
Control Characters .............................................................................................................. 26-16
MPC885 Family .................................................................................................................... 27-1
SCC Ethernet Parameter RAM Memory Map ...................................................................... 27-8
Transmit Commands ........................................................................................................... 27-10
Receive Commands............................................................................................................. 27-11
Transmission Errors ............................................................................................................ 27-14
Reception Errors ................................................................................................................. 27-14
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
lxxiii
Tables
Table
Number
27-7
27-8
27-9
27-10
28-1
28-2
28-3
28-4
28-5
28-6
28-7
28-8
28-9
28-10
29-1
29-2
29-3
29-4
29-5
29-6
29-7
29-8
29-9
29-10
29-11
29-12
29-13
29-14
29-15
29-16
29-17
29-18
29-19
29-20
29-21
29-22
29-23
30-1
30-2
30-3
30-4
Title
Page
Number
PSMR Field Descriptions.................................................................................................... 27-15
SCC Ethernet RxBD Status and Control Field Descriptions .............................................. 27-17
SCC Ethernet TxBD Status and Control Field Descriptions .............................................. 27-19
SCCE/SCCM Field Descriptions ........................................................................................ 27-20
Receiver SYNC Pattern Lengths of the DSR........................................................................ 28-3
SCC Transparent Parameter RAM Memory Map................................................................. 28-6
Transmit Commands ............................................................................................................. 28-6
Receive Commands............................................................................................................... 28-7
Transmit Errors ..................................................................................................................... 28-7
Receive Errors....................................................................................................................... 28-7
SCC Transparent RxBD Status and Control Field Descriptions........................................... 28-8
SCC Transparent Tx BD Status and Control Field Descriptions ........................................ 28-10
SCCE/SCCM Field Descriptions ........................................................................................ 28-11
SCCS Field Descriptions .................................................................................................... 28-12
SMCMR Field Descriptions.................................................................................................. 29-3
SMC UART and Transparent Parameter RAM Memory Map ............................................ 29-6
RFCR/TFCR Field Descriptions ........................................................................................... 29-7
SMC UART-Specific Parameter RAM Memory Map ........................................................ 29-10
Transmit Commands ........................................................................................................... 29-12
Receive Commands............................................................................................................. 29-12
SMC UART Errors.............................................................................................................. 29-13
SMC UART RxBD Status and Control Field Descriptions ................................................ 29-14
SMC UART TxBD Status and Control Field Descriptions ................................................ 29-17
SMCE/SMCM Field Descriptions ...................................................................................... 29-18
SMC Transparent Transmit Commands.............................................................................. 29-25
SMC Transparent Receive Commands ............................................................................... 29-25
SMC Transparent Error Conditions .................................................................................... 29-26
SMC Transparent RxBD Field Descriptions....................................................................... 29-26
SMC Transparent TxBD Field Descriptions....................................................................... 29-28
SMCE/SMCM Field Descriptions ...................................................................................... 29-29
SMC GCI Parameter RAM Memory Map ......................................................................... 29-31
SMC GCI Commands ......................................................................................................... 29-33
SMC Monitor Channel RxBD Field Descriptions .............................................................. 29-33
SMC Monitor Channel TxBD Field Descriptions .............................................................. 29-34
SMC C/I Channel RxBD Field Descriptions ...................................................................... 29-35
SMC C/I Channel TxBD Field Descriptions ...................................................................... 29-35
SMCE/SMCM Field Descriptions ...................................................................................... 29-36
SPMODE Field Descriptions ................................................................................................ 30-6
Example Conventions ........................................................................................................... 30-8
SPIE/SPIM Field Descriptions.............................................................................................. 30-9
SPCOM Field Descriptions................................................................................................... 30-9
MPC885 PowerQUICC Family Reference Manual, Rev. 2
lxxiv
Freescale Semiconductor
Tables
Table
Number
30-5
30-6
30-7
30-8
30-9
31-1
31-2
31-3
31-4
31-5
31-6
31-7
31-8
31-9
31-10
31-11
31-12
31-13
31-14
31-15
31-16
31-17
31-18
32-1
32-2
32-3
32-4
32-5
32-6
32-7
32-8
32-9
32-10
33-1
33-2
33-3
33-4
33-5
33-6
33-7
33-8
Title
Page
Number
SPI Parameter RAM Memory Map .................................................................................... 30-10
RFCR/TFCR Field Descriptions ......................................................................................... 30-11
SPI Commands.................................................................................................................... 30-12
SPI RxBD Status and Control Field Descriptions............................................................... 30-13
SPI TxBD Status and Control Field Descriptions............................................................... 30-15
USB Pins Functions .............................................................................................................. 31-3
USB Tokens .......................................................................................................................... 31-6
USB Tokens (Host Mode)................................................................................................... 31-10
Endpoint Parameter Block .................................................................................................. 31-13
FRAME_N Field Descriptions............................................................................................ 31-14
FRAME_N in Host Mode Field Descriptions..................................................................... 31-15
RFCR and TFCR Fields...................................................................................................... 31-16
USMOD Fields ................................................................................................................... 31-17
USADR Fields .................................................................................................................... 31-17
USEPx Fields ...................................................................................................................... 31-18
USCOM Fields.................................................................................................................... 31-19
USBER Fields ..................................................................................................................... 31-20
USBS Fields ........................................................................................................................ 31-21
USB RxBD Fields ............................................................................................................... 31-23
USB Function TxBD Fields................................................................................................ 31-25
USB Host TxBD Fields....................................................................................................... 31-27
USB Controller Transmission Errors .................................................................................. 31-29
USB Controller Reception Errors ....................................................................................... 31-29
I2MOD Field Descriptions.................................................................................................... 32-6
I2ADD Field Descriptions .................................................................................................... 32-7
I2BRG Field Descriptions..................................................................................................... 32-7
I2CER/I2CMR Field Descriptions........................................................................................ 32-8
I2COM Field Descriptions.................................................................................................... 32-8
I2C Parameter RAM Memory Map ...................................................................................... 32-9
RFCR/TFCR Field Descriptions ......................................................................................... 32-10
I2C Transmit/Receive Commands....................................................................................... 32-11
I2C RxBD Status and Control Bits...................................................................................... 32-12
I2C TxBD Status and Control Bits...................................................................................... 32-13
PIP Transmitter Parameter RAM Memory Map ................................................................... 33-3
PFCR Field Descriptions ...................................................................................................... 33-4
SMASK Field Descriptions .................................................................................................. 33-5
PIP Receiver Parameter RAM Memory Map ....................................................................... 33-5
Control Character Table, RCCM, and RCCR Descriptions.................................................. 33-7
PIPC Field Descriptions........................................................................................................ 33-8
PIPE Field Descriptions ...................................................................................................... 33-10
PTPR Field Descriptions ..................................................................................................... 33-11
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
lxxv
Tables
Table
Number
33-9
33-10
33-11
33-12
33-13
33-14
34-1
34-2
34-3
34-4
34-5
34-6
34-7
34-8
34-9
34-10
34-11
34-12
34-13
34-14
34-15
34-16
34-17
34-18
34-19
34-20
34-21
34-22
34-23
34-24
34-25
34-26
34-27
35-1
35-2
35-3
35-4
37-1
37-2
37-3
37-4
Title
Page
Number
PIP TxBD Status and Control Field Descriptions............................................................... 33-12
PIP RxBD Status and Control Field Descriptions............................................................... 33-14
PIP Transmit CP Commands .............................................................................................. 33-14
PIP Receive CP Commands................................................................................................ 33-15
Centronics Tx Errors ........................................................................................................... 33-21
Centronics Rx Error ............................................................................................................ 33-22
Port A Pin Assignment.......................................................................................................... 34-2
PAODR Bit Descriptions ...................................................................................................... 34-4
PADAT Bit Descriptions ....................................................................................................... 34-4
PADIR Bit Descriptions ........................................................................................................ 34-5
PAPAR Bit Descriptions ....................................................................................................... 34-5
Port B Pin Assignment .......................................................................................................... 34-8
PBODR Bit Descriptions ...................................................................................................... 34-9
PBDAT Bit Descriptions ..................................................................................................... 34-10
PBDIR Bit Descriptions..................................................................................................... 34-11
PBPAR Bit Descriptions ..................................................................................................... 34-11
Port C Pin Assignment ........................................................................................................ 34-12
Port C Pin Assignment for UTOPIA................................................................................... 34-14
PCDAT Bit Descriptions ..................................................................................................... 34-14
PCDIR Bit Descriptions...................................................................................................... 34-15
PCPAR Bit Descriptions ..................................................................................................... 34-15
PCSO Bit Descriptions........................................................................................................ 34-16
PCINT Bit Descriptions ...................................................................................................... 34-17
Port D Pin Assignment........................................................................................................ 34-18
PDDAT Bit Descriptions..................................................................................................... 34-19
PDDIR Bit Descriptions...................................................................................................... 34-19
PDPAR Field Descriptions.................................................................................................. 34-20
Port E Pin Assignment ........................................................................................................ 34-21
PEODR Bit Descriptions .................................................................................................... 34-22
PEDAT Bit Descriptions ..................................................................................................... 34-23
PEDIR Bit Descriptions ..................................................................................................... 34-24
PEPAR Bit Descriptions ..................................................................................................... 34-24
PESO Bit Descriptions........................................................................................................ 34-25
Prioritization of CPM Interrupt Sources ............................................................................... 35-3
Interrupt Vector Encodings ................................................................................................... 35-5
CICR Field Descriptions ....................................................................................................... 35-7
CIVR Field Descriptions..................................................................................................... 35-10
ATM RxBD Field Descriptions............................................................................................. 37-4
ATM TxBD Field Descriptions............................................................................................. 37-8
RCT Field Descriptions ...................................................................................................... 37-12
PTP RCT Field Descriptions............................................................................................... 37-16
MPC885 PowerQUICC Family Reference Manual, Rev. 2
lxxvi
Freescale Semiconductor
Tables
Table
Number
37-5
37-6
37-7
38-1
38-2
38-3
38-4
38-5
38-6
38-7
38-8
38-9
38-10
38-11
38-12
38-13
38-14
38-15
39-1
39-2
39-3
39-4
39-5
39-6
39-7
39-8
40-1
40-2
41-1
41-2
41-3
42-1
42-2
42-3
42-4
42-5
42-6
42-7
43-1
43-2
Title
Page
Number
TCT Field Descriptions....................................................................................................... 37-20
PTP TCT Field Descriptions ............................................................................................... 37-24
TCTE Field Descriptions .................................................................................................... 37-29
Serial ATM and UTOPIA Interface Parameter RAM Map................................................... 38-1
ESAR Mode Parameters ....................................................................................................... 38-6
Serial ATM Parameter RAM Map ........................................................................................ 38-7
SRFCR Field Descriptions.................................................................................................... 38-9
SRSTATE Field Descriptions................................................................................................ 38-9
STFCR Field Descriptions .................................................................................................. 38-10
STSTATE Field Descriptions.............................................................................................. 38-11
AM1–AM5 Parameters for the Internal Look-up Table ..................................................... 38-12
HMASK Field Descriptions................................................................................................ 38-12
AM1–AM5 Parameters
for Extended Channel Address Compression................................................................. 38-13
FLMASK Field Descriptions .............................................................................................. 38-13
AM1–AM5 Parameters for Extended Channel CAM Operation........................................ 38-14
APCST Field Descriptions.................................................................................................. 38-14
MPHYST Field Descriptions .............................................................................................. 38-16
ASTATUS Register Field Descriptions............................................................................... 38-16
Types of Cell Filtering .......................................................................................................... 39-6
Performance Monitoring Cell Fields..................................................................................... 39-8
PM Table Field Descriptions............................................................................................... 39-13
Available PTP Options ........................................................................................................ 39-16
PTP BD Field Descriptions ................................................................................................. 39-17
Address Signals in a Multi-PHY System ........................................................................... 39-19
CPCR ATM-Specific Field Descriptions ............................................................................ 39-22
ATM Commands ................................................................................................................. 39-23
APC Priority Levels ............................................................................................................ 40-15
APC Priority Level Parameter Descriptions ....................................................................... 40-17
UTOPIA Event Register (IDSR1) Field Descriptions .......................................................... 41-2
Serial ATM Event Register (SCCE) Field Descriptions ....................................................... 41-3
Interrupt Queue Entry Field Descriptions ............................................................................. 41-5
PDPAR Field Descriptions.................................................................................................... 42-1
SCCR Field Descriptions for the Internal UTOPIA Clock................................................... 42-3
Port B Pin Assignment .......................................................................................................... 42-4
Port C Pin Assignment for UTOPIA..................................................................................... 42-5
Port D Pin Assignment.......................................................................................................... 42-5
PCMCIA Port A Pin Assignments........................................................................................ 42-6
PSMR Serial ATM Field Descriptions.................................................................................. 42-8
UTMODE Field Descriptions ............................................................................................... 43-2
UTOPIA Signal Groups ........................................................................................................ 43-5
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Tables
Table
Number
44-1
44-2
44-3
44-4
44-5
44-6
44-7
44-8
45-1
45-2
45-3
45-4
45-5
45-6
45-7
45-8
45-9
45-10
45-11
45-12
45-13
45-14
45-15
45-16
45-17
45-18
45-19
45-20
45-21
45-22
45-23
45-24
45-25
45-26
45-27
45-28
45-29
45-30
45-31
45-32
45-33
Title
Page
Number
Acronyms and Abbreviated Terms........................................................................................ 44-2
TPD Field Descriptions......................................................................................................... 44-6
AAL2 Transmit Connection Table Field Descriptions ......................................................... 44-8
RPD Field Descriptions ...................................................................................................... 44-14
AAL2 Receive Connection Table Field Descriptions......................................................... 44-17
AAL2 Parameter RAM Memory Map ................................................................................ 44-22
AAL2-Specific Exceptions ................................................................................................. 44-25
Estimated AAL2 Performance ............................................................................................ 44-28
MPC885 Family .................................................................................................................... 45-1
MII and RMII Signals ........................................................................................................... 45-3
Serial Mode Connections to the External Transceiver.......................................................... 45-3
Transmission Errors .............................................................................................................. 45-9
Reception Errors ................................................................................................................... 45-9
CPTR RMII Related Field Descriptions ............................................................................. 45-11
FEC Parameter RAM Memory Map................................................................................... 45-12
ADDR_LOW Field Descriptions........................................................................................ 45-13
ADDR_HIGH Field Descriptions ....................................................................................... 45-14
HASH_TABLE_HIGH Field Descriptions......................................................................... 45-15
HASH_TABLE_LOW Field Descriptions.......................................................................... 45-16
R_DES_START Field Descriptions.................................................................................... 45-16
X_DES_START Field Descriptions.................................................................................... 45-17
R_BUFF_SIZE Field Descriptions ..................................................................................... 45-18
ECNTRL Field Descriptions............................................................................................... 45-19
I_EVENT/I_MASK Field Descriptions.............................................................................. 45-20
IVEC Field Descriptions ..................................................................................................... 45-21
R_DES_ACTIVE Field Descriptions ................................................................................. 45-22
X_DES_ACTIVE Field Descriptions ................................................................................. 45-23
MII_DATA Field Descriptions............................................................................................ 45-23
MII_SPEED Field Descriptions.......................................................................................... 45-24
Programming Examples for MII_SPEED Register ............................................................ 45-25
R_BOUND Field Descriptions ........................................................................................... 45-26
R_FSTART Field Descriptions ........................................................................................... 45-27
X_WMRK Field Descriptions ............................................................................................ 45-28
X_FSTART Field Descriptions ........................................................................................... 45-28
FUN_CODE Field Descriptions ......................................................................................... 45-29
R_CNTRL Field Descriptions ............................................................................................ 45-30
R_HASH Field Descriptions............................................................................................... 45-31
X_CNTRL Field Descriptions ............................................................................................ 45-32
Hardware Initialization ....................................................................................................... 45-33
ECNTRL[ETHER_EN] Deassertion Initialization ............................................................. 45-33
User Initialization (Before Setting ECNTRL[ETHER_EN]) ............................................. 45-33
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Tables
Table
Number
45-34
45-35
45-36
46-1
46-2
47-1
47-2
48-1
48-2
48-3
48-4
48-5
48-6
48-7
48-8
48-9
48-10
48-11
48-12
48-13
48-14
48-15
48-16
48-17
49-1
49-2
49-3
49-4
49-5
49-6
49-7
49-8
50-1
50-2
50-3
50-4
50-5
50-6
50-7
50-8
50-9
Title
Page
Number
User Initialization (After Setting ECNTRL[ETHER_EN])................................................ 45-34
Receive Buffer Descriptor (RxBD) Field Description....................................................... 45-35
Transmit Buffer Descriptor (TxBD) Field Descriptions ..................................................... 45-38
Example Data Packet Descriptor .......................................................................................... 46-3
Estimated Bulk Data Encryption Performance (Mbps) ........................................................ 46-6
Module Base Address Map ................................................................................................... 47-1
Security Engine Memory Map Showing Register Details IMMR[14:15]=10)..................... 47-1
DEU Mode Register Field Descriptions ............................................................................... 48-3
DEU Key Size Register Field Descriptions .......................................................................... 48-4
DEU Reset Control Register Field Descriptions................................................................... 48-6
DEU Status Register ............................................................................................................. 48-7
DEU Interrupt Status Register Field Descriptions ................................................................ 48-8
DEU Interrupt Control Register Field Descriptions ........................................................... 48-10
MDEU Mode Register ........................................................................................................ 48-14
MDEU Reset Control Register Field Descriptions ............................................................. 48-17
MDEU Status Register Field Descriptions ......................................................................... 48-18
MDEU Interrupt Status Register Field Descriptions .......................................................... 48-19
MDEU Interrupt Control Register Field Descriptions ........................................................ 48-21
AESU Mode Register Field Descriptions ........................................................................... 48-25
AESU Reset Control Register Field Descriptions .............................................................. 48-28
AESU Status Register Field Descriptions........................................................................... 48-30
AESU Interrupt Status Register Field Descriptions............................................................ 48-31
AESU Interrupt Control Register Field Descriptions ......................................................... 48-33
Counter Modulus................................................................................................................. 48-36
Header Bit Definitions .......................................................................................................... 49-2
EU_SELECT Values ............................................................................................................. 49-3
Descriptor Types ................................................................................................................... 49-4
Descriptor Length Field Mapping......................................................................................... 49-5
Descriptor Pointer Field Mapping......................................................................................... 49-5
Descriptor Length/Pointer Mapping ..................................................................................... 49-6
Descriptor Pointer Field Mapping......................................................................................... 49-6
Descriptor_HMAC_Snoop_Non_AFEU .............................................................................. 49-8
Crypto-Channel Configuration Register Fields .................................................................... 50-2
Burst Size Definition............................................................................................................. 50-4
Crypto-Channel Pointer Status Register 1 Fields.................................................................. 50-5
Crypto-Channel Pointer Status Register 2 Fields.................................................................. 50-5
STATE Field Values .............................................................................................................. 50-7
Crypto-Channel Pointer Status Register Error Field Definitions.......................................... 50-9
Crypto-Channel Pointer Status Register PAIR_PTR Field Values........................................ 50-9
Crypto-Channel Current Descriptor Pointer Register Fields .............................................. 50-10
Fetch Register Fields........................................................................................................... 50-11
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Tables
Table
Number
51-1
51-2
51-3
51-4
52-1
53-1
53-2
53-3
53-4
53-5
53-6
53-7
53-8
53-9
53-10
53-11
53-12
53-13
53-14
53-15
53-16
53-17
53-18
53-19
53-20
53-21
53-22
53-23
53-24
53-25
54-1
A-1
A-2
A-3
A-4
A-5
A-6
C-1
C-2
C-3
C-4
Title
Page
Number
Interrupt Mask, Status, and Clear Register 1 Signals............................................................ 51-5
Interrupt Mask, Status, and Clear Register 2 Signals............................................................ 51-5
Master Control Register Signals ........................................................................................... 51-7
Master Error Address Register Bit Definitions..................................................................... 51-8
CPTR SEC Lite–Related Field Descriptions ........................................................................ 52-1
Fetch Show Cycles Control................................................................................................... 53-3
Status Pin Groupings............................................................................................................. 53-3
VF Pins Encoding: Instruction Queue Flushes ..................................................................... 53-3
VF Pins Encoding: Instruction Fetch Types.......................................................................... 53-4
Detecting the Trace Buffer Start Point .................................................................................. 53-7
Instruction Watchpoints Programming Options.................................................................. 53-11
Load/Store Data Events....................................................................................................... 53-13
Load/Store Watchpoints Programming Options ................................................................. 53-13
Checkstop State and Debug Mode ...................................................................................... 53-22
Trap Enable Data Shifted into Development Port Shift Register ....................................... 53-29
Debug Port Command Shifted Into Development Port Shift Register ............................... 53-29
Status/Data Shifted Out of Development Port Shift Register ............................................. 53-30
Debug Instructions/Data Shifted Into Development Port Shift Register ............................ 53-31
MPC885-Specific Development Support and Debug SPRs ............................................... 53-34
Development Support/Debug Registers Protection ............................................................ 53-35
CMPA–CMPD Field Descriptions ...................................................................................... 53-35
CMPE–CMPF Field Descriptions....................................................................................... 53-36
CMPG–CMPH Field Descriptions...................................................................................... 53-36
BAR Field Descriptions ...................................................................................................... 53-37
ICTRL Field Descriptions................................................................................................... 53-37
LCTRL1 Field Descriptions................................................................................................ 53-39
LCTRL2 Field Descriptions................................................................................................ 53-40
COUNTA/COUNTB Field Descriptions ............................................................................ 53-42
ICR Field Descriptions........................................................................................................ 53-43
DER Field Descriptions ...................................................................................................... 53-45
Instruction Register Decoding .............................................................................................. 54-6
Byte-Ordering Parameters...................................................................................................... A-1
TLE 2-bit Munging ................................................................................................................ A-3
Little-Endian Program/Data Path Between the Register and 32-Bit Memory....................... A-4
Little-Endian Program/Data Path Between the Register and 16-Bit Memory....................... A-4
Little-Endian Program/Data Path between the Register and 8-Bit Memory ......................... A-5
PPC-LE 3-bit Munging .......................................................................................................... A-6
User-Level Registers...............................................................................................................C-1
User-Level SPRs .....................................................................................................................C-1
Supervisor-Level Registers .....................................................................................................C-2
Supervisor-Level SPRs ...........................................................................................................C-2
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Tables
Table
Number
C-5
C-6
D-1
D-2
D-3
D-4
D-5
D-6
D-7
D-8
D-9
D-10
D-11
D-12
D-13
D-14
D-15
D-16
D-17
D-18
D-19
D-20
D-21
D-22
D-23
D-24
D-25
D-26
D-27
D-28
D-29
D-30
D-30
D-31
D-32
D-33
D-34
D-35
D-36
D-37
D-38
Title
Page
Number
MPC885-Specific Supervisor-Level SPRs .............................................................................C-3
MPC885-Specific Debug-Level SPRs ....................................................................................C-4
Complete Instruction List Sorted by Mnemonic.................................................................... D-1
Complete Instruction List Sorted by Opcode......................................................................... D-9
Integer Arithmetic Instructions ............................................................................................ D-17
Integer Compare Instructions............................................................................................... D-18
Integer Logical Instructions ................................................................................................. D-18
Integer Rotate Instructions ................................................................................................... D-18
Integer Shift Instructions...................................................................................................... D-19
Floating-Point Arithmetic Instructions 6 ............................................................................. D-19
Floating-Point Multiply-Add Instructions 6 ........................................................................ D-20
Floating-Point Rounding and Conversion Instructions 6..................................................... D-20
Floating-Point Compare Instructions 6 ................................................................................ D-20
Floating-Point Status and Control Register Instructions 6................................................... D-20
Integer Load Instructions ..................................................................................................... D-21
Integer Store Instructions ..................................................................................................... D-21
Integer Load and Store with Byte-Reverse Instructions ...................................................... D-22
Integer Load and Store Multiple Instructions ...................................................................... D-22
Integer Load and Store String Instructions .......................................................................... D-22
Memory Synchronization Instructions................................................................................. D-22
Floating-Point Load Instructions 6 ...................................................................................... D-23
Floating-Point Store Instructions 6 ...................................................................................... D-23
Floating-Point Move Instructions 6 ..................................................................................... D-23
Branch Instructions .............................................................................................................. D-24
Condition Register Logical Instructions .............................................................................. D-24
System Linkage Instructions ................................................................................................ D-24
Trap Instructions .................................................................................................................. D-24
Processor Control Instructions ............................................................................................. D-24
Cache Management Instructions .......................................................................................... D-25
Segment Register Manipulation Instructions....................................................................... D-25
Lookaside Buffer Management Instructions ........................................................................ D-25
External Control Instructions ............................................................................................... D-26
I-Form .................................................................................................................................. D-27
B-Form ................................................................................................................................. D-27
SC-Form............................................................................................................................... D-27
DS-Form............................................................................................................................... D-29
X-Form................................................................................................................................. D-29
XL-Form .............................................................................................................................. D-33
XFX-Form............................................................................................................................ D-33
XFL-Form ............................................................................................................................ D-34
XS-Form............................................................................................................................... D-34
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Tables
Table
Number
D-39
D-40
D-41
D-42
D-43
D-44
H-1
H-2
H-3
H-4
Title
Page
Number
XO-Form .............................................................................................................................. D-34
A-Form................................................................................................................................. D-35
M-Form ................................................................................................................................ D-36
MD-Form ............................................................................................................................. D-36
MDS-Form ........................................................................................................................... D-36
Instruction Set Legend ......................................................................................................... D-39
Serial Interface Register Programming Example for Serial ATM ......................................... H-4
ATM Cell Transmission and Reception Programming Example ........................................... H-4
TDMA Port Pin Requirements............................................................................................... H-5
Port Register Programming Example .................................................................................... H-5
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About This Book
The primary objective of this manual is to help communications system designers build systems using the
Freescale MPC885 and to help software designers provide operating systems and user-level applications
to take fullest advantage of the MPC885, which contains a PowerPC™ processor core.
Although this book describes aspects of the PowerPC architecture that are critical for understanding the
MPC8xx core, it does not contain a complete description of the architecture. Where additional information
might help the reader, references are made to Programming Environments Manual for the PowerPC
Architecture. Ordering information for this book are provided in the section “Related Documentation.”
The information in this book is subject to change without notice, as described in the disclaimers on the title
page of this book. As with any technical documentation, it is the readers’ responsibility to be sure they are
using the most recent version of the documentation. Contact your sales representative for more
information.
Before Using This Manual
Before using this manual, determine whether it is the latest revision and if there are errata or addenda. To
locate any published errata or updates for this document, refer to the world-wide web at
http://www.freescale.com.
Note that this manual supports all members of the MPC885 family; however, it is written from the
perspective of the MPC885, which contains a superset of the functionality in Table i. Refer to this table to
determine the functionality of each MPC885.
Table i. MPC885 Family
Cache
Ethernet
Part
SCC SMC USB
10BaseT 10/100
ATM
Support
Security
Documentation
Engine
Instruction
Data
MPC885
8 Kbytes
8 Kbytes
Up to 3
2
3
2
1
Serial ATM
and UTOPIA
interface
Yes
This manual
MPC880
8 Kbytes
8 Kbytes
Up to 2
2
2
2
1
Serial ATM
and UTOPIA
interface
No
Appendix E
MPC875
8 Kbytes
8 Kbytes
1
2
1
1
1
—
Yes
Appendix F
MPC870
8 Kbytes
8 Kbytes
0
2
0
1
1
—
No
Appendix G
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lxxxiii
Audience
This manual is intended for software and hardware developers and application programmers who want to
develop products for the MPC885. It is assumed that the reader has a basic understanding of computer
networking, OSI layers, and RISC architecture. In addition, it is assumed that the reader has a basic
understanding of the communications protocols described here. Where it is considered useful, additional
sources are provided that provide in-depth discussions of such topics.
Organization
Following is a summary and a brief description of the chapters of this manual:
• Part I, “Overview,” provides a high-level description of the MPC885, describing general operation
and listing basic features.
— Chapter 1, “MPC885 Overview,” provides a high-level description of MPC885 functions and
features. It roughly follows the structure of this book, summarizing the relevant features and
providing references for the reader who needs additional information.
— Chapter 2, “Memory Map,” presents a table showing where MPC885 registers are mapped in
memory. It includes cross references that indicate where each register is described in detail.
• Part II, “MPC8xx Microprocessor Module,” describes the MPC8xx core. These chapters provide
details concerning the processor core as an implementation of the PowerPC architecture.
— Chapter 3, “The MPC8xx Core,” provides an overview of the MPC885 core.
— Chapter 4, “MPC8xx Core Register Set,” describes the hardware registers accessible to the
MPC885 core. These include both architecturally-defined and MPC885-specific registers.
— Chapter 5, “MPC885 Instruction Set,” describes the PowerPC instructions implemented by the
MPC885. These instructions are organized by the level of architecture in which they are
implemented—UISA, VEA, and OEA.
— Chapter 6, “Exceptions,” describes the PowerPC exception model as it is implemented on the
MPC885.
— Chapter 7, “Instruction and Data Caches,” describes the organization of the on-chip instruction
and data caches, cache control, various cache operations, and the interaction between the
caches, the load/store unit (LSU), the instruction sequencer, and the system interface unit
(SIU).
— Chapter 8, “Memory Management Unit,” describes how the PowerPC MMU model is
implemented on the MPC885. Although the MPC885 MMU is based on the PowerPC MMU
model, it differs greatly in many respects, which are described in this chapter.
— Chapter 9, “Instruction Execution Timing,” describes the MPC885 instruction unit, and
provides ways to take greatest advantage of its RISC architecture characteristics, such as
pipelining and parallel execution. It includes a table of instruction latencies and lists
dependencies and potential bottlenecks.
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•
•
•
Part III, “Configuration and Reset,” describes start-up behavior of the MPC885.
— Chapter 10, “System Interface Unit,” describes the SIU, which controls system start-up,
initialization and operation, and protection, as well as the external system bus.
— Chapter 11, “Reset,” describes the behavior of the MPC885 at reset and start-up.
Part IV, “Hardware Interface,” describes external signals, clocking, memory control, and power
management of the MPC885.
— Chapter 12, “External Signals,” provides a detailed description of the external signals that
comprise the MPC885 external interface.
— Chapter 13, “External Bus Interface,” describes interactions among signals described in the
previous chapter, including numerous examples and timing diagrams.
— Chapter 14, “Clocks and Power Control,” describes on-chip and external devices, including the
phase-locked loop circuitry and frequency dividers that generate programmable clock timing
for baud-rate generators, timers, and a variety of low-power mode options.
— Chapter 15, “Memory Controller,” describes the memory controller, which control a maximum
of eight memory banks shared between a general-purpose chip-select machine (GPCM) and a
pair of user-programmable machines (UPMs).
— Chapter 16, “PCMCIA Interface,” describes the PCMCIA host adapter module, which
provides all control logic for a PCMCIA socket interface and requires only additional external
analog power-switching logic and buffering.
Part V, “Communications Processor Module,” describes the configuration, clocking, and operation
of the various communications protocols supported by the MPC885.
— Chapter 17, “Communications Processor Module and CPM Timers,” provides a brief overview
of the MPC885 CPM and a detailed discussion of the clocking mechanisms supported.
— Chapter 18, “Communications Processor,” describes the RISC communications processor
(CP), which handles the low-level communications tasks, freeing the core for higher-level
tasks.
— Chapter 19, “SDMA Channels and IDMA Emulation,” describes the two physical serial DMA
(SDMA) channels on the MPC885 with which the CP implements virtual SDMA channels.
— Chapter 20, “Serial Interface,” describes the serial interface (SI) in which the physical interface
to all SCCs and SMCs is implemented.
— Chapter 21, “Serial Communications Controllers,” describes the serial communications
controllers (SCC), which can be configured independently to implement different protocols for
bridging functions, routers, and gateways, and to interface with a wide variety of standard
WANs, LANs, and proprietary networks.
— Chapter 22, “SCC UART Mode,” describes the MPC885 implementation of the universal
asynchronous receiver transmitter (UART) protocol, used for sending low-speed data between
devices.
— Chapter 23, “SCC HDLC Mode,” describes the MPC885 implementation of the HDLC
protocol.
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•
— Chapter 24, “SCC AppleTalk Mode,” describes the MPC885 implementation of AppleTalk, a
set of protocols developed by Apple Computer, Inc. to provide a LAN service between
Macintosh computers and printers.
— Chapter 25, “SCC Asynchronous HDLC Mode and IrDA,” describes the asynchronous HDLC
and IrDA use of HDLC framing techniques with UART-type characters.
— Chapter 26, “SCC BISYNC Mode,” describes the MPC885 implementation of the
byte-oriented BISYNC protocol developed by IBM for use in networking products.
— Chapter 27, “SCC Ethernet Mode,” describes the MPC885 implementation of the Ethernet
protocol.
— Chapter 28, “SCC Transparent Mode,” describes the MPC885 implementation of transparent
mode (also called totally transparent mode), which provides a clear channel on which the SCC
can send or receive serial data without bit-level manipulation.
— Chapter 29, “Serial Management Controllers (SMCs),” describes two serial management
controllers, full-duplex ports that can be configured independently to support one of three
protocols—UART, transparent, or general-circuit interface (GCI).
— Chapter 30, “Serial Peripheral Interface (SPI),” describes the serial peripheral interface, which
allows the MPC885 to exchange data between other MPC885 chips, the MC68360, the
MC68302, the M68HC11 and M68HC05 microcontroller families, and peripheral devices such
as EEPROMs, real-time clocks, A/D converters, and ISDN devices.
— Chapter 31, “Universal Serial Bus (USB),” describes the MPC885 implementation of the
universal serial bus (USB) controller.
— Chapter 32, “I2C Controller,” describes the MPC885 implementation of the inter-integrated
circuit (I2C®) controller, which allows data to be exchanged with other I2C devices, such as
microcontrollers, EEPROMs, real-time clock devices, and A/D converters.
— Chapter 33, “Parallel Interface Port (PIP),” describes the parallel interface port which allows
data to be sent to and from the MPC885 over 8 or 16 parallel data lines with two handshake
control signals.
— Chapter 34, “Parallel I/O Ports,” describes the four general-purpose I/O ports—A, B, C, and D.
Each signal in the I/O ports can be configured as a general-purpose I/O signal or as a signal
dedicated to supporting communications devices, such as SMCs and SCCs.
— Chapter 35, “CPM Interrupt Controller,” describes how the CPM interrupt controller (CPIC)
accepts and prioritizes the internal and external interrupt requests from the CPM blocks and
passes them to the system interface unit (SIU). The CPIC also provides a vector during the core
interrupt acknowledge cycle.
Part VI, “Asynchronous Transfer Mode (ATM),” describes the MPC885 ATM implementation. It
consists of the following chapters:
— Chapter 36, “ATM Overview,” gives a high-level description of the MPC885 ATM
implementation, which adds major new features available in enhanced SAR (ESAR) mode,
including multiple APC priority levels, port-to-port switching, simultaneous MII (100Base-T)
and UTOPIA (half-duplex) capability, relocatable UTOPIA-level-2-compliant interface with
added FIFO buffering to reduce the total cell transmission time.
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•
•
— Chapter 37, “Buffer Descriptors and Connection Tables,” describes the structure and
configuration of the buffer descriptors (BDs) and the transmit and receive connection tables
(TCTs and RCTs) used with ATM.
— Chapter 38, “ATM Parameter RAM,” describes how the parameter RAM is used to configure
the four SCCs for serial ATM and the UTOPIA interface. The CP also uses parameter RAM to
store operational and temporary values used during SAR activities.
— Chapter 39, “ATM Controller,” describes the address mapping mechanisms of the ATM
controller to support connection tables for both single- and multi-PHY interfaces, and the
commands provided to control ATM transmit and receive operations on a channel-by-channel
basis.
— Chapter 40, “ATM Pace Control,” describes how the ATM pace control unit (APC) processes
traffic parameters of each channel and defines the multiplex timing for all the channels.
— Chapter 41, “ATM Exceptions,” describes how the circular ATM interrupt queue operates with
an event register (SCCE or IDSR1) to provide an interrupt model for ATM operations.
— Chapter 42, “Interface Configuration,” describes the programming of registers and parameters
for ATM operations through both the UTOPIA and serial interfaces.
— Chapter 43, “UTOPIA Interface,” describes the single- and multi-classic SAR MPHY ATM
operation, including the UTOPIA modes and the signals provided for UTOPIA support.
— Chapter 44, “AAL2 Implementation,” describes the implementation of AAL2.
Part VII, “Fast Ethernet Controller (FEC),” describes the MPC885 support for 10/100 base-T
Ethernet. It consists of the following chapter:
— Chapter 45, “Fast Ethernet Controller (FEC),” describes the Fast Ethernet Controller, which is
implemented on all MPC885 parts. It provides general descriptions of supported operations,
full descriptions of the supporting registers, and initialization information.
Part VIII, “Integrated Security Engine (SEC Lite),” describes the MPC885 implementation of the
security engine. It contains the following chapters:
— Chapter 46, “SEC Lite Overview,” gives a high-level description of the MPC885 SEC Lite and
the features.
— Chapter 47, “SEC Lite Address Map,” describes the memory used by the SEC Lite.
— Chapter 48, “SEC Lite Execution Units,” describes the Data Encryption Standard execution
unit (DEU), the Advanced Encryption Standard execution unit (AESU), and the message digest
execution unit (MDEU).
— Chapter 49, “SEC Lite Descriptors,” describes the descriptors used to take SEC Lite through
the security operations.
— Chapter 50, “SEC Lite Crypto-Channel,” describes how the crypto-channel manages data
associated with one of more execution units.
— Chapter 51, “SEC Lite Controller,” describes the responsibility of the controller within the
SEC Lite to oversee the operations of the execution units (EUs), the interface to the host
processor, and the management of the crypto-channel.
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•
•
•
•
•
•
•
•
•
— Chapter 52, “SEC Lite Master/Slave Interface Module,” describes the master/slave interface
module and how it manages communication between the internal modules of the SEC Lite and
the rest of the PowerQUICC.
Part IX, “System Debugging and Testing Support,” describes how to use the MPC885 facilities for
debugging and system testing.
— Chapter 53, “System Development and Debugging,” describes support provided for program
flow tracking, internal watchpoint and breakpoint generation, and emulation systems control.
— Chapter 54, “IEEE 1149.1 Test Access Port,” describes the dedicated user-accessible test
access port (TAP), which is fully compatible with the IEEE 1149.1 Standard Test Access Port
and Boundary Scan Architecture.
Appendix A, “Byte Ordering,” discusses the MPC885 implementation of little- and big-endian
byte mapping.
Appendix B, “Serial Communications Performance,” provides guidelines for maximizing
performance of MPC885-based systems.
Appendix C, “Register Quick Reference Guide,” contains a quick reference guide to the MPC885
registers.
Appendix D, “Instruction Set Listings,” contains tables of the PowerPC instructions supported by
the MPC885.
Appendix E, “MPC880,” describes characteristics specific to the MPC880.
Appendix F, “MPC875,” describes characteristics specific to the MPC875.
Appendix G, “MPC870,” describes characteristics specific to the MPC870.
Appendix H, “Serial ATM Scrambling, Reception, and SI Programming,” describes payload
rescrambling and the MPC885 receive procedure. It also provides a serial interface programming
example.
This manual also includes a glossary and an index.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the PowerPC architecture.
MPC8xx Documentation
Supporting documentation for the MPC885 can be accessed through the world-wide web at
http://www.freescale.com. This documentation includes technical specifications, reference materials, and
detailed applications notes.
Related Documentation
The documentation is organized in the following types of documents:
• Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture
(MPEFPC32B/AD)—Describes resources defined by the PowerPC architecture.
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•
•
•
•
•
•
•
User’s manuals—These books provide details about individual implementations and are intended
for use with the Programming Environments Manual.
Addenda/errata to user’s manuals—Because some processors have follow-on parts an addendum
is provided that describes the additional features and functionality changes. These addenda are
intended for use with the corresponding user’s manuals.
Hardware specifications—Hardware specifications provide specific data regarding bus timing,
signal behavior, and AC, DC, and thermal characteristics, as well as other design considerations.
Separate hardware specifications are provided for each part described in this book.
Technical summaries—Each device has a technical summary that provides an overview of its
features. This document is roughly the equivalent to the overview (Chapter 1) of an
implementation’s user’s manual.
The Programmer’s Reference Guide for the PowerPC Architecture: MPCPRG/D—This concise
reference includes the register summary, memory control model, exception vectors, and the
PowerPC instruction set.
The Programmer’s Pocket Reference Guide for the PowerPC Architecture:
MPCPRGREF/D—This foldout card provides an overview of PowerPC registers, instructions, and
exceptions for 32-bit implementations.
Application notes—These short documents address specific design issues useful to programmers
and engineers working with Freescale processors.
Additional literature is published as new processors become available. For a current list of documentation,
refer to http://www.freescale.com.
Conventions
This document uses the following notational conventions:
Bold entries in figures and tables showing registers and parameter RAM should
Bold
be initialized by the user.
mnemonics
Instruction mnemonics are shown in lowercase bold.
italics
Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
0x0
Prefix to denote hexadecimal number
0b0
Prefix to denote binary number
rA, rB
Instruction syntax used to identify a source GPR
rD
Instruction syntax used to identify a destination GPR
REG[FIELD]
Abbreviations or acronyms for registers or buffer descriptors are shown in
uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For
example, MSR[LE] refers to the little-endian mode enable bit in the machine state
register.
x
In certain contexts, such as in a signal encoding or a bit field, indicates a don’t
care.
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n
¬
&
|
Used to express an undefined numerical value
NOT logical operator
AND logical operator
OR logical operator
Acronyms and Abbreviations
Table ii contains acronyms and abbreviations used in this document. Note that the meanings for some
acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not
be intuitively obvious.
Table ii. Acronyms and Abbreviated Terms
Term
Meaning
A/D
Analog-to-digital
ALU
Arithmetic logic unit
ATM
Asynchronous transfer mode
BD
Buffer descriptor
BIST
Built-in self test
BPU
Branch processing unit
BRI
Basic rate interface.
BUID
Bus unit ID
CAM
Content-addressable memory
CEPT
Conférence Européene des Administrations des Postes et des Télécommunications (European
Conference of Postal and Telecommunications Administrations)
CP
CPM
CR
Communications processor
Communications processor module
Condition register
CRC
Cyclic redundancy check
CTR
Count register
DABR
Data address breakpoint register
DAR
Data address register
DEC
Decrementer register
DMA
Direct memory access
DPLL
Digital phase-locked loop
DRAM
Dynamic random access memory
DSISR
Register used for determining the source of a DSI exception
DTLB
Data translation lookaside buffer
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Table ii. Acronyms and Abbreviated Terms (continued)
Term
EA
EEST
EPROM
FPR
FPSCR
Meaning
Effective address
Enhanced Ethernet serial transceiver
Erasable programmable read-only memory
Floating-point register
Floating-point status and control register
FPU
Floating-point unit
GCI
General circuit interface
GPCM
General-purpose chip-select machine
GPR
General-purpose register
GUI
Graphical user interface
HDLC
High-level data link control
I2C
Inter-integrated circuit
IDL
Inter-chip digital link
IEEE
Institute of Electrical and Electronics Engineers
IrDA
Infrared Data Association
ISDN
Integrated services digital network
ITLB
Instruction translation lookaside buffer
IU
Integer unit
JTAG
Joint test action group
LIFO
Last-in-first-out
LR
Link register
LRU
Least recently used
LSB
Least-significant byte
lsb
Least-significant bit
LSU
Load/store unit
MAC
Multiply accumulate
MESI
Modified/exclusive/shared/invalid—cache coherency protocol
MMU
Memory management unit
MSB
Most-significant byte
msb
Most-significant bit
MSR
Machine state register
NaN
Not a number
NIA
Next instruction address
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Table ii. Acronyms and Abbreviated Terms (continued)
Term
Meaning
NMSI
Nonmultiplexed serial interface
No-op
No operation
OEA
Operating environment architecture
OSI
Open systems interconnection
PCI
Peripheral component interconnect
PCMCIA
Personal Computer Memory Card International Association
PIR
Processor identification register
PRI
Primary rate interface
PVR
Processor version register
RISC
Reduced instruction set computing
RTOS
Real-time operating system
RWITM
Rx
Read with intent to modify
Receive
SCC
Serial communications controller
SCP
Serial control port
SDLC
Synchronous Data Link Control
SDMA
Serial DMA
SEC Lite
SI
SIMM
Integrated security engine—a low-cost derivative of the MPC185 security engine
Serial interface
Signed immediate value
SIU
System interface unit
SMC
Serial management controller
SNA
Systems network architecture
SPI
Serial peripheral interface
SPR
Special-purpose register
SPRGn
Registers available for general purposes
SRAM
Static random access memory
SRR0
Machine status save/restore register 0
SRR1
Machine status save/restore register 1
TAP
Test access port
TB
Time base register
TDM
Time-division multiplexed
TLB
Translation lookaside buffer
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Table ii. Acronyms and Abbreviated Terms (continued)
Term
Meaning
TSA
Time-slot assigner
Tx
Transmit
UART
Universal asynchronous receiver/transmitter
UIMM
Unsigned immediate value
UISA
User instruction set architecture
UPM
User-programmable machine
USART
Universal synchronous/asynchronous receiver/transmitter
VA
Virtual address
VEA
Virtual environment architecture
XER
Register used primarily for indicating conditions such as carries and overflows for integer operations
PowerPC Architecture Terminology Conventions
Table iii lists certain terms used in this manual that differ from the architecture terminology conventions.
Table iii. Terminology Conventions
The Architecture Specification
This Manual
Data storage interrupt (DSI)
DSI exception
Extended mnemonics
Simplified mnemonics
Instruction storage interrupt (ISI)
ISI exception
Interrupt
Exception
Privileged mode (or privileged state)
Supervisor-level privilege
Problem mode (or problem state)
User-level privilege
Real address
Physical address
Relocation
Translation
Storage (locations)
Memory
Storage (the act of)
Access
Table iv describes instruction field notation conventions used in this manual.
Table iv. Instruction Field Conventions
The Architecture Specification
Equivalent to:
BA, BB, BT
crbA, crbB, crbD (respectively)
BF, BFA
crfD, crfS (respectively)
D
d
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Table iv. Instruction Field Conventions (continued)
The Architecture Specification
Equivalent to:
DS
ds
FLM
FM
FXM
CRM
RA, RB, RT, RS
rA, rB, rD, rS (respectively)
SI
SIMM
U
IMM
UI
UIMM
/, //, ///
0...0 (shaded)
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Part I
Overview
Intended Audience
This part is intended for anyone who requires a high-level understanding of the MPC885 family of
PowerQUICC™ devices.
Contents
This part provides an overview of the features and functions of the MPC885. It includes the following
chapters:
• Chapter 1, “MPC885 Overview,” provides a high-level description of MPC885 functions and
features. It roughly follows the structure of this book, summarizing the relevant features and
providing references for the reader who needs additional information.
• Chapter 2, “Memory Map,” presents a table showing where MPC885 registers are mapped in
memory. It includes cross references that indicate where each register is described in detail.
Conventions
This part uses the following notational conventions:
mnemonics
Instruction mnemonics are shown in lowercase bold.
italics
Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
0x0
Prefix to denote hexadecimal number
0b0
Prefix to denote binary number
rA, rB
Instruction syntax used to identify a source GPR
rD
Instruction syntax used to identify a destination GPR
REG[FIELD]
Abbreviations or acronyms for registers or buffer descriptors are shown in
uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For
example, MSR[LE] refers to the little-endian mode enable bit in the machine state
register.
x
In certain contexts, such as in a signal encoding or a bit field, indicates a don’t
care.
n
Indicates an undefined numerical value
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I-1
Acronyms and Abbreviations
Table I-1 contains acronyms and abbreviations that are used in this document.
Table I-1. Acronyms and Abbreviated Terms
Term
BD
BPU
CP
Meaning
Buffer descriptor
Branch processing unit
Communications processor
CPM
Communications processor module
DMA
Direct memory access
DPLL
Digital phase-locked loop
DRAM
Dynamic random access memory
DTLB
Data translation lookaside buffer
EA
GPCM
Effective address
General-purpose chip-select machine
GPR
General-purpose register
HDLC
High-level data link control
I2C
Inter-integrated circuit
IEEE
Institute of Electrical and Electronics Engineers
IrDA
Infrared Data Association
ISDN
Integrated services digital network
ITLB
Instruction translation lookaside buffer
IU
Integer unit
JTAG
Joint Test Action Group
LRU
Least recently used (cache replacement algorithm)
LSU
Load/store unit
MMU
Memory management unit
MSR
Machine state register
NMSI
Nonmultiplexed serial interface
OEA
Operating environment architecture
OSI
Open systems interconnection
PCI
Peripheral component interconnect
PCMCIA
Personal Computer Memory Card International Association
RISC
Reduced instruction set computing
RTOS
Real-time operating system
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Table I-1. Acronyms and Abbreviated Terms (continued)
Term
Rx
Meaning
Receive
SCC
Serial communications controller
SDLC
Synchronous data link control
SDMA
Serial DMA
SEC Lite
SI
Integrated security engine—a low-cost derivative of the MPC185 security engine
Serial interface
SIU
System interface unit
SMC
Serial management controller
SPI
Serial peripheral interface
SPR
Special-purpose register
SRAM
TB
Static random access memory
Time base register
TDM
Time-division multiplexed
TLB
Translation lookaside buffer
TSA
Time-slot assigner
Tx
Transmit
UART
Universal asynchronous receiver/transmitter
UISA
User instruction set architecture
UPM
User-programmable machine
VEA
Virtual environment architecture
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Chapter 1
MPC885 Overview
The MPC885 PowerQUICC™ family is a 0.18-micron version of the MPC860 PowerQUICC family and
can operate at speeds of up to 120 MHz (2:1 mode) on the MPC8xx core and up to 80 MHz (1:1 mode) on
the external bus. The MPC885 family has a 1.8-V core and 3.3-V I/O operation with 5-V TTL
compatibility. The MPC885 integrated communications controller family is a versatile one-chip integrated
microprocessor and peripheral combination that can be used in a variety of controller applications. It
particularly excels in both communications and networking systems. The MPC885 contains a PowerPC™
processor core.
The MPC885 family is a PowerPC-architecture-based quad integrated communications controller
(PowerQUICC). The CPU on the MPC885 is the MPC8xx core, a 32-bit microprocessor which
implements the PowerPC architecture, incorporating memory management units (MMUs) and instruction
and data caches. The MPC885 is the superset of this family of devices and is mainly described in this
document.
Table 1-1 shows the functionality supported by the members of the MPC885 family:
Table 1-1. MPC885 Family
Cache
Ethernet
Part
SCC SMC USB
I Cache D Cache 10BaseT (SCC)
ATM Support
10/100 (FEC)
Security
Engine
MPC885
8 Kbyte
8 Kbyte
Up to 3
2
3
2
1
Serial ATM and
UTOPIA interface
Yes
MPC880
8 Kbyte
8 Kbyte
Up to 2
2
2
2
1
Serial ATM and
UTOPIA interface
No
MPC875
8 Kbyte
8 Kbyte
Up to 1
2
11
1
1
–
Yes
MPC870
8 Kbyte
8 Kbyte
—
2
—
1
1
–
No
1
The SCC may be used if any one of the FECs is not used.
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1-1
MPC885 Overview
1.1
Features
The following list summarizes the key MPC885 family features:
• Embedded MPC8xx core up to 120 MHz. The 120-MHz core frequency supports the 2:1 mode
only.
• Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode)
• The available core frequencies are 66, 80, and 120 MHz.
• Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two
32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1-1).
– Instruction cache is two-way, set-associative with 256 sets in two blocks.
– Data cache is two-way, set-associative with 256 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache-block basis.
— MMUs with 32-entry TLB, fully-associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, as well as 8 Mbytes; 16 virtual
address spaces and 16 protection groups
— Advanced on-chip-emulation debug mode
• The MPC885 family provides enhanced ATM functionality as found on the MPC862 and MPC866
Families. The MPC885 family includes the following:
— Improved operation, administration and maintenance (OAM) support
— OAM performance monitoring (PM) support
— Multiple APC priority levels available to support a range of traffic pace requirements
— Port-to-port switching capability without the need for RAM-based microcode
— Simultaneous MII (100Base-T) and UTOPIA (half- or full-duplex) capability
— Optional statistical cell counters per PHY
— UTOPIA-level-2-compliant interface with added FIFO buffering to reduce the total cell
transmission time and Multi-PHY support. (The earlier UTOPIA level-1 specification is also
supported.)
— Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode
— Supports full-duplex UTOPIA operation, both master (ATM side) and slave (PHY side), using
a 'split' bus
— AAL2/VBR functionality is ROM-resident
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• 32 address lines
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MPC885 Overview
•
•
•
•
•
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EEPROMs, flash EEPROMs, and other
memory devices
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32–256 Mbytes)
— Selectable write protection
— On-chip bus arbitration logic
General-purpose timers
— Four 16-bit or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
Two Fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet / IEEE 802.3 CDMA / CS
interface through MII and/or RMII interfaces
System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Clock synthesizer
— Decrementer and time base
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Security engine optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP,
802.11i, and iSCSI processing. Available on the MPC885 and the MPC875, the security engine
contains one crypto-channel, a controller, and a set of crypto execution units (EUs). These
execution units are:
— DEU—Data encryption standard execution unit
– DES, 3DES
– Two-key (K1, K2, K1) or three-key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— AESU—Advanced encryption standard unit
– Implements the Rijndael symmetric-key cipher
– ECB, CBC, and counter modes
– 128-, 192-, or 256-bit key lengths
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MPC885 Overview
•
•
•
•
— MDEU—Message digest execution unit
– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Crypto-channel supporting multi-command descriptor chains
— Integrated controller managing internal resources, and bus mastering
— Buffer size of 256 bytes for the DEU, AESU, and MDEU, with flow control for large data sizes
Interrupts
— Six external interrupt request (IRQ) lines
— 12 port pins with interrupt capability
— 23 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
Communications processor module (CPM)
— RISC controller
— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT
MODE, and RESTART TRANSMIT)
— Supports continuous-mode transmission and reception on all serial channels
— 8 Kbytes of dual-port RAM
— The MPC885 family has several serial DMA (SDMA) channels to support the CPM.
— Three parallel I/O registers with open-drain capability
Four baud rate generators
— Independent (can be connected to any SCC or SMC)
— Allow changes during operation
— Autobaud support option
Up to three serial communication controllers (SCCs) supporting the following protocols:
— Serial ATM capability on SCCs
— Optional UTOPIA port on SCC4
— Ethernet/IEEE 802.3 optional on the SCCs, supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
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MPC885 Overview
•
•
•
•
•
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
Up to two serial management channels (SMCs) supporting the following protocols:
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division multiplexed (TDM) channel
Universal serial bus (USB) — Supports operation as a USB function endpoint, a USB host
controller or both for testing purposes (loop-back diagnostics)
— USB 2.0 full/low-speed compatible
— The USB function mode features are as follows:
– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– CRC5 checking
– NRZI encoding/decoding with bit stuffing
– 12- or 1.5-Mbps data rate
– Flexible data buffers with multiple buffers per frame
– Automatic retransmission upon transmit error
— The USB host controller features are as follows:
– Supports control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– NRZI encoding/decoding with bit stuffing
– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and
data rate configuration). Note that low-speed operation requires an external hub.
– Flexible data buffers with multiple buffers per frame
– Supports local loopback mode for diagnostics (12 Mbps only)
One SPI (serial peripheral interface)
— Supports master and slave modes
— Supports multiple master operation on the same bus
One I2C (inter-integrated circuit) port
— Supports master and slave modes
— Multiple-master environment support
Time-slot assigner (TSA) (supports two TDMs on the MPC885 and the MPC880 and one TDM on
the MPC875)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, and user-defined
— one- or eight-bit resolution
— Allows independent transmit and receive routing, frame synchronization, and clocking
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1-5
MPC885 Overview
•
•
•
•
•
•
— Allows dynamic changes
— On the MPC885, can be internally connected to four serial channels (two SCCs and two SMCs)
Parallel interface port (PIP)
— Centronics interface support
— Supports fast connection between compatible ports on the MPC885 family and other MPC8xx
devices.
PCMCIA interface
— Master (socket) interface, release 2.1 compliant
— Supports two independent PCMCIA sockets (MPC875 and MPC870 support only one
PCMCIA socket)
— Eight memory or I/O windows supported
Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— Supports conditions: =, ≠, <, >
— Each watchpoint can generate a breakpoint internally
Normal high and normal low power modes to conserve power
1.8-V core and 3.3-V I/O operation with 5-V TTL compatibility
The MPC885/MPC880 comes in a 357-pin ball grid array (PBGA) package and the
MPC875/MPC870 comes in a 256-pin ball grid array
The MPC885 family is comprised of three modules that each use the 32-bit internal bus: the MPC8xx core,
the system integration unit (SIU), and the communication processor module (CPM).
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MPC885 Overview
The MPC885 block diagram is shown in Figure 1-2.
Instruction
Bus
Embedded
MPC8xx
Processor
Core
16-Kbyte
Instruction Cache
System Interface Unit (SIU)
Unified
Bus
Instruction MMU
32-Entry ITLB
Load/Store
Bus
Memory Controller
Internal
External
Bus Interface Bus Interface
Unit
Unit
8-Kbyte
Data Cache
System Functions
Data MMU
32-Entry DTLB
PCMCIA-ATA Interface
Fast Ethernet
Controller
DMAs
FIFOs
10/100
Base-T
Media Access
Control
Parallel I/O
4
Timers
4 Baud Rate
Generators
Parallel Interface Port
Timers
and UTOPIA
Interrupt
8-Kbyte
Controllers Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
16 Virtual
Serial
and
2
Independent
DMA
Channels
MII
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I 2C
Time Slot Assigner
Serial Interface
Figure 1-1. MPC866P Block Diagram
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1-7
MPC885 Overview
Instruction
Bus
8-Kbyte
Instruction Cache
System Interface Unit (SIU)
Unified
Bus
Instruction MMU
32-Entry ITLB
Embedded
MPC8xx
Processor
Core
Memory Controller
Internal
External
Bus Interface Bus Interface
Unit
Unit
8-Kbyte
Data Cache
Load/Store
Bus
System Functions
Data MMU
32-Entry DTLB
PCMCIA-ATA Interface
Slave / Master IF
Security Engine
Fast Ethernet
Controller
Controller
DMAs
DMAs
Channel
AESU
DEU
MDEU
FIFOs
10/100
Base-T
Media Access
Control
4
Timers
Parallel I/O
4 Baud Rate
Generators
Parallel Interface Port
MIII / RMII
USB
SCC2
Timers
Interrupt
8-Kbyte
Controllers Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
SCC3
SCC4/
UTOPIA
SMC1
Virtual IDMA
and
Serial DMAs
SMC2
SPI
I 2C
Time-Slot Assigner
Serial Interface
Figure 1-2. MPC885 Block Diagram
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Freescale Semiconductor
MPC885 Overview
The MPC880 block diagram is shown in Figure 1-4.
16-Kbyte
Instruction Cache
Instruction
Bus
Embedded
MPC8xx
Processor
Core
System Interface Unit (SIU)
Unified
Bus
Instruction MMU
32-Entry ITLB
Load/Store
Bus
Memory Controller
Internal
External
Bus Interface Bus Interface
Unit
Unit
8-Kbyte
Data Cache
System Functions
Data MMU
32-Entry DTLB
PCMCIA-ATA Interface
Fast Ethernet
Controller
DMAs
FIFOs
10/100
Base-T
Media Access
Control
Parallel I/O
4
Timers
4 Baud Rate
Generators
Parallel Interface Port
Timers
and UTOPIA
Interrupt
8-Kbyte
Controllers Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
16 Virtual
Serial
and
2
Independent
DMA
Channels
MII
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I 2C
Time Slot Assigner
Serial Interface
Figure 1-3. MPC866P Block Diagram
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Freescale Semiconductor
1-9
MPC885 Overview
Instruction
Bus
8-Kbyte
Instruction Cache
System Interface Unit (SIU)
Unified
Bus
Instruction MMU
32-Entry ITLB
Embedded
MPC8xx
Processor
Core
Memory Controller
Internal
External
Bus Interface Bus Interface
Unit
Unit
8-Kbyte
Data Cache
Load/Store
Bus
System Functions
Data MMU
32-Entry DTLB
PCMCIA-ATA Interface
Slave / Master IF
Fast Ethernet
Controller
DMAs
DMAs
FIFOs
10/100
Base-T
Media Access
Control
Parallel I/O
4
Timers
4 Baud Rate
Generators
Parallel Interface Port
MIII / RMII
USB
Timers
Interrupt
8-Kbyte
Controllers Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
SCC3
SCC4/
UTOPIA
SMC1
Virtual IDMA
and
Serial DMAs
SMC2
SPI
I 2C
Time-Slot Assigner
Serial Interface
Figure 1-4. MPC880 Block Diagram
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1-10
Freescale Semiconductor
MPC885 Overview
The MPC875 block diagram is shown in Figure 1-7.
Instruction
Bus
8-Kbyte
Instruction Cache
System Interface Unit (SIU)
Unified
Bus
Instruction MMU
32-Entry ITLB
Embedded
MPC8xx
Processor
Core
Memory Controller
Internal
External
Bus Interface Bus Interface
Unit
Unit
8-Kbyte
Data Cache
Load/Store
Bus
System Functions
Data MMU
32-Entry DTLB
PCMCIA-ATA Interface
Slave / Master IF
Security Engine
Fast Ethernet
Controller
Controller
DMAs
DMAs
DMAs
Channel
AESU
DEU
MDEU
FIFOs
10/100
Base-T
Media Access
Control
Parallel I/O
4
Timers
4 Baud Rate
Generators
Parallel Interface Port
MIII / RMII
USB
Timers
Interrupt
8-Kbyte
Controllers Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
SCC4
SMC1
Virtual IDMA
and
Serial DMAs
SPI
I2C
Time-Slot Assigner
Serial Interface
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Freescale Semiconductor
1-11
MPC885 Overview
16-Kbyte
Instruction Cache
Instruction
Bus
Embedded
MPC8xx
Processor
Core
System Interface Unit (SIU)
Unified
Bus
Instruction MMU
32-Entry ITLB
Load/Store
Bus
Memory Controller
Internal
External
Bus Interface Bus Interface
Unit
Unit
8-Kbyte
Data Cache
System Functions
Data MMU
32-Entry DTLB
PCMCIA-ATA Interface
Fast Ethernet
Controller
DMAs
FIFOs
10/100
Base-T
Media Access
Control
Parallel I/O
4
Timers
4 Baud Rate
Generators
Parallel Interface Port
Timers
and UTOPIA
Interrupt
8-Kbyte
Controllers Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
16 Virtual
Serial
and
2
Independent
DMA
Channels
MII
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I 2C
Time Slot Assigner
Serial Interface
Figure 1-5. MPC866P Block Diagram
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Freescale Semiconductor
MPC885 Overview
16-Kbyte
Instruction Cache
Instruction
Bus
Embedded
MPC8xx
Processor
Core
System Interface Unit (SIU)
Unified
Bus
Instruction MMU
32-Entry ITLB
Load/Store
Bus
Memory Controller
Internal
External
Bus Interface Bus Interface
Unit
Unit
8-Kbyte
Data Cache
System Functions
Data MMU
32-Entry DTLB
PCMCIA-ATA Interface
Fast Ethernet
Controller
DMAs
FIFOs
10/100
Base-T
Media Access
Control
Parallel I/O
4
Timers
4 Baud Rate
Generators
Parallel Interface Port
Timers
and UTOPIA
Interrupt
8-Kbyte
Controllers Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
16 Virtual
Serial
and
2
Independent
DMA
Channels
MII
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I 2C
Time Slot Assigner
Serial Interface
Figure 1-6. MPC866P Block Diagram
Figure 1-7. MPC875 Block Diagram
The MPC870 block diagram is shown in Figure 1-9.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
1-13
MPC885 Overview
16-Kbyte
Instruction Cache
Instruction
Bus
Embedded
MPC8xx
Processor
Core
System Interface Unit (SIU)
Unified
Bus
Instruction MMU
32-Entry ITLB
Load/Store
Bus
Memory Controller
Internal
External
Bus Interface Bus Interface
Unit
Unit
8-Kbyte
Data Cache
System Functions
Data MMU
32-Entry DTLB
PCMCIA-ATA Interface
Fast Ethernet
Controller
DMAs
FIFOs
10/100
Base-T
Media Access
Control
Parallel I/O
4
Timers
4 Baud Rate
Generators
Parallel Interface Port
Timers
and UTOPIA
Interrupt
8-Kbyte
Controllers Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
16 Virtual
Serial
and
2
Independent
DMA
Channels
MII
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I 2C
Time Slot Assigner
Serial Interface
Figure 1-8. MPC866P Block Diagram
MPC885 PowerQUICC Family Reference Manual, Rev. 2
1-14
Freescale Semiconductor
MPC885 Overview
Instruction
Bus
8-Kbyte
Instruction Cache
System Interface Unit (SIU)
Unified
Bus
Instruction MMU
32-Entry ITLB
Embedded
MPC8xx
Processor
Core
Memory Controller
Internal
External
Bus Interface Bus Interface
Unit
Unit
8-Kbyte
Data Cache
Load/Store
Bus
System Functions
Data MMU
32-Entry DTLB
PCMCIA-ATA Interface
Slave / Master IF
Fast Ethernet
Controller
DMAs
DMAs
FIFOs
10/100
Base-T
Media Access
Control
Parallel I/O
4
Timers
4 Baud Rate
Generators
Parallel Interface Port
MIII / RMII
Timers
USB
Interrupt
8-Kbyte
Controllers Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
SMC1
Virtual IDMA
and
Serial DMAs
SPI
I2C
Serial Interface
Figure 1-9. MPC870 Block Diagram
1.2
Embedded MPC8xx Core
The MPC885 family integrates an embedded MPC8xx core with high-performance, low-power
peripherals to extend the Freescale data communications family of embedded processors farther into
high-end communications and networking products.
The core is compliant with the UISA (user instruction set architecture) portion of the PowerPC
architecture. It has an integer unit (IU) and a load/store unit (LSU) that execute all integer and load/store
operations in hardware. The core supports integer operations on a 32-bit internal data path and 32-bit
arithmetic hardware. The core interface to the internal and external buses is 32 bits wide.
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1-15
MPC885 Overview
The IU uses thirty-two 32-bit GPRs for source and target operands. Typically, it can execute one integer
instruction each clock cycle. Each element in the integer block is clocked only when valid data is in the
data queue and is ready for operation. This holds power consumption of the device to the absolute
minimum.
The core is integrated with MMUs as well as instruction and data caches. Each MMU provides a 32-entry,
fully-associative instruction and data TLB, with multiple page sizes of 4, 16, 512, and 256 Kbytes and
8 Mbytes. It supports 16 virtual address spaces with 8 protection groups. Three special scratch registers
support software table search and update operations.
The instruction cache is two-way, set associative with physical addressing. It allows single-cycle access
on hits with no added latency for misses. It has four words per block, supporting a four-beat burst line fill
using an LRU (least recently used) replacement algorithm. The cache can be locked on a per-cache-block
basis for application-critical routines.
The data cache is two-way, set associative with physical addressing. It allows single-cycle accesses on hits
with one added clock latency for misses. It has four words per cache block, supporting burst line fill using
LRU replacement. The cache can be locked on a per-block basis for application critical routines. The data
cache can be programmed through the MMU to support copy-back or write-through. Cache-inhibit mode
can be programmed per MMU page.
The debug interface provides debug capabilities without degrading operation speed. This interface
supports six watchpoint pins that detect software events. Four of its eight internal comparators operate on
the effective address on the address bus, two operate on the effective address on the data address bus, and
two operate on the data bus. The core can make comparisons, using operators =, ≠, <, and >, to generate
watchpoints. Each watchpoint can then generate a breakpoint that can be configured to trigger in a
programmable number of events.
1.3
System Interface Unit (SIU)
The SIU on the MPC885 family integrates general-purpose features useful in almost any 32-bit processor
system. Dynamic bus sizing allows 8-, 16-, and 32-bit peripherals and memory to exist in the 32-bit system
bus mode.
The SIU also provides power management functions, reset control, decrementer, and timebase.
The memory controller supports up to eight memory banks with glueless interfaces to DRAM, SRAM,
SSRAM, EPROM, Flash EPROM, SDRAM, EDO, and other peripherals with 2-clock-cycle access to
external SRAM and bursting support. It provides variable block sizes from 32 Kbytes to 256 Mbytes. The
memory controller provides 0–30 wait states for each memory bank and can use address type matching to
qualify each memory bank access. It provides four byte-enable signals, an output-enable signal, and a boot
chip select available at reset.
The DRAM interface supports port sizes of 8, 16, and 32 bits. Memory banks can be defined in depths of
256 or 512 Kbytes or 1, 2, 4, 8, 16, 32, or 64 Mbytes for all port sizes. The memory depth can be 64 and
128 Kbytes for 8-bit memory or 128 and 256 Mbytes for 32-bit memory. The DRAM controller supports
page-mode access for successive transfers within bursts. The MPC885 supports a glueless interface to one
bank of DRAM, while external buffers are required for additional memory banks. The refresh unit
provides CAS before RAS, a programmable refresh timer, refresh active during external reset, disable
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Freescale Semiconductor
MPC885 Overview
refresh mode, and stacking up to seven refresh cycles. The DRAM interface uses a programmable state
machine to support almost any memory interface.
1.4
PCMCIA Controller
The PCMCIA interface is a master (socket) controller and is compliant with release 2.1. The interface
supports up to two independent PCMCIA sockets requiring only external transceivers/buffers. The
interface provides eight memory or I/O windows where each window can be allocated to a particular
socket. If only one PCMCIA port is used, the unused port may be used as general-purpose input with
interrupt capability.
1.5
Power Management
The MPC885 family supports two power management features including Normal High and Normal Low
power modes. Full on mode leaves the MPC885 processor fully powered with all internal units operating
at the full processor speed. A gear mode is determined by a clock divider, allowing the operating system
to reduce the processor’s operational frequency and operate in Normal Low mode.
1.6
Security Engine
A block diagram of the Security Engine’s internal architecture is shown in Figure 1-10. The 8xx bus
interface (8xx/IF) module is designed to transfer 32-bit words between the 8xx bus and any register inside
the Security Engine core.
An operation begins with a write of a pointer to the crypto-channel fetch register which points to a data
packet descriptor. The channel requests the descriptor and decodes the operation to be performed. The
channel then requests the controller to assign crypto execution units and fetch the keys, IVs, and data
needed to perform the given operation. The controller satisfies the requests by assigning execution units
to the channel and by making requests to the master interface. As data is processed, it is written to the
individual execution unit’s output buffer and then back to system memory through the 8xx/IF module.
CryptoChannel
8xx
Bus/IF
Unit
FIFO
FIFO
Controller
DEU
AESU
MDEU
FIFO
Figure 1-10. Security Engine Functional Blocks
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1-17
MPC885 Overview
1.7
Fast Ethernet Controller (FEC)
The FECs comply with the IEEE 802.3 specification for 10- and 100-Mbps connectivity. Full-duplex
100-Mbps operation is supported at system clock rates of 40 MHz and higher. A 25-MHz system clock
supports 10-Mbps operation or half-duplex 100-Mbps operation.
The implementation of bursting DMA reduces bus usage. Independent DMA channels for accessing BDs
and transmit and receive data minimize latency and FIFO depth requirements.
Transmit and receive FIFOs further reduce bus usage by localizing all collisions to the FEC. Transmit
FIFOs maintain a full collision window of transmit frame data, eliminating the need for repeated DMA
over the system bus when collisions occur. On the receive side, a full collision window of data is received
before any receive data is transferred into system memory, allowing the FIFO to be flushed in the event of
a runt or collided frame, with no DMA activity. However, external memory for buffers and BDs is
required; on-chip FIFOs are designed only to compensate for collisions and for system bus latency.
Independent TxBD and RxBD rings in external memory allow nearly unlimited flexibility in memory
management of transmit and receive data frames. External memory is inexpensive, and because BD rings
in external memory have no inherent size limitations, memory management can be easily optimized to
system needs.
1.8
Universal Serial Bus (USB)
The universal serial bus (USB) is an industry-standard extension to the PC architecture. The USB
controller on the MPC885 family supports data exchange between a wide range of simultaneously
accessible peripherals. Attached peripherals share USB bandwidth through a host-scheduled, token-based
protocol.
The USB physical interconnect is a tiered-star topology and the center of each star is a hub. Each wire
segment is a point-to-point connection between the host and a hub or function, or a hub connected to
another hub or a function. The USB transfers signal and power over a four-wire cable, and the signaling
occurs over two wires and point-to-point segments. The USB full-speed signaling bit rate is 12 Mbps.
Also, a limited-capability low-speed signalling mode is defined at 1.5 Mbps. Refer to the USB
Specification Revision 1.1 and Revision 2.0 for further details. They can be downloaded from
http://www.usb.org.
The MPC885 USB controller consists of a transmitter module, receiver module, and two protocol state
machines. The protocol state machines control the receiver and transmitter modules. One state machine
implements the function state diagram and the other implements the host state diagram. The USB
controller can implement a USB function endpoint, a USB host, or both for testing purposes (loop-back
diagnostics).
1.9
Communications Processor Module (CPM)
The MPC885 family is the next generation MPC8xx family of devices. Like its predecessor it implements
a dual-processor architecture, which provides both a high-performance, general-purpose processor for
application programming use as well as a special-purpose communication processor (CPM) uniquely
designed for communications applications.
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Freescale Semiconductor
MPC885 Overview
The CPM contains features that, like its predecessor, allow the MPC885 family to excel in
communications and networking products. These features are grouped as follows:
• Communications processor (CP)
• Independent DMA (SDMA) controllers
• Four general-purpose timers
The CP provides the communication features of the MPC885 family. Included are a RISC processor, three
serial communication controllers (SCCs), two serial management controllers (SMCs), a serial peripheral
interface (SPI), an I2C interface, 8 Kbytes of dual-port RAM, an interrupt controller, a time-slot assigner,
five parallel ports, a parallel interface port, four independent baud rate generators, and serial DMA
channels to support the SCCs, SMCs, SPI, and I2C.
The SDMAs provide two channels of general-purpose DMA capability for each communications channel.
They offer high-speed transfers, 32-bit data movement, buffer chaining, and independent request and
acknowledge logic.
The four general-purpose timers on the CPM are identical to the timers found on all of the MPC8xx
devices, and support the internal cascading of two timers to form a 32-bit timer.
1.10
ATM Capabilities
The MPC885 family can be used as an adaptable ATM controller suited for a variety of applications,
including the following:
• DSLAM line cards
• Access concentrators
• LAN/WAN switches
• Hubs/Gateways
• PBX systems
• Wireless base stations
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
1-19
MPC885 Overview
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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Freescale Semiconductor
Chapter 2
Memory Map
Each memory resource in the MPC885 is mapped within a contiguous block of 16 Kbytes of memory. The
location of this block within the global 4-Gbyte physical memory space can be mapped on 64-Kbyte
resolution through an implementation-specific special-purpose register (SPR) called the internal memory
map register (IMMR). See Section 10.4.1, “Internal Memory Map Register (IMMR).” Table 2-1 defines
the internal memory map, and Table 2-2 defines the internal security engine memory map.
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00)
Offset
Name
Size
Section/Page
General System Interface Unit
000
SIUMCR—SIU module configuration register
32 bits
10.4.2/10-5
004
SYPCR—System protection control register
32 bits
10.4.3/10-7
Reserved
6 bytes
—
00E
SWSR—Software service register
16 bits
10.7.1/10-21
010
SIPEND—SIU interrupt pending register
32 bits
10.5.3/10-13
014
SIMASK—SIU interrupt mask register
32 bits
10.5.4.2/10-16
018
SIEL—SIU interrupt edge/level register
32 bits
10.5.4.3/10-17
01C
SIVEC—SIU interrupt vector register
32 bits
10.5.4.4/10-17
020
TESR—Transfer error status register
32 bits
10.4.4/10-8
12 bytes
—
32 bits
19.2.1/19-4
76 bytes
—
008–00D
024–02F
030
034–07F
Reserved
SDCR—SDMA configuration register
Reserved
PCMCIA
080
PBR0—PCMCIA interface base register 0
32 bits
16.4.5/16-14
084
POR0—PCMCIA interface option register 0
32 bits
16.4.5/16-14
088
PBR1—PCMCIA interface base register 1
32 bits
16.4.5/16-14
08C
POR1—PCMCIA interface option register 1
32 bits
16.4.6/16-14
090
PBR2—PCMCIA interface base register 2
32 bits
16.4.5/16-14
094
POR2—PCMCIA interface option register 2
32 bits
16.4.6/16-14
098
PBR3—PCMCIA interface base register 3
32 bits
16.4.5/16-14
09C
POR3—PCMCIA interface option register 3
32 bits
16.4.6/16-14
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
2-1
Memory Map
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
Name
Size
Section/Page
0A0
PBR4—PCMCIA interface base register 4
32 bits
16.4.5/16-14
0A4
POR4—PCMCIA interface option register 4
32 bits
16.4.6/16-14
0A8
PBR5—PCMCIA interface base register 5
32 bits
16.4.5/16-14
0AC
POR5—PCMCIA interface option register 5
32 bits
16.4.6/16-14
0B0
PBR6—PCMCIA interface base register 6
32 bits
16.4.5/16-14
0B4
POR6—PCMCIA interface option register 6
32 bits
16.4.6/16-14
0B8
PBR7—PCMCIA interface base register 7
32 bits
16.4.5/16-14
0BC
POR7—PCMCIA interface option register 7
32 bits
16.4.6/16-14
32 bytes
—
0C0–0DF
Reserved
0E0
PGCRA—PCMCIA interface general control register
A
32 bits
16.4.4/16-13
0E4
PGCRB—PCMCIA interface general control register
B
32 bits
16.4.4/16-13
0E8
PSCR—PCMCIA interface status changed register
32 bits
16.4.2/16-10
Reserved
4 bytes
—
PIPR—PCMCIA interface input pins register
32 bits
16.4.1/16-8
Reserved
4 bytes
—
PER—PCMCIA interface enable register
32 bits
16.4.3/16-11
Reserved
4 bytes
—
0EC–0EF
0F0
0F4–0F7
0F8
0FC–0FF
Memory Controller
100
BR0—Base register bank 0
32 bits
15.4.1/15-8
104
OR0—Option register bank 0
32 bits
15.4.2/15-11
108
BR1—Base register bank 1
32 bits
15.4.1/15-8
10C
OR1—Option register bank 1
32 bits
15.4.2/15-11
110
BR2—Base register bank 2
32 bits
15.4.1/15-8
114
OR2—Option register bank 2
32 bits
15.4.2/15-11
118
BR3—Base register bank 3
32 bits
15.4.1/15-8
11C
OR3—Option register bank 3
32 bits
15.4.2/15-11
120
BR4—Base register bank 4
32 bits
15.4.1/15-8
124
OR4—Option register bank 4
32 bits
15.4.2/15-11
128
BR5—Base register bank 5
32 bits
15.4.1/15-8
12C
OR5—Option register bank 5
32 bits
15.4.2/15-11
130
BR6—Base register bank 6
32 bits
15.4.1/15-8
MPC885 PowerQUICC Family Reference Manual, Rev. 2
2-2
Freescale Semiconductor
Memory Map
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
Name
Size
Section/Page
134
OR6—Option register bank 6
32 bits
15.4.2/15-11
138
BR7—Base register bank 7
32 bits
15.4.1/15-8
13C
OR7—Option register bank 7
32 bits
15.4.2/15-11
36 bytes
—
140–163
Reserved
164
MAR—Memory address register
32 bits
15.4.7/15-17
168
MCR—Memory command register
32 bits
15.4.5/15-15
Reserved
4 bytes
—
170
MAMR—Machine A mode register
32 bits
15.4.4/15-14
174
MBMR—Machine B mode register
32 bits
15.4.4/15-14
178
MSTAT—Memory status register
16 bits
15.4.3/15-13
17A
MPTPR—Memory periodic timer prescaler
16 bits
15.4.8/15-18
17C
MDR—Memory data register
32 bits
15.4.6/15-17
128 bytes
—
16C–16F
180–1FF
Reserved
System Integration Timers
200
TBSCR—Timebase status and control register
16 bits
10.9.3/10-25
Reserved
2 bytes
—
204
TBREFA—Timebase reference register A
32 bits
10.9.2/10-24
208
TBREFB—Timebase reference register B
32 bits
202–203
20C–21F
Reserved
20 bytes
—
220
Reserved
16 bits
—
222–223
Reserved
2 bytes
—
224
Reserved
32 bits
—
228
Reserved
32 bits
—
22C
Reserved
32 bits
—
230–23F
Reserved
16 bytes
—
PISCR—Periodic interrupt status and control register
16 bits
10.10.1/10-26
Reserved
2 bytes
—
244
PITC—Periodic interrupt count registerA
32 bits
10.10.2/10-27
248
PITR—Periodic interrupt timer register
32 bits
10.10.3/10-28
52 bytes
—
240
242–243
24C–27F
Reserved
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
2-3
Memory Map
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
Name
Size
Section/Page
Clocks and Reset
280
SCCR—System clock reset control register
32 bits
14.6.1/14-18
284
PLPRCR—PLL and reset control register
32 bits
14.6.2/14-21
288
RSR—Reset status register
32 bits
11.2/11-4
116 bytes
—
28C–2FF
Reserved
System Integration Timers Keys
300
TBSCRK—Timebase status and control register key
32 bits
10.9.3/10-25
304
TBREFAK—Timebase reference register A key
32 bits
10.9.2/10-24
308
TBREFBK—Timebase reference register B key
32 bits
10.9.2/10-24
30C
TBK—Timebase/decrementer register key
32 bits
10.8.1/10-22
310–31F
Reserved
16 bytes
—
320
Reserved
32 bits
—
324
Reserved
32 bits
—
328
Reserved
32 bits
—
32C
Reserved
32 bits
—
330–33F
Reserved
16 bytes
—
340
PISCRK—Periodic interrupt status and control
register key
32 bits
10.10.1/10-26
344
PITCK—Periodic interrupt count register key
32 bits
10.10.2/10-27
56 bytes
—
348–37F
Reserved
Clocks and Reset Keys
380
SCCRK—System clock control key
32 bits
10.4.5/10-9
384
PLPRCRK—PLL and reset control register key
32 bits
10.4.5/10-9
388
RSRK—Reset status register key
32 bits
10.4.5/10-9
1236 bytes
—
8 bits
32.4.1/32-6
3 bytes
—
8 bits
32.4.2/32-7
3 bytes
—
8 bits
32.4.3/32-7
3 bytes
—
38C–85F
Reserved
I2C Controller
860
861–863
864
865–867
868
869–86B
I2MOD—I2C mode register
Reserved
I2ADD—I2C address register
Reserved
I2BRG—I2C BRG register
Reserved
MPC885 PowerQUICC Family Reference Manual, Rev. 2
2-4
Freescale Semiconductor
Memory Map
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
Size
Section/Page
8 bits
32.4.5/32-8
3 bytes
—
8 bits
32.4.4/32-7
3 bytes
—
8 bits
32.4.4/32-7
139 bytes
—
Reserved
4 bytes
—
904
SDAR—SDMA address register
32 bits
19.2.4/19-6
908
SDSR—SDMA status register
8 bits
19.2.2/19-5
3 bytes
—
8 bits
19.2.3/19-5
3 bytes
—
8 bits
19.3.3.2/19-9
3 bytes
—
8 bits
19.3.3.3/19-9
3 bytes
—
8 bits
19.3.3.2/19-9
3 bytes
—
8 bits
19.3.3.3/19-9
19 bytes
—
86C
86D–86F
870
871–873
874
875–8FF
Name
I2COM—I2C command register
Reserved
2
I2CER—I C event register
Reserved
2
I2CMR—I C mask register
Reserved
DMA
900–903
909–90B
90C
90D–90F
910
911–913
914
915–917
918
919–91B
91C
91D–92F
Reserved
SDMR—SDMA mask register
Reserved
IDSR1—IDMA1 status register
Reserved
IDMR1—IDMA1 mask register
Reserved
IDSR2—IDMA2 status register
Reserved
IDMR2—IDMA2 mask register
Reserved
Communications Processor Module Interrupt Control
930
932–93F
CIVR—CPM interrupt vector register
Reserved
16 bits
35.5.5/35-9
14 bytes
—
940
CICR—CPM interrupt configuration register
32 bits
35.5.1/35-6
944
CIPR—CPM interrupt pending register
32 bits
35.5.2/35-8
948
CIMR—CPM interrupt mask register
32 bits
35.5.3/35-9
94C
CISR—CPM in-service register
32 bits
35.5.4/35-9
Input/Output Port
950
PADIR—Port A data direction register
16 bits
34.2.1.3/34-4
952
PAPAR—Port A pin assignment register
16 bits
34.2.1.4/34-5
954
PAODR—Port A open drain register
16 bits
34.2.1.1/34-3
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
2-5
Memory Map
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
Size
Section/Page
PADAT—Port A data register
16 bits
34.2.1.2/34-4
Reserved
8 bytes
—
960
PCDIR—Port C data direction register
16 bits
34.4.1.2/34-14
962
PCPAR—Port C pin assignment register
16 bits
34.4.1.3/34-15
964
PCSO—Port C special options register
16 bits
34.4.1.4/34-16
966
PCDAT—Port C data register
16 bits
34.4.1.1/34-14
968
PCINT—Port C interrupt control register
16 bits
34.4.1.5/34-17
Reserved
6 bytes
—
970
PDDIR—Port D data direction register
16 bits
34.5.1/34-18
972
PDPAR—Port D pin assignment register
16 bits
34.5.1/34-18
974
Reserved
2 bytes
—
976
PDDAT—Port D data register
16 bits
34.5.1/34-18
978–97F
UTMODE—UTOPIA mode register
4 bytes
43.2/43-1
97C–97F
Reserved
4 bytes
—
956
958–95F
96A–96F
Name
CPM General-Purpose Timers
980
982–98F
TGCR—Timer global configuration register
Reserved
16 bits
17.2.3.1/17-8
14 bytes
—
990
TMR1—Timer 1 mode register
16 bits
17.2.4/17-9
992
TMR2—Timer 2 mode register
16 bits
17.2.4/17-9
994
TRR1—Timer 1 reference register
16 bits
17.2.4.1/17-10
996
TRR2—Timer 2 reference register
16 bits
17.2.4.1/17-10
998
TCR1—Timer 1 capture register
16 bits
17.2.4.2/17-10
99A
TCR2—Timer 2 capture register
16 bits
17.2.4.2/17-10
99C
TCN1—Timer 1 counter
16 bits
17.2.4.3/17-10
99E
TCN2—Timer 2 counter
16 bits
17.2.4.3/17-10
9A0
TMR3—Timer 3 mode register
16 bits
17.2.4/17-9
9A2
TMR4—Timer 4 mode register
16 bits
17.2.4/17-9
9A4
TRR3—Timer 3 reference register
16 bits
17.2.4.1/17-10
9A6
TRR4—Timer 4 reference register
16 bits
17.2.4.1/17-10
9A8
TCR3—Timer 3 capture register
16 bits
17.2.4.2/17-10
9AA
TCR4—Timer 4 capture register
16 bits
17.2.4.2/17-10
9AC
TCN3—Timer 3 counter
16 bits
17.2.4.3/17-10
MPC885 PowerQUICC Family Reference Manual, Rev. 2
2-6
Freescale Semiconductor
Memory Map
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
Name
Size
Section/Page
9AE
TCN4—Timer 4 counter
16 bits
17.2.4.3/17-10
9B0
TER1—Timer 1 event register
16 bits
17.2.4.4/17-11
9B2
TER2—Timer 2 event register
16 bits
17.2.4.4/17-11
9B4
TER3—Timer 3 event register
16 bits
17.2.4.4/17-11
9B6
TER4—Timer 4 event register
16 bits
17.2.4.4/17-11
Reserved
8 bytes
—
9B8–9BF
Communications Processor (CP)
9C0
CPCR—CP command register
16 bits
18.6.3/18-7
Reserved
2 bytes
—
9C4
RCCR—RISC controller configuration register
16 bits
18.6.1/18-5
9C6
Reserved
8 bits
—
9C7
RMDS—RISC microcode development support
control register
8 bits
18.6.2/18-6
Reserved
4 bytes
—
9CC
RCTR1—RISC controller trap register 1
16 bits
Used only by optional RAM
microcode
9CE
RCTR2—RISC controller trap register 2
16 bits
Used only by optional RAM
microcode
9D0
RCTR3—RISC controller trap register 3
16 bits
Used only by optional RAM
microcode
9D2
RCTR4—RISC controller trap register 4
16 bits
Used only by optional RAM
microcode
Reserved
2 bytes
—
RTER—RISC timer event register
16 bits
18.8.4/18-17
Reserved
2 bytes
—
RTMR—RISC timers mask register
16 bits
18.8.4/18-17
20 bytes
—
9C2–9C3
9C8–9CB
9D4–9D5
9D6
9D8–9D9
9DA
9DC–9EF
Reserved
Baud Rate Generators
9F0
BRGC1—BRG1 configuration register
32 bits
20.4.1/20-37
9F4
BRGC2—BRG2 configuration register
32 bits
20.4.1/20-37
9F8
BRGC3—BRG3 configuration register
32 bits
20.4.1/20-37
9FC
BRGC4—BRG4 configuration register
32 bits
20.4.1/20-37
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
2-7
Memory Map
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
Name
Size
Section/Page
Universal Serial Bus (USB)
A00
USMOD — USB mode register
8 bits
A01
USADDR — USB slave address register
8 bits
A02
USCOM — USB command register
8 bits
A03
Reserved
8 bits
A04
USEP0 — USB end point 0 register
16 bits
A06
USEP1 — USB end point 1 register
16 bits
A08
USEP2 — USB end point 2 register
16 bits
A0A
USEP3 — USB end point 3 register
16 bits
Reserved
32 bits
A10
USBER — USB event register
16 bits
A12
Reserved
16 bits
A14
USBMR — USB mask register
16 bits
A16
Reserved
8 bits
A17
USBS — USB status register
8 bits
A0C–A0F
A18–A1F
Reserved
8 bytes
Serial Communications Controller 2 (SCC2)
A20
GSMR_L2—SCC2 general mode register
32 bits
21.2.1/21-3
A24
GSMR_H2—SCC2 general mode register
32 bits
21.2.1/21-3
A28
PSMR2—SCC2 protocol-specific mode register
16 bits
21.2.2/21-10
22.16/22-13 (UART)
25.13.1/25-8 (Asynchronous HDLC)
26.11/26-10 (BISYNC)
27.17/27-15 (Ethernet)
28.8/28-7 (Transparent)
Reserved
16 bits
—
A2C
TODR2—SCC2 transmit on demand register
16 bits
21.2.4/21-10
A2E
DSR2—SCC2 data synchronization register
16 bits
21.2.3/21-10
A30
SCCE2—SCC2 event register
16 bits
22.20/22-22 (UART)
23.11/23-12 (HDLC)
25.13.1/25-8 (Asynchronous HDLC)
26.15/26-15 (BISYNC)
28.12/28-11 (Transparent)
Reserved
16 bits
—
A2A–A2B
A32–A33
MPC885 PowerQUICC Family Reference Manual, Rev. 2
2-8
Freescale Semiconductor
Memory Map
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
Name
Size
Section/Page
A34
SCCM2—SCC2 mask register
16 bits
22.20/22-22 (UART)
23.12/23-14 (HDLC)
25.13.1/25-8 (Asynchronous HDLC)
26.15/26-15 (BISYNC)
28.12/28-11 (Transparent)
A36
Reserved
8 bits
—
A37
SCCS2—SCC2 status register
8 bits
22.20/22-22 (UART)
23.12/23-14 (HDLC)
26.15/26-15 (BISYNC)
28.12/28-11 (Transparent)
Reserved
8 bytes
—
A38–A3F
Serial Communications Controller 3 (SCC3)
A40
GSMR_L3—SCC3 general mode register
32 bits
21.2.1/21-3
A44
GSMR_H3—SCC3 general mode register
32 bits
21.2.1/21-3
A48
PSMR3—SCC3 protocol specific mode register
16 bits
21.2.2/21-10
22.16/22-13 (UART)
25.13.1/25-8 (Asynchronous HDLC)
26.11/26-10 (BISYNC)
27.17/27-15 (Ethernet)
28.8/28-7 (Transparent)
Reserved
2 bytes
—
A4C
TODR3—SCC3 transmit on demand register
16 bits
21.2.4/21-10
A4E
DSR3—SCC3 data synchronization register
16 bits
21.2.3/21-10
A50
SCCE3—SCC3 event register
16 bits
Reserved
2 bytes
A54
SCCM3—SCC3 mask register
16 bits
22.20/22-22 (UART)
23.12/23-14 (HDLC)
25.13/25-8 (Asynchronous HDLC)
26.15/26-15 (BISYNC)
28.12/28-11 (Transparent)
A56
Reserved
1 byte
—
A57
SCCS3—SCC3 status register
8 bits
22.20/22-22 (UART)
23.12/23-14 (HDLC)
26.15/26-15 (BISYNC)
28.12/28-11 (Transparent)
8 bytes
—
A4A–A4B
A52–A53
A58–A5F
Reserved
Serial Communications Controller 4 (SCC4)
A60
GSMR_L4—SCC4 general mode register
32 bits
21.2.1/21-3
A64
GSMR_H4—SCC4 general mode register
32 bits
21.2.1/21-3
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
2-9
Memory Map
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
Size
Section/Page
PSMR4—SCC4 protocol specific mode register
16 bits
21.2.2/21-10
22.16/22-13 (UART)
25.13.1/25-8 (Asynchronous HDLC)
26.11/26-10 (BISYNC)
27.17/27-15 (Ethernet)
28.8/28-7 (Transparent)
Reserved
2 bytes
—
A6C
TODR4—SCC4 transmit on demand register
16 bits
21.2.4/21-10
A6E
DSR4—SCC4 data synchronization register
16 bits
21.2.3/21-10
A70
SCCE4—SCC4 event register
16 bits
Reserved
2 bytes
A74
SCCM4—SCC4 mask register
16 bits
22.20/22-22 (UART)
23.12/23-14 (HDLC)
25.13/25-8 (Asynchronous HDLC)
26.15/26-15 (BiSYNC)
28.12/28-11 (Transparent)
A76
Reserved
1 byte
—
A77
SCCS4—SCC4 status register
8 bits
22.20/22-22 (UART)
23.12/23-14 (HDLC)
26.15/26-15 (BiSYNC)
28.12/28-11 (Transparent)
10 bytes
—
A68
A6A–A6B
A72–A73
A78–A81
Name
Reserved
Serial Management Controller 1 (SMC1)
A82
A84–A85
A86
A87–A89
A8A
A8B–A91
SMCMR1—SMC1 mode register
16 bits
29.2.1/29-2
Reserved
2 bytes
—
8 bits
29.3.12/29-18 (UART)
29.4.11/29-29 (Transparent)
29.5.9/29-35 (GCI)
3 bytes
—
8 bits
29.3.12/29-18 (UART)
29.4.11/29-29 (Transparent)
29.5.9/29-35 (GCI)
7 bytes
—
SMCE1—SMC1 event register
Reserved
SMCM1—SMC1 mask register
Reserved
Serial Management Controller 2 (SMC2)
A92
A94–A95
A96
A97–A99
SMCMR2—SMC2 mode register
16 bits
29.2.1/29-2
Reserved
2 bytes
—
8 bits
29.3.12/29-18 (UART)
29.4.11/29-29 (Transparent)
29.5.9/29-35 (GCI)
3 bytes
—
SMCE2—SMC2 event register
Reserved
MPC885 PowerQUICC Family Reference Manual, Rev. 2
2-10
Freescale Semiconductor
Memory Map
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
A9A
A9B–A9F
Name
SMCM2—SMC2 mask register
Reserved
Size
Section/Page
8 bits
29.3.12/29-18 (UART)
29.4.11/29-29 (Transparent)
29.5.9/29-35 (GCI)
5 bytes
—
Serial Peripheral Interface (SPI)
AA0
AA2–AA5
AA6
AA7–AA9
AAA
AAB–AAC
AAD
AAE–AB1
SPMODE—SPI mode register
16 bits
30.4.1/30-6
Reserved
4 bytes
—
8 bits
30.4.2/30-8
3 bytes
—
8 bits
30.4.2/30-8
2 bytes
—
8 bits
30.4.3/30-9
4 bytes
—
SPIE—SPI event register
Reserved
SPIM—SPI mask register
Reserved
SPCOM—SPI command register
Reserved
Parallel Interface Port (PIP) and Port B
AB2
AB4–AB5
AB6
PIPC—PIP configuration register
16 bits
33.4.1/33-8
Reserved
2 bytes
—
PTPR—PIP timing parameters register
16 bits
33.4.4/33-10
Port B Registers
AB8
PBDIR—Port B data direction register
32 bits
34.3.1.3/34-10
ABC
PBPAR—Port B pin assignment register
32 bits
34.3.1.4/34-11
AC0
PBODR—Port B open drain register
32 bits
34.3.1.1/34-9
AC4
PBDAT—Port B data register
32 bits
34.3.1.2/34-9
Port E Registers
AC8
PEDIR — Port E data direction register
32 bits
34.6.1.3/34-23
ACC
PEPAR — Port E data assignment register
32 bits
34.6.1.4/34-24
ADO
PESO — Port E special options
32 bits
34.6.2/34-25
AD4
PEODR — Port E open drain register
32 bits
34.6.1.1/34-22
AD8
PEDAT — Port E data register
32 bits
34.5.1.1/34-18
Communications Processor Timing Register - Contains RMII Timing for the FECs
ADC
CPTR — CPTR Register
32 bits
45.3.1/45-11,
52.1/52-1
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
2-11
Memory Map
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
Name
Size
Section/Page
Serial Interface (SI)
AE0
SIMODE—SI mode register
32 bits
20.2.4/20-15
AE4
SIGMR—SI global mode register
8 bits
20.2.4.2/20-17
AE5
Reserved
8 bits
—
AE6
SISTR—SI status register
8 bits
20.2.4.5/20-24
AE7
SICMR—SI command register
8 bits
20.2.4.4/20-24
Reserved
4 bytes
—
AEC
SICR—SI clock route register
32 bits
20.2.4.3/20-22
AF0
SIRP—Serial interface RAM pointer register
32 bits
20.2.4.6/20-25
AE8–AEB
AF4–BFF
Reserved
268 bytes
—
C00–DFF
SIRAM—SI routing RAM
512 bytes
20.2.3.7/20-13
E00-1FFF
Reserved
4,608 bytes
—
Fast Ethernet Controller 1 (FEC)
E00
ADDR_LOW register
32 bits
45.3.2.1/45-13
E04
ADDR_HIGH
32 bits
45.3.2.2/45-14
E08
HASH_TABLE_HIGH
32 bits
45.3.2.3/45-14
E0C
HASH_TABLE_LOW
32 bits
45.3.2.4/45-15
E10
R_DES_START
32 bits
45.3.2.5/45-16
E14
X_DES_START
32 bits
45.3.2.6/45-16
E18
R_BUFF_SIZE
32 bits
45.3.2.7/45-17
E1C–E3F
Reserved
36 bytes
—
E40
ECNTRL
32 bits
45.3.2.8/45-18
E44
IEVENT
32 bits
45.3.2.9/45-19
E48
IMASK
32 bits
45.3.2.9/45-19
E4C
IVEC
32 bits
45.3.2.10/45-20
E50
R_DES_ACTIVE
32 bits
45.3.2.11/45-21
E54
X_DES_ACTIVE
32 bits
45.3.2.12/45-22
E58–E7F
Reserved
40 bytes
—
E80
MII_DATA
32 bits
45.3.2.13/45-22
E84
MII_SPEED
32 bits
45.3.2.14/45-24
68 bytes
—
32 bits
45.3.2.15/45-25
E88–ECB
ECC
Reserved
R_BOUND
MPC885 PowerQUICC Family Reference Manual, Rev. 2
2-12
Freescale Semiconductor
Memory Map
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
ED0
Name
R_FSTART
Size
Section/Page
32 bits
45.3.2.16/45-26
ED4–EE3
Reserved
16 bytes
—
EE4
X_WMRK
32 bits
45.3.2.17/45-27
EE8
Reserved
32 bits
—
EEC
X_FSTART
32 bits
45.3.2.18/45-28
68 bytes
—
32 bits
45.3.2.19/45-29
EF0–F33
F34
Reserved
FUN_CODE
F38–F43
Reserved
12 bytes
—
F44
R_CNTRL
32 bits
45.3.2.20/45-29
F48
R_HASH
32 bits
45.3.2.21/45-30
F4C–F83
Reserved
56 bytes
—
F84
X_CNTRL
32 bits
45.3.2.22/45-31
F88–1E00
Reserved
3704 bytes
—
Fast Ethernet Controller 2 (FEC)
1E00
ADDR2_LOW register
32 bits
45.3.2.1/45-13
1E04
ADDR2_HIGH
32 bits
45.3.2.2/45-14
1E08
HASH_TABLE2_HIGH
32 bits
45.3.2.3/45-14
1E0C
HASH_TABLE2_LOW
32 bits
45.3.2.4/45-15
1E10
R2_DES_START
32 bits
45.3.2.5/45-16
1E14
X2_DES_START
32 bits
45.3.2.6/45-16
1E18
R_BUFF2_SIZE
32 bits
45.3.2.7/45-17
36 bytes
—
1E1C–1E3F Reserved
1E40
ECNTRL2
32 bits
45.3.2.8/45-18
1E44
IEVENT2
32 bits
45.3.2.9/45-19
1E48
IMASK2
32 bits
45.3.2.9/45-19
1E4C
IVEC2
32 bits
45.3.2.10/45-20
1E50
R2_DES_ACTIVE
32 bits
45.3.2.11/45-21
1E54
X2_DES_ACTIVE
32 bits
45.3.2.12/45-22
40 bytes
—
1E58–1E7F Reserved
1E80
MII2_DATA
32 bits
45.3.2.13/45-22
1E84
MII2_SPEED
32 bits
45.3.2.14/45-24
68 bytes
—
1E88–1ECB Reserved
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
2-13
Memory Map
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
Name
Size
Section/Page
1ECC
R2_BOUND
32 bits
45.3.2.15/45-25
1ED0
R2_FSTART
32 bits
45.3.2.16/45-26
16 bytes
—
1ED4–1EE3 Reserved
1EE4
X2_WMRK
32 bits
45.3.2.17/45-27
1EE8
Reserved
32 bits
—
1EEC
X2_FSTART
32 bits
45.3.2.18/45-28
68 bytes
—
32 bits
45.3.2.19/45-29
12 bytes
—
1EF0–1F33 Reserved
1F34
FUN_CODE2
1F38–1F43 Reserved
1F44
R2_CNTRL
32 bits
45.3.2.20/45-29
1F48
R2_HASH
32 bits
45.3.2.21/45-30
56 bytes
—
32 bits
45.3.2.22/45-31
120 bytes
—
1F4C–1F83 Reserved
1F84
X2_CNTRL
1F88–1FFF Reserved
Dual-Port RAM (DPRAM)
2000–2FFF Dual-port system RAM
4,096 bytes
18.7.1/18-12
3000–3BFF Dual-port system RAM expansion
3,072 bytes
18.7.1/18-12
3C00–3FFF PRAM—Dual-port parameter RAM
1,024 bytes
18.7.3/18-13
Table 2-2. Security Engine Memory Map (IMMR[14–15]=10)
SEC Lite Address
SEC Lite
Module
Description
Size1
Section/Page
4104 bytes
—
00000-01007
Reserved
01008
Controller
Interrupt Mask
64 bits
51.1.1/51-1
01010
Controller
Interrupt Status
64 bits
51.1.2/51-2
01018
Controller
Interrupt Clear
64 bits
51.1.3/51-3
01020
Controller
Identification
64 bits
51.1.4/51-6
01028–0102F
Reserved
8 bytes
—
01030
Controller
Master Control
64 bits
51.1.5/51-6
01038
Controller
Master TEA Address
64 bits
51.1.6/51-7
01040–02007
Reserved
4040 bytes
—
02008
Channel
64 bits
50.1.1/50-2
Config Register
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Memory Map
Table 2-2. Security Engine Memory Map (IMMR[14–15]=10) (continued)
SEC Lite Address
SEC Lite
Module
Description
Pointer status
Size1
Section/Page
64 bits
50.1.2/50-4
40 bytes
—
02010
Channel
02018–0203F
Reserved
02040
Channel
Current descriptor pointer
64 bits
50.1.3/50-10
02048
Channel
Fetch register
64 bits
50.1.4/50-11
02050–0207F
Reserved
48 bytes
—
02080–020BF
Channel
64 bytes
50.1.5/50-12
020C0–03FFF
Reserved
8000 bytes
—
04000
AESU
Mode register
64 bits
48.3.2/48-24
04008
AESU
Key size register
64 bits
48.3.3/48-26
04010
AESU
Data size register
64 bits
48.3.4/48-27
04018
AESU
Reset control register
64 bits
48.3.5/48-28
04020–04027
Reserved
8 bytes
—
04028
AESU
Status register
64 bits
48.3.6/48-29
04030
AESU
Interrupt status register
64 bits
48.3.7/48-30
04038
AESU
Interrupt control register
64 bits
48.3.8/48-32
04040–0404F
Reserved
16 bytes
—
04050
AESU
64 bits
48.3.9/48-34
04058–040FF
Reserved
168 bytes
—
04100
AESU
64 bits
48.3.9.1/48-34
04108–043FF
Reserved
760 bytes
—
04400–04408
AESU
12 bytes
48.3.9.4/48-36
0440C–047FF
Reserved
1012 bytes
—
04800–04FFF
AESU
FIFO
2048 bytes
48.3.9.5/48-36
05000
DEU
Mode register
64 bits
48.1.2/48-2
05008
DEU
Key size register
64 bits
48.1.3/48-3
05010
DEU
Data size register
64 bits
48.1.4/48-4
05018
DEU
Reset control register
64 bits
48.1.5/48-5
05020–05027
Reserved
8 bytes
—
05028
DEU
Status register
64 bits
48.1.6/48-6
05030
DEU
Interrupt status register
64 bits
48.1.7/48-7
05038
DEU
Interrupt control register
64 bits
48.1.8/48-9
05040–0504F
Reserved
16 bytes
—
Descriptor buffer[16]
End of message register
IV register
Key memory
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2-15
Memory Map
Table 2-2. Security Engine Memory Map (IMMR[14–15]=10) (continued)
SEC Lite Address
SEC Lite
Module
Description
Section/Page
64 bits
48.1.9/48-11
168 bytes
—
64 bits
48.1.10/48-12
760 bytes
—
05050
DEU
05058–050FF
Reserved
05100
DEU
05108–053FF
Reserved
05400
DEU
Key 1 register
64 bits
48.1.11/48-12
05408
DEU
Key 2 register
64 bits
48.1.11/48-12
05410
DEU
Key 3 register
64 bits
48.1.11/48-12
05418–057FF
Reserved
1000 bytes
—
05800–05FFF
DEU
FIFO
2048 bytes
48.1.12/48-12
06000
MDEU
Mode register
64 bits
48.2.2/48-13
06008
MDEU
Key size register
64 bits
48.2.3/48-15
06010
MDEU
Data size register
64 bits
48.2.4/48-15
06018
MDEU
Reset control register
64 bits
48.2.5/48-16
06020–06027
Reserved
8 bytes
—
06028
MDEU
Status register
64 bits
48.2.6/48-17
06030
MDEU
Interrupt status register
64 bits
48.2.7/48-18
06038
MDEU
Interrupt control register
64 bits
48.2.8/48-20
06040–0604F
Reserved
16 bytes
—
06050
MDEU
64 bits
48.2.9/48-21
06058–060FF
Reserved
168 bytes
—
06100–06127
MDEU
32 bytes
48.2.10/48-22
06128–063FF
Reserved
728 bytes
—
06400–0647F
MDEU
128 bytes
48.2.11/48-23
06480–067FF
Reserved
896 bytes
—
06800–06FFF
MDEU
2048 bytes
48.2.12/48-23
07000–07FFF
Reserved
4096 bytes
—
1
EU-Go
Size1
IV register
EU_GO
Context memory
Key memory
FIFO
The registers are 64 bits long, but the upper 32 bits of each register must be cleared when the register is initialized.
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Part II
MPC8xx Microprocessor Module
Intended Audience
This part is intended for users who need to understand the programming model of the embedded
microprocessor. It assumes some familiarity with RISC architectures.
Contents
This part describes the MPC8xx microprocessor embedded in the MPC885. It provides detailed
information about the registers and instructions that are implemented, the memory management unit
(MMU), cache model, exception model, and an overview of instruction timing. It contains the following
chapters:
• Chapter 3, “The MPC8xx Core,” provides an overview of the MPC885 core, summarizing topics
described in further detail in subsequent chapters in Part II.”
• Chapter 4, “MPC8xx Core Register Set,” describes the hardware registers accessible to the
MPC885 core. These include both architecturally-defined and MPC885-specific registers.
• Chapter 5, “MPC885 Instruction Set,” describes the instructions implemented by the MPC885.
These instructions are organized by the level of architecture in which they are
implemented—UISA, VEA, and OEA.
• Chapter 6, “Exceptions,” describes the exception model implemented on the MPC885.
• Chapter 7, “Instruction and Data Caches,” describes the organization of the on-chip instruction and
data caches, cache control, various cache operations, and the interaction between the caches, the
load/store unit (LSU), the instruction sequencer, and the system interface unit (SIU).
• Chapter 8, “Memory Management Unit,” describes how the MMU is implemented on the
MPC885. Although the MPC885 MMU is based on the PowerPC MMU model, it differs greatly
in many respects, which are described in this chapter.
• Chapter 9, “Instruction Execution Timing,” describes the MPC885 instruction unit, and provides
ways to take greatest advantage of its RISC architecture characteristics, such as pipelining and
parallel execution. It includes a table of instruction latencies and lists dependencies and potential
bottlenecks.
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II-1
Suggested Reading
This section lists additional reading that provides background for the information in this manual.
MPC8xx Documentation
Supporting documentation for the MPC885 can be accessed through the world-wide web at
http://www.freescale.com. This documentation includes technical specifications, reference materials, and
detailed application notes.
Related Documentation
The documentation is organized in the following types of documents:
• Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture
(MPEFPC32B/AD)—Describes resources defined by the PowerPC architecture.
• User’s manuals—These books provide details about individual implementations and are intended
for use with the Programming Environments Manual.
• Addenda/errata to user’s manuals—Because some processors have follow-on parts an addendum
is provided that describes the additional features and functionality changes. These addenda are
intended for use with the corresponding user’s manuals.
• Hardware specifications—Hardware specifications provide specific data regarding bus timing,
signal behavior, and AC, DC, and thermal characteristics, as well as other design considerations.
Separate hardware specifications are provided for each part described in this book.
• Technical summaries—Each device has a technical summary that provides an overview of its
features. This document is roughly the equivalent to the overview (Chapter 1) of an
implementation’s user’s manual.
• The Programmer’s Reference Guide for the PowerPC Architecture: MPCPRG/D—This concise
reference includes the register summary, memory control model, exception vectors, and the
PowerPC instruction set.
• The Programmer’s Pocket Reference Guide for the PowerPC Architecture:
MPCPRGREF/D—This foldout card provides an overview of PowerPC registers, instructions, and
exceptions for 32-bit implementations.
• Application notes—These short documents address specific design issues useful to programmers
and engineers working with Freescale processors.
Additional literature is published as new processors become available. For a current list of documentation,
refer to http://www.freescale.com.
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Conventions
This chapter uses the following notational conventions:
Bold entries in figures and tables showing registers and parameter RAM should
be initialized by the user.
Instruction mnemonics are shown in lowercase bold.
Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
Prefix to denote hexadecimal number
Prefix to denote binary number
Instruction syntax used to identify a source GPR
Instruction syntax used to identify a destination GPR
Abbreviations or acronyms for registers or buffer descriptors are shown in
uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For
example, MSR[LE] refers to the little-endian mode enable bit in the machine state
register.
In certain contexts, such as in a signal encoding or a bit field, indicates a don’t
care.
Indicates an undefined numerical value
NOT logical operator
AND logical operator
OR logical operator
Bold
mnemonics
italics
0x0
0b0
rA, rB
rD
REG[FIELD]
x
n
¬
&
|
Acronyms and Abbreviations
Table II-1 contains acronyms and abbreviations that are used in this document. Note that the
meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which
an acronym stands may not be intuitively obvious.
Table II-1. Acronyms and Abbreviated Terms
Term
Meaning
ALU
Arithmetic logic unit
BIST
Built-in self test
BPU
Branch processing unit
BUID
Bus unit ID
CR
Condition register
CRC
Cyclic redundancy check
CTR
Count register
DABR
Data address breakpoint register
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Table II-1. Acronyms and Abbreviated Terms (continued)
Term
Meaning
DAR
Data address register
DEC
Decrementer register
DMA
Direct memory access
DRAM
Dynamic random access memory
DSISR
Register used for determining the source of a DSI exception
DTLB
Data translation lookaside buffer
EA
FPR
FPSCR
Effective address
Floating-point register
Floating-point status and control register
GPR
General-purpose register
IEEE
Institute of Electrical and Electronics Engineers
ITLB
Instruction translation lookaside buffer
IU
LIFO
LR
Integer unit
Last-in-first-out
Link register
LRU
Least recently used
LSB
Least-significant byte
lsb
Least-significant bit
LSU
Load/store unit
MMU
Memory management unit
MSB
Most-significant byte
msb
Most-significant bit
MSR
Machine state register
NaN
Not a number
No-op
No operation
OEA
Operating environment architecture
PCI
Peripheral component interconnect
PVR
Processor version register
RISC
Reduced instruction set computing
RTOS
Real-time operating system
RWITM
Rx
SIMM
Read with intent to modify
Receive
Signed immediate value
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Table II-1. Acronyms and Abbreviated Terms (continued)
Term
Meaning
SPR
Special-purpose register
SPRGn
Registers available for general purposes
SR
Segment register
SRR0
Machine status save/restore register 0
SRR1
Machine status save/restore register 1
TB
Time base register
TLB
Translation lookaside buffer
Tx
Transmit
UIMM
Unsigned immediate value
UISA
User instruction set architecture
VA
Virtual address
VEA
Virtual environment architecture
XER
Register used primarily for indicating conditions such as carries and overflows for integer operations
Architecture Terminology Conventions
Table II-2 lists certain terms used in this manual that differ from the architecture terminology
conventions.
Table II-2. Terminology Conventions
The Architecture Specification
This Manual
Data storage interrupt (DSI)
DSI exception
Extended mnemonics
Simplified mnemonics
Instruction storage interrupt (ISI)
ISI exception
Interrupt
Exception
Privileged mode (or privileged state)
Supervisor-level privilege
Problem mode (or problem state)
User-level privilege
Real address
Physical address
Relocation
Translation
Storage (locations)
Memory
Storage (the act of)
Access
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Table II-3 describes instruction field notation conventions used in this manual.
Table II-3. Instruction Field Conventions
The Architecture Specification
Equivalent To:
BA, BB, BT
crbA, crbB, crbD (respectively)
BF, BFA
crfD, crfS (respectively)
D
d
DS
ds
FLM
FM
FXM
CRM
RA, RB, RT, RS
rA, rB, rD, rS (respectively)
SI
SIMM
U
IMM
UI
UIMM
/, //, ///
0...0 (shaded)
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Chapter 3
The MPC8xx Core
This chapter provides an overview of the MPC8xx core, summarizing topics described in further detail in
subsequent chapters in Part II. This chapter describes the functional specifications of the core. It is based
on the Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture,
which provides a more in-depth discussion of issues related to the 32-bit portion of the PowerPC
architecture implementation.
The subset of PowerPC instructions supported by the MPC885 is listed in Chapter 5, “MPC885 Instruction
Set.”
3.1
The MPC885 Core as a PowerPC Implementation
The core implements all PowerPC user-level instructions defined for 32-bit implementations except
floating-point instructions (load/store and arithmetic). Likewise, it supports those registers defined by the
PowerPC architecture necessary for the supported instructions.
The MPC885 core adheres to portions of the PowerPC architecture definition for supervisor operations.
For example, it implements the PowerPC exception model (excluding inappropriate exceptions, such as
those that support floating-point operations). The architecture-defined memory management model has
been modified to suit the specific needs of the MPC885 core. Additional exceptions are defined (as
permitted by the architecture) to support address translation.
The PowerPC architecture defines features not supported on the MPC885 hardware. These features
include support for 64-bit addressing, multiprocessing, floating-point arithmetic, and some memory
management features.
The core also implements MPC885-specific development support features such as breakpoint and
watchpoint mechanisms, program-flow tracking data generation, and debug mode operation.
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The MPC8xx Core
3.2
PowerPC Architecture Overview
The PowerPC architecture takes advantage of recent technological advances in such areas as process
technology, compiler design, and reduced instruction set computing (RISC) microprocessor design to
provide software compatibility across a diverse family of implementations, primarily single-chip
microprocessors, intended for a wide range of systems, including battery-powered personal computers;
embedded controllers; high-end scientific and graphics workstations; and multiprocessing,
microprocessor-based mainframes.
To provide a single architecture for such a broad assortment of processor environments, the PowerPC
architecture is both flexible and scalable.
The flexibility of the PowerPC architecture offers many price/performance options. Designers can choose
whether to implement architecturally defined features in hardware or in software. For example, a processor
designed for a high-end workstation has greater need for the performance gained from implementing
floating-point normalization and denormalization in hardware than a device using a PowerPC-embedded
controller might.
The PowerPC architecture defines the following features:
• Separate 32-entry register files for integer instructions. The general-purpose registers (GPRs) hold
source data for integer arithmetic instructions.
• Instructions for loading and storing data between the memory system and the GPRs
• Uniform-length instructions to allow simplified instruction pipelining and parallel processing
instruction dispatch mechanisms
• Nondestructive use of registers for arithmetic instructions in which the second, third, and
sometimes the fourth operand, typically specify source registers for calculations whose results are
usually stored in the target register specified by the first operand
• A precise exception model
• A flexible architecture definition that allows certain features to be performed in either hardware or
with assistance from implementation-specific software depending on the needs of the processor
design
• User-level instructions for explicitly storing, flushing, and invalidating data in the on-chip caches.
The architecture also defines special instructions (cache block touch instructions) for speculatively
loading data before it is needed, reducing the effect of memory latency.
• A memory model that allows weakly-ordered memory accesses. This allows bus operations to be
reordered dynamically, which improves overall performance and in particular reduces the effect of
memory latency on instruction throughput.
• Support for separate instruction and data caches (Harvard architecture) and for unified caches
• Support for both big- and little-endian addressing modes
• Support for 64-bit addressing. The architecture supports both 32- or 64-bit implementations. This
document describes the 32-bit portion of the PowerPC architecture. For information about the
64-bit architecture, see Programming Environments Manual for Implementations of the PowerPC
Architecture.
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The MPC8xx Core
3.2.1
Levels of the PowerPC Architecture
The PowerPC architecture is defined in three levels that correspond to three programming environments,
roughly described from the most general, user-level instruction set environment, to the more specific,
operating environment.
This layering of the architecture provides flexibility, allowing degrees of software compatibility across a
wide range of implementations. For example, an implementation such as an embedded controller may
support the user instruction set, whereas it may be impractical for it to adhere to the memory management,
exception, and cache models.
The three levels of the PowerPC architecture are defined as follows:
• PowerPC user instruction set architecture (UISA)—The UISA defines the level of the architecture
to which user-level (called problem state in the architecture specification) software should
conform. The UISA defines the base user-level instruction set, user-level registers, data types, the
exception model as seen by user programs, and the memory and programming models.
• PowerPC virtual environment architecture (VEA)—The VEA defines additional user-level
functionality that falls outside typical user-level software requirements. The VEA describes the
memory model for an environment in which multiple devices can access memory, defines aspects
of the cache model, defines cache control instructions, and defines the time base facility from a
user-level perspective.
Implementations that conform to the PowerPC VEA also adhere to the UISA, but may not
necessarily adhere to the OEA.
• PowerPC operating environment architecture (OEA)—The OEA defines supervisor-level (called
privileged state in the architecture specification) resources typically required by an operating
system. The OEA defines the PowerPC memory management model, supervisor-level registers,
synchronization requirements, and the exception model. The OEA also defines the time base
feature from a supervisor-level perspective.
Implementations that conform to the PowerPC OEA also conform to the PowerPC UISA and VEA.
The MPC885 adheres to the OEA definition of the exception model and provides a subset of the
memory management model. It includes OEA-defined registers and instructions for configuration
and exception handling.
Implementations that adhere to the VEA level are guaranteed to adhere to the UISA level; likewise,
implementations that conform to the OEA level are also guaranteed to conform to the UISA and the VEA
levels. For a more detailed discussion of the characteristics of the PowerPC architecture, see the
Programming Environments Manual for Implementations of the PowerPC Architecture.
For details of the MPC8xx core as an implementation of the PowerPC architecture, see Section 3.7, “The
MPC885 and Implementation of the PowerPC Architecture.”
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The MPC8xx Core
3.3
Features
Figure 3-1 shows the basic features of the MPC885.
32-Bit (One Instruction)
32-Bit
Sequential
Fetcher
Completion
Queue
CQ5
CQ4
CQ3
CQ2
CQ1
CQ0
Branch
Processing Unit
CTR
CR
LR
32-Bit
Instruction
Queue
IQ3
IQ2
IQ1
INSTRUCTION UNIT
IQ0
32-Bit (One Instruction)
One Instruction Retired
per Clock
Integer
Unit
⁄
*
32-Bit
GPR File
(32-Entry)
+
XER
ALU
Performs
EA
Calculation
Data
MMU
Additional Features
• Power Dissipation Control
• Time Base Counter
• Decrementer
• JTAG
• BDM Interface
• Clock Multiplier
32-Bit
L-Bus
Load/Store
Unit (LSU)
••
•
Instruction
MMU
32-Bit
Entry
DTLB
Tags
Kbyte
D-Cache
Entry
ITLB
32-Bit
Tags
Kbyte
I-Cache
U-Bus Interface
Figure 3-1. Block Diagram of the Core
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The MPC8xx Core
The following is a list of the MPC8xx core main features:
• 32-bit implementation of PowerPC architecture features
— User-level instruction set (not including floating-point instructions)
— Thirty-two, 32-bit general-purpose registers (GPRs)
— Registers required to support PowerPC user-level instruction set (except floating-point
instructions). These include the integer exception register (XER), condition register (CR), link
register (LR), and counter register (CTR).
— Time base upper and time base lower registers (TBU and TBL)
— A subset of the supervisor-level registers for compliance with the following PowerPC models:
– Configuration—Machine state register (MSR)
– Exception model—Save/restore registers 0 and 1 (SRR0 and SRR1), DSI status register
(DSISR), data address register (DAR)
— Core-specific registers compliant with PowerPC architecture
— Static branch prediction
— Precise exception model that includes the subset of the PowerPC exceptions which supports the
instruction set and memory management. The MPC885 implements all PowerPC asynchronous
exceptions (interrupts)—system reset, machine check, decrementer, and external interrupts.
MPC885-specific exceptions are PowerPC-compliant.
— Separate 32-entry instruction and data translation lookaside buffers (TLBs)
• Core-specific features
— Fully static design
— Additional registers that support the MPC885-specific features
— The ability to optimally issue and retire one instruction per clock cycle
— Out-of-order execution and in-order completion
— Extensive debug/testing support
3.4
Basic Structure of the Core
The MPC885 core consists of the following subunits:
• Instruction unit (sequencer)—Consists of the branch processing unit (BPU), the instruction queue,
and the exception handling mechanism.
• Execution units—These consist of the following:
— Integer unit—Implements all integer arithmetic and logical instructions defined by the
PowerPC architecture:
— Load/store unit (LSU)—Implements all load and store instructions except floating-point
load/store instructions. Note that because the MPC885 does not implement floating-point load
and store instructions, this document refers to integer load/store instructions simply as
load/store instructions.
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The MPC8xx Core
3.4.1
Instruction Flow
As many as one instruction per clock cycle is fetched into the four-entry instruction queue (IQ). The branch
processing unit (BPU) predicts the outcome of branch instructions and in some cases, resolves whether the
branch is taken. Figure 3-2 shows general instruction flow.
Fetch (maximum one instruction per clock cycle)
IQ3
Instruction Queue
IQ2
IQ1
Branch
Unit
IQ0
Dispatch (maximum one instruction per clock cycle)
CQ5
CQ4
Completion Queue
CQ3
CQ2
Execution
Units
CQ1
CQ0
Retire (maximum one instruction per clock cycle)
Figure 3-2. Instruction Flow Conceptual Diagram
Non-branch instructions reaching IQ0 are dispatched to the execution units at an optimal rate of one
instruction per clock cycle. An instruction cannot be dispatched unless it can also take a position in the
six-entry completion queue (CQ).
All branch instructions, including unconditional branch instructions, reaching IQ0 must also take a
position in the completion queue. This allows program order to be maintained, it ensures a precise
execution model, and it allows branch instructions to be used as breakpoints.
All instructions enter the CQ along with processor state information that can be affected by the
instruction’s execution. Executed arithmetic instructions pass their results both to rename buffers and to
the architected registers (typically GPRs), but to ensure program order, instructions remain in the CQ until
they can be retired.
If an exception occurs before the instruction can be retired, any results are removed from the rename buffer
and GPR and the instruction is flushed from the completion queue, along with subsequent instructions that
have not executed or have not dispatched.
This information is used to enable out-of-order completion of instructions and ensure a precise exception
model. An instruction can be retired after all instructions ahead of it have retired and it updates the
architected destination registers without taking an exception.
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The MPC8xx Core
3.4.2
Basic Instruction Pipeline
Figure 3-3 shows instruction pipeline timing, showing how by distributing the processes required to fetch,
execute, and retire an instruction into stages, multiple instructions can be processed during a single clock
cycle.
Gclk1
lwz
Fetch
sub
addic
mulli
lwz
Decode
Read + Execute
addi
sub
Bubble
lwz
addic
sub
Writeback
addic
sub
L Address Drive
addic
ld
L Data
ld
Load Write Back
ld
Figure 3-3. Basic Instruction Pipeline Timing
3.4.3
Instruction Unit
The instruction unit implements the basic instruction pipeline, fetches instructions from the memory
system, dispatches them to available execution units, and maintains a state history to ensure a precise
exception model and that operations finish in order. The instruction unit implements all branch processor
instructions, including flow control and CR instructions. Table 9-1 on page 9-5 in Chapter 9 describes
instruction latencies.
3.4.3.1
Branch Operations
Because branch instructions can change program flow and because most branches cannot be resolved at
the same time they are fetched, program branching can keep a processor from operating at maximum
instruction throughput.
If a branch is mispredicted, additional time is required to flush the incorrect branch instructions and begin
fetching from the correct target stream, which can create bubbles in the pipeline. To reduce the latency
caused by misprediction, branch instructions allow the programmer to indicate whether a branch is likely
to be taken. This is called static branch prediction.
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The MPC8xx Core
Figure 3-4 represents the sequencer data path.
Instruction Memory System
32-Bit
Instruction Address Generator
Instruction Buffer
32-Bit
Read/Write
Busses
Branch
Condition
Evaluation
CC Unit
Instruction
Queue (4)
(IQ)
32-Bit
Execution Units and Registers Files
Figure 3-4. Sequencer Data Path
The instruction unit executes branches in parallel with those instructions that must be dispatched to an
execution unit. Ideally, an instruction is dispatched to an execution unit every clock cycle, even when
branches are in the code. The IQ also eliminates stalls due to instruction fetches that miss in the instruction
cache or that generate a page fault. All instructions are fetched into the IQ, and all instructions except
branch instructions are dispatched to the execution units when they reach IQ0. Branches enter the queue
to mark watchpoints. See Chapter 53, “System Development and Debugging.” Because branches do not
prevent the issue of nonbranch instructions unless they come in pairs, the performance impact of entering
branches in the IQ is negligible.
The core also implements a branch reservation station and static branch prediction so branches can be
resolved as early as possible. The reservation station allows a branch instruction to pass from the IQ before
its condition is ready. With the branch out of the way, fetching can continue as the branch is evaluated.
Static branch prediction (defined by the PowerPC UISA) determines which instruction stream is
prefetched while the branch is being resolved. When the branch operand becomes available, it is forwarded
to the BPU and the condition is evaluated. The static branch prediction mechanism is shown in Table 3-1.
Table 3-1. Static Branch Prediction
Branch Type
Default Prediction (y=0)
Modified Prediction (y=1)
BC with negative offset
Taken
Fall through
BC with positive offset
Fall through
Taken
BCLR or BCCTR (LR or CTR) address ready
Fall through
Taken
Wait
Wait
Taken
Taken
BCLR or BCCTR (LR or CTR) address not ready
B (unconditional branch)
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Branch instructions whose condition is unavailable are issued to the reservation station until they are
predicted. Branch instructions that issue with source data already available do not require prediction (and
are said to be resolved). Instructions fetched under a predicted branch are conditionally fetched. The core
flushes instructions conditionally fetched under a mispredicted branch.
3.4.3.2
Dispatching Instructions
The sequencer can dispatch a sequential instruction on each clock if the appropriate execution unit is
available and a position is free in the completion queue. The execution unit must be able to discern whether
source data is available and to ensure that no other executing instruction targets the same destination
register. The sequencer informs the execution units of the existence of the instruction on the instruction
bus. The execution units decode the instruction, check whether the source and destination operands are
free, and inform the sequencer whether instructions can be dispatched.
3.5
Register Set
Registers implemented in the MPC885 core can be grouped as follows:
• PowerPC registers. The MPC885 implements the user registers defined by the UISA and VEA
portions of the architecture except for those that support floating-point operations. PowerPC
registers implemented on the MPC885 are described in Chapter 4, “MPC8xx Core Register Set,”
and Section 4.1.2, “PowerPC Registers—Supervisor Registers.”
• Implementation-specific registers. These are all special-purpose registers (SPRs). These are
described in Section 4.1.3, “MPC885-Specific SPRs.”
3.6
Execution Units
As shown in Figure 3-1, the MPC885 allows parallel execution of instructions using separate branch
processing unit (BPU), load/store unit (LSU), and integer unit (IU). These execution units are described
in the following sections.
3.6.1
Branch Processing Unit
The branch processing unit differs from the other execution units in that it examines branch instructions
while they are in the IQ. Other instructions are dispatched to the IU and LSU from IQ0. For details about
the performance of various instructions, see Table 3-1.
The core supports the UISA-defined static branch prediction. That is, the y bit hints if the branch is likely
to be taken or not taken. No prediction is done for branches to the link register or count register if the target
address is not ready (see Table 3-1 for details).
3.6.2
Integer Unit
The core implements the following types of integer instructions:
• Arithmetic instructions
• Compare instructions
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•
•
•
Trap instructions
Logical instructions
Rotate and shift instructions
Most integer instructions can execute in 1 clock cycle. For details about the performance of the various
instructions, see Table 3-1.
Note the following special cases:
• If an mtspr or mfspr instruction specifies an invalid SPR in which spr[0] = 1, a program exception
occurs if the processor is in user mode. Valid SPRs are listed in Chapter 4, “MPC8xx Core Register
Set.”
• If divw[o][.] is used to perform either (0x80000000 ÷ –1) or (<anything> ÷ 0), the contents of rD
are 0x8000_0000 and if Rc = 1, the contents of the bits in the CR field 0 are LT = 1, GT = 0, EQ =
0, and SO is set to the correct value.
• In the cmpi, cmp, cmpli, and cmpl instructions, the L bit is applicable for 64-bit implementations.
For the MPC885, if L = 1 the instruction form is invalid. The core ignores this bit and, therefore,
the behavior when L = 1 is identical to the valid form instruction with L = 0.
3.6.3
Load/Store Unit
The load/store unit (LSU) transfers all data between the GPRs and the processor’s internal bus. It is
implemented as an independent execution unit so that stalls in the memory pipeline affect the master
instruction pipeline only if there is a data dependency.
The following lists the LSU’s main features:
• All instructions implemented in hardware, including unaligned, string, and multiple accesses
• Two-entry load/store instruction address queue
• Pipelined operation. The LSU pipelines load accesses. Individual cache accesses of all
multiple-register instructions and unaligned accesses are pipelined into the data cache interface.
• Load/store multiple and string instructions synchronize
• Load/store breakpoint/watchpoint detection support
• The LSU implements cache and TLB management instructions as special bus write cycles, which
are issued to the data cache interface.
Figure 3-5 is a block diagram of the LSU and its two queues. The address queue is a 2-entry queue shared
by all load/store instructions and the integer data queue is a 2-entry, 32-bit queue that holds integer data.
The LSU has a dedicated writeback bus so that loaded data received from the internal bus is written
directly back to the GPRs.
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Integer
Unit
GPRs
CORE
Address
Integer
Load Data
Integer
Store Data
32-Bit
32-Bit
32-Bit
LOAD/STORE
UNIT
Address
Queue
and
Increment
32-Bit
32-Bit
D-Cache/D-MMU
Interface
Integer
Data Queue
32-Bit
Figure 3-5. LSU Functional Block Diagram
To execute multiple/string instructions and unaligned accesses, the LSU increments the EA to access all
necessary data. This allows the LSU to execute unaligned accesses without stalling the master instruction
pipeline.
3.6.3.1
Executing Load/Store Instructions
When load or store instructions are dispatched, the LSU determines if all of the operands are available.
These operands include the following:
• Address register operands
• Source data register operands (for store instructions)
• Destination data registers (for load instructions)
• Destination address GPRs (for load/store with update instructions)
If all operands are available, the LSU takes the instruction and enables the sequencer to issue a new
instruction. Using a dedicated interface, the LSU notifies the integer unit of the need to calculate the EA.
All load/store instructions are executed and finished in order. If no prior instructions are in the address
queue, the load/store operation is issued to the data cache when the instruction executes. Otherwise, if prior
instructions remain whose addresses have not been issued to the data cache, the instruction’s address and
data are placed in their respective queues. For load/store with update instructions, the destination address
register is written back on the following clock cycle, regardless of the address queue’s state.
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3.6.3.2
Serializing Load/Store Instructions
The following load/store instructions are not executed until all previous instructions have finished:
• Load/store multiple instructions—lmw, stmw
• Memory synchronization instructions—lwarx, stwcx., sync
• String instructions—lswi, lswx, stswi, stswx
• Move to SPRs
The following load/store instructions must finish before more instructions can be issued:
• Load/store multiple instructions—lmw, stmw
• Memory synchronization instructions—lwarx, stwcx., sync
• String instructions—lswi, lswx, stswi, stswx
3.6.3.3
Store Accesses
Because the core supports the precise exception model, a new store instruction cannot update the data
cache until all prior instructions have finished without an exception. If a store instruction follows a load
instruction, a one-clock delay is inserted between the load bus cycle termination and the store cycle issue.
3.6.3.4
Nonspeculative Load Instructions
Load instructions targeted at nonspeculative memory are identified as nonspeculative one clock cycle after
the previous load/store bus cycle ends, only if all prior instructions have finished without an exception.
The nonspeculative identification relates to the state of the cycle’s associated instruction. For lmw,
although the accesses are pipelined into the bus, they are all marked as nonspeculative because the
instruction is nonspeculative. If a single-register load instruction generates more than one bus cycle, some
of the cycles can be marked as speculative and later cycles can be marked as nonspeculative after all prior
instructions end. Speculative load accesses to external memory marked nonspeculative cannot occur until
the load instruction becomes nonspeculative.
3.6.3.5
Unaligned Accesses
Although the 32-bit U-bus supports only naturally aligned transfers, the LSU supports unaligned accesses
in hardware by breaking them into a pipelined series of aligned transfers. Table 3-2 shows the number of
bus cycles needed for single-register load/store accesses.
Table 3-2. Bus Cycles Needed for Single-Register Load/Store Accesses
Transfer Size
Transfer Address (Last Two Bits)
Number of Bus Cycles
Transfer Type
Address/Size
Byte
0x00
1
Aligned
0x00/byte
0x01
1
Aligned
0x01/byte
0x02
1
Aligned
0x02/byte
0x03
1
Aligned
0x03/byte
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Table 3-2. Bus Cycles Needed for Single-Register Load/Store Accesses (continued)
Transfer Size
Transfer Address (Last Two Bits)
Number of Bus Cycles
Transfer Type
Address/Size
Half Word
0x00
1
Aligned
0x00/halfword
0x01
2
Unaligned
0x01/byte
0x02/byte
0x02
1
Aligned
0x02/halfword
0x03
2
Unaligned
0x03/byte
0x04/byte
0x00
1
Aligned
0x00/word
0x01
3
Unaligned
0x01/byte
0x02/halfword
0x05/byte
0x02
2
Unaligned
0x02/halfword
0x04/halfword
0x03
3
Unaligned
0x03/byte
0x04/halfword
0x06/byte
Word
3.6.3.6
Atomic Update Primitives
The lwarx and stwcx. instructions are atomic update primitives that set and clear memory reservations.
Reservation accesses made by the same processor are implemented by the LSU. The external bus interface
implements memory reservations as they relate to accesses made by external bus devices. Accesses made
by other internal devices to internal memories implement memory reservations as they relate to special
internal bus snoop logic.
When an lwarx instruction executes, the LSU issues a cycle to the data cache with a special attribute. For
external memory accesses, this attribute causes the external bus interface to set a memory reservation
during the address tenure. External logic must then snoop the external bus to determine if another device
breaks the memory reservation by accessing the same location. KR and CR signals are available to external
logic to signal loss of a reservation to the external bus interface. When an stwcx. instruction addresses
external memory and the external bus interface determines that the reservation was lost, it blocks the
external bus access and notifies the LSU.
The MPC885 supports the memory reservation mechanism in a hierarchical bus structure. For reservations
on internal memory, an lwarx causes on-chip snoop logic to latch the address. This logic notifies the LSU
of any internal master store access and resets the reservation. If a new lwarx instruction address tenure
executes successfully, it replaces any previous reservation address at the appropriate snoop logic.
However, executing an stwcx. instruction cancels the reservation unless an alignment exception is
detected.
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3.7
The MPC885 and Implementation of the PowerPC Architecture
This section describes the relationship between the MPC885 and implementation of the PowerPC
architecture. It indicates the types of distinguishing features of the MPC885 described in the following:
• In many cases, the PowerPC architecture specification is flexible enough to allow implementation
options. For example, the architecture does not specify whether unaligned transfers must be
handled in hardware or whether instruction execution must be performed in hardware or software.
• The PowerPC architecture defines optional features, some of which are implemented on the
MPC885 (such as TLBs) and some of which are not, such as the eciwx and ecowx instructions.
• The PowerPC architecture defines features, such as virtual memory and floating-point instructions,
that are not implemented on the MPC885.
Table 3-3 summarizes MPC885 features with respect to the UISA definition.
Table 3-3. UISA-Level Features
Functionality
Description
Reserved fields
Reserved fields in instructions are described under the specific instruction definition in Chapter 5,
“MPC885 Instruction Set.” Unless otherwise stated, instruction fields marked I, II, and III are
discarded during decoding. Thus, this type of instruction yields results of the defined instructions
with the appropriate field = 0. In most cases, reserved fields in registers are ignored on write and
return zeros for them on read for any control register implemented by the core. Exceptions are
XER[16–23] and the reserved bits of MSR, which are set by the source value on write and return
the value last set for it on read.
Classes of
instructions
Required instructions (except floating-point load, store, and compute instructions) are
implemented in hardware. Optional instructions are executed by implementation-dependent code;
any attempt to execute one of these commands causes the core to take the software emulation
exception (offset 0x01000). Illegal and reserved instruction class instructions are supported by
implementation-dependent code and, thus the core hardware generates a software emulation
exception.
Exceptions
Invocation of the system software for any exception caused by an instruction in the core is precise,
regardless of the type and setting.
Fetching
instructions
The core fetches a number of instructions into its IQ from which they are dispatched to the
execution units. If a program modifies instructions, it should call a system library program to ensure
that the instruction fetching mechanism can detect changes before execution.
Branch
instructions
The core implements all UISA instructions defined for the branch processor in hardware. For
details about the performance of various instructions, see Table 3-1.
Invalid branch
instruction forms
Bits marked with z in the BO encoding definition default to z = 0 and are discarded by the core
decoding. Thus, these instructions yield results of defined instructions for which z = 0. If the
decrement and test CTR option is specified for the bcctr or bcctrl instructions, the target address
of the branch is the new value of the CTR. Condition is evaluated correctly, including the value of
the counter after decrement.
Branch prediction The core uses the y bit to predict path for prefetch. Prediction is only done for not-ready branch
conditions. No prediction is done for branches to the link or count register if the target address is
not ready (see Table 3-1).
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Table 3-3. UISA-Level Features (continued)
Functionality
Description
Integer processor The core implements the following integer instructions:
• Arithmetic instructions
• Compare instructions
• Trap instructions
• Logical instructions
• Rotate and shift instructions
Move to/from
SPR instructions
Move to/from invalid SPRs in which SPR[0] = 1 invokes the privileged instruction error exception
handler if the processor is in user mode.
Integer arithmetic Attempting to use divw to perform either 0x80000000 ÷ -1 or <anything> ÷ 0 sets the contents of
instructions
rD to 0x80000000 and if Rc =1, the contents of CR0 are LT = 1, GT = 0, and EQ = 0. SO is set to
the correct value.
In the cmpi, cmp, cmpli, and cmpl instructions, the L bit is applicable for 64-bit implementations.
For the MPC885, if L = 1 the instruction form is invalid. The core ignores this bit and, therefore, the
behavior when L = 1 is identical to the valid form instruction with L = 0.
Integer load/store For load with update and store with update instructions where rA = 0, the EA is written into r0. For
load with update instructions where rA = rD, rA is boundedly undefined.
with update
instructions
Integer load/ store For these types of instructions, EA must be a multiple of four. If it is not, the system alignment error
handler is invoked. For an lmw instruction (if rA is in the range of registers to be loaded), the
multiple
instruction completes normally. rA is then loaded from the memory location as follows:
instructions
rA <- MEM(EA+(rA-rD)*4, 4)
Integer load string Load string instructions behave like load multiple instructions with respect to invalid format in which
instructions
rA is in the range of registers to be loaded. If rA is in the range, it is updated from memory.
Memory
synchronization
instructions
For these instructions, if EA is not a multiple of four, the system alignment error handler is invoked.
Optional
instructions
No optional instructions are supported.
Little-endian byte
ordering
The LSU supports little-endian byte ordering as specified in the UISA. In little-endian mode, trying
to execute an unaligned individual scalar or multiple/string access causes an alignment exception.
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Table 3-4 summarizes MPC885 features with respect to the VEA definition.
Table 3-4. VEA-Level Features
Functionality
Memory
coherency
Description
Memory coherency is not supported in the MPC885 hardware, but can be performed in the software
or by defining memory as cache inhibited. In addition, the MPC885 does not provide any data storage
attributes to an external system.
Atomic update Both the lwarx and stwcx. instructions are implemented according to the PowerPC architecture
primitives
requirements. When memory accessed by the lwarx and stwcx. instructions is in the cache-allowed
mode, it is assumed that the system works with the single master in this memory region. Therefore, if
a data cache miss occurs, the access on the internal and external buses does not have a reservation
attribute. The MPC885MPC885 does not cause the system DSI exception handler to be invoked if
memory accessed by the lwarx and stwcx. instructions is in write-through required mode. Also, the
MPC885 does not support snooping an external bus activity outside the chip. The provision is made
to cancel the reservation inside the MPC885 by using the CR and KR input signals. For accesses to
internal resources, internal snoop logic monitors the internal bus for communication processor module
(CPM) accesses of the address associated with the last lwarx instruction.
The effect of
operand
placement on
performance
The LSU hardware supports all PowerPC integer load/store instructions. Naturally-aligned operands
give optimal performance for a maximum size of four bytes. Unaligned operands are supported in
hardware and are broken into a series of aligned transfers. The effect of operand placement on
performance is as stated in the VEA, except for 8-byte operands. Because the MPC885 uses a 32-bit
data bus, performance is good rather than optimal. See Section 3.6.3.5, “Unaligned Accesses,” for a
description of integer unaligned instruction execution and timing; see Section 9.2.2, “String Instruction
Latency,” for a description of string instruction timing.
Memory
control
instructions
The MPC885 interprets cache control instructions as if they pertain only to the MPC885 cache. These
instructions do not broadcast. Any bus activity caused by these instructions results from an operation
performed on the MPC885 cache and not because of the instruction itself.
• Instruction Cache Block Invalidate (icbi)—The MMU translates the EA and the associated
instruction cache block is invalidated if hit.
• Instruction Synchronize (isync)—The isync instruction waits for all previous instructions to
complete and discards any prefetched instructions, causing subsequent instructions to be fetched
or refetched from memory and executed.
• Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store (dcbtst)—The appropriate
cache block is checked for a hit. If it is a miss, the instruction is treated as a regular miss, except
that bus error does not cause an exception. If no error occurs, the cache is updated.
• Data Cache Block Set to Zero (dcbz)—Executes as defined in the VEA.
• Data Cache Block Store (dcbst)—Executes as defined in the VEA.
• Data Cache Block Invalidate (dcbi)—The MMU translates the EA and the associative data cache
block is invalidated if hit.
• Data Cache Block Flush (dcbf)—Executes as defined in the VEA.
• Enforce In-Order Execution of I/O (eieio)—When executing an eieio instruction, the LSU waits for
previous accesses to terminate before beginning accesses associated with load/store instructions
after the eieio instruction.
Time base
The time base functions as defined by the VEA and supports an additional implementation-specific
exception. The time base is described in Chapter 10, “System Interface Unit,” and in Chapter 14,
“Clocks and Power Control.”
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Table 3-5 summarizes MPC885 features with respect to the OEA definition.
Table 3-5. OEA-Level Features
Functionality
Machine state
register
Description
The floating-point exception mode (bits FE0 and FE1) is ignored by the MPC885. The IP bit initial
state after reset is set as programmed by the reset configuration specified in Section 6.1.2.1,
“System Reset Interrupt (0x00100).”
Processor
The value of the PVR register’s version field is 0x0050. The value of the revision field is 0x0000, and
version register it is incremented each time the device is revised, to allow software to distinguish between revisions.
Other OEA
registers
The following registers are not implemented: SDR1, BAT registers, segment registers, and EAR
Page size
The MPC885 differs from the OEA-defined memory management mode with respect to page sizes.
Page sizes are 4, 16, and 512 Kbytes, and 8 Mbytes with an optional subpage granularity of 1 Kbyte
for 4-Kbyte pages in a maximum physical memory size of 4 Gbytes. Neither ordinary nor direct-store
segments are supported.
Address space
The MPC885 differs from the OEA-defined memory management model. Specifically, it does not
support the same address translation mechanism that requires an intermediate 52-bit virtual
address. It also does not support block address translation or the associated block address
translation SPRs. In its place, the MPC885’s internal memory space includes memory-mapped
control registers and memory used by various modules on the chip. This memory is part of the main
memory as seen by the core but cannot be accessed by any external system device.
Address
translation
If address translation is disabled (MSR[IR] = 0 for instruction accesses or MSR[DR] = 0 for data
accesses), the EA is treated as the physical address and is passed directly to the memory
subsystem. Otherwise, the EA is translated by using the MMU’s TLB mechanism. Instructions are
not fetched from no-execute or guarded memory and data accesses are not executed speculatively
to or from the guarded memory. The features of the MMU hardware are as follows:
• 32-entry fully-associative ITLB
• 32-entry fully-associative DTLB
• Supports up to 16 virtual address spaces
• Supports 16 access protection groups
• Supports fast software table search mechanism
The MPC885 MMU is described in detail in Chapter 8, “Memory Management Unit.”
Reference and
change bits
No reference bit is supported by the MPC885. However, the change bit is supported by using the
data TLB error exception mechanism when writing to an unmodified page.
Memory
protection
Two protection modes are supported by the MPC885:
• Domain manager mode
• PowerPC mode
See Chapter 8, “Memory Management Unit.”
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Chapter 4
MPC8xx Core Register Set
This chapter describes the software-accessible registers implemented on the MPC885. These include
registers that are defined by the PowerPC architecture and registers that are specific to the MPC885. This
section does not include registers that are part of the communication processor module (CPM); those
registers are described in Part V, “Communications Processor Module.” Refer to the Programming
Environments Manual for 32-Bit Implementations of the PowerPC Architecture for more information
about the architecture’s register definition.
4.1
MPC885 Register Implementation
Registers implemented in the MPC885 core can be grouped as follows:
• Two types of registers are defined by the PowerPC architecture.
— User registers, which can be accessed by user-level software. All PowerPC user-level registers
are defined by the user instruction set architecture (UISA), except for the time base registers,
which can be read by user-level software and are defined by the virtual environment
architecture (VEA). User registers are described in Section 4.1.1, “PowerPC Registers—User
Registers.”
— Supervisor registers, which can be accessed by supervisor software and in some cases are the
automatic result of hardware activity, such as when an exception is taken and when the system
is reset. All supervisor registers are defined by the operating environment architecture (OEA),
except the time base registers, which can be written to only by supervisor software and are
defined by the VEA. PowerPC supervisor registers are described in Section 4.1.2, “PowerPC
Registers—Supervisor Registers.”
The UISA, VEA, and OEA architecture definitions are described in Section 3.2.1, “Levels of the
PowerPC Architecture.”
• MPC885-specific registers. These registers are either supervisor-level registers or debug registers.
These are described briefly in Section 4.1.3, “MPC885-Specific SPRs.” Table 4-9 and Table 2-1
provide cross references to the sections in this book where each register is described.
4.1.1
PowerPC Registers—User Registers
The MPC885 implements the user-level registers defined by the PowerPC architecture except those
required for supporting floating-point operations (the floating-point register file (FPRs) and the
floating-point status and control register (FPSCR)). User-level PowerPC registers are listed in Table 4-1
and Table 4-2. Table 4-2 lists user-level special-purpose registers (SPRs).
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Table 4-1. User-Level PowerPC Registers
Description
Name
General-purpose
registers
Reference/Section
Access Level Serialize Access
GPRs The thirty-two 32-bit (GPRs) are used for source
and destination operands.
Condition register
CR
See Section 4.1.1.1.1, “Condition Register (CR).”
User
—
User
Only mtcrf
Table 4-2 lists SPRs defined by the PowerPC architecture implemented on the MPC885.
Table 4-2. MPC885-Specific User-Level SPRs
SPR Number
Name
Decimal
1
2
Reference/Section
Serialize Access
SPR [5–9] SPR [0–4]
1
00000
00001
XER
See Section 4.1.1.1.3, Write: Full sync
“XER.”
Read: Sync relative to load/store
operations
8
00000
01000
LR
See the Programming
Environments Manual
No
9
00000
01001
CTR
See the Programming
Environments Manual
No
268
01000
01100
269
01000
01101
TBL read1 Section 10.9,
“Timebase”
TBU read2
Write (as a store)
Extended opcode for mftb, 371 rather than 339.
Any write (mtspr) to this address causes an implementation-dependent software emulation exception.
4.1.1.1
PowerPC User-Level Register Bit Assignments
This section describes bit assignments of PowerPC registers implemented by the MPC885. For more
details, see the Programming Environments Manual for 32-Bit Processors.
Condition Register (CR)
4.1.1.1.1
The condition register (CR) is a 32-bit register that reflects the result of certain operations and provides a
mechanism for testing and branching. The bits in the CR are grouped into eight 4-bit fields, CR0–CR7, as
shown in Figure 4-1.
CR0
0
CR1
3
4
CR2
7
8
CR3
11 12
CR4
15 16
CR5
19 20
CR6
23 24
CR7
27 28
31
Figure 4-1. Condition Register (CR)
The CR fields can be set in one of the following ways:
• Specified fields of the CR can be set from a GPR by using the mtcrf instruction.
• An mcrf instruction can move the contents of XER[0–3] to a CR field.
• An mcrxr instruction can copy a specified XER field to a specified CR field.
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•
•
•
Condition register logical instructions perform logical operations on specified CR bits.
CR0 can be the implicit result of an integer instruction.
A specified CR field can indicate the result of an integer compare instruction.
Note that branch instructions are provided to test individual CR bits.
4.1.1.1.2
Condition Register CR0 Field Definition
For all integer instructions, when the CR is set to reflect the result of the operation (that is, when Rc = 1),
and for addic., andi., and andis., CR0[0–2] are set by an algebraic comparison of the result to zero;
CR0[3] is copied from XER[SO]. For integer instructions, CR[0–3] reflects the result as a signed quantity.
The CR bits are interpreted as shown in Table 4-3. If any portion of the result is undefined, the value placed
into CR0[0–3] is undefined.
Table 4-3. Bit Settings for CR0 Field of CR
CR0 Bit
Description
0
Negative (LT). Set when the result is negative.
1
Positive (GT). Set when the result is positive (and not zero).
2
Zero (EQ). Set when the result is zero.
3
Summary overflow (SO). This is a copy of the final state of XER[SO] at the completion of the instruction.
Note that CR0 may not reflect the true (that is, infinitely precise) result if overflow occurs.
4.1.1.1.3
XER
Figure 4-2 shows XER bit assignments. Settings are based on the final result produced by executing an
instruction.
Field
0
1
2
SO
OV
CA
3
15
—
Reset
0000_0000_0000_0000
R/W
R/W
16
Field
Reset
R/W
24
25
—
31
BCNT
0000_0000_0000_0000
R/W
Figure 4-2. XER Register
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XER bits are described in Table 4-4.
Table 4-4. XER Field Definitions
Bits
Name
Description
0
SO
Summary overflow. Set when an instruction (except mtspr) sets the overflow bit (OV). When set,
SO remains set until it is cleared by an mtspr(XER) or an mcrxr instruction. It is not altered by
compare instructions or other instructions (except mtspr(XER) and mcrxr) that cannot overflow.
1
OV
Overflow. Set to indicate that an overflow occurred during execution of an instruction. Add, subtract
from, and negate instructions with OE = 1 set OV if the carry out of the msb is not equal to the carry
out of the msb + 1 and clear it otherwise. Multiply low and divide instructions with OE = 1 set OV if
the result cannot be represented in 32 bits (mullw, divw, divwu) and clear it otherwise. The OV bit
is not altered by compare instructions that cannot overflow (except mtspr(XER) and mcrxr).
2
CA
Carry. Set during execution of the following instructions:
• Add carrying, subtract from carrying, add extended, and subtract from extended instructions set
CA if there is a carry out of the msb, and clear it otherwise.
• Shift right algebraic instructions set CA if any 1 bits have been shifted out of a negative operand,
and clear it otherwise.
The CA bit is not altered by compare instructions, nor by other instructions that cannot carry (except
shift right algebraic, mtspr(XER), and mcrxr).
3–24
—
Reserved
25–31
BCNT
Specifies the number of bytes to be transferred by a Load String Word Indexed (lswx) or Store String
Word Indexed (stswx) instruction.
Although divide instructions have a relatively long latency, they can update XER[OV] after one cycle.
Therefore, data dependency on the XER is limited to one cycle, although the divide instruction latency can
be a maximum of 11 clocks.
4.1.1.1.4
Time Base Registers
The time base registers (TBU and TBL) are described in Section 10.9, “Timebase,” and in Chapter 14,
“Clocks and Power Control.” The PowerPC architecture does not define an exception associated directly
with the time base, but one is implemented in the MPC885.
4.1.2
PowerPC Registers—Supervisor Registers
All supervisor-level registers implemented on the MPC885 are SPRs, except for the machine state register
(MSR), described in Table 4-5.
Table 4-5. Supervisor-Level PowerPC Registers
Description
Machine state register
Name
MSR
Reference/Section
See Section 4.1.2.3.1, “Machine State Register (MSR).”
Serialize Access
Write fetch sync
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Table 4-6 lists supervisor-level SPRs defined by the PowerPC architecture.
Table 4-6. Supervisor-Level PowerPC SPRs
SPR Number
Name
1
Reference/Section
Serialize Access
Decimal
SPR[5–9]
SPR[0–4]
18
00000
10010
DSISR
See the Programming Environments
Manual and Section 4.1.2.1, “DAR,
DSISR, and BAR Operation.”
Write: Full sync
Read: Sync relative to
load/store operations
19
00000
10011
DAR
See the Programming Environments
Manual and Section 4.1.2.1, “DAR,
DSISR, and BAR Operation.”
Write: Full sync
Read: Sync relative to
load/store operations
22
00000
10110
DEC
Write
See Section 10.8.1, “Decrementer
Register (DEC),” and Chapter 14, “Clocks
and Power Control.”
26
00000
11010
SRR0
See SRR0 settings for individual
exceptions in Chapter 6, “Exceptions.”
Write
27
00000
11011
SRR1
See SRR1 settings for individual
exceptions in Chapter 6, “Exceptions.”
Write
272
01000
10000
SPRG0
Write
273
01000
10001
SPRG1
See the Programming Environments
Manual.
274
01000
10010
SPRG2
275
01000
10011
SPRG3
284
01000
11100
Write (as a store)
285
01000
11101
TBL write1 See Section 10.9, “Timebase,” and
Chapter 14, “Clocks and Power Control.”
TBU write1
287
01000
11111
PVR
No (read-only register)
Section 4.1.2.3.2, “Processor Version
Register.”
Any read (mftb) to this address causes an implementation-dependent software emulation exception.
4.1.2.1
DAR, DSISR, and BAR Operation
The LSU updates the DAR, DSISR, and BAR when an exception is taken.
• When a bus error occurs, the data address register (DAR) is loaded with the effective address. For
instructions that generate multiple accesses, the effective address of the first offending tenure is
loaded.
• The DSI status register (DSISR) notifies the error handler when an exception is caused by a load
or store. For a data MMU error, the data MMU loads the DSISR with error status. For alignment
exceptions, the DSISR is loaded with the instruction information as defined by the PowerPC
architecture.
• The breakpoint address register (BAR) notifies the address on which a data breakpoint occurred.
For a multiple-cycle instruction, the BAR contains the address of the first cycle with which the
breakpoint condition was associated. The BAR has a valid value only when a data breakpoint
exception is taken. At any other time, its value is boundedly undefined. (This term is defined very
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specifically by the PowerPC architecture and is discussed in the Programming Environments
Manual.)
The following situations cause the DAR, BAR, and DSISR registers to be updated.
Table 4-7. Value Summary of the DAR, BAR, and DSISR Registers
Exception Type
DAR Value
DSISR Value
BAR Value
DSI
Cycle EA
Data MMU error status
Undefined
Alignment
Data EA
Instruction information
Undefined
Data breakpoint
Does not change
Does not change
Cycle EA
Machine check
Cycle EA
Instruction information
Undefined
Software emulation exception
Does not change
Does not change
Undefined
Floating-point unavailable
Does not change
Does not change
Undefined
Program exception
Does not change
Does not change
Does not change
4.1.2.2
Unsupported Registers
The MPC885 does not support the following OEA registers:
• DBATs and IBATs —The MPC885 does not support block address translation.
• EAR—The MPC885 does not support the optional external access facility.
• SDR1—The MPC885 does not support memory segments.
• Segment registers—The MPC885 does not support memory segments.
4.1.2.3
PowerPC Supervisor-Level Register Bit Assignments
This section describes bit assignments of supervisor-level PowerPC registers implemented by the
MPC885. For more details, see the Programming Environments Manual for 32-Bit Processors.
4.1.2.3.1
Machine State Register (MSR)
The 32-bit machine state register (MSR) is used to configure such parameters as the privilege level,
whether translation is enabled, and the endian mode. It can be read by the mfmsr instruction and modified
by the mtmsr, sc, and rfi instructions.
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0
12
Field
—
Reset
13
14
15
–
—
ILE
29
30
31
0000_0000_0000_0000
R/W
R/W
16
17
18
19
20
21
22
Field
EE
PR
FP
ME
—
SE
BE
Reset
0
0
0
0
0
0
0
R/W
23
24
—
0
0
25
26
27
28
IP
IR
DR
—
RI
LE
0
01
0
0
0
0
R/W
1
The reset value of IP is determined by the IIP bit (bit 2) in the hard reset configuration word. See Section 11.3.1.1, “Hard
Reset Configuration Word.” Subsequent soft resets cause IP to revert to the value latched during hard reset configuration.
Figure 4-3. Machine
State Register (MSR)
When an exception is taken, most MSR bits are saved in the SRR1 and the MSR is reconfigured with the
state of the exception handler using the values in Figure 4-3. This process is described in Section 6.1.6,
“Exception Latency.”
After a hard reset, MSR[IP] takes the value specified in hard reset configuration word. See
Section 11.3.1.1, “Hard Reset Configuration Word.” MSR bits are described in Table 4-8.
Table 4-8. MSR Field Descriptions
Bits
Name
Description
0–12
—
Reserved
13
—
Reserved. Must be written as a 0.
14
—
Reserved
15
ILE
Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to select
the endian mode for the context established by the exception.
16
EE1
External interrupt enable
0 The processor delays recognition of external and decrementer interrupt conditions.
1 The processor is enabled to take an external or decrementer interrupt.
17
PR 1
Privilege level
0 The processor can execute both user- and supervisor-level instructions.
1 The processor can only execute user-level instructions.
18
FP 1
Floating-point available
0 The processor prevents dispatch of floating-point instructions, including floating-point loads,
stores, and moves.
1 The processor can execute floating-point instructions. (This setting is invalid on the MPC885.)
19
ME 1
Machine check enable
0 Machine check exceptions are disabled.
1 Machine check exceptions are enabled.
20
—
Reserved
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Table 4-8. MSR Field Descriptions (continued)
1
Bits
Name
21
SE 1
Single-step trace enable (optional)
0 The processor executes instructions normally.
1 A single-step trace exception is generated when the next instruction executes successfully.
Note: If the function is not implemented, SE is treated as reserved.
22
BE 1
Branch trace enable (Optional)
0 The processor executes branch instructions normally.
1 The processor generates a branch trace exception after completing the execution of a branch
instruction, regardless of whether the branch was taken.
Note: If the function is not implemented, this bit is treated as reserved.
23–24
—
Reserved
25
IP
Exception prefix. The setting of IP specifies whether an exception vector offset is prepended with Fs
or 0s. In the following description, nnnnn is the offset of the exception vector. See Table 6-1.
0 Exceptions are vectored to the physical address 0x000n_nnnn
1 Exceptions are vectored to the physical address 0xFFFn_nnnn
The reset value of IP is determined by the IIP bit (bit 2) in the hard reset configuration word. See
Section 11.3.1.1, “Hard Reset Configuration Word.” Subsequent soft resets cause IP to revert to the
value latched during hard reset configuration.
26
IR 1
Instruction address translation
0 Instruction address translation is disabled.
1 Instruction address translation is enabled.
For more information, see Chapter 8, “Memory Management Unit.”
27
DR 1
Data address translation
0 Data address translation is disabled.
1 Data address translation is enabled.
For more information, see Chapter 8, “Memory Management Unit.”
28–29
—
1
30
RI
31
LE 1
Description
Reserved
Recoverable exception (for system reset and machine check exceptions)
0 Exception is not recoverable.
1 Exception is recoverable.
For more information, see Chapter 6, “Exceptions.”
Little-endian mode enable
0 The processor runs in big-endian mode.
1 The processor runs in little-endian mode.
These bits are loaded into SRR1 when an exception is taken. These bits are written back into the MSR when an rfi
is executed.
4.1.2.3.2
Processor Version Register
The value of the PVR register’s version field is 0x0050. The value of the revision field is incremented each
time the core is revised.
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4.1.3
MPC885-Specific SPRs
Table 4-2 and Table 4-9 list SPRs specific to the MPC885. Debug registers, which have additional
protection, are described in Chapter 53, “System Development and Debugging.” Supervisor-level registers
are described in Table 4-9.
Table 4-9. MPC885-Specific Supervisor-Level SPRs
SPR Number
Name
Reference/Section
Serialize Access
Decimal
SPR[5–9]
SPR[0–4]
80
00010
10000
EIE
Section 6.1.5, “Recoverability After an Write
Exception”
81
00010
10001
EID
—
Write
82
00010
10010
NRI
—
Write
631
10011
10111
DPIR1
—
Fetch-only
638
10011
11110
IMMR
Section 10.4.1, “Internal Memory Map Write (as a store)
Register (IMMR)”
560
10001
10000
IC_CST
Section 7.3.1, “Instruction Cache
Control Registers”
Write (as a store)
561
10001
10001
IC_ADR
Section 7.3.1, “Instruction Cache
Control Registers”
Write (as a store)
562
10001
10010
IC_DAT
Section 7.3.1, “Instruction Cache
Control Registers”
Write (as a store)
568
10001
11000
DC_CST
Section 7.3.2, “Data Cache Control
Registers”
Write (as a store)
569
10001
11001
DC_ADR
Section 7.3.2, “Data Cache Control
Registers”
Write (as a store)
570
10001
11010
DC_DAT
Section 7.3.2, “Data Cache Control
Registers”
Write (as a store)
784
11000
10000
MI_CTR
Section 8.8.1, “IMMU Control Register Write (as a store)
(MI_CTR)”
786
11000
10010
MI_AP
Section 8.8.10, “MMU Access
Write (as a store)
Protection Registers (MI_AP/MD_AP)”
787
11000
10011
MI_EPN
Section 8.8.3, “IMMU/DMMU Effective Write (as a store)
Page Number Register (Mx_EPN)”
789
11000
10101
MI_TWC
(MI_L1DL2P)
Section 8.8.4, “IMMU Tablewalk
Control Register (MI_TWC)”
Write (as a store)
790
11000
10110
MI_RPN
Section 8.8.6, “IMMU Real Page
Number Register (MI_RPN)”
Write (as a store)
816
11001
10000
MI_CAM
Section 8.8.12.1, “IMMU CAM Entry
Read Register (MI_CAM)”
Write (as a store)
817
11001
10001
MI_RAM0
Section 8.8.12.2, “IMMU RAM Entry
Read Register 0 (MI_RAM0)”
Write (as a store)
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Table 4-9. MPC885-Specific Supervisor-Level SPRs (continued)
SPR Number
Name
1
Reference/Section
Serialize Access
Decimal
SPR[5–9]
SPR[0–4]
818
11001
10010
MI_RAM1
Section 8.8.13, “DMMU RAM Entry
Read Register 1 (MD_RAM1)”
Write (as a store)
792
11000
11000
MD_CTR
Section 8.8.2, “DMMU Control
Register (MD_CTR)”
Write (as a store)
793
11000
11001
M_CASID
Section 8.8.9, “MMU Current Address Write (as a store)
Space ID Register (M_CASID)”
794
11000
11010
MD_AP
Section 8.8.10, “MMU Access
Write (as a store)
Protection Registers (MI_AP/MD_AP)”
795
11000
11011
MD_EPN
Section 8.8.3, “IMMU/DMMU Effective Write (as a store)
Page Number Register (Mx_EPN)”
796
11000
11100
M_TWB
(MD_L1P)
Section 8.8.8, “MMU Tablewalk Base
Register (M_TWB)”
Write (as a store)
797
11000
11101
MD_TWC
(MD_L1DL2P)
Section 8.8.5, “DMMU Tablewalk
Control Register (MD_TWC)”
Write (as a store)
798
11000
11110
MD_RPN
Section 8.8.7, “DMMU Real Page
Number Register (MD_RPN)”
Write (as a store)
799
11000
11111
M_TW (M_SAVE) Section 8.8.11, “MMU Tablewalk
Special Register (M_TW)”
Write (as a store)
824
11001
11000
MD_CAM
Section 8.8.12.4, “DMMU CAM Entry
Read Register (MD_CAM)”
Write (as a store)
825
11001
11001
MD_RAM0
Section 8.8.12.5, “DMMU RAM Entry
Read Register 0 (MD_RAM0)”
Write (as a store)
826
11001
11010
MD_RAM1
Section 8.8.13, “DMMU RAM Entry
Read Register 1 (MD_RAM1)”
Write (as a store)
Fetch-only register. mtspr is ignored; using mfspr gives an undefined value.
Debug-level registers are described in Table 4-10. These registers are described in Section 53.5.1,
“Development Support Registers.”
Table 4-10. MPC885-Specific Debug-Level SPRs
SPR Number
Name
Decimal SPR[5–9]
Serialize Access
SPR[0–4]
144
00100
10000
CMPA
Fetch sync on write
145
00100
10001
CMPB
Fetch sync on write
146
00100
10010
CMPC
Fetch sync on write
147
00100
10011
CMPD
Fetch sync on write
148
00100
10100
ICR
Fetch sync on write
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Table 4-10. MPC885-Specific Debug-Level SPRs (continued)
SPR Number
Name
Decimal SPR[5–9]
Serialize Access
SPR[0–4]
149
00100
10101
DER
Fetch sync on write
150
00100
10110
COUNTA
Fetch sync on write
151
00100
10111
COUNTB
Fetch sync on write
152
00100
11000
CMPE
Write: Fetch sync
Read: Sync relative to load/store operations
153
00100
11001
CMPF
Write: Fetch sync
Read: Sync relative to load/store operations
154
00100
11010
CMPG
Write: Fetch sync
Read: Sync relative to load/store operations
155
00100
11011
CMPH
Write: Fetch sync
Read: Sync relative to load/store operations
156
00100
11100
LCTRL1
Write: Fetch sync
Read: Sync relative to load/store operations
157
00100
11101
LCTRL2
Write: Fetch sync
Read: Sync relative to load/store operations
158
00100
11110
ICTRL
Fetch sync on write
159
00100
11111
BAR
Write: Fetch sync
Read: Sync relative to load/store operations. See
Section 4.1.2.1, “DAR, DSISR, and BAR Operation.”
630
10011
10110
DPDR
Read and Write
4.1.3.1
Accessing SPRs
All SPRs are accessed using the mtspr and mfspr instructions, regardless of whether they are within the
processor core. To access registers outside of the core, an internal bus tenure occurs using the address lines,
as described in Table 4-11.
Table 4-11. Addresses of SPRs Located Outside of the Core
Address Lines
0:17
18:22
23:27
28:31
0...0
SPR[0–4]
SPR[5–9]
0000
Address errors in this tenure cause a software emulation exception.
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4.2
Register Initialization at Reset
This section describes how basic registers are set under reset conditions, other register settings are
described in Chapter 7, “Instruction and Data Caches,” and Chapter 8, “Memory Management Unit.”
A system reset interrupt occurs when a nonmaskable interrupt is generated either by the software watchdog
timer or the assertion of IRQ0. The only registers affected by the system reset interrupt are MSR, SRR0,
and SRR1; no other reset activity occurs. Section 6.1.2.1, “System Reset Interrupt (0x00100),” describes
values for these registers after system reset.
When a hard or soft reset occurs, registers are set in the same way, as follows:
• SRR0, SRR1—Set to an undefined value
• MSR[IP]—Programmable through the IIP bit in the hard reset configuration word
• MSR[ME]—Cleared
• ICTRL—Cleared
• LCTRL1—Cleared
• LCTRL2—Cleared
• COUNTA[16–31]—Cleared
• COUNTB[16–31]—Cleared
• ICR—Cleared (no exception occurred)
• DER[2,14,28–31]—Set (all debug-specific exceptions cause debug mode entry)
Reset values for memory-mapped registers are provided with individual register descriptions throughout
this manual.
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Chapter 5
MPC885 Instruction Set
This chapter describes the instructions implemented by the MPC885. These instructions are organized by
the level of architecture in which they are implemented—UISA, VEA, and OEA. These levels are
described in Section 3.2.1, “Levels of the PowerPC Architecture.”
5.1
Operand Conventions
This section describes the operand conventions as they are represented in two levels of the architecture. It
also provides detailed descriptions of conventions used for storing values in registers and memory,
accessing the MPC885’s registers, and representing data in these registers.
5.1.1
Data Organization in Memory and Data Transfers
Bytes in memory are numbered consecutively starting with 0. Each number is the address of the
corresponding byte.
Memory operands may be bytes, half words, words, or double words, or, for the load/store multiple and
move assist instructions, a sequence of bytes or words. The address of a memory operand is the address of
its first byte (that is, of its lowest-numbered byte).
5.1.2
Aligned and Misaligned Accesses
The operand of a single-register memory access instruction has a natural alignment boundary equal to the
operand length. In other words, the natural address of an operand is an integer multiple of the operand
length. A memory operand is said to be aligned if it is aligned at its natural boundary; otherwise it is
misaligned.
Operands for single-register memory access instructions have the characteristics shown in Table 5-1.
(Although not permitted as memory operands, quad words are shown because quad-word alignment is
desirable for certain memory operands.)
Table 5-1. Memory Operands
Operand
Length
Addr[28–31] if Aligned
Byte
8 bits
xxxx
Half word
2 bytes
xxx0
Word
4 bytes
xx00
Double word
8 bytes
x000
Quad word
16 bytes
0000
Note: An “x” in an address bit position indicates that the bit can be 0 or 1 independent of the state of other bits in the address.
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The concept of alignment is also applied more generally to data in memory. For example, a 12-byte data
item is said to be word-aligned if its address is a multiple of four.
Any memory access that crosses an alignment boundary must be broken into multiple discrete accesses.
For the case of string accesses, the hardware makes no attempt to get aligned in an effort to reduce the
number of discrete accesses. (Multi-word accesses are architecturally required to be aligned.) The
resulting performance degradation depends upon how well each individual access behaves with respect to
the memory hierarchy. At a minimum, additional cache access cycles are required. More dramatically, for
the case of access to a noncacheable page, each discrete access involves an individual bus operation which
will reduce the effective bandwidth of the bus.
The frequent use of misaligned accesses is discouraged since they can compromise the overall
performance of the processor.
5.2
Instruction Set Summary
This section describes instructions and addressing modes defined for the MPC885. These instructions are
divided into the following functional categories:
• Integer instructions—These include arithmetic and logical instructions. For more information, see
Section 5.2.4.1, “Integer Instructions.”
• Load and store instructions—These include integer load and store instructions only. For more
information, see Section 5.2.4.2, “Load and Store Instructions.”
• Flow control instructions—These include branching instructions, condition register logical
instructions, and other instructions that affect the instruction flow. For more information, see
Section 5.2.4.3, “Branch and Flow Control Instructions.”
• Trap instructions—These instructions test for a specified set of conditions; see Section 5.2.4.4,
“Trap Instructions,” for more information.
• Processor control instructions—These instructions synchronize memory accesses and managing
caches and TLBs. For more information, see Sections 5.2.4.5, 5.2.5.1, and 5.2.6.2.
• Memory synchronization instructions—These instructions are used for memory synchronizing.
See Sections 5.2.4.6 and 5.2.5.2 for more information.
• Memory control instructions—These instructions provide control of caches, and TLBs. For more
information, see Sections 5.2.5.3 and 5.2.6.3.
• System linkage instructions—For more information, see Section 5.2.6.1, “System Linkage
Instructions.”
Note that this grouping of instructions does not necessarily indicate the execution unit that processes a
particular instruction or group of instructions. This information, which is useful in taking full advantage
of the MPC885’s parallel instruction execution, is provided in Chapter 8, “Instruction Set,” in The
Programming Environments Manual.
Integer instructions operate on word operands. The architecture uses instructions that are four bytes long
and word-aligned. It provides for byte, half word, and word operand loads and stores between memory and
a set of 32 general-purpose registers (GPRs).
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Arithmetic and logical instructions do not read or modify memory. To use the contents of a memory
location in a computation and then modify the same or another memory location, the memory contents
must be loaded into a register, modified, and then written to the target location using load and store
instructions.
The description of each instruction includes the mnemonic and a formatted list of operands. To simplify
assembly language programming, a set of simplified mnemonics (extended mnemonics in the architecture
specification) and symbols is provided for some of the frequently used instructions; see Appendix F,
“Simplified Mnemonics,” in The Programming Environments Manual for a complete list of simplified
mnemonic examples.
5.2.1
Classes of Instructions
The MPC885 instructions belong to one of the following three classes:
• Defined
• Illegal
• Reserved
Note that while the definitions of these terms are consistent among the MPC8xx processors, the
assignment of these classifications is not. For example, an instruction that is specific to 64-bit
implementations is considered defined for 64-bit implementations but illegal for 32-bit implementations,
such as the MPC885.
The class is determined by examining the primary opcode and the extended opcode, if any. If the opcode,
or combination of opcode and extended opcode, is not that of a defined instruction or of a reserved
instruction, the instruction is illegal.
In future versions of the architecture, instruction codings that are now illegal may become assigned to
instructions in the architecture, or may be reserved by being assigned to processor-specific instructions.
5.2.1.1
Definition of Boundedly Undefined
If instructions are encoded with incorrectly set bits in reserved fields, the results on execution can be said
to be boundedly undefined. If a user-level program executes the incorrectly coded instruction, the resulting
undefined results are bounded in that a spurious change from user to supervisor state is not allowed, and
the level of privilege exercised by the program in relation to memory access and other system resources
cannot be exceeded. Boundedly undefined results for a given instruction may vary between
implementations, and between execution attempts in the same implementation.
5.2.1.2
Defined Instruction Class
Defined instructions are guaranteed to be supported in all MPC8xx implementations, except as stated in
the instruction descriptions in Chapter 8, “Instruction Set,” in The Programming Environments Manual.
The MPC885 provides hardware support for all instructions defined for 32-bit implementations, except
floating-point instructions.
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An MPC8xx processor invokes the illegal instruction error handler (part of the program exception) when
the unimplemented instructions are encountered so they may be emulated in software, as required.
A defined instruction can have invalid forms, as described in the following section.
5.2.1.3
Illegal Instruction Class
Illegal instructions can be grouped into the following categories:
• Instructions that are not implemented in the architecture. These opcodes are available for future
extensions of the architecture; that is, future versions of the architecture may define any of these
instructions to perform new functions.
The following primary opcodes are defined as illegal, but may be used in future extensions to the
architecture:
1, 4, 5, 6, 9, 22, 56, 57, 60, 61
• Instructions that are not implemented in a specific MPC8xx implementation. For example,
instructions that can be executed on 64-bit processors are considered illegal by 32-bit processors.
The following primary opcodes are defined for 64-bit implementations only and are illegal on the
MPC885:
2, 30, 58, 62
• All unused extended opcodes are illegal. The unused extended opcodes can be determined from
information in Section A.2, “Instructions Sorted by Opcode,” in the Programming Environments
Manual and Section 5.2.1.4, “Reserved Instruction Class.” Notice that extended opcodes for
instructions that are defined only for 64-bit implementations are illegal in 32-bit implementations,
and vice versa.
The following primary opcodes have unused extended opcodes.
17, 19, 31, 59, 63 (primary opcodes 30 and 62 are illegal for all 32-bit implementations, but as
64-bit opcodes they have some unused extended opcodes)
• An instruction consisting entirely of zeros is guaranteed to be an illegal instruction. This increases
the probability that an attempt to execute data or uninitialized memory invokes the system illegal
instruction error handler (a program exception). Note that if only the primary opcode consists of
all zeros, the instruction is considered a reserved instruction. This is further described in
Section 5.2.1.4, “Reserved Instruction Class.”
An attempt to execute an illegal instruction invokes the illegal instruction error handler (a program
exception) but has no other effect. See Section 6.1.2.7, “Program Exception (0x00700),” for additional
information about illegal and invalid instruction exceptions.
With the exception of the instruction consisting entirely of binary zeros, the illegal instructions are
available for further additions to the architecture.
5.2.1.4
Reserved Instruction Class
Reserved instructions are allocated to specific implementation-dependent purposes not defined by the
architecture. An attempt to execute an unimplemented reserved instruction invokes the illegal instruction
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error handler (a program exception). See Section 6.1.2.7, “Program Exception (0x00700),” for additional
information about illegal and invalid instruction exceptions.
The following types of instructions are included in this class:
• Implementation-specific instructions
• Optional instructions defined by the architecture but not implemented by the MPC885 (for
example, Floating Square Root (fsqrt) and Floating Square Root Single (fsqrts) instructions)
5.2.2
Addressing Modes
This section provides an overview of conventions for addressing memory and for calculating effective
addresses. For more detailed information, see “Conventions,” in Chapter 4, “Addressing Modes and
Instruction Set Summary,” of the Programming Environments Manual.
5.2.2.1
Memory Addressing
A program references memory using the effective (logical) address computed by the processor when it
executes a memory access or branch instruction or when it fetches the next sequential instruction.
5.2.2.2
Effective Address Calculation
An effective address (EA) is the 32-bit sum computed by the processor when executing a memory access
or branch instruction or when fetching the next sequential instruction. For a memory access instruction, if
the sum of the effective address and the operand length exceeds the maximum effective address, the
memory operand is considered to wrap around from the maximum effective address through effective
address 0, as described in the following paragraphs.
Effective address computations for both data and instruction accesses use 32-bit unsigned binary
arithmetic. A carry from bit 0 is ignored.
Load and store operations have three categories of effective address generation:
• Register indirect with immediate index mode
• Register indirect with index mode
• Register indirect mode
Refer to Section 5.2.4.2.1, “Integer Load and Store Address Generation,” for further discussion of
effective address generation for load and store operations.
Branch instructions have three categories of effective address generation:
•
•
•
Immediate
Link register indirect
Count register indirect
Refer to Section 5.2.4.3.1, “Branch Instruction Address Calculation,” for further discussion of branch
instruction effective address generation.
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5.2.2.3
Synchronization
The synchronization described in this section refers to the state of the processor that is performing the
synchronization.
5.2.2.3.1
Context Synchronization
The System Call (sc) and Return from Interrupt (rfi) instructions perform context synchronization by
allowing previously issued instructions to complete before performing a change in context. Execution of
one of these instructions ensures the following:
• No higher priority exception exists (sc).
• All previous instructions have completed to a point where they can no longer cause an exception.
• Previous instructions complete execution in the context (privilege, protection, and address
translation) under which they were issued.
• The instructions following the sc or rfi instruction execute in the context established by these
instructions.
5.2.2.3.2
Execution Synchronization
An instruction is execution synchronizing if all previously initiated instructions appear to have completed
before the instruction is initiated or, in the case of the Synchronize (sync) and Instruction Synchronize
(isync) instructions, before the instruction completes. For example, the Move to Machine State Register
(mtmsr) instruction is execution synchronizing. It ensures that all preceding instructions have completed
execution and will not cause an exception before the instruction executes, but does not ensure subsequent
instructions execute in the newly established environment. For example, if the mtmsr sets the MSR[PR]
bit, unless an isync immediately follows the mtmsr instruction, a privileged instruction could be executed
or privileged access could be performed without causing an exception even though the MSR[PR] bit
indicates user mode.
5.2.2.3.3
Instruction-Related Exceptions
There are two kinds of exceptions in the MPC885—those caused directly by the execution of an instruction
and those caused by an asynchronous event. Either may cause components of the system software to be
invoked.
Exceptions can be caused directly by the execution of an instruction as follows:
• An attempt to execute an illegal instruction causes the illegal instruction (program exception)
handler to be invoked. An attempt by a user-level program to execute the supervisor-level
instructions listed below causes the privileged instruction (program exception) handler to be
invoked. The MPC885 provides the following supervisor-level instructions—dcbi, mfmsr, mfspr,
mtmsr, mtspr, rfi, tlbie, and tlbsync. Note that the privilege level of the mfspr and mtspr
instructions depends on the SPR encoding.
•
An attempt to access memory that is not available (page fault) causes the ISI exception
handler to be invoked.
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•
An attempt to access memory with an effective address alignment that is invalid for the
instruction causes the alignment exception handler to be invoked. See Section 6.1.2.6,
“Alignment Exception (0x00600),” for restrictions on operand alignment.
• The execution of an sc instruction invokes the system call exception handler that permits a
program to request the system to perform a service.
• The execution of a trap instruction invokes the program exception trap handler.
Exceptions caused by asynchronous events are described in Chapter 6, “Exceptions.”
5.2.3
Instruction Set Overview
This section provides a brief overview of the instructions implemented in the MPC885 and highlights any
special information with respect to how the MPC885 implements a particular instruction. Note that the
categories used in this section correspond to those used in Chapter 4, “Addressing Modes and Instruction
Set Summary,” in The Programming Environments Manual.
Note that some of the instructions have the following optional features:
• CR Update—The dot (.) suffix on the mnemonic enables the update of the CR.
• Overflow option—The ‘o’ suffix indicates that the XER overflow bit is enabled.
5.2.4
PowerPC UISA Instructions
The PowerPC UISA includes the base user-level instruction set (excluding a few user-level cache control,
synchronization, and time base instructions), user-level registers, programming model, data types, and
addressing modes. This section discusses the instructions defined in the UISA.
5.2.4.1
Integer Instructions
This section describes the integer instructions. These consist of the following:
• Integer arithmetic instructions
• Integer compare instructions
• Integer logical instructions
• Integer rotate and shift instructions
Integer instructions use the content of the GPRs as source operands and place results into GPRs, into the
XER, and into condition register (CR) fields.
5.2.4.1.1
Integer Arithmetic Instructions
Table 5-2 lists the integer arithmetic instructions for the MPC885.
Table 5-2. Integer Arithmetic Instructions
Name
Mnemonic
Syntax
Add Immediate
addi
rD,rA,SIMM
Add Immediate Shifted
addis
rD,rA,SIMM
Add
add (add.addo addo.)
rD,rA,rB
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Table 5-2. Integer Arithmetic Instructions (continued)
Name
Mnemonic
Syntax
Subtract From
subf (subf.subfo subfo.)
rD,rA,rB
Add Immediate Carrying
addic
rD,rA,SIMM
Add Immediate Carrying and Record
addic.
rD,rA,SIMM
Subtract from Immediate Carrying
subfic
rD,rA,SIMM
Add Carrying
addc (addc.addco addco.)
rD,rA,rB
Subtract from Carrying
subfc (subfc.subfco subfco.)
rD,rA,rB
Add Extended
adde (adde.addeo addeo.)
rD,rA,rB
Subtract from Extended
subfe (subfe.subfeo subfeo.)
rD,rA,rB
Add to Minus One Extended
addme (addme.addmeo addmeo.)
rD,rA
Subtract from Minus One Extended
subfme (subfme.subfmeo subfmeo.)
rD,rA
Add to Zero Extended
addze (addze.addzeo addzeo.)
rD,rA
Subtract from Zero Extended
subfze (subfze.subfzeo subfzeo.)
rD,rA
Negate
neg (neg.nego nego.)
rD,rA
Multiply Low Immediate
mulli
rD,rA,SIMM
Multiply Low
mullw (mullw.mullwo mullwo.)
rD,rA,rB
Multiply High Word
mulhw (mulhw.)
rD,rA,rB
Multiply High Word Unsigned
mulhwu (mulhwu.)
rD,rA,rB
Divide Word
divw1 (divw.divwo divwo.)
rD,rA,rB
Divide Word Unsigned
divwu (divwu.divwuo divwuo.)
rD,rA,rB
1
Implementation Note: Attempting to use divw to perform either 0x80000000 ÷ -1 or <anything> ÷ 0 sets the
contents of rD to 0x80000000, and if Rc =1, the contents of CR0 are LT = 1, GT = 0, and EQ = 0. SO is set to the
correct value.
Although there is no Subtract Immediate instruction, its effect can be achieved by using an addi instruction
with the immediate operand negated. Simplified mnemonics are provided that include this negation. The
subf instructions subtract the second operand (rA) from the third operand (rB). Simplified mnemonics are
provided in which the third operand is subtracted from the second operand. See Appendix F, “Simplified
Mnemonics,” in The Programming Environments Manual for examples.
5.2.4.1.2
Integer Compare Instructions
The integer compare instructions algebraically or logically compare the contents of rA with either the
UIMM operand, the SIMM operand, or the contents of rB. The comparison is signed for the cmpi and cmp
instructions, and unsigned for the cmpli and cmpl instructions. Table 5-3 lists the integer compare
instructions.
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Table 5-3. Integer Compare Instructions
Name
Syntax1
Mnemonic
Compare Immediate
cmpi
crfD,L,rA,SIMM
Compare
cmp
crfD,L,rA,rB
Compare Logical Immediate
cmpli
crfD,L,rA,UIMM
Compare Logical
cmpl
crfD,L,rA,rB
1
Implementation Note: In these instructions, the L bit is applicable for 64-bit implementations. For the MPC885, if
L = 1 the instruction form is invalid. The core ignores this bit and, therefore, the behavior when L = 1 is identical to the
valid form instruction with L = 0.
The crfD operand can be omitted if the result of the comparison is to be placed in CR0. Otherwise the
target CR field must be specified in the instruction crfD field.
For more information refer to Appendix F, “Simplified Mnemonics,” in the Programming Environments
Manual.
5.2.4.1.3
Integer Logical Instructions
The logical instructions shown in Table 5-4 perform bit-parallel operations. Logical instructions with the
CR update enabled and instructions andi. and andis. set CR field CR0 to characterize the result of the
logical operation. These fields are set as if the sign-extended low-order 32 bits of the result were
algebraically compared to zero. Logical instructions without CR update and the remaining logical
instructions do not modify the CR. Logical instructions do not affect the XER[SO], XER[OV], and
XER[CA] bits.
For simplified mnemonics examples for the integer logical operations see Appendix F, “Simplified
Mnemonics,” in the Programming Environments Manual.
Table 5-4. Integer Logical Instructions
Name
Mnemonic
Syntax
AND Immediate
andi.
rA,rS,UIMM
AND Immediate Shifted
andis.
rA,rS,UIMM
OR Immediate
ori
rA,rS,UIMM
OR Immediate Shifted
oris
rA,rS,UIMM
XOR Immediate
xori
rA,rS,UIMM
XOR Immediate Shifted
xoris
rA,rS,UIMM
AND
and (and.)
rA,rS,rB
OR
or (or.)
rA,rS,rB
XOR
xor (xor.)
rA,rS,rB
NAND
nand (nand.)
rA,rS,rB
NOR
nor (nor.)
rA,rS,rB
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Table 5-4. Integer Logical Instructions (continued)
Name
Mnemonic
Syntax
Equivalent
eqv (eqv.)
rA,rS,rB
AND with Complement
andc (andc.)
rA,rS,rB
OR with Complement
orc (orc.)
rA,rS,rB
Extend Sign Byte
extsb (extsb.)
rA,rS
Extend Sign Half Word
extsh (extsh.)
rA,rS
Count Leading Zeros Word
cntlzw (cntlzw.)
rA,rS
5.2.4.1.4
Integer Rotate and Shift Instructions
Rotation operations are performed on data from a GPR, and the result, or a portion of the result, is returned
to a GPR. See Appendix F, “Simplified Mnemonics,” in The Programming Environments Manual for a
complete list of simplified mnemonics that allows simpler coding of often-used functions such as clearing
the leftmost or rightmost bits of a register, left justifying or right justifying an arbitrary field, and simple
rotates and shifts.
Integer rotate instructions rotate the contents of a register. The result of the rotation is either inserted into
the target register under control of a mask (if a mask bit is 1 the associated bit of the rotated data is placed
into the target register, and if the mask bit is 0 the associated bit in the target register is unchanged), or
ANDed with a mask before being placed into the target register. The integer rotate instructions are listed
in Table 5-5.
Table 5-5. Integer Rotate Instructions
Name
Mnemonic
Syntax
Rotate Left Word Immediate then AND with Mask
rlwinm (rlwinm.)
rA,rS,SH,MB,ME
Rotate Left Word then AND with Mask
rlwnm (rlwnm.)
rA,rS,rB,MB,ME
Rotate Left Word Immediate then Mask Insert
rlwimi (rlwimi.)
rA,rS,SH,MB,ME
The integer shift instructions perform left and right shifts. Immediate-form logical (unsigned) shift
operations are obtained by specifying masks and shift values for certain rotate instructions. Simplified
mnemonics are provided to make coding of such shifts simpler and easier to understand. The integer shift
instructions are listed in Table 5-6.
Table 5-6. Integer Shift Instructions
Name
Mnemonic
Syntax
Shift Left Word
slw (slw.)
rA,rS,rB
Shift Right Word
srw (srw.)
rA,rS,rB
Shift Right Algebraic Word Immediate
srawi (srawi.)
rA,rS,SH
Shift Right Algebraic Word
sraw (sraw.)
rA,rS,rB
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5.2.4.2
Load and Store Instructions
Load and store instructions are issued and translated in program order; however, the accesses can occur
out of order. Synchronizing instructions are provided to enforce strict ordering. This section describes the
load and store instructions of the MPC885, which consist of the following:
• Integer load instructions
• Integer store instructions
• Integer load and store with byte-reverse instructions
• Integer load and store multiple instructions
• Integer load and store string instructions
5.2.4.2.1
Integer Load and Store Address Generation
Integer load and store operations generate effective addresses using register indirect with immediate index
mode, register indirect with index mode, or register indirect mode. See Section 5.2.2.2, “Effective Address
Calculation,” for information about calculating effective addresses. Note that the MPC885 is optimized for
load and store operations that are aligned on natural boundaries, and operations that are not naturally
aligned may suffer performance degradation. Refer to Section 6.1.2.6.1, “Integer Alignment Exceptions,”
for additional information about load and store address alignment exceptions.
5.2.4.2.2
Register Indirect Integer Load Instructions
For integer load instructions, the byte, half word, or word addressed by the EA is loaded into rD. Many
integer load instructions have an update form, in which rA is updated with the generated effective address.
For these forms, the EA is placed into rA and the memory element (byte, half word, word, or double word)
addressed by EA is loaded into rD. Table 5-7 lists the integer load instructions.
Table 5-7. Integer Load Instructions
Name
Mnemonic
Syntax
Load Byte and Zero
lbz
rD,d(rA)
Load Byte and Zero Indexed
lbzx
rD,rA,rB
Load Byte and Zero with Update
lbzu
rD,d(rA)
Load Byte and Zero with Update Indexed
lbzux
rD,rA,rB
Load Half Word and Zero
lhz
rD,d(rA)
Load Half Word and Zero Indexed
lhzx
rD,rA,rB
Load Half Word and Zero with Update
lhzu
rD,d(rA)
Load Half Word and Zero with Update Indexed
lhzux
rD,rA,rB
Load Half Word Algebraic
lha
rD,d(rA)
Load Half Word Algebraic Indexed
lhax
rD,rA,rB
Load Half Word Algebraic with Update
lhau
rD,d(rA)
Load Half Word Algebraic with Update Indexed
lhaux
rD,rA,rB
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Table 5-7. Integer Load Instructions (continued)
Name
Mnemonic
Syntax
Load Word and Zero
lwz
rD,d(rA)
Load Word and Zero Indexed
lwzx
rD,rA,rB
Load Word and Zero with Update
lwzu
rD,d(rA)
Load Word and Zero with Update Indexed
lwzux
rD,rA,rB
5.2.4.2.3
Integer Store Instructions
For integer store instructions, the contents of rS are stored into the byte, half word, word, or double word
in memory addressed by the effective address (EA). Many store instructions have an update form, in which
rA is updated with the EA. For these forms, the following rules apply:
• If rA ≠ 0, the EA is placed into rA.
• If rS = rA, the contents of rS are copied to the target memory element, then the generated EA is
placed into rA (rS).
The MPC885 defines store with update instructions with rA = 0 and integer store instructions with the CR
update option enabled (Rc[31] = 1) to be invalid forms. Table 5-8 lists integer store instructions for the
MPC885.
Table 5-8. Integer Store Instructions
Name
Mnemonic
Syntax
Store Byte
stb
rS,d(rA)
Store Byte Indexed
stbx
rS,rA,rB
Store Byte with Update
stbu
rS,d(rA)
Store Byte with Update Indexed
stbux
rS,rA,rB
Store Half Word
sth
rS,d(rA)
Store Half Word Indexed
sthx
rS,rA,rB
Store Half Word with Update
sthu
rS,d(rA)
Store Half Word with Update Indexed
sthux
rS,rA,rB
Store Word
stw
rS,d(rA)
Store Word Indexed
stwx
rS,rA,rB
Store Word with Update
stwu
rS,d(rA)
Store Word with Update Indexed
stwux
rS,rA,rB
5.2.4.2.4
Integer Load and Store with Byte-Reverse Instructions
Table 5-9 describes integer load and store with byte-reverse instructions. When used in a system operating
with the default big-endian byte order, these instructions have the effect of loading and storing data in
little-endian order. Likewise, when used in a system operating with little-endian byte order, these
instructions have the effect of loading and storing data in big-endian order. For more information about
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big-endian and little-endian byte ordering, see “Byte Ordering” in Chapter 3, “Operand Conventions,” in
The Programming Environments Manual.
Table 5-9. Integer Load and Store with Byte-Reverse Instructions
Name
Mnemonic
Syntax
Load Half Word Byte-Reverse Indexed
lhbrx
rD,rA,rB
Load Word Byte-Reverse Indexed
lwbrx
rD,rA,rB
Store Half Word Byte-Reverse Indexed
sthbrx
rS,rA,rB
Store Word Byte-Reverse Indexed
stwbrx
rS,rA,rB
5.2.4.2.5
Integer Load and Store Multiple Instructions
The integer load/store multiple instructions move blocks of data to and from the GPRs. In some
implementations, these instructions are likely to have greater latency and take longer to execute, perhaps
much longer, than a sequence of individual load or store instructions that produce the same results.
When the MPC885 is operating with little-endian byte order, execution of a load or store multiple
instruction causes the system alignment error handler to be invoked; see “Byte Ordering” in Chapter 3,
“Operand Conventions,” in the Programming Environments Manual for more information. Table 5-10 lists
the integer load and store multiple instructions for the MPC885.
Table 5-10. Integer Load and Store Multiple Instructions
Name
Mnemonic
Syntax
Load Multiple Word
lmw
rD,d(rA)
Store Multiple Word
stmw
rS,d(rA)
5.2.4.2.6
Integer Load and Store String Instructions
The integer load and store string instructions allow movement of data from memory to registers or from
registers to memory without concern for alignment. These instructions can be used for a short move
between arbitrary memory locations or to initiate a long move between misaligned memory fields.
When the MPC885 is operating with little-endian byte order, execution of a load or store string instruction
causes the system alignment error handler to be invoked; see “Byte Ordering” in Chapter 3, “Operand
Conventions,” in the Programming Environments Manual for more information. Table 5-11 lists the
integer load and store string instructions.
Table 5-11. Integer Load and Store String Instructions
Name
Mnemonic
Syntax
Load String Word Immediate
lswi
rD,rA,NB
Load String Word Indexed
lswx
rD,rA,rB
Store String Word Immediate
stswi
rS,rA,NB
Store String Word Indexed
stswx
rS,rA,rB
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Load string and store string instructions may involve operands that are not word-aligned. As described in
“Alignment Exception (0x00600)” in Chapter 6, “Exceptions,” in the Programming Environments
Manual, a misaligned string operation suffers a performance penalty compared to a word-aligned
operation of the same type.
When a string operation crosses a page boundary, the instruction may be interrupted by a DSI exception
associated with the address translation of the second page. In this case, the MPC885 performs some or all
memory references from the first page and none from the second before taking the exception. On return
from the DSI exception, the load or store string instruction will re-execute from the beginning. For more
information, refer to “DSI Exception (0x00300)” in Chapter 6, “Exceptions,” in the Programming
Environments Manual.
5.2.4.3
Branch and Flow Control Instructions
Branch instructions are executed by the branch processing unit (BPU). The BPU receives branch
instructions from the fetch unit and performs condition register (CR) lookahead operations on conditional
branches to resolve them early, achieving the effect of a zero-cycle branch in many cases.
Some branch instructions can redirect instruction execution conditionally based on the value of bits in the
CR. When the branch processor encounters one of these instructions, it scans the execution pipelines to
determine whether an instruction in progress may affect the particular CR bit. If no interlock is found, the
branch can be resolved immediately by checking the bit in the CR and taking the action defined for the
branch instruction.
If an interlock is detected, the branch is considered unresolved and the direction of the branch is predicted
using static branch prediction as described in “Conditional Branch Control” in Chapter 4, “Addressing
Modes and Instruction Set Summary,” in the Programming Environments Manual. The interlock is
monitored while instructions are fetched for the predicted branch. When the interlock is cleared, the branch
processor determines whether the prediction was correct based on the value of the CR bit. If the prediction
is correct, the branch is considered completed and instruction fetching continues. If the prediction is
incorrect, the fetched instructions are purged, and instruction fetching continues along the alternate path.
See Chapter 9, “Instruction Execution Timing,” for information about how branches are executed.
5.2.4.3.1
Branch Instruction Address Calculation
Branch instructions can alter the sequence of instruction execution. Instruction addresses are always
assumed to be word aligned; the processor ignores the two low-order bits of the generated branch target
address.
Branch instructions compute the effective address (EA) of the next instruction address using the following
addressing modes:
• Branch relative
• Branch conditional to relative address
• Branch to absolute address
• Branch conditional to absolute address
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•
•
Branch conditional to link register
Branch conditional to count register
5.2.4.3.2
Branch Instructions
Table 5-12 lists the branch instructions. To simplify assembly language programming, a set of simplified
mnemonics and symbols is provided for the most frequently used forms of branch conditional, compare,
trap, rotate and shift, and certain other instructions. See Appendix F, “Simplified Mnemonics,” in the
Programming Environments Manual for a list of simplified mnemonics.
Table 5-12. Branch Instructions
Name
Mnemonic
Syntax
Branch
b (ba bl bla)
target_addr
Branch Conditional
bc (bca bcl bcla)
BO,BI,target_addr
Branch Conditional to Link Register
bclr (bclrl)
BO,BI
Branch Conditional to Count Register
bcctr (bcctrl)
BO,BI
5.2.4.3.3
Condition Register Logical Instructions
Condition register logical instructions, shown in Table 5-13, and the Move Condition Register Field
(mcrf) instruction are also defined as flow control instructions.
Table 5-13. Condition Register Logical Instructions
Name
Mnemonic
Syntax
Condition Register AND
crand
crbD,crbA,crbB
Condition Register OR
cror
crbD,crbA,crbB
Condition Register XOR
crxor
crbD,crbA,crbB
Condition Register NAND
crnand
crbD,crbA,crbB
Condition Register NOR
crnor
crbD,crbA,crbB
Condition Register Equivalent
creqv
crbD,crbA,crbB
Condition Register AND with Complement
crandc
crbD,crbA,crbB
Condition Register OR with Complement
crorc
crbD,crbA,crbB
Move Condition Register Field
mcrf
crfD,crfS
Note that if the LR update option is enabled for any of these instructions, these forms of the instructions
are invalid in the MPC885.
5.2.4.4
Trap Instructions
The trap instructions shown in Table 5-14 are provided to test for a specified set of conditions. If any of
the conditions tested by a trap instruction are met, the system trap handler is invoked. If the tested
conditions are not met, instruction execution continues normally.
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Table 5-14. Trap Instructions
Name
Mnemonic
Syntax
Trap Word Immediate
twi
TO,rA,SIMM
Trap Word
tw
TO,rA,rB
See Appendix F, “Simplified Mnemonics,” in the Programming Environments Manual for a complete set
of simplified mnemonics.
5.2.4.5
Processor Control Instructions
Processor control instructions are read from and write to the condition register (CR), machine state register
(MSR), and special-purpose registers (SPRs), and to read from the time base register (TBU or TBL).
5.2.4.5.1
Move to/from Condition Register Instructions
Table 5-15 lists the instructions provided by the MPC885 for reading from or writing to the CR.
Table 5-15. Move to/from Condition Register Instructions
Name
Mnemonic
Syntax
Move to Condition Register Fields
mtcrf
CRM,rS
Move to Condition Register from XER
mcrxr
crfD
Move from Condition Register
mfcr
rD
5.2.4.6
Memory Synchronization Instructions—UISA
Memory synchronization instructions control the order in which memory operations are completed with
respect to asynchronous events, and the order in which memory operations are seen by other processors or
memory access mechanisms. See Section 7.6.6, “Atomic Memory References,” for additional information
about these instructions and about related aspects of memory synchronization. Table 5-16 lists the UISA
memory synchronization instructions for the MPC885.
Table 5-16. Memory Synchronization Instructions—UISA
Name
Mnemonic
Syntax
Load Word and Reserve Indexed
lwarx
rD,rA,rB
Store Word Conditional Indexed
stwcx.
rS,rA,rB
Synchronize
sync
—
The sync instruction delays execution of subsequent instructions until previous instructions have
completed to the point that they can no longer cause an exception and until all previous memory accesses
are performed globally; the sync operation is not broadcast onto the MPC885 bus interface. Additionally,
all load and store cache/bus activities initiated by prior instructions are completed. Touch load operations
(dcbt and dcbtst) are required to complete at least through address translation, but not required to
complete on the bus.
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The functions performed by the sync instruction normally take a significant amount of time to complete;
as a result, frequent use of this instruction may adversely affect performance. In addition, the number of
cycles required to complete a sync instruction depends on system parameters and on the processor's state
when the instruction is issued.
The proper paired use of the lwarx and stwcx. instructions allows programmers to emulate common
semaphore operations such as “test and set,” “compare and swap,” “exchange memory,” and “fetch and
add.” Examples of these semaphore operations can be found in Appendix E, “Synchronization
Programming Examples,” in the Programming Environments Manual. The lwarx instruction must be
paired with an stwcx. instruction with the same effective address used for both instructions of the pair.
Note that the reservation granularity is 16 bytes.
The lwarx and stwcx. instructions are implemented according to the PowerPC architecture requirements.
The concept behind the use of the lwarx and stwcx. instructions is that a processor may load a semaphore
from memory, compute a result based on the value of the semaphore, and conditionally store it back to the
same location (only if that location has not been modified since it was first read), and determine if the store
was successful. The conditional store is performed based upon the existence of a reservation established
by the preceding lwarx instruction. If the reservation exists when the store is executed, the store is
performed and a bit is set in the CR. If the reservation does not exist when the store is executed, the target
memory location is not modified and a bit is cleared in the CR.
If the store was successful, the sequence of instructions from the read of the semaphore to the store that
updated the semaphore appear to have been executed atomically (that is, no other processor or mechanism
modified the semaphore location between the read and the update), thus providing the equivalent of a real
atomic operation. However, in reality, other processors may have read from the location during this
operation. In the MPC885, the reservations are made on behalf of aligned 16-byte sections of the memory
address space.
The lwarx and stwcx. instructions require the EA to be aligned. Exception handling software should not
attempt to emulate a misaligned lwarx or stwcx. instruction, because there is no correct way to define the
address associated with the reservation.
In general, the lwarx and stwcx. instructions should be used only in system programs, which can be
invoked by application programs as needed.
At most, one reservation exists simultaneously on any processor. The address associated with the
reservation can be changed by a subsequent lwarx instruction. The conditional store is performed based
upon the existence of a reservation established by the preceding lwarx, regardless of whether the address
generated by the lwarx matches that generated by the stwcx. instruction. A reservation held by the
processor is cleared by one of the following:
• Executing an stwcx. instruction to any address
• Attempt by another device to modify a location in the reservation granularity (16 bytes)
In write-through mode, lwarx and stwcx. do not cause a DSI exception.
The sync instruction guarantees that previously fetched instructions finish before any subsequent
instructions are dispatched to the execution units. It does not affect fetching; instructions continue to be
fetched up to the instruction queue limit, but dispatch stalls until the sync finishes.
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The original purpose of the sync instruction was to synchronize coherent memory with other processors
in a multiprocessor system; it makes sure that memory as seen by one processor is the same as memory
seen by the other processors, and broadcasts a special signal to signal that the action is taking place.
However, the MPC885 does not support this enforcement of coherency in a multiprocessor system, and it
broadcasts no special synchronization signal. The MPC885 simply expects other processors not to rely on
coherency of memory that it has cached in copy-back mode.
The only case where a sync instruction would be useful in an MPC8xx system is if software modified the
page table structure associated with the SMMU only and needed to guarantee that data accesses after that
instruction would be executed in the new data context. However, this is an unexpected special case; isync
would work here, but the pipeline need not be flushed in this case, so sync is sufficient.
5.2.5
PowerPC VEA Instructions
The PowerPC VEA describes the semantics of the memory model that can be assumed by software
processes, and includes descriptions of the cache model, cache control instructions, address aliasing, and
other related issues.
5.2.5.1
Processor Control Instructions
In addition to the move to condition register instructions specified by the UISA, the VEA defines the Move
from Time Base (mftb) instruction for reading the contents of the time base register. The mftb is a
user-level instruction and is shown in Table 5-17
Simplified mnemonics are provided for the mftb instruction so it can be coded with the TBR name as part
of the mnemonic rather than requiring it to be coded as an operand. The mftb instruction serves as both a
basic and simplified mnemonic. Assemblers recognize an mftb mnemonic with two operands as the basic
form, and an mftb mnemonic with one operand as the simplified form. Simplified mnemonics are also
provided for Move from Time Base Upper (mftbu), which is a variant of the mftb instruction rather than
of mfspr. The MPC885 ignores the extended opcode differences between mftb and mfspr by ignoring bit
25 of both instructions and treating them both identically. For more information refer to Appendix F,
“Simplified Mnemonics,” in the Programming Environments Manual.
Table 5-17. Move from Time Base Instruction
Name
Move from Time Base
5.2.5.2
Mnemonic
mftb
Syntax
rD, TBR
Memory Synchronization Instructions—VEA
Memory synchronization instructions control the order in which memory operations are completed with
respect to asynchronous events, and the order in which memory operations are seen by other processors or
memory access mechanisms. See Chapter 7, “Instruction and Data Caches,” for additional information
about these instructions and about related aspects of memory synchronization.
Table 5-18 lists the VEA memory synchronization instructions for the MPC885.
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Table 5-18. Memory Synchronization Instructions—VEA
Name
Mnemonic
Syntax
MPC885 Notes
Enforce In-Order
Execution of I/O
eieio
—
During execution, the LSU waits for previous accesses to terminate before
beginning accesses associated with load/store instructions after an eieio.
Instruction
Synchronize
isync
—
The isync instruction waits for all previous instructions to complete and
discards any prefetched instructions, causing subsequent instructions to be
refetched from memory.
5.2.5.2.1
eieio Behavior
The purpose of eieio is to prevent loads and stores from executing speculatively when appropriate. This
might be desirable for a FIFO, where performing a read or write changes the FIFO's data. This should not
be done unless it is certain that the instruction will be completed and not cancelled.
The same function as eieio can be accomplished by defining a memory space as having the guarded
attribute in the MMU, in which case, the eieio instruction is redundant.
However, eieio could be useful in the rare event that a region where speculative accesses are not allowed
lies in the middle of a non-guarded page.
5.2.5.2.2
isync Behavior
The isync instruction is context synchronizing, which guarantees that all of the effects of previous
instructions are in place and any instructions in the instruction queue are flushed (which means all
instructions that were in the instruction queue need to be refetched). In the MPC885, fetching an isync
instruction causes fetch to stall, so no refetching is required. On the MPC885, writes to SPRs and MSR
that affect context are automatically context synchronizing; thus, an isync is not required before these
instructions. However, isync should be inserted after these instructions to ensure that instructions are
fetched in the appropriate context. Furthermore, load/store instructions that update the MMU page tables
in external memory should both be preceded and followed by an isync to ensure that instructions before
and after such instructions are fetched and completed in the appropriate context.
5.2.5.3
Memory Control Instructions—VEA
Memory control instructions include the following types:
• Cache management instructions
• Translation lookaside buffer (TLB) management instructions
This section describes the user-level cache management instructions defined by the VEA. See
Section 5.2.6.3, “Memory Control Instructions—OEA,” for information about supervisor-level cache and
translation look aside buffer management instructions.
The instructions listed in Table 5-19 provide user-level programs the ability to manage on-chip caches.
As with other memory-related instructions, the effect of the cache management instructions on memory
are weakly ordered. If the programmer needs to ensure that cache or other instructions have been
performed with respect to all other processors and system mechanisms, a sync instruction must be placed
in the program following those instructions.
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Note that when data address translation is disabled (MSR[DR] = 0), the Data Cache Block Set to Zero
(dcbz) instruction allocates a cache block in the cache and may not verify that the physical address is valid.
If a cache block is created for an invalid physical address, a machine check condition may result when an
attempt is made to write that cache block back to memory. The cache block could be written back as a
result of the execution of an instruction that causes a cache miss and the invalid addressed cache block is
the target for replacement or a Data Cache Block Store (dcbst) instruction.
Table 5-19 lists the cache instructions that are accessible to user-level programs.
Table 5-19. User-Level Cache Instructions
Name
Mnemonic
Syntax
MPC885 Notes
Data Cache Block Touch
dcbt
rA,rB
Data Cache Block Touch for
Store
dcbtst
rA,rB
The appropriate cache block is checked for a hit. If it is a miss,
the instruction is treated as a regular miss, except that bus
error does not cause an exception. If no error occurs, the
cache is updated.
Data Cache Block Set to Zero dcbz
rA,rB
Executes as defined in the VEA.
Data Cache Block Store
dcbst
rA,rB
Executes as defined in the VEA.
Data Cache Block Flush
dcbf
rA,rB
Executes as defined in the VEA.
Instruction Cache Block
Invalidate
icbi
rA,rB
The MMU translates the EA and the associated instruction
cache block is invalidated if hit.
5.2.6
PowerPC OEA Instructions
The PowerPC OEA includes the structure of the memory management model, supervisor-level registers,
and the exception model.
5.2.6.1
System Linkage Instructions
This section describes system linkage instructions (see Table 5-20). The sc instruction is a user-level
instruction that permits a user program to call on the system to perform a service and causes the processor
to take an exception. The Return from Interrupt (rfi) instruction is a supervisor-level instruction that is
useful for returning from an exception handler.
Table 5-20. System Linkage Instructions
Name
Mnemonic
Syntax
System Call
sc
—
Return from Interrupt
rfi
—
5.2.6.2
Processor Control Instructions—OEA
Processor control instructions read from and write to the condition register (CR), machine state register
(MSR), and special-purpose registers (SPRs), and to read from the time base register (TBU or TBL).
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5.2.6.2.1
Move to/from Machine State Register Instructions
Table 5-15 lists the instructions provided by the MPC885 for reading from or writing to the MSR.
Table 5-21. Move to/from Machine State Register Instructions
Name
Mnemonic
Syntax
Move to Machine State Register
mtmsr
rS
Move from Machine State Register
mfmsr
rD
5.2.6.2.2
Move to/from Special-Purpose Register Instructions
Simplified mnemonics are provided for the mtspr and mfspr instructions so they can be coded with the
SPR name as part of the mnemonic rather than as a numeric operand. See Appendix F, “Simplified
Mnemonics,” in the Programming Environments Manual for simplified mnemonic examples. The mtspr
and mfspr instructions are shown in Table 5-22.
Table 5-22. Move to/from Special-Purpose Register Instructions
Name
Mnemonic
Syntax
Move to Special-Purpose Register
mtspr
SPR,rS
Move from Special-Purpose Register
mfspr
rD,SPR
For mtspr and mfspr instructions, the SPR number coded in assembly language does not appear directly
as a 10-bit binary number in the instruction. The number coded is split into two 5-bit halves that are
reversed in the instruction encoding, with the high-order 5 bits appearing in bits 16–20 of the instruction
encoding and the low-order 5 bits in bits 11–15.
If the SPR field contains a value not shown in Section 4.1, “MPC885 Register Implementation,” either the
program exception handler is invoked or results are boundedly undefined.
5.2.6.3
Memory Control Instructions—OEA
This section describes memory control instructions, which include the following types:
• Cache management instructions
• TLB management instructions
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Chapter 6
Exceptions
Core exceptions can be generated when an exception condition occurs. Exception sources in the MPC885
include the following:
• External interrupt request
• Certain memory access conditions (protection faults and bus errors)
• Internal errors, such as an attempt to execute an unimplemented opcode
• Trap instructions
• Internal exceptions (breakpoints and debug counter’s expiration)
Exception handling is transparent to user software and uses the same mechanism to handle all types of
exceptions. When an exception is taken, control is transferred to an exception handler located at an offset
defined for the type of exception encountered. The exception prefix bit, MSR[IP], determines whether this
base address for the vector table resides at 0x000n_nnnn (IP = 0) or 0xFFFn_nnnn (IP = 1). Exceptions
are handled in supervisor mode.
After the exception has been handled, the handler returns control to the interrupting program. As specified
in the Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, the
core implements a precise exception model. This means that when an exception is taken, the following
conditions are met:
• Subsequent instructions in the program flow are discarded.
• Previous instructions finish and write back their results.
• The address of the faulting instruction is saved in SRR0 and the machine state of the interrupted
process is saved in SRR1.
• When the exception is taken, the instruction causing the exception might not have started
executing, could be partially executed, or has completed, depending on the exception and
instruction types. See Table 6-20.
For more information, see Section 6.1.4, “Implementing the Precise Exception Model.”
6.1
Exceptions
The OEA defines a set of exceptions for processors which implement the PowerPC architecture, some of
which are optional. The following sections describe exceptions implemented on the MPC885. Those
defined by the OEA are described in Section 6.1.2, “PowerPC-Defined Exceptions.” Section 6.1.3,
“Implementation-Specific Exceptions,” describes implementation-specific exceptions.
All exceptions associated with memory are implemented as precise, which means that a load/store
instruction is not complete until all possible error indications are sampled from the load/store bus. This
also implies that a store or nonspeculative load instruction is not issued to the load/store bus until all
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Exceptions
previous instructions have completed. If a late error occurs, a store cycle (or a nonspeculative load cycle)
can be issued and aborted.
In each exception handler, when registers SRR0 and SRR1 are saved, MSR[RI] can be set.
Table 6-1 defines the offset value by exception type and the sections that follow describe each exception
in detail. Note that the base is determined by the setting of MSR[IP].
Table 6-1. Offset of First Instruction by Exception Type
Offset
Exception
Description
OEA-Defined Exceptions
0x00000
Reserved
—
0x00100
System reset interrupt
See Section 6.1.2.1, “System Reset Interrupt (0x00100).”
0x00200
Machine check interrupt
See Section 6.1.2.2, “Machine Check Interrupt (0x00200).”
0x00300
DSI
A DSI exception is never generated by hardware, but software may branch to
this location because of an data TLB error or miss exception. See
Section 6.1.2.3, “DSI Exception (0x00300).”
0x00400
ISI
An ISI exception is never generated by the hardware, but software may
branch to this location because of an implementation-specific instruction TLB
error exception. See Section 6.1.2.4, “ISI Exception (0x00400).”
0x00500
External interrupt
See Section 6.1.2.5, “External Interrupt Exception (0x00500).”
0x00600
Alignment
Alignment exceptions result from the following conditions:
• The operand of a load/store multiple is not word-aligned.
• The operand of a lwarx or stwcx. is not word-aligned.
• The operand of a load/store instruction is not naturally aligned when
MSR[LE] = 1.
• Trying to execute a multiple/string instruction when MSR[LE] = 1.
See Section 6.1.2.3, “DSI Exception (0x00300).”
0x00700
Program
The MPC885 cannot generate a floating-point exception type exception. See
Section 6.1.2.7, “Program Exception (0x00700).” An implementation-specific
software emulation exception is generated instead of an illegal instruction
type program exception. A privileged instruction program exception is
generated for an on-core valid SPR field or any SPR encoded as an external
SPR if SPR[0] = 1 and MSR[PR] = 1, as well as for attempts to execute
supervisor-level instructions when MSR[PR] = 1. See Table 6-11.
0x00800
Floating-point unavailable
The MPC885 cannot generate a floating-point exception. Attempting to
execute a floating-point instruction causes an implementation-specific
software emulation exception (see Section 6.1.3.1, “Software Emulation
Exception (0x01000)”) regardless of the setting of MSR[FP].
0x00900
Decrementer
See Section 6.1.2.8, “Decrementer Exception (0x00900).”
0x00A00– Reserved
0x00B00
—
0x00C00
System call
See Section 6.1.2.9, “System Call Exception (0x00C00).”
0x00D00
Trace
See Section 6.1.2.10, “Trace Exception (0x00D00).”
0x00E00
Floating-point assist
See Section 6.1.2.11, “Floating-Point Assist Exception.”
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Table 6-1. Offset of First Instruction by Exception Type (continued)
Offset
Exception
Description
Implementation-Specific Exceptions
0x01000
Software emulation
See Section 6.1.3.1, “Software Emulation Exception (0x01000).”
0x01100
Instruction TLB miss
See Section 6.1.3.2, “Instruction TLB Miss Exception (0x01100).”
0x01200
Data TLB miss
See Section 6.1.3.3, “Data TLB Miss Exception (0x01200).”
0x01300
Instruction TLB error
See Section 6.1.3.4, “Instruction TLB Error Exception (0x01300).”
0x01400
Data TLB error
See Section 6.1.3.5, “Data TLB Error Exception (0x014000).”
0x015000x01B00
Reserved
—
0x01C00
Data breakpoint
See Section 6.1.3.6, “Debug Exceptions (0x01C00–0x01F00).”
0x01D00
Instruction breakpoint
0x01E00
Peripheral breakpoint
0x01F00
Nonmaskable development port
6.1.1
Exception Ordering
There are two types of exceptions. Instruction-related exceptions (synchronous exceptions) and
asynchronous exceptions (interrupts).
Synchronous exceptions are detected while the core is processing the instruction. These exceptions are
handled in strict program order and cannot be nested. A single instruction may generate multiple
exceptions; however, any subsequent exceptions are not detected until the first exception is handled and
control is returned to the program.
If more than one instruction in the pipeline causes an exception or if one instruction causes multiple
exceptions, the first exception in program order is taken first. Subsequent instructions are flushed and
additional instruction-related exceptions are handled in order.
Typically, asynchronous exceptions are generated by signals or by other hardware conditions. Table 6-2
lists the instruction-related exceptions in the order of detection within the instruction processing.
Table 6-2. Instruction-Related Exception Detection Order
Number
Exception Type
Cause
1
Trace
Trace bit asserted 1
2
ITLB miss 2
Instruction MMU TLB miss
3
ITLB error 2
Instruction MMU protection/translation error
4
Machine check
Fetch error
5
Debug instruction breakpoint 2
6
Software emulation exception
2
Match detection
Attempt to invoke unimplemented feature
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Table 6-2. Instruction-Related Exception Detection Order
Number
73
Exception Type
Cause
Privileged instruction
Attempt to execute privileged instruction in user mode
Alignment
Load/store checking
System call
sc instruction
Trap
Trap instruction
8
DTLB miss 2
Data TLB miss
9
DTLB error 2
Data TLB protection/translation error
10
Machine check
Load or store access error
11
Debug L- breakpoint 2
Match detection
1
The trace mechanism is implemented by letting one instruction go as if no trace is enabled and trapping the second
instruction. This, of course, refers to this second instruction.
2 MPC885-specific exception.
3 Exclusive for any one instruction.
When multiple exception conditions exist, only the highest priority exception is taken, as shown in
Table 6-3.
Table 6-3. Exception Priority
Priority
Exception Type
Cause
1
Development port nonmaskable interrupt
Signal from the development port
2
System reset interrupt
IRQ0 assertion
3
Instruction-related exceptions
Instruction processing
4
Peripheral breakpoint request or development port maskable interrupt Breakpoint signal from any
peripheral
5
External interrupt (masked if MSR[EE] = 0)
Signal from the interrupt controller
6
Decrementer interrupt (masked if MSR[EE] = 0)
Decrementer request
6.1.2
PowerPC-Defined Exceptions
The following sections describe the exceptions as they are defined by the OEA and describes how they are
implemented on the MPC885.
6.1.2.1
System Reset Interrupt (0x00100)
A system reset interrupt occurs when IRQ0 is asserted. When the exception is taken, processing begins at
offset 0x00100. A hard or soft reset also causes program execution to begin fetching at 0x00100 after the
associated reset actions. Table 6-4 shows register settings.
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Table 6-4. Register Settings After a System Reset Interrupt Exception
Register
Setting
SRR0
Set to the EA of the next instruction of the interrupted process.
SRR1
Saves the machine status before exceptions and to restore status when an rfi instruction is executed.
1–4
0
10–15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR
IP
ME
LE
Other
6.1.2.2
No change
No change
Value of MSR[ILE] of the interrupted process.
0
Machine Check Interrupt (0x00200)
A machine check interrupt indication is received from the U bus in response to an address or data tenure.
It is typically caused by an access for which the address does not exist or a data error occurs.
As defined in the OEA, machine check interrupts are enabled when MSR[ME] = 1. If MSR[ME] = 0 and
a machine check condition is detected, the processor enters the checkstop state. The behavior of the core
in checkstop state is dependent on the working mode as defined in Section 53.3.1.1, “Debug Mode Enable
vs. Debug Mode Disable.” When debug mode is enabled, debug mode is entered instead of checkstop state.
When debug mode is disabled, instruction processing is suspended and cannot be restarted without
resetting the core.
An indication that can generate an automatic reset in this condition is sent to the system interface unit. See
Section 11.1.3.2, “Checkstop Reset,” and Section 14.6.2, “PLL and Reset Control Register (PLPRCR),”
for more details. If MSR[ME] = 1, the machine check interrupt is taken. If SRR1[30] = 1, the interrupt is
recoverable. Instruction fetching begins at offset 0x00200 and the registers are set as shown in Table 6-5.
Table 6-5. Register Settings After a Machine Check Interrupt Exception
Register
Setting
SRR0
Set to the EA of the instruction that caused the exception.
SRR1
1
2–4
10–15
Others
1 for instruction fetch-related errors; 0 for load/store-related errors.
0
0
Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR
IP
ME
LE
Other
No change
0
Copied from the ILE setting of the interrupted process
0
DSISR
Set when the load/store bus is used:
0–14
0
15–16
Set to bits 29-30 of the instruction if X-form instruction and to 0b00 if D-form.
17
Set to bit 25 of the instruction if X-form instruction and to bit 5 if D-form.
18–21
Set to bits 21-24 of the instruction if X-form instruction and to bits 1-4 if D-form.
22–31
Set to bits 6-15 of the instruction.
DAR
When the load/store bus is used, DAR holds the EA of the data access that caused the exception.
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6.1.2.3
DSI Exception (0x00300)
DSI exceptions are never generated by the hardware. Software may branch to this location as a result of
either implementation specific DTLB error interrupt or implementation specific STLB miss interrupt.
6.1.2.4
ISI Exception (0x00400)
ISI exceptions is never generated by the hardware. The software may branch to this location as a result of
an implementation-specific ITLB error interrupt.
6.1.2.5
External Interrupt Exception (0x00500)
In the MPC885 the external interrupt is generated by the on-chip interrupt controller. It is software
acknowledged and maskable by MSR[EE], which hardware clears automatically to disable external
interrupts when any exception is taken.
When an external interrupt is detected, program execution continues until all previous instructions retire
from the completion queue and the exception is assigned to the instruction last entry in the completion
queue (at point B in Table 6-19). However, the following conditions must be met before the instruction at
the end of the queue can retire.
• The instruction must be completed without exception
• The instruction must either be a mtspr, mtmsr, rfi, a memory reference, or a memory- or
cache-control instruction.
Instructions not fitting these criteria are discarded along with any execution results. After the exception
handler completes, execution resumes with the first instruction that was discarded. If all the instructions
in the completion queue were allowed to complete, execution at the end of the exception handler resumes
with the next instruction. External exception latency depends on the time required to reference memory.
The measurement is equal to the time taken for one of the following three events, in addition to the interval
from B to E, as shown in Table 6-19.
• Longest load/store multiple/string instruction used
• One bus cycle for aligned access
• Two bus cycles for unaligned access
System-level exception latency can be longer than the interval from B to E. If an instruction ahead of the
exception-causing instruction also generates an exception, that exception is recognized first. If it is
important to minimize exception latency, exception handlers should save the machine context and reenable
exceptions as quickly as possible so pending external exceptions are handled quickly.
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Register settings for the external interrupt exception are shown in Table 6-6.
Table 6-6. Register Settings after an External Interrupt
Register
Setting Description
SRR0
Set to the effective address of the instruction that the processor would have attempted to execute next if
no interrupt conditions were present.
SRR1
0
Loaded with equivalent bits from the MSR
1–4
Cleared
5–9
Loaded with equivalent bits from the MSR
10–15 Cleared
16–31 Loaded with equivalent bits from the MSR
Note that depending on the implementation, reserved bits in the MSR may not be copied to SRR1.
MSR
POW
ILE
EE
PR
6.1.2.6
0
—
0
0
FP
ME
SE
BE
IP
IR
DR
RI
0
—
0
0
—
0
0
0
LE
Set to value of ILE
Alignment Exception (0x00600)
This section describes conditions that can cause alignment exceptions in the processor. Similar to DSI
exceptions, alignment exceptions use SRR0 and SRR1 to save the machine state and DSISR to determine
the source of the exception. An alignment exception occurs when no higher priority exception exists and
the implementation cannot perform a memory access for one of the following reasons:
• The operand of lmw, stmw, lwarx, or stwcx. is not aligned.
• The instruction is lmw, stmw, lswi, lswx, stswi, or stswx and the processor is in little-endian mode.
• An unaligned load or store in little-endian mode.
For lmw, stmw, lswi, lswx, stswi, and stswx instructions in little-endian mode, an alignment exception
always occurs. For lmw and stmw instructions with an operand that is not aligned in big-endian mode, and
for lwarx and stwcx. with an operand that is not aligned in either endian mode, an implementation may
yield boundedly-undefined results instead of causing an alignment exception. For all other cases listed
above, an implementation may execute the instruction correctly instead of causing an alignment exception.
The register settings for alignment exceptions are shown in Table 6-7.
Table 6-7. Register Settings after an Alignment Exception
Register
Setting Description
SRR0
Set to the effective address of the instruction that caused the exception.
SRR1
0
Loaded with equivalent bits from the MSR
1–4
Cleared
5–9
Loaded with equivalent bits from the MSR
10–15
Cleared
16–31
Loaded with equivalent bits from the MSR
Note that depending on the implementation, reserved bits in the MSR may not be copied to SRR1.
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Table 6-7. Register Settings after an Alignment Exception (continued)
Register
Setting Description
0
—
0
0
FP
ME
SE
BE
0
—
0
0
IP
IR
DR
RI
—
0
0
0
LE
Set to value of ILE
MSR
POW
ILE
EE
PR
DSISR
0–14
15–16
Cleared
For instructions that use register indirect with index addressing—set to bits 29–30 of the
instruction encoding.
For instructions that use register indirect with immediate index addressing—cleared
17
For instructions that use register indirect with index addressing—set to bit 25 of the instruction
encoding.
For instructions that use register indirect with immediate index addressing— set to bit 5 of the
instruction encoding.
18–21
For instructions that use register indirect with index addressing—set to bits 21–24 of the
instruction encoding.
For instructions that use register indirect with immediate index addressing—set to bits 1–4 of the
instruction encoding.
22–26
Set to bits 6–10 (identifying either the source or destination) of the instruction encoding.
Undefined for dcbz.
27–31
Set to bits 11–15 of the instruction encoding (rA) for update-form instructions
Set to either bits 11–15 of the instruction encoding or to any register number not in the range of
registers loaded by a valid form instruction for lmw, lswi, and lswx instructions. Otherwise
undefined.
If there is no corresponding instruction, no alternative value can be specified.
DAR
Set to the EA of the data access as computed by the instruction causing the alignment exception.
The architecture does not support the use of a misaligned EA by load/store with reservation instructions.
If one of these instructions specifies a misaligned EA, the exception handler should not emulate the
instruction but should treat the occurrence as a programming error.
6.1.2.6.1
Integer Alignment Exceptions
Operations that are not naturally aligned may suffer performance degradation, depending on the processor
design, the type of operation, the boundaries crossed, and the mode that the processor is in during
execution. More specifically, these operations may either cause an alignment exception or they may cause
the processor to break the memory access into multiple, smaller accesses with respect to the cache and the
memory subsystem.
6.1.2.7
Program Exception (0x00700)
A program exception occurs when no higher priority exception exists and one or more of the following
exception conditions, which correspond to bit settings in SRR1, occur during execution of an instruction:
• An lswx instruction for which rA or rB is in the range of registers to be loaded (may cause results
that are boundedly undefined)
• Privileged instruction—A privileged instruction type program exception is generated when the
execution of a privileged instruction is attempted and the processor is operating in user mode
(MSR[PR] is set). It is also generated for mtspr or mfspr instructions that have an invalid SPR
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•
field that contain one of the defined values having spr[0] = 1 and if MSR[PR] = 1. Some
implementations may also generate a privileged instruction program exception if a specified SPR
field (for a move to/from SPR instruction) is not defined for a particular implementation, but spr[0]
= 1; in this case, the implementation may cause either a privileged instruction program exception,
or an illegal instruction program exception may occur instead.
Trap—A trap program exception is generated when any of the conditions specified in a trap
instruction is met. Trap instructions are described in Section 5.2.4.4, “Trap Instructions.”
The register settings when a program exception is taken are shown in Table 6-8.
Table 6-8. Register Settings After a Program Exception
Register
Setting Description
SRR0
Set to the EA of the instruction that causes the exception.
SRR1
0
Loaded with equivalent bits from the MSR
1–4
Cleared
5–9
Loaded with equivalent bits from the MSR
10
Cleared
Note that only one of bits 11–14 of SRR1 can be set at a time.
11
Cleared.
12
Set for an illegal instruction program exception; otherwise cleared.
13
Set for a privileged instruction program exception; otherwise cleared.
14
Set for a trap program exception; otherwise cleared.
15
Cleared if SRR0 contains the address of the instruction causing the exception, and set if SRR0
contains the address of a subsequent instruction.
16–31 Loaded with equivalent bits from the MSR
Note that depending on the implementation, reserved bits in the MSR may not be copied to SRR1.
MSR
POW
ILE
EE
PR
0
—
0
0
FP
ME
SE
BE
0
—
0
0
IP
IR
DR
RI
—
0
0
0
LE
Set to value of ILE
When a program exception is taken, instruction execution resumes at offset 0x00700 from the physical
base address indicated by MSR[IP].
6.1.2.8
Decrementer Exception (0x00900)
A decrementer exception occurs when no higher priority exception exists, a decrementer exception
condition occurs (for example, the decrementer register has completed decrementing), and MSR[EE] = 1.
The decrementer register counts down, causing an exception request when it passes through zero. A
decrementer exception request remains pending until the decrementer exception is taken and then it is
cancelled. The decrementer implementation meets the following requirements:
• The counters for the decrementer and the time-base counter are driven by the same fundamental
time base.
• Loading a GPR from the decrementer does not affect the decrementer.
• Storing a GPR value to DEC replaces the DEC contents with the value in the GPR.
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•
•
Whenever bit 0 of the decrementer changes from 0 to 1, a decrementer exception request is
signaled. If multiple decrementer exception requests are received before the first can be reported,
only one exception is reported.
If the decrementer is altered by software and if bit 0 is changed from 0 to 1, an exception request
is signaled.
The register settings for the decrementer exception are shown in Table 6-9.
Table 6-9. Register Settings after a Decrementer Exception
Register
Setting Description
SRR0
Set to the effective address of the instruction that the processor would have attempted to execute next if
no exception conditions were present.
SRR1
0
Loaded with equivalent bits from the MSR
1–4
Cleared
5–9
Loaded with equivalent bits from the MSR
10–15 Cleared
16–31 Loaded with equivalent bits from the MSR
Note that depending on the implementation, reserved bits in the MSR may not be copied to SRR1.
MSR
POW
ILE
EE
PR
0
—
0
0
FP
ME
SE
BE
0
—
0
0
IP
IR
DR
RI
—
0
0
0
LE
Set to value of ILE
When a decrementer exception is taken, instruction execution resumes at offset 0x00900 from the physical
base address indicated by MSR[IP].
6.1.2.9
System Call Exception (0x00C00)
A system call exception occurs when a System Call (sc) instruction is executed. The effective address of
the instruction following the sc instruction is placed into SRR0. MSR bits are saved in SRR1, as shown in
Table 6-10, and a system call exception is generated.
The system call exception causes the next instruction to be fetched from offset 0x00C00 from the physical
base address indicated by the new setting of MSR[IP]. As with most other exceptions, this exception is
context-synchronizing. Refer to Section 5.2.2.3.1, “Context Synchronization,” regarding actions
performed by a context-synchronizing operation.
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Table 6-10. Register Settings After a System Call Exception
Register
Setting Description
SRR0
Set to the effective address of the instruction following the System Call instruction
SRR1
0
Loaded with equivalent bits from the MSR
1–4
Cleared
5–9
Loaded with equivalent bits from the MSR
10–15 Cleared
16–31 Loaded with equivalent bits from the MSR
Note that depending on the implementation, reserved bits in the MSR may not be copied to SRR1.
MSR
POW
ILE
EE
PR
0
—
0
0
FP
ME
SE
BE
IP
IR
DR
RI
0
—
0
0
—
0
0
0
LE
Set to value of ILE
When a system call exception is taken, instruction execution resumes at offset 0x00C00 from the physical
base address indicated by MSR[IP].
6.1.2.10
Trace Exception (0x00D00)
A trace exception occurs if MSR[SE] = 1 and any instruction except rfi is successfully completed or if
MSR[BE] = 1 and a branch is completed. Notice that the trace exception does not occur after an instruction
that causes an exception. The monitor/debugger software must change the vectors of other possible
exception addresses to single-step these instructions. If this is unacceptable, other debug features can be
used. See Chapter 53, “System Development and Debugging,” for more information. Table 6-11 shows
register settings for trace exceptions.
Table 6-11. Register Settings After a Trace Exception
Register
Setting
SRR0
Set to the EA of the instruction following the executed instruction.
SRR1
1–4
10–15
Others
0
0
Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR
IP
ME
LE
Other
No change
No change
Copied from the ILE setting of the interrupted process
0
Execution resumes at offset 0x00D00 from the base address indicated by MSR[IP].
6.1.2.11
Floating-Point Assist Exception
The floating-point assist exception is not generated by the MPC885. Attempting to execute a floating-point
causes an instruction implementation-specific software emulation exception.
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6.1.3
Implementation-Specific Exceptions
The following sections describe the MPC885’s implementation-specific exceptions.
6.1.3.1
Software Emulation Exception (0x01000)
A software emulation exception occurs as a result of one of the following conditions:
• When executing any unimplemented instruction, including all illegal and unimplemented optional
and floating-point instructions.
• When executing a mtspr or mfspr that specifies an on-core unimplemented register, regardless of
SPR[0].
• When executing a mtspr or mfspr that specifies an off-core unimplemented register and SPR[0]
= 0 or MSR[PR] = 0 (no program exception condition).
In addition, Table 6-12 shows the following set of registers:
Table 6-12. Register Settings after a Software Emulation Exception
Register
Setting
SRR0
Set to the EA of the instruction that caused the exception.
SRR1
1–4
0
10–15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR
IP
ME
LE
Other
No change
No change
Copied from the ILE setting of the interrupted process
0
Execution resumes at offset 0x01000 from the base address indicated by MSR[IP].
6.1.3.2
Instruction TLB Miss Exception (0x01100)
This type of exception occurs if MSR[IR] = 1 and an attempt is made to fetch an instruction from a page
whose effective page number cannot be translated by TLB. As shown in Table 6-13, the following registers
are set:
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Table 6-13. Register Settings After an Instruction TLB Miss Exception
Register
Setting
SRR0
Set to the EA of the instruction that caused the exception.
SRR1
0–3
4
10
11–15
Others
0
1
1
0
Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR
IP
ME
LE
Other
No change
No change
Copied from the ILE setting of the interrupted process
0
Some instruction TLB registers are set to the values described in Chapter 8, “Memory Management Unit.”
Execution resumes at offset 0x01100 from the base address indicated by MSR[IP].
6.1.3.3
Data TLB Miss Exception (0x01200)
This type of exception occurs when MSR[DR] = 1 and an attempt is made to access a page whose effective
page number cannot be translated by TLB. Table 6-14 shows the following set registers:
Table 6-14. Register Settings After a Data TLB Miss Exception
Register
Setting
SRR0
Set to the EA of the instruction that caused the exception.
SRR1
1–4
0
10–15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR
IP
ME
LE
Other
No change
No change
Copied from the ILE setting of the interrupted process
0
Some instruction TLB registers are set to the values described in Chapter 8, “Memory Management Unit.”
Execution resumes at offset 0x01200 from the base address indicated by MSR[IP].
6.1.3.4
Instruction TLB Error Exception (0x01300)
This type of exception occurs as a result of one of the following conditions if MSR[IR] = 1:
• The EA cannot be translated. Either the segment or page valid bit of this page is cleared in the
translation table. Note that although the MPC885 does not implement segment registers as they are
defined by the OEA, the concept of segment is retained as the memory space accessible to the
level-one table descriptors.
• The fetch access violates memory protection.
• The fetch access is to guarded memory.
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Table 6-15 shows how these registers are set:
Table 6-15. Register Settings after an Instruction TLB Error Exception
Register
Setting
SRR0
Set to the EA of the instruction that caused the exception.
SRR1
Note that only one of bits 1, 3, and 4 will be set.
1
1 if the translation of an attempted access is not in the translation tables. Otherwise 0
2
0
3
1 if the fetch access was to guarded memory when MSR[IR] = 1. Otherwise 0
4
1 if the access is not permitted by the protection mechanism; otherwise 0.
11–15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR
IP
ME
LE
Other
No change
No change
Copied from the ILE setting of the interrupted process
0
Some instruction TLB registers are set to a value described in Chapter 8, “Memory Management Unit.”
Execution resumes at offset 0x01300 from the base address indicated by MSR[IP].
6.1.3.5
Data TLB Error Exception (0x014000)
This type of exception occurs as a result of one of the following conditions:
• No EA of a load, store, icbi, dcbz, dcbst, dcbf or dcbi instruction can be translated (either the
segment or page valid bit of this page is cleared in the translation table).
• The access violates memory protection.
• An attempt was made to write to a page with a cleared change bit.
The following registers are set, as shown in Table 6-16.
Table 6-16. Register Settings After a Data TLB Error Exception
Register
Setting
SRR0
Set to the EA of the instruction that caused the exception.
SRR1
1–4
0
10–15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR
IP
ME
LE
Other
No change
No change
Copied from the ILE setting of the interrupted process
0
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Table 6-16. Register Settings After a Data TLB Error Exception (continued)
Register
DSISR
Setting
0
1
2–3
4
5
6
7–31
DAR
0
Set if the translation of an attempted access is not found in the translation tables. Otherwise,
cleared
0
Set if the memory access is not permitted by the protection mechanism; otherwise cleared
0
1 for a store operation; 0 for a load operation.
0
Set to the EA of the data access that caused the exception.
Some instruction TLB registers are set to the values described in Chapter 8, “Memory Management Unit.”
Execution resumes at offset 0x01400 from the base address indicated by MSR[IP].
6.1.3.6
Debug Exceptions (0x01C00–0x01F00)
A debug exception occurs in response to one of the following conditions:
• When there is an internal breakpoint match (for more details, see Section 53.2, “Watchpoints and
Breakpoints Support.”)
• When a peripheral breakpoint request is presented to the exception mechanism
• When the development port request is presented to the exception mechanism
Table 6-17 shows the following register settings:
Table 6-17. Register Settings after a Debug Exception
Register
Setting
SRR0
For I-breakpoints, set to the EA of the instruction that caused the exception. For L-breakpoint, set to the
EA of the instruction after the one that caused the exception. For development port maskable request or
a peripheral breakpoint, set to the EA of the instruction that the processor would have executed next if
no exception conditions were present. If the development port request is asserted at reset, the value of
SRR0 is undefined.
SRR1
1–4
0
10–15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
If the development port request is asserted at reset, the value of SRR1 is undefined.
MSR
IP
ME
LE
Other
BAR
For L-bus breakpoint conditions. Set to the EA of the data access as computed by the instruction that
caused the exception.
DSISR
For L-bus breakpoint conditions. Do not change.
DAR
For L-bus breakpoint conditions. Do not change.
No change
No change
Copied from the ILE setting of the interrupted process
0
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Execution resumes from the following offsets from the base indicated by the MSR[IP]:
• 0x01D00—For an instruction breakpoint match
• 0x01C00—For a data breakpoint match
• 0x01E00—For a development port maskable request or a peripheral breakpoint
• 0x01F00—For a development port nonmaskable request
6.1.4
Implementing the Precise Exception Model
Because instructions execute in parallel, they may execute out of order. To ensure that out-of-order
execution does not affect data integrity, hardware ensures a precise exception model. As instructions are
dispatched in-order to the execution units, they are assigned sequential positions in the six-entry
completion queue, a FIFO buffer maintains program order. The completion queue is shown in Figure 3-2.
When an exception condition is encountered, previous instructions in the completion queue are allowed to
complete and be retired from the completion queue. If one of these instructions generates another
exception, that exception is handled first. Subsequent instructions (and any results associated with them)
are flushed from the processor before instruction processing resumes at the appropriate exception vector.
Before control passes to the exception handler, machine state is saved in SRR0 and SRR1.
After an exception handler executes, the machine state of the interrupted process is restored, typically by
executing the rfi instruction, which writes bits from SRR1 to the MSR, SRR0 contains the instruction
address at which fetching should resume. To correctly restore the architectural state, the CQ must record
the value of the destination before the instruction is executed. The destination of a store instruction,
however, is in memory and it is not practical from a performance standpoint to always read memory before
writing it. Therefore, stores issue immediately to store buffers but do not update memory until all previous
instructions have finished executing without exception or until the store instruction reaches CQ0.
The completion queue can hold six instructions, but no more than four integer instructions. The other two
instructions can be condition code or branch instructions. Long latency instructions may cause the
completion queue to fill, stalling dispatch until the long latency instruction vacates the completion queue.
The following instructions may cause the completion queue to fill:
• Integer divide instructions
• Instructions that affect or use resources external to the core (load/store instructions, and especially
load/store string multiple/instructions)
6.1.5
Recoverability After an Exception
The processor cannot always recover from system reset and machine check interrupts, either because the
conditions that cause the interrupt are catastrophic or because they caused the save/restore information in
SRR0 and SRR1 to be overwritten.
All other exceptions should be restartable. Registers such as SRR0 and SRR1 (and for some exceptions
the data address register (DAR) and DSI status register (DSISR)) that may be affected by subsequent
exceptions should be saved early in the routine to avoid being overwritten. Likewise, the saved values
should be restored to those registers at the end of the handler routine in such a way that protects them from
an exception before the instruction returns control to the interrupted process. Interrupts should also be
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masked in these areas by clearing (disabling) MSR[ME] for system reset and machine check interrupts and
MSR[EE] for external interrupt, decrementer and two implementation-specific exceptions—debug port
unmaskable interrupt and breakpoint interrupt in nonmaskable mode.
The recoverable exception bit (MSR[RI]) is defined to notify the exception handler code whether it is in a
restartable state. The MSR[RI] shadow bit in SRR1 indicates if the exception is restartable. This bit does
not need to be checked on exception types that are restartable by convention, except those previously
mentioned. When an exception occurs, MSR[RI] is copied to the equivalent bit in SRR1 and cleared. When
an rfi instruction is executed, MSR[RI] is copied from SRR1 or software can change the bit by using it the
mtmsr instruction. The MSR[RI] bit is intended to be set by the exception handler after saving the
machine state, in SRR0 and SRR1 (and DAR and DSISR if needed) and cleared by the exception handler
before retrieving the machine state.
In critical code sections where MSR[EE] is cleared but SRR0 and SRR1 are not busy, MSR[RI] should
remain set. In such cases, if an exception occurs, the process is restartable.
Table 6-18 lists SPRs that facilitate manipulation of MSR[RI] and MSR[EE]. Writing to these locations
performs the specified operation. Attempting to read these locations is treated as an unimplemented
instruction and causes a software emulation exception.
Table 6-18. Additional SPRs that Affect MSR Bits
Name
SPR
MSR[EE]
MSR[RI]
Used For
EIE
80
1
1
External interrupt enable:
End of handler’s prologue, enable nested external interrupts;
End of critical code segment in which external interrupts were disabled
EID
81
0
1
External interrupt disable, but other exception are recoverable:
End of handler’s prologue, keep external nested interrupts disabled;
Start of critical code segment in which external interrupts are disabled
NRI
82
0
0
Nonrecoverable interrupt:
Start of handler’s epilogue
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6.1.6
Exception Latency
Figure 6-1 describes significant events during exception processing.
0
1
3
2
A
4
5
B
6
7
8
9
10
11
12
C
13
14
D
E
15
16
17
18
•••
1
2
3
4
5
6
7
Stage
IH1
Fetch (in IQ)
IH2
In dispatch entry (IQ0)
IH3
Execute
IH4
Complete (In CQ)
IH5
In retirement entry (CQ0)
IH6
Instruction Queue
6
7
5
6
4
5
3
4
Completion Queue
2
1
3
2
IH2
IH1
IH4
IH3
IH2
IH1
IH4
IH3
IH2
IH1
IH4
IH3
IH2
IH1
IH4
IH3
IH2
IH1
IH4
IH3
IH2
IH1
3
IH5
IH4
IH3
IH2
IH6
IH5
IH4
IH3
IH7
IH6
IH5
IH4
IH8
IH7
IH6
IH5
IH1
IH2
IH1
IH3
IH2
IH4
IH3
Figure 6-1. Exception Latency
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Exceptions
Table 6-19. Exception Latency
Time Point
Fetch
Issue
A
Instruction Complete
Kill Pipeline
Faulting instruction issue
B
Instruction complete and all
previous instructions complete
C
Start fetch handler
Kill pipeline
D (at least 3
clocks after B)
E
First instruction of handler
dispatched
Note: The following are time point explanations.
A—At time point A the excepting instruction dispatches and begins executing. Previously dispatched instructions are
proceeding through the pipeline.
B—The excepting instruction has executed and reached CQ0; previous instructions have finished execution without generating
exceptions. The exception is recognized and between B and D (between 3 and 10 cycles) the effects of any instructions after
the one that generated the interrupt are cancelled and the instructions are flushed. If the instruction had not generated an
exception, it would have been retired.
C—The core fetches the first instructions of the exception handler if the exception handler is external. It is 5 cycles if it is in the
instruction cache and no-show mode is on.
D—All state has been restored. During the interval between D and E, the machine is saving context information in the SRR0
and SRR1 registers, disabling exceptions, placing the machine in privileged mode, and fetching instructions of the exception
handler. The interval between D and E requires at least one clock. The time between C and E depends on the memory system
and the time it takes to fetch the first instruction of the exception handler. For full completion queue restore time, it is no less
than two clocks.
E—The MSR and instruction pointer of the executing process have been saved and control has been transferred to the
exception handler routine. Exception handler instructions that have been fetched can be dispatched.
6.1.7
Partially Completed Instructions
Partially completed instructions can be reexecuted after the exception is handled. This precise exception
model can simplify exception processing because software does not have to save the machine’s internal
states, unwind the pipelines, or cleanly terminate the faulting instruction stream and reverse the process to
resume execution of the faulting stream.
Table 6-20. Before and After Exceptions
Exception Type
Instruction Type
Before/After
Contents of SRR0
Hard reset (caused by HRESET or SRESET)
Any
NA
Undefined
System reset
Any
Before
Next instruction to execute
Machine check
Any
Before
Faulting instruction
TLB miss/error1
Any
Before
Faulting fetch or load/store
Other noninstruction-related exceptions
Any
Before
Next instruction to execute
Alignment
Load/store
Before
Faulting instruction
Privileged instruction
Any privileged
instruction
Before
Faulting instruction
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Exceptions
Table 6-20. Before and After Exceptions (continued)
Exception Type
Instruction Type
Before/After
Contents of SRR0
Trap
tw, twi
Before
Faulting instruction
System call
sc
After
Next instruction to execute
Trace
Any
After
Next instruction to execute
Debug I- breakpoint 1
Any
Before
Faulting instruction
Debug L- breakpoint 1
Load/store
After
Faulting instruction + 4
Software emulation 1
NA
Before
Faulting instruction
Floating-point unavailable
Floating-point
Before
Faulting instruction
1
Implementation-specific exceptions not defined by the PowerPC architecture.
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Chapter 7
Instruction and Data Caches
This chapter describes cache implementation for the derivatives of the MPC885 family. Table 7-1 is
provided as a quick reference of the fundamental cache differences among these derivatives. The
appropriate appendix for each derivative should also be consulted.
Table 7-1. MPC885 Family
Cache
Part
Documentation
Instruction Cache
Data Cache
MPC885
8 Kbyte
8 Kbyte
This manual
MPC880
8 Kbyte
8 Kbyte
Appendix E
MPC875
8 Kbyte
8 Kbyte
Appendix F
MPC870
8 Kbyte
8 Kbyte
Appendix G
The MPC885 contains separate instruction and data caches to allow rapid core access to instructions and
data. This chapter describes the organization of the on-chip instruction and data caches, cache control,
various cache operations, and the interaction between the caches, the load/store unit (LSU), the instruction
sequencer, and the system interface unit (SIU).
The MPC885 cache implementation has the following characteristics:
• There are separate 8-Kbyte instruction and 8-Kbyte data caches (Harvard architecture).
• The MPC885 instruction cache is two-way set associative, and the data cache is two-way set
associative. The caches implement a least-recently-used (LRU) replacement algorithm within each
set.
• The cache directories are physically addressed. The physical (real) address tag is stored in the
cache directory.
• Both the instruction and data caches have 16-byte cache blocks. A cache block is the block of
memory that a coherency state describes, also called a cache line.
• Two state bits for each data cache block allow encoding for three states:
— Modified-valid (sometimes called ‘modified’)
— Unmodified-valid (sometimes called ‘exclusive’)
— Invalid
• A single state bit for each instruction cache block allows encoding for two possible states:
— Valid
— Invalid
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Instruction and Data Caches
•
•
Both caches can be disabled, invalidated, or locked by issuing commands to their respective cache
control registers, special-purpose registers (SPRs) specific to the MPC885. See Section 7.3,
“Cache Control Registers,” for more information.
Individual cache blocks can be locked so that frequently accessed instructions or data are
guaranteed to be resident in the respective cache.
On a cache miss, the MPC885 cache blocks are filled in 16-byte bursts. The burst fill is performed as a
critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the
requesting unit, thus minimizing stalls due to cache fill latency. Both caches provide storage for cache tags
and perform cache block replacement (LRU) function.
Both caches are tightly coupled to the MPC885 system interface unit (SIU) to allow efficient access to the
system memory controller and other bus masters. The SIU receives requests for bus operations from the
instruction and data caches and executes the operations according to the external bus protocol.
The data cache provides buffers for load and store bus operations. The data cache supplies data to the GPRs
by means of a 32-bit interface to the load/store unit. The LSU is directly coupled to the data cache to allow
efficient movement of data to and from the general-purpose registers. The load/store unit provides all logic
required to calculate effective addresses, handles data alignment to and from the data cache, and provides
sequencing for load and store string and multiple operations. Write operations to the data cache can be
performed on a byte, half-word, or word basis.
The instruction cache provides a 32-bit interface to the instruction sequencer. The instruction sequencer
uses the instruction cache as much as possible in order to sustain the high throughput provided by the
four-entry instruction queue.
7.1
Instruction Cache Organization
The MPC885 instruction cache is organized as 256 sets of two blocks, as shown in Figure 7-1. Each block
consists of 16 bytes, a single state bit, a lock bit, and an address tag.
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Instruction and Data Caches
0
19
20
27 28 29 30 31
8 Bits
Data Effective Address
2
20
2
8
Word Select
Way0
Way1
Set254 Tag254
Set255 Tag255
Tag0
Tag1
w0 w1 w2 w3 . .
w0 w1 w2 w3 . .
..
..
Tag254
Tag255
20
...
...
...
w0 w1 w2 w3
w0 w1 w2 w3
Valid Bit
Lock Bit
...
L
R
U
..
..
A
r
r
a
y
...
Valid Bit
Lock Bit
...
Tag0
Tag1
...
w0 w1 w2 w3 . .
w0 w1 w2 w3 ..
...
Set0
Set1
Reserved
w0 w1 w2 w3
w0 w1 w2 w3
20
MMU
128
128
COMP
COMP
Hit1
Hit0
Bidirectional Multiplexer 2 -> 1
128
HIT
To/From Block Buffer
Figure 7-1. MPC885 Instruction Cache Organization
Each instruction cache block contains four contiguous words from memory that are loaded from a
four-word boundary; that is, bits A[30–31] of the logical (effective) addresses are zero. As a result, cache
blocks are aligned with page boundaries. Also, address bits A[20–27] provide the index to select a set, and
bits A[28–29] select a word within a block. The tags consist of the high-order physical address bits
PA[0–19]. Address translation occurs in parallel with set selection (from A[20–27]).
The instruction cache implements a single state bit for each cache block that indicates whether the cache
block is valid or invalid. The MPC885 does not support snooping of the instruction cache. All memory is
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Instruction and Data Caches
considered to have memory-coherency-not-required attributes. Therefore, software must maintain
instruction cache coherency. The MPC885 supports a fast instruction cache invalidate capability as
described in Section 7.3.1.2.5, “Instruction Cache Invalidate All Command.”
The instruction cache also implements a lock bit for each cache block that allows instructions to be loaded
into the instruction cache and locked, providing fast and deterministic execution time for critical code
segments. The MPC885 supports commands for locking and unlocking individual cache blocks and for
unlocking all the cache blocks at once.
7.2
Data Cache Organization
The MPC885 data cache is organized as 256 sets of two blocks as shown in Figure 7-2. Each block consists
of four words, two state bits, a lock bit, and an address tag.
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Instruction and Data Caches
0
19
20
27 28 29 30 31
Data Effective Address
8 Bits
2
20
Reserved
2
8
Word Select
Way0
Set254 Tag254
Set255 Tag255
Tag0
Tag1
w0 w1 w2 w3 . .
w0 w1 w2 w3 . .
..
..
Tag254
Tag255
20
...
...
...
w0 w1 w2 w3
w0 w1 w2 w3
Dirty Bit
Valid Bit
Lock Bit
...
L
R
U
..
..
A
r
r
a
y
...
...
Dirty Bit
Valid Bit
Lock Bit
...
Tag0
Tag1
...
Set0
Set1
Way1
w0 w1 w2 w3 . .
w0 w1 w2 w3 . .
w0 w1 w2 w3
w0 w1 w2 w3
20
MMU
128
COMP
COMP
128
Hit1
Hit0
Bidirectional Multiplexer 2 -> 1
128
HIT
To/From Block Buffer
Figure 7-2. MPC885 Data Cache Organization
Each cache block contains four contiguous words from memory that are loaded from a four-word
boundary, that is, bits A[30–31] of the logical (effective) addresses are zero. As a result, cache blocks are
aligned with page boundaries. Note that address bits A[20–27] provide the index to select a cache set for
the MPC885. Bits A[28–29] select a word within a block. The tags consist of the high-order physical
address bits PA[0–19]. Address translation occurs in parallel with set selection (from A[20–27]).
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Instruction and Data Caches
The two state bits implement a three-state (modified-valid/unmodified-valid/invalid) protocol. The
MPC885 does not provide support for snooping external bus activity. All coherency between the internal
caches and external agents (memory or I/O devices) must be controlled by software.
The data cache also implements a lock bit for each cache block that allows data to be loaded into the data
cache and locked. The MPC885 supports commands for locking and unlocking individual cache blocks
and for unlocking all the cache blocks at once.
7.3
Cache Control Registers
The MPC885 caches are controlled by programming commands using the cache control registers and by
issuing dedicated cache control instructions. This section describes control of the instruction and data
caches by the cache control registers. Section 7.4, “Cache Control Instructions,” describes the cache
control instructions.
7.3.1
Instruction Cache Control Registers
The MPC885 implements three special purpose registers (SPRs) to control the instruction cache: the
instruction cache control and status register (IC_CST), the instruction cache address register (IC_ADR),
and the instruction cache data port register (IC_DAT). The instruction cache can be disabled, invalidated,
or locked by issuing the appropriate commands to the instruction cache control registers (IC_CST,
IC_ADR, and IC_DAT). In addition, the instruction cache control registers can be used to read the contents
and tags of specific instruction cache blocks.
The mtspr and mfspr instructions access the cache control registers, but they can be accessed only by
supervisor-level programs (that is, when MSR[PR] = 0). Any attempt to access these SPRs with a
user-level program (MSR[PR] = 1) results in a supervisor-level program exception.
The IC_CST register, shown in Figure 7-3, has an SPR encoding of 560.
0
Field IEN
1
3
4
6
7
9
—
CMD
—
10
11
12
15
CCER1 CCER2
—
Reset
0
—
—
—
0
0
—
R/W
R
—
R/W
—
R
R
—
16
31
Field
—
Reset
—
R/W
—
SPR
560
Figure 7-3. Instruction Cache Control and Status Register (IC_CST)
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Instruction and Data Caches
Table 7-2 describes the bits of the IC_CST register.
Table 7-2. Instruction Cache Control and Status Register—IC_CST
Bits
Name
Description
0
IEN
1–3
—
4–6
CMD
7–9
—
10
CCER1
Instruction cache error type 1—bus error during an IC_CST load & load cache block command
0 No error detected
1 Error detected
Note that this is a read-only, sticky bit, set only by the MPC885 when an error is detected.
Reading this bit clears it.
11
CCER2
Instruction cache error type 2—no unlocked way available for an IC_CST load-and-lock
cache block command
0 No error detected
1 Error detected
Note that this is a read-only, sticky bit, set only by the MPC885 when an error is detected.
Reading this bit clears it.
12–31
—
Instruction cache enable status
0 The instruction cache is disabled.
1 The instruction cache is enabled.
Note that this is a read-only bit. Any attempt to write to it is ignored.
Reserved
Instruction cache command
000 Reserved
001 Cache enable
010 Cache disable
011 Load-and-lock cache block
100 Unlock cache block
101 Unlock all
110 Invalidate all
111 Reserved
Note that reading these bits always returns 0b000.
Reserved
Reserved
The IC_ADR register, shown in Figure 7-4, has an SPR encoding of 561.
0
31
Field
ADR
Reset
—
R/W
R/W
SPR
561
Figure 7-4. Instruction Cache Address Register (IC_ADR)
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Instruction and Data Caches
Table 7-3 describes the bits of the IC_ADR register.
Table 7-3. Instruction Cache Address Register—IC_ADR
Bits
Name
0–31
ADR
Description
Instruction cache command address. When programming the IC_CST[CMD] load-and-lock cache
block and unlock cache block commands, IC_ADR contains the physical address in external
memory of the desired cache block element. When reading the data, tags, and status contained
within the instruction cache, IC_ADR is used to qualify what is to be read according to Table 7-7.
See Section 7.3.1.1, “Reading Data and Tags in the Instruction Cache,” for more information.
The IC_DAT register, shown in Figure 7-5, has an SPR encoding of 562.
0
31
Field
DAT
Reset
—
R/W
R/W
SPR
562
Figure 7-5. Instruction Cache Data Port Register (IC_DAT)
Table 7-4 describes the bits of the IC_DAT register.
Table 7-4. Instruction Cache Data Port Register—IC_DAT
Bits
Name
0–31
DAT
7.3.1.1
Description
Instruction cache command data. The data received when reading information from the
instruction cache. See Section 7.3.1.1, “Reading Data and Tags in the Instruction Cache,” for
more information.
Reading Data and Tags in the Instruction Cache
The MPC885 supports reading the data, tags, and the state and lock bits stored in the instruction cache.
The instruction cache read command, issued by reading the IC_DAT register, uses the IC_ADR register to
qualify what is to be read. Table 7-5 describes the fields of the IC_ADR register during an instruction
cache read command.
Table 7-5. IC_ADR Fields for Cache Read Commands
0–16
Reserved
17
0 Tag
1 Data
18
Reserved
19
0 = Way 0
1 = Way 1
20–27
28–29
30–31
Set select
(0–255)
Word select
(used only for
data array)
Reserved
To read the data or tags stored in the instruction cache, do the following:
1. Write the address of the data or tag to be read to the IC_ADR according to the format in Table 7-5.
Note that it is also possible to read this register for debugging purposes.
2. Read the IC_DAT register.
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Instruction and Data Caches
For data array (IC_ADR[17] = 1) read commands, the word selected by IC_ADR[28–29] is placed in the
target general-purpose register. For tag array (IC_ADR[17] = 0) read commands, the tag and state
information is placed in the target general-purpose register. Table 7-6 provides the format of the IC_DAT
register for a tag read.
Table 7-6. IC_DAT Format for a Tag Read (IC_ADR[17] = 0)
0–19
20–21
Tag value
Reserved
7.3.1.2
22
0 = Invalid
1 = Valid
23
0 = Unlocked
1 = Locked
24
LRU code:
1 = way1 is more recent than way0.
0 = way0 is more recent than way1.
25-31
Reserved
IC_CST Commands
All IC_CST commands, except the load-and-lock cache block command, are executed immediately after
writing to the IC_CST register and do not generate any errors. Therefore, when executing these commands
there is no need to check the error type bits in the IC_CST register. All commands should be followed by
an isync instruction, if the instruction cache command is required to affect all instruction fetches that come
after it in the program order. In addition, correct operation of the instruction cache relies on software
following the procedures described in Section 7.5.5, “Updating Code and Memory Region Attributes.”
Note that when the instruction cache is executing a command, it stops handling CPU requests, which can
result in machine stalls.
7.3.1.2.1
Instruction Cache Enable/Disable Commands
The instruction cache enable command (IC_CST[CMD] = 0b001) is used to enable the instruction cache;
the instruction cache disable command (IC_CST[CMD] = 0b010) is used to disable the instruction cache.
Neither of these commands has any error cases. The current state of the instruction cache is available by
reading the instruction cache enable status bit (IC_CST[IEN]).
When disabled, the MPC885 ignores the instruction cache valid bit and operates as if all accesses have
caching-inhibited access attributes (that is, all instruction fetches are propagated to the bus as single-beat
transactions). Disabling the instruction cache does not affect the instruction address translation logic;
MSR[IR] controls instruction address translation.
At hard reset, the instruction cache is disabled.
7.3.1.2.2
Instruction Cache Load-and-Lock Cache Block Command
The instruction cache load and lock cache block command (IC_CST[CMD] = 0b011) is used to lock
critical code segments in the instruction cache. Locked cache blocks are not replaced during misses and
are not affected by invalidate commands. Correct operation of locked instruction cache blocks relies on
software following the procedures described in Section 7.5.5, “Updating Code and Memory Region
Attributes.”
To load and lock one or more cache blocks:
1. Read the IC_CST error type bits to clear them.
2. Write the address of the cache block to be locked to the IC_ADR register.
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Instruction and Data Caches
3.
4.
5.
6.
Write the load-and-lock cache block command (IC_CST[CMD] = 0b011) to the IC_CST register.
Execute an isync instruction.
Repeat steps 2 through 4 to load and lock another cache block.
Read the IC_CST error type bits to determine if the sequence completed without errors.
After the load-and-lock cache block command is written to the IC_CST register, the cache checks if the
block containing the byte addressed by IC_ADR[ADR] is in the cache (hit). If it is in the cache, the block
is locked. If the block is not in the cache, a normal miss sequence is initiated (see Section 7.5.2,
“Instruction Cache Miss,” for more information). After the addressed block is placed into the cache, the
block is locked.
The user must check the IC_CST error type bits to determine if the load-and-lock cache block operation
completed without error. The load-and-lock cache block command generates two possible errors:
• Type 1—A bus error occurred in one of the fetch cycles
• Type 2—There is no available way to lock (It is the responsibility of the user to make sure that there
is at least one unlocked way in the appropriate set.)
The error type bits in the IC_CST register are sticky, thus allowing the user to perform a series of
load-and-lock cache block commands before checking the termination status. These bits are set by the
MPC885 and are cleared by software.
Note that the MPC885 considers all zero-wait-state devices on the internal bus as caching-inhibited. For
this reason, software should not perform load-and-lock cache block operations from these devices on the
internal bus.
7.3.1.2.3
Instruction Cache Unlock Cache Block Command
The unlock cache block command (IC_CST[CMD] = 0b100) is used to unlock previously locked cache
blocks. To unlock a cache block:
1. Write the address of the cache block to be unlocked to the IC_ADR register.
2. Write the unlock cache block command (IC_CST[CMD] = 0b100) to the IC_CST register.
If the block is found in the cache (hit), it is unlocked and thereafter operates as a regular valid cache block.
If the block is not found in the cache (miss), no operation is performed. There are no error cases for the
unlock block command.
The instruction cache performs the unlock cache block command in one clock cycle.
7.3.1.2.4
Instruction Cache Unlock All Command
The unlock all command (IC_CST[CMD] = 0b101) is used to unlock the entire instruction cache with a
single command.
When the unlock all command is performed, if a cache block is locked, it is unlocked and thereafter
operates as a regular valid cache block. If a block is not locked or if it is marked invalid, no operation is
performed. There are no error cases for the unlock all command
The instruction cache performs the unlock all command in one clock cycle.
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Instruction and Data Caches
7.3.1.2.5
Instruction Cache Invalidate All Command
The instruction cache invalidate all command (IC_CST[CMD] = 0b110) causes all unlocked, valid blocks
in the instruction cache to be marked invalid. As a result of the invalidate all command, the LRU bits of
all cache blocks point to either the unlocked way or to way 0 if both ways are unlocked. There are no error
cases for the invalidate all command.
The instruction cache performs the invalidate all command in one clock cycle.
7.3.2
Data Cache Control Registers
The MPC885 implements three special purpose registers (SPRs) to control the data cache: the data cache
control and status register (DC_CST), the data cache address register (DC_ADR), and the data cache data
port register (DC_DAT). The data cache can be disabled, invalidated, locked, or flushed by issuing the
appropriate commands to the data cache control registers (DC_CST, DC_ADR, and DC_DAT). Also, the
data cache control registers can be used to read the contents and tags of specific data cache blocks.
DC_CST[DFWT] can be used to force the data cache into write-through mode. DC_CST[LES] controls
true little-endian byte-ordering of the MPC885. See Appendix A, “Byte Ordering,” for more information.
The mtspr and mfspr instructions access the cache control registers, but they can be accessed only by
supervisor-level programs (that is, when MSR[PR] = 0). Any attempt to access these SPRs with a
user-level program (MSR[PR] = 1) results in a supervisor-level program exception.
The DC_CST register, shown in Figure 7-6, has an SPR encoding of 568.
0
1
2
Field DEN DFWT LES
3
4
7
8
9
—
CMD
—
10
11
12
CCER1 CCER2
15
—
Reset
0
0
0
—
—
—
0
0
—
R/W
R
R
R
—
R/W
—
R
R
—
16
31
Field
—
Reset
—
R/W
—
SPR
568
Figure 7-6. Data Cache Control and Status Register (DC_CST)
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Instruction and Data Caches
Table 7-7 describes the bits of the DC_CST register.
Table 7-7. Data Cache Control and Status Register—DC_CST
Bits
Name
Description
0
DEN
Data cache enable status
0 The data cache is disabled.
1 The data cache is enabled.
Note: This is a read-only bit. Any attempt to write to it is ignored. This bit is programmed by issuing
the appropriate command in DC_CST[CMD].
1
DFWT
Data cache forced write-through
0 The write-through behavior of the data cache is determined by the write-through memory/cache
access attribute (the W bit) in the MMU.
1 Writes to the data cache are forced to write through to memory.
Note: This is a read-only bit. Any attempt to write to it is ignored. This bit is programmed by issuing
the appropriate command in DC_CST[CMD].
2
LES
Little-endian swap
0 Used for big-endian (BE) and modified little-endian (MOD-LE) modes. No modifications to the
address or byte lanes are performed.
1 Used for true little-endian (TLE) mode. A 2-bit munge is performed on the physical address before
accessing the internal U-bus. Also, for accesses originating from the MPC8xx core, the SIU
unmunges the address and swaps the bytes of data within each word at the external bus/internal
U-bus boundary.
See Appendix A, “Byte Ordering,” for more information about MPC885 byte ordering. Note that this
is a read-only bit. Any attempt to write to it is ignored. This bit is programmed by issuing the
appropriate command in DC_CST[CMD].
3
4–7
8–9
10
Reserved
CMD
Data cache command
0000 Reserved
0001 Set forced write-through bit
0010 Cache enable
0011 Clear forced write-through bit
0100 Cache disable
0101 Set true little-endian swap bit
0110 load-and-lock cache block
0111 Clear little-endian swap bit
1000 Unlock cache block
1001 Reserved
1010 Unlock all
1011 Reserved
1100 Invalidate all
1101 Reserved
1110 Flush cache block
1111 Reserved
Note: Reading these bits always returns 0b0000
Reserved
CCER1 Data cache error type 1. Copyback error during dcbf or dcbst instruction execution or during
DC_CST flush cache block command. A machine check exception is generated when this bit is set.
0 No error detected
1 Error detected
Note that this is a read-only, sticky bit, set only by the MPC885 when an error is detected. Reading
this bit clears it.
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Table 7-7. Data Cache Control and Status Register—DC_CST (continued)
Bits
11
Name
Description
CCER2 Data cache error type 2. This bit indicates one of two possible errors—either a bus error during
DC_CST load & load cache block or flush cache block command or there is no unlocked way
available for a DC_CST load-and-lock cache block or flush cache block command.
0 No error detected
1 Error detected
Note that this is a read-only, sticky bit, set only by the MPC885 when an error is detected. Reading
this bit clears it.
12–31
—
Reserved
The DC_ADR register, shown in Figure 7-7, has an SPR encoding of 569.
0
31
Field
ADR
Reset
—
R/W
R/W
SPR
569
Figure 7-7. Data Cache Address Register (DC_ADR)
Table 7-8 describes the bits of the DC_ADR register.
Table 7-8. Data Cache Address Register—DC_ADR
Bits
Name
Description
0–31
ADR
Data cache command address. When programming the DC_CST load-and-lock cache block,
unlock cache block, and flush cache block commands, DC_ADR contains the physical address
of the desired cache block element in external memory. When reading the data, tags, and status
contained within the data cache, DC_ADR is used to qualify what is to be read according to
Table 7-8. See Section 7.3.2.1, “Reading Data Cache Tags and Copyback Buffer,” for more
information.
The DC_DAT register, shown in Figure 7-8, has an SPR encoding of 570.
0
31
Field
DAT
Reset
—
R/W
R/W
SPR
570
Figure 7-8. Data Cache Data Port Register (DC_DAT)
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Table 7-9 describes the bits of the DC_DAT register.
Table 7-9. Data Cache Data Port Register—DC_DAT
Bits
Name
0–31
DAT
7.3.2.1
Description
Data cache command data. The data received when reading information from the data cache.
See Section 7.3.2.1, “Reading Data Cache Tags and Copyback Buffer,” for more information.
Reading Data Cache Tags and Copyback Buffer
The MPC885 supports reading the tags, the state bits and the lock bits stored in the data cache as well as
the last copyback address, and data words in the copyback buffer. The data cache read command, issued
by reading DC_DAT, uses the DC_ADR register to qualify what is to be read. Table 7-10 describes the
fields of the DC_ADR register during a data cache read command.
Table 7-10. DC_ADR Fields for Cache Read Commands
0–17
Reserved
18
19
0 Tags
0 Way 0
1 Way 1
1 Copyback buffer
Reserved
20–27
28–31
Set select
(0–255)
Reserved
Copyback buffer address/
data-word select
To read the copyback buffer data or the tags stored in the data cache, do the following:
1. Write the address of the copyback buffer or tag to be read to the DC_ADR according to the format
shown in Table 7-10.
Note that it is also possible to read this register for debugging purposes.
2. Read the DC_DAT register. Note that writing to the DC_DAT register is illegal. A write to
DC_DAT results in an undefined data cache state.
For tag array (DC_ADR[18] = 0) read commands, the tag and state information is placed in the target
general-purpose register. Figure 7-11 provides the format of the DC_DAT register for a tag read.
Table 7-11. DC_DAT Format for a Tag Read (DC_ADR[18] = 0)
0–19
20–21
22
Tag value
Reserved
0 Invalid
1 Valid
23
0 Unlocked
1 Locked
24
25
26–31
LRU bit of this 0 Unmodified
set
1 Modified
Reserved
The last copyback address or data buffer can be read by using the copyback buffer read command
(DC_ADR[18] = 1). The copyback buffer select field (DC_ADR[20–27]), shown in Table 7-12,
determines which word of the cache block in the copyback buffer is read.
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Table 7-12. Copyback Buffer Select Field (DC_ADR[20–27]) Encoding
DC_ADR[20–27]
7.3.2.2
Buffer Selected
0x00
Copyback buffer data word 0
0x01
Copyback buffer data word 1
0x02
Copyback buffer data word 2
0x03
Copyback buffer data word 3
0x04
Copyback address
DC_CST Commands
All DC_CST commands, except the load-and-lock cache block and flush cache block commands, are
executed immediately after writing to the DC_CST register and do not generate any errors. Therefore,
there is no need to check the error type bits in the DC_CST register except when executing the
load-and-lock cache block and flush cache block commands.
Note that when the data cache is executing a command, it stops handling CPU requests, which can result
in machine stalls.
7.3.2.2.1
Data Cache Enable/Disable Commands
The data cache enable command (DC_CST[CMD] = 0b0010) is used to enable the data cache; the data
cache disable command (DC_CST[CMD] = 0b0100) is used to disable the data cache. Neither of these
commands has any error cases. The current state of the data cache is available by reading the data cache
enable status bit (DC_CST[DEN]).
When disabled, the MPC885 ignores the data cache state bits and operates as if all accesses have
caching-inhibited access attributes (that is, all accesses are propagated to the bus as single-beat
transactions). Disabling the data cache does not affect the data address translation logic; MSR[DR]
controls data address translation.
Note that the data cache is disabled at hard reset. Also, the data cache is automatically disabled when a
type 1 data cache error (see Table 7-7 for DC_CST[CCER1] conditions) generates a machine check
exception.
7.3.2.2.2
Data Cache Load-and-Lock Cache Block Command
The data cache load-and-lock cache block command (DC_CST[CMD] = 0b0110) is used to lock critical
data in the data cache. Locked cache blocks are not replaced during misses and are not affected by
invalidate commands.
To load and lock one or more cache blocks:
1. Read the DC_CST error type bits to clear them.
2. Write the address of the cache block to be locked to the DC_ADR register.
3. Write the load-and-lock cache block command (DC_CST[CMD] = 0b0110) to the DC_CST
register.
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4. Repeat steps 2 and 3 to load and lock another cache block.
5. Read DC_CST[CCER2] to determine if the sequence completed without errors.
After the load-and-lock cache block command is written to the DC_CST register, the cache checks if the
block containing the byte addressed by DC_ADR[ADR] is in the cache (hit). If it is in the cache, the block
is locked and the command terminates with no exception. If the block is not in the cache, a normal miss
sequence is initiated (see Section 7.6, “Data Cache Operation,” for more information). After the addressed
block is placed into the cache, the block is locked.
The user must check DC_CST[CCER2] to determine if the load-and-lock cache block operation
completed without error. The error type bits in the DC_CST register are sticky, thus allowing the user to
perform a series of load-and-lock commands before checking the termination status. These bits are set by
the MPC885 and are cleared by software.
Note that the MPC885 considers all zero-wait-state devices on the internal bus as caching-inhibited. For
this reason, software should not perform load-and-lock operations from these devices on the internal bus.
7.3.2.2.3
Data Cache Unlock Cache Block Command
The unlock cache block command (DC_CST[CMD] = 0b1000) is used to unlock previously locked cache
blocks. To unlock a cache block:
1. Write the address of the cache block to be unlocked to the DC_ADR register.
2. Write the unlock cache block command (DC_CST[CMD] = 0b1000) to the DC_CST register.
If the block is found in the cache (hit), it is unlocked and thereafter operates as a regular valid cache block.
If the block is not found in the cache (miss), no operation is performed. There are no error cases for the
unlock block command.
The data cache performs the unlock cache block command in one clock cycle.
7.3.2.2.4
Data Cache Unlock All Command
The data cache unlock all command (DC_CST[CMD] = 0b1010) is used to unlock the entire data cache
with a single command. When the unlock all command is performed, if a cache block is locked, it is
unlocked and thereafter operates as a regular valid cache block. If a block is not locked or if it is marked
invalid, no operation is performed. There are no error cases for the unlock all command.
The data cache performs the unlock all command in one clock cycle.
7.3.2.2.5
Data Cache Invalidate All Command
The data cache invalidate all command (DC_CST[CMD] = 0b1100) causes all unlocked, valid blocks in
the data cache to be marked invalid, regardless of whether the data is modified. Therefore, this command
may effectively destroy modified data. To invalidate the entire data cache the invalidate all command
should be preceded by an unlock all command. Note that the data cache is not automatically invalidated at
hard reset.
As a result of the invalidate all command, the LRU bits of all cache blocks point to either the unlocked
way or to way 0 if both ways are unlocked. There are no error cases for the invalidate all command.
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The data cache performs the invalidate all command in one clock cycle.
7.3.2.2.6
Data Cache Flush Cache Block Command
The data cache flush cache block command (DC_CST[CMD] = 0b1110) is used to write the contents of
an unlocked, modified-valid cache block to memory and subsequently invalidate that cache block. If the
cache block is unmodified-valid, the cache block is invalidated without writing the contents to memory. If
the cache block is locked or if it is marked invalid, no operation is performed.
If a bus error occurs while executing the DC_CST flush cache block command, DC_CST[CCER1] is set
and a machine check exception is generated. The data of the cache block flagged by the bus error is
contained in the copyback buffer; it will have already been flushed from the data cache array. See
Section 7.3.2.1, “Reading Data Cache Tags and Copyback Buffer,” for more information.
The cache control instructions dcbst and dcbf can also be used to flush the data cache. Note that the cache
control instructions operate on effective addresses that are translated while the DC_CST flush cache block
command operates on a physically addressed block contained within the data cache. When there is a need
to restrict the flushing to a specific memory area or to maintain architectural compliance, it is
recommended to use the cache control instructions; when there is a need to flush the entire data cache and
there is no concern for architectural compliance, using the DC_CST flush cache block command is more
efficient.
7.4
Cache Control Instructions
The PowerPC architecture defines instructions for controlling both the instruction and data caches. The
cache control instructions, icbi, dcbt, dcbtst, dcbz, dcbst, dcbf, and dcbi, are intended for the
management of the local caches. In the following descriptions, the memory/cache access attributes refer
to the write-through/write-back, caching-inhibited/caching-allowed, guarded/not guarded status of the
addressed page.
Note that the MPC885 does not broadcast cache control instructions nor does it snoop such broadcasts.
A TLB miss exception is generated if the effective address of one of these instructions cannot be translated
and data address relocation is enabled. A TLB error exception is generated if these instructions encounter
a TLB protection violation.
7.4.1
Instruction Cache Block Invalidate (icbi)
The effective address is computed, translated, and checked for protection violations as defined in the
PowerPC architecture. This instruction is treated as a store with respect to address translation and memory
protection. If the address hits an unlocked block in the instruction cache, the cache block is placed in the
invalid state. If the address misses in the instruction cache or if the block is locked, no action is taken. The
function of this instruction is independent of the memory/cache access attributes.
This command is not privileged and has no associated error cases. The instruction cache performs the icbi
instruction in one clock cycle. To accurately calculate the latency of this instruction, bus latency should be
taken into consideration.
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7.4.2
Data Cache Block Touch (dcbt) and
Data Cache BlockTouch for Store (dcbtst)
The Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store (dcbtst) instructions provide
potential system performance improvement through the use of software-initiated prefetch hints. The
MPC885 treats these instructions identically (that is, a dcbtst instruction behaves exactly the same as a
dcbt instruction on the MPC885).
The MPC885 loads the data into the cache when the effective address hits in the TLB, is permitted load
access from the addressed page, and is directed at a caching-allowed page. Otherwise, the MPC885 treats
these instructions as no-ops. The data brought into the cache as a result of this instruction is validated in
the same manner that a load instruction would be (that is, it is marked as unmodified-valid). Note that the
successful execution of the dcbt (or dcbtst) instruction affects the state of the TLB and cache LRU bits.
7.4.3
Data Cache Block Zero (dcbz)
The effective address is computed, translated, and checked for protection violations as defined in the
PowerPC architecture. The dcbz instruction is treated as a store to the addressed byte with respect to
address translation and protection.
If the block containing the byte addressed by the EA is in the data cache, all bytes are cleared, and the tag
is marked as modified-valid. If the block containing the byte addressed by the EA is not in the data cache
and the corresponding page is caching-allowed, the block is established in the data cache without fetching
the block from main memory, and all bytes of the block are cleared, and the tag is marked as
modified-valid.
The dcbz instruction executes regardless of whether the cache block is locked, but if the cache is disabled,
an alignment exception is generated. If the page containing the byte addressed by the EA is
caching-inhibited or write-through, the system alignment exception handler is invoked.
7.4.4
Data Cache Block Store (dcbst)
The effective address is computed, translated, and checked for protection violations as defined in the
PowerPC architecture. This instruction is treated as a load with respect to address translation and memory
protection.
If the address hits in the cache and the cache block is in the unmodified-valid state, no action is taken. If
the address hits in the cache and the cache block is in the modified-valid state, the modified block is written
back to memory and the cache block is placed in the unmodified-valid state.
If a bus error occurs while executing the dcbst instruction, DC_CST[CCER1] is set and a machine check
exception is generated. The data of the cache block flagged by the bus error is retrieved from the copyback
buffer, not from the data cache. See Section 7.3.2.1, “Reading Data Cache Tags and Copyback Buffer,” for
more information.
The function of this instruction is independent of the memory/cache access attributes. The dcbst
instruction executes regardless of whether the cache is disabled or the cache block is locked.
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7.4.5
Data Cache Block Flush (dcbf)
The effective address is computed, translated, and checked for protection violations as defined in the
PowerPC architecture. This instruction is treated as a load with respect to address translation and memory
protection.
If the address hits in the cache, and the block is in the modified-valid state, the modified block is written
back to memory and the cache block is placed in the invalid state. If the address hits in the cache, and the
cache block is in the unmodified-valid state, the cache block is placed in the invalid state. If the address
misses in the cache, no action is taken.
If a bus error occurs while executing the dcbf instruction, DC_CST[CCER1] is set and a machine check
exception is generated. The data of the cache block flagged by the bus error is retrieved from the copyback
buffer, not from the data cache. See Section 7.3.2.1, “Reading Data Cache Tags and Copyback Buffer,” for
more information.
The function of this instruction is independent of the memory/cache access attributes. The dcbf instruction
executes regardless of whether the cache is disabled or the cache block is locked.
7.4.6
Data Cache Block Invalidate (dcbi)
The effective address is computed, translated, and checked for protection violations as defined in the
PowerPC architecture. This instruction is treated as a store with respect to address translation and memory
protection.
If the address hits in the cache, the cache block is placed in the invalid state, regardless of whether the data
is modified. If the address misses in the cache, no action is taken. Because this instruction may effectively
destroy modified data, it is privileged (that is, dcbi is available only to programs at the supervisor privilege
level, MSR[PR] = 0).
The function of this instruction is independent of the memory/cache access attributes. The dcbi instruction
executes regardless of whether the cache is disabled or the cache block is locked.
7.5
Instruction Cache Operations
When the instruction MMU is enabled (MSR[IR] = 1), the instruction cache operates as defined by the
memory/cache access attributes. When the instruction MMU is disabled (MSR[IR] = 0), the instruction
cache operates as defined by the default instruction memory access attributes. The default state of the
caching-inhibited/caching-allowed attribute is determined by MI_CTR[CIDEF], and the entire memory
space defaults to the guarded attribute. See Chapter 8, “Memory Management Unit,” for more information.
An instruction cache access begins with an instruction fetch request from the instruction sequencer in the
MPC8xx core. As shown in Figure 7-1, bits 20–27 of the instruction address provide the index to select a
set (0–255) within the instruction cache array. The tags from each way of the set are compared against
bits 0–19 of the instruction address. If a match is found and the matched entry is valid, it is a cache hit. If
no tag matches or the matched tag is not valid, it is a cache miss.
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The data path for the instruction cache and its surrounding logic are shown in Figure 7-9.
Address [20–27]
Instruction Cache
Array
Set
Decoder
Address [28–29]
128
32
Data
Bypass
Mux
2->1
To Instruction
Sequencer
Word
Select
Mux
4->1
128
Stream
Hit
Mux
2->1
128 4-Word
Cache
Block
Buffer
128
4-Word
Burst
Buffer
128
32
32
Internal Data Bus
Figure 7-9. Instruction Cache Data Path
The 4-word burst buffer holds the last cache block received from the internal bus (the last miss); the 4-word
block buffer holds the last block retrieved from the instruction cache (the last hit). Note that if one of these
buffers contains the requested instruction, it is also considered a cache hit. To minimize power
consumption, the MPC885 can detect that one of the buffers contains the requested instruction and service
the instruction request from the buffers without activating the instruction cache array.
The MPC885 instruction cache includes the following operational features:
• Instruction fetch latency is reduced by sending the requested instruction address to the instruction
cache and internal bus simultaneously. A cache hit aborts the internal bus transaction before the
MPC885 can initiate an external fetch.
• The instruction cache supports stream hits (allows fetching from the burst buffer or directly from
the internal data bus, before the instruction cache array is filled)
• The instruction cache supports hits under misses (allows servicing hits while a previous miss is
being fetched from the external bus)
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•
•
•
7.5.1
A fetch request from the instruction sequencer has priority over burst buffer writes to the cache
array (the burst buffer holds the last missed cache block), thus increasing the overall performance
The cache efficiently uses the pipeblock of the internal data bus by initiating a new burst cycle (if
miss is detected) while bringing the tail of the previous missed block
Performance for caching-inhibited regions is enhanced by fetching a full 4-word block into the
burst buffer. Instructions in the burst buffer are only used once before being refetched
Instruction Cache Hit
In the case of a cache hit, the cache block is transferred to the cache block buffer and forwarded to the
stream hit multiplexer and word select multiplexer. As shown in Figure 7-2, bits 28–29 of the instruction
address select one word of the cache block which is transferred to the instruction sequencer in the core.
7.5.2
Instruction Cache Miss
On an instruction cache miss, the address of the missed instruction is driven on the internal bus with a
4-word burst transfer read request. The transfer begins with the word requested by the instruction
sequencer (critical-word first), followed by the remaining words (if any) of the cache block, then by any
remaining words at the beginning of the block (wrap-around).
On a cache miss, the critical word is simultaneously written to the burst buffer and forwarded to the
instruction sequencer, thus minimizing stalls due to cache fill latency. As subsequent words are received
from the internal bus, they are also written into the burst buffer and delivered to the instruction sequencer
either directly from the internal bus or from the burst buffer (a stream hit). A cache block in the array is
then selected to receive the cache block being gathered in the burst buffer. The selection algorithm gives
first priority to invalid blocks. If all blocks in the set are marked invalid, the block in way 0 is selected. If
none of the blocks in the selected set are invalid, the least recently used block is selected for replacement.
Locked cache blocks are never replaced.
The instruction cache is not blocked to internal accesses while the fetch (caused by a cache miss)
completes. This functionality is sometimes called ‘hits under misses,’ because the cache can service a hit
while a cache miss fill is waiting to complete. If no bus errors are encountered during the 4-word cache
block fetch, the burst buffer is marked valid and written to the cache array, provided the cache array is not
busy servicing a hit.
If a bus error is encountered while fetching the requested instruction (the critical word), a machine check
exception is generated. If a bus error occurs while fetching subsequent words in the cache block, the burst
buffer is marked invalid and the cache block is not written to the cache array.
7.5.3
Instruction Fetching on a Predicted Path
The core implements branch prediction to allow branches to issue as early as possible. This mechanism
allows instruction prefetching to continue while an unresolved branch is being computed and the condition
is being evaluated. Instructions fetched after unresolved branches are said to be fetched on a predicted
path. These instructions may be discarded later if it turns out that the machine has followed the wrong path.
To minimize power consumption, the MPC885 instruction cache does not initiate a miss sequence in most
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cases when the instruction is inside a predicted path. The MPC885 instruction cache evaluates fetch
requests to see if they are inside a predicted path. If a hit is detected, the requested instruction is delivered
to the core. However, if it is a cache miss, the miss sequence is not initiated in most cases until the core
finishes the branch evaluation.
7.5.4
Fetching Instructions from Caching-Inhibited Regions
The caching-inhibited/caching-allowed attributes of a memory region are programmed in the memory
management unit (MMU). To improve performance when fetching instructions from caching-inhibited
regions, the MPC885 loads the burst buffer with a full 4-word block. Instructions that are stored in the burst
buffer and originate from a cache-inhibited region, can be sent to the instruction sequencer, at most, once
before being refetched.
If an instruction fetch from a caching-inhibited region results in a cache hit, the instruction is delivered to
the instruction sequencer in the core from the cache and not from memory. However, it is considered a
programming error if an instruction fetch from a caching-inhibited region results in a cache hit. Software
must ensure that instructions from a caching-inhibited region have not been previously loaded into the
cache, or, if so, those blocks have been flushed from the cache. See Section 7.5.5, “Updating Code and
Memory Region Attributes,” for more information.
It is also considered a programming error to perform load-and-lock cache block operations from zero wait
state devices that are located on the internal bus. The MPC885 considers these devices as caching-inhibited
memory regions. If a load-and-lock cache block operation is performed from such a device, the instruction
is not guaranteed to be fetched from the instruction cache; in most cases, the instruction is fetched from
the device, regardless of whether it is in the instruction cache.
7.5.5
Updating Code and Memory Region Attributes
The instruction cache does not perform snooping, so if a processor modifies a memory location that may
be contained in the instruction cache, software must ensure that such memory updates are visible to the
instruction fetching mechanism. Also, whenever the memory/cache attributes of any memory region are
changed, it is critical that the cache contents reflect the new attributes. Therefore, when updating code or
changing memory region attributes (in the MMU) the user must perform the following steps:
1. Update code/change memory region attributes.
2. Execute a sync instruction to ensure the update/change operation finished.
3. Unlock all locked cache blocks containing code that was updated.
4. Invalidate all cache blocks containing code that was updated.
5. Execute an isync instruction.
7.6
Data Cache Operation
When the data MMU is enabled (MSR[DR] = 1), the data cache operates as defined by the memory/cache
access attributes. When the data MMU is disabled (MSR[DR] = 0), the data cache operates as defined by
the default data memory access attributes. The default state of the write-through/write-back attribute is
determined by MD_CTR[WTDEF]; the caching-inhibited/caching-allowed attribute is determined by
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MD_CTR[CIDEF]; and the entire memory space defaults to the guarded attribute. See Chapter 8,
“Memory Management Unit,” for more information.
A data cache access begins with a load or store request from the load/store unit (LSU) in the core. The data
cache has a 32-bit data path to and from the load/store unit, allowing for a 4-byte transfer per cycle. As
shown in Figure 7-2, bits 20–27 of the data address provide the index to select a set (0–255) within the data
cache array. The tags from both ways of the set are compared against bits 0–19 of the data address. If a
match is found and the matched entry is valid, it is a cache hit. If neither tag matches or the matched tag
is not valid, it is a cache miss.
The data cache operates in both write-through and write-back modes as programmed by the memory/cache
access attributes. These modes affect store hit and store miss behavior of the data cache. Load hits and load
misses behave the same regardless of the write-through/write-back mode. If two logical blocks map to the
same physical block, it is considered a programming error for them to specify different cache write
policies.
Each data cache block contains two state bits that implement a three-state
(modified-valid/unmodified-valid/invalid) protocol. The MPC885 does not support snooping of the data
cache. All memory is considered to have memory coherency not required attributes. Therefore, software
must maintain data cache coherency. The MPC885 does not provide support for snooping external bus
activity. All coherency between the internal caches and external agents (memory or I/O devices) must be
controlled by software. In addition, there is no mechanism provided for DMA or other internal masters to
access the data cache directly.
The MPC885 data cache includes the following operational features:
• Single-cycle cache access on hit and one clock latency added for miss
• The data cache supports hits under load misses.
• 1-word store buffer
• Store misses bypass the data cache (no-allocate store miss) in write-through mode
• 4-word copyback buffer holds replaced modified cache blocks until they can be written to memory
• Cache operation is blocked until the cache block is written to the cache array for store misses in
write-back mode,
• The data cache supports the sync instruction through a cache pipe clean indication to the core.
7.6.1
Data Cache Load Hit
In the case of a data cache load hit, the requested word is transferred to the load/store unit. The LRU state
of the set is updated, but the state bits remain unchanged.The access time for a data cache load hit is one
clock cycle (that is, zero wait states).
7.6.2
Data Cache Read Miss
In the case of a data cache load miss, a block in the cache array is selected to receive the data from memory.
The selection algorithm gives first priority to invalid blocks. If both blocks in the set are marked invalid,
the block in way 0 is selected. If neither of the two blocks in the selected set are invalid, the least recently
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used block is selected for replacement. If the replacement block is marked modified-valid, it is temporarily
stored in a copyback buffer to be written to memory later. Locked cache blocks are never replaced.
After a cache block has been selected, the word-aligned physical address of the requested data is sent to
the SIU with a 4-word burst transfer read request. The SIU arbitrates for the bus and initiates the burst read.
The transfer begins with the aligned word containing the requested data (critical word first), followed by
the remaining words of the cache block (if any), then by any remaining words at the beginning of the block
(wrap-around).
The critical word is simultaneously written to the burst buffer and forwarded to the load/store unit, thus
minimizing stalls due to cache fill latency. The data cache is not blocked to internal accesses while the load
(caused by a cache miss) completes. This functionality is sometimes called ‘hits under misses,’ because
the cache can service a hit while a cache miss fill is waiting to complete. If no bus errors are encountered
during the 4-word cache block load, the burst buffer is written to the cache array (provided the cache array
is not busy servicing a hit) and the cache block is marked unmodified-valid.
If a bus error is encountered while loading the requested data (the critical word), a machine check
exception is generated. If a bus error occurs while loading subsequent words in the cache block, the cache
block is marked invalid.
After the cache block with the requested data has been loaded from memory, the modified-valid cache
block in the copyback buffer is sent to the SIU to be written to memory. If a bus error is encountered during
the copyback, a machine check exception is generated (the copyback error is an imprecise exception). The
address and data in the copyback buffer can be read as specified in Section 7.3.2.1, “Reading Data Cache
Tags and Copyback Buffer.”
7.6.3
Write-Through Mode
In write-through mode, store operations always update memory. The write-through mode is used when
external memory and internal cache images must always agree. Write-through mode provides a lower
worst case exception latency at the expense of average performance (for example, if it does not have to
perform flush accesses).
7.6.3.1
Data Cache Store Hit in Write-Through Mode
In the case of a data cache store hit in write-through mode, the data is written into both the cache block
and to memory. The LRU state of the set is updated, but the state bits remain unchanged. If a bus error is
encountered during the write operation to memory, the cache block is still updated, but a machine check
exception is generated.
7.6.3.2
Data Cache Store Miss in Write-Through Mode
In the case of a store miss in write-through mode, the data is only written to memory, not to the data cache.
This is sometimes called a no-allocate store miss because the data cache does not allocate a cache block
in the cache array for the missed store operation. The state and LRU bits remain unchanged. If a bus error
is encountered during the write operation to memory, a machine check exception is generated.
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7.6.4
Write-Back Mode
In write-back mode, store operations do not necessarily update external memory. Data is only copied to
external memory when a copyback operation is required (or the cache is deliberately flushed). For this
reason the write-back mode is the preferred mode of operation when it is necessary to minimize external
bus utilization and as a side effect, reduce operational power consumption.
7.6.4.1
Data Cache Store Hit in Write-Back Mode
In the case of a data cache store hit in write-back mode, the cache operation depends on the state bits of
the cache block. If the store hit is to a modified-valid cache block, data is stored in the cache block and the
block stays marked modified-valid. If the store hit is to a unmodified-valid cache block, data is stored in
the cache block and the block is marked modified-valid. In either case, the LRU state of the set is updated
to reflect the hit.
7.6.4.2
Data Cache Store Miss in Write-Back Mode
In the case of a data cache store miss in write-back mode, the data cache must establish the block in the
cache array before modifying that block. Therefore, a block in the cache array is selected to receive the
data from memory and from the load/store unit. The selection algorithm gives first priority to invalid
blocks. If both blocks in the set are marked invalid, the block in way 0 is selected. If neither of the two
blocks in the selected set are invalid, the least recently used block is selected for replacement. If the
replacement block is marked modified-valid, it is temporarily stored in the copyback buffer to be written
to memory later. Locked cache blocks are never replaced.
After a cache block has been selected, the word-aligned physical address of the store data is sent to the SIU
with a 4-word burst transfer read request. The SIU arbitrates for the bus and initiates a burst read. The
transfer begins with the aligned word containing the requested data (critical word first), followed by the
remaining words of the cache block (if any), then by any remaining words at the beginning of the block
(wrap-around). As the critical word is received from the internal bus, it is merged in the burst buffer with
the store data from the load/store unit. If no bus errors are encountered during the burst buffer fill
operation, the cache block is written into the cache array and marked modified-valid. The data cache does
not support further requests until the entire block is written to the cache array. If the machine has stalled
waiting for the store to complete, execution is allowed to resume when the cache block is written into the
cache array.
If a bus error is encountered while loading the target data cache block, even on a word not accessed by the
load/store unit, the cache block is not modified, and a machine check exception is generated.
After the cache block with the requested data has been loaded from memory, the cache block in the
copyback buffer is sent to the SIU to be written to memory. The data cache can support further requests,
as long as they hit in the cache, while performing the copyback to memory. If a bus error is encountered
during the copyback, a machine check exception is generated (the copyback error is an imprecise
exception). The address and data in the copyback buffer can be read as specified in Section 7.3.2.1,
“Reading Data Cache Tags and Copyback Buffer.”
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7.6.5
Data Accesses to Caching-Inhibited Memory Regions
For load misses to caching-inhibited memory regions, the data is read from memory but not placed in the
cache and the cache status is not affected.
For store misses to caching-inhibited memory regions, the data is written to memory but not placed in the
cache and the cache status is not affected.
It is considered a programming error if a load, store, or dcbz targeting a caching-inhibited memory region
results in a cache hit. The PowerPC architecture allows the result of such programming errors to be
boundedly undefined. Software must ensure that data from a caching-inhibited regions have not been
previously loaded into the data cache, or, if they have, that those blocks have been flushed from the cache.
Whenever the memory/cache attributes of any memory region are changed (for example, from
caching-allowed to caching-inhibited), it is critical that the cache contents reflect the new attributes.
Therefore, when changing memory region attributes (in the MMU) the user must perform the procedures
described in Section 7.5.5, “Updating Code and Memory Region Attributes.”
7.6.6
Atomic Memory References
The PowerPC architecture defines the Load Word and Reserve Indexed (lwarx) and the Store Word
Conditional Indexed (stwcx.) instructions to provide an atomic update function for a single, aligned word
of memory. These instructions can be used to develop a rich set of multiprocessor synchronization
primitives. For detailed information about these instructions, refer to Section 5.2.4.6, “Memory
Synchronization Instructions—UISA,” in this book and Chapter 8, “Instruction Set,” in the Programming
Environments Manual.
The lwarx instruction performs a load word from memory operation and creates a reservation for the
16-byte section of memory that contains the accessed word. The reservation granularity is 16 bytes. The
lwarx instruction makes a nonspecific reservation with respect to the executing processor and a specific
reservation with respect to other masters. This means that any subsequent stwcx. executed by the same
processor, regardless of address, will cancel the reservation. Also, any bus write operation from another
processor to an address that matches the reservation address will cancel the reservation.
The stwcx. instruction does not check the reservation for a matching address. The stwcx. instruction is
only required to determine whether a reservation exists. The stwcx. instruction performs a store word
operation only if the reservation exists. If the reservation has been cancelled for any reason, the stwcx.
instruction fails and clears the CR0[EQ] bit in the condition register. The architectural intent is to follow
the lwarx/stwcx. instruction pair with a conditional branch which checks to see whether the stwcx.
instruction failed.
Note that atomic memory references constructed using lwarx/stwcx. instructions depend on the presence
of a coherent memory system for correct operation. These instructions should not be expected to provide
atomic access to noncoherent memory. Since the MPC885 does not snoop external bus activity, provision
is made to cancel a reservation inside the MPC885 by using the CR and KR input signals. The state of the
reservation is always presented onto the RSV output signal. This can be used by external agents to
determine when an internal condition has caused a change in the reservation state. See Section 13.4.9,
“Memory Reservation,” for more information. Internal to the MPC885, the data cache has snoop logic to
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monitor the internal bus for communication processor module (CPM) accesses of the address associated
with the last lwarx instruction.
If a memory region is marked caching-allowed, the MPC885 assumes that it is the single master in the
system to that region. If a caching-allowed lwarx or stwcx. access misses in the data cache, the transaction
on the internal and external buses do not have a reservation. If the memory region is marked
caching-inhibited or the cache is locked, and the access misses, the lwarx instruction appears on the bus
as a single-beat load with the reservation.
lwarx and stwcx. accesses to write-through memory regions do not generate DSI exceptions. The
MPC885’s data cache treats all stwcx. operations as write-through independent of the memory/cache
access attributes. When the write-through operation completes successfully on the external bus, the data
cache entry is updated (assuming it hits), and CR0[EQ] is modified to reflect the success of the operation.
If the reservation is not intact, the stwcx. cancels the external bus transaction, and the cache block is not
altered.
7.7
Cache Initialization after Reset
At power-on and hard reset, both caches are disabled. Although disabled, the cache state is preserved to
enable the user to investigate the exact state of the cache before the event that caused the reset. To ensure
proper operation after reset, initialize the instruction cache by performing the following:
1. Write the unlock all command (IC_CST[CMD] = 0b101) to the IC_CST register.
2. Write the invalidate all command (IC_CST[CMD] = 0b110) to the IC_CST register.
3. Write the cache enable command (IC_CST[CMD] = 0b001) to the IC_CST register.
Similarly, to ensure proper operation after reset, initialize the data cache by performing the following:
1. Write the unlock all command (DC_CST[CMD] = 0b1010) to the DC_CST register.
2. Write the invalidate all command (DC_CST[CMD] = 0b1100) to the DC_CST register.
3. Write the cache enable command (DC_CST[CMD] = 0b0010) to the DC_CST register.
After the caches are initialized, all the cache blocks are invalidated, and the LRU bits point to way 0 of
each set.
7.8
Debug Support
The MPC885 can be debugged either in debug mode or by a software monitor debugger. In both cases the
core of the MPC885 asserts the internal freeze signal. See Chapter 53, “System Development and
Debugging,” for a detailed description of the MPC885 debug support.
7.8.1
Instruction and Data Cache Operation in Debug Mode
The development system interface of the MPC885 uses the development port, which is a dedicated serial
port. The development port is a relatively inexpensive interface that allows a development system to
operate in a lower frequency than the core’s frequency and controls system activity when the core is in
debug mode. See Section 53.3, “Development System Interface,” for more information.
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When the MPC885 is in debug mode, all instructions are fetched from the development port, regardless of
the address generated by the MPC885 core. Therefore, the instruction cache is bypassed when the
MPC885 is in debug mode. In addition, the data cache is frozen in debug mode. Loads and stores in debug
mode always target system memory, regardless of whether the accessed data is resident in the data cache.
The only way to access the contents of the instruction or data cache in debug mode is by using the IC_DAT
or DC_DAT registers.
7.8.2
Instruction and Data Cache Operation with a Software Monitor
Debugger
With debug mode disabled, a software monitor debugger can use the development support registers to
assert the internal freeze signal during run-time. See Section 53.4, “Software Monitor Debugger Support,”
for more information.
When the internal freeze signal is asserted during run-time, the instruction cache treats all misses as if they
were from cache-inhibited regions. Misses are loaded only into the burst buffer; hits are loaded from the
cache array and the LRU bits are updated. If the debug routine is not in the instruction cache, it is loaded
from memory like any other miss and the cache state remains the same as before the freeze signal was
asserted.
For performance reasons, it may be preferable to run the debug routine from the cache. To load the debug
routine into the instruction cache before entering debug mode, perform the following procedure:
1. Save all four ways of the sets that are needed for the debug routine by reading the tag, the LRU,
valid, and lock bit states
2. Unlock the locked ways in the selected sets
3. Use the load-and-lock cache block command to load the debug routine into the instruction cache
and lock the cache blocks containing the debug routine.
4. Run the debug routine, all accesses to it will result in hits.
To restore the state of the instruction cache after the debug routine is finished, perform the following
procedure:
1. Unlock any ways in any sets that are used by the debug routine
2. Invalidate any ways in any sets that are used by the debug routine
3. Use the load-and-lock cache block command to restore the old sets in the cache array
4. Unlock any ways of the original sets that were not previously locked
5. To restore the old state of the LRU bits make sure that the last access (load-and-lock cache block
or unlock cache block command) is performed on the most-recently used way (not the LRU way).
When the internal freeze signal is asserted during run-time, the data cache treats all load misses as if they
were from cache-inhibited regions. That is, the data is loaded from memory and the cache LRU and state
bits are unchanged. Load hits are serviced from the cache array but the cache LRU and state bits are
unchanged.
When the internal freeze signal is asserted, store hits and misses are treated as write-through accesses, but
the LRU bits in the data cache array are not updated. For the dcbz instruction, data is written both into data
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cache and memory, but the LRU bits in the data cache array are not updated. For the dcbst/dcbf/dcbi
instructions, the data cache and memory are updated according to the PowerPC architecture, but the LRU
bits in the data cache array are not updated.
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Chapter 8
Memory Management Unit
The MPC885 implements a virtual memory management scheme that provides cache control, memory
access protections, and effective-to-physical (real) address translation. The MMU largely complies with
the PowerPC operating environment architecture (OEA) with respect to architecturally defined memory
management features that are appropriate for this implementation. It does not support some PowerPC
MMU features more appropriate for a personal computer that is expected to run many applications
simultaneously, and in some cases provides greater flexibility than is defined by the PowerPC architecture,
especially with respect to page sizes. Available protection granularity is 4-, 16-, 512-Kbyte, or 8-Mbyte
pages or 1-Kbyte subpages (for 4-Kbyte pages only). The MPC885 has separate instruction and data
MMUs. The prefix Mx_ indicates a reference to both the instruction and data (MI_ and MD_) versions of
the register. The MMU supports two protection modes—default mode with extended encoding and domain
manager mode, which provides programmable overrides to page protection settings.
8.1
Features
The following is a list of the MMU’s important features:
• Multiple page sizes—4-, 16-, 512-Kbyte, or 8-Mbyte pages (optional 1-Kbyte subpage protection
granularity for 4-Kbyte pages) with the following page attributes:
— Changed bit support through the DTLB error exception on a write attempt to a unmodified page
(data MMU only)
— Write-through attribute for data accesses
— Cache-inhibit attribute for data and instruction accesses
— Default write-through and cache-inhibited attributes can be programmed for when translation
is disabled
— Guarded attribute for memory-mapped I/O and other nonspeculative regions
• Instruction and data address translation can be disabled separately
• MPC885-specific special-purpose registers (SPRs) accessible with the PowerPC mfspr/mtspr
instructions
• Supports up to 16 virtual address spaces
• Supports 16 access protection groups (group protection overrides page protection)
• Separate-entry, fully associative data translation lookaside buffer (DTLB) and instruction TLB
(ITLB) with the following features:
— Implementation-specific exceptions—ITLB and DTLB miss exceptions, ITLB and DTLB
error exceptions
— Supports PowerPC tlbie and tlbia instructions. The tlbsync instruction, which is optional to
PowerPC architecture implementations, is not supported and is treated as a no-op.
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•
•
8.2
— Software tablewalk updates supported by DTLB and ITLB miss exceptions and SPRs
— Each entry can be programmed to match user or supervisor accesses or both.
— Entries in each TLB can optionally be locked to ensure fast translation for selected regions.
High performance
— 1 clock (zero wait state) access for a data cache hit and for an instruction cache hit when the
access is from the same page as the previous access
— 1 clock penalty for other TLB hit instruction accesses
Low power consumption
PowerPC Architecture Compliance
The MPC885 core complies largely with the MMU as it is defined by the OEA, with the following
differences:
• The MPC885 does not implement the following PowerPC features:
— Block-address translation
— The optional direct-store functionality
— The memory coherency attribute
• The MPC885 supports the following additional features not defined by the PowerPC architecture:
— Variable page sizes. The OEA defines 4-Kbyte pages only
— Programmable defaults for write-through and cache-inhibited memory attributes when
translation is disabled.
— Additional registers and exceptions for handling table walks in software.
Note that although the MPC885 does not define segment registers as they are defined by the OEA, the
concept of segment is retained as the memory space accessible to the level-one table descriptors.
8.3
Address Translation
The core generates 32-bit effective addresses (EA) for memory accesses. Setting MSR[IR] and MSR[DR]
enables the effective-to-real translation for instruction fetching and data accesses, respectively.
Section 8.3.1, “Translation Disabled,” describes behavior when translation is disabled. Section 8.3.2,
“Translation Enabled,” describes behavior when translation is enabled.
8.3.1
Translation Disabled
Because the IMMU and DMMU are separate, translation can be disabled or enabled independently for data
and instruction accesses by clearing MSR[DR] and MSR[IR], respectively. When translation is disabled,
the effective address is also the physical address.
Because the page translation mechanism is not used, the protection attributes that are part of the page table
structure cannot be used, so defaults are used. The default for whether accesses are cache-inhibited are
programmed through Mx_CTR[CIDEF]. Data accesses can be either write-through (memory writes go
both to the cache and to external memory) or write-back (memory writes directly affect the cache only and
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memory is updated indirectly, such as when a modified data in the cache is cast-out by newer data at a
different address that maps to the same cache block). The default is configured by MD_CTR[WTDEF].
Also, when translation is disabled (real mode), the entire memory space is treated as guarded by default.
The implications of this are:
1. Speculative load/store accesses are stalled until they are no longer speculative.
2. Speculative instruction fetches outside of the current real-mode page are stalled until they are no
longer speculative. The size of real-mode page is determined by MI_CTR[PPM]. If
MI_CTR[PPM] = 0, the real-mode page size is 4 Kbytes; if MI_CTR[PPM] = 1, the real-mode
page size is 1 Kbyte.
This behavior can result in significant performance degradation.
8.3.2
Translation Enabled
Translations are generated on a per-page basis and are stored in tables in memory. Along with the
translation, each table entry holds attributes for that page, for example, whether a location is cacheable.
Recently used translations are kept in translation lookaside buffers (TLBs) in hardware. In the MPC885,
software handles the table lookup and TLB reload with little hardware assistance. This offers a flexible
translation table structure choice, because many systems would not benefit from a full-featured hardware
translation mechanism.
A TLB hit in multiple entries is avoided when a TLB is being reloaded. When TLB logic detects that a
new effective page number (EPN) overlaps one in the TLB (when taking into account pages sizes, subpage
validity flags, user/supervisor state, address pace ID (ASID), and the SH values of the TLB entries), the
new EPN is written and the old one is invalidated.
The MMU supports a multiple virtual address space model. Each translation is associated with an ASID,
which must equal the address space ID (CASID) for a translation to be valid.
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Figure 8-1 shows the flow for a read access or instruction fetch.
Data/Instruction Fetch
32-bit EA is generated
Same Page
(Fast TLB Hit)
?
Yes
Use current page description
No
Compare address
with TLB
entries
TLB
Hit
?
(1 clock penalty)
Yes
No
TLB reload (read page
description from external
memory to TLB)
Is page
valid
?
No
TLB Error Exception
Yes
Access permitted
by page protection
?
No
(20–23 clock penalty
Yes
@ one wait-state
external memory)
Use page description from TLB
Figure 8-1. Read/Instruction Fetch Flow Diagram
Figure 8-2 shows the flow for a load/store access, assuming translation is enabled. Because data transfers
have less locality than instruction fetches, the DMMU does not implement a fast TLB mechanism. The
DTLB is accessed for each transfer simultaneously with the data cache tag read, hence there is no time
penalty.
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Data/Instruction Fetch
32-bit EA is generated
Compare address
with TLB
entries
TLB
Hit
?
(0 clock penalty)
Is page
valid
?
Yes
No
No
TLB Error Exception
Yes
TLB reload (read page
description from external
memory to TLB)
Access permitted
by page protection
?
(20–23 clock penalty
@ one wait-state
external memory)
No
Yes
Use page description from TLB
Figure 8-2. Flow of Load/Store Access
8.3.3
TLB Operation
Each TLB contains pointers to pages in physical memory where data is indexed by the EPN. TLBs entries
can have different page sizes. The entry page size determines which EA bits are compared and how many
of its lsbs pass untranslated as physical address bits.
For a 4-Kbyte page, four subpage validity flags are supported, allowing any combination of 1-Kbyte
subpages to be mapped. For any other page size, all of these flags should have the same value.
Programming non-4-Kbyte pages with different valid bits is a programming error. Subpage validity flags
can be manipulated to implement 1–4-Kbyte pages or any other combination of 1-Kbyte subpages.
However, all subpages of an effective page frame must map to the same physical page. During translation,
the EA, the privilege level (MSR[PR]), and CASID are provided to the TLB, as shown in Figure 8-3. In
the TLB, the EA and CASID are compared with each entry’s EPN and ASID. The CASID is compared
only when the matching entry is programmed as unshared. See Table 8-12 and Table 8-13.
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MSR[PR] M_CASID[CASID] 32-Bit EA
20-Bit
Page
20-Bit
32-Bit Logical
Address
Byte
12-Bit
Page Protection
32-Entry Fully Associative TLB
ImplementationSpecific TLB
Miss Exceptions
to Core
Free Access
20-Bit
Physical Page Number
Protection
Group Number
Byte
No Access
Translation
Enabled
Translation
Enabled
ImplementationSpecific
Error Exceptions
to Core
Protection
Lookup Table
32-Bit Physical Address
Exception
Logic
Figure 8-3. Effective-to-Physical Address Translation for 4-Kbyte Pages Block Diagram
A TLB hit occurs if the incoming EA matches the EPN and M_CASID[CASID] matches the ASID field
in a valid TLB entry, and if the subpage validity flag is set for the subpage that the incoming EA points to.
If a hit is detected, the contents of the physical page number are concatenated with the appropriate number
of lsbs from the EA to form the physical address sent to the cache and memory system.
8.4
Using Access Protection Groups
Access control is assigned on a page-by-page basis; additional control is provided on a protection group
basis. Each TLB entry holds an access protection group (APG) number. When a match is detected, the
value of the matched entry’s APG is used to index a field in the access protection register (MI_AP or
MD_AP) that defines access control for the translation. Each Mx_AP contains 16 fields. The field content
is used according to the group protection mode.
To be consistent with the PowerPC OEA, the APG value should match the four msbs of the effective page
number. To override protection using APG, use it on blocks of addresses which are defined by the 4 msbs
of the effective page number. If APG is not to be used for a particular block, set the GP for that block to
‘client’ in the Mx_AP register. To ignore it globally, set all of the Mx_AP fields to 01. In default mode,
each field holds the Kp and Ks bits for the corresponding segment defined by the level-one table descriptor.
In domain manager mode, each field holds override information over the page protection setting: no
override, no access override, and free access override.
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8.5
Protection Resolution Modes
The MMUs can be programmed in three different modes that have different methods of defining the
protection resolution of the address space. These are as follows:
• Mode 1—Protection resolution to 4-Kbyte minimum page size. This is the simplest mode with the
most efficient memory size (that is, MMU tables are smaller). Use this mode if 1-Kbyte protection
resolution is not required.
In this mode, program the following:
— MD_CTR[TWAM] = 1
— Mx_CTR[PPM] = 0
— Bits 20–27 of the level-two descriptor take on the meaning described in the right side of
Table 8-4.
• Mode 2—Protection resolution to 1-Kbyte minimum subpage size, where all 4-Kbyte logical
address pages map to the same 4-Kbyte physical page, but the four 1-Kbyte subpages may have
different protection attributes.
In this mode, program the following:
— MD_CTR[TWAM]=1
— Mx_CTR[PPM]=1
For 4-Kbyte pages, program the four PP pairs (bits 20–27) to the subpage protection attributes for
the 1-Kbyte subpages.
For pages larger than 4 Kbytes, the four PP pairs (bits 20–27) must all be programmed to the same
protection attributes, which are applied to the full page.
This mode is just as efficient in memory size as mode 1, but has the memory protection resolution
of mode 3.
• Mode 3—Protection resolution to 1-Kbyte minimum subpage size, with no restriction on subpage
mapping. In this mode, program:
— MD_CTR[TWAM] = 0
— Mx_CTR[PPM] = 0
— Mx_CTR[PPCS] = 0
For pages larger than 4-Kbyte, program subpage validity flags (bits 24-27) of the level-two
descriptor (and thus Mx_RPN) to 0b1111.
For 4-Kbyte pages, there are four separate entries with different encodings of subpage validity flags
(bits 24–27) of the level-two descriptor (and thus Mx_RPN) allowable for each entry.
For 4-Kbyte pages, the subpage validity flags (bits 24–27) of the level-two descriptor (and thus
Mx_RPN) can be different for each of the four separate entries.
In this mode, the MMU page tables defined for the software tablewalk resolve to a single level-two
descriptor entry for a 1-Kbyte page. This is done by allowing manipulation of the subpage validity
flags of a 4-Kbyte page. For example:
— To define a 4-Kbyte page with uniform protection, create four level-two descriptors for the
4-Kbyte page, each with subpage validity flags set to 0b1111. All other fields of the level-two
descriptors must also be the same for each of these entries.
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— To define four different 1-Kbyte pages, create four level-two descriptors, but set the subpage
validity flags such that: entry one = 0b1000, entry two = 0b0100, entry three = 0b0010, entry
four = 0b0001. All other fields of the level-two descriptor can be set differently for each of
these entries.
— To define two different 2-Kbyte pages, create four level-two descriptors, but set the subpage
validity flags in pairs such that: entry one = 0b1100, entry two = 0b1100, entry three = 0b0011,
entry four = 0b0011. The other fields of the ‘paired’ level-two descriptors must be the same for
each of the pairs.
Other combinations are also possible.
This mode is the most complex and the most inefficient in memory size (that is, MMU tables are
approximately four times larger). However, it allows the most detailed resolution of protection with
full functionality.
IMMUs and DMMUs can use different modes; the IMMU could use mode 1 and the DMMU could use
mode 2, or vice versa. However, if mode 3 is desired, both MMUs must be in mode 3.
8.6
Memory Attributes
Memory attributes defined by the PowerPC architecture are implemented as follows:
• Reference and change bit updates—The MPC885 does not generate an exception for an R
(reference) bit update. In fact, there is no entry for an R bit in the TLB.
The change bit (C) is bit 23 in the level-two descriptor, described in Table 8-4. Software updates C
(changed) bits, but hardware treats the C bit (negated) as a write-protect attribute. Therefore,
attempting to write to a page marked unmodified invalidates that entry and causes an
implementation-specific DTLB error exception. If change bits are not needed, set the C bit to one
by default in the PTEs.
• Memory control attributes—The MPC885 supports cache inhibit (CI), writethrough (WT), and
guarded (G) attributes, defined in the PowerPC Virtual Environment Architecture (VEA). The
memory coherence (M) attribute is not supported; to ensure memory coherency, configure the page
as cache-inhibited. Chapter 7, “Instruction and Data Caches,” describes the effects of CI and WT
attributes in the MPC885.
The G attribute is used to map I/O devices that are sensitive to speculative (out-of-order) accesses.
An attempted speculative access to a page marked guarded (G = 1) stalls until either the access is
nonspeculative or is canceled by the core. Attempting to fetch from guarded memory causes an
implementation-specific instruction TLB error interrupt.
8.7
Translation Table Structure
The MMU hardware supports a two-level software tablewalk. Other table structures are not precluded.
Figure 8-4 shows the two-level translation table when MD_CTR[TWAM] = 1 (4-Kbyte resolution of
protection).
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0
19
Effective Address
19 20
9 10
0
Level-1 Table Pointer (M_TWB)
Level-2 Index
Level-1 Index
20-Bit
31
Page Offset
10-Bit
Level-1 Table Base
Level-1 Index
Level-1 Table
20-Bit
00
10-Bit
Level-1 Descriptor 0
12 for 4 Kbyte
14 for 16 Kbyte
19 for 512 Kbyte
23 for 8 Mbyte
Level-1 Descriptor 1
10-Bit
Level-1 Descriptor N
20-Bit
Level-1 Descriptor 1023
Level-2 Table Base
Level-2 Index
Level-2 Table
20-Bit
00
10-Bit
Level-2 Descriptor 0
Level-2 Descriptor 1
Level-2 Descriptor N
20 for 4 Kbyte
18 for 16 Kbyte
13 for 512 Kbyte
9 for 8 Mbyte
Level-2 Descriptor 1023
Physical Page Address
Page Offset
Physical Address
Figure 8-4. Two-Level Translation Table (MD_CTR[TWAM] = 1)
When MD_CTR[TWAM] = 1, the tablewalk begins at the level-one base address in M_TWB. EA[0–9]
indicates the level-one page descriptor. As shown in Table 8-1, an 8-Mbyte page requires two identical
entries in the level-one table, one for bit 9 = 0 and one for bit 9 = 1.
Table 8-1. Identical Entries Required in Level-One/Level-Two Tables
Identical Entries Required in Level-One Table
Identical Entries Required in Level-Two Table
Page Size
MD_CTR[TWAM] = 0
MD_CTR[TWAM] = 1
MD_CTR[TWAM] = 0
MD_CTR[TWAM] = 1
1 Kbyte
1
—
1
—
4 Kbytes
1
1
4
1
16 Kbytes
1
1
16
4
512 Kbytes
1
1
1
1
8 Mbytes
8
2
1
1
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The page size and the level-two base address are read from the level-one descriptor. If the page size is 512
Kbytes or 8 Mbytes, the level-two base address is used directly as the address of the level-two descriptor.
If the page size is less than 512 Kbytes, the address of the level-two descriptor is determined by indexing
the level-two base address by EA[10–19]. For 16-Kbyte pages, this requires that multiple identical
level-two descriptors be provided. This is summarized in Table 8-1.
Figure 8-5 shows the two-level translation table when MD_CTR[TWAM] = 0 (1-Kbyte resolution of
protection).
0
17
Effective Address
11 12
21 22
0
Level-1 Index
Level-1 Table Pointer (M_TWB)
18-Bit
Level-2 Index
31
Page Offset
12-Bit
Level-1 Table Base
Level-1 Index
Level-1 Table
18-Bit
00
12-Bit
Level-1 Descriptor 0
12 for 1 Kbyte
12 for 4 Kbyte
14 for 16 Kbyte
19 for 512 Kbyte
23 for 8 Mbyte
Level-1 Descriptor 1
10-Bit
Level-1 Descriptor N
20-Bit
Level-1 Descriptor 4095
Level-2 Table Base
20-Bit
Level-2 Index
Level-2 Table
00
10-Bit
Level-2 Descriptor 0
Level-2 Descriptor 1
20 for 1 Kbyte
20 for 4 Kbyte
18 for 16 Kbyte
13 for 512 Kbyte
9 for 8 Mbyte
Level-2 Descriptor N
Level-2 Descriptor 1023
Physical Page Address
Page Offset
Physical Address
Figure 8-5. Two-Level Translation Table (MD_CTR[TWAM] = 0)
During address translation, the msbs of the missed effective address are replaced by the physical page
address bits from the level-two page descriptor; the page size determines the number of replaced bits as
shown in Table 8-2. The remaining physical address bits come directly from the effective address. When
MD_CTR[TWAM] = 0, the tablewalk begins at the level-one base address placed in M_TWB. The
level-one table is indexed by EA[0–11] to get the level-one page descriptor. As shown in Table 8-1,
8-Mbyte pages must have eight identical entries in the level-one table for EA[9–11].
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Table 8-2. Number of Replaced EA Bits per Page Size
Page Size
Number of Replaced EA Bits
1 Kbyte
20
4 Kbyte
20
16 Kbyte
18
512 Kbyte
13
8 Mbyte
9
The page size and the level-two base address are read from the level-one descriptor. If the page size is 512
Kbytes or 8Mbytes, the level-two base address is used directly as the address of the level-two descriptor.
If the page size is less than 512 Kbytes, the address of the level-two descriptor is determined by indexing
the level-two base address by EA[12–21]. For 4Kbyte or 16 Kbyte pages, this requires that multiple
identical level-two descriptors be provided. This is summarized in Table 8-1.
The number of replaced bits depends on the page size, as shown in Table 8-2. The remaining physical
address bits are taken directly from the effective address.
8.7.1
Level-One Descriptor
Table 8-3 describes the level-one descriptor format supported by the hardware to minimize the software
tablewalk routine.
Table 8-3. Level-One Segment Descriptor Format
Bits
Name
Description
0–19
L2BA Level-2 table base address. Bits 18–19 should be 0b00 unless MD_CTR[TWAM] = 1.
20–22
—
Reserved
23–26
APG
27
G
Guarded memory attribute for entry
0 Nonguarded memory
1 Guarded memory
28–29
PS
Page size level one. Used with the level-two (L2) descriptor’s small-page-size (SPS) field; see
Section 8.7.3, “Page Size.”
00 Small (4 Kbyte or 16 Kbyte)
01 512 Kbyte
10 Reserved
11 8 Mbyte
30
WT
Writethrough attribute for entry
0 Copyback cache policy region (default)
1 Writethrough cache policy region
31
V
Access protection group
Level-one segment valid bit
0 Segment is not valid
1 Segment is valid
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8.7.2
Level-Two Descriptor
Table 8-4 describes the level-two descriptor format supported by hardware. (Section 8.5, “Protection
Resolution Modes,” describes the protection modes.)
Table 8-4. Level-Two (Page) Descriptor Format
Bits
Name
0–19
RPN
20–21
PP
22
PP1
Mode 2
Mode 1 or Mode 3
Physical (real) page number
Protection For Instruction Pages
Supervisor User
for 1st
subpage 00 No access No access
01 Executable No access
1x Executable Executable
2nd
subpage
For Data Pages
Supervisor
00 No access
01 R/W
10 R/W
11 R/W
User
No access
No access
R/O
R/W
23
1
For Instruction Pages
Supervisor User
Extended encoding:
00 No access No access
01 Executable No access
1x Reserved
Basic encoding:
00 Executable No access
01 Executable Executable
1x Executable Executable
For Data Pages
Supervisor
User
Extended encoding:
00 No access No access
01 R/O
No access
1x Reserved
Basic encoding:
00 R/W
No access
01 R/W
R/O
10 R/W
R/W
11 R/O
R/O
0 Bits 20–21 contain Basic encoding
1 Bits 20–21 contain extended encoding
C—Change bit for entry. Set to 1 by default if change
tracking functionality is not desired.
0 Unchanged region (write-protected)
1 Changed region, write allowed
24–25
3rd
subpage
26–27
4th
subpage
MD_CTR[PPCS] = 0.
For 1-Kbyte pages in mode
3, program to the
appropriate subpage
validity. For mode 1,
program to 0b1111.
MD_CTR[PPCS] = 1 (mode
1 only)
1000 Hit (supervisor
accesses only)
0100 Hit (user accesses
only)
1100 Hit for both
28
SPS
Small page size. Used with the level-one (L1) descriptor’s page-size (PS) field; see Section 8.7.3,
“Page Size.”
0 4 Kbyte
1 16 Kbyte or larger (512 Kbyte or 8 Mbyte)
29
SH
Shared page
0 Entry matches only if a TLB entry’s ASID field matches the value in M_CASID.
1 ASID comparison is disabled for the entry.
30
CI
Cache-inhibit attribute for the entry.
0 Caching is allowed.
1 Caching is inhibited.
31
V
Page valid bit
For pages larger than 4 Kbytes in mode 2, PP in bits [22–23,24–25,26–27] must equal the PP in bits [20–21].
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8.7.3
Page Size
The page size is determined by a combination of two fields: the page-size (PS) field in the level-one
descriptor and the small-page-size (SPS) field in the level-two descriptor. Table 8-5 shows how the two
fields select the page size.
Table 8-5. Page Size Selection
8.8
Level 1 [PS]
Level 2 [SPS]
Page Size
00
0
4 Kbyte
00
1
16 Kbyte
01
0
Reserved
01
1
512 Kbyte
10
x
Reserved
11
0
11
1
8 Mbyte
Programming Model
All MMU programming model registers are supervisor-level SPRs that are accessed by using mtspr and
mfspr. Attempting to access these SPRs in user mode causes a program exception. The tlbie and tlbia
instructions can be used to invalidate TLBs. MMU registers should be accessed when both MSR[IR] = 0
and MSR[DR] = 0. No similar restriction exists for tlbie and tlbia.
Table 8-6 lists the MPC885-specific MMU registers and indicates the sections that describe them. These
SPRs should be accessed when both instruction and data address translation is disabled.
Table 8-6. MPC885-Specific MMU SPRs
Register
Name
SPR
Section
Control Registers
MI_CTR
IMMU control register
784
8.8.1
MD_CTR
DMMU control register
792
8.8.2
8.8.3
TLB Source Registers
MI_EPN
IMMU effective number register
787
MD_EPN
DMMU effective number register
795
MI_TWC
IMMU tablewalk control register
789
8.8.4
MD_TWC
DMMU tablewalk control register
797
8.8.5
MI_RPN
IMMU real (physical) page number port
790
8.8.6
MD_RPN
DMMU real (physical) page number register
798
8.8.7
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Table 8-6. MPC885-Specific MMU SPRs (continued)
Register
Name
SPR
Section
796
8.8.8
Tablewalk Assist Registers
M_TWB
MMU tablewalk base register
Protection Registers
M_CASID
CASID register
793
8.8.9
MI_AP
IMMU access protection register
786
8.8.10
MD_AP
DMMU access protection register
794
Scratch Register
M_TW
MMU tablewalk special register
799
8.8.11
Debug Registers
MI_CAM
IMMU CAM entry read register
816
8.8.12.1
MI_RAM0
IMMU RAM entry read register 0
817
8.8.12.2
MI_RAM1
IMMU RAM entry read register 1
818
8.8.12.3
MD_CAM
DMMU CAM entry read register
824
8.8.12.4
MD_RAM0
DMMU RAM entry read register 0
825
8.8.12.5
MD_RAM1
DMMU RAM entry read register 1
826
8.8.13
8.8.1
IMMU Control Register (MI_CTR)
The IMMU control register (MI_CTR), shown in Figure 8-6, controls IMMU operation.
0
1
2
Field GPM PPM CIDEF
3
4
5
6
—
RSV4I
—
PPCS
Reset
—
R/W
16
Reset
15
0
R/W
Field
7
18
—
19
23
24
ITLB_INDX
31
—
0
R/W
R/W
SPR
784
Figure 8-6. IMMU Control Register (MI_CTR)
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Table 8-7 describes MI_CTR fields.
Table 8-7. MI_CTR Field Descriptions
Bits
Name
0
GPM
Group protection mode
0 Default mode
1 Domain manager mode
1
PPM
Page protection mode. Valid regardless of whether translation is enabled. If translation is
enabled, PPM determines how M x_RPN is interpreted. See Table 8-12 and Table 8-13.
0 Page resolution of protection
1 1-Kbyte resolution of protection for 4-Kbyte pages
2
CIDEF
3
—
4
RSV4I
5
—
6
PPCS
7–18
—
19–23
Default value for instruction cache-inhibit attribute when the IMMU is disabled (MSR[IR] = 0)
0 Caching is allowed.
1 Caching is inhibited.
Reserved. Ignored on write, returns 0 on read.
Reserve four ITLB entries. See Section 8.10.2, “Locking TLB Entries.”
0 ITLB_INDX decremented modulo 32
1 ITLB_INDX decremented modulo 28
Reserved. Ignored on write, returns 0 on read.
Privilege/user state compare mode
0 Ignore user/supervisor state during address compare
1 Account for user/supervisor state according to MI_RPN[24–27]
Reserved. Ignored on write, returns 0 on read.
ITLB_INDX ITLB index. Points to the ITLB entry to be loaded. Decremented every ITLB update
24–31
8.8.2
Description
—
Reserved. Ignored on write, returns 0 on read.
DMMU Control Register (MD_CTR)
The DMMU control register (MD_CTR), shown in Figure 8-7, controls DMMU operation.
0
1
2
3
4
5
6
7
15
Field GPM PPM CIDEF WTDEF RS4VD TWAM PPCS
Reset
0000_0
1
R/W
0
0_0000_0000
R/W
16
Field
—
18
—
Reset
19
23
24
DTLB_INDX
31
—
0x0000
R/W
R/W
SPR
792
Figure 8-7. DMMU Control Register (MD_CTR)
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Table 8-8 describes MD_CTR fields.
Table 8-8. MD_CTR Field Descriptions
Bits
Name
0
GPM
Group protection mode
0 Default mode
1 Domain manager mode
1
PPM
Page protection mode
0 Page resolution of protection
1 1-Kbyte resolution of protection for 4-Kbyte pages
2
CIDEF
CI default when the DMMU is disabled (MSR[DR] = 0)
0 Caching is allowed.
1 Caching is inhibited.
3
WTDEF
WT default when the DMMU is disabled (MSR[DR] = 0)
4
RSV4D
Reserve four DTLB entries. See Section 8.10.2, “Locking TLB Entries.”
0 DTLB_INDX decremented modulo 32
1 DTLB_INDX decremented modulo 28
5
TWAM
Tablewalk assist mode
0 1-Kbyte subpage hardware assist
1 4-Kbyte page hardware assist (default)
6
PPCS
Privilege/user state compare mode
0 Ignore user/supervisor state during address compare
1 Account for user/supervisor state according to MD_RPN[24–27]
7–18
—
19–23
Description
Reserved. Ignored on write, returns 0 on read
DTLB_INDX DTLB index. Points to DTLB entry to be loaded. Decremented every DTLB update.
24–31
—
Reserved. Ignored on write, returns 0 on read
IMMU/DMMU Effective Page Number Register (Mx_EPN)
8.8.3
The effective page number registers (MI_EPN and MD_EPN), shown in Figure 8-8, contain the EA to be
loaded into a TLB entry
0
15
Field
EPN
Reset
0000_0000_0000_0000
R/W
R/W
16
19
20
21
22
23
27
28
31
Field
EPN
—
EV
—
ASID
Reset
—
0
0
0
0
R/W
R
R/W
R
R/W
R/W
SPR
787 (MI_EPN); 795 (MD_EPN)
Figure 8-8. IMMU/DMMU Effective Page Number Register (Mx_EPN)
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Table 8-9 describes Mx_EPN fields.
Table 8-9. Mx_EPN Field Descriptions
Bits
Name
0–19
EPN
20–21
—
Reserved. Ignored on write, undefined on read
22
EV
TLB entry valid bit.
0 TLB entry is invalid
1 TLB entry is valid. EV is set to 1 on each ITLB/DTLB miss.
23–27
—
Reserved. Ignored on write, returns 0 on read
28–31
ASID
8.8.4
Description
Effective page number for TLB entry. Default value is the EA of the last ITLB/DTLB miss
Address space ID of the ITLB/DTLB entry to be compared with M_CASID[CASID]. Loaded with
M_CASID on a TLB miss.
IMMU Tablewalk Control Register (MI_TWC)
The IMMU tablewalk control register (MI_TWC), shown in Figure 8-9, contains the access protection
group and page size of the entry to be loaded into the TLB.
0
15
Field
—
Reset
0000_0000_0000_0000
R/W
R/W
16
22
23
26
27
28
29
30
31
Field
—
APG
G
PS
—
V
Reset
0
—
—
—
0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SPR
789
Figure 8-9. IMMU Tablewalk Control Register (MI_TWC)
Table 8-10 describes MI_TWC fields.
Table 8-10. MI_TWC Field Descriptions
Bits
Name
0–22
—
23–26
APG
27
G
Description
Reserved. Ignored on write, returns 0 on read.
Access protection group. Up to 16 protection groups supported. Default for ITLB miss is 0
Guarded memory attribute for entry
0 Nonguarded memory (default for ITLB miss)
1 Guarded memory
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Table 8-10. MI_TWC Field Descriptions (continued)
Bits
Name
28–29
PS
Page size level-one
00 Small (4 or 16 Kbyte. See MI_RPN[SPS]) Default for ITLB miss
01 512 Kbyte
10 Reserved
11 8 Mbyte
30
—
Reserved. Ignored on write, returns 0 on read.
31
V
Entry valid bit
0 Entry is not valid
1 Entry is valid. Default value on ITLB miss.
8.8.5
Description
DMMU Tablewalk Control Register (MD_TWC)
The DMMU tablewalk control register (MD_TWC), shown in Figure 8-10, contains the level-two pointer
and access protection group of an entry to be loaded into the TLB.
0
15
Field
L2TB
Reset
—
R/W
R/W
16
Field
Reset
19
L2TB
20
22
23
26
—
APG
27
G
28
29
PS
30
31
WT
V
—
R/W
R/W
SPR
797
Figure 8-10. DMMU Tablewalk Control Register (MD_TWC)
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Table 8-11 describes MD_TWC fields.
Table 8-11. MD_TWC Field Descriptions
Name
Description
Bits
Write
Read
0–19
L2TB
L2TB
20–22
—
23–26
APG
27
G
Guarded memory attribute of the entry:
0 Nonguarded memory. Cleared on DTLB miss.
1 Guarded memory
28–29
PS
Level-one page size. (Cleared on a DTLB miss.)
00 Small (4 Kbyte or 16 Kbyte. See MD_RPN)
01 512 Kbyte
10 Reserved
11 8 Mbyte
30
WT
—
Writethrough attribute for page entry:
0 Copyback data cache policy. Cleared on DTLB
miss.
1 Writethrough data cache policy
Returns 0 on read.
31
V
—
0 Entry is not valid
1 Entry is valid. (set on a DTLB miss)
Returns 0 on read
8.8.6
Write
Read
Tablewalk level-two table base value
L2INDX Ignore
Access protection group. Up to 16 protection groups
are supported. Set to 0000 on a DTLB miss.
Level-two table index. Returns
MD_EPN[10–19] when
MD_CTR[TWAM] = 1
Returns MD_EPN[12–21] when
MD_CTR[TWAM] = 0
IMMU Real Page Number Register (MI_RPN)
The IMMU real page number register (MI_RPN), shown in Figure 8-11, contains the physical address and
the memory attributes of an entry to be loaded into a TLB. MI_RPN should be written after MI_EPN and
MI_TWC are written.
0
15
Field
RPN
Reset
—
R/W
R/W
16
Field
Reset
19
RPN
20
27
PP
28
29
30
31
SPS
SH
CI
V
—
R/W
R/W
SPR
790
Figure 8-11. IMMU Real Page Number Register (MI_RPN)
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Table 8-12 describes MI_RPN fields. (Section 8.5, “Protection Resolution Modes,” describes the
protection modes.)
Table 8-12. MI_RPN Field Descriptions
Bits
Name
0–19
RPN
Real (physical) page number
20–21
PP
Protection attributes for
subpages 1–4.
Supervisor User
00 No access No access
01 Executable No access
1x Executable Executable
22
PP1
Mode 2
23
Extended Encoding:
Supervisor
User
00 No access
No access
01 Executable
No access
1x Reserved
Reserved
Basic Encoding:
Supervisor
00 Executable
01 Executable
1x Executable
User
No access
Executable
Executable
0 Bits 20–21 contain basic encoding
1 Bits 20–21 contain extended encoding
Reserved
24–25
MD_CTR[PPCS] = 0
For 1-Kbyte pages in mode 3, set
to the appropriate subpage
validity. Otherwise, set to
0b1111.
26–27
1
Mode 1 or Mode 3
MD_CTR[PPCS] = 1
1000 Hit only for supervisor
accesses
0100 Hit only for user accesses
1100 Hit for both
28
SPS
Small page size. Used with the level-one (L1) descriptor’s page-size (PS) field; see Section 8.7.3,
“Page Size.”
0 4 Kbyte
1 16 Kbyte or larger (512 Kbyte or 8 Mbyte)
29
SH
Shared page:
0 This entry matches only if ASID field in the TLB entry matches the value M_CASID.
1 ASID comparison is disabled for the entry.
30
CI
Cache-inhibit attribute for the entry.
0 Caching is allowed.
1 Caching is inhibited.
31
V
Entry valid indication.
For pages larger than 4 Kbytes in mode 2, PP in bits [22–23,24–25,26–27] must equal the PP in bits [20–21].
8.8.7
DMMU Real Page Number Register (MD_RPN)
The DMMU real page number register (MD_RPN), shown in Figure 8-12, contains the physical address
and the memory attributes of an entry to be loaded into a TLB. This register should be written after the
MD_EPN and MD_TWC registers.
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0
15
Field
RPN
Reset
—
R/W
R/W
16
17
Field
18
19
20
RPN
27
PP
Reset
28
29
30
31
SPS
SH
CI
V
—
R/W
R/W
SPR
798
Figure 8-12. DMMU Real Page Number Register (MD_RPN)
Table 8-13 describes MD_RPN fields. (Section 8.5, “Protection Resolution Modes,” describes the
protection modes.)
Table 8-13. MD_RPN Field Descriptions
Bits
Name
0–19
RPN
Real (physical) page number
20–21
PP
Protection attributes for
subpages 1–4.
Supervisor User
00 No access No access
01 R/W
No access
10 R/W
R/O
11 R/W
R/W
22
PP1
Mode 2
23
Mode 1 or Mode 3
Extended Encoding:
Supervisor
User
00 No access
No access
01 R/O
No access
1x Reserved
Basic Encoding:
Supervisor
00 R/W
01 R/W
10 R/W
11 R/O
User
No access
R/O
R/W
R/O
0 Bits 20–21 contain basic encoding
1 Bits 20–21 contain extended encoding
Change bit for DTLB entry. Set to 1 by default if change tracking
functionality is not desired.
0 Unchanged region. Write access causes an IMMU exception.
Software should take an appropriate action before setting this bit.
1 Changed region. Write access is allowed to this page.
24–27
MD_CTR[PPCS] = 0
For 1-Kbyte pages in mode 3, set
to the appropriate subpage
validity. Otherwise, set to
0b1111.
MD_CTR[PPCS] = 1
1000 Hit only for supervisor
accesses
0100 Hit only for user accesses
1100 Hit for both
28
SPS
Small page size. Used with the level-one (L1) descriptor’s page-size (PS) field; see Section 8.7.3,
“Page Size.”
0 4 Kbyte
1 16 Kbyte or larger (512 Kbyte or 8 Mbyte)
29
SH
Shared page
0 This entry matches only if the ASID field in the DTLB entry matches the M_CASID value.
1 ASID comparison is disabled for the entry.
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Memory Management Unit
Table 8-13. MD_RPN Field Descriptions (continued)
1
Bits
Name
Mode 2
Mode 1 or Mode 3
30
CI
Cache-inhibit attribute for the entry
0 Caching is allowed.
1 Caching is inhibited.
31
V
Entry valid indication
For pages larger than 4 Kbytes in mode 2, PP in bits [22–23,24–25,26–27] must equal the PP in bits [20–21].
8.8.8
MMU Tablewalk Base Register (M_TWB)
The MMU tablewalk base register (M_TWB), shown in Figure 8-13, contains a pointer to the level-one
table to be used in hardware-assisted tablewalk mode.
0
19 20
Field
L1TB
29 30 31
L1INDX
Reset
—
00
—
R/W
R/W
SPR
796
Figure 8-13. MMU Tablewalk Base Register (M_TWB)
Table 8-14 describes M_TWB fields.
Table 8-14. M_TWB Field Descriptions
Bits
Name
0–19
L1TB
20–29
Tablewalk level-one base value
L1INDX Level-one table index. Ignored on write, returns MD_EPN[0–9] on read when MD_CTR[TWAM] =
1. Returns MD_EPN[2–11] on read when MD_CTR[TWAM] = 0
30–31
8.8.9
Description
—
Reserved. Ignored on write, returns 0 on read.
MMU Current Address Space ID Register (M_CASID)
The MMU current address space ID register (M_CASID), shown in Figure 8-14, is used to compare the
current EA with the ASID field in the TLB entry when searching for a match.
0
Field
Reset
27 28
—
31
CASID
—
R/W
R/W
SPR
793
Figure 8-14. MMU Current Address Space ID Register (M_CASID)
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Memory Management Unit
Table 8-15 describes M_CASID fields.
Table 8-15. M_CASID Field Descriptions
Bits
Name
0–27
—
28–31
CASID
8.8.10
Description
Reserved. Ignored on write, returns 0 on read
Current address space ID. Compared with ASID field of a TLB entry to qualify a match
MMU Access Protection Registers (MI_AP/MD_AP)
The IMMU access protection register (MI_AP, SPR 786) contains the settings for the access protection
groups for the IMMU. The DMMU access protection register (MD_AP, SPR 794) is identical. Both
registers are shown in Figure 8-15.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field GP0 GP1 GP2 GP3 GP4 GP5
GP6
GP7
Reset
GP8
GP9 GP10 GP11 GP12 GP13 GP14 GP15
—
R/W
R/W
SPR
786 (MI_AP); 794 (MD_AP)
Figure 8-15. MMU Access Protection Registers (MI_AP/MD_AP)
MI_AP/MD_AP fields are described in Table 8-16.
Table 8-16. MI_AP/MD_AP Field Descriptions
Bits
Name
0–1
GPx
2–3
…
30–31
8.8.11
Domain Manager Mode (Mx_CTR[GPM] = 1)
GP
00 No access
01 Client–access permission defined by page
protection bits
10 Reserved
11 Manager–free access
Default Mode (M x_CTR[GPM] = 0)
GP = Ks/Kp as defined by PowerPC architecture
00 All accesses are treated as supervisor
01 Access permission defined by page
protection bits
10 User and supervisor interpretation is
swapped
11 All accesses are treated as user
MMU Tablewalk Special Register (M_TW)
The MMU tablewalk special register (M_TW), shown in Figure 8-16, is a scratch register used by
tablewalk exception handlers.
0
Reset
31
—
R/W
R/W
SPR
799
Figure 8-16. MMU Tablewalk Special Register (M_TW)
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Memory Management Unit
8.8.12
MMU Debug Registers
The MMU CAM and RAM entries can be read through MX_CAM, MX_RAM0, and MX_RAM1.
Attempting to write to MX_CAM using an mtspr instruction loads the CAM and RAM values of the entry
indexed by DTLB_INDX to MX_CAM, MX_RAM0, and MX_RAM1. Any register can be the source for
mtspr since its value is not used. The values of MX_CAM, MX_RAM0, and MX_RAM1 can be read
using mfspr; mtspr[MX_RAM0] and mtspr[MX_RAM1] are considered no-ops.
8.8.12.1
IMMU CAM Entry Read Register (MI_CAM)
Figure 8-17 shows the MMU instruction CAM entry read register (MI_CAM). When the
content-addressable memory of the MI_CAM register is read, it contains the effective address and page
sizes of an entry indexed by MI_CTR[ITLB_INDX]. MI_CAM is updated only by writing to it.
0
15
Field
EPN
Reset
—
R/W
R
16
Field
19
20
EPN
22
23
27
PS
ASID
Reset
28
SH
31
SPV
—
R/W
R/W
SPR
816
Figure 8-17. IMMU CAM Entry Read Register (MI_CAM)
Table 8-17 describes the MI_CAM fields.
Table 8-17. MI_CAM Field Descriptions
Bits
Name
0–19
EPN
20–22
PS
23–26
ASID
27
SH
Function
Effective page number
Page size. (Values not shown are reserved)
000 4 Kbyte
001 16 Kbyte
011 512 Kbyte
111 8 Mbyte
Address space ID of the DTLB entry to be compared with M_CASID[CASID]
Shared page
0 This entry matches only if the ASID field in the DTLB entry matches the value in M_CASID.
1 ASID comparison is disabled for the entry
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Table 8-17. MI_CAM Field Descriptions (continued)
Bits
Name
28
SPV
Function
Subpage validity (subpage 0)
0 Subpage 0 (Address[20–21] = 00) is not valid
1 Subpage 0 (Address[20–21] = 00) is valid
29
0 Subpage 1 (Address[20–21] = 01) is not valid
1 Subpage 1 (Address[20–21] = 01) is valid
30
0 Subpage 2 (Address[20–21] = 10) is not valid
1 Subpage 2 (Address[20–21] = 10) is valid
31
0 Subpage 3 (Address[20–21] = 11) is not valid
1 Subpage 3 (Address[20–21] = 11) is valid
8.8.12.2
IMMU RAM Entry Read Register 0 (MI_RAM0)
The IMMU RAM entry read register 0 (MI_RAM0), shown in Figure 8-18, contains the physical page
number and page attributes of an entry indexed by MI_CTR[ITLB_INDX]. This register is updated only
when MI_CAM is updated.
0
15
Field
RPN
Reset
—
R/W
R
16
19
Field
20
RPN
22
PS_B
23
24
CI
27
APG
Reset
—
R/W
R
SPR
817
28
31
SFP
Figure 8-18. IMMU RAM Entry Read Register 0 (MI_RAM0)
Table 8-18 describes MI_RAM0 fields.
Table 8-18. MI_RAM0 Field Descriptions
Bits
Name
0–19
RPN
20–22
PS_B Page size. (Values not shown are reserved)
000 4 Kbyte
001 16 Kbyte
011 512 Kbyte
111 8 Mbyte
23
CI
24–27
APG
Description
Real (physical) page number
Cache-inhibit attribute for the entry.
0 Caching is allowed.
1 Caching is inhibited.
Access protection group. Up to 16 protection groups supported (uses one’s complement format)
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Memory Management Unit
Table 8-18. MI_RAM0 Field Descriptions (continued)
Bits
Name
28
SFP
Description
Supervisor (supervisor) fetch permission
0 Subpage 0 (Address[20–21] = 00) Supervisor fetch is not permitted
1 Subpage 0 (Address[20–21] = 00) Supervisor fetch is permitted
29
0 Subpage 1 (Address[20–21] = 01) Supervisor fetch is not permitted
1 Subpage 1 (Address[20–21] = 01) Supervisor fetch is permitted
30
0 Subpage 2 (Address[20–21] = 10) Supervisor fetch is not permitted
1 Subpage 2 (Address[20–21] = 10) Supervisor fetch is permitted
31
0 Subpage 3 (Address[20–21] = 11) Supervisor fetch is not permitted
1 Subpage 3 (Address[20–21] = 11) Supervisor fetch is permitted
8.8.12.3
IMMU RAM Entry Read Register 1 (MI_RAM1)
The IMMU RAM entry read register 1 (MI_RAM1), shown in Figure 8-19, contains the protection mode
information of the entry indexed by MI_CTR[ITLB_INDX]. This register is updated only when MI_CAM
is written to
.
0
15
Field
—
Reset
0
R/W
R
16
25
26
29
30
31
Field
—
UFP
PV
G
Reset
0
—
—
—
R/W
R
SPR
818
Figure 8-19. IMMU RAM Entry Read Register 1 (MI_RAM1)
Table 8-19 describes MI_RAM1 fields.
Table 8-19. MI_RAM1 Field Descriptions
Bits
Name
0–25
—
26
UFP
Description
Reserved
User fetch permission
0 Subpage 0 (Address[20–21] = 00) User fetch is not permitted
1 Subpage 0 (Address[20–21] = 00) User fetch is permitted
27
0 Subpage 1 (Address[20–21] = 01) User fetch is not permitted
1 Subpage 1 (Address[20–21] = 01) User fetch is permitted
28
0 Subpage 2 (Address[20–21] = 10) User fetch is not permitted
1 Subpage 2 (Address[20–21] = 10) User fetch is permitted
29
0 Subpage 3 (Address[20–21] = 11) User fetch is not permitted
1 Subpage 3 (Address[20–21] = 11) User fetch is permitted
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Table 8-19. MI_RAM1 Field Descriptions (continued)
Bits
Name
30
PV
Page validity
0 Page is not valid
1 Page is valid
31
G
Guarded memory attribute for entry
0 Nonguarded memory
1 Guarded memory
8.8.12.4
Description
DMMU CAM Entry Read Register (MD_CAM)
When the DMMU CAM entry read register (MD_CAM), shown in Figure 8-20, is read, it contains the
effective address and page sizes of an entry indexed by MD_CTR[DTLB_INDX]. This register is updated
when a value is written to it.
0
15
Field
EPN
Reset
—
R/W
R(/W)
16
19
Field
20
EPN
23
24
SPVF
Reset
26
PS
27
SH
28
31
ASID
—
R/W
R(/W)
SPR
824
Figure 8-20. DMMU CAM Entry Read Register (MD_CAM)
Table 8-20 describes MD_CAM fields.
Table 8-20. MD_CAM Field Descriptions
Bits
Name
0–19
EPN
Description
Effective page number
20
SPVF Subpage validity flags
0 Subpage 0 (address[20–21] = 00) is not valid
1 Subpage 0 (address[20–21] = 00) is valid
21
0 Subpage 1 (address[20–21] = 01) is not valid
1 Subpage 1 (address[20–21] = 01) is valid
22
0 Subpage 2 (address[20–21] = 10) is not valid
1 Subpage 2 (address[20–21] = 10) is valid
23
0 Subpage 3 (address[20–21] = 11) is not valid
1 Subpage 3 (address[20–21] = 11) is valid
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Table 8-20. MD_CAM Field Descriptions (continued)
Bits
Name
24–26
PS
Page size. (Values not shown are reserved)
000 4 Kbyte
001 16 Kbyte
011 512 Kbyte
111 8 Mbyte
27
SH
Shared page
0 This entry matches only if the ASID field in the DTLB entry matches the value in M_CASID
1 ASID comparison is disabled for the entry
28–31
ASID
8.8.12.5
Description
Address space ID of the DTLB entry to be compared with M_CASID[CASID]
DMMU RAM Entry Read Register 0 (MD_RAM0)
The DMMU RAM entry read register 0 (MD_RAM0), shown in Figure 8-21, contains the physical page
number and page attributes of an entry indexed by MD_CTR[DTLB_INDX]. This register is updated
when any value is written to MD_CAM.
0
15
Field
RPN
Reset
—
R/W
R
16
Field
19
20
RPN
22
23
26
PS
APGI
Reset
27
28
29
G
WT
CI
30
31
—
—
R/W
R/W
SPR
825
Figure 8-21. DMMU RAM Entry Read Register 0 (MD_RAM0)
Table 8-21 describes MD_RAM0 fields.
Table 8-21. MD_RAM0 Field Descriptions
Bits
Name
0–19
RPN
20–22
PS
23–26
APGI
27
G
Description
Real (physical) page number
Page size. (Values not shown are reserved)
000 4 Kbyte
001 16 Kbyte
011 512 Kbyte
111 8 Mbyte
Access protection group inverted. Access protection group number in one’s complement format
Guarded memory attribute for the entry
0 Nonguarded memory
1 Guarded memory
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Memory Management Unit
Table 8-21. MD_RAM0 Field Descriptions (continued)
Bits
Name
28
WT
Writethrough attribute for the entry
0 Copyback data cache policy page entry
1 Writethrough data cache policy page entry
29
CI
Cache-inhibit attribute for the entry.
0 Caching is allowed.
1 Caching is inhibited.
30–31
—
Reserved
8.8.13
Description
DMMU RAM Entry Read Register 1 (MD_RAM1)
The DMMU RAM entry read register 1 (MD_RAM1), shown in Figure 8-22, contains the protection mode
information of the entry indexed by MD_CTR[DTLB_INDX]. This register is updated only when a value
is written to MD_CAM.
0
15
Field
—
Reset
0
R/W
R
16
17
18
19
22
Field
—
C
EVF
SA
Reset
0
—
—
—
23
24
25
26
27
28
29
30
31
SAT URP0 UWP0 URP1 UWP1 URP2 UWP2 URP3 UWP3
—
—
—
R/W
R
SPR
826
—
—
—
—
—
—
Figure 8-22. DMMU RAM Entry Read Register 1 (MD_RAM1)
Table 8-22 describes MD_RAM1 fields.
Table 8-22. MD_RAM1 Field Descriptions
Bits
Name
Description
0–16
—
Reserved
17
C
Change bit for DTLB entry
0 Unchanged region. Write access to this page results in the implementation-specific IMMU
exception invocation. Software should take an appropriate action before setting this bit to 1.
1 Changed region. Write access is allowed to this page.
18
EVF
Entry valid flag
0 Entry is invalid
1 Entry is valid
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Table 8-22. MD_RAM1 Field Descriptions (continued)
Bits
Name
19
SA
Description
Supervisor access
0 Subpage 0 (address[20–21] = 00) Supervisor access is not permitted
1 Subpage 0 (address[20–21] = 00) Supervisor access is permitted
20
0 Subpage 1 (address[20–21] = 01) Supervisor access is not permitted
1 Subpage 1 (address[20–21] = 01) Supervisor access is permitted
21
0 Subpage 2 (address[20–21] = 10) Supervisor access is not permitted
1 Subpage 2 (address[20–21] = 10) Supervisor access is permitted
22
0 Subpage 3 (address[20–21] = 11) Supervisor access is not permitted
1 Subpage 3 (address[20–21] = 11) Supervisor access is permitted
23
SAT
Supervisor access type
0 Supervisor access type is read only
1 Supervisor access type is read/write
24
URP0
User read permission page zero
0 Subpage 0 (address[20–21] = 00) User read access is not permitted
1 Subpage 0 (address[20–21] = 00) User read access is permitted
25
UWP0
User write permission page zero
0 Subpage 0 (address[20–21] = 00) User write access is not permitted
1 Subpage 0 (address[20–21] = 00) User write access is permitted
26
URP1
0 Subpage 1 (address[20–21] = 01) User read access is not permitted
1 Subpage 1 (address[20–21] = 01) User read access is permitted
27
UWP1
0 Subpage 1 (address[20–21] = 01) User write access is not permitted
1 Subpage 1 (address[20–21] = 01) User write access is permitted
28
URP2
0 Subpage 2 (address[20–21] = 10) User read access is not permitted
1 Subpage 2 (address[20–21] = 10) User read access is permitted
29
UWP2
0 Subpage 2 (address[20–21] = 10) User write access is not permitted
1 Subpage 2 (address[20–21] = 10) User write access is permitted
30
URP3
0 Subpage 3 (address[20–21] = 11) User read access is not permitted
1 Subpage 3 (address[20–21] = 11) User read access is permitted
31
UWP3
0 Subpage 3 (address[20–21] = 11) User write access is not permitted
1 Subpage 3 (address[20–21] = 11) User write access is permitted
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8.9
Memory Management Unit Exceptions
Table 8-23 describes MPC885-specific MMU exceptions.
Table 8-23. MPC885-Specific MMU Exceptions
Exception
Cause
ITLB miss
MSR[IR] = 1 and an attempt is made to fetch an instruction from a page whose EPN cannot be translated
by the ITLB. Tablewalk software is responsible for loading information for the missed page from the
translation table. See Section 8.10.1.1, “Translation Reload Examples,” and Section 6.1.3.2, “Instruction
TLB Miss Exception (0x01100).”
DTLB miss
MSR[DR] = 1 and an attempt is made to access a page whose EPN cannot be translated by the DTLB.
Tablewalk software is responsible for loading translation information for the missed page from the
translation table. See Section 8.10.1.1, “Translation Reload Examples,” and Section 6.1.3.3, “Data TLB
Miss Exception (0x01200).”
ITLB error
The EA cannot be translated and the level-one segment or page valid bit is zero in the translation table,
the fetch access violates memory protection, or the fetch access is to guarded memory and MSR[IR] = 1.
The exact exception cause is found in SRR1. Table 6-15 describes bit assignments. If needed, it is
software’s responsibility to invoke the ISI exception handler.
DTLB error
MSR[DR] = 1 and the EA of a load, store, icbi, dcbz, dcbst, dcbf, or dcbi cannot be translated and
either the level-one segment or page valid bit are zero in the translation table, the access violates
memory protection, or an attempt is made to write to a page with a negated change bit.
The DSISR explains invocation of the DTLB error exception handler. Table 6-16 describes bit
assignments. If needed, it is software’s responsibility to invoke the DSI exception handler.
8.10
TLB Manipulation
The TLBs can be updated in several ways. The TLB reloading process is primarily performed in software
with some hardware assistance. The TLB replacement counter can be configured to select only from the
first 28 entries in each TLB. TLBs can be invalidated by using the tlbie and tlbia instructions.
8.10.1
TLB Reload
The TLB reload (tablewalk) function is performed in the software with some hardware assistance. It
consists of the following actions:
• Automatic storage of the missed data or instruction EA and default attributes in MI_EPN or
MD_EPN. This value is loaded into the selected entry on a write to MI_RPN or MD_RPN.
• Automatic updating of the replacement location counter to point to the entry to be replaced. This
value is placed in the index field in MI_CTR and MD_CTR.
• As Figure 8-4 and Figure 8-5 show, the level-one pointer is generated when an mfspr[M_TWB] is
performed by concatenating the level-one table base with the level-one index.
• The level-two pointer is generated when an mfspr[MD_TWC] is performed by concatenating the
level-two table base (extracted from the level-one table) with the level-two index.
• The TLB entry is written by loading the tablewalk level-two entry value to Mx_RPN.
• A scratch register, M_TW, is provided in addition to the architecture-defined SPRG0–SPRG3, so
miss code need not corrupt existing GPRs.
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Memory Management Unit
8.10.1.1
Translation Reload Examples
The following examples reload a TLB entry using a two-level tree page table structure. In both examples,
M_TWB holds the base pointer to the first-level table and data and instruction address translation are
turned off. Figure 8-23 performs a DTLB reload.
dtlb_swtw
mtspr
M_TW, R1
# Save R1
mfspr
R1, M_TWB
# Load R1 with level-1 pointer
lwz
R1, (R1)
# Load level-1 page entry
mtspr
MD_TWC,R1
# Save level-2 base pointer and level-1 attributes
mfspr
R1, MD_TWC
# Load R1 with level-2 pointer while taking page
# size into account
lwz
R1, (R1)
# Load level-2 page entry
mtspr
MD_RPN, R1
# Write TLB entry
mfspr
R1, M_TW
# Restore R1
rfi
Figure 8-23. DTLB Reload Code Example
Figure 8-24 performs an ITLB reload.
itlb_swtw
mtspr
M_TW, R1
# Save R1
mfspr
R1, SRR0
# Load R1 with instruction miss EA (the same data
# may be taken from MI_EPN)
mtspr
MD_EPN, R1
# Save instruction miss EA in MD_EPN
mfspr
R1, M_TWB
# Load R1 with level-1 pointer
lwz
R1, (R1)
# Load level-1 page entry
mtspr
MI_TWC,R1
# Save level-1 attributes
mtspr
MD_TWC,R1
# Save level-2 base pointer
mfspr
R1, MD_TWC
# Load R1 with level-2 pointer while taking page
# size into account
lwz
R1, (R1)
# Load level-2 page entry
mtspr
MI_RPN, R1
# Write TLB entry
mfspr
R1, M_TW
# Restore R1
rfi
Figure 8-24. ITLB Reload Code Example
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8.10.2
Locking TLB Entries
Four entries in each TLB can be made unavailable to the replacement algorithm; thus by configuring the
TLB replacement counters, the user can lock translation entries into them.
As shown in Figure 8-25, setting MI_CTR[RSV4I] or MD_CTR[RSV4D], configures the TLB
replacement counter to select only from the first 28 entries in each TLB. Those fields also affect the tlbia
instruction as described later. Replacement counters are cleared after a tlbia instruction executes.
ITLB_INDX decrements after an ITLB reload; DTLB_INDX decrements after a DTLB reload.
ITLB
DTLB
0
1
2
•
•
•
26
27
28
29
30
31
0
1
2
•
•
•
26
27
28
29
30
31
RSV4I = 1
RSV4D = 1
RSV4I = 0
RSV4D = 0
Figure 8-25. Configuring the TLB Replacement Counter
8.10.3
Loading Locked TLB Entries
The process of loading a single reserved entry in the TLB is as follows:
1. Disable the TLB by clearing MSR[IR] or MSR[DR] as needed.
2. Clear MI_CTR[RSV4I] (MD_CTR[RSV4D]).
3. Invalidate the EA of the reserved page by using tlbia or tlbie.
4. Set MI_CTR[ITLB_INDX] (MD_CTR[DTLB_INDX]) to the appropriate value (between 27 and
31).
5. Load Mx_EPN with the effective page number, the ASID of the reserved page, and set EV.
6. Run software tablewalk code to load the appropriate entry into the translation lookaside buffer. See
Section 8.10.1.1, “Translation Reload Examples.”
7. Repeat steps 4–6 to load other TLB entries.
8. Set MI_CTR[RSV4I] (MD_CTR[RSV4D]).
8.10.4
TLB Invalidation
Executing tlbie invalidates TLB entries that hit, including reserved entries. Note that EA[0–21] is used in
the comparison because segment registers as defined by the PowerPC architecture are not implemented.
Although for entries with pages larger than 4 Kbytes, some lower bits of the effective page number are
ignored. The ASID value in the entry is ignored for the purpose of matching an invalidate address; thus,
multiple entries can be invalidated if they have the same effective address and different ASID values.
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Executing tlbia invalidates all entries in both TLBs, however if MI_CTR[RSVI] or MD_CTR[RSVD] is
set, the reserved entries are not invalidated. Software can explicitly invalidate one or more of these entries
by setting MD_CTR[DTLB_INDX] or MI_CTR[ITLB_INDX], negating MD_EPN[EV] or
MI_EPN[EV], and writing to the appropriate MD_RPN or MI_RPN. The TLBs are not invalidated
automatically on reset, but are disabled. However, they must be invalidated under program control during
initialization.
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Chapter 9
Instruction Execution Timing
This chapter describes the timing of instructions that execute in the core. Examples show stalls and bubbles
due to serialization, latency, and blockage.
9.1
Instruction Execution Timing Examples
The following sections provide timings for the following scenarios:
• Data cache load
• Writeback arbitration
• Private writeback bus load
• Fastest external load (data cache miss)
• Full completion queue (CQ)
• Branch instruction handling
• Branch prediction
All examples assume an instruction cache hit.
9.1.1
Data Cache Load with a Data Dependency
Figure 9-1 shows a data cache load with zero wait states. The sub instruction depends on the value loaded
to r12,which causes a bubble in the instruction stream. The example in Section 9.1.3, “Private Writeback
Bus Load,” has no such dependency.
lwz
sub
addic
mulli
addi
r12,64 (SP)
r3,r12,3
r4,r14,1
r5,r3,3
r4,3(r0)
GCLK1
Fetch
Decode
Read + Execute
lwz
sub
addic
mulli
lwz
addi
sub
Bubble
lwz
addic
sub
Writeback
L Address Drive
L Data
Load Write Back
addic
sub
addic
ld
ld
ld
Figure 9-1. Data Cache Load Timing
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9-1
Instruction Execution Timing
9.1.2
Writeback Arbitration
In Figure 9-2, the addic instruction is dependent on the mulli result. Because the single-cycle instruction
sub has priority on the writeback bus over the mulli, the mulli writeback is delayed one clock and causes
a bubble in the execute stream.
mulli
sub
addic
r12,r4,3
r3,r15,3
4,r12,1
GCLK1
mulli
Fetch
sub
addic
mulli
Decode
sub
mulli
Read + Execute
addic
sub
Writeback
addic
Bubble
sub, mulli
mulli
addic
Figure 9-2. Writeback Arbitration Timing—Example 1
In this example, the addic instruction is dependent on sub rather than on mulli. Although the writeback
of the mulli is delayed two clocks, there is no bubble in the execution stream.
mulli r12,r4,3
sub r3,r15,3
addic r4,r3,1
GCLK1
Fetch
mulli
Decode
Read + Execute
sub
mulli
addic
sub
mulli
addic
sub, mulli
Writeback
addic
sub
addic
mulli
Figure 9-3. Writeback Arbitration Timing—Example 2
9.1.3
Private Writeback Bus Load
In Figure 9-4, lwz and xor write back in the same clock since they use the writeback bus in two different
ticks (a tick = 1/4 of a processor clock).
lwz
sub
cror
and
xor
ori
r12,64 (SP)
r5,r5,3
4,14,1
r3,r4.r5
r4,r3,r5
r6,r12.r3
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Freescale Semiconductor
Instruction Execution Timing
GCLK1
lwz
Fetch
sub
cror
load
Decode
and
cror
sub
load
Read + Execute
xor
sub
and
xor
cror
ori
xor
and
cror
sub
Writeback
ori
and
ori
ori
xor
lwz
L Address Drive
lwz
L Data
Cache Address
lwz
Load Writeback
lwz
E Address
lwz
E Data
lwz
Figure 9-4. Private Writeback Bus Load Timing
9.1.4
Fastest External Load (Data Cache Miss)
Figure 9-5 shows a sub instruction dependent on the value read by the load. It causes three bubbles in the
execution stream. Assuming SCCR[EBDF] = 00, the external clock (CLKOUT) is shifted 90° from the
internal clock (GCLK1).
lwz
sub
addic
r12,64 (SP)
r3,r12,3
r4,r14,1
GCLK1
Fetch
lwz
Decode
sub
addic
lwz
Read + Execute
sub
lwz
Bubble
Bubble
Bubble
Bubble
sub
Writeback
sub
L Address Drive
lwz
L Data
lwz
Cache Address
lwz
Load Writeback
lwz
E Address
lwz
lwz
E Data
Figure 9-5. External Load Timing
9.1.5
A Full Completion Queue
Figure 9-6 shows stalls due to a full CQ. Here, the CQ is full from executing sub, addic, and and. It takes
one more bubble from the load writeback to allow further issue while the CQ retires sub, addic, and and.
lwz
sub
addic
and
r12,64 (SP)
r5,r5,3
r4,r14,1
r3,r4.r5
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9-3
Instruction Execution Timing
xor
ori
r4,r3,r5
r7,r8,1
GCLK1
lwz
Fetch
sub
addic
lwz
Decode
sub
lwz
Read + Execute
and
xor
addic
sub
and
xor
addic
sub
Writeback
ori
Bubble
and
addic
Bubble
xor
and
xor
lwz
L Address Drive
lwz
L Data
lwz
Cache Address
lwz
Load Writeback
lwz
E Address
lwz
E Data
Figure 9-6. Full Completion Queue Timing
9.1.6
Branch Instruction Handling
In Figure 9-7 the lwz instruction accesses internal memory with one wait state. The IQ and parallel
operation of the BPU allows the two bubbles caused by the bl issue and execution to overlap the two
bubbles caused by the load. Issuing bl causes a bubble because it does no work.
lwz
sub
addic
bl
...
func:
mulli
addi
r12,64 (SP)
r3,r12,3
r4,r14,1
func
r5,r3,3
r4,3(r0)
GCLK1
Fetch
Decode
Read + Execute
lwz
sub
addic
lwz
bl
Bubble
sub
lwz
mulli
addic
Bubble
Bubble
L Data
sub
mulli
addic
lwz
lwz
Load Writeback
Branch Decode
mulli
addic
sub
Writeback
L Address Drive
addi
lwz
bl
Branch Execute
bl
Figure 9-7. Branch Folding Timing
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Instruction Execution Timing
9.1.7
Branch Prediction
In this example, the blt instruction is dependent on the cmpi instruction. Nevertheless, the BPU predicts
the correct path and allows an overlap of its bubbles with those of lwz. When cmpi writes back, the BPU
reevaluates the decision. If the prediction is correct, no more action is taken and execution continues.
Instructions on the predicted path cannot be dispatched before the condition is resolved.
while:
mulli
addi
...
lwz
cmpi
addic
blt
...
r3,r12,r4
r4,3(r0)
r12,64 (r2)
0,r12,3
r6,r5,1
cr0,while
GCLK1
Fetch
lwz
cmpi
Decode
addic
blt
Bubble
lwz
Read + Execute
cmpi
lwz
mulli
cmpi
Writeback
addic
cmp
L Address Drive
addi
addic
Bubble
Bubble
mulli
mulli
addic
lwz
L Data
lwz
Load Writeback
lwz
Branch Decode
blt
Branch Execute
Branch Final
Decision
blt
blt
Figure 9-8. Branch Prediction Timing
9.2
Instruction Timing List
Table 9-1 summarizes instruction execution timings in terms of latency and blockage of the appropriate
execution unit. A serializing instruction blocks all execution units.
Table 9-1. Instruction Execution Timing
Instructions
Latency
Blockage
Branch: b, ba, bl, bla, bc, bca, bcl, bcla, bclr, bclrl,
bcctr, bcctl
Taken 2
2
Not taken 1
1
System call: sc, rfi
Serialize + 2
CR logical: crand, crxor, cror, crnand, crnor, crandc,
creqv, crorc, mcrf
1
1
Unit
Serializing
BPU
No
—
Yes
BPU
No
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9-5
Instruction Execution Timing
Table 9-1. Instruction Execution Timing (continued)
Instructions
Integer trap: twi, tw
Latency
Blockage
Taken
serialize + 3
Serialize + 3
Not taken 1
1
Move to: mtspr, mtcrf, mtmsr, mcrxr except mtspr to LR Serialize + 1
and CTR and to SPRs external to the core.
Unit
IU
Serializing
After
No
All
Yes
1
BPU
No
Move to SPRs external to core: mtspr, mttb, mttbu. See Serialize + 11
Section 9.2.3, “Accessing Off-Core SPRs.”
Serialize + 1
LSU
Yes
Move from SPRs external to core: mfspr, mftb, mftbu
Load latency
1
LSU
No
Move from SPRs internal to core: mfspr2
1
—
See list 3
Move from: mfcr, mfmsr
Serialize + 1
—
See list 4
IU
No
Move to LR, CTR: mtspr
1
Integer arithmetic: addi, add, addis, subf, addic, subfic, 1
addic., addc, adde, subfc, subfe, addme, addze,
subfme, subfze, neg
Integer divide: divw, divwu
Min 2
Max 115
Min 2
Max 116
IU
No
Integer multiply: mul, mullw, mulhw, mulhwu
2
1 – 27
IU
No
Integer compare: cmpi, cmp, cmpli, cmpl
1
IU
No
Integer logical: andi., andis., ori, oris, xori, xoris, and, 1
or, xor, nand, nor, eqv, andc, orc, extsb, extsh, cntlzw
IU
No
Integer rotate and shift: rlwinm, rlwnm, rlwimi, slw,srw, 1
srawi, sraw
IU
No
Integer load: lbz, lbzu, lbzx, lbzux, lhz, lhzu, lhzx, lhzux, 28
lha, lhau, lhax, lhaux, lwz, lwzu, lwzx, lwzux, lhbrx,
lwbrx.
1
LSU
No
Integer store: stb, stbu, stbx, stbux, sth, sthu, sthx,
sthux, stw, stwu, stwbrx, stwx, stwux, sthbrx
11
1
LSU
No
Integer load/store multiple: lmw, smw
Serialize + 1 + no. of registers LSU
Yes
Synchronize: sync
Serialize + 1
LSU
Yes
Memory synchronization: lwarx, stwcx.
Serialize + 2
LSU
Yes
Move CR from XER: mcrxr
Serialize + 1
LSU
Yes
Move to/from SPR (Debug, DAR, DSISR): mtspr, mfspr
Serialize + 1
LSU
Yes
String instructions: lswi, lswx, stswi, stswx. See
Section 9.2.2, “String Instruction Latency.”
Serialize + 1 + no. of words
accessed
LSU
Yes
Memory control instructions: isync
Serialize
BPU
Yes
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Instruction Execution Timing
Table 9-1. Instruction Execution Timing (continued)
Instructions
Latency
Blockage
Unit
Serializing
Order memory access: eieio
1
LSU
Next load/store
is synchronized
with ones before
Cache control: icbi
1
LSU,
No
I-cache
1
Although a store (as well as mtspr for SPRs external to the core) issued to the LSU buffer frees the core pipeline, the
next load or store is not performed on the bus until it is free.
2
See Table 4-5.
3
Refer to Chapter 4, “MPC8xx Core Register Set.”
4
See Section 4.1.1.1.1, “Condition Register (CR),” and Section 4.1.2.3.1, “Machine State Register (MSR).”
5
DivisionLatency =
34 – divisorLength
N oO ve r flow ⇒ 3 + ⎛ ------------------------------------------------------⎞
⎝
⎠
4
-----------------------------------------------------------------------------------------------------------------------Ov er flo w ⇒ 2
x
MaxNegativ eNumber
Where Overflow = ⎛ ---⎞ or ⎛ --------------------------------------------------⎞
⎝ 0⎠ ⎝
⎠
–1
6
Division blockage = division latency.
Blockage of the multiply instruction is dependent on the next instruction.If the next instruction is a divide, the blockage
is 2 clocks; otherwise, the blockage is 1 clock.
8 Assumes nonspeculative aligned access, on-chip memory, and available bus. See Section 3.6.3.4, “Nonspeculative
Load Instructions,” Section 3.6.3.5, “Unaligned Accesses,” and Section 9.2.1, “Load/Store Instruction Timing.”
7
9.2.1
Load/Store Instruction Timing
Table 9-2. summarizes load/store instruction timings. This table assumes zero wait-state memory
references on a parked bus and pipelined external memory accesses.
Table 9-2. Load/Store Instruction Timing
Latency
Cleared from LSU
Instruction Type
Data Cache External Memory Data Cache External Memory
Integer single target register load (aligned)
2 cycles
5 cycles
2 cycles
5 cycles
Integer single target register store (aligned)
1 cycle
1 cycle
2 cycles
5 cycles
Load/store multiple
1+N1
N+1
3 + N + ⎛ --------------⎞
⎝ 3 ⎠
1+N
N+1
3 + N + ⎛ --------------⎞
⎝ 3 ⎠
1
N denotes the number of registers transferred.
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9-7
Instruction Execution Timing
9.2.2
String Instruction Latency
String accesses require separate aligned bus accesses. Figure 9-9 shows the maximum number of bus
cycles needed for string accesses where the beginning and end are unaligned.
Figure 9-9. Bus Latency for String Instructions
9.2.3
0x00
00
01
02
03
0x04
04
05
06
07
0x08
08
09
0A
0B
0x0C
0C
0D
0E
0F
0x10
10
11
12
13
0x14
14
15
16
17
0x18
18
19
1A
1B
2 Bus Cycles
Word Transfers
3 Bus Cycles
2 Bus Cycles
Accessing Off-Core SPRs
The LSU handles mtspr and mfspr accesses to off-core SPRs by using a special cycle on the internal bus.
See Section 4.1.3.1, “Accessing SPRs.” If the access ends in a bus error, a software emulation exception
is taken. All write operations to off-core SPRs (mtspr) are previously synchronized. In other words, the
instruction is not taken until all prior instructions terminate.
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Part III
Configuration and Reset
Audience
This part is intended for system designers and programmers who need to understand the operation of the
MPC885 at start up. It assumes an understanding of the programming model described in the previous
chapters and a high level understanding of the MPC885.
Contents
This part describes start-up behavior of the MPC885. It contains the following chapters:
• Chapter 10, “System Interface Unit,” describes the SIU, which controls system start-up,
initialization and operation, protection, as well as the external system bus.
• Chapter 11, “Reset,” describes the behavior of the MPC885 at reset and start-up.
Suggested Reading
Supporting documentation such as technical specifications, reference materials, and detailed applications
notes can be accessed through the world-wide web at http://www.freescale.com.
Conventions
This chapter uses the following notational conventions:
Bold entries in figures and tables showing registers and parameter RAM should
Bold
be initialized by the user.
mnemonics
Instruction mnemonics are shown in lowercase bold.
italics
Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
0x0
Prefix to denote hexadecimal number
0b0
Prefix to denote binary number
rA, rB
Instruction syntax used to identify a source GPR
rD
Instruction syntax used to identify a destination GPR
REG[FIELD]
Abbreviations or acronyms for registers or buffer descriptors are shown in
uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For
example, MSR[LE] refers to the little-endian mode enable bit in the machine state
register.
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III-1
x
In certain contexts, such as in a signal encoding or a bit field, indicates a don’t
care.
Indicates an undefined numerical value
n
Acronyms and Abbreviations
Table III-1 contains acronyms and abbreviations that are used in this document. Note that the meanings for
some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may
not be intuitively obvious.
Table III-1. Acronyms and Abbreviated Terms
Term
Meaning
BIST
Built-in self test
CRC
Cyclic redundancy check
CTR
Count register
DABR
Data address breakpoint register
DAR
Data address register
DEC
Decrementer register
DMA
Direct memory access
DRAM
Dynamic random access memory
DTLB
Data translation lookaside buffer
EA
Effective address
GPR
General-purpose register
IEEE
Institute of Electrical and Electronics Engineers
ITLB
Instruction translation lookaside buffer
LSB
Least-significant byte
lsb
Least-significant bit
LSU
Load/store unit
MMU
Memory management unit
MSB
Most-significant byte
msb
Most-significant bit
MSR
Machine state register
PCI
Peripheral component interconnect
RISC
Reduced instruction set computing
RTOS
Real-time operating system
Rx
SPR
Receive
Special-purpose register
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Table III-1. Acronyms and Abbreviated Terms (continued)
Term
SWT
Meaning
Software watchdog timer
TB
Time base register
TLB
Translation lookaside buffer
Tx
Transmit
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Chapter 10
System Interface Unit
The system interface unit (SIU) controls system startup, initialization and operation, protection, and the
external system bus. The system configuration and protection function controls the overall system and
provides various monitors and timers, including the bus monitor, software watchdog timer, periodic
interrupt timer (PIT), decrementer, and timebase. The clock synthesizer generates the clock signals for
other modules and external devices with which the SIU interfaces. The main system clock can be changed
dynamically; and the baud rate generators and serial ports work with a fixed frequency. For more
information, see Chapter 14, “Clocks and Power Control.”
The external bus interface handles the transfer of information between internal buses and the memory or
peripherals in the external address space. The MPC885 is designed to allow external bus devices to request
and obtain system bus mastership. Chapter 12, “External Signals,” describes bus operation. The memory
controller module provides a glueless interface to many types of memory devices and peripherals; it
supports a maximum of eight memory banks, each with its own device and timing attributes. Memory
control services are provided to both internal and external masters. The MPC885 supports circuit board
test strategies through user-accessible test logic that is fully compliant with the IEEE 1149.1 standard
described in Chapter 54, “IEEE 1149.1 Test Access Port.”
The PCMCIA host adapter module provides all control logic for a PCMCIA interface. This interface
complies fully with the PCMCIA standard, Release 2.1+ (PC Card -16). It can support PCMCIA socket
with a maximum of eight memory or I/O windows.
10.1
Features
The following is a list of the SIU’s main features:
• System configuration and protection
• System interrupt configuration
• System reset monitoring and generation
• Clock synthesizer
• Power management
• Decrementer
• Time base
• Periodic interrupt timer (PIT)
• External bus interface control
• Eight memory banks supported by the memory controller
• Debug support
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10-1
System Interface Unit
•
•
10.2
PCMCIA host adapter module supports slot with eight memory or I/O windows
IEEE 1149.1 test access port
System Configuration and Protection
The MPC885 incorporates many system functions that normally must be provided in external circuits. The
following features provide maximum system safeguards against hardware and/or software faults:
• System configuration—Allows control of show cycle operation, and part and mask number
constants.
• Bus monitor—Monitors the TA response time for bus accesses initiated by internal masters. TEA
is asserted if the TA response limit is exceeded. The bus monitor measures time between TS and
any termination of the bus cycle, including TA, TEA, and RETRY.
• Software watchdog timer (SWT)—Asserts a reset or nonmaskable interrupt (NMI) that is selected
by the system protection control register (SYPCR) if software fails to service this timer after a
certain period. After system reset, the timer, if enabled, selects a maximum time-out period and
asserts SRESET or NMI (system reset interrupt) if the time-out is reached. This timer can be
disabled or its time-out period can be changed in SYPCR. Once SYPCR is written, it cannot be
written again until a system reset.
• Periodic interrupt timer (PIT)—Generates periodic interrupts for use with a real-time operating
system (RTOS) or the application software. The PIT is clocked by the PITCLK clock and can be
disabled if it is not needed.
• Timebase counter—Provides a timebase reference for the operating system or application
software. This 64-bit timebase counter is defined by the PowerPC architecture and has two
independent reference registers that generate a maskable interrupt when the programmed value in
one of the registers is reached. The associated bit in the timebase status and control register
(TBSCR) is set for the reference register that generated the interrupt. The timebase is clocked by
the TMBCLK clock.
• Decrementer—Provides a decrementer register/interrupt clocked at the timebase frequency. This
32-bit decrementing counter is defined to be clocked by TMBCLK. When it is driven by a 4-MHz
oscillator the period for the decrementer is 4,295 seconds (approximately 71.6 minutes).
• Freeze support—The SIU determines whether the software watchdog timer, PIT, timebase, and
decrementer should continue to run in freeze mode.
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System Interface Unit
Figure 10-1 is a block diagram of the system configuration and protection logic.
Module
Configuration
Bus
Monitor
Clock
TEA
Periodic Interrupt
Timer
Interrupt
Software
Watchdog Timer
Interrupt or
System Reset
Decrementer
Interrupt
Timebase Counter
Interrupt
Figure 10-1. System Configuration and Protection Logic
10.3
Multiplexing SIU Pins
Due to the limited number of pins available in the MPC885 package, some of the pins share functions.
Table 10-1 shows how functionality is controlled on each pin.
Table 10-1. Multiplexing Control
Name
Pin Configuration Control
TSIZ0/REG
Dynamically active if the transaction addresses a slave controlled by the
PCMCIA interface.
BDIP/GPL_B5
RSV/IRQ2
KR/RETRY/IRQ4/SPKROUT
IRQ[3:6]
FRZ/IRQ6
Programmed in SIUMCR.
CS6/CE1_B
CS7/CE2_B
Address matching and bank valid bits. When a transfer matches either memory
controller bank 6 or any PCMCIA bank mapped to slot B, CS6/CE1_B is
asserted. When a transfer matches either memory controller bank 7 or any
PCMCIA bank mapped to slot B, CS7/CE2_B is asserted.
WE0/BS_AB0/IORD
WE1/BS_AB1/IOWR
WE2/BS_AB2/PCOE
WE3/BS_AB3/PCWE
Dynamically active depending on the machine (GPCM, UPMB, or PCMCIA
interface) assigned to control the required slave.
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10-3
System Interface Unit
Table 10-1. Multiplexing Control (continued)
Name
Pin Configuration Control
GPL_A0/GPL_B0
Dynamically active depending on the machine (UPMA or UPMB) assigned to
control the required slave.
OE/GPL_A1/GPL_B1
Dynamically active depending on the machine (GPCM, UPMA, or UPMB)
assigned to control the required slave.
GPL_A[2:3]/GPL_B[2:3]/CS[2:3]
GPL_A[2:3]/GPL_B[2:3]: Dynamically active depending on the machine (UPMA
or UPMB) assigned to control the required slave.
GPL_A[2:3]/CS[2:3]: Programmed in the SIUMCR.
ALE_B/DSCK/AT1
IP_B[0:1]/IWP[0:1]/VFLS[0:1]
IP_B2/IOIS16_B/AT2
IP_B3/IWP2/VF2
IP_B4/LWP0/VF0
IP_B5/LWP1/VF1
IP_B6/DSDI/AT0
IP_B7/PTR/AT3
TDI/DSDI
TCK/DSCK
TDO/DSDO
Programmed in the SIUMCR and hard reset configuration. See Section 11.3.1.1,
“Hard Reset Configuration Word.”
OP2/MODCK1/STS
OP3/MODCK2/DSDO
At power-on reset, this functions as MODCK[1:2]. Otherwise, programmed in the
SIUMCR and hard reset configuration.
10.4
Programming the SIU
The following sections describe registers used for programming the SIU.
10.4.1
Internal Memory Map Register (IMMR)
The internal memory map register (IMMR) is an SPR that identifies specific devices and the internal
memory map base address. Using mfspr, software can read IMMR to determine the location and
availability of any on-chip system resource. ISB can be written by mtspr, but PARTNUM and
MASKNUM are mask-programmed and cannot be changed.
0
15
Field
ISB
Reset
Set by reset configuration
R/W
R/W
16
23
24
31
Field
PARTNUM
MASKNUM
Reset
000_0000
Value depends on the mask revision
R
R
R/W
SPR
638
Figure 10-2. Internal Memory Map Register (IMMR)
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Table 10-2 describes IMMR fields.
Table 10-2. MMR Field Descriptions
Bits
Name
Description
0–15
ISB
Internal space base. Defines the base address of the internal memory space. At reset, ISB can
be configured to one of four addresses and changed to any value by the software. The number
of programmable ISB bits and the resolution of the location of internal space depends on the
implementation’s internal memory space. In the MPC885, all 16 bits can be programmed.
Chapter 2, “Memory Map,” describes the internal memory map. Section 11.3.1.1, “Hard Reset
Configuration Word,” describes available and default initial values.
16–23
PARTNUM
Part number (read-only). Mask programmed with a code corresponding to the part number of
the MPC885. Intended to help factory test and user code that is sensitive to part refinements.
PARTNUM would change if a new module is added or if the size of the memory module is
revised. However, it would not change if the part is revised to fix a bug in an existing module.
24–31
MASKNUM Mask number. (read-only) Mask programmed with a code corresponding to the mask number
of the MPC885. Intended to help factory test and user code that is sensitive to part refinements.
For the latest documentation on part/revision numbers and microcode REV_NUMs, see the MPC885
Website at www.freescale.com.
10.4.2
SIU Module Configuration Register (SIUMCR)
The SIU module configuration register (SIUMCR) contains bits that configure the following features in
the SIU:
• External bus arbitration
• External master support
• Debug and test port configuration
• System interface pin configuration
0
1
Field EARB
Reset
3
4
7
EARP
—
n
8
9
DSHW
10
n
000
(IMMR & 0xFFFF0000) + 0x000
Field
—
Reset
MPRE
20
21
MLRC
22
23
24
AEME SEME BSC
15
n
Addr
19
14
— FRC DLK
R/W
18
13
DBPC
000_0001_0
17
12
DBGC
R/W
16
11
25
26
27
GB5E B2DD B3DD
28
31
—
0000_0000_0000_0000
R/W
R/W
Addr
(IMMR & 0xFFFF0000) + 0x002
Figure 10-3. SIU Module Configuration Register (SIUMCR)
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This register is affected by HRESET but is not affected by SRESET. Table 10-3 describes SIUMCR fields.
Table 10-3. SIUMCR Field Descriptions
Bits
Name
Description
0
EARB
External arbitration. For more information, see Section 13.4.6, “Arbitration Phase.” The default value
depends on the reset configuration; see Section 11.3.1.1, “Hard Reset Configuration Word.”
0 Internal arbitration is performed.
1 External arbitration is assumed.
1–3
EARP
External arbitration request priority. Defines the priority of the external master’s arbitration request
relative to requests by internal modules. Valid when EARB is cleared. 000 = lowest priority and 111
= highest (however, the internal UPM-based refresh cycles always have a higher priority and will
preempt any external master if the internal arbiter is used). See Figure 13-21 and Table 19-1.
4–7
—
8
Reserved, should be cleared.
DSHW Data show cycles. Selects the show cycle mode to be applied to data cycles. Data show cycles do
not include CPU interaction with the data cache; they only include CPU interactions with peripherals
on the internal U-bus (that is, CPM and SIU). (Instruction show cycles are programmed in ICTRL
see the Hardware Specifications for more information.) This bit is locked by the DLK bit.
0 Disable show cycles for all internal data cycles.
1 Show address and data of all internal data cycles.
9–10
DBGC Debug pin configuration. The default is set by the hard reset configuration word. See
Section 11.3.1.1, “Hard Reset Configuration Word,” for the description of these bits.
11–12
DBPC
13
—
14
FRC
FRZ pin configuration. Configures the functionality of FRZ/IRQ6.
0 FRZ/IRQ6 functions as FRZ.
1 FRZ/IRQ6 functions as IRQ6.
15
DLK
Debug register lock. If DLK is set, bits 8–15 are locked and writes to those bits are no longer
performed. These bits can be written once the internal FRZ signal is asserted, regardless of the
state of DLK. Cleared at reset.
16-18
—
19
20–21
22
Debug port pins configuration. Determines the active pins for the development port. The default is
set by the hard reset configuration word. See Section 11.3.1.1, “Hard Reset Configuration Word,” for
the description of these bits.
Reserved, should be cleared.
Reserved, should be cleared.
MPRE Multiprocessors reservation enable.
0 RSV/IRQ2 functions as IRQ2, and CR/IRQ3 functions as IRQ3.
1 RSV/IRQ2 functions as RSV. The interprocessor reservation protocol is enabled. RSV functions
as defined in Section 13.4.9, “Memory Reservation.”
MLRC Multi-level reservation control. Configures the functionality of KR/RETRY/IRQ4/SPKROUT.
00 KR/RETRY/IRQ4/SPKROUT functions as IRQ4.
01 KR/RETRY/IRQ4/SPKROUT is three-stated.
10 KR/RETRY/IRQ4/SPKROUT functions as KR/RETRY.
11 KR/RETRY/IRQ4/SPKROUT functions as SPKROUT.
AEME Asynchronous external master enable. Configures how the memory controller refers to external
asynchronous masters initiating a transaction. If AEME = 1, the memory controller interprets any
assertion of AS as an external asynchronous master initiating a transaction. If it is reset, the memory
controller ignores the value of AS.
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Table 10-3. SIUMCR Field Descriptions (continued)
Bits
23
Name
Description
SEME Synchronous external master enable. Configures how the memory controller refers to synchronous
external masters initiating a transaction. If SEME = 1, the memory controller interprets any assertion
of TS not driven by the MPC885 as a synchronous external master initiating a transaction. If SEME
= 0, the memory controller ignores TS unless it is external bus master.
24
BSC
Configures how memory controller and PCMCIA interface byte selects and strobes are configured.
0 BS_A[0:3] are driven just on their dedicated pins.
WE0/BS_B0/IORD is driven on its dedicated pin.
WE1/BS_B1/IOWR is driven on its dedicated pin.
WE2/BS_B2/PCOE is driven on its dedicated pin.
WE3/BS_B3/PCWE is driven on its dedicated pin.
1 Assertion of either BS_A0, WE0, BS_B0 or IORD is driven on BS_A0 and WE0/BS_B0/IORD.
Assertion of either BS_A1, WE1, BS_B1 or IOWR is driven on BS_A1 and WE1/BS_B1/IOWR.
Assertion of either BS_A2, WE2, BS_B2 or PCOE is driven on BS_A2 and WE2/BS_B2/PCOE.
Assertion of either BS_A3, WE3, BS_B3 or PCWE is driven on BS_A3 and WE3/BS_B3/PCWE.
25
GB5E
GPL_B5 enable
0 The BDIP functionality is active.
1 The GPL_B5 of the memory controller functionality is active
26
B2DD
Bank 2 double drive. If this bit is set, CS2 is reflected on GPL_x2.
27
B3DD
Bank 3 double drive. If this bit is set, CS3 is reflected on GPL_x3.
28–31
—
10.4.3
Reserved, should be cleared.
System Protection Control Register (SYPCR)
The system protection control register (SYPCR) controls the system monitors and bus monitor timing. It
can be read at any time, but can be written only once after system reset. This register is affected by
HRESET but not by SRESET.
0
15
Field
SWTC
Reset
1111_1111_1111_1111
R/W
R/W
SPR
(IMMR & 0xFFFF0000) + 0x004
16
23
24
25
27
Field
BMT
BME
—
Reset
1111_1111
0
000
R/W
R/W
SPR
(IMMR & 0xFFFF0000) + 0x006
28
29
30
31
SWF SWE SWRI SWP
0
1
1
1
Figure 10-4. System Protection Control Register (SYPCR)
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Table 10-4 describes SYPCR fields.
Table 10-4. SYPCR Field Descriptions
Bits
Name
Description
0–15
SWTC Software watchdog timer count. Count value for the software watchdog timer.
16–23
BMT
Bus monitor timing. Defines the timeout period, in 8 system clock resolution, for the bus monitor.
maximum timeout is 2,040 clocks.
24
BME
Bus monitor enable. Controls bus monitor operation during internal-to-external bus cycles.
0 Disable the bus monitor
1 Enable the bus monitor
Note: If the bus monitor is disabled, transfer error conditions do not cause TEA to be asserted.
25–27
—
28
SWF
Software watchdog freeze
0 The software watchdog timer continues counting even if FRZ is asserted.
1 The software watchdog timer stops counting when FRZ is asserted.
29
SWE
Software watchdog enable.
To disable the software watchdog timer, it should be cleared by the software after a system reset.
0 Software watchdog timer disabled
1 Software watchdog timer enabled (default)
30
SWRI
Software watchdog reset/interrupt select.
0 The software watchdog timer causes an NMI (system reset interrupt) to the core.
1 The software watchdog timer causes an HRESET. (default)
31
SWP
Software watchdog prescale.
0 The software watchdog timer is not prescaled.
1 The software watchdog timer is prescaled by a factor of 2,048 (default).
10.4.4
Reserved, should be cleared.
Transfer Error Status Register (TESR)
The transfer error status register (TESR) has a bit for each transfer error exception source. Set bits indicate
what type of transfer error exception that occurred since bits were last cleared. Bits are cleared by reset or
by writing ones to them. Canceled speculative accesses that do not cause an interrupt may set these bits.
TESR has two identical sets of fields, one for instruction transfers and one for data transfers.This register
is affected by HRESET and SRESET.
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0
15
Field
—
Reset
xxxx_xxxx_xxxx_xxxx
R/W
R/W
SPR
(IMMR & 0xFFFF0000) + 0x020
16
Field
17
18
—
19
20
21
22
IEXT ITMT
23
24
25
—
Reset
26
27
DEXT DTMT
28
29
30
31
—
0000_0000_0000_0000
R/W
R/W
SPR
(IMMR & 0xFFFF0000) + 0x022
Figure 10-5. Transfer Error Status Register (TESR)
Table 10-5 describes the TESR fields.
Table 10-5. TESR Field Descriptions
Bits
Name
0–17
—
18
IEXT
Instruction external transfer error acknowledge. Set if the cycle is terminated by an externally
generated TEA when an instruction fetch is initiated.
19
ITMT
Instruction transfer monitor timeout. Set if the cycle is terminated by a bus monitor timeout when
an instruction fetch is initiated.
20–25
—
26
DEXT
Data external transfer error acknowledge. Set if the cycle is terminated by an externally
generated TEA signal when a data load or store is requested by an internal master.
27
DTMT
Data transfer monitor timeout. Set if the cycle is terminated by a bus monitor timeout when a data
load or store is requested by an internal master.
28–31
—
10.4.5
Description
Reserved, should be cleared.
Reserved, should be cleared.
Reserved
Register Lock Mechanism
To provide protection of the SIU registers against uncontrolled shutdown, a register locking mechanism is
included. These registers can be write-protected in a set of associated key registers. The MPC885 key
registers are shown in Table 10-6.
Table 10-6. Key Registers
Offset
Name
Size
System Integration Timers Keys
0x300
TBSCRK—Timebase status and control register key
32 bits
0x304
TBREFAK—Timebase reference register A key
32 bits
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Table 10-6. Key Registers (continued)
Offset
Name
Size
0x308
TBREFBK—Timebase reference register B key
32 bits
0x30C
TBK—Timebase/decrementer register key
32 bits
0x310–31F
Reserved
16 bytes
0x320
Reserved
32 bits
0x324
Reserved
32 bits
0x328
Reserved
32 bits
0x32C
Reserved
32 bits
0x330–33F
Reserved
16 bytes
0x340
PISCRK—Periodic interrupt status and control register key
32 bits
0x344
PITCK—Periodic interrupt count register key
32 bits
0x348–37F
Reserved
56 bytes
Clocks and Reset Keys
0x380
SCCRK—System clock control key
32 bits
0x384
PLPRCRK—PLL and reset control register key
32 bits
0x388
RSRK—Reset status register key
32 bits
0x38C–7FF
Reserved
1140 bytes
Each register has a key register that can be in an open or locked state. At power-on reset, all key registers
are open. Each key register has an associated address in the internal memory map, as shown in Table 10-6.
A write of 0x55CC_AA33 to a key register unlocks its associated SIU register; any other access (including
reads or writes of any other value) to a key register locks its associated SIU register. For example, writing
a 0x55CC_AA33 to the TBK key register allows the Timebase/decrementer register to be written. The key
registers are write-only; a read of the key register does not return the last value written.
When a register is locked, an attempt to write to it will result in a machine check exception, and will not
change the value in the register. One exception to this is the timebase register (TBU and TBL), locked with
TBK. A write to the timebase register when it is locked results in a software emulation exception.
Reads are allowed at all times to any of the SIU registers, regardless of whether they are locked or
unlocked.
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Write any other value to the key register
Power-on reset
Open
Locked
Write 0x55CC_AA33 to the key register
Figure 10-6. Register Lock Mechanism
10.5
System Configuration
The SIU module configuration register (SIUMCR) is used for configuring external bus arbitration logic,
external master support, and pin multiplexing. See Section 10.4.2, “SIU Module Configuration Register
(SIUMCR).”
10.5.1
Interrupt Structure
The SIU receives interrupts from internal sources, like the PIT, communications processor module (CPM),
and the external IRQ pins. Figure 10-7 shows the MPC885 interrupt structure.
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Software
Watchdog Timer
SIU
IRQ[0-4]
IRQ[6-7]
NMI
Generator
IRQ0
Edge
Detector
NMI
Selector
Decrementer
Decrementer
Level 7
Timebase
Periodic
Interrupt Timer
Level 6
MPC8xx
CORE
Level 5
Level 4
Level 3
Interrupt
Controller
External
Interrupt
PCMCIA
Level 2
CPM
Level 1
Level 0
Debug
Debug
Figure 10-7. MPC885 Interrupt Structure
If programmed to generate interrupts, the software watchdog timer generates a nonmaskable system reset
interrupt (NMI) to the core. Asserting the external IRQ0 pin generates an NMI as well. Note that the core
takes the system reset interrupt vector when an NMI is asserted and jumps to the external interrupt vector
when any other interrupt is asserted by the interrupt controller. Each external IRQ pin is assigned a priority
level. Each SIU internal interrupt source, generated by the CPM’s interrupt controller (CPIC), can be
assigned by the software to one of eight additional internal interrupt priority levels, described in
Chapter 35, “CPM Interrupt Controller.”
Section 10.5.3.1, “Nonmaskable Interrupts—IRQ0 and SWT,” describes how IRQ0 operates differently
from other IRQ signals, and how the operation is configurable through SIU registers.
10.5.2
Priority of Interrupt Sources
There are seven external IRQ pins (IRQ0 is essentially nonmaskable, although in a limited sense it can be
masked as shown in Table 10-8, and IRQ5 is not an external interrupt pin but can be assigned to generate
an internal interrupt) and eight interrupt levels. Asserting IRQ0 causes an NMI. The other 15 interrupt
sources assert a single interrupt request to the core (the external interrupt). Table 10-7 shows interrupt
priorities.
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Table 10-7. Priority of SIU Interrupt Sources
Number
Priority Level
Interrupt Source
Interrupt Code
(SIVEC[INTC])
0
Highest
IRQ0
0000_0000
1
Internal Level 0
0000_0100
2
IRQ1
0000_1000
3
Internal Level 1
0000_1100
4
IRQ2
0001_0000
5
Internal Level 2
0001_0100
6
IRQ3
0001_1000
7
Internal Level 3
0001_1100
8
IRQ4
0010_0000
9
Internal Level 4
0010_0100
10
—
0010_1000
11
Internal Level 5
0010_1100
12
IRQ6
0011_0000
13
Internal Level 6
0011_0100
14
IRQ7
0011_1000
Internal Level 7
0011_1100
Reserved
—
15
Lowest
16-31
10.5.3
SIU Interrupt Processing
Figure 10-8 shows the general flow of SIU interrupt processing.
Start
SIU interrupt occurs
Set bit in SIPEND
Bit set in SIMASK
Assert external interrupt
to core
Bit not set in SIMASK
End
Figure 10-8. SIU Interrupt Processing
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10.5.3.1
Nonmaskable Interrupts—IRQ0 and SWT
Figure 10-9 is a logical representation of IRQ0.
SIEL[ED0]
SIEL[ED0]
MUX
MUX
Level
Level
NMI
IRQ0
Edge
FF
Q
Edge
Q
R
SIPEND[IRQ0]
SIPEND[IRQ0] = 1
Figure 10-9. IRQ0 Logical Representation
Table 10-8 describes the differences between IRQ0 and other IRQ interrupts.
Table 10-8. IRQ0 Versus IRQx Operation
Functionality
IRQ0
IRQx
Exception Vector
0x100
0x500
Core input
NMI
External interrupt
SIMASK
Not used, except for enabling SIVEC
Used for masking
SIVEC
Not normally used. If used, SIMASK[IRQ0] must Supplies the interrupt code so the core knows
be set.
the interrupt source.
SWT (software watchdog timer) interrupts behave similarly in that they jump to the system reset vector
(0x100). However, they are not affected by any interrupt controller registers.
Although NMI causes a jump to the system reset vector, no other reset action is taken. For information
about recoverability of NMI, see Section 6.1.5, “Recoverability After an Exception.”
10.5.4
Programming the SIU Interrupt Controller
The SIU’s interrupt controller includes the SIU interrupt pending register (SIPEND), SIU interrupt mask
register (SIMASK), SIU interrupt edge/level register (SIEL), and SIU interrupt vector register (SIVEC)
registers. These are described in the following sections.
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10.5.4.1
SIU Interrupt Pending Register (SIPEND)
SIU interrupt pending register (SIPEND) bits, shown in Figure 10-10, correspond to interrupt requests.
This register is affected by HRESET and SRESET.
0
1
2
3
4
5
6
7
8
9
Field IRQ0 LVL0 IRQ1 LVL1 IRQ2 LVL2 IRQ3 LVL3 IRQ4 LVL4
Reset
10
—
11
12
13
14
15
LVL5 IRQ6 LVL6 IRQ7 LVL7
0000_0000_0000_0000
R/W
R/W
Addr
(IMMR & 0xFFFF0000) + 0x010
16
31
Field
—
Reset
xxxx_xxxx_xxxx_xxxx
R/W
R/W
Addr
(IMMR & 0xFFFF0000) + 0x012
Figure 10-10. SIU Interrupt Pending Register (SIPEND)
Table 10-9 describes SIPEND fields.
Table 10-9. SIPEND Field Descriptions
Bits
Name
0, 2, 4,
6, 8, 12,
14
IRQ n
10
—
1, 3, 5,
7, 9, 11,
13, 15
LVLn
16–31
—
Description
Interrupt request 0–7. Indicate whether an edge-triggered interrupt is pending.
0 The appropriate interrupt is not pending.
1 The appropriate interrupt is pending.
Reserved
Level 0–7. When set, these bits indicate a pending level interrupt of corresponding value.
0 The appropriate interrupt is not pending.
1 The appropriate interrupt is pending.
Reserved, should be cleared.
The LVL[0–7] bits are associated with internal exceptions, and when set indicate that an interrupt service
is requested if they are not masked by the corresponding SIMASK bit. These bits reflect the status of the
internal requesting device and are cleared when the appropriate actions are software-initiated in the device.
Writing to LVLn bits has no effect.
The IRQ[0–7] bits are associated with the IRQ[0:7] signals, and their function depends on the sensitivity
defined for them in SIEL; see Section 10.5.4.3, “SIU Interrupt Edge/Level Register (SIEL).”
• When an IRQ pin is defined as a level interrupt (SIEL[EDn] = 0), the corresponding IRQ bit
behaves like an LVL bit.
• If an IRQ pin is defined as an edge interrupt (SIEL[EDn] = 1), the corresponding bit being set
indicates that a falling edge was detected on the line and are reset by writing ones to them.
Note that IRQ0 can be masked in only a very limited sense. If SIEL[ED0] = 1, edge-sensitive, and
SIPEND[IRQ0] is not cleared in the interrupt service routine, further assertions of IRQ0 are masked.
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10.5.4.2
SIU Interrupt Mask Register (SIMASK)
Bits in SIMASK correspond to the interrupt request bits in SIPEND. Setting SIMASK bits enable the
generation of interrupt requests to the core. SIMASK is updated by the software, which must determine
which interrupt sources are enabled at a given time. This register is affected by HRESET and SRESET.
.
0
1
2
3
4
5
6
7
8
9
Field IRM0 LVM0 IRM1 LVM1 IRM2 LVM2 IRM3 LVM3 IRM4 LVM4
Reset
10
—
11
12
13
14
15
LVM5 IRM6 LVM6 IRM7 LVM7
0000_0000_0000_0000
R/W
R/W
Addr
(IMMR & 0xFFFF0000) + 0x014
16
31
Field
—
Reset
xxxx_xxxx_xxxx_xxxx
R/W
R/W
Addr
(IMMR & 0xFFFF0000) + 0x016
Figure 10-11. SIU Interrupt Mask Register (SIMASK)
Table 10-10 describes SIMASK fields.
Table 10-10. SIMASK Field Descriptions
Bits
Name
Description
0
IRM0
Interrupt request mask 0. Enables/disables updating SIVEC[INTC]. IRQ0 generates an NMI
regardless of this bit.
1, 3, 5,
7, 9, 11,
13, 15
LVMn
Level mask 0–7. When set, these bits enable an internal interrupt request to be generated.
0 Disable generation of an interrupt request bit in SIPEND
1 Enable generation of an interrupt request bit in SIPEND
2, 4, 6,
8, 12,
14
IRM n
Interrupt request mask 1–7. When set, these bits enable an IRQ interrupt request to be
generated.
0 Disable generation of an interrupt request bit in SIPEND
1 Enable generation of an interrupt request bit in SIPEND
10
—
Reserved, should be cleared
16–31
—
Reserved, should be cleared.
The following procedure prevents possible interrupt errors when modifying mask registers, such as
SIMASK:
1. Clear MSR[EE]. (Disable external interrupts to the core.)
2. Modify the mask register.
3. Set MSR[EE]. (Enable external interrupts to the core.)
This mask modification procedure ensures that an already pending interrupt is not masked before being
serviced.
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10.5.4.3
SIU Interrupt Edge/Level Register (SIEL)
Bits in SIEL, shown in Figure 10-12, define interrupts as edge- or level-triggered. This register is affected
by HRESET but not by SRESET.
0
Field ED0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
–
ED1
–
ED2
–
ED3
–
ED4
–
—
–
ED6
–
ED7
–
Reset
0000_0000_0000_0000
R/W
R/W
Addr
(IMMR & 0xFFFF0000) + 0x018
16
31
Field
—
Reset
xxxx_xxxx_xxxx_xxxx
R/W
R/W
Addr
(IMMR & 0xFFFF0000) + 0x01A
Figure 10-12. SIU Interrupt Edge/Level Register (SIEL)
Table 10-11 describes SIEL fields.
Table 10-11. SIEL Field Descriptions
Bits
Name
0, 2, 4,
6, 8,
12, 14
EDn
1, 3, 5,
7, 9,
10, 11,
13, 15
_
Reserved, should be cleared.
16–31
—
Reserved, should be cleared.
10.5.4.4
Description
Edge detect 0–7.
0 A low logical level in the IRQ signal indicates an interrupt request.
1 A falling edge in the corresponding IRQ signal indicates interrupt request.
SIU Interrupt Vector Register (SIVEC)
The SIU interrupt vector register (SIVEC) is shown in Figure 10-13. This register is affected by HRESET
and SRESET.
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0
Field
7
8
INTC
15
—
Reset
xx11_11xx_xxxx_xxxx
R/W
R
Addr
(IMMR & 0xFFFF0000) + 0x01C
16
31
Field
—
Reset
xxxx_xxxx_xxxx_xxxx
R/W
R
Addr
(IMMR & 0xFFFF0000) + 0x01E
Figure 10-13. SIU Interrupt Vector Register (SIVEC)
Table 10-12 describes SIVEC fields.
Table 10-12. SIVEC Field Descriptions
Bits
Name
Description
0–7
INTC
Interrupt code. Indicates the highest priority pending interrupt; equals the interrupt number times 4,
as shown in Table 10-7.
8–31
—
Reserved, should be cleared.
SIVEC[INTC] represents the unmasked interrupt source of the highest priority level. When SIVEC is read
as a byte, a branch table can be used in which each entry contains one instruction (branch). The interrupt
code is the interrupt number times 4, which allows indexing into the table. When read as a half word, each
entry can contain a full routine of up to 256 instructions; see Figure 10-14 and Table 10-7.
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Intr: • • •
Intr: • • •
Save State
R3 <– @ SIVEC
R4 <– Base of Branch Table
Save State
R3 <– @ SIVEC
R4 <– Base of Branch Table
•••
•••
lbz
add
mtspr
bctr
# Load as Byte
Rx, R3 (0)
Rx, Rx, R4
CTR, Rx
lhz
add
mtspr
bctr
Base
b
Routine1
Base
Base + 4
b
Routine2
Base + 400
Base + 8
b
Routine3
Base + 800
Base + C
b
Routine4
Base + C00
Base + 10
•
Base + 1000
Base + n
•
Base + n
Rx, R3 (0)
Rx, Rx, R4
CTR, Rx
# Load as half word
1st Instruction of Routine1
•
1st Instruction of Routine2
•
1st Instruction of Routine3
•
1st Instruction of Routine4
•
•
•
•
•
Figure 10-14. Interrupt Table Handling Example
The interrupt to be serviced can be determined by reading SIVEC[INTC]. For example, if IRQ3, level 3,
and IRQ6 interrupts occur simultaneously and IRQ3 is masked, INTC = 0b0001_1100 (0x1C), indicating
that the level 3 interrupt should be handled.
Note that SIVEC[INTC] contains the encoding for a level-7 interrupt (see Table 10-7) by default, even
when no interrupts are pending. Thus, polling SIVEC when all interrupts are masked returns the level-7
vector. Therefore, the level-7 interrupt vector may indicate a spurious interrupt in the following cases:
• Polling SIVEC returns a level 7 interrupt, but nothing is programmed to interrupt at level 7.
• Polling SIVEC returns a level 7 interrupt, but SIPEND[LV7] is not set (assuming something is
programmed to interrupt at level 7).
10.6
The Bus Monitor
Control of the bus monitor is provided in the SYPCR. The bus monitor ensures that each bus cycle initiated
by the MPC885 terminates within a reasonable time. The MPC885’s bus monitor does not monitor
accesses initiated by external masters. At the start of the transfer start signal (TS), the monitor begins
counting and stops when transfer acknowledge (TA), retry (RETRY) or transfer error (TEA) is asserted.
For burst cycles, this action is also performed between subsequent TA assertions for each data beat. If the
monitor times out, the bus monitor terminates the cycle by internally asserting TEA. The programmability
of the timeout allows for a variation in system peripheral response time. The timing mechanism is clocked
by the system clock divided by eight. The maximum value is 2,040 system clocks. The bus monitor is
always active when FRZ is asserted or when a debug mode request is pending, regardless of the state of
the SYPCR[BME] bit.
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System Interface Unit
Note that if the bus monitor is disabled, transfer errors do not cause TEA to be asserted.
10.7
Software Watchdog Timer
The SIU provides the software watchdog timer (SWT) option that prevents system lockup when software
gets trapped in loops without a controlled exit. The software watchdog timer is enabled after HRESET to
automatically generate a HRESET if it times out. If the software watchdog timer is not needed, clear
SYPCR[SWE] to disable it. If it is used, the software watchdog timer requires a special service sequence
to be executed periodically; otherwise, the watchdog timer times out and issues a reset or an NMI, which
is programmed by SYPCR[SWRI]. Once SYPCR is written by the software, SYPCR[SWE] cannot be
changed. See Section 10.4.3, “System Protection Control Register (SYPCR).” To service the software
watchdog timer, follow these steps:
1. Write 0x556C to the software service register. (SWSR)
2. Write 0xAA39 to the SWSR.
This sequence clears the watchdog timer and the timing process repeats. If a value other than 0x556C or
0xAA39 is used, the entire sequence must start over. Although the writes must occur in the correct order
before a timeout occurs, any number of instructions may be executed between the writes. This allows
interrupts and exceptions to occur between the two writes when necessary. See Figure 10-15.
0x556C/Don’t reload
Reset
State 0
Waiting for 0x556C
State 1
Waiting for 0xAA39
0xAA39/Reload
Not 0x556C/Don’t reload
Not 0xAA39/Don’t reload
Figure 10-15. Software Watchdog Timer Service State Diagram
The decrementer begins counting when it is loaded with a value from the SWTC field. This value is then
loaded into a 16-bit down-counter clocked by the system clock. When necessary, an additional divide by
2,048 prescaler is used. After the timer reaches 0x0, a software watchdog expiration request is issued to
the reset or NMI control logic. At reset, the value in SWTC is set to the maximum value and is loaded into
the software watchdog down-counter, starting the process.
Although most software disciplines permit or encourage the watchdog concept, some systems require a
selection of timeout periods. For this reason, the software watchdog timer provides a selectable range for
the timeout period. Figure 10-16 shows the method for handling this need. When a new value is loaded
into SWTC, the software watchdog timer is not updated until the servicing sequence is written to SWSR.
If the SWE bit is loaded with a zero, the modulus counter will not count.
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System Interface Unit
SWSR
SWTC
Service
Logic
SWE
Reload
16-Bit
Down-counter
Clock
Disable
Core
Clock
Divide
by 2,048
Rollover = 0
MUX
HRESET
or NMI
Timeout
FRZ
SWP
Figure 10-16. Software Watchdog Timer Block Diagram
10.7.1
Software Service Register (SWSR)
The software service register (SWSR) is the location to which the software watchdog timer servicing
sequence writes. To prevent a SWT timeout, a write of 0x556C followed by 0xAA39 should be written to
this register. The SWSR can be written at any time, but returns all zeros when read. This register is affected
by HRESET and SRESET.
0
15
Field
SEQ
Reset
0000_0000_0000_0000
R/W
W
Addr
(IMMR & 0xFFFF0000) + 0x00E
Figure 10-17. Software Service Register (SWSR)
Table 10-13 describes SWSR fields.
Table 10-13. SWSR Field Descriptions
Bits
Name
Description
0–15
SEQ
Sequence. This field is the pattern that is used to control the state of the software watchdog timer.
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System Interface Unit
10.8
The Decrementer
A PowerPC-defined 32-bit decrementing counter supports the decrementer interrupt. In the MPC885, the
decrementer is clocked by TMBCLK, so TBSCR[TBE] must be set for the decrementer to start. The
timebase and decrementer counters are driven by TMBCLK:
T
32
2
= ----------------------------dec
(F
)
tmbclk
The state of the decrementer is not affected by HRESET and SRESET, so it should be initialized by
software. Note, however, that it is disabled and reset by PORESET. It continues counting while HRESET
and SRESET are asserted and it is implemented with the following requirements in mind.
•
•
•
The decrementer is unaffected when read.
When DEC[0] changes from 0 to 1, an interrupt request is signaled. If a previous decrementer
interrupt request was made, only one interrupt is reported.
Explicitly changing DEC[0] from 0 to 1 in software signals an interrupt request.
A decrementer exception causes a pending interrupt request in the core, which is cleared automatically
when the decrementer interrupt is taken, Table 10-14 shows some decrementer periods available,
assuming a 4-MHz oscillator.
Table 10-14. Decrementer Timeout Values
Count Value
Timeout
Count Value
Timeout
0
1 µs
999999
1.0 s
9
10. µs
9999999
10.0 s
99
100. µs
99999999
100.0 s
999
1.0 ms
999999999
1,000 s
9999
10.0 ms
FFFFFFFF (hex)
4,295 s
10.8.1
Decrementer Register (DEC)
The decrementer register (DEC) is an SPR as defined in the PowerPC architecture. It can be read or written
to by mfspr or mtspr. Control of the decrementer is provided in the TBSCR. The decrementer and
timebase use TMBCLK. Note that DEC is a keyed register. It must be unlocked in TBK before it can be
written.
0
31
Field
DEC
Reset
—
R/W
R/W
SPR
22
Figure 10-18. Decrementer Register (DEC)
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System Interface Unit
Table 10-15 describes the DEC register.
Table 10-15. DEC Field Descriptions
Bits
Name
Description
0–31
DEC
Decrementer. These bits are used by a down counter to cause decrementer interrupts. Reading
DEC always returns the current count value from the down counter.
10.9
Timebase
The timebase is a 64-bit free-running binary counter as defined in the PowerPC architecture. For the
MPC885, the timebase is clocked by TMBCLK. The timebase period is as follows:
T
TB
2 64
= ----------------------F
tmbclk
The timebase is unaffected by HRESET and SRESET and should be initialized by software. PORESET,
however, disables and resets the timebase. The entire timebase cannot be accessed with a single
instruction; mttb and mftb access the lower half of the timebase and mttbu and mftbu access the upper
half. A maskable interrupt is generated when the timebase count reaches a value programmed in one of the
reference registers, TBREFA and TBREFB; two status bits indicate which one caused the interrupt.
10.9.1
Timebase Register (TBU and TBL)
The timebase register (TB) holds a 64-bit integer that is incremented periodically. It is implemented in two
parts, time base upper and time base lower (TBU and TBL). There is no automatic initialization of TB,
therefore, system software must perform this initialization. The contents of TB can be written by mtspr
and read by mftb or mftbu instruction. Figure 10-19 shows TBU. Note that the TBU and TBL are keyed
registers. They must be unlocked in TBK before they can be written.
0
31
Field
TBU
Reset
—
R/W
R/W
SPR
269 (Read)/285 (Write)
Figure 10-19. Timebase Upper Register (TBU)
Table 10-16 describes TBU fields.
Table 10-16. TBU Field Descriptions
Bits
Name
0–31
TBU
Description
Timebase upper. The value in this field is used as an upper part of the timebase counter.
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System Interface Unit
Figure 10-20 shows TBL.
0
31
Field
TBL
Reset
—
R/W
R/W
SPR
268 (Read)/284 (Write)
Figure 10-20. Timebase Lower Register (TBL)
Table 10-17 describes TBL fields.
Table 10-17. TBL Field Descriptions
Bits
Name
0–31
TBL
10.9.2
Description
Timebase lower. The value in this field is used as the lower part of the timebase register.
Timebase Reference Registers (TBREFA and TBREFB)
TBREFA and TBREFB are associated with TBL. When the contents of TBL matches a reference register,
a reference event is signaled in TBSCR[REFA] or TBSCR[REFB]. These events can generate interrupts,
if enabled. Note that TBREFA and TBREFB are keyed registers. They must be unlocked in TBREFAK
and TBREFBK before they can be written.
0
15
Field
TBREFA/TBREFB
Reset
—
R/W
R/W
Addr
TBREFA (IMMR & 0xFFFF0000) + 0x204/TBREFB (IMMR & 0xFFFF0000) + 0x208
16
31
Field
TBREFA/TBREFB
Reset
—
R/W
R/W
Addr
TBREFA (IMMR & 0xFFFF0000) + 0x206/TBREFB (IMMR & 0xFFFF0000) + 0x20A
Figure 10-21. Timebase Reference Registers (TBREFA and TBREFB)
These registers are affected by HRESET but are not affected by SRESET. Table 10-18 describes
TBREFA/TBREFB fields.
Table 10-18. TBREFA/TBREFB Field Descriptions
Bits
Name
Description
0–31
TBREFA
Timebase reference A. Represents the 32-bit reference value for TBL.
0–31
TBREFB
Timebase reference B. Represents the 32-bit reference value for TBL
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System Interface Unit
10.9.3
Timebase Status and Control Register (TBSCR)
The timebase status and control register (TBSCR) controls the timebase count enable and interrupt
generation. It is also used for reporting the interrupt sources, and it can be read at any time. Status bits are
cleared by writing ones; writing zeros has no effect. Note that TBSCR is a keyed register. It must be
unlocked in TBSCRK before it can be written.
0
7
Field
TBIRQ
Reset
8
9
10
REFA REFB
11
—
12
13
14
REFAE REFBE TBF
15
TBE
0000_0000_0000_0000
R/W
R/W
Addr
(IMMR & 0xFFFF0000) + 0x200
Figure 10-22. Timebase Status and Control Register (TBSCR)
This register is affected by HRESET but is not affected by SRESET. Table 10-19 describes TBSCR fields.
Table 10-19. TBSCR Field Descriptions
Bits
Name
Description
0–7
TBIRQ
Timebase interrupt request. Determines interrupt priority level of the timebase. To specify a
certain level, the appropriate bit should be set.
8
REFA
9
REFB
Reference interrupt status. If set, indicates that a match was detected between the
corresponding reference register (TBREFA for REFA and TBREFB for REFB) and the TBL.
REFA and REFB are cleared by writing ones.
10–11
—
12
REFAE
13
REFBE
14
TBF
Timebase freeze enable
0 The timebase and decrementer are unaffected.
1 The FRZ signal stops the timebase and decrementer.
15
TBE
Timebase enable
0 Disables timebase and decrementer operation.
1 Enables timebase and decrementer operation.
Reserved, should be cleared.
Reference interrupt enable. If asserted, the timebase generates an interrupt on assertion of
REFA or REFB. Otherwise, the interrupt is disabled.
10.10 Periodic Interrupt Timer (PIT)
The PIT, shown in Figure 10-23, consists of a 16-bit counter clocked by a PITCLK clock supplied by the
clock module. The PIT is not affected by HRESET and RESET; however, it is disabled and reset by
PORESET. It decrements to zero when loaded with a value from the PIT count register (PITC) and after
the timer reaches zero, PS is set and an interrupt is generated if PIE is a 1. At the next input clock edge,
the PITC value is loaded into the counter and the process repeats. When a new value is loaded into PITC,
the PIT is updated, the divider is reset, and the counter starts counting. If the PS bit is set, an interrupt is
generated at the interrupt controller that remains pending until PS is cleared. If PS is set again, before being
cleared, the interrupt remains pending until PS is cleared. Any write to PITC stops the current countdown
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System Interface Unit
and the count resumes with a new value in the PITC. If the PTE bit is not set, the PIT is unable to count
and retains the old count value. Reading the PIT does not affect it.
PITCLK
Clock
PTE
PITC
Clock
Disable
16-Bit
Modulus Counter
PS
PIT
Interrupt
FRZ
PIE
Figure 10-23. Periodic Interrupt Timer Block Diagram
The time-out period is calculated as follows:
PIT
period
PITC + 1
PITC + 1
= ------------------------- = -----------------------------------------------------------F
ExternalClock⎞
⎛
pitclk
------------------------------------------ ÷ 4
⎝ 1 o or o 128 ⎠
10.10.1 Periodic Interrupt Status and Control Register (PISCR)
The periodic interrupt status and control register (PISCR), shown in Figure 10-24, contains the interrupt
request level and status bits. It also controls the 16 bits to be loaded in a modulus counter. Note that PISCR
is a keyed register. It must be unlocked in PISCRK before it can be written.
0
7
Field
PIRQ
8
9
PS
Reset
12
—
13
PIE
14
15
PITF PTE
0000_0000_0000_0000
R/W
R/W
Addr
(IMMR & 0xFFFF0000) + 0x240
Figure 10-24. Periodic Interrupt Status and Control Register (PISCR)
This register is affected by HRESET but is not affected by SRESET. Table 10-20 describes PISCR fields.
Table 10-20. PISCR Field Descriptions
Bits
Name
Description
0–7
PIRQ
8
PS
Periodic interrupt status. Can be cleared by writing a 1 to it (zero has no effect).
0 The PIT is unaffected.
1 The PIT has issued an interrupt.
9–12
—
Reserved, should be cleared.
Periodic interrupt request level. Configures internal interrupt levels for periodic interrupts.
Figure 10-7 shows interrupt request levels.
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System Interface Unit
Table 10-20. PISCR Field Descriptions (continued)
Bits
Name
Description
13
PIE
Periodic interrupt enable
0 Disables the PS bit.
1 Enables the PS bit to generate an interrupt.
14
PITF
PIT freeze enable
0 The PIT is unaffected by the FRZ signal.
1 The FRZ signal stops the PIT.
15
PTE
Periodic timer enable
0 The PIT is disabled.
1 The PIT is enabled.
10.10.2 PIT Count Register (PITC)
PITC, shown in Figure 10-25, contains a 16-bit value to be loaded into the periodic interrupt down counter.
Note that PITC is a keyed register. It must be unlocked in PITCK before it can be written.
0
15
Field
PITC
Reset
—
R/W
R/W
Addr
(IMMR & 0xFFFF0000) + 0x244
Bit
16
31
Field
—
Reset
0000_0000_0000_0000
R/W
R/W
Addr
(IMMR & 0xFFFF0000) + 0x246
Figure 10-25. PIT Count Register (PITC)
This register is not affected by HRESET or SRESET. Table 10-21 describes PITC fields.
Table 10-21. PITC Field Descriptions
Bits
Name
0–15
PITC
16–31
—
Description
PIT count. Contains the count for the periodic timer. Setting this field to 0xFFFF selects the
maximum count period.
Reserved, should be cleared.
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System Interface Unit
10.10.3 PIT Register (PITR)
The PIT register (PITR) is a read-only register that shows the current value in the periodic interrupt down
counter. Writes to PITR do not affect it; reads do not affect the counter.
0
15
Field
PIT
Reset
—
R/W
R
Addr
(IMMR & 0xFFFF0000) + 0x248
16
31
Field
—
Reset
-
R/W
R
Addr
(IMMR & 0xFFFF0000) + 0x24A
Figure 10-26. PIT Register (PITR)
Table 10-22 describes PITR fields.
Table 10-22. PITR Field Descriptions
Bits
Name
Description
0–15
PIT
Periodic interrupt timing count. Holds the current count remaining for the periodic timer. Writes do
not affect PIT.
16–31
—
Reserved, should be cleared.
10.11 General SIU Timers Operation
The following sections provide detailed information about the operation of the SIU timers.
10.11.1 Freeze Operation
The external FRZ signal is asserted as a result of entry into debug mode, or as a result of actions performed
by a software monitor debugger as described in Section 53.4.1, “Freeze Indication.” When the FRZ signal
is asserted, the clocks to the software watchdog, PIT, timebase counter, and decrementer can be disabled.
This is controlled by the associated bits in the control register of each timer. If they are programmed to
stop counting when FRZ is asserted, the counters maintain their values until FRZ is negated. The bus
monitor, however, will be enabled regardless of this signal’s state.
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Chapter 11
Reset
The reset block has reset control logic that determines the cause of reset, synchronizes it if necessary, and
resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller,
and parallel I/O signals are initialized only on hard reset. Soft reset initializes the internal logic while
maintaining the system configuration. The system configuration includes the SIU pin configuration, the
parallel I/O configuration, and the memory controller configuration. Table 11-1 shows the reset responses
of the MPC885.
Table 11-1. MPC885 Reset Responses
Reset Effect
Reset Logic
and PLL
States Reset
System
Configuration1
Reset
Clock
Module
Reset
HRESET
Driven
Debug
Port
Config
Other Internal
Logic2 Config
Reset
SRESET
Driven
Power-on reset
Yes
Yes
Yes
Yes
Yes
Yes
Yes
External hard
reset,
loss-of-lock,
software
watchdog,
checkstop, debug
port hard reset
No
No
No
No
Reset Source
JTAG reset,
external soft
reset, debug port
soft reset
1
2
Includes SIU pin configuration, the parallel I/O configuration and the memory controller configuration
Includes all other CPM and core logic not explicitly noted elsewhere in the table
11.1
Types of Reset
The MPC885 has several sources of input to the reset logic:
• Power-on reset
• External hard reset
• Internal hard reset
— Software watchdog reset
— Checkstop reset
— Debug port hard reset
• JTAG reset
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11-1
Reset
•
•
External soft reset
Internal soft reset
— Debug port soft reset
All of these reset sources are fed into the reset controller and, depending on the source of the reset, different
actions are taken. The reset status register reflects the last source to cause a reset.
11.1.1
Power-On Reset
Power-on reset of the MPC885 is accomplished through the PORESET input signal. The PORESET signal
must be externally asserted following initial power-up. When PORESET is asserted the MODCK bits are
sampled to configure SCCR[PTDIV] and SCCR[PTSEL]. The phase-locked loop multiplication factor is
configured for default operation in the PLPRCR register. When PORESET is negated, the MODCK values
are sampled and internally latched. To ensure proper operation, PORESET should be asserted for a
minimum of 3 µs. After sampling the assertion of PORESET, the MPC885 enters the power-on reset state
and stays there until both of the following events occur:
• The internal PLL enters the lock state and the system clock is active.
• PORESET is negated.
After the negation of PORESET or PLL lock, the core enters the state of internal initiated HRESET and
continues driving both HRESET and SRESET for 512 clock cycles. After 512 cycles elapse, the
MPC885’s configuration is sampled from the data signals and the core stops internally asserting both
HRESET and SRESET. To ensure prompt negation, external pull-up resistors should be provided to drive
HRESET and SRESET high. After HRESET and SRESET are internally negated, a 16-cycle period passes
before the presence of an external (hard/soft) reset is sampled. See Section 11.3.1, “Hard Reset,” for more
information.
11.1.2
External Hard Reset
The hard reset (HRESET) signal is a bidirectional, active low, open-collector I/O signal. The MPC885 can
only sample an external assertion of HRESET if it occurs while the MPC885 is not internally asserting
HRESET. While HRESET is asserted, SRESET is also asserted.
11.1.3
Internal Hard Reset
When the core initiates a hard reset it asserts the HRESET and SRESET signals for 512 cycles. After 512
clock cycles the data signals are sampled, initial configuration is established, and the core stops driving
the HRESET and SRESET signals. Following the negation of HRESET and SRESET a 16-cycle period
passes before an external hard or soft reset is sampled. Note that external pull-up resistors should be
provided to drive HRESET and SRESET high. See Section 11.3.1, “Hard Reset,” for more information.
The causes of internal hard reset are as follows:
• Software watchdog reset
• Checkstop reset
• Debug port hard reset
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Reset
The following sections describe the events that can initiate an internal assertion of HRESET and SRESET.
11.1.3.1
Software Watchdog Reset
When the core watchdog counter decrements to zero, a software watchdog reset is asserted generating an
internal hard reset sequence. Note that this is the default response; that is, an NMI to the core can be issued
instead of a hard reset, and the timer can be disabled. See Section 10.7, “Software Watchdog Timer.”
11.1.3.2
Checkstop Reset
If the core enters a checkstop state and PLPRCR[CSR] = 1, the checkstop reset is asserted generating an
internal hard reset sequence. See Section 14.6.2, “PLL and Reset Control Register (PLPRCR).”
11.1.4
Debug Port Hard or Soft Reset
When the development port receives a hard or soft reset request from a development tool, an internal hard
or soft reset sequence is generated. The development tool must reconfigure the debug port following a reset
event. See Section 53.3.2.1.2, “Development Serial Data In (DSDI).”
11.1.5
JTAG Reset
When the JTAG logic asserts the JTAG reset signal, an internal soft reset sequence is generated.
11.1.6
Power-On and Hard Reset Sequence
Figure 11-1 shows the reset sequence following a power-on or internal or external hard reset event.
Power On
Power-On
Reset
• Sample MODCK pins and initialize clocks
• HRESET and SRESET are asserted
PORESET is Negated and PLL Lock
Internal or External
HRESET Asserted
Internally
Initiated
HRESET
• HRESET and SRESET assert
• The time counter is set to 512
Timer Expires (After 512 Clocks)
External HRESET
Asserted
Wait
• Sample configuration from data pins
• Negate HRESET and SRESET
• Wait for 16 clocks
16 Clocks Expire
• Test for HRESET or SRESET
Start Normal Operation
(From system reset interrupt exception vector)
Figure 11-1. Power-On and Hard Reset Sequence
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Reset
11.1.7
External Soft Reset
When an external SRESET is asserted, the core starts driving the SRESET signal. After 512 clock cycles
the debug port configuration is sampled from the DSDI and DSCK signals and the core stops driving the
SRESET signal. Once the core negates SRESET 16 clock cycles must elapse before the external soft reset
signal is again sampled.
The soft reset (SRESET) signal is also a bidirectional, active low, open-collector I/O signal. The MPC885
can detect an external assertion of SRESET only if it occurs while the MPC885 is not internally asserting
HRESET or SRESET.
11.1.8
Internal Soft Reset
The JTAG and debug ports can initiate an internal soft reset, resulting in the assertion of the SRESET
signal. After 512 cycles, the core negates SRESET and the debug port configuration is sampled from the
DSDI and DSCK signals. Once the core negates SRESET, 16 clock cycles must elapse before the external
soft reset signal is sampled.
11.1.9
Soft Reset Sequence
Figure 11-2 shows the reset sequence following an internal or external soft reset event.
Internal or external
SRESET asserted
Internal initiated • SRESET assert
SRESET
• The time counter is set to 512
Timer expires (after 512 clocks)
• Sample debug port configuration from DSDI and DSCK pins
• Negate SRESET
• Wait for 16 clocks
Wait
16 clocks expire
& DSCK high
Debug
Mode
External SRESET still asserted
16 clocks expire
& DSCK low
• DSDI is sampled to determine
clocked or self-clocked mode
Test for
HRESET or
SRESET
Start normal execution
(From system reset interrupt exception vector)
Figure 11-2. Soft Reset Sequence
11.2
Reset Status Register (RSR)
The 32-bit reset status register (RSR) is memory-mapped into the MPC885 system interface unit register
map and receives its default reset values at power-on reset. This register is also affected by HRESET and
SRESET.
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11-4
Freescale Semiconductor
Reset
0
1
Field EHRS ESRS
2
—
3
4
5
6
7
8
SWRS CSRS DBHRS DBSRS JTRS
Reset
15
—
1100_0000_0000_0000
R/W
R/W
16
31
Field
—
Reset
0000_0000_0000_0000
R/W
R/W
Figure 11-3. Reset Status Register (RSR)
The RSR bits are described in Table 11-2. Note that the bits in this register (except those that are reserved)
are cleared by writing ones; writing zeros has no effect.
Table 11-2. Reset Status Register Bit Settings
Bits
Name
Description
0
EHRS
External hard reset status. Set by a power-on reset. When an external hard reset event is
detected, EHRS is set and remains set until software clears it.
0 No external hard reset event occurred.
1 An external hard reset event occurred.
1
ESRS
External soft reset status. Set by a power-on reset. When an external soft reset event is detected,
ESRS is set and remains set until software clears it.
0 No external soft reset event occurred.
1 An external soft reset event occurred.
2
—
3
SWRS
Software watchdog reset status. Cleared by a power-on reset. When a software watchdog expire
event occurs, SWRS is set and remains set until software clears it.
0 No software watchdog reset event occurred.
1 A software watchdog reset event occurred.
4
CSRS
Check stop reset status. Cleared by a power-on reset. When the core enters the checkstop state
and the checkstop reset is enabled by PLPRCR[CSR], CSRS is set and remains set until
software clears it.
0 No enabled checkstop reset event occurred.
1 An enabled checkstop reset event occurred.
5
DBHRS
Debug port hard reset status. Cleared by a power-on reset. When the debug port hard reset
request is set, DBHRS is set and remains set until software clears it.
0 No debug port hard reset request occurred.
1 A debug port hard reset request occurred.
6
DBSRS
Debug port soft reset status. Cleared by a power-on reset. When the debug port soft reset
request is set, DBSRS is set and remains set until software clears it.
0 No debug port soft reset request occurred.
1 A debug port soft reset request occurred.
Reserved
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
11-5
Reset
Table 11-2. Reset Status Register Bit Settings (continued)
Bits
Name
Description
7
JTRS
JTAG reset status. Cleared by a power-on reset. When the JTAG reset request is set, this bit is
set and remains set until software clears it.
0 No JTAG reset event occurred.
1 A JTAG reset event occurred.
8–31
—
11.3
Reserved, should be cleared.
MPC885 Reset Configuration
When a hard reset event occurs, the MPC885 reconfigures both its internal hardware and the development
port. A soft reset is used to reconfigure the development port without changing the MPC885’s internal
machine state. The following sections describe the configuration of the MPC885 using hard and soft reset
events.
11.3.1
Hard Reset
When a hard reset event occurs, the MPC885 determines its initial mode of operation by sampling the
values present on the data bus (D[0–31]) or from an internal default constant (D[0–31] = 0x00000000). If
the RSTCONF signal is asserted at sampling time, the configuration is sampled from the data bus. If the
RSTCONF signal is negated the internal default value is selected. While HRESET and RSTCONF are
asserted, the MPC885 weakly pulls the data bus low, and the desired configuration is selected by driving
the appropriate bits high as shown in Figure 11-4.
Figure 11-4 shows a typical data bus configuration input circuit.
Configuration
Word
MUX
DX (Data Line)
MPC885
MPC860
HRESET
RSTCONF
NOTE: The value of the internal pull-down resistor is not specified or guaranteed.
Figure 11-4. Data Bus Configuration Input Circuit
MPC885 PowerQUICC Family Reference Manual, Rev. 2
11-6
Freescale Semiconductor
Reset
The configuration of the MPC885 following the assertion of PORESET is shown in Figure 11-5 through
Figure 11-7. While the PORESET input signal is being asserted, the core assumes the default reset
configuration (0x0000_0000). When PORESET is negated or the CLKOUT signal begins oscillation, the
hardware configuration is sampled from the data bus every nine clock cycles on the rising edge of
CLKOUT. The setup time required for the data bus is 15 cycles, and the maximum rise time of HRESET
should be less than six clock cycles. Refer to Section 11.3.2, “Soft Reset,” for more information.
Figure 11-5 shows a reset operation with a short PORESET signal assertion. Note that the configuration
of the MPC885 is determined from the signal levels driven on the D[0–31] signals following the assertion
of RSTCONF and the negation of HRESET.
CLKOUT
PORESET
INTPORESET
HRESET
RSTCONF
TSUP
D[0:31]
Default
RSTCONF Controlled
Figure 11-5. Reset Configuration Sampling for Short PORESET Assertion
Figure 11-6 shows a reset operation with a long PORESET signal assertion.
CLKOUT
PORESET
INTPORESET
HRESET
RSTCONF
TSUP
D[0:31]
Default
RSTCONF Controlled
Figure 11-6. Reset Configuration Sampling for Long PORESET Assertion
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
11-7
Reset
Figure 11-7 shows the configuration data sampling timing relative to HRESET and CLKOUT.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLKOUT
HRESET
Maximum Time of
Reset Recognition
RSTCONF
Reset Configuration Word
Data
Maximum Setup Time of
Reset Recognition
Sample Data
Configuration
Sample Data
Configuration
Sample Data
Configuration
Figure 11-7. Reset Configuration Sampling Timing Requirements
11.3.1.1
Hard Reset Configuration Word
The hard reset configuration word is sampled from the data bus. These bits determine the default values
of the corresponding bits in the SIUMCR, IMMR, and MSR.
0
Field EARB
Default
1
IIP
2
3
BBE BDIS
4
5
BPS
6
—
7
8
ISB
9
10
DBGC
11
12
DBPC
13
14
EBDF
15
CLES
0000_0000_0000_0000
16
Field
31
—
Default
0000_0000_0000_0000
NOTE: The default value is due to the internal pull-down resistor on the data bus.
Figure 11-8. Hard Reset Configuration Word
Table 11-3 describes hard reset configuration word fields.
Table 11-3. Hard Reset Configuration Word Field Descriptions
Bits
Name
Description
0
EARB
External arbitration. If this bit is set, external arbitration is assumed; if cleared, internal arbitration is
performed. See Section 10.4.2, “SIU Module Configuration Register (SIUMCR).”
1
IIP
Initial interrupt prefix. Defines the initial value of the MSR[IP] which defines the interrupt table
location. If IIP is cleared (default), the MSR[IP] initial value is one; if it is set, the MSR[IP] initial value
is zero. See Section 4.1.2.3.1, “Machine State Register (MSR).”
MPC885 PowerQUICC Family Reference Manual, Rev. 2
11-8
Freescale Semiconductor
Reset
Table 11-3. Hard Reset Configuration Word Field Descriptions (continued)
Bits
Name
2
BBE
Boot Burst Enable
0 The boot device does not support bursting.
1 The boot device does support bursting.
3
BDIS
Boot disable. If BDIS is set, memory bank 0 is invalid; that is, BR0[V] is cleared. (See Section 15.4.1,
“Base Registers (BRx).”)
0 The memory controller is activated after reset so that it matches all addresses.
1 The memory controller is cleared after reset but is not activated.
4–5
BPS
Boot port size. Defines the port size of the boot device as shown in the following chart.
00 32-bit port size.
01 8-bit port size.
10 16-bit port size.
11 Reserved.
6
—
Reserved for future use and should be allowed to float.
7–8
ISB
Initial internal space base select. Defines the initial value of the IMMR bits 0-15 and determines the
base address of the internal memory space.
00 0x00000000.
01 0x00F00000.
10 0xFF000000.
11 0xFFF00000.
9–10
Description
DBGC Debug pin configuration. Selects the signal function of the following pins:
Pin
DBGC = 00
DBGC = 01
DBGC = 10
Reserved
DBGC = 11
IP_B[0–1]/IWP[0–1]/VFLS[0–1] IP_B[0–1]
IWP[0–1]
VFLS[0–1]
IP_B3/IWP2/VF2
IP_B3
IWP2
VF2
IP_B4/LWP0/VF0
IP_B4
LWP0
VF0
IP_B5/LWP1/VF1
IP_B5
LWP1
VF1
OP2/MODCK1/STS
OP2
STS
STS
ALE_B/DSCK/AT1
ALE_B
AT1
AT1
IP_B2/IOIS16_B/AT2
IP_B2
AT2
AT2
IP_B6/DSDI/AT0
IP_B6
AT0
AT0
IP_B7/PTR/AT3
IP_B7
AT3
AT3
OP3/MODCK2/DSDO
OP3
OP3
OP3
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Freescale Semiconductor
11-9
Reset
Table 11-3. Hard Reset Configuration Word Field Descriptions (continued)
Bits
Name
11–12
DBPC
Description
Debug port pins configuration. Selects the signal function for the following development port pins:
Pin
ALE_B/DSCK/AT1
IP_B6/DSDI/AT0
DBPC = 00
DBPC = 01
DBPC = 10
Reserved
Defined by DBGC.
Note that if DBPC = 11, DBPC
overrides DBGC.
DBPC = 11
DSCK
DSDI
OP3/MODCK2/DSDO
DSDO
IP_B7/PTR/AT3
PTR
TCK/DSCK
DSCK
TCK
TCK
TDI/DSDI
DSDI
TDI
TDI
TDO/DSDO
DSDO
TDO
TDO
13–14
EBDF
External bus division factor. Defines the frequency division factor between GCLK1/GCLK2 and
GCLK1_50/GCLK2_50. CLKOUT is similar to GCLK2_50. GCLK2_50 and GCLK1_50 are used by
the system interface unit and memory controller to interface with the external system. Refer to
Chapter 14, “Clocks and Power Control,” for additional information.
00 CLKOUT is GCLK2 divided by 1, Full Speed Bus.
01 CLKOUT is GCLK2 divided by 2, Half Speed Bus.
10 Reserved
11 Reserved
15
CLES
Core Little Endian Swap. Defines core access operation following reset.
0 Big Endian
1 Little Endian
11.3.2
Soft Reset
When a soft reset event occurs, the MPC885 reconfigures the development port. See Section 53.3.1.2,
“Entering Debug Mode,” and Section 53.3.2.3.3, “Selection of Development Port Clock Mode.”
11.4
TRST Considerations
Note the following when connecting the TRST (test reset) signal:
• If TAP is never used, connect TRST to ground.
• If TAP is used, connect TRST to PORESET.
See also Section 54.6, “Recommended TAP Configuration.”
MPC885 PowerQUICC Family Reference Manual, Rev. 2
11-10
Freescale Semiconductor
Part IV
Hardware Interface
Intended Audience
This part is intended for system designers who need to understand how each MPC885 signal works and
how those signals interact.
Contents
This part describes external signals, clocking, memory control, and power management of the MPC885.
It contains the following chapters:
• Chapter 12, “External Signals,” provides a detailed description of the external signals that
comprise the MPC885 external interface.
• Chapter 13, “External Bus Interface,” describes interactions among signals described in the
previous chapter, including numerous examples and timing diagrams.
• Chapter 14, “Clocks and Power Control,” describes on-chip and external devices, including the
phase-locked loop circuitry and frequency dividers that generate programmable clock timing for
baud-rate generators and timers.
• Chapter 15, “Memory Controller,” describes the memory controller, which controlling a maximum
of eight memory banks shared between a general-purpose chip-select machine (GPCM) and a pair
of user-programmable machines (UPMs).
• Chapter 16, “PCMCIA Interface,” describes the PCMCIA host adapter module, which provides all
control logic for a PCMCIA socket interface and requires only additional external analog power
switching logic and buffering.
Suggested Reading
This section lists additional reading that provides background for the information in this manual.
MPC8xx Documentation
Supporting documentation for the MPC885 can be accessed through the world-wide web at
http://www.freescale.com. This documentation includes technical specifications, reference materials, and
detailed applications notes.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
IV-1
Conventions
This document uses the following notational conventions:
Bold entries in figures and tables showing registers and parameter RAM should
Bold
be initialized by the user.
mnemonics
Instruction mnemonics are shown in lowercase bold.
italics
Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
0x0
Prefix to denote hexadecimal number
0b0
Prefix to denote binary number
REG[FIELD]
Abbreviations or acronyms for registers or buffer descriptors are shown in
uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For
example, MSR[LE] refers to the little-endian mode enable bit in the machine state
register.
x
In certain contexts, such as in a signal encoding or a bit field, indicates a do not
care.
n
Indicates an undefined numerical value
¬
NOT logical operator
&
AND logical operator
|
OR logical operator
Acronyms and Abbreviations
Table IV-1 contains acronyms and abbreviations used in this document. Note that the meanings for some
acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not
be intuitively obvious.
Table IV-1. Acronyms and Abbreviated Terms
Term
Meaning
BD
Buffer descriptor
BIST
Built-in self test
BRI
Basic rate interface
BUID
Bus unit ID
CAM
Content-addressable memory
CPM
Communications processor module
CRC
Cyclic redundancy check
DMA
Direct memory access
DPLL
Digital phase-locked loop
DRAM
Dynamic random access memory
MPC885 PowerQUICC Family Reference Manual, Rev. 2
IV-2
Freescale Semiconductor
Table IV-1. Acronyms and Abbreviated Terms (continued)
Term
DSISR
EA
EEST
GCI
Meaning
Register used for determining the source of a DSI exception
Effective address
Enhanced Ethernet serial transceiver
General circuit interface
GPCM
General-purpose chip-select machine
HDLC
High-level data link control
I2C
Inter-integrated circuit
IDL
Inter-chip digital link
IEEE
Institute of Electrical and Electronics Engineers
IrDA
Infrared Data Association
ISDN
Integrated services digital network
JTAG
Joint Test Action Group
LIFO
Last-in-first-out
LRU
Least recently used
LSB
Least-significant byte
lsb
Least-significant bit
LSU
Load/store unit
MAC
Multiply accumulate
MMU
Memory management unit
MSB
Most-significant byte
msb
Most-significant bit
MSR
Machine state register
NMSI
Nonmultiplexed serial interface
OSI
Open systems interconnection
PCI
Peripheral component interconnect
PCMCIA
Personal Computer Memory Card International Association
PRI
Primary rate interface
Rx
Receive
SCC
Serial communications controller
SCP
Serial control port
SDLC
Synchronous data link control
SDMA
Serial DMA
SI
Serial interface
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
IV-3
Table IV-1. Acronyms and Abbreviated Terms (continued)
Term
Meaning
SIU
System interface unit
SMC
Serial management controller
SNA
Systems network architecture.
SPI
Serial peripheral interface
SPR
Special-purpose register
SRAM
Static random access memory
TDM
Time-division multiplexed
TLB
Translation lookaside buffer
TSA
Time-slot assigner
Tx
Transmit
UART
Universal asynchronous receiver/transmitter
UISA
User instruction set architecture
UPM
User-programmable machine
USART
Universal synchronous/asynchronous receiver/transmitter
MPC885 PowerQUICC Family Reference Manual, Rev. 2
IV-4
Freescale Semiconductor
Chapter 12
External Signals
This chapter contains descriptions of the MPC885 input and output signals, showing multiplexing, pin
assignments, and reset values.
12.1
MPC885/MPC880 Signals
The following sections describe the signals, pin numbers, and signal descriptions.
12.1.1
MPC885/MPC880 Signals and Pin Numbers
Figure 12-1 and Figure 12-2 show the MPC885 signals and pin numbers.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-1
External Signals
VDDSYN/VSSSYN /VSSSYN1/VDDH /VDDL/GND
USBRXD/PA15
USBOE/PA14
RxD2/PA13
TxD2/PA12
RXD4/MII1-TXD0/RMII1-TXD0/PA11
MII-TXER/TIN4/CLK7/PA10
L1TXDA/RXD3/PA9
L1RxDA/TXD3/PA8
TIN1/L1RCLKA/BRGO1/CLK1/PA7
TOUT1/CLK2/PA6
TIN2/L1TCLKA/BRGO2/CLK3/PA5
CTS4/MII1-TXD1/RMII1-TXD1/PA4
MII1-RXER/RMII1-RXER/BRGO3/PA3
MII1-RXDV/RMII1-CRS_DV/TXD4/PA2
MII1-RXD0/RMII1-RXD0/BRGO4/PA1
MII1-RXD1/RMII1-RXD1/TOUT4/PA0
MII1-TXCLK/RMII1-REFCLK/SPISEL/PB31
SPICLK/PB30
SPIMOSI/PB29
BRGO4/SPIMISO/PB28
BRGO1/I2CSDA/PB27
BRGO2/I2CSCL/PB26
SMTxD1/RXADDR3/TXADDR3/PB25
SMRxD1/RXADDR3/TXADDR3/PB24
SMSYN1/SDACK1/RXADDR2/TXADDR2/PB23
SMSYN2/SDACK2/RXADDR4/TXADDR4/PB22
PHSEL[1]/SMTxD2/BRGO1/RXADDR1/TXADDR1/PB21
PHSEL[0]/SMRxD2/L1CLKOA/RXADDR0/TXADDR0/PB20
MII1-RXD3/RTS4/PB19
L1ST2/RTS2/RXADDR4/TXADDR4/PB18
PHREQ[1]/L1ST3/BRGO2/RXADDR1/TXADDR1/PB17
PHREQ[0]/L1ST4/L1RQA/RTS4/RXADDR0/TXADDR0/PB16
RXCLAV/TXCLAV/BRG03/PB15
RXADDR2/TXADDR2/PB14
L1ST1/RTS3/DREQ0/RXCLAV/TXCLAV/PC15
L1ST2/RTS2/DREQ1/PC14
MII1-TXD3/SDACK1/PC13
MII1-TXD2/TOUT1/PC12
USBRXP/PC11
TGATE1/USBRXN/PC10
CTS2/PC9
TGATE2/CD2/PC8
CTS4/USBTXP/L1TSYNCB/PC7
CD4/USBTXN/L1RSYNCB/PC6
CTS3/SDACK2/L1TSYNCA/PC5
CD3/L1RSYNCA/PC4
UTPB[0]/L1TSYNCA/PD15
UTPB[1]/L1RSYNCA/PD14
UTPB[2]/L1TSYNCB/PD13
UTPB[3]/L1RSYNCB/PD12
RXENB/RxD3/PD11
TXENB/ TxD3/PD10
UTPCLK/TxD4/PD9
MII-MDC/RMII-MDC/RxD4/PD8
UTPB[4]/RTS3/PD7
UTPB[5]/ RTS4/PD6
UTPB[6]/ CLK8/L1TCKB/PD5
UTPB[7]/CLK4/PD4
SOC/CLK7/TIN4/PD3
TMS
DSDI/TDI
DSCK/TCK
TRST
DSDO/TDO
AS
125
1–N16
1–P17
1–W11
1–P16
1–W9
1–W17
1–T15
1–W15
1–V14
1–U13
1–W13
1–U4
1–W2
1–T4 MPC885
1–U1
1–U3
1–V3
1–P18
1–T19
1–V19
1–U19
1–R17
1–V17
1–U16
1–W16
1–V15
1–U14
1–T13
1–V13
1–T12
1–W12
1–V11
1–U10
1–U18
1–R19
1–R18 U9–1
1–V10 W7–1
1–T18 T8–1
1–V16 V5–1
1–U15 V4–1
1–T14
1–W14 T1–1
1–V12
1–U11 T3–1
1–T10 V8–1
1–W10 V2–1
1–U8
V1–1
1–U7
1–U6
1–U5 V9–1
1–R2
R4–1
1–T2
1–U2
1–R3 T6–1
1–W3
R1–1
1–W5
1–V6
1–W4 W8–1
1–T9 T7–1
1–V18
1–T16 W6–1
1–U17
V7–1
1–W18
1–T17
1–D7
B2–VDDLSYN
E4–VSSSYN
C2–VSSSYN1
E7–VDDH
E8
E10
E5–VDDL
E12
E6
E13
E9
E15
E11
F5-F15
E14
G5
G15
G14
H5
H6
J5
H15
J15
J6
K15
J14
L5
K5
M15
N5
K6
R6
K14
R9
L6
R10
L14
R12
L15
R15
M5
M6
M14
N6
N15
P5
G6-G13 - GND
P6
H7-H14
P8-P12
J7-J13
P14
K7-K13
P15
L7-L13
R5
M7-M13
R7
N7-N14
R8
P7
R11
P13
R13
R16
R14
PE31/CLK8/L1TCLKB/MII-RXCLK
PE30/L1RXDB/MII1-RXD2
PE29/MII2-CRS
PE28/TOUT3/MII2-COL
PE27/RTS3/L1RQB/MII2-RXER/
RMII2-RXER
PE26/L1CLKOB/MII2-RXDV/
RMII2-CRS_DV
PE25/RXD4/MII2-RXD3/L1ST2
PE24/SMRXD1/BRGO1/MII2-RXD2
PE23/SMSYN2/TXD4/MII2-RXCLK/
L1ST1
PE22/TOUT2/MII2-RXD1/
RMII2-RXD1/SDACK1
PE21/SMRXD2/TOUT1/MII2-RXD0/
RMII2-RXD0/RTS3
PE20/L1RSYNCA/SMTXD2/
CTS3/MII2-TXER
PE19/L1TXDB/MII2-TXEN/
RMII2-TXEN
PE18/L1TSYNCA/SMTXD1/
MII2-TXD3
PE17/TIN3/CLK5/BRG03/
SMSYN1/MII2-TXD2
PE16/L1RCLKB/CLK6/TXD3/
MII2-TXCLK/RMII2-REFCLK
PE15/TGATE1/MII2-TXD1/RMII2-TXD1
PE14/RXD3/MII2-TXD0/RMII2-TXD0
Figure 12-1. MPC885 Signals and Pin Numbers (Part 1)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-2
Freescale Semiconductor
External Signals
A0–M16
A1–N18
A2–N19
A3–M19
A4–M17
A5–M18
A6–L16
A7–L19
A8–L17
A9–L18
A10–K19
A11–K18
A12–K17
A13–K16
A14–J19
A15–J17
A16–J18
A17–J16
A18–E19
A19–H18
A20–H17
A21–G19
A22–F17
A23–G17
A24–H16
A25–F19
A26–D19
A27–H19
A28–E18
A29–G18
A30–F18
A31–D18
D0–P2
D1–M1
D2–L1
D3–K2
D4–N1
D5–K4
D6–H3
D7–F2
D8–P1
D9–L4
D10–L3
D11–L2
D12–N3
D13–N2
D14–K3
D15–K1
D16–J2
D17–M4
D18–J1
D19–J3
D20–H2
D21–H1
D22–J4
D23–M3
D24–G2
D25–G1
D26–G3
D27–M2
D28–H4
D29–F1
D30–E1
D31–F3
MII1_CRS
MII1_COL
MII_MDIO
MII1_TXEN
32
G16–1
E17–1
D13–1
C10–1
A13–1
A12–1
C12–1
B12–1
D12–1
B10–1
C7–1
A11–1
32
D11–1
C11–1
B11–1
D10–1
N4,P3–2
P4–1
6
D15–1
B16–1
B18–1
E16–1
C17–1
B19–1
D17,C18,C19,F16–4
B17–1
A18–1
D16, A17–2
B13–1
MPC885
A14–1
C13–1
B3–1
D4–1
B4–1
A3–1
A4–1
D5–1
G4–1
A5–1
C4–1
B7–1
B15–1
C15–1
A2–1
B1, C1–2
F4–1
E3, D2, D1, E2, D3–5
D8–1
C3–1
A9, D9–2
T11-1
C8–1
U12-1
C9–1
B9–1
P19-1
A10–1
T5-1
A8–1
B8–1
B6, C6–2
D6–1
A6–1
A7–1
C5, B5–2
A[0:31]
TSIZ0/REG
TSIZ1
RD/WR
BURST
BDIP/GPL_B5
TS
TA
TEA
BI
IRQ2/RSV
IRQ4/KR/RETRY/SPKROUT
CR/IRQ3
D[0:31]
BR
BG
BB
FRZ/IRQ6
IRQ[0:1]
IRQ7
CS[0:5] – B14,C14,A15,D14,C16,A16
CS6/CE1_B
CS7/CE2_B
WE0/BS_B0/IORD
WE1/BS_B1/IOWR
WE2/BS_B2/PCOE
WE3/BS_B3/PCWE
BS_A[0:3]
GPL_A0/GPL_B0
OE/GPL_A1/GPL_B1
GPL_A[2:3]/GPL_B[2:3]/CS[2:3]
UPWAITA/GPL_A4
UPWAITB/GPL_B4
GPL_A5
PORESET
RSTCONF
HRESET
SRESET
XTAL
EXTAL
CLKOUT
EXTCLK
TEXP
ALE_A
CE1_A
CE2_A,
WAIT_A/ SOC_Split
IP_A[0:1]/ UTPB_Split[0:1]
IP_A2/IOIS16_A/UTPB_Split2
E3–IP_A3/UTPB_Split3
ALE_B/DSCK/AT1
D2–IP_A4/UTPB_Split4
WAIT_B
D1–IP_A5/UTPB_Split5
IP_B[0:1]/WP[0:1]/VFLS[0:1] E2–IP_A6/UTPB_Split6
IP_B2/IOIS16_B/AT2
D3–IP_A7/UTPB_Split7
IP_B3/WP2/VF2
IP_B4/LWP0/VF0
IP_B5/LWP1/VF1
IP_B6/DSDI/AT0
IP_B7/PTR/AT3
B6-–OP0/UtpClk_Split
OP2/MODCK1/STS C6–OP1
OP3/MODCK2/DSDO
BADDR30/REG
BADDR[28:29]
Figure 12-2. MPC885 Signals and Pin Numbers (Part 2)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-3
External Signals
12.1.2
MPC885/MPC880 System Bus Signals
The MPC885 system bus consists of all signals that interface with the external bus. Many of these signals
perform different functions, depending on how the user assigns them. The input and output signals in
Table 12-1 are identified by their abbreviation.
Table 12-1. MPC885/MPC880 Signal Descriptions
Name
Hard
Reset
Number
Type
Description
A[0:31]
Hi-Z
TSIZ0
REG
Hi-Z
G16
Bidirectional Transfer Size 0—When accessing a slave in the external bus,
three-state used (together with TSIZ1) by the bus master to indicate the
number of operand bytes waiting to be transferred in the current
bus cycle. TSIZ0 is an input when an external master starts a bus
transaction.
Register—When an internal master initiates an access to a slave
controlled by the PCMCIA interface, REG is output to indicate
which space in the PCMCIA card is accessed.
TSIZ1
Hi-Z
E17
Bidirectional Transfer Size 1—Used (with TSIZ0) by the bus master to indicate
three-state the number of operand bytes waiting to be transferred in the
current bus cycle. The MPC885 drives TSIZ1 when it is bus
master. TSIZ1 is input when an external master starts a bus
transaction.
RD/WR
Hi-Z
D13
Bidirectional Read/Write—Driven by a bus master to indicate the direction of
three-state the data transfer. A logic one indicates a read from a slave device
and a logic zero indicates a write to a slave device.
The MPC885 drives this signal when it is a bus master. This
signal is input when an external master initiates a transaction on
the bus.
BURST
Hi-Z
C10
Bidirectional Burst Transaction—Driven by the bus master to indicate that the
three-state current initiated transfer is a burst. The MPC885 drives this signal
when it is bus master. This signal is input when an external
master initiates a transaction on the bus.
BDIP
GPL_B5
See
Table 12-3
A13
Hi-Z
A12
TS
See
Bidirectional Address Bus—Provides the address for the current bus cycle. A0
Figure 12-2 three-state is the msb. The bus is output when an internal master starts a
transaction on the external bus. The bus is input when an external
master starts a transaction on the bus.
Output
Burst Data in Progress—When accessing a slave device in the
external bus, the master on the bus asserts this signal to indicate
that the data beat in front of the current one is the one requested
by the master. BDIP is negated before the expected last data beat
of the burst transfer.
General-Purpose Line B5—Used by the memory controller when
UPMB takes control of the slave access.
Bidirectional Transfer Start—Asserted by a bus master to indicate the start of
a bus cycle that transfers data to or from a slave device.
active
Driven by the master only when it has gained the ownership of the
pull-up
bus. Every master should negate this signal before the bus
relinquishes. TS requires the use of an external pull-up resistor.
The MPC885 samples TS when it is not the external bus master
to allow the memory controller/PCMCIA interface to control the
accessed slave device. It indicates that an external synchronous
master initiated a transaction.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-4
Freescale Semiconductor
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
TA
Hi-Z
C12
Bidirectional Transfer Acknowledge—Indicates that the slave device
addressed in the current transaction accepted data sent by the
active
master (write) or has driven the data bus with valid data (read).
pull-up
This is an output when the PCMCIA interface or memory
controller controls the transaction. The only exception occurs
when the memory controller controls the slave access by means
of the GPCM, and the corresponding option register is instructed
to wait for an external assertion of TA. Every slave device should
negate TA after a transaction ends and immediately three-state it
to avoid bus contention if a new transfer is initiated addressing
other slave devices. TA requires the use of an external pull-up
resistor.
TEA
Hi-Z
B12
Open-drain
BI
Hi-Z
D12
Bidirectional Burst Inhibit—Indicates that the slave device addressed in the
current burst transaction cannot support burst transfers. It acts as
active
an output when the PCMCIA interface or the memory controller
pull-up
takes control of the transaction. BI requires the use of an external
pull-up resistor.
RSV
IRQ2
See
Table 12-3
B10
Bidirectional Reservation—The MPC885 outputs this three-state signal with
three-state the address bus to indicate that the core initiated a transfer as a
result of a stwcx. or lwarx.
Interrupt Request 2—One of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core.
KR/RETRY
IRQ4
SPKROUT
See
Table 12-3
C7
Bidirectional Kill Reservation—Input used as a part of the memory reservation
three-state protocol, when the MPC885 initiated a transaction as the result of
a stwcx. instruction. Retry—Input used by a slave device to
indicate it cannot accept the transaction. The MPC885 must
relinquish mastership and reinitiate the transaction after winning
in the bus arbitration.
Interrupt Request 4—One of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core. SPKROUT—Digital audio wave form output
to be driven to the system speaker.
CR
IRQ3
Hi-Z
A11
D[0:31]
Hi-Z1
Name
Type
Input
Description
Transfer Error Acknowledge—Indicates that a bus error occurred
in the current transaction. The MPC885 asserts TEA when the
bus monitor does not detect a bus cycle termination within a
reasonable amount of time. Asserting TEA terminates the bus
cycle, thus ignoring the state of TA. TEA requires the use of an
external pull-up resistor.
Cancel Reservation—Input used as a part of the storage
reservation protocol.
Interrupt Request 3—One of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core.
See
Bidirectional Data Bus—Bidirectional three-state bus, provides the
Figure 12-2 three-state general-purpose data path between the MPC885 and all other
devices. The 32-bit data path can be dynamically sized to support
8-, 16-, or 32-bit transfers. D0 is the msb of the data bus.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-5
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
BR
Hi-Z
D11
Bidirectional Bus Request—Asserted low when a possible master is
requesting ownership of the bus. When the MPC885 is
configured to work with the internal arbiter, this signal is
configured as an input. When the MPC885 is configured to work
with an external arbiter, this signal is configured as an output.
BG
Hi-Z
C11
Bidirectional Bus Grant—Asserted low when the arbiter of the external bus
grants the bus to a specific device. When the MPC885 is
configured to work with the internal arbiter, BG is configured as
an output and asserted every time the external master asserts
BR and its priority request is higher than any internal sources
requiring a bus transfer. However, when the MPC885 is
configured to work with an external arbiter, BG is an input.
BB
Hi-Z
B11
Bidirectional Bus Busy—Asserted low by a master to show that it owns the
bus. The MPC885 asserts BB after the arbiter grants it bus
active
pull-up
ownership and BB is negated.
FRZ
IRQ6
See
Table 12-3
D10
Bidirectional Freeze—Output asserted to indicate that the core is in debug
mode.
Interrupt Request 6—One of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core.
IRQ0
Hi-Z
N4
Input
Interrupt Request 0—One of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core.
IRQ1
Hi-Z
P3
Input
Interrupt Request 1—One of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core.
IRQ7
Hi-Z
P4
Input
Interrupt Request 7—One of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core.
CS[0:5]
High
B14, C14,
A15, D14,
C16, A16
Output
Chip Select—These outputs enable peripheral or memory
devices at programmed addresses if they are appropriately
defined. CS0 can be configured to be the global chip-select for
the boot device.
CS6
CE1_B
High
D15
Output
Chip Select 6—This output enables a peripheral or memory
device at a programmed address if defined appropriately in the
BR6 and OR6 in the memory controller.
Card Enable 1 Slot B—This output enables even byte transfers
when accesses to the PCMCIA slot B are handled under the
control of the PCMCIA interface.
CS7
CE2_B
High
B16
Output
Chip Select 7—Output that enables a peripheral or memory
device at a programmed address if defined appropriately in the
BR7 and OR7 in the memory controller.
Card Enable 2 Slot B—Output that enables odd byte transfers
when accesses to the PCMCIA slot B are handled under the
control of the PCMCIA interface.
Name
Type
Description
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-6
Freescale Semiconductor
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
Type
Description
WE0
BS_B0
IORD
High
B18
Output
Write Enable 0—Output asserted when a write access to an
external slave controlled by the GPCM is initiated by the
MPC885. WE0 is asserted if D[0:7] contains valid data to be
stored by the slave device.
Byte Select 0 on UPMB—Output asserted under control of
UPMB, as programmed by the user. In a read or write transfer, the
line is only asserted if D[0:7] contains valid data.
I/O Device Read—Output asserted when the MPC885 starts a
read access to a region controlled by the PCMCIA interface.
Asserted only for accesses to a PC card I/O space.
WE1
BS_B1
IOWR
High
E16
Output
Write Enable 1—Output asserted when the MPC885 initiates a
write access to an external slave controlled by the GPCM. WE1
is asserted if D[8:15] contains valid data to be stored by the slave
device.
Byte Select 1 on UPMB—Output asserted under control of
UPMB, as programmed by the user. In a read or write transfer, the
line is only asserted if D[8:15] contains valid data.
I/O Device Write—Output asserted when the MPC885 initiates a
write access to a region controlled by the PCMCIA interface.
IOWR is asserted only if the access is to a PC card I/O space.
WE2
BS_B2
PCOE
High
C17
Output
Write Enable 2—Output asserted when the MPC885 starts a
write access to an external slave controlled by the GPCM. WE2
is asserted if D[16:23] contains valid data to be stored by the
slave device.
Byte Select 2 on UPMB—Output asserted under control of
UPMB, as programmed by the user. In a read or write transfer,
BS_B2 is asserted only if D[16:23] contains valid data.
PCMCIA Output Enable—Output asserted when the MPC885
initiates a read access to a memory region under the control of
the PCMCIA interface.
WE3
BS_B3
PCWE
High
B19
Output
Write Enable 3—Output asserted when the MPC885 initiates a
write access to an external slave controlled by the GPCM. WE3
is asserted if D[24:31] contains valid data to be stored by the
slave device.
Byte Select 3 on UPMB—Output asserted under control of
UPMB, as programmed by the user. In a read or write transfer,
BS_B3 is asserted only if D[24:31] contains valid data.
PCMCIA Write Enable—Output asserted when the MPC885
initiates a write access to a memory region under control of the
PCMCIA interface.
BS_A[0:3]
High
D17, C18,
C19, F16
Output
Byte Select 0 to 3 on UPMA—Outputs asserted under
requirement of UPMA, as programmed by the user. For read or
writes, asserted only if their corresponding data lanes contain
valid data:
BS_A0 for D[0:7], BS_A1 for D[8:15],
BS_A2 for D[16:23], BS_A3 for D[24:31]
Name
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-7
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
Type
Description
GPL_A0
GPL_B0
High
B17
Output
General-Purpose Line 0 on UPMA—Output reflecting the value
specified in UPMA when an external transfer to a slave is
controlled by UPMA
General-Purpose Line 0 on UPMB—Output reflecting the value
specified in UPMB when an external transfer to a slave is
controlled by UPMB
OE
GPL_A1
GPL_B1
High
A18
Output
Output Enable—Output asserted when the MPC885 initiates a
read access to an external slave controlled by the GPCM.
General-Purpose Line 1 on UPMA—Output reflecting the value
specified in UPMA when an external transfer to a slave is
controlled by UPMA.
General-Purpose Line 1 on UPMB—Output reflecting the value
specified in UPMB when an external transfer to a slave is
controlled by UPMB.
GPL_A[2:3]
GPL_B[2:3]
CS[2:3]
High
D16, A17
Output
General-Purpose Line 2 and 3 on UPMA— outputs reflecting the
value specified in UPMA when an external transfer to a slave is
controlled by UPMA.
General-Purpose Line 2 and 3 on UPMB—Outputs reflecting the
value specified in UPMB when an external transfer to a slave is
controlled by UPMB.
Chip Select 2 and 3—Outputs that enable peripheral or memory
devices at programmed addresses if they are appropriately
defined. The double drive capability for CS2 and CS3 is
independently defined for each signal in the SIU module
configuration register (SIUMCR).
UPWAITA
GPL_A4
Hi-Z
B13
Bidirectional User Programmable Machine Wait A—Input that is sampled as
defined by the user when an access to an external slave is
controlled by UPMA.
General-Purpose Line 4 on UPMA—Output reflecting the value
specified in UPMA when an external transfer to a slave is
controlled by UPMA.
UPWAITB
GPL_B4
Hi-Z
A14
Bidirectional User Programmable Machine Wait B—This input is sampled as
defined by the user when an access to an external slave is
controlled by UPMB.
General-Purpose Line 4 on UPMB—This output reflects the value
specified in UPMB when an external transfer to a slave is
controlled by UPMB.
GPL_A5
High
C13
Output
General-Purpose Line 5 on UPMA—This output reflects the value
specified in UPMA when an external transfer to a slave is
controlled by UPMA. This signal can also be controlled by UPMB.
PORESET
Hi-Z
B3
Input
Power-on Reset—When asserted, this input causes the MPC885
to enter the power-on reset state.
RSTCONF
Hi-Z
D4
Input
Reset Configuration—The MPC885 samples this input while
HRESET is asserted. If RSTCONF is asserted, the configuration
mode is sampled in the form of the hard reset configuration word
driven on the data bus. When RSTCONF is negated, the
MPC885 uses the default configuration mode. Note that the initial
base address of internal registers is determined in this sequence.
Name
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-8
Freescale Semiconductor
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
Type
Description
HRESET
Low
B4
Open-drain
Hard Reset—Asserting this open drain signal puts the MPC885
in a hard reset state.
SRESET
Low
A3
Open-drain
Soft Reset—Asserting this open drain line puts the MPC885 in a
soft reset state.
Analog
driving
A4
Analog
Output
This output is one of the connections to an external crystal for the
internal oscillator circuitry.
Hi-Z
D5
CLKOUT
Note2
G4
EXTCLK
Hi-Z
A5
TEXP
High
C4
Output
Timer Expired—This output reflects the status of
PLPRCR[TEXPS].
ALE_A
Low
B7
Output
Address Latch Enable A—This output line is asserted when
MPC885 initiates an access to a region under the control of the
PCMCIA interface to socket A.
CE1_A
High
B15
Output
Card Enable 1 Slot A—This output signal enables even byte
transfers when accesses to PCMCIA slot A are handled under the
control of the PCMCIA interface.
CE2_A
High
C15
Output
Card Enable 2 Slot A—This output signal enables odd byte
transfers when accesses to PCMCIA slot A are handled under the
control of the PCMCIA interface.
WAIT_A
Hi-Z
A2
Input
Wait Slot A—This input signal, if asserted low, causes a delay in
the completion of a transaction on the PCMCIA controlled Slot A.
Name
XTAL
EXTAL
Analog Input This line is one of the connections to an external crystal for the
(3.3 V only) internal oscillator circuitry.
Output
Clock Out—This output is the clock system frequency.
Input (3.3 V External Clock—This input is the external input clock from an
only)
external source.
SOC_Split
SOC_Split—This input signal is used for the UTOPIA master Rx
start of cell signal in split bus mode only.
WAIT_B
Hi-Z
C3
Input
Wait Slot B—This input, if asserted low, causes a delay in the
completion of a transaction on the PCMCIA controlled Slot B.
IP_A(0)
Hi-Z
B1
Input
Input Port A 0—This input signal is monitored by the MPC885 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
UTPB_Split[0]
UTPB_Split[0]—This input signal is used as Rx data in split bus
mode only. This is the least-significant bit of the UTPB_Aux bus.
IP_A(1)
Hi-Z
UTPB_Split[1]
C1
Input
Input Port A 1—This input signal is monitored by the MPC885 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
UTPB_Split[1]—This input signal is used as Rx data in split bus
mode only.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-9
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Name
IP_A2
Hard
Reset
Number
Type
Description
Hi-Z
F4
Input
Input Port A 2—This input signal is monitored by the MPC885 and
its value and changes are reported in the PIPR and PSCR of the
PCMCIA interface.
IOIS16_A
UTPB_Split[2]
I/O Device A is 16 Bits Ports Size—This input signal is monitored
by the MPC885 when a transaction under the control of the
PCMCIA interface is initiated to an I/O region in socket A of the
PCMCIA space.
UTPB_Split[2]—This input signal is used as Rx data in split bus
mode only.
IP_A(3)
Hi-Z
E3
Input
UTPB_Split[3]
Input Port A 3—This input signal is monitored by the MPC885 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
UTPB_Split[3]—This input signal is used as Rx data in split bus
mode only.
IP_A(4)
Hi-Z
D2
Input
UTPB_Split[4]
Input Port A 4—This input signal is monitored by the MPC885 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
UTPB_Split[4]—This input signal is used as Rx data in split bus
mode only.
IP_A(5)
Hi-Z
D1
Input
UTPB_Split[5]
Input Port A 5—This input signal is monitored by the MPC885 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface
UTPB_Split[5]—This input signal is used as Rx data in split bus
mode only.
IP_A(6)
Hi-Z
E2
UTPB_Split[6]
Bidirectional Input Port A 6—This input signal is monitored by the MPC885 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
UTPB_Split[6]—This input signal is used as Rx data in split bus
mode only.
IP_A(7)
Hi-Z
D3
UTPB_Split[7]
Input
Input Port A 7—This input signal is monitored by the MPC885 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
UTPB_Split[7]—This input signal is used as Rx data in split bus
mode only. This is the most-significant bit of the UTPB_Aux bus.
ALE_B
DSCK
AT1
See
Table 12-3
D8
Bidirectional Address Latch Enable B—This output is asserted when the
three-state MPC885 initiates an access to a region under the control of the
PCMCIA socket B interface.
Development Serial Clock—This input is the clock for the debug
port interface.
Address Type 1—The MPC885 drives this bidirectional
three-state line when it initiates a transaction on the external bus.
When the transaction is initiated by the core, it indicates if the
transfer is for user or supervisor state. This signal is not used for
transactions initiated by external masters.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-10
Freescale Semiconductor
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Name
Hard
Reset
Number
Type
Description
IP_B[0:1]
IWP[0:1]
VFLS[0:1]
See
Table 12-3
A9, D9
Bidirectional Input Port B[0:1]—The MPC885 senses these inputs; their values
and changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Instruction Watchpoint[0:1]—These outputs report the detection
of an instruction watchpoint in the program flow executed by the
core.
Visible History Buffer Flushes Status—The MPC885 outputs
VFLS[0:1] when program instruction flow tracking is required.
They report the number of instructions flushed from the history
buffer in the core.
IP_B2
IOIS16_B
AT2
Hi-Z
C8
Bidirectional Input Port B 2—The MPC885 senses this input; its value and
three-state changes are reported in the PIPR and PSCR of the PCMCIA
interface.
I/O Device B is 16 Bits Port Size—The MPC885 monitors this
input when a PCMCIA interface transaction is initiated to an I/O
region in socket B in the PCMCIA space.
Address Type 2—The MPC885 drives this bidirectional
three-state signal when it initiates a transaction on the external
bus. If the core initiates the transaction, it indicates if the transfer
is instruction or data. This signal is not used for transactions
initiated by external masters.
IP_B3
IWP2
VF2
See
Table 12-3
C9
Bidirectional Input Port B 3—The MPC885 monitors this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Instruction Watchpoint 2—This output reports the detection of an
instruction watchpoint in the program flow executed by the core.
Visible Instruction Queue Flushes Status—The MPC885 outputs
VF2 with VF0/VF1 when instruction flow tracking is required. VFn
reports the number of instructions flushed from the instruction
queue in the core.
IP_B4
LWP0
VF0
Hi-Z
B9
Bidirectional Input Port B 4—The MPC885 monitors this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Load/Store Watchpoint 0—This output reports the detection of a
data watchpoint in the program flow executed by the core.
Visible Instruction Queue Flushes Status—The MPC885 outputs
VF0 with VF1/VF2 when instruction flow tracking is required. VFn
reports the number of instructions flushed from the instruction
queue in the core.
IP_B5
LWP1
VF1
Hi-Z
A10
Bidirectional Input Port B 5—The MPC885 monitors this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Load/Store Watchpoint 1—This output reports the detection of a
data watchpoint in the program flow executed by the core.
Visible Instruction Queue Flushes Status—The MPC885 outputs
VF1 with VF0 and VF2 when instruction flow tracking is required.
VFn reports the number of instructions flushed from the
instruction queue in the core.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-11
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
IP_B6
DSDI
AT0
Hi-Z
A8
Bidirectional Input Port B 6—The MPC885 senses this input and its value and
three-state changes are reported in the PIPR and PSCR of the PCMCIA
interface. See Chapter 16, “PCMCIA Interface.”
Development Serial Data Input—Data input for the debug port
interface. See Chapter 53, “System Development and
Debugging.”
Address Type 0—The MPC885 drives this bidirectional
three-state line when it initiates a transaction on the external bus.
If high (1), the transaction is the CPM. If low (0), the transaction
initiator is the CPU. This signal is not used for transactions
initiated by external masters.
IP_B7
PTR
AT3
Hi-Z
B8
Bidirectional Input Port B 7—The MPC885 monitors this input; its value and
three-state changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Program Trace—To allow program flow tracking, the MPC885
asserts this output to indicate an instruction fetch is taking place
Address Type 3—The MPC885 drives the bidirectional
three-state signal when it starts a transaction on the external bus.
When the core initiates a transfer, AT3 indicates whether it is a
reservation for a data transfer or a program trace indication for an
instruction fetch. This signal is not used for transactions initiated
by external masters.
OP(0)
Low
B6
Name
Type
Output
UtpClk_Split
Description
Output Port 0—This output signal is generated by the MPC885 as
a result of a write to the PGCRA register in the PCMCIA interface.
UtpClk_Split—This input/output signal is used as the UTOPIA Rx
clock in split bus mode only. The direction of this I/O pin in split
UTOPIA mode is defined by UTOPIA mode register
(UTMODE[RCLK]). As an input or output the frequency of the
UTOPIA clock can be up to 50 Mhz and in the following range:
SYSCLK > UTPCLK > SYSCLK/10.
OP1
Low
C6
Output
Output Port 1—The MPC885 generates these outputs as a result
of a write to the PGCRA register in the PCMCIA interface.
OP2
MODCK1
STS
Hi-Z
D6
Bidirectional Output Port 2—This output is generated by the MPC885 as a
result of a write to the PGCRB register in the PCMCIA interface.
Mode Clock 1—Input sampled when PORESET is negated to
configure PLL/clock mode.
Special Transfer Start—The MPC885 drives this output to
indicate the start of an external bus transfer or an internal
transaction in show-cycle mode.
OP3
MODCK2
DSDO
Hi-Z
A6
Bidirectional Output Port 3—This output is generated by the MPC885 as a
result of a write to the PGCRB register in the PCMCIA interface.
Mode Clock 2—This input is sampled at the PORESET negation
to configure the PLL/clock mode of operation.
Development Serial Data Output—Output data from the debug
port interface.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-12
Freescale Semiconductor
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
Type
Description
BADDR30
REG
Hi-Z
A7
Output
Burst Address 30—This output duplicates the value of A30 when
the following is true:
• An internal master in the MPC885 initiates a transaction on the
external bus.
• An asynchronous external master initiates a transaction.
• A synchronous external master initiates a single beat
transaction.
The memory controller uses BADDR30 to increment the address
lines that connect to memory devices when a synchronous
external master or an internal master initiates a burst transfer.
Register—When an internal master initiates an access to a slave
under control of the PCMCIA interface, this signal duplicates the
value of TSIZ0/REG. When an external master initiates an
access, REG is output by the PCMCIA interface (if it must handle
the transfer) to indicate the space in the PCMCIA card being
accessed.
BADDR[28:29]
Hi-Z
C5, B5
Output
Burst Address—Outputs that duplicate A[28:29] values when one
of the following occurs:
• An internal master in the MPC885 initiates a transaction on the
external bus.
• An asynchronous external master initiates a transaction.
• A synchronous external master initiates a single beat
transaction.
The memory controller uses these signals to increment the
address lines that connect to memory devices when a
synchronous external or internal master starts a burst transfer.
AS
Hi-Z
D7
Input
PA[15]
USBRXD
Hi-Z
N16
Bidirectional General-Purpose I/O Port A Bit 15—Bit 15 of the general-purpose
I/O port A
USBRXD —Receive data. Input to the USB receiver from the
differential line receiver.
PA[14]
USBOE
Hi-Z
P17
Bidirectional General-Purpose I/O Port A Bit 14—Bit 14 of the general-purpose
I/O port A.
(optional:
open-drain) USBOE—Output enable. Enables the transceiver to send data
on the bus.
PA[13]
RXD2
Hi-Z
W11
Bidirectional General-Purpose I/O Port A Bit 13—Bit 13 of the general-purpose
I/O port A
RXD2—Receive data input for SCC2
PA[12]
TXD2
Hi-Z
P16
Bidirectional General-Purpose I/O Port A Bit 12—Bit 12 of the general-purpose
I/O port A
(optional:
open-drain) TXD2—Transmit data output for SCC2
Name
Address Strobe—Input driven by an external asynchronous
master to indicate a valid address on A[0:31]. The MPC885
memory controller synchronizes AS and controls the memory
device addressed under its control.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-13
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
PA[11]
RXD4
MII1-TXD0
RMII1-TXDO
Hi-Z
W9
Bidirectional General-Purpose I/O Port A Bit 11—Bit 11 of the general-purpose
I/O port A
(optional:
open-drain) RXD4—Receive data input for SCC4
MII1-TXD0—Media-independent interface 1, transmit data 0
RMII1-TXD0—Reduced media-independent interface 1, transmit
data 0.
PA[10]
MII-TXER
CLK7
TIN4
Hi-Z
W17
Bidirectional General-Purpose I/O Port A Bit 10—Bit 10 of the general-purpose
(optional:
I/O port A
open-drain)3 MII-TXER- media-independent interface 1, transmit error.
CLK7—One of eight clock inputs that can be used to clock SCCs
and SMCs
TIN4—Timer 4 external clock input
PA[9]
L1TXDA
RXD3
Hi-Z
T15
Bidirectional General-Purpose I/O Port A Bit 11—Bit 9 of the general-purpose
I/O port A
(optional:
open-drain) L1TXDA—Transmit data output for the serial interface TDMa
RXD3—Receive data input for SCC3
PA[8]
L1RXDA
TXD3
Hi-Z
W15
Bidirectional General-Purpose I/O Port A Bit 8—Bit 8 of the general-purpose
(optional:
I/O port A
open-drain)3 L1RXDA—Receive data input for the serial interface TDMa
TXD3—Transmit data output for SCC3
PA[7]
CLK1
TIN1
L1RCLKA
BRGO1
Hi-Z
V14
Bidirectional General-Purpose I/O Port A Bit 7—Bit 7 of the general-purpose
I/O port A
CLK1—One of eight clock inputs that can be used to clock SCCs
and SMCs
TIN1—Timer 1 external clock
L1RCLKA—Receive clock for the serial interface TDMa
BRGO1—Output clock of BRG1
PA[6]
CLK2
TOUT1
Hi-Z
U13
Bidirectional General-Purpose I/O Port A Bit 6—Bit 6 of the general-purpose
I/O port A.
CLK2—One of eight clock inputs that can be used to clock SCCs
and SMCs. CLK2 can also be used as a clock source for the
BRGs.
TOUT1—Timer 1 output
PA[5]
CLK3
TIN2
L1TCLKA
BRGO2
Hi-Z
W13
Bidirectional General-Purpose I/O Port A Bit 5—Bit 5 of the general-purpose
I/O port A.
CLK3—One of eight clock inputs that can be used to clock SCCs
and SMCs
TIN2—Timer 2 external clock input
L1TCLKA—Transmit clock for the serial interface TDMa
BRGO2—Output clock of BRG2
PA[4]
CTS4
MII1-TXD1
RMII1-TXD1
Hi-Z
U4
Bidirectional General-Purpose I/O Port A Bit 4—Bit 4 of the general-purpose
I/O port A
CTS4—Clear to send modem line for SCC4
MII1-TXD1—Media-independent interface 1, transmit data 1
RMII1-TXD1—Reduced media-independent interface 1, transmit
data 1
Name
Type
Description
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-14
Freescale Semiconductor
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
PA[3]
MII1-RXER
RMII1-RXER
BRGO3
Hi-Z
W2
Bidirectional General-Purpose I/O Port A Bit 3—Bit 3 of the general-purpose
I/O port A
MII1-RXER —Media-independent interface 1, receive error
RMII1-RXER—Reduced media-independent interface 1, receive
error
BRGO3—Output clock of BRG3
PA[2]
MII1-RXDV
RMII1-CRS_DV
TXD4
Hi-Z
T4
Bidirectional General-Purpose I/O Port A Bit 2—Bit 2 of the general-purpose
I/O port A
MII1-RXDV—Media-independent interface 1, receive data valid
RMII1-CRS_DV—Reduced MII 1, carrier receive sense or data
valid
TXD4—Transmit data for serial channel 4
PA[1]
MII1-RXD0
RMII1 -RXD0
BRGO4
Hi-Z
U1
Bidirectional General-Purpose I/O Port A Bit 1—Bit 1 of the general-purpose
I/O port A
MII1-RXD0—Media-independent interface 1, receive data 0
RMII1-RXD0—Reduced media-independent interface 1, receive
data 0
BRGO4—BRG4 output clock
PA[0]
MII1-RXD1
RMII1-RXD1
TOUT4
Hi-Z
U3
Bidirectional General-Purpose I/O Port A Bit 0—Bit 0 of the general-purpose
I/O port A
MII1-RXD1—Media-independent interface 1, receive data 1
RMII1-RXD1—Reduced media-independent interface 1, receive
data 1
TOUT4—Timer 4 output
PB[31]
SPISEL
MII1 - TXCLK
RMII1-REFCLK
Hi-Z
V3
Bidirectional General-Purpose I/O Port B Bit 31—Bit 31 of the general-purpose
I/O port B
(optional:
open-drain) SPISEL—SPI slave select input
MII1-TXCLK—Media-independent interface 1, transmit clock
RMII1-REFCLK—Reduced media-independent interface 1,
reference clock
PB[30]
SPICLK
Hi-Z
P18
Bidirectional General-Purpose I/O Port B Bit 30—Bit 30 of the general-purpose
I/O port B
(optional:
open-drain) SPICLK—SPI output clock when it is configured as a master or
SPI input clock when it is configured as a slave.
PB[29]
SPIMOSI
Hi-Z
T19
Bidirectional General-Purpose I/O Port B Bit 29—Bit 29 of the general-purpose
I/O port B
(optional:
open-drain) SPIMOSI—SPI output data when it is configured as a master or
SPI input data when it is configured as a slave
PB[28]
SPIMISO
BRGO4
Hi-Z
V19
Bidirectional General-Purpose I/O Port B Bit 28—Bit 29 of the general-purpose
I/O port B
(optional:
open-drain) SPIMISO—SPI input data when the MPC885 is a master; SPI
output data when it is a slave
BRGO4—BRG4 output clock
PB[27]
I2CSDA
BRGO1
Hi-Z
U19
Bidirectional General-Purpose I/O Port B Bit 27—Bit 27 of the general-purpose
I/O port B
(optional:
open-drain) I2CSDA—I2C serial data pin. Bidirectional; should be configured
as an open-drain output
BRGO1—BRG1 output clock
Name
Type
Description
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-15
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
PB[26]
I2CSCL
BRGO2
Hi-Z
R17
Bidirectional General-Purpose I/O Port B Bit 26—Bit 26 of the general-purpose
I/O port B
(optional:
open-drain) I2CSCL—I2C serial clock pin. Bidirectional; should be configured
as an open-drain output
BRGO2—BRG2 output clock
PB[25]
SMTXD1
RXADDR3
TXADDR3
Hi-Z
V17
Bidirectional General-Purpose I/O Port B Bit 25—Bit 25 of the general-purpose
I/O port B
(optional:
open-drain) SMTXD1—SMC1 transmit data output
UTOPIA multi-PHY receive address line 3 - only if in ESAR mode
UTOPIA multi-PHY transmit address line 3
PB[24]
SMRXD1
TXADDR3
RXADDR3
Hi-Z
U16
Bidirectional General-Purpose I/O Port B Bit 24—Bit 24 of the general-purpose
I/O port B
(optional:
open-drain) SMRXD1—SMC1 receive data input
UTOPIA multi-PHY transmit address line 3 - only if in ESAR mode
UTOIPIA multi-PHY receive address line 3
PB[23]
SMSYN1
SDACK1
TXADDR2
RXADDR2
Hi-Z
W16
Bidirectional General-Purpose I/O Port B Bit 23—Bit 23 of the general-purpose
I/O port B
(optional:
open-drain) SMSYN1—SMC1 external sync input
SDACK1—SDMA acknowledge 1 output that is used as a
peripheral interface signal for IDMA emulation, or as a CAM
interface signal for Ethernet
UTOPIA multi-PHY transmit address line 2 - only if in ESAR mode
UTOPIA multi-PHY receive address line 2
PB[22]
SMSYN2
SDACK2
TXADDR3
RXADDR3
Hi-Z
V15
Bidirectional General-Purpose I/O Port B Bit 22—Bit 22 of the general-purpose
I/O port B
(optional:
open-drain) SMSYN2—SMC2 external sync input
SDACK2—SDMA acknowledge 2 output that is used as a
peripheral interface signal for IDMA emulation
UTOPIA multi-PHY transmit address line 4 - only if in ESAR mode
UTOPIA multi-PHY receive address line 4
PB[21]
SMTXD2
BRGO1
PHSEL[1]
TXADDR1
RXADDR1
Hi-Z
U14
Bidirectional General-Purpose I/O Port B Bit 21—Bit 21 of the general-purpose
I/O port B
(optional:
open-drain) SMTXD2—SMC2 transmit data output
BRGO1—Output clock of BRG1
PHSEL[1]—Least-significant bit of PHY select bus (used in
classic SAR MPHY mode only)
UTOPIA multi-PHY transmit address line 1 - only if in ESAR mode
UTOPIA multi-PHY receive address line 1
PB[20]
SMRXD2
L1CLKOA
PHSEL[0]
TXADDR0
RXADDR0
Hi-Z
T13
Bidirectional General-Purpose I/O Port B Bit 20—Bit 20 of the general-purpose
I/O port B
(optional:
open-drain) SMRXD2—SMC2 receive data input
L1CLKOA—Clock output from the serial interface TDMa
PHSEL[0]—Most significant bit of PHY select bus (used in classic
SAR MPHY mode only)
UTOPIA multi-PHY transmit address line 0 - only if in ESAR mode
UTOPIA multi-PHY receive address line 0
Name
Type
Description
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-16
Freescale Semiconductor
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
PB[19]
RTS4
MII1-RXD3
Hi-Z
V13
Bidirectional General-Purpose I/O Port B Bit 19—Bit 19 of the general-purpose
I/O port B
(optional:
open-drain) RTS4—Request to send modem line for SCC4
MII1-RXD3 —Media-independent interface 1, receive data 3
PB[18]
RTS2
L1ST2
RXADDR4
TXADDR4
Hi-Z
T12
Bidirectional General-Purpose I/O Port B Bit 18—Bit 18 of the general-purpose
I/O port B
(optional:
open-drain) RTS2—Request to send modem line for SCC2
L1ST2—One of four output strobes that can be generated by the
serial interface
UTOPIA multi-PHY receive address line 4 - only if in ESAR mode
UTOPIA multi-PHY transmit address line 4
PB[17]
L1ST3
PHREQ[1]
RXADDR1
TXADDR1
BRGO2
Hi-Z
W12
Bidirectional General-Purpose I/O Port B Bit 17—Bit 17 of the general-purpose
I/O port B
(optional:
open-drain) L1ST3—One of four output strobes that can be generated by the
serial interface
PHREQ[1]—Least-significant bit of PHY request bus (used in
classic SAR MPHY mode only)
UTOPIA multi-PHY receive address line 1 - only if in ESAR mode
UTOPIA multi-PHY transmit address line
BRGO2—Output clock of BRG2
PB[16]
L1RQa
L1ST4
RTS4
PHREQ[0]
RXADDR0
TXADDR0
Hi-Z
V11
Bidirectional General-Purpose I/O Port B Bit 16—Bit 16 of the general-purpose
I/O port B
(optional:
open-drain) L1RQa—D-channel request signal for serial interface TDMa
L1ST4—One of four output strobes that can be generated by the
serial interface
RTS43—Request to send modem line for SCC4
PHREQ[0]—Most significant bit of PHY request bus (used in
classic SAR MPHY mode only)
UTOPIA multi-PHY receive address line 0 - only if in ESAR mode
UTOPIA multi-PHY transmit address line 0
PB[15]
BRGO3
TXCLAV
RXCLAV
Hi-Z
U10
Bidirectional General-Purpose I/O Port B Bit 15—Bit 15 of the general-purpose
I/O port B
BRGO3—BRG3 output clock
TXCLAV—Transmit cell available input signal
RXCLAV—Receive cell available input signal
PB[14]
RXADDR2
TXADDR2
Hi-Z
U18
Bidirectional General-Purpose I/O Port B Bit 14—Bit 14 of the general-purpose
I/O port B
RXADDR2—UTOPIA multi-PHY receive address line 2, in ESAR
mode only
TXADDR2—UTOPIA multi-PHY transmit address line 2
PC[15]
DREQ0
RTS3
L1ST1
TXCLAV
RXCLAV
Hi-Z
R19
Bidirectional General-Purpose I/O Port C Bit 15—Bit 15 of the
general-purpose I/O port C
DREQ0—IDMA channel 1 request input
RTS3—Request to send modem line for SCC3
L1ST1—One of four output strobes that can be generated by the
serial interface
TXCLAV—Transmit cell available input signal
RXCLAV—Receive cell available input signal
Name
Type
Description
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-17
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
PC[14]
DREQ1
RTS2
L1ST2
Hi-Z
R18
Bidirectional General-Purpose I/O Port C Bit 14—Bit 14 of the
general-purpose I/O port C
DREQ1—IDMA channel 2 request input
RTS2—Request to send modem line for SCC2
L1ST2—One of four output strobes that can be generated by the
serial interface
PC[13]
MII1-TXD3
SDACK1
Hi-Z
V10
Bidirectional General-Purpose I/O Port C Bit 13—Bit 13 of the
general-purpose I/O port C
MII1-TXD3—Media-independent interface 1, transmit data 3
SDACK1—SDMA acknowledge 1 output that is used as a
peripheral interface signal for IDMA emulation or as a CAM
interface signal for Ethernet.
PC[12]
MII1-TXD2
TOUT1
Hi-Z
T18
Bidirectional General-Purpose I/O Port C Bit 12—Bit 12 of the
general-purpose I/O port C
MII1-TXD2—Media-independent interface 1, transmit data 2
TOUT1—Timer 1 output
PC[11]
USBRXP
Hi-Z
V16
Bidirectional General-Purpose I/O Port C Bit 11—Bit 11 of the
general-purpose I/O port C
USBRXP—USB receive - gated version of D+
PC[10]
USBRXN
TGATE1
Hi-Z
U15
Bidirectional General-Purpose I/O Port C Bit 10—Bit 10 of the
general-purpose I/O port C
USBRXN—USB receive - gated version of D-.
TGATE1—Timer 1/timer 2 gate signal
PC[9]
CTS2
Hi-Z
T14
Bidirectional General-Purpose I/O Port C Bit 9—Bit 9 of the general-purpose
I/O port C
CTS2—Clear to send modem line for SCC2
PC[8]
CD2
TGATE2
Hi-Z
W14
Bidirectional General-Purpose I/O Port C Bit 8—Bit 8 of the general-purpose
I/O port C
CD2—Carrier detect modem line for SCC2
TGATE2—Timer 3/timer 4 gate signal
PC[7]
CTS4
L1TSYNCB
USBTXP
Hi-Z
V12
Bidirectional General-Purpose I/O Port C Bit 7—Bit 7 of the general-purpose
I/O port C
CTS4—Clear to send modem line for SCC4
L1TSYNCB—Transmit sync input for serial interface TDMb.
USBTXP—USB transmit +.
PC[6]
CD4
L1RSYNCB
USBTXN
Hi-Z
U11
Bidirectional General-Purpose I/O Port C Bit 6—Bit 6 of the general-purpose
I/O port C
CD4—Carrier detect modem line for SCC4
L1RSYNCB—Receive sync input for the serial interface TDMb
USBTXN—USB transmit -
PC[5]
CTS3
L1TSYNCA
SDACK2
Hi-Z
T10
Bidirectional General-Purpose I/O Port C Bit 5—Bit 5 of the general-purpose
I/O port C
CTS3—Clear to send modem line for SCC3
L1TSYNCA—Transmit sync input for serial interface TDMa
SDACK2—SDMA acknowledge 1 output that is used as a
peripheral interface signal for IDMA emulation or as a CAM
interface signal for Ethernet
Name
Type
Description
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-18
Freescale Semiconductor
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
PC[4]
CD3
L1RSYNCA
Hi-Z
W10
Bidirectional General-Purpose I/O Port C Bit 4—Bit 4 of the general-purpose
I/O port C
CD3—Carrier detect modem line for SCC3
L1RSYNCA—Receive sync input for serial interface TDMa
PD[15]
L1TSYNCA
UTPB[0]
Hi-Z
U8
Bidirectional General-Purpose I/O Port D Bit 15—Bit 15 of the
general-purpose I/O port D
L1TSYNCA—Input transmit data sync signal to the TDM channel
A
UTPB[0]—UTOPIA bus bit 0 input/output signal
PD[14]
L1RSYNCA
UTPB[1]
Hi-Z
U7
Bidirectional General-Purpose I/O Port D Bit 14—Bit 14 of the
general-purpose I/O port D
L1RSYNCA—Input receive data sync signal to the TDM channel
A
UTPB[1]—UTOPIA bus bit 1 input/output signal
PD[13]
L1TSYNCB
UTPB[2]
Hi-Z
U6
Bidirectional General-Purpose I/O Port D Bit 13—Bit 13 of the
general-purpose I/O port D
L1TSYNCB—Input transmit data sync signal to the TDM channel
B
UTPB[2]—UTOPIA bus bit 2 input/output signal
PD[12]
L1RSYNCB
UTPB[3]
Hi-Z
U5
Bidirectional General-Purpose I/O Port D Bit 12—Bit 12 of the
general-purpose I/O port D
L1RSYNCB—Input receive data sync signal to the TDM channel
B
UTPB[3]—UTOPIA bus bit 3 input/output signal
PD[11]
RXD3
RXENB
Hi-Z
R2
Bidirectional General-Purpose I/O Port D Bit 11—Bit 11 of the
general-purpose I/O port D
RXD3—Receive data for serial channel 3
RXENB—Receive enable output signal
PD[10]
TXD3
TXENB
Hi-Z
T2
Bidirectional General-Purpose I/O Port D Bit 10—Bit 10 of the
general-purpose I/O port D
TXD3—Transmit data for serial channel 3
TXENB—Transmit enable output signal
PD[9]
TXD4
UTPCLK
Hi-Z
U2
Bidirectional General-Purpose I/O Port D Bit 9—Bit 9 of the general-purpose
I/O port D
TXD4—Transmit data for serial channel 4
UTPCLK—UTOPIA clock input/output signal. The direction of this
I/O pin in non-muxed UTOPIA mode is defined by UTOPIA mode
register. As an input or output the frequency of the UTOPIA clock
can be up to 50 Mhz and in the following range: SYSCLK >
UTPCLK > SYSCLK/10
PD[8]
RXD4
MII-MDC
Hi-Z
R3
Bidirectional General-Purpose I/O Port D Bit 8—Bit 8 of the general-purpose
I/O port D
RXD4—Receive data for serial channel 4
MII-MDC—Media-independent interface management data
clock.
RMII-MDC—Reduced media-independent interface
management data clock.
Name
RMII-MDC
Type
Description
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-19
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
PD[7]
RTS3
UTPB[4]
Hi-Z
W3
Bidirectional General-Purpose I/O Port D Bit 7—Bit 7 of the general-purpose
I/O port D
RTS3—Active low request to send output indicates that SCC3 is
ready to transmit data
UTPB[4]—UTOPIA bus bit 4 input/output signal
PD[6]
RTS4
UTPB[5]
Hi-Z
W5
Bidirectional General-Purpose I/O Port D Bit 6—Bit 6 of the general-purpose
I/O port D
RTS4—Active low request to send output indicates that SCC4 is
ready to transmit data
UTPB[5]—UTOPIA bus bit 5 input/output signal
PD[5]
UTPB[6]
CLK8
L1TCLKB
Hi-Z
V6
Bidirectional General-Purpose I/O Port D Bit 5—Bit 5 of the general-purpose
I/O port D
UTPB[6]—UTOPIA bus bit 6 input/output signal
CLK8—One of eight clock inputs that can be used to clock SCCs
and SMCs
L1TCLKB—Transmit clock for the serial interface TDMb
PD[4]
UTPB[7]
CLK4
Hi-Z
W4
Bidirectional General-Purpose I/O Port D Bit 4—Bit 4 of the general-purpose
I/O port D
UTPB[7]—UTOPIA bus bit 7 input/output signal (most-significant
bit of UTPB)
CLK4—One of eight clock inputs that can be used to clock SCCs
and SMCs
PD[3]
SOC
CLK7
TIN4
Hi-Z
T9
Bidirectional General-Purpose I/O Port D Bit 3—Bit 3 of the general-purpose
I/O port D
SOC—Start of cell input/output signal
CLK7—One of eight clock inputs that can be used to clock SCCs
and SMCs
TIN4—Timer 4 external clock input
PE31
CLK8
L1TCLKB
MII1-RXCLK
Hi-Z
U9
Bidirectional General-Purpose I/O Port E Bit 31
CLK8—One of eight clock inputs that can be used to clock SCCs
(optional:
open-drain) and SMCs
L1TCLKB—Transmit clock for the serial interface TDMb
MII-RXCLK—Media-independent interface receive clock
PE30
L1RXDB
MII1-RXD2
Hi-Z
W7
Bidirectional General-Purpose I/O Port E Bit 30
L1RXDB—Receive data input for the serial interface TDMb
(optional:
open-drain) MII1-RXD2 —Media-independent interface 1, receive data 2
PE29
MII2-CRS
Hi-Z
T8
Bidirectional General-Purpose I/O Port E Bit 29
MII2-CRS —Media-independent interface 2, carrier receive
(optional:
open-drain) sense
PE28
TOUT3
MII2-COL
Hi-Z
V5
Bidirectional General-Purpose I/O Port E Bit 28
TOUT3—Timer 3 output
(optional:
open-drain) MII2-COL—Media-independent interface 2 collision
Name
Type
Description
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-20
Freescale Semiconductor
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
PE27
RTS3
L1RQB
MII2-RXER
RMII2-RXER
Hi-Z
V4
Bidirectional General-Purpose I/O Port E Bit 27
RTS3—Active low request to send output indicates that SCC3 is
(optional:
open-drain) ready to transmit data
L1RQB—D-channel request signal for serial interface TDMb
MII2-RXER —Media-independent interface 2, receive error
RMII2-RXER—Reduced media-independent interface 2, receive
error
PE26
L1CLKOB
MII2-RXDV
RMII2-CRS_DV
Hi-Z
T1
Bidirectional General-Purpose I/O Port E Bit 26
L1CLKOB—Clock output from the serial interface TDMb
(optional:
open-drain) MII2-RXDV—Media-independent interface 2, receive data valid
RMII2-CRS_DV—Reduced media-independent interface 2,
carrier receive sense or data valid
PE25
RXD4
MII2-RXD3
L1ST2
Hi-Z
T3
Bidirectional General-Purpose I/O Port E Bit 25
RXD4—Receive data input for SCC4
(optional:
open-drain) MII2-RXD3—Media-independent interface 2, receive data 3
L1ST2—One of four output strobes that can be generated by the
serial interface
PE24
SMRXD1
BRGO1
MII2-RXD2
Hi-Z
V8
Bidirectional General-Purpose I/O Port E Bit 24
SMRXD1—SMC1 receive data input
(optional:
open-drain) BRGO1—Output clock of BRG1
MII2-RXD2—Media-independent interface 2, receive data 2
PE23
SMSYN2
TXD4
MII2-RXCLK
L1ST1
Hi-Z
V2
Bidirectional General-Purpose I/O Port E Bit 23
SMSYN2—SMC2 external sync input
(optional:
open-drain) TXD4—Transmit data for serial channel 4
MII2-RXCLK—Media-independent interface 2, receive clock
L1ST1—One of four output strobes that can be generated by the
serial interface
PE22
TOUT2
MII2-RXD1
RMII2-RXD1
SDACK1
Hi-Z
V1
Bidirectional General-Purpose I/O Port E Bit 22
TOUT2—Timer 2 output
(optional:
open-drain) MII2-RXD1—Media-independent interface 2, receive data 1
RMII2-RXD1—Reduced media-independent interface 2, receive
data 1
SDACK1—SDMA acknowledge 1 output that is used as a
peripheral interface signal for IDMA emulation, or as a CAM
interface signal for Ethernet.
PE21
SMRXD2
TOUT1
MII2-RXD0
RMII2-RXD0
RTS3
Hi-Z
V9
Bidirectional General-Purpose I/O Port E Bit 21
SMRXD2—SMC2 receive data input
(optional:
open-drain) TOUT1—Timer 1 output
MII2-RXD0—Media-independent interface 2, receive data 0
RMII2-RXD0—Reduced media-independent interface 2, receive
data 0
RTS3—Active low request to send output indicates that SCC3 is
ready to transmit data
PE20
L1RSYNCA
SMTXD2
CTS3
MII2-TXER
Hi-Z
R4
Bidirectional General-Purpose I/O Port E Bit 20
L1RSYNCA—Receive sync input for serial interface TDMa
(optional:
open-drain) SMTXD2—SMC2 transmit data output
CTS3—Clear to send modem line for SCC3
MII2-TXER—Media independent interface 2, transmit error
Name
Type
Description
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-21
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Reset
Number
PE19
L1TXDB
MII2-TXEN
RMII2-TXEN
Hi-Z
T6
Bidirectional General-Purpose I/O Port E Bit 19
L1TXDB—Transmit data output for the serial interface TDMb.
(optional:
open-drain) MII2-TXEN—Media-independent interface 2, transmit enable
RMII2-TXEN—Reduced media-independent interface 2, transmit
enable
PE18
L1TSYNCA
SMTXD1
MII2-TXD3
Hi-Z
R1
Bidirectional General-Purpose I/O Port E Bit 18
L1TSYNCA—Transmit sync input for serial interface TDMa
(optional:
open-drain) SMTXD1—SMC1 transmit data output
MII2-TXD3—Media-independent interface 2, transmit data 3
PE17
TIN3
CLK5
BRGO3
SMSYN1
MII2-TXD2
Hi-Z
W8
Bidirectional General-Purpose I/O Port E Bit 17
TIN3—Timer 3 external clock input
(optional:
open-drain) CLK5—One of eight clock inputs that can be used to clock SCCs
and SMCs
BRGO3—Output clock of BRG3
SMSYN1—SMC1 external sync input
MII2-TXD2—Media-independent interface 2, transmit data 2
PE16
L1RCLKB
CLK6
TXD3
MII2-TXCLK
RMII2-REFCLK
Hi-Z
T7
Bidirectional General-Purpose I/O Port E Bit 16
L1RCLKB—Receive clock for the serial interface TDMb
(optional:
open-drain) CLK6—One of eight clock inputs that can be used to clock SCCs
and SMCs
TXD3—Transmit data output for SCC3
MII2-TXCLK—Media-independent interface 1, transmit clock
RMII2-REFCLK—Reduced media-independent interface 1,
reference clock
PE15
TGATE1
MII2-TXD1
RMII2-TXD1
Hi-Z
W6
Bidirectional General-Purpose I/O Port E Bit 15
TGATE1—Timer 1/timer 2 gate signal
MII2-TXD1—Media-independent interface 2, transmit data 1
RMII2-TXD1—Reduced media-independent interface 2, transmit
data 1
PE14
RXD3
MII2-TXD0
RMII2-TXD0
Hi-Z
V7
Bidirectional General-Purpose I/O Port E Bit 14
RXD3—Receive data input for SCC3
MII2-TXD0—Media-independent interface 2, transmit data 0
RMII2-TXD0—Reduced media-independent interface 2, transmit
data 0
TCK
DSCK
Hi-Z
U17
Input
Provides clock to scan chain logic or for the development port
logic
Name
Type
Description
TMS
Pulled up
V18
Input
Controls the scan chain test mode operations
TDI
DSDI
Pulled up
T16
Input
Input serial data for either the scan chain logic or the development
port and determines the operating mode of the development port
at reset
TDO
DSDO
Low
T17
Output
Output serial data for either the scan chain logic or for the
development port
TRST
Pulled up3
W18
Input
Test reset for the JTAG scan chain logic
MII1_CRS
Hi-Z
T11
Input
MII1_CRS —Media-independent interface 1, carrier receive
sense
MII_MDIO
Hi-Z
P19
MII1_TXEN
Low
T5
Bidirectional MII_MDIO—Media-independent interface management data
Output
MII1_TXEN—Media-independent interface 1, transmit enable
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-22
Freescale Semiconductor
External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Name
MII1_COL
Hard
Reset
Number
Type
Hi-Z
U12
Input
MII1_COL—Media-independent interface 1, collision
See
Figure 12-1
Power
VDDL—Power supply of the internal logic
VDDH—Power supply of the I/O buffers and certain parts of the
clock control
VDDSYN—Power supply of the PLL circuitry
GND—Ground for circuits, except for the PLL circuitry
VSSSYN, VSSSYN1—Ground for the PLL circuitry
Power supply
Description
1
Pulled low if RSTCONF pulled down.
High until DPLL locked, then oscillates.
3
See Section 11.4, “TRST Considerations,” and Section 54.6, “Recommended TAP Configuration.”
2
12.2
MPC875/MPC870 Signals
The following sections describe the signals, their descriptions, and pin numbers.
12.2.1
MPC875/MPC870 Signals and Pin Numbers
Figure 12-3 and Figure 12-4 show MPC875 signals and pin numbers.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-23
External Signals
VDDSYN /VSSSYN/VSSSYN1/VDDH/VDDL/GND
USBRXD/PA15
USBOE/PA14
RXD4/MII1-TXD0/RMII1-TXD0/PA11
MII-TXER/TIN4/CLK7/PA10
TIN1/BRGO1/CLK1/PA7
TOUT1/CLK2/PA6
CTS4/MII1-TXD1/RMII1-TXD1/PA4
MII1-RXER/RMII1-RXER/BRGO3/PA3
MII1-RXDV/RMII1-CRS_DV/TXD4/PA2
MII1-RXD0/RMII1-RXD0/BRGO4/PA1
MII1-RXD1/RMII1-RXD1/TOUT4/PA0
MII1-TXCLK/RMII1-REFCLK/SPISEL/PB31
SPICLK/PB30
SPIMOSI/PB29
BRGO4/SPIMISO/PB28
BRGO1/I2CSDA/PB27
BRGO2/I2CSCL/PB26
SMTxD1/PB25
SMRxD1/PB24
SMSYN1/SDACK1/PB23
MII1-RXD3/RTS4/PB19
L1ST1/DREQ0/PC15
MII1-TXD3/SDACK1/PC13
MII1-TXD2/TOUT1/PC12
USBRXP/PC11
TGATE1/USBRXN/PC10
L1TSYNCB/CTS4/USBTXP/PC7
L1RSYNCB/CD4/USBTXN/PC6
MII-MDC/RMII-MDC/RxD4/PD8
L1TCLKB/CLK8/MII-RXCLK/PE31
L1RXDB/MII1-RXD2/PE30
MII2-CRS/PE29
TOUT3/MII2-COL/PE28
L1RQB/MII2-RXER/RMII2-RXER/PE27
L1CLKOB/MII2-RXDV/RMII2-CRS_DV/PE26
RXD4/MII2-RXD3/L1ST2/PE25
SMRXD1/BRGO1/MII2-RXD2/PE24
TXD4/MII2-RXCLK/L1ST1/PE23
TOUT2/MII2-RXD1/RMII2-RXD1/SDACK1/PE22
TOUT1/MII2-RXD0/RMII2-RXD0/PE21
MII2-TXER/PE20
L1TXDB/MII2-TXEN/RMII2-TXEN/PE19
SMTXD1/MII2-TXD3/PE18
SMSYN1/TIN3/CLK5/BRG03/MII2-TXD2/PE17
L1RCLKB/CLK6/MII2-TXCLK/RMII2-REFCLK/PE16
TGATE1/MII2-TXD1/RMII2-TXD1/PE15
RXD3/MII2-TXD0/RMII2-TXD0/PE14
TMS
DSDI/TDI
DSCK/TCK
TRST
DSDO/TDO
AS
58
1–P14
1–U16
1–R9
1–R12
1–R11
1–P11
1–P7
1–R5
1–N6
1–T4
1–P6
1–T5
1–T17
1–R17
MPC875
1–R14
1–N13
1–N12
1–U13
1–T12
1–U12
1–T11
1–R15
1–U9
1–T15
1–P12
1–U11
1–T10
1–P10
1–T3
1–P9
1–R8
1–U7
1–R7
1–T6
1–T2
1–R4
1–U8
1–U4
1–P4
1–T9
1–U3
1–R6
1–M5
1–T8
1–U6
1–T7
1–P8
E6
E5
F6
G7
G8
G9
G10
G11
G12
H7
H12
J7
J12
K7
K12
L7
L12
M7
M8
M9
M10
M11
M12
— VDDLSYN
— VSSSYN
— VSSSYN1
— VDDH
F7— F11 — VDDL
H6
H13
J6
J13
K6
K13
L6
L13
N7 —N11
H8—H11— GND
J8—J11
K8—K11
L8—L11
U15
1–T14
1–T13
1–R13
1–U14
1–P13
1–C7
Figure 12-3. MPC875 Signals and Pin Numbers (Part 1)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-24
Freescale Semiconductor
External Signals
A0— R16
A1— N14
A2— M14
A3— P15
A4— P17
A5— P16
A6— N15
A7— N16
A8— M15
A9— N17
A10— L14
A11— M16
A12— L15
A13— M17
A14— K14
A15— L16
A16— L17
A17— K17
A18— G17
A19— K15
A20— J16
A21— J15
A22— G16
A23— J14
A24— H17
A25— H16
A26— G15
A27— K16
A28—a H14
29— J17
A30— H15
A31— F17
D0— L5
D1— N3
D2— L3
D3— L2
D4— R2
D5— K2
D6— H3
D7— G2
D8— R3
D9— M3
D10— N2
D11— M2
D12— M4
D13— N4
D14— K5
D15— K3
D16— K4
D17— P3
D18— J2
D19— J3
D20— J4
D21— J5
D22— H2
D23— P2
D24— H4
D25— H5
D26— G5
D27— L4
D28— G3
D29— F2
D30— F3
D31— E2
32
F16–1
G14–1
D13–1
B9–1
C13–1
C11–1
C12–1
B12–1
B13–1
C9–1
E9–1
E10–1
32
B11–1
D10–1
C10–1
B10–1
M6,P5–2
N5–1
6
F12–1
D15–1
E15–1
D17–1
D16–1
G13–1
F14,E16,E17,F15 –4
C17–1
F13–1
E14,C16–2
D11–1
MPC875
E12–1
D12–1
D5–1
C3–1
E7–1
C4–1
D6–1
D7–1
G4–1
B4–1
B3–1
B7–1
C15–1
D14–1
D4–1
G6, F5–2
D3–1
E4,D2,E3,F4,C2–5
C8–1
MII1_CRS
U10-1
MII1_COL
R10-1
MII_MDIO
M13-1
MII1_TXEN
U5-1
A[0:31]
TSIZ0/REG
TSIZ1
RD/WR
BURST
BDIP/GPL_B5
TS
TA
TEA
BI
IRQ2/RSV
IRQ4/KR/RETRY/SPKROUT
CR/IRQ3
D[0:31]
BR
BG
BB
FRZ/IRQ6
IRQ[0:1]
IRQ7
CS[0:5] — B14, E11, C14, B15, E13, B16
CS6/CE1_B
CS7/CE2_B
WE0/BS_B0/IORD
WE1/BS_B1/IOWR
WE2/BS_B2/PCOE
WE3/BS_B3/PCWE
BS_A[0:3]
GPL_A0/GPL_B0
OE/GPL_A1/GPL_B1
GPL_A[2:3]/GPL_B[2:3]/CS[2:3]
UPWAITA/GPL_A4
UPWAITB/GPL_B4
GPL_A5
PORESET
RSTCONF
HRESET
SRESET
XTAL
EXTAL
CLKOUT
EXTCLK
TEXP
ALE_A
CE1_A
CE2_A,
WAIT_A
IP_A[0:1]
IP_A2/IOIS16_A
ALE_B/DSCK
E4–IP_A3
D2–IP_A4
E3–IP_A5
F4–IP_A6
C2–IP_A7
B8,D9–2
IP_B[0:1]/WP[0:1]/VFLS[0:1]
B6, C6–2
B5–1
B2–1
D8–1
E8,C5–2
OP2/MODCK1/STS C6–OP1
OP3/MODCK2/DSDO
BADDR30/REG
BADDR[28:29]
B6-–OP0/
Figure 12-4. MPC875 Signals and Pin Numbers (Part 2)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-25
External Signals
12.2.2
MPC875/MPC870 System Bus Signals
The MPC875 system bus consists of signals that interface with the external bus. Many of these signals
perform different functions, depending on how the user assigns them. The input and output signals in
Table 12-2 are identified by their abbreviations.
Table 12-2. MPC875/MPC870 Signal Descriptions
Name
Hard
Reset
Number
Type
Description
A[0:31]
Hi-Z
See
Figure 12-4
Bidirectional Address Bus—Provides the address for the current bus cycle. A0
three-state is the msb. The bus is output when an internal master starts a
transaction on the external bus. The bus is input when an external
master starts a transaction on the bus.
TSIZ0
REG
Hi-Z
F16
Bidirectional Transfer Size 0—When accessing a slave in the external bus,
three-state used (together with TSIZ1) by the bus master to indicate the
number of operand bytes waiting to be transferred in the current
bus cycle. TSIZ0 is an input when an external master starts a bus
transaction.
Register—When an internal master initiates an access to a slave
controlled by the PCMCIA interface, REG is output to indicate
which space in the PCMCIA card is accessed.
TSIZ1
Hi-Z
G14
Bidirectional Transfer Size 1—Used (with TSIZ0) by the bus master to indicate
three-state the number of operand bytes waiting to be transferred in the
current bus cycle. The MPC875 drives TSIZ1 when it is bus
master. TSIZ1 is input when an external master starts a bus
transaction.
RD/WR
Hi-Z
D13
Bidirectional Read/Write—Driven by a bus master to indicate the direction of
three-state the data transfer. A logic one indicates a read from a slave device
and a logic zero indicates a write to a slave device.
The MPC875 drives this signal when it is bus master. Input when
an external master initiates a transaction on the bus.
BURST
Hi-Z
B9
Bidirectional Burst Transaction—Driven by the bus master to indicate that the
three-state current initiated transfer is a burst. The MPC875 drives this signal
when it is bus master. This signal is input when an external master
initiates a transaction on the bus.
BDIP
GPL_B5
See
Table 12-3
C13
Hi-Z
C11
TS
Output
Burst Data in Progress—When accessing a slave device in the
external bus, the master on the bus asserts this signal to indicate
that the data beat in front of the current one is the one requested
by the master. BDIP is negated before the expected last data beat
of the burst transfer.
General-Purpose Line B5—Used by the memory controller when
UPMB takes control of the slave access.
Bidirectional Transfer Start—Asserted by a bus master to indicate the start of a
bus cycle that transfers data to or from a slave device.
active
Driven by the master only when it has gained the ownership of the
pull-up
bus. Every master should negate this signal before the bus
relinquish. TS requires the use of an external pull-up resistor.
The MPC875 samples TS when it is not the external bus master
to allow the memory controller/PCMCIA interface to control the
accessed slave device. It indicates that an external synchronous
master initiated a transaction.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-26
Freescale Semiconductor
External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Reset
Number
TA
Hi-Z
C12
Bidirectional Transfer Acknowledge—Indicates that the slave device addressed
in the current transaction accepted data sent by the master (write)
active
or has driven the data bus with valid data (read). This is an output
pull-up
when the PCMCIA interface or memory controller controls the
transaction. The only exception occurs when the memory
controller controls the slave access by means of the GPCM and
the corresponding option register is instructed to wait for an
external assertion of TA. Every slave device should negate TA
after a transaction ends and immediately three-state it to avoid
bus contention if a new transfer is initiated addressing other slave
devices. TA requires the use of an external pull-up resistor.
TEA
Hi-Z
B12
Open-drain
BI
Hi-Z
B13
Bidirectional Burst Inhibit—Indicates that the slave device addressed in the
current burst transaction cannot support burst transfers. It acts as
active
an output when the PCMCIA interface or memory controller takes
pull-up
control of the transaction. BI requires the use of an external
pull-up resistor.
RSV
IRQ2
See
Table 12-3
C9
Bidirectional Reservation—The MPC875 outputs this three-state signal with
three-state the address bus to indicate that the core initiated a transfer as a
result of a stwcx. or lwarx.
Interrupt Out 2—One of eight external inputs that can request (by
means of the internal interrupt controller) a service routine from
the core
KR/RETRY
IRQ4
SPKROUT
See
Table 12-3
E9
Bidirectional Kill Reservation—Input used as a part of the memory reservation
three-state protocol, when the MPC875 initiated a transaction as the result of
a stwcx. instruction.
Retry—Input used by a slave device to indicate it cannot accept
the transaction. The MPC875 must relinquish mastership and
reinitiate the transaction after winning in the bus arbitration.
Interrupt Request 4—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine
from the core.
SPKROUT—Digital audio wave form output to be driven to the
system speaker.
CR
IRQ3
Hi-Z
E10
D[0:31]
Hi-Z1
See
Figure 12-4
Name
Type
Input
Description
Transfer Error Acknowledge—Indicates that a bus error occurred
in the current transaction. The MPC875 asserts TEA when the
bus monitor does not detect a bus cycle termination within a
reasonable amount of time. Asserting TEA terminates the bus
cycle, thus ignoring the state of TA. TEA requires the use of an
external pull-up resistor.
Cancel Reservation—Input used as a part of the storage
reservation protocol.
Interrupt Request 3—One of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core.
Bidirectional Data Bus—Bidirectional three-state bus, provides the
three-state general-purpose data path between the MPC875 and all other
devices. The 32-bit data path can be dynamically sized to support
8-, 16-, or 32-bit transfers. D0 is the msb of the data bus.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-27
External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Reset
Number
BR
Hi-Z
B11
Bidirectional Bus Request—Asserted low when a possible master is requesting
ownership of the bus. When the MPC875 is configured to work
with the internal arbiter, this signal is configured as an input. When
the MPC875 is configured to work with an external arbiter, this
signal is configured as an output.
BG
Hi-Z
D10
Bidirectional Bus Grant—Asserted low when the arbiter of the external bus
grants the bus to a specific device. When the MPC875 is
configured to work with the internal arbiter, BG is configured as an
output and asserted every time the external master asserts BR
and its priority request is higher than any internal sources
requiring a bus transfer. However, when the MPC875 is configured
to work with an external arbiter, BG is an input.
BB
Hi-Z
C10
Bidirectional Bus Busy—Asserted low by a master to show that it owns the bus.
The MPC875 asserts BB after the arbiter grants it bus ownership
active
pull-up
and BB is negated.
FRZ
IRQ6
See
Table 12-3
B10
Bidirectional Freeze—Output asserted to indicate that the core is in debug
mode.
Interrupt Out 6—One of eight external inputs that can request (by
means of the internal interrupt controller) a service routine from
the core.
IRQ0
Hi-Z
M6
Input
Interrupt Out 0—One of eight external inputs that can request (by
means of the internal interrupt controller) a service routine from
the core.
IRQ1
Hi-Z
P5
Input
Interrupt Out 1—One of eight external inputs that can request (by
means of the internal interrupt controller) a service routine from
the core.
IRQ7
Hi-Z
N5
Input
Interrupt Out 7—One of eight external inputs that can request (by
means of the internal interrupt controller) a service routine from
the core.
CS[0:5]
High
B14, E11,
C14, B15,
E13, B16
Output
Chip Select—These outputs enable peripheral or memory devices
at programmed addresses if they are appropriately defined. CS0
can be configured to be the global chip-select for the boot device.
CS6
CE1_B
High
F12
Output
Chip Select 6—This output enables a peripheral or memory
device at a programmed address if defined appropriately in the
BR6 and OR6 in the memory controller.
Card Enable 1 Slot B—This output enables even byte transfers
when accesses to the PCMCIA slot B are handled under the
control of the PCMCIA interface.
CS7
CE2_B
High
D15
Output
Chip Select 7—This output enables a peripheral or memory
device at a programmed address if defined appropriately in the
BR7 and OR7 in the memory controller.
Card Enable 2 Slot B—This output enables odd byte transfers
when accesses to the PCMCIA slot B are handled under the
control of the PCMCIA interface.
Name
Type
Description
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-28
Freescale Semiconductor
External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Reset
Number
Type
Description
WE0
BS_B0
IORD
High
E15
Output
Write Enable 0—Output asserted when a write access to an
external slave controlled by the GPCM is initiated by the MPC875.
WE0 is asserted if D[0:7] contains valid data to be stored by the
slave device.
Byte Select 0 on UPMB—Output asserted under control of UPMB,
as programmed by the user. In a read or write transfer, the line is
only asserted if D[0:7] contains valid data.
I/O Device Read—Output asserted when the MPC875 starts a
read access to a region controlled by the PCMCIA interface.
Asserted only for accesses to a PC card I/O space.
WE1
BS_B1
IOWR
High
D17
Output
Write Enable 1—Output asserted when the MPC875 initiates a
write access to an external slave controlled by the GPCM. WE1 is
asserted if D[8:15] contains valid data to be stored by the slave
device.
Byte Select 1 on UPMB—Output asserted under control of UPMB,
as programmed by the user. In a read or write transfer, the line is
only asserted if D[8:15] contains valid data.
I/O Device Write—This output is asserted when the MPC875
initiates a write access to a region controlled by the PCMCIA
interface. IOWR is asserted only if the access is to a PC card I/O
space.
WE2
BS_B2
PCOE
High
D16
Output
Write Enable 2—Output asserted when the MPC875 starts a write
access to an external slave controlled by the GPCM. WE2 is
asserted if D[16:23] contains valid data to be stored by the slave
device.
Byte Select 2 on UPMB—Output asserted under control of UPMB,
as programmed by the user. In a read or write transfer, BS_B2 is
asserted only D[16:23] contains valid data.
PCMCIA Output Enable—Output asserted when the MPC875
initiates a read access to a memory region under the control of the
PCMCIA interface.
WE3
BS_B3
PCWE
High
G13
Output
Write Enable 3—Output asserted when the MPC875 initiates a
write access to an external slave controlled by the GPCM. WE3 is
asserted if D[24:31] contains valid data to be stored by the slave
device.
Byte Select 3 on UPMB—Output asserted under control of UPMB,
as programmed by the user. In a read or write transfer, BS_B3 is
asserted only if D[24:31] contains valid data.
PCMCIA Write Enable—Output asserted when the MPC875
initiates a write access to a memory region under control of the
PCMCIA interface.
BS_A[0:3]
High
F14, E16,
E17, F15
Output
Byte Select 0 to 3 on UPMA—Outputs asserted under
requirement of UPMA, as programmed by the user. For read or
writes, asserted only if their corresponding data lanes contain
valid data:
BS_A0 for D[0:7], BS_A1 for D[8:15],
BS_A2 for D[16:23], BS_A3 for D[24:31]
Name
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-29
External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Reset
Number
Type
Description
GPL_A0
GPL_B0
High
C17
Output
General-Purpose Line 0 on UPMA—This output reflects the value
specified in UPMA when an external transfer to a slave is
controlled by UPMA.
General-Purpose Line 0 on UPMB—This output reflects the value
specified in UPMB when an external transfer to a slave is
controlled by UPMB.
OE
GPL_A1
GPL_B1
High
F13
Output
Output Enable—Output asserted when the MPC875 initiates a
read access to an external slave controlled by the GPCM.
General-Purpose Line 1on UPMA—This output reflects the value
specified in UPMA when an external transfer to a slave is
controlled by UPMA.
General-Purpose Line 1 on UPMB—This output reflects the value
specified in UPMB when an external transfer to a slave is
controlled by UPMB.
GPL_A[2:3]
GPL_B[2:3]
CS[2:3]
High
E14, C16
Output
General-Purpose Line 2 and 3 on UPMA—These outputs reflect
the value specified in UPMA when an external transfer to a slave
is controlled by UPMA.
General-Purpose Line 2 and 3 on UPMB—These outputs reflect
the value specified in UPMB when an external transfer to a slave
is controlled by UPMB.
Chip Select 2 and 3—These outputs enable peripheral or memory
devices at programmed addresses if they are appropriately
defined. The double drive capability for CS2 and CS3 is
independently defined for each signal in the SIU module
configuration register (SIUMCR).
UPWAITA
GPL_A4
Hi-Z
D11
Bidirectional User Programmable Machine Wait A—This input is sampled as
defined by the user when an access to an external slave is
controlled by UPMA.
General-Purpose Line 4 on UPMA—This output reflects the value
specified in UPMA when an external transfer to a slave is
controlled by UPMA.
UPWAITB
GPL_B4
Hi-Z
E12
Bidirectional User Programmable Machine Wait B—This input is sampled as
defined by the user when an access to an external slave is
controlled by UPMB.
General-Purpose Line 4 on UPMB—This output reflects the value
specified in UPMB when an external transfer to a slave is
controlled by UPMB.
GPL_A5
High
D12
Output
General-Purpose Line 5 on UPMA—This output reflects the value
specified in UPMA when an external transfer to a slave is
controlled by UPMA. This signal can also be controlled by UPMB.
PORESET
Hi-Z
D5
Input
Power-on Reset—When asserted, this input causes the MPC875
to enter the power-on reset state.
RSTCONF
Hi-Z
C3
Input
Reset Configuration—The MPC875 samples this input while
HRESET is asserted. If RSTCONF is asserted, the configuration
mode is sampled in the form of the hard reset configuration word
driven on the data bus. When RSTCONF is negated, the MPC875
uses the default configuration mode. Note that the initial base
address of internal registers is determined in this sequence.
Name
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-30
Freescale Semiconductor
External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Reset
Number
Type
Description
HRESET
Low
E7
Open-drain
Hard Reset—Asserting this open drain signal puts the MPC875 in
hard reset state.
SRESET
Low
C4
Open-drain
Soft Reset—Asserting this open drain line puts the MPC875 in
soft reset state.
Analog
driving
D6
Analog
Output
Hi-Z
D7
CLKOUT
Note 2
G4
EXTCLK
Hi-Z
B4
TEXP
High
B3
Output
Timer Expired—This output reflects the status of
PLPRCR[TEXPS].
ALE_A
Low
B7
Output
Address Latch Enable A—This output line is asserted when
MPC875 initiates an access to a region under the control of the
PCMCIA interface to socket A.
CE1_A
High
C15
Output
Card Enable 1 Slot A—This output signal enables even byte
transfers when accesses to PCMCIA slot A are handled under the
control of the PCMCIA interface.
CE2_A
High
D14
Output
Card Enable 2 Slot A—This output signal enables odd byte
transfers when accesses to PCMCIA slot A are handled under the
control of the PCMCIA interface.
WAIT_A
Hi-Z
D4
Input
Wait Slot A—This input signal, if asserted low, causes a delay in
the completion of a transaction on the PCMCIA controlled Slot A.
IP_A0
Hi-Z
G6
Input
Input Port A 0—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
IP_A1
Hi-Z
F5
Input
Input Port A 1—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
IP_A2
Hi-Z
D3
Input
Input Port A 2—This input signal is monitored by the MPC875 and
its value and changes are reported in the PIPR and PSCR of the
PCMCIA interface.
Name
XTAL
EXTAL
This output is one of the connections to an external crystal for the
internal oscillator circuitry.
Analog Input This line is one of the connections to an external crystal for the
(3.3 V only) internal oscillator circuitry.
Output
Clock Out—This output is the clock system frequency.
Input (3.3 V External Clock—This input is the external input clock from an
only)
external source.
IOIS16_A
I/O Device A is 16 Bits Ports Size—This input signal is monitored
by the MPC875 when a transaction under the control of the
PCMCIA interface is initiated to an I/O region in socket A of the
PCMCIA space.
IP_A3
Hi-Z
E4
Input
Input Port A 3—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-31
External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Reset
Number
Type
Description
IP_A4
Hi-Z
D2
Input
Input Port A 4—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
IP_A5
Hi-Z
E3
Input
Input Port A 5—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface
IP_A6
Hi-Z
F4
IP_A7
Hi-Z
C2
ALE_B
DSCK
See
Table 12-3
C8
Bidirectional Address Latch Enable B—This output is asserted when the
three-state MPC875 initiates an access to a region under the control of the
PCMCIA socket B interface.
Development Serial Clock—This input is the clock for the debug
port interface.
IP_B[0:1]
IWP[0:1]
VFLS[0:1]
See
Table 12-3
B8, D9
Bidirectional Input Port B 0-1—The MPC875 senses these inputs; their values
and changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Instruction Watchpoint 0-1—These outputs report the detection of
an instruction watchpoint in the program flow executed by the
core.
Visible History Buffer Flushes Status—The MPC875 outputs
VFLS[0:1] when program instruction flow tracking is required.
They report the number of instructions flushed from the history
buffer in the core.
OP0
Low
B6
Output
Output Port 0—This output signal is generated by the MPC875 as
a result of a write to the PGCRA register in the PCMCIA interface.
OP1
Low
C6
Output
Output Port 1—The MPC875 generates these outputs as a result
of a write to the PGCRA register in the PCMCIA interface.
OP2
MODCK1
STS
Hi-Z
B5
Bidirectional Output Port 2—This output is generated by the MPC875 as a
result of a write to the PGCRB register in the PCMCIA interface.
Mode Clock 1—Input sampled when PORESET is negated to
configure PLL/clock mode.
Special Transfer Start—The MPC875 drives this output to indicate
the start of an external bus transfer or an internal transaction in
show-cycle mode.
OP3
MODCK2
DSDO
Hi-Z
B2
Bidirectional Output Port 3—This output is generated by the MPC875 as a
result of a write to the PGCRB register in the PCMCIA interface.
Mode Clock 2—This input is sampled at the PORESET negation
to configure the PLL/clock mode of operation.
Development Serial Data Output—Output data from the debug
port interface.
Name
Bidirectional Input Port A 6—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
Input
Input Port A 7—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-32
Freescale Semiconductor
External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Reset
Number
Type
Description
BADDR30
REG
Hi-Z
D8
Output
Burst Address 30—This output duplicates the value of A30 when
the following is true:
• An internal master in the MPC875 initiates a transaction on the
external bus.
• An asynchronous external master initiates a transaction.
• A synchronous external master initiates a single beat
transaction.
The memory controller uses BADDR30 to increment the address
lines that connect to memory devices when a synchronous
external master or an internal master initiates a burst transfer.
Register—When an internal master initiates an access to a slave
under control of the PCMCIA interface, this signal duplicates the
value of TSIZ0/REG. When an external master initiates an
access, REG is output by the PCMCIA interface (if it must handle
the transfer) to indicate the space in the PCMCIA card being
accessed.
BADDR[28:29
]
Hi-Z
E8, C5
Output
Burst Address—Outputs that duplicate A[28:29] values when one
of the following occurs:
• An internal master in the MPC875 initiates a transaction on the
external bus.
• An asynchronous external master initiates a transaction.
• A synchronous external master initiates a single beat
transaction.
The memory controller uses these signals to increment the
address lines that connect to memory devices when a
synchronous external or internal master starts a burst transfer.
AS
Hi-Z
C7
Input
PA[15]
USBRXD
Hi-Z
P14
Bidirectional General-Purpose I/O Port A Bit 15—Bit 15 of the general-purpose
I/O port A.
USBRXD —Receive data. Input to the USB receiver from the
differential line receiver.
PA[14]
USBOE
Hi-Z
U16
Bidirectional General-Purpose I/O Port A Bit 14—Bit 14 of the general-purpose
I/O port A.
(optional:
open-drain) USBOE—Output enable. Enables the transceiver to send data on
the bus.
PA[11]
RXD4
MII1-TXD0
RMII1-TXDO
Hi-Z
R9
Bidirectional General-Purpose I/O Port A Bit 11—Bit 11 of the general-purpose
I/O port A.
(optional:
open-drain) RXD4—Receive data input for SCC4.
MII1-TXD0—Media independent interface 1, transmit data 0.
RMII1-TXD0—Reduced media-independent interface 1, transmit
data 0.
Name
Address Strobe—Input driven by an external asynchronous
master to indicate a valid address on A[0:31]. The MPC875
memory controller synchronizes AS and controls the memory
device addressed under its control.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-33
External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Reset
Number
PA[10]
MII-TXER
CLK7
TIN4
Hi-Z
R12
Bidirectional General-Purpose I/O Port A Bit 10—Bit 10 of the general-purpose
(optional:
I/O port A.
open-drain)3 MII-TXD0- Media independent interface 1, transmit error.
CLK7—One of eight clock inputs that can be used to clock SCCs
and SMCs.
TIN4—Timer 4 external clock input.
PA[7]
CLK1
TIN1
BRGO1
Hi-Z
R11
Bidirectional General-Purpose I/O Port A Bit 7—Bit 7 of the general-purpose
I/O port A
CLK1—One of eight clock inputs that can be used to clock SCCs
and SMCs.
TIN1—Timer 1 external clock.
BRGO1—Output clock of BRG1.
PA[6]
CLK2
TOUT1
Hi-Z
P11
Bidirectional General-Purpose I/O Port A Bit 6—Bit 6 of the general-purpose
I/O port A.
CLK2—One of eight clock inputs that can be used to clock SCCs
and SMCs. CLK2 can also be used as a clock source for the
BRGs.
TOUT1—Timer 1 output.
PA[4]
CTS4
MII1-TXD1
RMII1-TXD1
Hi-Z
P7
Bidirectional General-Purpose I/o Port A Bit 4—Bit 4 of the general-purpose I/O
port A.
CTS4—Clear to send modem line for SCC4.
MII1-TXD1—Media-independent interface 1, transmit data 1.
RMII1-TXD1—Reduced media-independent interface 1, transmit
data 1.
PA[3]
MII1-RXER
RMII1-RXER
BRGO3
Hi-Z
R5
Bidirectional General-Purpose I/O Port A Bit 3—Bit 3 of the general-purpose
I/O port A.
MII1-RXER—Media-independent interface 1, receive error.
RMII1-RXER—Reduced media-independent interface 1, receive
error.
BRGO3—Output clock of BRG3.
PA[2]
MII1-RXDV
RMII1-CRS_D
V
TXD4
Hi-Z
N6
Bidirectional General-Purpose I/O Port A Bit 2—Bit 2 of the general-purpose
I/O port A
MII1-RXDV—Media-independent interface 1, receive data valid
RMII1-CRS_DV—Reduced MII 1, carrier receive sense or data
valid
TXD4—Transmit data for serial channel 4.
PA[1]
MII1-RXD0
RMII1 -RXD0
BRGO4
Hi-Z
T4
Bidirectional General-Purpose I/O Port A Bit 1—Bit 1 of the general-purpose
I/O port A.
MII1-RXD0 —Media-independent interface 1, receive data 0.
RMII1-RXD0—Reduced media-independent interface 1, receive
data 0.
BRGO4—BRG4 output clock.
PA[0]
MII1-RXD1
RMII1-RXD1
TOUT4
Hi-Z
P6
Bidirectional General-Purpose I/O Port A Bit 0—Bit 0 of the general-purpose
I/O port A.
MII1-RXD1 —Media-independent interface 1, receive data 1.
RMII1-RXD1—Reduced media-independent interface 1, receive
data 1.
TOUT4—Timer 4 output.
Name
Type
Description
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-34
Freescale Semiconductor
External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Reset
Number
PB[31]
SPISEL
MII1 - TXCLK
RMII1-REFCL
K
Hi-Z
T5
Bidirectional General-Purpose I/O Port B Bit 31—Bit 31 of the general-purpose
I/O port B.
(optional:
open-drain) SPISEL—SPI slave select input.
MII1-TXCLK —Media-independent interface 1, transmit clock.
RMII1-REFCLK—Reduced media-independent interface 1,
reference clock.
PB[30]
SPICLK
Hi-Z
T17
Bidirectional General-Purpose I/O Port B Bit 30—Bit 30 of the general-purpose
I/O port B.
(optional:
open-drain) SPICLK—SPI output clock when it is configured as a master or
SPI input clock when it is configured as a slave.
PB[29]
SPIMOSI
Hi-Z
R17
Bidirectional General-Purpose I/O Port B Bit 29—Bit 29 of the general-purpose
I/O port B.
(optional:
open-drain) SPIMOSI—SPI output data when it is configured as a master or
SPI input data when it is configured as a slave.
PB[28]
SPIMISO
BRGO4
Hi-Z
R14
Bidirectional General-Purpose I/O Port B Bit 28—Bit 29 of the general-purpose
I/O port B.
(optional:
open-drain) SPIMISO—SPI input data when the MPC875 is a master; SPI
output data when it is a slave.
BRGO4—BRG4 output clock.
PB[27]
I2CSDA
BRGO1
Hi-Z
N13
Bidirectional General-Purpose I/O Port B Bit 27—Bit 27 of the general-purpose
I/O port B.
(optional:
open-drain) I2CSDA—I2C serial data pin. Bidirectional; should be configured
as an open-drain output.
BRGO1—BRG1 output clock.
PB[26]
I2CSCL
BRGO2
Hi-Z
N12
Bidirectional General-Purpose I/O Port B Bit 26—Bit 26 of the general-purpose
I/O port B.
(optional:
open-drain) I2CSCL—I2C serial clock pin. Bidirectional; should be configured
as an open-drain output.
BRGO2—BRG2 output clock.
PB[25]
SMTXD1
Hi-Z
U13
Bidirectional General-Purpose I/O Port B Bit 25—Bit 25 of the general-purpose
I/O port B.
(optional:
open-drain) SMTXD1—SMC1 transmit data output.
PB[24]
SMRXD1
Hi-Z
T12
Bidirectional General-Purpose I/O Port B Bit 24—Bit 24 of the general-purpose
I/O port B.
(optional:
open-drain) SMRXD1—SMC1 receive data input.
PB[23]
SMSYN1
SDACK1
Hi-Z
U12
Bidirectional General-Purpose I/O Port B Bit 23—Bit 23 of the general-purpose
I/O port B.
(optional:
open-drain) SMSYN1—SMC1 external sync input.
SDACK1—SDMA acknowledge 1 output that is used as a
peripheral interface signal for IDMA emulation, or as a CAM
interface signal for Ethernet.
PB[19]
RTS4
MII1-RXD3
Hi-Z
T11
Bidirectional General-Purpose I/O Port B Bit 19—Bit 19 of the general-purpose
I/O port B.
(optional:
open-drain) RTS4—Request to send modem line for SCC4.
MII1-RXD3 —Media-independent interface 1, receive data 3.
Name
Type
Description
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
12-35
External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Reset
Number
PC[15]
DREQ0
L1ST1
Hi-Z
R15
Bidirectional General-Purpose I/O Port C Bit 15—Bit 15 of the general-purpose
I/O port C.
DREQ0—IDMA channel 1 request input.
L1ST1—One of four output strobes that can be generated by the
serial interface.
PC[13]
MII1-TXD3
SDACK1
Hi-Z
U9
Bidirectional General-Purpose I/O Port C Bit 13—Bit 13 of the general-purpose
I/O port C.
MII1-TXD3—Media-independent interface 1, transmit data 3.
SDACK1—SDMA acknowledge 1 output that is used as a
peripheral interface signal for IDMA emulation or as a CAM
interface signal for Ethernet.
PC[12]
MII1-TXD2
TOUT1
Hi-Z
T15
Bidirectional General-Purpose I/O Port C Bit 12—Bit 12 of the general-purpose
I/O port C.
MII1-TXD2—Media-independent interface 1, transmit data 2.
TOUT1—Timer 1 output.
PC[11]
USBRXP
Hi-Z
P12
Bidirectional General-Purpose I/O Port C Bit 11—Bit 11 of the general-purpose
I/O port C.
USBRXP—USB receive - gated version of D+.
PC[10]
USBRXN
TGATE1
Hi-Z
U11
Bidirectional General-Purpose I/O Port C Bit 10—Bit 10 of the general-purpose
I/O port C.
USBRXN—USB receive - gated version of D-.
TGATE1—Timer 1/timer 2 gate signal
PC[7]
CTS4
L1TSYNCB
USBTXP
Hi-Z
T10
Bidirectional General-Purpose I/O Port C Bit 7—Bit 7 of the general-purpose
I/O port C.
CTS4—Clear to send modem line for SCC4.
L1TSYNCB—Transmit sync input for serial interface TDMb.
USBTXP—USB transmit +.
PC[6]
CD4
L1RSYNCB
USBTXN
Hi-Z
P10
Bidirectional General-Purpose I/O Port C Bit 6—Bit 6 of the general-purpose
I/O port C.
CD4—Carrier detect modem line for SCC4.
L1RSYNCB—Receive sync input for the serial interface TDMb.
USBTXN—USB transmit -.
PD[8]
RXD4
MII-MDC
Hi-Z
T3
Bidirectional General-Purpose I/O Port D Bit 8—Bit 8 of the general-purpose
I/O port D.
RXD4—Receive data for serial channel 4.
MII-MDC—Media-independent interface management data clock.
RMII-MDC—Reduced media-independent interface management
data clock.
PE31
CLK8
L1TCLKB
MII1-RXCLK
Hi-Z
P9
Bidirectional General-Purpose I/O Port E Bit 31
CLK8—One of eight clock inputs that can be used to clock SCCs
(optional:
open-drain) and SMCs.
L1TCLKB—Transmit clock for the serial interface TDMb.
MII-RXCLK—Media-independent interface receive clock
PE30
L1RXDB
MII1-RXD2
Hi-Z
R8
Bidirectional General-Purpose I/O Port E Bit 30
L1RXDB—Receive data input for the serial interface TDMb.
(optional:
open-drain) MII1-RXD2 —Media-independent interface 1, receive data 2.
Name
RMII-MDC
Type
Description
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-36
Freescale Semiconductor
External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Reset
Number
PE29
MII2-CRS
Hi-Z
U7
Bidirectional General-Purpose I/O Port E Bit 29
MII2-CRS —Media-independent interface 2, carrier receive sense
(optional:
open-drain)
PE28
TOUT3
MII2-COL
Hi-Z
R7
Bidirectional General-Purpose I/O Port E Bit 28
TOUT3—Timer 3 output.
(optional:
open-drain) MII2-COL—Media-independent interface 2 collision
PE27
L1RQB
MII2-RXER
RMII2-RXER
Hi-Z
T6
Bidirectional General-Purpose I/O Port E Bit 27
L1RQB—D-channel request signal for serial interface TDMb.
(optional:
open-drain) MII2-RXER —Media-independent interface 2, receive error.
RMII2-RXER—Reduced media-independent interface 2, receive
error.
PE26
L1CLKOB
MII2-RXDV
RMII2-CRS_D
V
Hi-Z
T2
Bidirectional General-Purpose I/O Port E Bit 26
L1CLKOB—Clock output from the serial interface TDMb.
(optional:
open-drain) MII2-RXDV—Media-independent interface 2, receive data valid.
RMII2-CRS_DV—Reduced media-independent interface 2,
carrier receive sense or data valid.
PE25
RXD4
MII2-RXD3
L1ST2
Hi-Z
R4
Bidirectional General-Purpose I/O Port E Bit 25
RXD4—Receive data input for SCC4.
(optional:
open-drain) MII2-RXD3—Media-independent interface 2, receive data 3.
L1ST2—One of four output strobes that can be generated by the
serial interface.
PE24
SMRXD1
BRGO1
MII2-RXD2
Hi-Z
U8
Bidirectional General-Purpose I/O Port E Bit 24
SMRXD1—SMC1 receive data input.
(optional:
open-drain) BRGO1—Output clock of BRG1.
MII2-RXD2—Media-independent interface 2, receive data 2.
PE23
TXD4
MII2-RXCLK
L1ST1
Hi-Z
U4
Bidirectional General-Purpose I/O Port E Bit 23
TXD4—Transmit data for serial channel 4.
(optional:
open-drain) MII2-RXCLK—Media-independent interface 2, receive clock.
L1ST1—One of four output strobes that can be generated by the
serial interface.
PE22
TOUT2
MII2-RXD1
RMII2-RXD1
SDACK1
Hi-Z
P4
Bidirectional General-Purpose I/O Port E Bit 22
TOUT2—Timer 2 output.
(optional:
open-drain) MII2-RXD1—Media-independent interface 2, receive data 1.
RMII2-RXD1—Reduced media-independent interface 2, receive
data 1.
SDACK1—SDMA acknowledge 1 output that is used as a
peripheral interface signal for IDMA emulation, or as a CAM
interface signal for Ethernet.
PE21
TOUT1
MII2-RXD0
RMII2-RXD0
Hi-Z
T9
Bidirectional General-Purpose I/O Port E Bit 21
TOUT1—Timer 1 output.
(optional:
open-drain) MII2-RXD0—Media-independent interface 2, receive data 0.
RMII2-RXD0—Reduced media-independent interface 2, receive
data 0.
PE20
MII2-TXER
Hi-Z
U3
Bidirectional General-Purpose I/O Port E Bit 20
MII2-TXER - Media independent interface 2, transmit error.
(optional:
open-drain)
Name
Type
Description
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Freescale Semiconductor
12-37
External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Reset
Number
PE19
L1TXDB
MII2-TXEN
RMII2-TXEN
Hi-Z
R6
Bidirectional General-Purpose I/O Port E Bit 19
L1TXDB—Transmit data output for the serial interface TDMb
(optional:
open-drain) MII2-TXEN—Media-independent interface 2, transmit enable
RMII2-TXEN—Reduced media-independent interface 2, transmit
enable
PE18
SMTXD1
MII2-TXD3
Hi-Z
M5
Bidirectional General-Purpose I/O Port E Bit 18
SMTXD1—SMC1 transmit data output
(optional:
open-drain) MII2-TXD3—Media-independent interface 2, transmit data 3
PE17
TIN3
CLK5
BRGO3
SMSYN1
MII2-TXD2
Hi-Z
T8
Bidirectional General-Purpose I/O Port E Bit 17
TIN3—Timer 3 external clock input
(optional:
open-drain) CLK5—One of eight clock inputs that can be used to clock SCCs
and SMCs
BRGO3—Output clock of BRG3
SMSYN1—SMC1 external sync input
MII2-TXD2—Media-independent interface 2, transmit data 2
PE16
L1RCLKB
CLK6
MII2-TXCLK
RMII2-REFCL
K
Hi-Z
U6
Bidirectional General-Purpose I/O Port E Bit 16
L1RCLKB—Receive clock for the serial interface TDMb.
(optional:
open-drain) CLK6—One of eight clock inputs that can be used to clock SCCs
and SMCs
MII2-TXCLK—Media-independent interface 1, transmit clock
RMII2-REFCLK—Reduced media-independent interface 1,
reference clock
PE15
TGATE1
MII2-TXD1
RMII2-TXD1
Hi-Z
T7
Bidirectional General-Purpose I/O Port E Bit 15
TGATE1—Timer 1/timer 2 gate signal
MII2-TXD1—Media-independent interface 2, transmit data 1
RMII2-TXD1—Reduced media-independent interface 2, transmit
data 1
PE14
MII2-TXD0
RMII2-TXD0
Hi-Z
P8
Bidirectional General-Purpose I/O Port E Bit 14
MII2-TXD0—Media-independent interface 2, transmit data 0
RMII2-TXD0—Reduced media-independent interface 2, transmit
data 0
TCK
DSCK
Hi-Z
R13
Input
Provides clock to scan chain logic or for the development port
logic
Name
Type
Description
TMS
Pulled up
T14
Input
Controls the scan chain test mode operations
TDI
DSDI
Pulled up
T13
Input
Input serial data for either the scan chain logic or the development
port and determines the operating mode of the development port
at reset
TDO
DSDO
Low
P13
Output
Output serial data for either the scan chain logic or the
development port
TRST
Pulled up3
U14
Input
Test reset for the JTAG scan chain logic
MII1_CRS
Hi-Z
U10
Input
MII1_CRS —Media-independent interface 1, carrier receive
sense
MII_MDIO
Hi-Z
M13
MII1_TXEN
Low
U5
Bidirectional MII_MDIO —Media-independent interface management data
Output
MII1_TXEN —Media-independent interface 1, transmit enable
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External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Name
MII1_COL
Hard
Reset
Number
Type
Hi-Z
R10
Input
MII1_COL —Media-independent interface 1, collision
See
Figure 12-3
Power
VDDL—Power supply for the internal logic
VDDH—Power supply for the I/O buffers and certain parts of the
clock control
VDDSYN—Power supply of the PLL circuitry
GND—Ground for circuits, except for the PLL circuitry
VSSSYN, VSSSYN1—Ground for the PLL circuitry
Power supply
Description
1
Pulled low if RSTCONF pulled down.
High until DPLL locked, then oscillates.
3
See Section 11.4, “TRST Considerations,” and Section 54.6, “Recommended TAP Configuration.”
2
12.3
Reset Behavior
The reset behavior of a subset of multiple-function pins depends on which signal function is active. The
SIU module configuration register (SIUMCR) programming determines which signal functions of this pin
subset are activated at reset; see Section 10.4.2, “SIU Module Configuration Register (SIUMCR).” Some
(but not all) of the SIUMCR default values are determined by the user-controlled hardware reset
configuration word; see Section 11.3.1.1, “Hard Reset Configuration Word.” When HRESET (or
PORESET) is asserted, these pins immediately begin functioning as the signals selected in the SIUMCR.
The behavior of these signals is shown in Table 12-3.
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External Signals
Table 12-3. Configuration-Dependent Signal Behavior During Reset
Signal Function Determined at Reset by
Pin
SRESET
Previous
programming of
SIUMCR
SIUMCR default values only
BDIP/GPL_B5
BDIP: high impedance
GPL_B5: high1
RSV/IRQ2
IRQ2: high impedance
RSV: high 1
CR/IRQ3
IRQ3: high impedance
CR: high 1
KR/RETRY/IRQ4/SPKROUT
FRZ/IRQ6
SIUMCR default values as
driven by the hard reset
configuration word
1
Signal Behavior
HRESET (or PORESET)
ALE_B/DSCK/AT1
IP_B[0:1]/IWP[0:1]/VFLS[0:1]
IRQ4: high impedance
KR/RETRY: high impedance 1
SPKROUT: low 1
FRZ: low
IRQ6: high impedance 1
ALE_B: low
DSCK/AT1: high impedance
IP_B[0:1]: high impedance
IWP[0:1]: high
VFLS[0:1]: low
IP_B3/IWP2/VF2
IP_B3: high impedance
IWP2: high
VF2: low
IP_B4/LWP0/VF0
IP_B4: high impedance
LWP0: high
VF0: low
IP_B5/LWP1/VF1
IP_B5: high impedance
LWP1: high
VF1: low
After a hard reset, this signal function is actually inactive until the user selects the function by programming the
SIUMCR.
12.4
Active Pull-Up Buffers
An active pull-up buffer is a special variety of a bidirectional three-state buffer with the following
properties:
• When enabled as an output and driving low, it behaves as a normal output driver (that is, the pin is
constantly driven low).
• When enabled as an output and driving high, it drives high until an internal detection circuit
determines that the output has reached the logic high threshold and then stops driving (that is, the
pin switches to high impedance).
• When disabled as an output or functioning as an input, it is not driven.
Due to the behavior of the buffer when being driven high, a pull-up resistor is required externally to
function as a ‘bus keep’ for these shared signals in periods when no drivers are active and to keep the buffer
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Freescale Semiconductor
External Signals
from oscillating when the buffer is driving high. This is because the buffer reactivates if the voltage ever
dips below the logic high threshold while the buffer is enabled as an output. Furthermore, the external logic
must not attempt to drive these signals low while active pull-up buffers are enabled as outputs because the
buffers will reactivate and drive high. This would result in a buffer fight and possible damage to the
MPC885, the system, or both.
Figure 12-5 compares three-state buffers and active pull-up buffers graphically in general terms. It makes
no implication as to which edges trigger which events for any particular signal.
Legend:
1-Drive high on one edge
2-Switch to Hi-Z on later edge
3-Pull-up resistor maintains
logic high state
3
Three-State
Buffer
1
2
Legend:
5
3
Active
Pull-Up
Buffer
1 2
4
1-Drive high on one edge
2-Switch to Hi-Z when
threshold voltage
(Voh + margin) is reached
3-Pull-up resistor maintains
logic high state
4-Disable buffer as output
5-Pull-up resistor maintains
logic high state; other
driver can drive signal
Note: Events 1 and 4 can be in quick succession.
Figure 12-5. Three-State Buffers and Active Pull-Up Buffers
Table 12-4 summarizes when active pull-up drivers are enabled as outputs.
Table 12-4. Active Pull-Up Resistors Enabled as Outputs
Signal
TS, BB
Description
When the MPC885 is the external bus master throughout the entire bus cycle
BI
When the MPC885 memory controller responds to the access on the external bus throughout the entire bus
cycle
TA
When the MPC885 memory controller responds to the access on the external bus:
• For chip-selects controlled by the GPCM set for external TA, the TA buffer is not enabled as an output.
• For chip-selects controlled by the GPCM set to terminate in n wait-states, TA is enabled as an output on
cycle (n-1) and driven high, then is driven low on cycle n, terminating the bus transaction. External logic
can drive TA at any point before this, thus terminating the cycle early. (For example, assume the GPCM
is programmed to drive TA after 15 cycles. If external logic drives TA before 14 clocks have elapsed then
the TA is accepted by the processor as a cycle termination.)
• For UPM-controlled chip-selects, the TA buffer is enabled as an output throughout the entire bus cycle.
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12-41
External Signals
The purpose of active pull-up buffers is to allow access to zero wait-state logic that drives a shared signal
on the clock cycle immediately following a cycle in which the signal is driven by the MPC885. In other
words, it eliminates the need for a bus turn-around cycle.
12.5
Internal Pull-Up and Pull-Down Resistors
The TDI/DSDI, TMS, and TRST pins have internal pull-up resistors.
If RSTCONF is pulled down during hardware reset (initiated by HRESET or PORESET), the data bus
D[0:31] is pulled down with internal pull-down resistors. These internal pull-down resistors are to provide
a logic-zero default for these pins when programming the hard reset configuration word (see
Section 11.3.1.1, “Hard Reset Configuration Word”). These internal pull-down resistors are disconnected
after HRESET is negated.
No other pins have internal pullups or pulldowns.
Resistance values for internal pull-up and pull-down resistors are not specified because their values may
vary due to process variations and shrinks in die size, and they are not tested. Typical values are on the
order of 5 kΩ but can vary by approximately a factor of 2.
12.6
Recommended Basic Pin Connections
The following sections provide recommended pin connections.
12.6.1
Reset Configuration
Some external pin configurations are determined at reset by the hard reset configuration word. Thus, some
decisions regarding system configuration (for example, location of BDM pins) should be made before
required application of pull-up and pull-down resistors can be determined.
RSTCONF should be grounded if the hard reset configuration word is used to configure the MPC885 or
should be connected to VCC if the default configuration is used.
Pull-up resistors should not be used on D[0:31] to set the hard reset configuration word, as the values of
the internal pull-down resistors are not specified or guaranteed. To change a data bus signal from its default
logic low state during reset, actively drive that signal high.
MODCK[1:2] must be used to determine the default clocking mode for the MPC885. After power-on reset,
the MODCK[1:2] pins change function and become outputs. Thus, if these alternate functions are also
desired, then the MODCK[1:2] configuration should be set with three-state drivers that turn off after
PORESET is negated. However, if the MODCK[1:2] pins alternate output functions are not used in the
system, they can be configured with pull-up and pull-down resistors.
12.6.1.1
Bus Control Signals and Interrupts
Signals with open-drain buffers and active pull-up buffers (HRESET, SRESET, TEA, TS, TA, BI, and BB)
must have external pull-up resistors.
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External Signals
Some other input signals do not require a pull-up resistor, as they may be actively driven by external logic.
However, if they are not used externally, or if the external logic connected to them is not always actively
driving, they may need external pull-up resistors to keep them negated. These signals include the
following:
• PORESET
• AS
• CR/IRQ3
• KR/RETRY/IRQ4/SPKROUT (if configured as KR/RETRY or IRQ4)
• Any IRQx (if configured as IRQx)
• BR (if the internal bus arbiter is used)
• BG (if an external bus arbiter is used)
12.6.2
JTAG and Debug Ports
Recommendations on configuration of the JTAG pins (including TMS, TRST, TDI, TDO, and TCK) are
made in Section 54.6, “Recommended TAP Configuration.” See also Section 11.4, “TRST
Considerations.”
TCK/DSCK or ALE_B/DSCK/AT1 (depending on the configuration of the DSCK function) should be
connected to ground through a pull-down resistor to disable debug mode as a default. When required, an
external debug-mode controller can actively drive this signal high to put the processor into debug mode.
The two signals TCK/DSCK and TDI/DSDI have special requirements to keep them from oscillating when
unused (see Section 12.5, “Internal Pull-Up and Pull-Down Resistors”).
12.6.3
Unused Inputs
In general, pull-up resistors should be used on any unused inputs to keep them from oscillating. For
example, if PCMCIA is not used, the PCMCIA input pins (WAIT_A, WAIT_B, IP_A[0:8], IP_B[0:8])
should have external pull-up resistors. However, unused pins of port A, B, C, or D can be configured as
outputs, and, if they are configured as outputs they do not require external terminations.
12.6.4
Unused Outputs
Unused outputs can be left unterminated.
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External Signals
12.7
Signal States During Reset
During a reset, the MPC885 signals behave as shown in Table 12-5.
Table 12-5. General Signal Behavior During Reset
Reset Signal
Signal Behavior
HRESET or PORESET Bus signals are high impedance.
Port I/O signals are configured as inputs and are, therefore, high impedance.
Memory controller signals are driven to their inactive state. Refresh stops.
(For the behavior of specific signals during a hard reset, see Section 12.1.2,
“MPC885/MPC880 System Bus Signals.”)
SRESET
The current bus cycle aborts. Bus signals revert to their inactive state. (For example, BR or
BG negate, and address and data signals become high impedance.)
Memory controller aborts the current access, and signals drive to their inactive state (high).
Refresh continues.
Port I/O signals are not reconfigured (maintain previous programming).
SIU pin configuration maintains previous programming; see Table 12-3.
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Freescale Semiconductor
Chapter 13
External Bus Interface
The MPC885 bus is a synchronous, burstable bus that can support multiple masters. Signals driven on this
bus are required to make the setup and hold time relative to the bus clock’s rising edge. The MPC885
architecture supports byte, half-word, and word operands allowing access to 8-, 16-, and 32-bit data ports
through the use of synchronous cycles controlled by the size outputs (TSIZ0, TSIZ1). Access to 16- and
8-bit ports is done for slaves controlled by the memory controller.
13.1
Features
The MPC885 bus interface features are listed as follows:
• 32-bit address bus with transfer size indication
• 32-bit data bus
• Dynamic bus sizing to 32-, 16-, or 8-bit ports accessed through the memory controller
• TTL-compatible interface
• Bus arbitration supported optionally by internal or external logic
• Bus arbitration logic on-chip supports an external master with programmable priority
• Compatible with PowerPC architecture
• Easy to interface to slave devices
• Bus is synchronous (all signals are referenced to rising edge of bus clock)
13.2
Bus Transfer Overview
The bus transfers information between the MPC885 and external memory or a peripheral device. External
devices can accept or provide 8, 16, and 32 bits in parallel and must follow the handshake protocol
described in this section. The maximum number of bits accepted or provided during a bus transfer is
defined as port width.
The MPC885’s address bus specifies the address for the transfer and its data bus transfers the data. Control
signals indicate the beginning of the cycle and the type of cycle, as well as the address space and size of
the transfer. The selected device controls cycle length with signal(s) used to terminate the cycle. A strobe
signal for the address bus indicates the validity of the address and gives data timing information. The
MPC885 bus is synchronous, therefore, the bus and control input signals must be timed to setup and hold
times relative to the rising edge of the clock. At minimum, single-beat bus cycles can be completed in two
clock cycles.
Furthermore, for all inputs, the MPC885 latches the input’s level during a sample window, shown in
Figure 13-1, around the rising clock edge. To ensure that an input signal is recognized on a specific rising
clock edge, that input must be stable during the sample window. If an input changes during the window,
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13-1
External Bus Interface
the level recognized by the MPC885 is unpredictable; however, the MPC885 always resolves the latched
level to either a logical high or low before using it. For deterministic operation, all input signals must obey
the protocols described in this chapter in addition to meeting input setup and hold times.
Input Hold Time
Input Setup Time
Clock
Signal
Sample
Window
Figure 13-1. Input Sample Window
TSIZ0 and TSIZ1 indicate the number of bytes remaining to be transferred during an operand cycle
(consisting of one or more bus cycles) and are driven with the address type signals at the beginning of a
bus cycle. These signals are valid at the rising edge of the clock in which the transfer start signal (TS) is
asserted.
13.3
Bus Interface Signal Descriptions
Figure 13-3 shows the bus signals for the MPC885.
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13-2
Freescale Semiconductor
External Bus Interface
32
1
1
2
4
1
1
1
1
1
A[0:31]
R/W
BURST
TSIZ[0:1]
AT[0:3]
PTR
RSV
STS
BDIP
TS
MPC885
1
1
32
1
1
1
1
1
1
Address
and
Transfer
Attributes
KR/RETRY
CR
Transfer
Start
Reservation
Protocol
D[0:31]
Data
BI
TA
TEA
Transfer
Cycle
Termination
BR
BG
BB
Arbitration
Figure 13-2. MPC885 Bus Signals
Table 13-1 describes each signal; detailed descriptions can be found in subsequent sections.
Table 13-1. MPC885 Signal Overview
Signal
Pins
I/O1
Description
Address and Transfer Attributes
A[0:31]
Address Bus
32
RD/WR
Read/Write
1
O
Driven by the MPC885 when it owns the external bus. Specifies the physical address of
the bus transaction. Can change during a transaction when controlled by the memory
controller.
I
Sampled by the MPC885 when an external device initiates a transaction and the
memory controller was configured to handle external master accesses.
O
Driven by the MPC885 along with the address when it owns the external bus. Driven high
indicates that a read access is in progress. Driven low indicates that a write access is in
progress.
I
Sampled by the MPC885 when an external device initiates a transaction and the
memory controller was configured to handle external master accesses.
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13-3
External Bus Interface
Table 13-1. MPC885 Signal Overview (continued)
Signal
BURST
Burst Transfer
TSIZ[0:1]
Transfer Size
Pins
I/O1
Description
1
O
Driven by the MPC885 along with the address when it owns the external bus. Driven low
indicates that a burst transfer is in progress. Driven high indicates that the current
transfer is not a burst.
I
Sampled by the MPC885 when an external device initiates a transaction and the
memory controller was configured to handle external master accesses.
O
Driven by the MPC885 along with the address when it owns the external bus. Specifies
the data transfer size for the transaction.
I
Sampled by the MPC885 when an external device initiates a transaction and the
memory controller was configured to handle external master accesses.
2
AT[0:3]
Address Type
4
O
Driven by the MPC885 along with the address when it owns the external bus. Indicates
additional information about the address on the current transaction.
RSV
Reservation
Transfer
1
O
Driven by the MPC885 along with the address when it owns the external bus. Indicates
additional information about the address on the current transaction.
PTR
Program Trace
1
O
Driven by the MPC885 along with the address when it owns the external bus. Indicates
additional information about the address on the current transaction.
BDIP
Burst Data in
Progress
1
O
Driven by the MPC885 when it owns the external bus as part of the burst protocol.
Asserted indicates that the second beat in front of the current one is requested by the
master. Negated before the burst transfer ends to abort the burst data phase.
Transfer Start
TS
Transfer Start
STS
Special Transfer
Start
1
1
O
Driven by the MPC885 when it owns the external bus. Indicates the start of a transaction
on the external bus.
I
Sampled by the MPC885 when an external device initiates a transaction and the
memory controller was configured to handle external master accesses.
O
Driven by the MPC885 when it owns the external bus. Indicates the start of a transaction
on the external bus or signals the beginning of an internal transaction in show cycle
mode.
Reservation Protocol
KR/RETRY
Kill Reservation/
Retry
1
I
If the core initiates a bus cycle by executing a stwcx. to a nonlocal bus on which the
memory reservation is lost, the nonlocal bus uses this signal to back-off the cycle. See
Section 13.4.9, “Memory Reservation.”
For regular transactions, the slave device drives this signal to indicate that the MPC885
must relinquish the bus and retry the cycle.
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External Bus Interface
Table 13-1. MPC885 Signal Overview (continued)
Signal
Pins
I/O1
Description
Data
D[0:31]
Data Bus
32
The data bus has the following byte lane assignments:
Data Byte
Byte Lane
D[0:7]
0
D[8:15]
1
D[16:23]
2
D[24:31]
3
O
Driven by the MPC885 when it is external bus master and it initiated a write transaction
to a slave device. For single-beat transactions, the byte lanes not selected for the transfer
by the A[30:31] and TSIZ[0:1] will not supply valid data.
I
Driven by the slave in a read transaction. For single-beat transactions, the byte lanes not
selected for the transfer by the A[30:31] and TSIZ[0:1] will not be sampled by the
MPC885
Transfer Cycle Termination
TA
Transfer
Acknowledge
1
TEA
Transfer Error
Acknowledge
1
BI
Burst Inhibit
1
I
Driven by the slave device to which the current transaction is addressed. Indicates that
the slave received the data on the write cycle or returned data on the read cycle. If the
transaction is a burst, TA should be asserted for each beat.
O
Driven by the MPC885 when the slave device is controlled by the on-chip memory
controller or PCMCIA interface.
I
Driven by the slave device to which the current transaction is addressed. Indicates that
an error condition occurred during the bus cycle.
O
Driven by the MPC885 when the internal bus monitor detects a bus error.
I
Driven by the slave device to which the current transaction was addressed. Indicates that
the current slave does not support burst mode.
O
Driven by the MPC885 when the on-chip memory controller controls the slave.
Arbitration
BR
Bus Request
BG
Bus Grant
1
1
I
Asserting BR when the internal arbiter is enabled indicates an external master is
requesting the bus.
O
The MPC885 drives BR when the internal arbiter is disabled.
O
When the internal arbiter is enabled, the MPC885 asserts BG to indicate that an external
master may assume bus mastership and begin a bus transaction. The device requesting
bus mastership should qualify BG to ensure it is the bus owner:
Qualified BG = BG & ~BB
I
When the internal arbiter is disabled, BG is sampled and properly qualified by the
MPC885 when an external bus transaction is to be executed by the chip.
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External Bus Interface
Table 13-1. MPC885 Signal Overview (continued)
Signal
Pins
I/O1
Description
1
O
When the internal arbiter is enabled, the MPC885 asserts BB to indicate it is bus master.
When the internal arbiter is disabled, the MPC885 asserts BB after the external arbiter
granted mastership to the chip and it is ready to start the transfer.
I
When the internal arbiter is enabled, the MPC885 samples this signal to get indication
of when the external master ended its bus tenure (BB negated).
When the internal arbiter is disabled, the BB is sampled, to properly qualify the BG line,
when an external bus transaction is to be executed by the chip.
BB
Bus Busy
1
O= Output from the MPC885; I= Input to the MPC885
13.4
Bus Operations
This section provides a functional description of the system bus, the signals that control it, and the bus
cycles provided for data transfers. It also describes error conditions, bus arbitration, and the reset
operation. The MPC885 generates a system clock output (CLKOUT), which directly sets the bus interface
operation frequency. Internally, the MPC885 uses a phase-lock loop (PLL) circuit to generate a master
clock for all core circuitry (including the bus interface), which is phase-locked to CLKOUT.
MPC885 bus interface signals are specified with respect to the rising edge of the external CLKOUT and
are guaranteed to be sampled as inputs or changed as outputs with respect to that edge. Because the same
clock edge is used for driving or sampling bus signals, clock skew may occur between various modules in
a system due to routing or the use of multiple clock lines. The system must handle any clock skew
problems that could occur as a result of layout, lead length, and physical routing.
13.4.1
Basic Transfer Protocol
The basic transfer protocol defines the sequence of actions required for a complete MPC885 bus
transaction. Figure 13-3 shows a simplification of the basic transfer protocol.
Arbitration
Address transfer
Data transfer
Termination
Figure 13-3. Basic Transfer Protocol
•
•
•
•
Arbitration—A device requests bus access
Address phase—The address and the transfer attributes are generated.
Data phase—Any data to be transferred is transferred. The data phase may transfer a single beat of
data (4 bytes or less) for nonburst operations, a 4-beat data burst (4 × 4 bytes), an 8-beat data burst
(8 × 2 bytes), or a 16-beat data burst (16 × 1 bytes).
Termination—The transfer completes successfully or it was aborted.
13.4.2
Single-Beat Transfer
During the data transfer, the master writes data to the slave or reads data from the slave. On a write cycle,
the master drives the data as soon as it can, but not before the cycle after the address transfer phase. The
master must consider the one dead clock cycle switching between drivers to avoid electrical contention.
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The master can stop driving the data bus as soon as it samples TA asserted on the rising edge of CLKOUT.
On a read cycle the master accepts the data bus contents as valid at the rising edge of CLKOUT in which
TA is sampled asserted.
13.4.2.1
Single-Beat Read Flow
The basic read cycle begins with a bus arbitration, followed by the address transfer, then the data transfer.
The following flow and timing diagrams show the handshakes applicable to the fixed transaction protocol.
Figure 13-4 maps the flow of a single-beat read cycle.
MASTER
SLAVE
Bus Request (BR)
Receives Bus Grant (BG) from arbiter
Asserts Bus Busy (BB) if no other master is driving
Asserts Transfer Start (TS)
Drives address and attributes
Receives Address
Returns data
Asserts Transfer Acknowledge (TA)
Receives data
Figure 13-4. Basic Flow Diagram of a Single-Beat Read Cycle
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External Bus Interface
Figure 13-5 shows the basic timing for a single-beat read cycles with no wait states.
CLKOUT
BR
Receive BG and BB negated
BG
Assert BB, drive address and assert TS
BB
A[0:31]
R/W
TSIZ[0:1], AT[0:3]
BURST
TS
Data
TA
Data is Valid
Figure 13-5. Basic Timing: Single-Beat Read Cycle, Zero Wait States
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External Bus Interface
Figure 13-6 demonstrates the basic timing of a single-beat read cycle with one wait state.
CLKOUT
BR
Receive BG and BB negated
BG
Assert BB, drive address and assert TS
BB
A[0:31]
R/W
TSIZ[0:1], AT[0:3]
BURST
TS
Data
TA
Wait State
Data is Valid
Figure 13-6. Basic Timing: Single-Beat Read Cycle, One Wait State
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External Bus Interface
13.4.2.2
Single-Beat Write Flow
The basic write cycle begins with a bus arbitration, followed by the address transfer, then the data transfer.
The following flow and timing diagrams show the handshakes as applicable to the fixed transaction
protocol. Figure 13-7 maps the flow of a single-beat write cycle.
MASTER
SLAVE
Bus Request (BR)
Receives Bus Grant (BG) from arbiter
Asserts Bus Busy (BB) if no other master is driving
Asserts Transfer Start (TS)
Drives address and attributes
Drives data
Asserts Transfer Acknowledge (TA)
Interrupts data driving
Figure 13-7. Basic Flow of a Single-Beat Write Cycle
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External Bus Interface
The timing chart in Figure 13-8 shows the basic timing of a single-beat write cycle with no wait states.
CLKOUT
BR
Receive BG and BB negated
BG
Assert BB, drive address and assert TS
BB
A[0:31]
R/W
TSIZ[0:1], AT[0:3]
BURST
TS
Data
TA
Data is sampled
Figure 13-8. Basic Timing: Single-Beat Write Cycle, Zero Wait States
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External Bus Interface
Figure 13-9 shows the basic time of a single-beat write cycle with one wait state.
CLKOUT
BR
Receive BG and BB negated
BG
BB
Assert BB, drive address and assert TS
A[0:31]
R/W
TSIZ[0:1], AT[0:3]
BURST
TS
Data
TA
Wait State
Data is Sampled
Figure 13-9. Basic Timing: Single-Beat Write Cycle, One Wait State
The general case of single-beat transfers assumes that external memory has a 32-bit port size. As
demonstrated in Figure 13-10, the MPC885 provides an effective mechanism for interfacing with 16- and
8-bit port size memories by allowing transfers to these devices when they are controlled by the internal
memory controller.
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External Bus Interface
CLKOUT
BR
BG
BB
A[0:31]
A
A+2
00
10
R/W
TSIZ[0:1]
BURST
TS
STS
ABCDEFGH
Data
EFGHEFGH
TA
PS
10
Figure 13-10. Basic Timing: Single-Beat, 32-Bit Data Write Cycle, 16-Bit Port Size
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External Bus Interface
13.4.3
Burst Transfers
The MPC885 or other synchronous external bus devices use burst transfers to access 16-byte operands. A
burst accesses a 16-byte block aligned to a 16-byte memory boundary by supplying a starting address that
points to one of the words and requiring the memory device to sequentially drive/sample each word on the
data bus. The selected slave device must internally increment A28 and A29 (and A30 in the case of a 16-bit
port size slave device) of the supplied address for each transfer, causing the address to wrap around at the
end of the four-word block. For slaves controlled by the memory controller, the MPC885 increments the
address on A[28:31] or BADDR[28:30].
Address and transfer attributes supplied by the master bus remain stable during the transfers; the selected
device terminates each transfer by asserting TA after each word transferred on the data bus. The MPC885
also supports burst-inhibited transfers for slave devices that do not support bursting. For this type of cycle,
the selected slave device supplies/samples the address of the first word of the burst and asserts the
burst-inhibit signal (BI) with TA for the first transfer of the burst access. The MPC885 responds by
terminating the burst and accessing the rest of the 16-byte block, using three read/write cycles (each one
for a word) for a 32-bit port-width slave, seven read/write cycles for a 16-bit port-width slave, or fifteen
read/write cycles for a 8-bit port-width slave.
The general case of burst transfers assumes that external memory has a 32-bit port size. The MPC885
provides an effective mechanism for interfacing with 16-bit port size memories and 8-bit port size
memories allowing burst transfers to these devices when they are controlled by the internal memory
controller. In this case, the MPC885 attempts to initiate a burst transfer as in the normal case. If, in a cycle
before the TA is asserted for the first beat, the memory controller responds that the port size is 16-/8-bits
and that the burst is accepted, the MPC885 completes a 8-/16-beat burst. Each data beat effectively
transfers only 2/1 bytes. Note that this 8-/16-beat burst is considered an atomic transaction, so the MPC885
does not allow other unrelated master accesses or bus arbitration between transfers.
13.4.4
Burst Operations
The MPC885 burst mechanism uses additional signals to the basic protocol: BURST indicates that the
cycle is a burst cycle, burst data in progress (BDIP) indicates the duration of the burst data, and burst
inhibit (BI) indicates whether the slave supports bursts. Along with asserting TS, the master drives the
address, address attributes, and BURST signals to indicate that a burst transfer is being initiated. Slaves
that support bursting negate BI. If the slave cannot burst, it asserts BI. During the data phase of a burst
write cycle the master drives the data. The master also asserts BDIP if it intends to drive the data beat after
the current one.
When the slave has received the data, it asserts TA to indicate to the master that it is ready for the next
transfer. The master again drives the next data and asserts or negates BDIP. If the master does not intend
to drive another data beat, it negates BDIP to indicate to the slave that the next data beat is the last one in
the burst write.
Bursts performed by MPC885 internal masters are always 16 bytes. The MPC885 memory controller
responds only to fixed-length bursts (also typically programmed to be 16 bytes). Therefore, devices in an
MPC885 system should attempt only 16-byte burst transfers except for external masters with a dedicated
chip select, such as an external MPC603 that bursts to a chip select programmed for a 32-byte burst.
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During the data phase of a burst read cycle, the master receives data from the addressed slave. If the master
needs more than one data, it asserts BDIP. When the master receives the next-to-last data, it negates BDIP.
Thus, the slave stops driving new data after receiving the negation of BDIP at the rising clock edge.
In the case of 32-bit port size, the burst includes 4 beats. When the port size is 16 bits and controlled by
the internal memory controller, the burst includes 8 beats. When the port size is 8 bits and controlled by
the internal memory controller, the burst includes 16 beats. The MPC885 bus supports critical data first
access for fixed-size burst. The order of wraparound wraps back to the critical data. For example, assuming
data 2 is critical:
• Case burst of four:
data 2 → data 3 → data 0 → data 1
• Case burst of eight:
data 2 → data 3 → data 4 →......... → data 7 → data 0 → data 1
The following flow, Figure 13-11, and timing diagrams, Figure 13-12 through Figure 13-15, show the
handshakes for burst read transactions.
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External Bus Interface
MASTER
SLAVE
Bus Request (BR)
Receives Bus Grant (BG) from arbiter
Asserts Bus Busy (BB) if no other master is driving
Asserts Transfer Start (TS)
Drives address and attributes
Drives BURST asserted
Asserts Burst Data in Progress (BDIP)
Receives address
Returns data
Asserts Transfer Acknowledge (TA)
Receives data
BDIP asserted
?
No
Yes
Returns data
Asserts Transfer Acknowledge (TA)
Receives data
BDIP asserted
?
No
Yes
Returns data
Asserts Transfer Acknowledge (TA)
Receives Data
Negates Burst Data in Progress (BDIP)
BDIP asserted
?
Yes
BDIP asserted
?
Yes
Don’t drive
data
No
Returns data
Asserts Transfer Acknowledge (TA)
Receives data
Don’t drive
data
Don’t drive
data
No
Don’t drive
data
Figure 13-11. Basic Flow of a Burst-Read Cycle
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External Bus Interface
CLKOUT
BR
BG
BB
A[0:31], AT[0:3]
R/W
TSIZ[0:1]
00
BURST
TS
Last Beat
Expects Another Data
BDIP
Data
TA
PS
00
Data is
Valid
Data is
Valid
Data is
Valid
Data is
Valid
Figure 13-12. Burst-Read Cycle: 32-Bit Port Size, Zero Wait State
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External Bus Interface
CLKOUT
BR
BG
BB
A[0:31], AT[0:3]
R/W
TSIZ[0:1]
00
BURST
TS
Last Beat
Expects Another Data
BDIP
Data
TA
PS
00
Data is
Valid
Data is
Valid
Data is
Valid
Data is
Valid
Wait State
Figure 13-13. Burst-Read Cycle: 32-Bit Port Size, One Wait State
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External Bus Interface
CLKOUT
BR
BG
BB
A[0:31], AT[0:3]
R/W
TSIZ[0:1]
00
BURST
TS
Last Beat
Expects Another Data
BDIP
Data
TA
PS
00
Data is
Valid
Data is
Valid
Data is
Valid
Data is
Valid
Wait State
Figure 13-14. Burst-Read Cycle: 32-Bit Port Size, Wait States between Beats
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External Bus Interface
CLKOUT
BR
BG
BB
A[0:31], AT[0:3]
R/W
TSIZ[0:1]
00
BURST
TS
BDIP
Data
TA
PS
10
Figure 13-15. Burst-Read Cycle: 16-Bit Port Size, One Wait State between Beats
The following flow, Figure 13-16, and timing diagram, Figure 13-17, show the handshakes for a burst
write transaction.
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External Bus Interface
MASTER
SLAVE
Bus Request (BR)
Receives Bus Grant (BG) from arbiter
Asserts Bus Busy (BB) if no other master is driving
Asserts Transfer Start (TS)
Drives address and attributes
Drives BURST asserted
Drives data
Asserts burst data in progress (BDIP)
Receives address
Asserts Transfer Acknowledge (TA)
Drives data
BDIP asserted
?
No
Don’t sample
next data
Yes
Asserts Transfer Acknowledge (TA)
Drives data
BDIP asserted
?
No
Don’t sample
next data
Yes
Asserts Transfer Acknowledge (TA)
Drives data
Negates Burst Data in Progress (BDIP)
BDIP asserted
?
No
Don’t sample
next data
Yes
Asserts Transfer Acknowledge (TA)
Stops driving data
BDIP asserted
?
Yes
No
Don’t sample
next data
Figure 13-16. Basic Flow of a Burst Write Cycle
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External Bus Interface
CLKOUT
BR
BG
BB
A[0:31], AT[0:3]
R/W
TSIZ[0:1]
00
BURST
TS
Last beat
BDIP
Will drive another data
Data
TA
Data is
sampled
Data is
sampled
Data is
sampled
Data is
sampled
Figure 13-17. Burst-Write Cycle: 32-Bit Port Size, Zero Wait States
Figure 13-18 shows an attempted burst read to a slave device that does not support bursting. The slave
acknowledges the first transfer and also asserts the burst-inhibit signal (BI). The MPC885 responds by
terminating the burst and accessing the rest of the 16-byte block, using three single-beat read cycles.
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External Bus Interface
CLKOUT
BR
BG
BB
A[0:27]
A[28:29]
n
n+1 Mod 4
n+2 Mod 4
n+3 Mod 4
A[30:31]
R/W
TSIZ[0:1]
00
BURST
TS
BDIP
Data
TA
BI
Figure 13-18. Burst-Inhibit Cycle: 32-Bit Port Size
13.4.5
Alignment and Data Packing on Transfers
The MPC885 external bus supports only natural address alignment:
• Byte access can have any address alignment
• Half-word access must have A[31] = 0b0
• Word access must have A[30:31] = 0b00
• For burst accesses A[30:31] = 0b00
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External Bus Interface
Misaligned accesses performed by the core are broken into multiple bus accesses with natural alignment.
Misaligned accesses performed by external masters are not supported.
The MPC885 transfers operands through its 32-bit data port. If the transfer is controlled by the internal
memory controller, the MPC885 can support 8- and 16-bit data port sizes. The bus requires that the portion
of the data bus used for a transfer to or from a particular port size be fixed. A 32-bit port must reside on
D[0:31], a 16-bit port must reside on D[0:15], and an 8-bit port must reside on D[0:7]. The MPC885
always tries to transfer the maximum amount of data on all bus cycles; for a word operation, it always
assumes that the port is 32 bits wide when beginning the cycle. Figure 13-19, Figure 13-20, Table 13-2,
and Table 13-3 use the following conventions:
• OP0 is the MSB of a word operand; OP3 is the LSB.
• The two bytes of a half-word operand are OP0 (most-significant) and OP1 or OP2
(most-significant) and OP3, depending on the address of the access.
• The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on the address of
the access.
0
31
OP0
OP1
OP0
OP1
OP2
OP3
OP2
OP3
Word
Half Word
OP0
OP1
Byte
OP2
OP3
Figure 13-19. Internal Operand Representation
Figure 13-20 shows the device connections on the data bus.
0
31
OP0
OP1
D[0:7]
OP2
D[8:15]
OP0
OP1
OP0
OP1
OP2
OP3
OP3
D[16:23]
OP2
Interface Output
Register
D[24:31]
OP3
32-Bit Port Size
16-Bit Port Size
OP0
OP1
OP2
8-Bit Port Size
OP3
Figure 13-20. Interface to Different Port Size Devices
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Table 13-2 lists the bytes required on the data bus for read cycles.
Table 13-2. Data Bus Requirements for Read Cycles
Transfer
Size
Byte
0
Half-Word
Word
1
32-Bit Port1
Address
16-Bit Port1
8-Bit Port
TSIZ[0:1]
1
0
1
0
0
A30
A31
D[0:7]
D[8:15]
D[16:D3]
D[24:31]
D[0:7]
D[8:15]
D[0:7]
0
0
OP0
—
—
—
OP0
—
OP0
0
1
—
OP1
—
—
—
OP1
OP1
1
0
—
—
OP2
—
OP2
—
OP2
1
1
—
—
—
OP3
—
OP3
OP3
0
0
OP0
OP1
—
—
OP0
OP1
OP0
1
0
—
—
OP2
OP3
OP2
OP3
OP2
0
0
OP0
OP1
OP2
OP3
OP0
OP1
OP0
Denotes a byte not required during that read cycle.
Table 13-3 lists data transfer patterns for write cycles when the MPC885 initiates accesses.
Table 13-3. Data Bus Contents for Write Cycles
Transfer
Size
Byte
Half-Word
Word
1
13.4.6
External Data Bus Pattern1
Address
TSIZ[0:1]
0
1
0
1
0
0
A30
A31
D[0:7]
D[8:15]
D[16:D3]
D[24:31]
0
0
OP0
—
—
—
0
1
OP1
OP1
—
—
1
0
OP2
—
OP2
—
1
1
OP3
OP3
—
OP3
0
0
OP0
OP1
—
—
1
0
OP2
OP3
OP2
OP3
0
0
OP0
OP1
OP2
OP3
Denotes a byte not required during that read cycle.
Arbitration Phase
The external bus design provides for a single bus master at any one time, either the MPC885 or an external
device. The arbitration of external bus devices contending for bus mastership may be handled either by an
external central bus arbiter or by the internal on-chip arbiter. In the latter case, the system is optimized for
one external bus master besides the MPC885. The arbitration configuration (external or internal) is set at
system reset. See Section 15.8, “External Master Support.”
Each bus master must have bus request (BR), bus grant (BG), and bus busy (BB) signals. A device needing
the bus asserts BR and waits for the arbiter to assert BG. The new master must look at BB to ensure that
no other master is driving the bus before it can assert BB to assume bus mastership. (Note that the internal
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External Bus Interface
arbiter may take away the BG if an internal master of higher priority requests the bus and the new master
does not assert BB within one clock after BG.)
If the arbiter removes the bus grant from a device that wants another transfer, the device must rearbitrate
for bus mastership. The MPC885, however, guarantees data coherency for accesses to small ports and for
decomposed bursts. This means that the MPC885 does not release the bus before atomic transactions
complete. For example, a half-word transfer to a byte port is broken into two byte transfers; the MPC885
does not deassert BB until the second transfer completes, unless an error occurs. Figure 13-21 shows basic
bus arbitration protocol. Section 10.4.2, “SIU Module Configuration Register (SIUMCR),” describes how
prioritization can be configured.
Requesting Device
Arbiter
Request the bus
Assert BR
Grant bus
Assert BG
Request the bus
1. Wait for BB to be negated
2. Assert BB to become next master
3. Negate BR
Terminate arbitration
Operate as bus master
Negate BG (or keep it asserted to park
bus master)
Perform data transfer
Release bus mastership
Negate BB
Figure 13-21. Basic Bus Arbitration Protocol
13.4.6.1
Bus Request (BR)
The potential bus master asserts BR to request bus mastership. BR should be negated as soon as the bus is
granted, the bus is not busy, and the new master can drive the bus. If requests are pending, the master can
assert BR as long as needed. When configured for external arbitration, the MPC885 drives BR when it
requires bus mastership. When the internal on-chip arbiter is used, BR is an input to the internal arbiter
and should be driven by the external bus master.
13.4.6.2
Bus Grant (BG)
The arbiter asserts BG to indicate that the bus is granted to the requesting device. BG can be negated after
BR is negated or it can remain asserted to park the current master on the bus. The internal arbiter may take
away the BG if the new master does not assert BB within one clock.
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When the internal on-chip arbiter is used, BG is an output from the internal arbiter to the external bus
master. When configured for external central arbitration, BG is an input to the MPC885 from the external
arbiter.
13.4.6.3
Bus Busy (BB)
BB indicates that the current master is using the bus. New masters should not begin a transfer until BB is
deasserted. The bus master should not relinquish or negate BB until it completes its transfer. To avoid
contention on BB, masters should three-state BB when it gets a logical 1 value. This situation implies an
external pull-up resistor is needed to ensure that a master that acquires the bus can recognize the negation
of BB, regardless of how many cycles have passed since the previous master relinquished the bus. See
Figure 13-22.
External Bus
Master
MPC885
TS
BB
Slave 2
Figure 13-22. Bus Busy (BB) and Transfer Start (TS) Connection Example
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External Bus Interface
Figure 13-23 shows an example bus arbitration between two contending masters.
CLKOUT
BR0
BG0
BR1
BG1
BB
ADDR/ATTR
TS
TA
Master 0
‘turns on’
and
drives
signals
Master 0
negates
BB
and
‘turns off’
Master 1
‘turns on’
and
drives
signals
Figure 13-23. Bus Arbitration Timing Diagram
The MPC885 can be configured at system reset to use the internal bus arbiter. In this case, the MPC885 is
parked on the bus. Section 10.4.2, “SIU Module Configuration Register (SIUMCR),” describes
prioritization of external devices relative to the internal MPC885 bus masters. If the external device
requests the bus and the MPC885 does not require it, or the external device has higher priority than the
current internal bus master, the MPC885 grants the bus to the external device. Figure 13-24 shows the
internal finite state machine that implements the arbiter protocol.
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BB = 0
External owner
BB = three-state
BG = 0
BR
BB = 0
=1
BB
BR = 1
=
,B 0
R
=1
External master
requests bus
MPC885
Internal master
with higher priority than the
external device requires
the bus
External master
release bus
Idle
885 owner
BB = three-state
BG = 1
BB = three-state
BG = 1
MPC885
needs the bus
MPC885
no longer
needs the bus
BR = 0
External device which
has higher priority than the
current internal bus master
requests the bus
BB = 1
885 owner
BG = 1
BB = 0
MPC885
still
needs the bus
Figure 13-24. Internal Bus Arbitration State Machine
13.4.6.4
External Bus Parking
During external arbitration, the MPC885 supports bus parking. If the MPC885 detects that an external
arbiter has asserted BG to it and BB is negated, the MPC885 starts a transfer without asserting BR.
13.4.7
Address Transfer Phase-Related Signals
The following sections describe the address transfer phase-related signals.
13.4.7.1
Transfer Start (TS)
The transfer start signal (TS) indicates the beginning of a transaction on the bus addressing a slave device.
A device should assert TS only after the arbitration protocol has granted mastership. TS is asserted only
for the first cycle of the transaction and is negated in the successive clock cycles until the end of the
transaction. To avoid contention, the master should three-state this signal when it relinquishes the bus. This
situation indicates that an external pull-up resistor should be connected to TS to avoid having a slave
recognize this signal as asserted when no master drives it; see Figure 13-22.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
13-29
External Bus Interface
13.4.7.2
Address Bus
The 32-bit address bus, A[0:31], is byte addressable, so each address can address one or more bytes. A[0]
is the msb. The address and its attributes are driven on the bus with TS; they remain valid until the bus
master receives a transfer acknowledge from the slave. To distinguish an individual byte, the slave device
must observe the TSIZ signals.
13.4.7.3
Transfer Attributes
The transfer attributes signal group consists of RD/WR, BURST, TSIZ[0:1], AT[0:3], STS, and BDIP.
These signals (with the exception of the BDIP) are available at the same time as the address bus.
13.4.7.3.1
Read/Write (RD/WR)
RD/WR high indicates a read access and low indicates a write access. Driven at the beginning of a bus
cycle, RD/WR is valid at the rising edge of the clock in which TS is asserted. RD/WR changes levels only
when a write cycle is preceded by a read cycle or vice versa. It may remain low for consecutive write
cycles.
13.4.7.3.2
Burst Indicator (BURST)
BURST is driven by the bus master at the beginning of the bus cycle (along with the address) to indicate
that the transfer is a burst transfer.
13.4.7.3.3
Transfer Size (TSIZ)
TSIZ[0:1] indicates the size of the requested data transfer. The TSIZ signals may be used with BURST and
A[30:31] to determine which data byte lanes are used in the transfer. For nonburst transfers, TSIZ[0:1]
specifies the number of bytes starting from the byte location addressed by A[30:31]. In burst transfers, the
value of TSIZ[0:1] is always 00.
Table 13-4. BURST/TSIZ Encoding
13.4.7.3.4
BURST
TSIZ[0:1]
Transfer Size
1
01
Byte
1
10
Half word
1
11
x
1
00
Word
0
00
Burst (16 bytes)
Address Types (AT)
The address type signals (AT[0:3]), PTR and RSV, are outputs that indicate one of 16 address types to
which the address applies. These types are designated as either a normal/alternate master cycle,
user/supervisor (problem/privilege), and instruction/data types. The address type signals are valid at the
rising edge of the clock in which the special transfer start (STS) signal is asserted.
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Freescale Semiconductor
External Bus Interface
Address type signals reflect the current status of the master originating the access, not necessarily the status
in which the original access to this location has occurred. An example of this situation is when a modified
data cache block is copied back after the privilege level of the processor has been changed since the last
access to the same cache block. A functional usage of the address type signal RSV is for the reservation
protocol described in Section 13.4.9, “Memory Reservation.” Table 13-5 provides the space definition
encoded by the STS, TS, AT[0:3], PTR, and RSV.
Table 13-5. Address Types Definition
STS TS
Core/
CPM
(AT0)
Reservation/ Program
User/
Instruction/
Reservation
Program Trace Trace
Supervisor
Data (AT2)
(RSV)
(PTR)
(AT3)
(AT1)
Address Space
Definitions
1
x
x
x
x
x
1
1
No transfer or not the first
transaction of a transfer
0
x
x
x
x
x
x
x
Start of a transaction
x
0
0
0
0
0
0
1
Core-initiated, normal
instruction, program trace,
supervisor mode
1
1
1
Core-initiated, normal
instruction, supervisor
mode
0
1
0
Core-initiated, reservation
data, supervisor mode
1
1
1
Core-initiated, normal data,
supervisor mode
0
0
1
Core-initiated, normal
instruction, program trace,
user mode
1
1
1
Core-initiated, normal
instruction, user mode
0
1
0
Core-initiated, reservation
data, user mode
1
1
1
Core-initiated, normal data,
user mode
AT3
1
1
DMA-initiated, normal,
AT[1:3] user-programmable
(see IDMA and DMA
function code registers)
1
1
0
1
1
AT1
AT2
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Freescale Semiconductor
13-31
External Bus Interface
Table 13-5. Address Types Definition (continued)
STS TS
x
1
Core/
CPM
(AT0)
0
Reservation/ Program
User/
Instruction/
Reservation
Program Trace Trace
Supervisor
Data (AT2)
(RSV)
(PTR)
(AT3)
(AT1)
0
0
1
1
0
1
1
AT1
AT2
Address Space
Definitions
0
0
1
Core-initiated, show cycle
address instruction,
program trace, supervisor
mode
1
1
1
Core-initiated, show cycle
address instruction,
supervisor mode
0
1
0
Core-initiated, reservation
show cycle data, supervisor
mode
1
1
1
Core-initiated, show cycle
data, supervisor mode
0
0
1
Core-initiated, show cycle
address instruction,
program trace, user mode
1
1
1
Core-initiated, show cycle
address instruction, user
mode
0
1
0
Core-initiated, reservation
show cycle data, user mode
1
1
1
Core-initiated, show cycle
data, user mode
AT3
1
1
DMA-initiated, normal,
AT[1:3] user-programmable
(see IDMA and DMA
function code registers)
Show cycles are accesses to the core’s internal bus devices. These accesses are made visible externally for
emulation and debugging. A show cycle can have one address phase and one data phase (or just an address
phase for the instruction show cycles). The cycle can be a write or a read access. The address of the show
cycle is valid on the bus for one clock and the data of the show cycle is valid on the bus for one clock. The
data phase does not require a transfer acknowledge to terminate the bus-show cycle. In a burst-show cycle,
only the first data beat is shown externally.
When AT3 = 0 for an access from the core, it indicates either program trace (for an instruction cycle) or
reservation (for a data cycle). These indications can also be monitored on two separate signals (PTR and
RSV), if desired.
• PTR is low when the following is true:
— AT0 = 0 (Core access)
— AT2 = 0 (Instruction)
— AT3 = 0 (Program Trace)
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External Bus Interface
•
RSV is low when the following is true:
— AT0 = 0 (Core access)
— AT2 = 1 (Data)
— AT3 = 0 (Reservation)
13.4.7.3.5
Burst Data in Progress (BDIP)
The master asserts BDIP to indicate to the slave that another data beat follows the current data beat.
13.4.8
Termination Signals
The following sections discuss the termination signals supported by the MPC885.
13.4.8.1
Transfer Acknowledge (TA)
TA indicates normal completion of the bus transfer. The slave asserts TA with every data beat returned or
accepted during a burst cycle.
13.4.8.2
Burst Inhibit (BI)
The slave asserts BI to indicate to the master that it cannot burst. If this signal is asserted, the master must
transfer in multiple cycles and increment the address for the slave to complete the burst transfer.
13.4.8.3
Transfer Error Acknowledge (TEA)
Terminates the bus cycle under a bus error condition for which the current cycle is aborted. TEA overrides
other cycle termination signals, such as TA.
Note that for burst transactions, TEA should be asserted externally only on the first or last beats. Assertion
of TEA on an intermediate beat may result in erratic operation, including lockup of the MPC885 requiring
hard reset.
13.4.8.4
Termination Signals Protocol
The transfer protocol was defined to avoid electrical contention on lines that can be driven by various
sources. To do that, a slave should not drive signals associated with the data transfer until the address phase
is completed and it recognizes the address as its own. The slave should disconnect from signals
immediately after it has acknowledged the cycle and no later than the termination of the next address phase
cycle. This indicates that termination signals should be connected to power through a pull-up resistor to
prevent a master from sampling undefined values in any of these signals when no real slave is addressed.
See Figure 13-25 and Figure 13-26.
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Freescale Semiconductor
13-33
External Bus Interface
External Bus
Slave 1
MPC885
Termination Signals
(TA, TEA, BI)
Slave 2
Figure 13-25. Termination Signals Protocol Basic Connection
CLKOUT
A[0:31]
Slave 1
Slave 2
R/W
TSIZ[0:1]
TS
Data
TA, BI, TEA
Slave 1
allowed to
drive
acknowledge
signals
Slave 1
negates
acknowledge
signals
and
‘turns off’
Slave 2
allowed to
drive
acknowledge
signals
Slave 2
negates
acknowledge
signals
and
‘turns off’
Figure 13-26. Termination Signals Protocol Timing Diagram
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Freescale Semiconductor
External Bus Interface
13.4.9
Memory Reservation
The MPC885 memory reservation protocol supports multilevel bus structures. For each local bus,
reservations are handled by the local reservation logic. The protocol tries to optimize reservation
cancellation such that an MPC8xx core processor is notified of memory reservation loss on a remote bus
only when it has issued a STWCX cycle to that address. That is, the reservation loss indication comes as
part of the STWCX cycle, which avoids the need for fast memory reservation loss indication signals
between each remote bus and each MPC8xx master. The memory reservation protocol assumes the
following:
• Each processor has no more than one reservation flag.
• lwarx sets the reservation flag.
• lwarx by the same processor clears the reservation flag related to a previous lwarx instruction and
again sets the reservation flag.
• stwcx. by the same processor clears the reservation flag.
• Store by the same processor does not clear the reservation flag.
• Some other processor (or other mechanism) store to the same address as an existing reservation
clears the reservation flag.
• If memory reservation is lost, it is guaranteed that stwcx. will not modify the memory.
13.4.9.1
Cancel Reservation (CR)
CR is a point-to-point signal. To use it, reservation logic must remember specifically which bus master
requested reservation for which address. If another master writes to the reserved address, the reservation
logic asserts CR only to the master that holds the associated reservation, thus clearing its flag.
The advantage of CR is that it preempts the stwcx. instruction if reservation is lost, thus eliminating
unnecessary traffic on the external bus.
Figure 13-27 shows the reservation protocol for a single-level (local) bus. It assumes that an external logic
on the bus handles the following:
• Snoops accesses to all local bus slaves.
• Holds one reservation for each local master capable of memory reservations.
• Sets the reservation when that master issues a load and reserve request.
• Clears the reservation when another master issues a store to the reservation address.
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Freescale Semiconductor
13-35
External Bus Interface
MPC885
External Bus
External Bus
Interface
Other
Bus
Master
AT[0:3], RSV, R/W, TS
Iwarx
S
Q
R
A[0:31]
Enable
External
stwcx.
Access
CR
Reservation
Logic
CR
CLKOUT
Figure 13-27. Reservation On Local Bus
The MPC885 samples CR at the rising edge of CLKOUT. When CR is asserted, the reservation flag is
reset. The external bus interface samples the logical value of the reservation flag before externally starting
a bus cycle initiated by a stwcx. instruction in the core. If the reservation flag is set, the external bus
interface begins the bus cycle and if it is reset, no bus cycle is initiated externally and this situation is
reported to the core.
13.4.9.2
Kill Reservation (KR)
KR is a bused signal. In order to use it, the reservation logic must only remember that one of the bus
masters has a reservation for a particular address. If another bus master writes to the address with an
instruction other than stwcx., the reservation logic remembers that the reservation for that address was lost.
When the master with the reservation subsequently attempts an stwcx. instruction to that address, the
reservation logic responds to that external bus cycle with KR.
Note that for burst transactions, KR should be asserted externally only on the first or last beats. Assertion
of KR on an intermediate beat may result in erratic operation, including lockup of the MPC885 requiring
hard reset.
Figure 13-28 shows the reservation protocol for a multi-level (local) bus. The system describes a situation
in which the reserved location is in the remote bus.
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Freescale Semiconductor
External Bus Interface
External Bus (Local Bus)
MPC885
A[:31]
External Bus
Interface
AT[0:3], RSV,
R/W, TS
Q
KR
S
R
Buses’
Interface
Master in the Remote
Bus Write to the
Reserved Location
Remote Bus
Figure 13-28. Reservation on Multilevel Bus Hierarchy
In this case, the buses’ interface block implements a reservation flag for the local bus master. The
reservation flag is set by the buses’ interface when a load with the local bus master issues a reservation
whose address is on the remote bus. The flag is reset when an alternative master on the remote bus accesses
the same location in a write cycle. If the MPC885 begins a memory cycle to the previously reserved
address (located in the remote bus) as a result of a stwcx., the following two cases can occur:
• If the reservation flag is set, the local bus interface acknowledges the cycle in a normal way.
• If the reservation flag is reset, the local bus interface should assert KR. However, the local bus
interface should either not perform the remote bus write access or abort it if the remote bus supports
aborted cycles. The failure of stwcx. is reported to the core.
13.4.10 Bus Exception Control Cycles
The MPC885 bus architecture requires assertion of the TA from an external device to signal that the bus
cycle is complete. TA is not asserted in the following cases:
• the external device does not respond
• various other application-dependent errors occur
External circuitry or the internal MPC885 bus monitor can provide TEA when no device responds by
asserting TA within an appropriate period of time after the MPC885 initiates the bus cycle. This allows the
cycle to terminate and the processor to enter exception processing for the error condition (each one of the
internal masters causes an internal interrupt under this situation).
To properly control termination of a bus cycle for a bus error, TEA must be asserted at the same time or
before TA is asserted. When TEA is sampled as asserted, it should be negated before the next rising edge
to avoid influencing the next initiated bus cycle. TEA is an open-drain pin that allows the wire-OR of
different sources of error generation.
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Freescale Semiconductor
13-37
External Bus Interface
13.4.10.1 RETRY
When an external device asserts RETRY during a bus cycle, the MPC885 enters a sequence in which it
terminates the current transaction, relinquishes bus ownership, and retries the cycle using the same
address, address attributes, and data (in the case of a write cycle). Figure 13-29 shows that when the
internal arbiter is enabled, the MPC885 negates BB and asserts BG in the clock cycle after RETRY is
detected to allow any external master to gain bus ownership. Normal arbitration resumes in the next clock
cycle. If the external master does not use the bus, the MPC885 initiates a new transfer with the same
address and attributes as before.
CLKOUT
BR
BG (Output)
BB
A[0:31]
Allow external master
to gain the bus
A
A
R/W
TSIZ[0:1]
BURST
TS
Data
TA
RETRY
Figure 13-29. Retry Transfer Timing–Internal Arbiter
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Freescale Semiconductor
External Bus Interface
In Figure 13-30 the same situation is shown where the MPC885 is working with an external arbiter. In this
case, in the clock cycle after RETRY is detected asserted, BR and BB are negated together. Normal
arbitration resumes one clock cycle later.
CLKOUT
BR (Output)
BG
BB
A[0:31]
Allow external master
to gain the bus
A
A
R/W
TSIZ[0:1]
BURST
TS
Data
TA
RETRY
Figure 13-30. Retry Transfer Timing–External Arbiter
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
13-39
External Bus Interface
When the MPC885 initiates a burst access, the bus interface only recognizes the RETRY assertion as a
retry termination if it detects it before the slave device acknowledges the first data beat. Note that for burst
transactions, RETRY should be asserted externally only on the first or last beats. Assertion of RETRY on
an intermediate beat may result in erratic operation, including lockup of the MPC885 requiring hard reset.
CLKOUT
BR
BG (Output)
BB
A[0:31]
A
Allow external master
to gain the bus
A
R/W
TSIZ[0:1]
BURST
TS
Data
TA
BI
RETRY
If asserted will cause transfer error
Figure 13-31. Retry on Burst Cycle
If a burst access is acknowledged on its first beat with a normal TA, but with BI asserted, the following
single-beat transfers initiated by the MPC885 to complete the 16 byte transfers process the RETRY signal
assertion as a TEA. If the MPC885 initiates non-burst access to a small port size device, the transfer size
of the access is bigger than the slave port size, and the first transfer of this access is terminated normally
by the assertion of TA, then subsequent single-beat transfers, which are initiated by the MPC885 to
complete the access, process the RETRY assertion as a TEA.
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External Bus Interface
Table 13-6 summarizes how the MPC885 recognizes the termination signals provided by the slave device
that is addressed by the initiated transfer.
Table 13-6. Termination Signals Protocol
TEA
TA
RETRY/KR
Action
0
x
x
Transfer error termination
1
0
x
Normal transfer termination
1
1
0
Retry transfer termination/kill reservation
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
13-41
External Bus Interface
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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Freescale Semiconductor
Chapter 14
Clocks and Power Control
The MPC885 clock system provides any different clocking options for all on-chip and external devices.
For its clock sources, the MPC885 contains phase-locked loop and crystal oscillator support circuitry. The
phase-locked loop circuitry can be used to provide a high-frequency system clock from a low-frequency
external source. Also, to enable flexible power control, the MPC885 provides frequency dividers options.
Figure 14-1 illustrates internal clock source and distribution that includes the digital phase-locked loop
(DPLL) and interface, clock dividers, drivers, and crystal oscillator.
14.1
Features
The main features of the MPC885 clocks are as follows:
• Contains digital system PLL (DPLL)
• Supports crystal oscillator circuits
• Clock dividers are provided for internal clocks
• Contains the following power modes
— Normal High
— Normal Low
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
14-1
Clocks and Power Control
VDDSYN
PLPRCR[PDF, MFI, MFN, MFD]
PLPRCR[S]
DPLL
1
––––––
(PDF +1)
dpdref
2x
MFI +
dpgdck Interface
Logic
MFN
______
MFD+1
jdbck
(divide
by 1, 2, 4)
MODCK[1:2]
divout1
÷2
gclk2
gclk/
gclk2
EXTCLK
2:1
MUX
gclk1c/
gclk2c
osclk
2:1 MUX
(÷4 OR ÷16)
SCCR
[TBS]
gclk1_50/
gclk2_50
Low-Power
Dividers
Clock
Drivers
utpclk
brgclk
syncclk
tbclk
CLKOUT
Driver
SCCR[PTDIV]
SCCR[PTSEL]
÷4
XTAL
EXTAL
Main
Clock
Oscillator
OSCM
2:1
MUX
2:1
MUX
÷512
CLKOUT
Time Base and
Decrementer
Driver
tmbclk
PIT
Clock
and Driver
pitclk
Note that only CLKOUT is an actual external output; all other outputs are internal signals.
Figure 14-1. Clock Source and Distribution
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14-2
Freescale Semiconductor
Clocks and Power Control
14.2
Clock Module
The clock module consists of two external reference sources and a programmable phase-locked loop,
arranged as shown in Figure 14-2.
Crystal = 10 MHz
0.1uF
0.1uF
GND
EXTAL
XTAL
OSCM
EXTCLK
VDD
VSSSYN
DPLL and Interface Logic
2:1
MUX
VDDSYN
VSSSYN1
CKPLPDM
CLKOUT
Low-Power Divider
OSC
Figure 14-2. Clock Module Components
14.2.1
External Reference Clocks
The MPC885 has two input clock sources, provided at the EXTCLK pin or at the EXTAL and XTAL pins.
These two clock sources can select to drive three internal clock signals, referred to as OSCLK, PITCLK,
and TMBCLK. OSCLK provides the input clock to the phase-locked loop. PITCLK and TMBCLK
provide dedicated clocks for special system timer circuitry, which includes the periodic interrupt timer
(PIT), timebase (TB), and decrementer (DEC) in the SIU. These separate clock sources for the PIT, TB,
and DEC are provided to enable these modules to continue to count at a fixed, user-defined rate regardless
of system frequency.
The clock sources for OSCLK, PITCLK, and TMBCLK are selected at reset. The sources for PITCLK and
TMBCLK can also be selected in software by manipulation of SCCR; see Section 14.6.1, “System Clock
and Reset Control Register (SCCR).” For more information, see Section 14.2.3, “DPLL Reset
Configuration,” Section 14.3.2, “PIT Clock (PITCLK),” and Section 14.3.3, “Time Base and Decrementer
Clock (TMBCLK).”
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
14-3
Clocks and Power Control
NOTE
It is possible to use both clock sources in a system, with each providing
reference for different functions. If either reference source is not used, its
input should be grounded. It is not recommended to select the crystal
oscillator circuit as OSCLK while also driving a high-frequency clock
source on EXTCLK. This is because noise from the EXTCLK clock source
will couple into the crystal oscillator circuit and will in many cases not allow
the digital phase-locked loop (DPLL) to lock. The converse, however, is
allowable; EXTCLK can be selected as OSCLK while the crystal oscillator
circuit supplies a separate frequency reference.
A typical configuration uses a canned oscillator with the EXTCLK input selected as OSCLK, and uses a
10MHz crystal at EXTAL and XTAL to provide PITCLK.
There are 4 different PLL Modes defined by the MODCK pins at reset that determine the initial value of
the PLPRCR register. Three of these modes require a 10 MHz input frequency, while the fourth mode can
accept from 45 to 66 MHz. After reset, the PLPRCR can be programmed to achieve a different general
system clock as long as the following requirements are met.
• OSCM is 10 MHz only (MODCK = 00 or 01)
• EXTCLK is 10 MHz (MODCK = 11)
• EXTCLK is 45 MHz to 66 MHz (MODCK = 10)
The Input Frequency Requirements at reset are shown in Table 14-1
Table 14-1. The Input Frequency Requirements
MODCK[1:2]
00, 01
14.2.2
Freq. In
PDF
MFI, MFN, MFD for DPGDCK
OSCM = 10 MHz
0
160 MHz < OSCLK * 2 * (MFI + (MFN /
(MFD+1))) < 320 MHz
11
EXTCLK = 10 MHz
0
160 MHz < OSCLK * 2 * (MFI + (MFN /
(MFD+1))) < 320 MHz
10
45 MHz ≤ EXTCLK ≤ 66 MHz
10 MHz ≤ EXTCLK /
(PDF+1) ≤ 32 MHz
160 MHz < OSCLK * 2 * (MFI + (MFN /
(MFD+1))) / (PDF+1) < 320 MHz
Digital Phase Lock Loop and Interface
The programmable digital phase lock loop (DPLL) in the MPC885 generates the overall system operating
frequency in integer and non-multiples of the input clock frequency. CLKOUT synchronization is not
guaranteed for non-integer multiples of OSCLK. If CLKOUT is an integer multiple of OSCLK/EXTCLK,
the rising edge of EXTCLK is aligned (locked/synchronized) with the rising edge of CLKOUT. For a non
integer multiple of EXTCLK, this synchronization is lost, and the rising edges of EXTCLK and CLKOUT
have a continuously varying phase skew.
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Freescale Semiconductor
Clocks and Power Control
Digital implementation of frequency control and loop filtering functions in the design of the DPLL allows
the following new features:
• Eliminating an on-board loop filter capacitor, minimization of internal capacitor value;
• Selection of frequency and phase/frequency operation modes;
• An improved noise immunity, eliminating additional supply and ground pins;
• A high frequency resolution with a reduced lock time;
• Reduced sensitivity to parameter variations caused by temperature and process.
The main purpose of the DPLL is to generate a stable reference frequency by multiplying the frequency
and eliminating the clock skew. The DPLL allows the processor to operate at a high internal clock
frequency using a low frequency clock input, providing two advantages. First, lower frequency clock input
reduces the overall electromagnetic interference generated by the system. Second, the programmability of
the oscillator enables the system to operate at a variety of frequencies with only a single external clock
source.
The DPLL reference clock (OSCLK) can be generated from either of the external clock sources described
in Section 14.2.1, “External Reference Clocks.”
Inside the DPLL, the OSCLK is divided by the predivision factor (PDF+1) to generate DPDREF clock.
Frequency range of DPDREF is 10 to 32 Mhz. This DPDREF clock is used, further inside the DPLL, for
generating the output clock of the DPLL, i.e DPGDCK (see Figure 14-1). Frequency range of DPGDCK
is 160 to 320 Mhz. These frequency ranges must be maintained by both the reset configuration settings of
the DPLL and Interface and the final operating frequency of the DPLL and the Interface.
The interface logic works in three modes depending on divider selection input PLPRCR[S]. The formula
for the output frequency of the DPLL and interface logic for each mode is given as per formula.
jdbck = 2 *
MFI + (MFN/(MFD+1))
PDF + 1
* OSCLK / 2s
for S = 0, 1, or 2
NOTE
For synchronization between EXTCLK to CLKOUT, the total value that the
EXTCLK gets multiplied by must be an integer.
This also requires the total MF factor i.e [MFI + (MFN/(MFD+1))] to be an
integer as a prerequisite.
Table 14-2 shows the DPLL parameters for some typical system frequencies during Normal Operation.
The frequency after Power On Reset is shown in Table 14-3. The multiplication factors (MF) shown are
for the integer part (MFI), the numerator part (MFN), the denominator part minus 1(MFD), and the
predivison factor minus 1 (PDF) with their ranges listed in Table 14-9. The total MF value,
MFI+(MFN/(MFD+1)), must be between 5 to 15.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
14-5
Clocks and Power Control
Table 14-2. Typical System Frequency Generation
1
2
Input
Frequency
(MHz) (fref)
PDF
MFI
MFN
10
0
8
10
0
10
General System
Frequency
(MHz) [GCLK2] 2
MFD
dpgdck
PLPRCR
S[10:11]
0
0
160
1
80
40
9
6
9
192
1
96
48
0
10
4
9
208
1
104
52
10
0
13
2
9
264
1
132
66
10
0
15
0
0
300
1
150
75
10
0
10
0
0
200
0
200
100
10
0
13
3
9
266
0
266
133
45
3
8
0
0
180
1
90
45
45
2
8
1
2
250
0
250
125
50
2
9
0
0
300
1
150
75
50
1
5
2
6
264
0
264
132
66
2
6
0
1
264
1
132
66
66
2
6
0
1
264
0
264
132
1
JDBCK
For MFN = 0, EXTCLK will be synchronized to CLKOUT.
Assuming DFNH = 0 and CSR = 0.
The OSCLK can be supplied by either a crystal or an external clock oscillator. Crystals are typically much
cheaper than clock oscillators; however, a clock oscillator has significant design advantages over a crystal
circuit in that clock oscillators are easier to work with, resulting in faster design, debugging, and
production.
14.2.3
DPLL Reset Configuration
While PORESET is asserted, the reset configuration of the DPLL is sampled on the MODCK[1:2] pins.
The DPLL immediately begins to use the multiplication factor and pre-division factor values and external
clock source for OSCLK determined by the sampled MODCK[1:2] pin and attempts to achieve lock;
therefore, the MODCK[1:2] signals should be maintained steadily throughout PORESET assertion. The
mode selection field and various factors are set as shown in Table 14-3. After PORESET is negated, the
MODCK[1:2] values are internally latched, and the signals applied to MODCK[1:2] can be changed.
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Clocks and Power Control
Table 14-3. Power-On Reset DPLL Configuration
Default at Power-On Reset
MODCK[1:2]
OSCLK (DPLL and Interface input) General System Frequency (GCLK2)
MFI[12:15]
PDF[27:30]
00
8
0000
OSCM Freq
40 MHz (for OSCLK freq = 10 MHZ)
01
15
0000
OSCM Freq
75MHz (for OSCLK freq = 10 MHZ)
10
6
0010
EXTCLK Freq
1:1 Mode (The allowable frequencies on
EXTCLK are 45 MHz to 66 MHz)
11
15
0000
EXTCLK Freq
75 MHz (for EXTCLK freq = 10 MHZ)
Note: Note: S = 1, MFN = 0, MFD = 1 for all of the reset configurations.
Note: The general system clock[GCLK2] is jdbck divided by 2.
Note: divout1 is jdbck divided by 2.
NOTE
Under no condition should the voltage on MODCK1 and MODCK2 exceed
the power supply voltage VDDH applied to the part.
At power-on reset, before the PLL achieves lock, no internal or external clocks are generated by the
MPC885, which may cause higher than normal static current during the short period of stabilization.
14.2.4
Crystal Oscillator Support (EXTAL and XTAL)
The MPC885 provides support for crystal oscillator circuits with the oscillator module (OSCM). The
OSCM supports a frequency of 10MHz.
The clock source of OSCM can be provided by a crystal circuit or an external oscillator. If an external
oscillator is used, it should be connected to EXTAL, and XTAL should be left unconnected. If a crystal
circuit is used, it should be connected between EXTAL and XTAL. The crystal circuit is composed of an
on-chip inverting amplifier, an external parallel resonant crystal, two capacitors, and two resistors, as
shown in Figure 14-3. EXTAL is the amplifier input for the crystal circuit; XTAL is the amplifier output.
Example values for the passive components of the crystal circuits are provided in Figure 14-3. However,
because this is a sensitive analog circuit, these values cannot be guaranteed. These components may have
to be tuned due to design-specific parasitic capacitance variation due, for example, to layout and board
composition. Careful consideration must be given to component placement and layout, keeping
components as near as possible to the chip and keeping all trace lengths to a minimum. It should be noted
that the sensitivity of crystal circuits to external component values is so great that even probing the circuit
changes its behavior to the point that it may fail to resonate. In practice, experimentation is required to find
an acceptable range of component values, with the final design value being selected in the middle of this
range.
Lastly, it should also be noted that future changes in the device technology (shrinks) may change the
characteristics of the input and output impedance of the on-chip amplifier. Freescale reserves the right to
perform these changes, and designers should be prepared to modify their crystal circuits appropriately
should these changes cause their crystal circuit designs to fail. This risk should be taken into account when
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
14-7
Clocks and Power Control
the design is performed; if potential manufacturing downtime due to redesign of crystal circuits is
unacceptable, a canned oscillator circuit should be used instead.
Crystal = 10 MHz
C1
R2
C2
R1
EXTAL
XTAL
A5
A4
OSCM
R1=10MΩ, R2=1KΩ, C1=47pf, C2=56pf
Figure 14-3. Crystal Circuit Examples
14.3
Clock Signals
The MPC885 uses the following clocks, summarized in Table 14-4. These clocks are described in the
following three sections, grouped by their different sources.
.
Table 14-4. Functionality Summary of the Clocks
Clock
GCLK1C/GCLK2C
GCLK1/GCLK2
GCLK1_50/GCLK2_50
Description
Basic clocks supplied to the core, the data and instruction caches, and MMUs
Basic clocks supplied to the SIU, clock module, CP, and most other features in the CPM
Optionally divided versions of GCLK1/GCLK2 that clock the GPCM and UPM in the
memory controller and provide the CLKOUT output for the external bus
UTPCLK
Clocks the Utopia Module
BRGCLK
Clocks the four baud rate generators and the memory controller refresh timer. This allows
the serial ports to operate at a fixed frequency and the memory refresh to continue at a
uniform rate even when the rest of the MPC885 is operating at a reduced frequency.
SYNCCLK
Used by the serial synchronization circuitry in the serial ports of the CPM, and includes the
SI, SCC, and SMCs. SYNCCLK performs the function of synchronizing externally
generated clocks before they are used internally. SYNCCLK allows the SI, SCC, and SMCs
to continue operating at a fixed frequency.
CLKOUT
Clock out is an external clock signal used to drive other devices, and thus provide the ability
to operate synchronously with those devices. Equivalent to the internal GCLK2_50 signal.
TMBCLK
Clocks the time base and decrementer
PITCLK
Clocks the periodic interrupt timer
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Clocks and Power Control
14.3.1
Clocks Derived from the DPLL Output
The MPC885 uses the following 10 internal clock signals, which are derived from the DPLL and interface
logic output clock, JDBCK:
• General system clocks—GCLK1C, GCLK2C, GCLK1, GCLK2
• Memory controller and external bus clocks—GCLK1_50, GCLK2_50
• Utopia clock — UTPCLK
• Baud rate generator clock—BRGCLK
• Synchronization clocks—SYNCCLK, SYNCCLKS
The MPC885 also provides the GCLK2_50 signal externally on the CLKOUT pin.
The DPLL and Interface output JDBCK is sent to frequency dividers that generate the GCLKx, GCLKxC,
GCLKx_50, SYNCCLK, and BRGCLK which are sent to the rest of the modules of the MPC885. The
signal, divout1, is an intermediate signal and is equivalent to JDBCK divide by 2. The division factor for
each divider is programmed in the SCCR. The organization of the dividers is shown in Figure 14-4.
divout1
DFUTP
UTPCLK
UTOPIA Module
DFAUTP
SYNCCLK
DFSYNC
CPM
BRGCLK
DFBRG
GCLK1C
GCLK2C
CPM and
UPM
(Refresh
Timers)
Phase
GCLK2
DFNH
GCLK1
2:1
MUX
DFNL
GCLK1_50
EBDF
Phase
GCLK2_50
Timer module,
Core, CPM and
SIU.
UPM and SIU
CLKOUT
Figure 14-4. Clock Dividers
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Freescale Semiconductor
14-9
Clocks and Power Control
14.3.1.1
Internal General System Clocks
(GCLK1C, GCLK2C, GCLK1, GCLK2)
The GCLKxC and GCLKx signals are referred to here as GCLKx. The difference between the GCLKxC
and GCLKx signals are as follows:
• The GCLKxC clocks are supplied to the core, data and instruction caches, and memory
management unit.
• The GCLKx clocks are supplied to the SIU, clock module, memory controller, and most of the
other blocks in the CPM.
GCLKx can be dynamically switched between two different frequencies determined by dividers
programmed in SCCR[DFNH] and SCCR[DFNL], as shown in Figure 14-5.
divout1
DFNH Divider
DFNH
2:1
MUX
DFNL Divider
GCLK1
DFNL
Figure 14-5. Frequency Dividers for GCLK x
The high frequency is generated by using the DFNH field in the SCCR, and it is used in normal high mode.
The low frequency is generated using the DFNL field in the SCCR, and it is used in normal low mode. The
DFNH and DFNL dividers are cleared by HRESET, and therefore GCLKx defaults to divout1, where
divout1 is equivalent to JDBCK divide by 2.
The frequency for the GCLKx system clock is:
divout1 freq
GCLKx freq = ------------------------------------------------------------------DFNH
DFNL + 1
(2
)or ( 2
)
When GCLKx is divided, its duty cycle is modified. One phase remains the same while the other stretches
out. GCLKx no longer has a 50% duty cycle when the division factor is greater than 1, as shown in
Figure 14-6.
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Freescale Semiconductor
Clocks and Power Control
GCLK1 Divided by 1
GCLK2 Divided by 1
GCLK1 Divided by 2
GCLK2 Divided by 2
GCLK1 Divided by 4
GCLK2 Divided by 4
Figure 14-6. Divided System Clocks (GCLK x) Timing Diagram
14.3.1.2
Memory Controller and External Bus Clocks
(GCLK1_50, GCLK2_50, CLKOUT)
The MPC885 provides the capability to run the external bus and memory controller at a lower frequency
than the internal modules. This capability is provided by the external bus frequency dividers. The external
bus clocks GCLK1_50 and GCLK2_50 are derived from GCLK1 and GCLK2, as determined by the
SCCR[EBDF]. SCCR[EBDF] is cleared by HRESET, and thus GCLK1_50 and GCLK2_50 default to
GCLK1 and GCLK2. The timing relationship between GCLKx and GCLKx_50 is shown in Figure 14-7.
GCLK1
GCLK2
GCLK1_50
(EBDF=00)
GCLK2_50
(EBDF=00)
CLKOUT
(EBDF=00)
GCLK1_50
(EBDF=01)
GCLK2_50
(EBDF=01)
CLKOUT
(EBDF=01)
Figure 14-7. Memory Controller and External Bus Clocks Timing
Diagram for EBDF=0 and EBDF=1
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Freescale Semiconductor
14-11
Clocks and Power Control
If SCCR[EBDF]=0, the duty cycle of both GCLK1_50 and GCLK2_50 is 50%. However, if
SCCR[EBDF]=1, the duty cycle of GCLK2_50 is 50%, but the duty cycle of GCLK1_50 is 37.5%, as
shown in Figure 14-7.
The low-power frequency dividers described in Section 14.3.1.1, “Internal General System Clocks
(GCLK1C, GCLK2C, GCLK1, GCLK2),” also affect the frequency and duty cycle of GCLK1_50,
GCLK2_50, and CLKOUT. For an example of this, see Figure 14-8.
GCLK1
GCLK2
GCLK1_50
(EBDF=00)
GCLK2_50
(EBDF=00)
CLKOUT
(EBDF=00)
GCLK1_50
(EBDF=01)
GCLK2_50
(EBDF=01)
CLKOUT
(EBDF=01)
Figure 14-8. Memory Controller and External Bus Clocks Timing
Diagram for (CSRC=0 and DFNH=1) or (CSRC=1 and DFNL=0)
The frequency of GCLK1_50 and GCLK2_50 are affected both by the SCCR[DFNH] and SCCR[DFNL]
dividers and by the SCCR[EBDF] divider. Thus, the frequency for GCLKx_50 and CLKOUT is:
divout1 freq
1
GCLKx_50f req = ----------------------------------------------------------- × -------------------------DFNH
DFNL + 1
EBDF
+1
(2
)or ( 2
)
CLKOUT is the only externally visible clock, and is equivalent to the internal signal GCLK2_50. While
the DPLL is acquiring lock, the CLKOUT signal does not oscillate and remains in a low state.
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Clocks and Power Control
14.3.1.3
CLKOUT Special Considerations: 1:2:1 Mode
To enable synchronization of a system to the EXTCLK signal while still allowing the internal circuits of
the MPC885 to operate at an increased frequency, it is necessary to maintain synchronization of the
EXTCLK and CLKOUT signal. Specifically, this operation entails:
• input clock source EXTCLK
• internal clock of 2xEXTCLK, provided by multiplying EXTCLK by 2 in the DPLL (by
programming PLPRCR[MFI]=10, PLPRCR[MFN]=0, PLPRCR [MFD]=0, PLPRCR[PDF]=4,
PLPRCR[S]=0)
• external bus clock CLKOUT with frequency equivalent to EXTCLK, provided by dividing
GCLK2 by 2 (by programming SCCR[EBDF]=01)
This is also known as 1:2:1 mode. In this mode, in order to allow multiple devices clocked by the same
EXTCLK source to maintain synchronization on the external bus, EXTCLK and CLKOUT must be in
phase. This operation can be guaranteed, but it requires that SCCR[EBDF] be written first, followed by
the write to PLPRCR[MFI, MFN, MFD]. Synchronization between EXTCLK and CLKOUT is only
possible when the total multiplication factor between EXTCLK and CLKOUT is maintained as an integer
number.
14.3.1.4
Baud Rate Generator Clock (BRGCLK)
The baud rate generator clock (BRGCLK) is used by the four baud rate generators of the communication
processor module and by the memory controller refresh counter. The baud rate generator clock is
controlled independently in order to allow the baud rate generators and memory refresh rate to continue
operating at a fixed frequency, even when the rest of the MPC885 is operating at a reduced frequency.
BRGCLK defaults to divout1, where divout1 is equivalent to JDBCK divide by 2, but can be reduced in
frequency by a frequency divider. This frequency divider is controlled by SCCR[DFBRG].
divout1
DFBRG
BRGCLK
CPM and
UPM
(Refresh
Timer)
Figure 14-9. BRGCLK Divider
The baud rate generator clock frequency is:
divout1freq
BRGCLK freq = ---------------------------------------2 × DFBRG
(2
)
14.3.1.5
Synchronization Clock (SYNCCLK, SYNCCLKS)
The synchronization clock signals (SYNCCLK and SYNCCLKS, collectively as SYNCCLK) are used by
the signal synchronization circuitry in the serial ports of the communication processor module. The signal
synchronization circuitry is used to sample and synchronize asynchronous external signals provided to
these ports. SYNCCLK allows the serial interface, serial communication controller, and serial
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14-13
Clocks and Power Control
management controllers to continue operating at a fixed frequency, even when the rest of the MPC885 is
operating at a reduced frequency.
SYNCCLK defaults to divout1, where divout1 is equivalent to JDBCK divide by 2, but can be reduced in
frequency by a frequency divider. This frequency divider is controlled by SCCR[DFSYNC].
divout1
DFSYNC
SYNCCLK
CPM
Figure 14-10. SYNCCLK Divider
The synchronization clock frequency is:
SYNCCLK
divout1freq
= -------------------------------------------freq
2 × DFSYNC
(2
)
Limitations on SYNCCLK include:
• SYNCCLK must always have a frequency at least as high as GCLKx.
• SYNCCLK must and be at least two times the maximum serial clock rate used by the serial ports
in the system.
• If the time-slot assigner (TSA) is used, SYNCCLK must be at least 2.5 times the maximum serial
clock rate of the TSA.
14.3.2
PIT Clock (PITCLK)
The PIT clock is generated either from EXTCLK or the crystal oscillator circuit (OSCM). This input
source can be divided by either 4 or 512. The PITCLK source and divide factor are selected by
SCCR[PTSEL] and SCCR[PTDIV].
The MODCK[1:2] state at PORESET negation determines the input clock source and prescalar value for
PITCLK. These values can be changed after reset by manipulating the associated bits in the SCCR.
Table 14-5. PITCLK Configuration at PORESET
MODCK [1:2]
PITCLK Prescaler
SCCR[PTDIV]
PITCLK Input Source
SCCR[PTSEL]
00
4
OSCM (crystal oscillator)
01
512
OSCM (crystal oscillator)
10
512
EXTCLK
11
512
EXTCLK
Note: Since OSCM just uses one frequency input of 10 MHz, it is not possible to get a PITCLK period of 1 second.
This could however be achieved by giving an appropriate input to the EXTCLK.
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Clocks and Power Control
14.3.3
Time Base and Decrementer Clock (TMBCLK)
The time base and decrementer clock is generated either from the input frequency of the DPLL and
Interface (OSCLK) or the general system clock GCLK2. The SCCR[TBS] bit is used to select between
these two sources.
The MODCK[1:2] state at PORESET negation, the SCCR[TBS], and the DPLL multiplication factor
determine the input clock source and prescalar value for TMBCLK.
Table 14-6. TMBCLK Configuration
SCCR[TBS]
MODCK[1:2] at
PORESET
MF
Clock Source
TMBCLK Prescaler
1
XX
X
GCLK2
16
0
0X
X
OSCLK
4
0
1X
1, 2
OSCLK
16
0
1X
>2
OSCLK
4
Note: TMBCLK prescalar is unpredictable (4 or 16) whenever MF lies between 2 to 2.33
14.4
Power Distribution
The various modules of the MPC885 are connected to four distinct power rails. These power rails have
different requirements, as explained in the following sections. The organization of the power rails is shown
in Figure 14-11.
MPC885
I/O Pad
Internal Logic
and
Clock Drivers
OSCM, PIT,
TB,
DEC, SCCR,
PLPRCR,
and RSR
Analog
DPLL
TEXP
Clock Control
and Digital DPLL
VDDH
3.3 V
VDDL
1.8 V
VDDSYN
1.8 V
Figure 14-11. MPC885 Power Rails
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Freescale Semiconductor
14-15
Clocks and Power Control
A complete tabulation of modules and power supplies is given in Table 14-7.
Table 14-7. MPC885 Modules vs. Power Rails
Block
VDDH
VDDL
I/O Pad
X
X
CLKOUT
X
Digital SPLL
X
Clock Control
X
Internal Logic
X
Clock Drivers
X
Analog DPLL
VDDSYN
X
OSCM
X
SCCR, PLPRCR, and RSR
X
PIT, TB, and DEC
X
To assure that the part works correctly, use the following power up and power down instruction sequences.
• Power-up sequence: The designer should power up the I/O voltage supply (VDDH) first and the
core voltage source (VDDL) next. The VDDH and VDDL voltage supplies maybe raised at the
same time, but in no case, should the core voltage supply (VDDL) be raised before I/O voltage
supply (VDDH).
• Power-down sequence: The designer should power down the core voltage supply (VDDL) first and
the I/O voltage supply (VDDH) next. They may be powered down together, but in no case, is the
I/O voltage supply (VDDH) to be powered down before core voltage supply (VDDL).
14.4.1
I/O Buffer Power (VDDH)
The I/O buffers are fed by a 3.3-V power supply.
14.4.2
Internal Logic Power (VDDL)
The internal logic are to be fed by the 1.8-V source.
14.4.3
Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1)
To improve stability, the power supply pins for the DPLL are uniquely identified in order to allow special
filtration to be provided for them.
A well-regulated voltage should be applied to VDDSYN via a low-impedance path to the VDDL power
rail. The allowable noise on the VDDSYN power plane is 20 mV peak up to a bandwidth of 100 MHz.
This typically requires isolation of the VDDSYN power plane from the VDDL power plane. An example
implementation of this is a split power plane, with the VDDSYN plane implemented as an island in the
VDDL power plane, connected to the VDDL power plane with an inductor and to the ground plane with
MPC885 PowerQUICC Family Reference Manual, Rev. 2
14-16
Freescale Semiconductor
Clocks and Power Control
bypass capacitors. An inductor value of 8.2 Mhz and bypass capacitor values of 0.1 µF and 10 µF provide
a two-pole filter with a cutoff frequency of 500 Hz.
VSSSYN and VSSSYN1 must have a low-impedance path to the ground plane. If sufficient isolation is
provided for VDDSYN (as described above), no additional isolation for VSSSYN and VSSSYN1 is
required.
14.5
Power Control
To optimize power consumption, the MPC885 provides a low-power mode that can be used to dynamically
activate and deactivate certain internal modules, such that only the needed modules are operating at any
given time. In addition to normal high mode (i.e. fully activated), the MPC885 supports a normal low
mode.
In addition to the normal low power-saving mode, it should be noted that the architecture of the CPM
inherently supports optimum power consumption. When the CPM is idle, it uses its own power-saving
mechanism to shut down automatically.
The normal low power mode is controlled in the PLPRCR[CSRC]. Events can cause automatic changes
from normal low to normal high mode. These events include software-initiation, CPM activity, internal
interrupt sources, external interrupt sources, and resets.
14.5.1
Normal High Mode
Normal high mode is the default mode of the MPC885. In this mode, the GCLKx frequency is determined
by SCCR[DFNH], and all modules of the MPC885 are enabled. For more information about
SCCR[DFNH], refer to Section 14.3.1.1, “Internal General System Clocks (GCLK1C, GCLK2C, GCLK1,
GCLK2).”
Normal high mode is selected if PLPRCR[CSRC]=0 and PLPRCR[LPM]=00, or if an enabled event has
caused an exit from Normal Low power mode.
14.5.2
Normal Low Mode
Normal low mode takes advantage of the low-power dividers for GCLKx to enable full functionality of
the MPC885, but at a lower frequency so that power consumption is reduced. The low-power dividers
allow the system to reduce and restore the operating frequencies of different sections of the MPC885
without losing the DPLL lock. This mode is sometimes called slow-go or low gear mode.
Normal low mode is selected if PLPRCR[CSRC]=1. In normal low mode, the GCLKx frequency is
determined by SCCR[DFNL]. For more information about SCCR[DFNL], see Section 14.3.1.1, “Internal
General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2).”
Normal low mode can be entered at any time, and the frequency of operation of normal low mode can be
changed dynamically. This is controlled by PLPRCR[CSRC] and SCCR[DFNL]. Changes to these bits
take effect immediately.
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14-17
Clocks and Power Control
The following event cause the MPC885 to leave normal low mode and enter normal high mode:
• The communications processor (CP) has a service request from a peripheral (SCC, SMC, etc.).
This option is maskable with SCCR[CRQEN].
14.6
Clock and Power Control Registers
The following sections describe the clock and power control registers.
14.6.1
System Clock and Reset Control Register (SCCR)
The DPLL has a 32-bit control register, the system clock and reset control register (SCCR), shown in
Figure 14-12, which is memory-mapped into the MPC885 SIU’s register map.
0
1
2
3
5
6
7
8
Field
—
COM
—
HRESET
—
#
0
#
#
#
POR
0
0
0
0
*
*
9
TBS PTDIV PTSEL CRQEN
Field
—
DFSYNC
20
DFBRG
21
23
15
0
0
0
†
0
0
0
0
†
0
24
DFNL
14
—
(IMMR & 0xFFFF0000) + 280
19
13
EBDF
Addr
18
12
—
R/W
17
11
–
R/W
16
10
26
DFNH
HRESET
0
POR
0
R/W
R/W
Addr
(IMMR & 0xFFFF0000) + 282
27
29
DFUTP
30
31
DFAUTP
Note: HRESET is hard reset and POR is power-on reset.
# The field is undefined
— The field is unaffected.
* PTDIV depends on the combination of MODCK1 and MODCK2. PTSEL depends on MODCK1. See Table 14-5 for
more information.
† This field is set according to the default of the hard reset configuration word.
Figure 14-12. System Clock and Reset Control Register (SCCR)
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Clocks and Power Control
This register is affected by HRESET but is not affected by SRESET. Table 14-8 describes SCCR fields.
Table 14-8. SCCR Field Descriptions
Bits
Name
Description
0
—
1–2
COM
3–5
—
6
TBS
7
PTDIV
Periodic interrupt timer clock divide. Determines if the clock, the crystal oscillator, or main clock
oscillator to the periodic interrupt timer is divided by 4 or 512. At power-on reset this bit is cleared
if the MODCK1 and MODCK2 signals are low.
0 The clock is divided by 4.
1 The clock is divided by 512.
8
PTSEL
Periodic interrupt timer select. Selects the crystal oscillator or main clock oscillator as the input
source to PITCLK. At power-on reset, it reflects the value of MODCK1.
0 OSCM (crystal oscillator) is selected.
1 EXTCLK is selected.
9
CRQEN
CPM request enable. Cleared by power-on or hard reset. In low-power modes, specifies if the
general system clock returns to high frequency while the CP is active.
0 The system remains in low frequency even if the communication processor module is active.
1 The system switches to high frequency when the communication processor module is active.
10
–
Reserved, should be cleared
11–12
—
Reserved, should be cleared.
13–14
EBDF
15–16
—
Reserved, should be cleared.
Clock output module. This field controls the output buffer of the CLKOUT pin. When both bits are
set, the CLKOUT pin is held in the high state. These bits can be dynamically changed without
generating spikes on the CLKOUT pin. If the CLKOUT pin is not connected to external circuits,
clock output should be disabled to minimize noise and power dissipation. The COM field is cleared
by hard reset.
00 Clock output enabled full-strength buffer.
01 Reserved.
10 Reserved.
11 Clock output disabled.
Reserved, should be cleared.
Timebase source. Determines the clock source that drives the timebase and decrementer.
0 Timebase frequency source is the OSCLK divided by 4 or 16.
1 Timebase frequency source is GCLK2 divided by 16.
External bus division factor. This field defines the frequency division factor between GCLKx and
GCLKx_50. CLKOUT is similar to GCLK2_50. The GCLKx_50 is used by the bus interface and
memory controller to interface with an external system. This field is initialized during hard reset
using the hard reset configuration word in Section 11.3.1.1, “Hard Reset Configuration Word.”
00 CLKOUT is GCLK2 divided by 1.
01 CLKOUT is GCLK2 divided by 2.
10 Reserved.
11 Reserved.
Reserved, should be cleared.
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Freescale Semiconductor
14-19
Clocks and Power Control
Table 14-8. SCCR Field Descriptions (continued)
Bits
17–18
Name
Description
DFSYNC Division factor for the SYNCCLK. This field sets the divout1, where divout1 is equivalent to JDBCK
divide by 2, frequency division factor for the SYNCCLK signal. Changing the value of this field
does not result in a loss-of-lock condition. This field is cleared by a power-on or hard reset.
00 Divide by 1 (normal operation).
01 Divide by 4.
10 Divide by 16.
11 Divide by 64.
19–20
DFBRG
Division factor of the BRGCLK. This field sets the divout1, where divout1 is equivalent to JDBCK
divide by 2, frequency division factor for the BRGCLK signal. Changing the value of this field does
not result in a loss-of-lock condition. This field is cleared by a power-on or hard reset.
00 Divide by 1 (normal operation).
01 Divide by 4.
10 Divide by 16.
11 Divide by 64.
21–23
DFNL
Division factor low frequency. Sets the divout1, where divout1 is equivalent to JDBCK divide by 2,
frequency division factor for general system clocks to be used in low-power mode. In low-power
mode, the MPC885 automatically switches to the DFNL frequency. To select the DFNL frequency,
load this field with the divide value and set the CSRC bit. A loss-of-lock condition will not occur
when changing the value of this field. This field is cleared by a power-on or hard reset.
000 Divide by 2.
001 Divide by 4.
010 Divide by 8.
011 Divide by 16.
100 Divide by 32.
101 Divide by 64.
110 Reserved.
111 Divide by 256.
24–26
DFNH
Division factor high frequency. Sets the divout1, where divout1 is equivalent to JDBCK divide by
2, frequency division factor for general system clocks to be used in normal mode. In normal mode,
the MPC885 automatically switches to the DFNH frequency. To select the DFNH frequency, load
this field with the divide value and clear CSRC. A loss-of-lock condition does not occur when this
field is changed. This field is cleared by a power-on or hard reset.
000 Divide by 1.
001 Divide by 2.
010 Divide by 4.
011 Divide by 8.
100 Divide by 16.
101 Divide by 32.
110 Divide by 64.
111 Reserved.
27–29
DFUTP
30–31
DFAUTP
UTOPIA clock dividers; see Section 42.2, “UTOPIA Mode Registers.”
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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Freescale Semiconductor
Clocks and Power Control
14.6.2
PLL and Reset Control Register (PLPRCR)
The 32-bit system PLL and reset control register (PLPRCR), shown in Figure 14-13, is used to control the
system frequency and low-power mode operation.
0
4 5
Field
11 12
15
MFN
MFD
—
—
—
—
—
0000
00001
0
1
*
27
30
HRESET
POR
9 10
S
R/W
R/W
Addr
(IMMR & 0xFFFF0000) + 284
16
17
18
19
20
21
Field
—
TEXPS
—
–
—
CSRC
HRESET
—
1
0
0
0
POR
0
1
0
0
0
22
23
MFI
24
25
26
–
CSR
—
FIOPD
PDF
DBRMO
0
0
—
—
—
0000
0
0
0
0
0
0
*
0
R/W
R/W
Addr
(IMMR & 0xFFFF0000) + 286
31
Notes: HRESET is hard reset and POR is power-on reset. * POR depends on the combination of MODCK1 and
MODCK2. See Table 14-5 for more information.
Figure 14-13. PLL and Reset Control Register (PLPRCR)
This register is affected by HRESET and SRESET. Table 14-9 describes PLPRCR bits.
Table 14-9. PLPRCR Field Descriptions
Bits
Name
Description
0–4
MFN
Numerator of the fractional part of the multiplication factor in the formula for the output frequency of
the DPLL and Interface. The range of values for the MFN is 0 to 31. The numerator of the fractional
part of the multiplication factor (MFN) must be less than the denominator of the fractional part of the
multiplication factor (MFD+1).1 If the numerator is larger than the denominator, the output clock
frequency will differ from the desired frequency. If the numerator is zero, the circuit for fractional
division is disabled to save power.
Refer to Section 14.2.2, “Digital Phase Lock Loop and Interface.”
5–9
MFD
Denominator minus 1 of the fractional part of the multiplication factor in the formula for the output
frequency of the DPLL and Interface.The range of values for the MFD is 1 to 31. The denominator
of the fractional part of the multiplication factor(MFD+1) must be greater than the numerator of the
fractional part of the multiplication factor MFN. 1 If the numerator is larger than the denominator, the
output clock frequency will differ from the desired frequency. If the numerator is zero, the circuit for
fractional division is disabled to save power.
Refer to Section 14.2.2, “Digital Phase Lock Loop and Interface.”
10–11
S
Selection Bits for the Divider after the Double Clock (fdck)
00 Divide By 1
01 Divide By 2
10 Divide By 4
11 = Reserved.
Refer to Section 14.2.2, “Digital Phase Lock Loop and Interface.”
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
14-21
Clocks and Power Control
Table 14-9. PLPRCR Field Descriptions (continued)
Bits
Name
12–15
MFI
16
—
17
Description
Integer part of the multiplication factor in the formula for the output frequency of the DPLL and
Interface. The range of values for the MFI is 5 to 15. 1 If the MFI is less than 5, the DPLL uses 5.
Refer to Section 14.2.2, “Digital Phase Lock Loop and Interface.”
Reserved
TEXPS Timer expired status. Internal status bit set when the periodic timer expires, the timebase clock
alarm sets, the decrementer interrupt occurs, or the system resets.
This bit is cleared by writing a 1; writing a zero has no effect.
0 TEXP is negated.
1 TEXP is asserted.
18
—
Reserved, should be cleared.
19
–
Reserved, should be cleared.
20
—
Reserved, should be cleared.
21
CSRC
22–23
–
24
CSR
25
—
26
1
Clock source. Specifies whether DFNH or DFNL generates the general system clock. Cleared by
hard reset.
0 The general system clock is generated by the DFNH field.
1 The general system clock is generated by the DFNL field.
Reserved, should be cleared.
Checkstop reset enable. Enables an automatic reset when the processor enters checkstop mode. If
the processor enters debug mode at reset, reset is not generated automatically; refer to Table 14-10.
See Section 53.5.2.2, “Debug Enable Register (DER).”
Reserved, should be cleared.
FIOPD Force I/O pull down. Indicates when the address and data external pins are driven by an internal
pull-down device in sleep and deep-sleep mode.
0 No pull-down on the address and data bus.
1 Address and data bus is driven low in sleep and deep-sleep mode.
27-30
PDF
Predivision factor minus 1 in the formula for the output frequency of the DPLL and Interface. The
range of values for the PDF is 0 to 15.
Refer to Section 14.2.2, “Digital Phase Lock Loop and Interface.”
31
DBRM
O
DPLL BRM Order bit
0 First Order (should be used when fractional part, MFN/MFD, in undivisible form is greater than
1/10)
1 Second Order (should be used when fractional part, MFN/MFD, in undivisible form is less than
1/10)
This bit is ignored if the MFN is zero.
The total multiplication factor, including both the integer and fractional parts, must be between 5 to 15.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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Clocks and Power Control
Table 14-10 describes PLPRCR[CSR] and DER[CHSTPE] bit combinations.
Table 14-10. PLPRCR[CSR] and DER[CHSTPE] Bit Combinations
PLPRCR[CSR]
DER[CHSTPE]
Checkstop Mode
Result
0
0
No
—
0
0
Yes
—
0
1
No
—
0
1
Yes
Enter debug mode
1
0
No
—
1
0
Yes
Automatic reset
1
1
No
—
1
1
Yes
Enter debug mode
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
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Clocks and Power Control
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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Freescale Semiconductor
Chapter 15
Memory Controller
The memory controller is responsible for controlling a maximum of eight memory banks shared between
a general-purpose chip-select machine (GPCM) and a pair of sophisticated user-programmable machines
(UPMs). It supports a glueless interface to SRAM, EPROM, flash EPROM, regular DRAM devices,
self-refresh DRAMs, extended data output DRAM devices, synchronous DRAMs, and other peripherals.
This flexible memory controller allows the implementation of memory systems with very specific timing
requirements.
The GPCM provides interfacing for simpler, lower-performance memory resources and memory-mapped
devices. The GPCM has inherently lower performance because it does not support bursting. For this
reason, GPCM-controlled banks are used primarily for boot-loading and access to nonburstable
memory-mapped peripherals.
The UPM provides both more features and, because it supports bursting, higher performance. Therefore it
is typically used to interface with higher-performance run-time memory such as DRAM and bursting
SRAM.
The UPM supports address multiplexing of the external bus, periodic timers, and generation of
programmable control signals for row address and column address strobes to allow for a glueless interface
to DRAM devices. The periodic timers allow refresh cycles to be initiated while the address MUXing
provides row and column addresses.
Different timing patterns can be generated for the control signals that govern a memory device. These
patterns define how the external control signals behave in read-access, write-access, burst read-access, or
burst write-access requests. Periodic timers are also available to periodically generate user-defined refresh
cycles.
15.1
Features
The following is a list of the memory controller’s main features:
• Eight memory banks
— 32-bit address decode with mask
— Variable block sizes (32 Kbytes to 4 Gbytes)
— Write-protection capability
— Address types protection for memory bank accesses by internal masters
— Control signal generation machine selection on a per-bank basis
— Support for external master access to memory banks
— Synchronous and asynchronous external masters support
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
15-1
Memory Controller
•
•
General-purpose chip-select machine (GPCM)
— Compatible with SRAM, EPROM, FEPROM, and peripherals
— Global (boot) chip-select available at system reset
— Boot chip-select support for 8-, 16-, and 32-bit devices
— Minimum two clock accesses to external device
— Four byte write enable signals (WE)
— Output enable signal (OE)
Two user-programmable machines
— Programmable-array-based machine controls external signal timing with a granularity of one
quarter of an external bus clock period
— User-specified control-signal patterns run when an internal or external synchronous master
requests a single-beat or burst read or write access.
— User-specified control-signal patterns run when an external asynchronous master requests a
single-beat read or write access.
— UPM periodic timer runs a user-specified control signal pattern to support refresh
— User-specified control-signal patterns can be initiated by software
— Each UPM can be defined to support DRAM devices with depths o