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INA138-Q1, INA168-Q1
SGLS174H – SEPTEMBER 2003 – REVISED MAY 2016
INA1x8-Q1 Automotive-Grade, High-Side, Current-Output, Current-Shunt Monitor
1 Features
3 Description
•
•
The INA138-Q1 and INA168-Q1 (INA1x8-Q1) are
high-side, unidirectional, current sense amplifiers.
Wide input common-mode voltage range, low
quiescent current, and TSSOP and SOT-23
packaging enable use in a variety of applications.
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C6
Complete Unipolar High-Side CurrentMeasurement Circuit
Wide Supply and Common-Mode Ranges
– INA138-Q1: 2.7 V to 36 V
– INA168-Q1: 2.7 V to 60 V
Independent Supply and Input Common-Mode
Voltages
Single Resistor Gain Set
Low Quiescent Current (25 µA Typical)
Wide Temperature Range: –40°C to +125°C
Packages: TSSOP-8, SOT-23-5 (INA168-Q1)
Input common-mode and power-supply voltages are
independent, and range from 2.7 V to 36 V for the
INA138-Q1, and 2.7 V to 60 V for the INA168-Q1.
Quiescent current is only 25 μA, which permits
connecting the power supply to either side of the
current-measurement shunt with minimal error.
The device converts a differential input voltage to a
current output. This current is converted back to a
voltage with an external load resistor that sets any
gain from 1 to over 100. Although designed for
current shunt measurement, the circuit invites
creative applications in measurement and level
shifting.
Both devices are available in a TSSOP-8 package.
The INA168-Q1 is also available in a SOT-23-5
package. Both devices are specified for the –40°C to
+125°C temperature range.
2 Applications
•
•
•
•
Electric Power Steering (EPS) Systems
Body Control Modules
Brake Systems
Electronic Stability Control (ESC) Systems
Device Information(1)
PART NUMBER
INA138-Q1
INA168-Q1
INA168-Q1
PACKAGE
BODY SIZE (NOM)
TSSOP (8)
4.40 mm × 3.00 mm
SOT-23 (5)
2.90 mm × 1.60 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Typical Application Circuit
RS
IS
VIN+
Up to 60 V
VIN+
5 kΩ
VIN–
5 kΩ
VO = ISRSRL / 5 kΩ
RL
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA138-Q1, INA168-Q1
SGLS174H – SEPTEMBER 2003 – REVISED MAY 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Applications ................................................ 11
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device And Documentation Support................. 19
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
12 Mechanical, Packaging, And Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (January 2014) to Revision H
Page
•
Added Device Information, ESD Ratings, Recommended Operating Conditions, and Thermal Information tables,
and Feature Description, Application and Implementation, Power Supply Recommendations, Layout, Device and
Documentation Support, and Mechanical, Packaging, and Orderable Information sections ................................................. 1
•
Added new automotive qualification features bullet, and deleted old bullet........................................................................... 1
•
Changed Application bullets .................................................................................................................................................. 1
•
Added pin names to all figures and removed all pin numbers ............................................................................................... 1
•
Deleted Ordering Information table; information available in the Package Option Addendum at the end of this data sheet 3
•
Added missing minus sign to VIN– pin in pin configuration figures ......................................................................................... 3
•
Deleted thermal resistance from Absolute Maximum Ratings table; see new Thermal Information table ............................. 4
•
Changed RθJA value for both packages .................................................................................................................................. 5
•
Changed VS to V+ throughout data sheet for consistency ..................................................................................................... 5
•
Changed ROUT in Electrical Characteristics table to RL for consistency ................................................................................. 5
•
Changed VIN to VSENSE in Figure 4 ......................................................................................................................................... 6
•
Deleted VS symbol from text regarding voltage drop in Operation section ........................................................................... 9
•
Changed 10 µA to 100 µA in Operation section (typo) .......................................................................................................... 9
•
Changed Figure 9; removed incorrect pin numbers, and moved embedded table to outside of figure ............................... 10
•
Changed Figure 10 ............................................................................................................................................................... 11
•
Changed Figure 15 ............................................................................................................................................................... 15
Changes from Revision F (November 2013) to Revision G
•
Page
Changed part number from IN168-Q1 to INA168-Q1 in multiple locations throughout the document................................... 1
Changes from Revision E (September 2012) to Revision F
•
2
Page
Corrected Y-axis label of QUIESCENT CURRENT versus POWER-SUPPLY VOLTAGE graph ......................................... 6
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SGLS174H – SEPTEMBER 2003 – REVISED MAY 2016
5 Pin Configuration and Functions
PW Package
8-Pin TSSOP
Top View
V
IN–
1
DBV Package
5-Pin SOT-23
Top View
8
V+
IN+
2
7
NC
NC
3
6
OUT
GND
4
5
NC
V
OUT
1
GND
2
IN+
3
V
5
V+
4
V
IN–
Pin Functions
PIN
NAME
GND
NC
INA138-Q1
INA168-Q1
INA168-Q1
TSSOP−8
SOT-23−5
4
2
—
Ground
I/O
DESCRIPTION
3, 5, 7
–
—
No internal connection
OUT
6
1
O
Output current
V+
8
5
I
Power supply voltage
VIN–
1
4
I
Negative input voltage
VIN+
2
3
I
Positive input voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
Supply, V+
Voltage
Common mode
Analog inputs, VIN+, VIN−
MIN
MAX
UNIT
INA138-Q1
−0.3
60
V
INA168-Q1
−0.3
75
V
INA138-Q1
−0.3
60
V
INA168-Q1
−0.3
75
V
V
−40
2
Analog output, OUT
−0.3
40
V
Operating, TA
−55
150
°C
150
°C
150
°C
Differential, (VIN+ – VIN–)
Temperature
Junction, TJ
−65
Storage, Tstg
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage, V+
Common-mode voltage
MIN
NOM
MAX
INA138-Q1
2.7
5
36
INA168-Q1
2.7
5
60
INA138-Q1
2.7
12
36
INA168-Q1
2.7
12
60
–40
25
125
Operating temperature, TA
4
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UNIT
V
V
°C
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SGLS174H – SEPTEMBER 2003 – REVISED MAY 2016
6.4 Thermal Information
THERMAL METRIC
(1)
INA138-Q1,
INA168-Q1
INA168-Q1
PW (TSSOP)
DBV (SOT-23)
8 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
179.1
209.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
62.6
196.8
°C/W
RθJB
Junction-to-board thermal resistance
107.7
107.5
°C/W
ψJT
Junction-to-top characterization parameter
7.0
36.2
°C/W
ψJB
Junction-to-board characterization parameter
106.0
104.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
at TA = −40°C to +125°C, V+ = 5 V, VIN+ = 12 V, and RL = 125 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
INA138-Q1
MIN
INA168-Q1
TYP
MAX
100
500
MIN
TYP
MAX
100
500
UNIT
INPUT
Full-scale sense voltage
Common-mode rejection
VSENSE = VIN+ – VIN−
VIN+ = 2.7 V to 36 V, VSENSE = 50 mV
100
VIN+ = 2.7 V to 60 V, VSENSE = 50 mV
100
Offset voltage (1)
±0.2
Offset voltage vs temperature
±2
V+ = 2.7 V to 36 V, VSENSE = 50 mV
Input bias current
VIN+ = VIN− = 12 V
dB
120
±0.2
1
Offset voltage vs power supply
(V+)
mV
120
±2
mV
μV/°C
1
0.1
10
V+ = 2.7 V to 60 V, VSENSE = 50 mV
0.1
10
μV/V
10
10
μA
206
μA/V
OUTPUT
Transconductance
VSENSE = 10 mV to 150 mV
Transconductance versus
temperature
VSENSE = 100 mV
Nonlinearity error
VSENSE = 10 mV to 150 mV
Total output error
VSENSE = 100 mV
194
206
10
Output impedance
194
10
nA/°C
±0.01%
±0.2 %
±0.01%
±0.2 %
±0.5%
±3.2%
±0.5%
±3.2%
1 || 5
1 || 5
GΩ || pF
Voltage output swing to power
supply (V+)
(V+) – 0.8
(V+) – 1.2
(V+) – 0.8
(V+) – 1.2
V
Voltage output swing to
common mode, VCM
VCM – 0.5
VCM – 1.2
VCM – 0.5
VCM – 1.2
V
FREQUENCY RESPONSE
Bandwidth
Settling time (0.1%)
RL = 5 kΩ
800
800
RL = 125 kΩ
32
32
5-V step, RL = 5 kΩ
1.8
1.8
5-V step, RL = 125 kΩ
30
30
kHz
μs
NOISE
Output-current noise density
TA = 25°C
9
9
pA/√Hz
Total output-current noise
BW = 100 kHz
3
3
nA RMS
POWER SUPPLY
Quiescent current
(1)
VSENSE = 0 V, IO = 0 mA
25
60
25
60
μA
Defined as the amount of input voltage, VSENSE, to drive the output to zero.
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6.6 Typical Characteristics
RL = 500kW
Gain (dB)
RL = 50kW
RL = 5kW
–
CL = 10nF
CL = 1nF
CL = 100pF
Common-Mode Rejection (dB)
at TA = 25°C, V+ = 5 V, VIN+ = 12 V, and RL = 125 kΩ (unless otherwise noted)
–
Figure 2. Common-Mode Rejection vs Frequency
Figure 1. Gain vs Frequency
VSENSE = (VIN+ – VIN–)
Total Output Error (%)
Power-Supply Rejection (dB)
–55°C
150°C
–
25°C
–
–
VSENSE (mV)
Output error is essentially
independent of both
V+ supply voltage and
input common-mode voltage.
Figure 4. Total Output Error vs VSENSE
150ºC
Quiescent Current (µA)
Total Output Error (%)
Figure 3. Power-Supply Rejection vs Frequency
–
125ºC
25ºC
–55ºC
(V+) > 36 V
–
Power-Supply Voltage (V)
Figure 5. Total Output Error vs Power-Supply Voltage
6
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Power-Supply Voltage (V)
Figure 6. Quiescent Current vs Power-Supply Voltage
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Typical Characteristics (continued)
at TA = 25°C, V+ = 5 V, VIN+ = 12 V, and RL = 125 kΩ (unless otherwise noted)
m
m
Figure 7. Step Response
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Figure 8. Step Response
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7 Detailed Description
7.1 Overview
The INA138-Q1 and INA168-Q1 devices (INA1x8-Q1) are comprised of a high-voltage, precision operational
amplifier, precision thin film resistors trimmed in production to an absolute tolerance, and a low-noise output
transistor. The INA1x8-Q1 are powered from a single power supply, and the input voltages can exceed the power
supply voltage. The INA1x8-Q1 are ideal for measuring small differential voltages, such as those generated
across a shunt resistor, in the presence of large common-mode voltages. The Functional Block Diagram
illustrates the functional components within both INA138-Q1 and INA168-Q1 devices.
7.2 Functional Block Diagram
VIN+
VIN±
V+
+
OUT
GND
8
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7.3 Feature Description
7.3.1 Output Voltage Range
The output of the INA1x8-Q1 is a current that is converted to a voltage by the load resistor, RL. The output
current remains accurate within the compliance voltage range of the output circuitry. The shunt voltage and the
input common-mode and power-supply voltages limit the maximum possible output swing. The maximum output
voltage (Vout max) compliance is limited by either Equation 1 or Equation 2, whichever is lower:
Vout max = (V+) – 0.7 V − (VIN+ – VIN−)
(1)
Vout max = VIN− − 0.5 V
(2)
or
7.3.2 Bandwidth
Measurement bandwidth is affected by the value of the load resistor, RL. High gain produced by high values of
RL yields a narrower measurement bandwidth (see the Typical Characteristics). For the widest possible
bandwidth, keep the capacitive load on the output to a minimum. Reduction in bandwidth due to capacitive load
is shown in the Typical Characteristics section.
If bandwidth limiting (filtering) is desired, add a capacitor to the output (see Figure 12). This capacitor does not
cause instability.
7.4 Device Functional Modes
For proper operation, the INA1x8-Q1 must operate within the specified limits. Operating either device outside of
their specified power-supply voltage range, or their specified common-mode range, results in unexpected
behavior, and is not recommended. Additionally, operating the output beyond the specified limits with respect to
power-supply voltage and input common-mode voltage also produces unexpected results. See the Electrical
Characteristics for the device specifications.
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Operation
Figure 9 illustrates the basic circuit diagram for both the INA138-Q1 and INA168-Q1. Load current IS is drawn
from supply VP through shunt resistor RS. The voltage drop in the shunt resistor is forced across RG1 by the
internal op amp, causing current to flow into the collector of Q1. External resistor RL converts the output current,
IO, to a voltage, VOUT, at the OUT pin. The transfer function for the INA1x8-Q1 is shown in Equation 3:
IO = gm (VIN+ − VIN−)
where
•
gm = 200 μA/V
(3)
In the circuit of Figure 9, the input voltage, (VIN+ − VIN−), is equal to IS × RS. The output voltage, VOUT, is equal to
IO × RL. The transconductance, gm, of the INA1x8-Q1 is 200 μA/V. The complete transfer function for the current
measurement amplifier in this application is shown in Equation 4:
VOUT = (IS) (RS) (200 μA/V) (RL)
(4)
The maximum differential input voltage for accurate measurements is 0.5 V, producing a 100-μA output current.
A differential input voltage of up to 2 V does not cause damage. Differential measurements (VIN+ and VIN− pins)
must be unipolar, with a more-positive voltage applied to the VIN+ pin. If a more-negative voltage is applied to the
VIN+ pin, IO goes to zero, but no damage occurs.
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Application Information (continued)
VP
Load Power Supply
2.7 V to 36 V(1)
V+ power can be common or
V+
independent of load supply.
2.7 V ≤ (V+) ≤ 36 V
(1)
Shunt
RS
IS
VIN–
VIN+
R G1
5 kΩ
Load
R G1
5 kΩ
Q1
OUT
INA138-Q1
+
IO
GND
RL
VO
–
Copyright © 2016, Texas Instruments Incorporated
(1)
Maximum VP and V+ voltage is 60 V with INA168-Q1.
Figure 9. Basic Circuit Connections
Table 1. Voltage Gains and Corresponding Load-Resistor Values
10
VOLTAGE GAIN
EXACT RL (kΩ)
NEAREST 1% RL (kΩ)
1
5
4.99
2
10
10
5
25
24.9
10
50
49.9
20
100
100
50
250
249
100
500
499
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8.2 Typical Applications
The INA1x8-Q1 are designed for current-shunt measurement circuits, as shown in Figure 9, but its basic function
is useful in a wide range of circuitry. With a little creativity, many unforeseen uses can be found in measurement
and level-shifting circuits. A few ideas are illustrated in the following subsections.
8.2.1 Buffering Output to Drive an ADC
Digitize the output of the INA138-Q1 or INA168-Q1 devices using a 1-MSPS analog-to-digital converter (ADC).
IS
RS
VIN+
VIN±
R
+
OUT
ADC
OPA340
INA138-Q1
or
INA168-Q1
RL
GND
Buffer amplifier
drives ADC without
affecting gain
C
Figure 10. Buffering Output to Drive an ADC
8.2.1.1 Design Requirements
For this design example, use the input parameters shown in Table 2.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Supply voltage, V+
Common-mode voltage, VCM
5V
INA138-Q1: 2.7 V to 36 V
INA168-Q1: 2.7 V to 60 V
Full-scale shunt voltage, VSENSE
50 mV to 100 mV
Load resistor, RL
5 kΩ to 500 kΩ
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Selecting RS and RL
In Figure 10, the value chosen for the shunt resistor, RS, depends on the application and is a compromise
between small-signal accuracy and maximum permissible voltage loss in the measurement line. High values of
RS provide better accuracy at lower currents by minimizing the effects of offset, while low values of RS minimize
voltage loss in the supply line. For most applications, best performance is attained with an RS value that provides
a full-scale shunt voltage range of 50 mV to 100 mV. Maximum input voltage for accurate measurements is 500
mV.
Choose an RL that provides the desired full-scale output voltage. The output impedance of the INA1x8-Q1 OUT
pin is very high, permitting the use of RL values up to 500 kΩ with excellent accuracy. The input impedance of
any additional circuitry at the output must be much higher than the value of RL to avoid degrading accuracy.
Some ADCs have input impedances that significantly affects measurement gain. The input impedance of the
ADC can be included as part of the effective RL if the ADC input can be modeled as a resistor to ground.
Alternatively, an op amp can be used to buffer the ADC input, as shown in Figure 10. The INA1x8-Q1 are current
output devices, and as such, have an inherently large output impedance. The output currents from the amplifier
are converted to an output voltage using the load resistor, RL, connected from the amplifier output to ground. The
ratio of the load resistor value to that of the internal resistor value determines the voltage gain of the system.
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In many applications, digitizing the output of the INA1x8-Q1 is required. Digitizing is accomplished by connecting
the output of the amplifier to an ADC. It is very common for an ADC to have a dynamic input impedance. If the
INA1x8-Q1 output is connected directly to an ADC input, the input impedance of the ADC is effectively connected
in parallel with gain setting resistor RL. This parallel impedance combination affects the gain of the system and
the impact on the gain is difficult to estimate accurately. A simple solution that eliminates the paralleling of
impedances, and simplifies the gain of the circuit is to place a buffer amplifier, such as the OPA340, between the
output of the INA1x8-Q1 and the input to the ADC.
Figure 10 illustrates this concept. Notice that a low-pass filter is placed between the OPA340 output and the
input to the ADC. The filter capacitor is required to provide any instantaneous demand for current required by the
input stage of the ADC. The filter resistor is required to isolate the OPA340 output from the filter capacitor in
order to maintain circuit stability. The values for the filter components vary according to the operational amplifier
used for the buffer and the particular ADC selected. More information regarding the design of the low-pass filter
is found in the TI Precision Design, 16 bit 1MSPS Data Acquisition Reference Design for Single-Ended
Multiplexed Applications, TIPD173.
Figure 11 shows the expected results when driving an ADC at 1 MSPS with and without buffering the INA1x8-Q1
output. Without the buffer, the high impedance of the INA1x8-Q1 reacts with the input capacitance and sampleand-hold capacitance of the ADC, and does not allow the sampled value to reach the correct final value before
the ADC is reset, and the next conversion starts. Adding the buffer amplifier significantly reduces the output
impedance driving the sample-and-hold circuitry, and allows for higher conversion rates.
8.2.1.3 Application Curve
Input to ADC (0.25 V/div)
with buffer
without Buffer
Time
Figure 11. Driving an ADC With and Without a Buffer
12
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8.2.2 Output Filter
Filter the output of the INA1x8-Q1 devices.
VIN+
f–3dB
VIN–
INA138-Q1
f–3dB =
2pRLCL
VO
OUT
GND
CL
RL
Figure 12. Output Filter
8.2.2.1 Design Requirements
For this design example, use the input parameters shown in Table 3.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
INA138-Q1: 2.7 V to 36 V
Supply voltage, V+
INA168-Q1: 2.7 V to 60 V
INA138-Q1: 2.7 V to 36 V
Common-mode voltage, VCM
INA168-Q1: 2.7 V to 60 V
Full-scale shunt voltage, VSENSE
50 mV to 100 mV
Load resistor, RL
5 kΩ to 500 kΩ
8.2.2.2 Detailed Design Procedure
A low-pass filter can be formed at the output of the INA1x8-Q1 simply by placing a capacitor of the desired value
in parallel with the load resistor. First, determine the value of the load resistor needed to achieve the desired gain
by using Table 1. Next, determine the capacitor value that results in the desired cutoff frequency according to the
equation shown in Figure 12. Figure 13 illustrates various combinations of gain settings (determined by RL) and
filter capacitors.
8.2.2.3 Application Curve
RL = 500kW
Gain (dB)
RL = 50kW
RL = 5kW
–
CL = 10nF
CL = 1nF
CL = 100pF
–
Figure 13. Gain vs Frequency
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: INA138-Q1 INA168-Q1
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8.2.3 Offsetting the Output Voltage
For many applications using only a single power supply, the output voltage may have to be level shifted away
from ground when there is no load current flowing in the shunt resistor. Level shifting the output of the INA1x8Q1 is easily accomplished by one of two simple methods shown in Figure 14. Method (a) on the left-hand side of
Figure 14 illustrates a simple voltage-divider method. This method is useful for applications that require the
output of the INA1x8-Q1 to remain centered with respect to the power supply at zero load current through the
shunt resistor. Using this method, the gain is determined by the parallel combination of R1 and R2, while the
output offset is determined by the voltage divider ratio of R1 and R2, as shown in Figure 14(a). For applications
that require a fixed value of output offset independent of the power-supply voltage, use current-source method
(b) shown on the right-hand side of Figure 14. With this method, a REF200 constant current source is used to
generate a constant output offset. Using this method, the gain is determined by RL, and the offset is determined
by the product of the value of the current source and RL.
VR
VIN+
VIN–
VIN+
R1
INA138-Q1
INA138-Q1
VO
OUT
VIN–
100 μA
RL
R2
Gain Set by R1 || R2
(VR)R2
R1 + R2
VO
OUT
Gain Set by RL
Output Offset = (100 μA)(RL)
(independent of V+)
Output Offset =
b) Using current source.
a) Using resistor divider.
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Offsetting the Output Voltage
8.2.4 Bipolar Current Measurement
Configure the INA1x8-Q1 as shown in Figure 15 for applications where bidirectional current measurement is
required. Two INA1x8-Q1 devices are required; connect the inputs across the shunt resistor as shown in
Figure 15. A comparator, such as the TLV3201, is used to detect the polarity of the load current. The magnitude
of the load current is monitored across the resistor connected between ground and the connection labeled
Output. In this example, the 100-kΩ resistor results in a gain of 20 V/V. The 10-kΩ resistors connected in series
with the INA1x8-Q1 output current are used to develop a voltage across the comparator inputs. Two diodes are
required to prevent current flow into the INA1x8-Q1 output because only one device at a time provides current to
the Output connection of the circuit. The circuit functionality is illustrated in Figure 16.
14
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INA138-Q1, INA168-Q1
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SGLS174H – SEPTEMBER 2003 – REVISED MAY 2016
±1-A
Load Curent
RS
100 m
VIN+
VIN±
VIN±
VIN+
Bus
Voltage
Load
Current
5k
5V
5k
5k
5k
V+
5V
V+
+
INA138-Q1
or
INA168-Q1
+
OUT
OUT
GND
1N4148
INA138-Q1
or
GND INA168-Q1
1N4148
+
Sign
TLV3201
10 k
10 k
Output
100 k
Figure 15. Bipolar Current Measurement
8.2.4.1 Application Curve
Voltage
Load Current
Output
Sign
Time
Figure 16. Bipolar Current Measurements Results (Arbitrary Scale)
Copyright © 2003–2016, Texas Instruments Incorporated
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8.2.5 Bipolar Current Measurement Using Differential Input of an ADC
Use the INA1x8-Q1 with an ADC such as the ADS7870 programmed for differential-mode operation; Figure 17
illustrates this configuration. In this configuration, the use of two INA138-Q1s or INA168-Q1s allows for
bidirectional current measurement. Depending on the polarity of the current, one of the INA devices provides an
output voltage, while the other INA device output is zero. In this way, the ADC reads the polarity of current
directly, without the need for additional circuitry.
RS
VIN–
VIN+
VIN+
VIN–
5V
5V
5V
INA138-Q1
OUT
INA138-Q1
GND
RL
25 kΩ
GND
OUT
12-Bit
ADC
Mux
RL
25 kΩ
ADC programmed for differential input.
Depending on polarity of current, one INA138-Q1 provides
an output voltage, and the output of the other device is zero.
Figure 17. Bipolar Current Measurement Using Differential Input of the ADC
16
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INA138-Q1, INA168-Q1
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SGLS174H – SEPTEMBER 2003 – REVISED MAY 2016
8.2.6 Multiplexed Measurement Using Logic Signal for Power
Measure multiple loads as shown in Figure 18. In this configuration, each INA138-Q1 or INA168-Q1 device is
powered by the digital I/O from the ADS7870. Multiplexing is achieved by switching on or off each desired I/O.
Other INA168-Q1s
Digital I/O on the ADS7870 provides power to select
the desired INA168-Q1. Diodes prevent output current of
the on INA168-Q1 from flowing into the off INA168-Q1.
INA168-Q1
5V
–
INA168-Q1
–
12-Bit
ADC
Mux
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Multiplexed Measurement Using Logic Signal for Power
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: INA138-Q1 INA168-Q1
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INA138-Q1, INA168-Q1
SGLS174H – SEPTEMBER 2003 – REVISED MAY 2016
www.ti.com
9 Power Supply Recommendations
The input circuitry of the INA1x8-Q1 can accurately measure beyond the power-supply voltage, V+. For example,
the V+ power supply can be 5 V, whereas the load power-supply voltage goes up to 36 V with the INA138-Q1, or
60 V with the INA168-Q1. However, the output voltage range of the OUT pin is limited by the lesser of the two
voltages (see the Output Voltage Range section). Place a 0.1-µF capacitor near the power-supply pin on the
INA1x8-Q1. Additional capacitance may be required for applications with noisy power-supply voltages.
10 Layout
10.1 Layout Guidelines
Figure 19 shows the basic connection of the INA1x8-Q1 in the TSSOP-8 package. Connect input pins VIN+ and
VIN− as closely as possible to the shunt resistor to minimize any resistance in series with the shunt resistance.
Output resistor RL is shown connected between the OUT pin and ground. Best accuracy is achieved with the
output voltage measured directly across RL. Measuring directly across RL is especially important in high-current
systems where load current could flow in the ground connections and affect measurement accuracy.
No power-supply bypass capacitors are required for stability of the INA1x8-Q1. However, applications with noisy
or high-impedance power supplies may require decoupling capacitors to reject power-supply noise. Connect
bypass capacitors close to the device pins.
10.2 Layout Example
To Load
VIN-
Sense/Shunt
Resistor
INA138-Q1
INA168-Q1
V+
VIN+
NC
NC
OUT
GND
NC
Supply
Bypass
Capacitor
RL
To Bus Voltage
Via to Ground Plane
Via to Power Plane
Figure 19. Typical Layout Example
18
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INA138-Q1, INA168-Q1
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SGLS174H – SEPTEMBER 2003 – REVISED MAY 2016
11 Device And Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
• TI Precision Design, 16 bit 1MSPS Data Acquisition Reference Design for Single-Ended Multiplexed
Applications, TIPD173.
11.2 Related Links
Table 4 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
INA138-Q1
Click here
Click here
Click here
Click here
Click here
INA168-Q1
Click here
Click here
Click here
Click here
Click here
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, And Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: INA138-Q1 INA168-Q1
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19
PACKAGE OPTION ADDENDUM
www.ti.com
23-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
INA138QPWRQ1
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA138
INA168QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LUIQ
INA168QPWRQ1
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
INA168
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Mar-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF INA138-Q1, INA168-Q1 :
• Catalog: INA138, INA168
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
INA138QPWRQ1
Package Package Pins
Type Drawing
TSSOP
PW
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
7.0
B0
(mm)
K0
(mm)
P1
(mm)
3.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
INA138QPWRQ1
TSSOP
PW
8
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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