High-Performance mm-Wave and Wideband Large

High-Performance mm-Wave and Wideband Large
High-Performance mm-Wave and
Wideband Large-Signal Amplifiers
Yi Zhao
High-Performance mm-Wave and
Wideband Large-Signal Amplifiers
Proefschrift
ter verkrijging van de graad van doctor
aan de Technische Universiteit Delft,
op gezag van de Rector Magnificus prof. ir. K.C.A.M. Luyben,
voorzitter van het College voor Promoties,
in het openbaar te verdedigen
op donderday 24 oktober 2013 om 12:30 uur
door
YI ZHAO
elektrotechnisch ingenieur
geboren te Mengzhou, China.
Dit proefschrift is goedgekeurd door de promotor:
Prof. dr. J. R. Long
Samenstelling promotiecommissie:
Rector Magnificus
voorzitter
Prof. dr. J. R. Long
Technische Universiteit Delft, promotor
Prof. dr. P. Ferrari
Université de Grenoble
Prof. dr. ir. M. Möller
Universität des Saarlandes
Prof. dr. F. Svelto
Universitá degli Studi di Pavia
Prof. dr. ir. F. E. van Vliet Universiteit Twente
Prof. dr. R. B. Staszewski
Technische Universiteit Delft
Dr. M. Spirito
Technische Universiteit Delft
Reservelid:
Prof. dr. A. Neto
Technische Universiteit Delft
ISBN 978-94-6186-204-4
c 2013 by YI ZHAO
Copyright All rights reserved. No part of this publication may be reproduced or distributed in any form
of by any means, or stored in a database or retrieval system, without any prior permission
of the copyright owner.
Keywords: passive-aided RF and mm-wave circuit design, power amplifier, power combiner,
optical modulator driver, distributed amplifier, transformer, transmission line.
Printed in the Netherlands
To my father and my brother
“You’ve got to think about big things while you’re doing small
things, so that all the small things go in the right direction.”
Alvin Toffler
Preface
In hindsight, my 5-year Ph.D. trajectory can be divided into three periods. The first two
and half years of the research was supported in part by the European MEDEA+ project
Silicon Analogue to Millimeter-wave Technologies (SIAM). The seed for developing advanced
on-chip passive components was sown at the very beginning of that period, and several mmwave power combiners and amplifiers then came into being. After the SIAM project ended
in 2011, I continued my work on the passive-aided large-signal amplifier design, when the
wideband distributed amplifier for optical fiber communication was developed. In 2012, I had
the opportunity to work for IBM USA on benchmarking the newly developed SiGe-BiCMOS
technology. However, only a small part of the work is included in this thesis due to changes
in schedule.
I have to admit that my love for power amplifiers did not start at first sight. I had imagined a more ‘ambitious’ and challenging task, e.g., developing a fully-integrated, multiband,
multifunctional transceiver. However, it did not take me long to realize addressing the fundamental problems in a circuit building block can be just as challenging. The design of a
fully-digital Mach-Zenhder modulator driver later on extends the research scope into the
system level, satisfying my desire for a more complicated design from the first place.
The completion of this thesis involves a lot more than just financial resources and my hard
work. Many important people have contributed in one way or another to it along the way
and I want to express my sincere gratitude towards them.
My first and deepest gratitude goes to my promotor and advisor, Prof. John R. Long. Your
knowledge and expertise have inspired me to pursue a Ph.D. degree. It was during one of our
last meetings in NXP Semiconductors in Eindhoven you presented me the opportunity to
work on the SIAM project. Your guidance, supervision, encouragement, time and efforts in
all these years are highly appreciated. John, I owe you much for my professional development,
for my (yet) still-improving technical writing skills, and for career opportunities outside of
the university. The small talks in Delft, the lunchtime chats at IBM cafeteria, the dinnertime
laughters in Vermont, and your sense of humor will also be greatly missed. Also, thank you
for making such a big effort to be at my wedding!
I would like to thank the members of my doctoral examination committee for their comments,
discussions, time and efforts.
My colleague and officemate, Marco Spirito, thank you for your company in the office. More
importantly, thank you for all the fruitful discussions and your tremendous support in testing.
I remember very well the many hours we spent in our lab on the 18th floor working on PA
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Preface
large-signal measurement. On this matter, I would also like to thank Atef Akhnoukh and
Wil Straver. Atef, you may be the most patient and cautious person I have ever known so
far. Thanks for your time and efforts on arranging MPW tapeouts and helping me through
many testing occasions and catch deadlines. Wil, you are a great technician! I admire your
skills and experiences in test fixture assembly. You seem always having a solution to my
problems such as using a brass screw as the heat sink for the modulator driver.
There are so many colleagues, Ph.D. students and friends, who have made my life in the
Netherlands easier and more pleasant. Wanghua, we always seem to have so much to talk
about. Thanks for being here, for your company and understanding. We will continue our
friendship in Marvell, in California. Yanyu, we both participated in the SIAM project. Thanks
for all the discussions and helpful tips. Coby, our bond rooted long ago in Fudan University
in 2001. Thanks for being a friend I can always turn to far away from home. Leonardo, a
special thanks to you for being together with me in the American adventure and helping me
out whenever needed. Our friendship started late but I hope it grows deep. Yuanyuan, thanks
for sharing the apartment with me. The 3 years we spent together in the Beethovenlaan,
Delft are very crucial for the progress on my Ph.D. study. Marion, our secretary, thanks for
taking care of all the paperwork and bringing positive energy to our group. Antoon, thank
you for solving all my computer problems and answering my somewhat related but silly
questions. Zu-yao Zhang, the technician from the 13th floor, thanks for helping me out of
a couple of emergency situations for deadlines. Koen Buisman, thanks for your support in
NPN transistor and temperature measurement. Arturo Santaniello, thanks for your work and
efforts on helping me with the PA large-signal measurement. My other Italian colleagues,
Gennaro Gentile, Mauro Marchetti, Michele Squillante and Luca, thank you for your kind
company and support in the labs, where I spent lots of hours.
I would prefer to mention everybody one by one if possible. Nevertheless, all other staff
members and colleagues: Prof. Bogdan Staszewski, Dr. Leo de Vreede, Dr. Wouter Serdijn,
Dr. Chris Verhoeven, Loek, Akshay, Nitz, Sharon, Chan, Morteza, Masoud, Massoud, Iman,
Ali, Cong, Rui, Duan, Yongjia, Yao, Ruimin, Qinwen, Chi, David, Marijn, Senad, Wannaya,
Cees-Jeroen, Mark, Andre and whoever I may forget, thanks for your company and for
creating such a nice and pleasant academic environment. Cees-Jeroen and Mark, thanks for
the help in translating my propositions and summary.
I spent almost one and a half years in Essex Junction, Vermont, USA, where I met and made
some new friends, whom I also wish to thank. Kurt and Donna, ‘my American parents’, you
make Nico and me feel very special, feel like part of the family. Thank you for your care,
support, and hospitality. Kurt, a special thanks to you for getting my H-1B visa arranged,
which smooths my transition from Europe to USA. Jeff and Biz, many thanks for your
advice, experience sharing, great food and hospitality. I look forward to going with you to
Maine for the lobster festival. Jack, thanks for all your support on tapeouts and at IBM, and
thanks to the family as well for being a great host. David, thank you for the opportunity to
work with the team and for everything you did for me at IBM. Also, thank you and MaryLou for inviting us to the house and I owe you my first experience with the Super Bowl
game. Anna, thank you for getting me out of a ‘home-less’ situation in Vermont. Thanks for
Preface
ix
sharing the apartment, for your company, sweetness and everything. Thomas, many thanks
for answering all of the HBT modeling related questions, and your company in Vermont.
Look forward to meeting you (often) in California. Pui, Yun and Lin, thanks for sharing
your life and hanging out with me outside work, and also thanks to Bob and Santosh for
joining our team. All my other friends: Peter, Kelly, Will, Yan, Zhenzhen, Yanting, Beth
Ann, Andy, Laura, Chaojiang, Daniel and others to be mentioned, thank you all for making
my stay in Vermont richer and more wonderful!
My family in China, I am so lucky to have you in my life! Thank you for all of the unconditional love and support you have given me all the past years, for which I am eternally
grateful. A special thanks to my brother and sister-in-law, thank you for taking care of our
family while I am so far away. My family-in-law in the Netherlands, thank you for loving me
as a family, as a daughter, and as a sister.
Nico, my date-boyfriend-fiancé-husband, your role in my life has changed a few times in the
past 5 years, but what a solid support you are to me never changes. Thank you for all of
it, for bearing the occasional long working days and nights, for comforting and motivating
me, for your hard work in LATEX, SketchUp, Illustrator and translation. Also, thank you for
leaving the family and going on a new adventure with me to the USA!
To myself, I have longed for this moment. Well, it seems about time to close this life chapter.
Cherishing all my experiences in the past years, I will start a new journey with great passion
and the dream to know more about everything.
Yi Zhao
October 2013, Schiedam
x
Preface
Contents
Preface
vii
1 Introduction
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1 Multi-gigahertz Wireless Bandwidth . . . . . . . . . . . . . .
1.1.2 Operational Benefits at mm-Wave Frequencies . . . . . . . . .
1.1.3 mm-Wave Standardization and Applications . . . . . . . . . .
1.1.4 Advantages of Optical Fiber Communications . . . . . . . . .
1.2 Research Topics and Design Challenges . . . . . . . . . . . . . . . . .
1.2.1 Electrical Transmitter and RF Power Output . . . . . . . . .
1.2.2 Optical Transmitter and MZ Modulator Driver . . . . . . . .
1.2.3 Influences from Technology Scaling . . . . . . . . . . . . . . .
1.3 Passive-aided Amplifier Design Objectives . . . . . . . . . . . . . . .
1.3.1 mm-Wave Output-combining Power Amplifier . . . . . . . . .
1.3.2 Silicon-based Distributed Amplifier Optical Modulator Driver
1.4 Organization of this Thesis . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2 Literature Survey of mm-Wave Power Amplifiers
2.1 Millimeter-wave Power Amplifiers . . . . . . . . . .
2.1.1 Basics of Power Amplifiers . . . . . . . . . .
2.1.2 Bias Classes . . . . . . . . . . . . . . . . . .
2.1.3 Power Gain and Efficiency Trade-off . . . .
2.1.4 Impedance Matching at mm-Wave . . . . .
2.1.5 Reliability . . . . . . . . . . . . . . . . . . .
2.2 Prior-art Millimeter-Wave Power Amplifiers . . . .
2.2.1 Single-ended and Differential Topologies . .
2.2.2 Single-cell Amplifiers . . . . . . . . . . . . .
2.2.3 Output-Combining Amplifiers . . . . . . . .
2.3 On-chip Passive Power Combiners . . . . . . . . . .
2.3.1 LC Balun Combiner . . . . . . . . . . . . .
2.3.2 Marchand Balun Combiner . . . . . . . . . .
2.3.3 Wilkinson Combiner . . . . . . . . . . . . .
2.3.4 Generic Transmission Line based Combiner .
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Contents
2.3.5 Monolithic Transformer Combiner . . . . . . . . . . . . . . . . . . . .
2.3.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 On-chip mm-Wave Power Combiners and Splitters
3.1 mm-Wave Monolithic Passive Combiners . . . . . . . . . . . .
3.1.1 Design Requirements . . . . . . . . . . . . . . . . . . .
3.1.2 Interwinding Capacitance . . . . . . . . . . . . . . . .
3.1.3 Substrate Shielding . . . . . . . . . . . . . . . . . . . .
3.2 Transformer-type Power Combiners . . . . . . . . . . . . . . .
3.2.1 Parasitic Compensation . . . . . . . . . . . . . . . . .
3.2.2 Frequency Scalability . . . . . . . . . . . . . . . . . . .
3.2.3 Prototypes and Characterization . . . . . . . . . . . .
3.2.4 Lumped-element Model . . . . . . . . . . . . . . . . .
3.3 S-CPW-type Power Combiners . . . . . . . . . . . . . . . . . .
3.3.1 Slow-wave Propagation . . . . . . . . . . . . . . . . . .
3.3.2 S-CPW Comparison in SiGe-BiCMOS and SOI-CMOS
3.3.3 Prototypes and Characterization . . . . . . . . . . . .
3.3.4 Lumped-element Model . . . . . . . . . . . . . . . . .
3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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4 Multi-stage and Output-combining Power Amplifier Design
4.1 Single-stage Topology Comparison . . . . . . . . . . . . . . . . .
4.1.1 Power Gain, Stability and Reverse Isolation . . . . . . .
4.1.2 Collector-Emitter Breakdown Voltage . . . . . . . . . . .
4.1.3 Temperature Dependence . . . . . . . . . . . . . . . . .
4.1.4 Output Power and Efficiency . . . . . . . . . . . . . . . .
4.1.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Electrical Stability . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 Neutralization . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 Parasitic Reduction and Equalization . . . . . . . . . . .
4.2.3 On-chip Isolation . . . . . . . . . . . . . . . . . . . . . .
4.3 Power-combining PA Prototypes . . . . . . . . . . . . . . . . . .
4.3.1 Prototype Specifications . . . . . . . . . . . . . . . . . .
4.3.2 Top-level Design Considerations . . . . . . . . . . . . . .
4.3.3 Transformer Output Combining and Interstage Coupling
4.3.4 60 and 77/79 GHz-band SiGe-BiCMOS PA Prototypes .
4.3.5 60 GHz-band CMOS-SOI PA Prototype . . . . . . . . .
4.4 Study Case - Cascode, Output-Combining PA . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Power Amplifier Prototype Testing and Performance
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Contents
5.1
Large-signal Measurement Setup . . . . .
5.1.1 Three-step Calibration Procedure
5.1.2 V- and W-band Test Setups . . .
5.2 PA Prototype Performance . . . . . . . .
5.2.1 Experimental Results . . . . . . .
5.2.2 Performance Comparisons . . . .
References . . . . . . . . . . . . . . . . . . . .
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6 A Digitally-Controlled, Differential Distributed Amplifier MZM
6.1 Mach-Zehnder Modulator Driver . . . . . . . . . . . . . . . . . . . .
6.1.1 Design Challenges . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Limitations of the Conventional MZ Modulator Driver . . . . . . .
6.2.1 Bandwidth Limitations . . . . . . . . . . . . . . . . . . . . .
6.2.2 Maximum Number of DA Stages . . . . . . . . . . . . . . .
6.3 Digitally-Controlled DA Modulator Driver . . . . . . . . . . . . . .
6.3.1 Distributed LA with a Periodically-Loaded Output Line . .
6.3.2 Clock and Data Timing Control . . . . . . . . . . . . . . . .
6.3.3 Quadrature Clock Generation . . . . . . . . . . . . . . . . .
6.3.4 Clock Phase Control . . . . . . . . . . . . . . . . . . . . . .
6.3.5 Digital Latch and Limiting Amplifier Stage . . . . . . . . . .
6.3.6 Output Transmission Line and On-chip Back Termination .
6.4 Prototype Characterization . . . . . . . . . . . . . . . . . . . . . .
6.4.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . .
6.4.3 Performance Comparison . . . . . . . . . . . . . . . . . . . .
6.4.4 Prototype Power Dissipation Analysis . . . . . . . . . . . . .
6.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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7 Conclusions and Recommendations
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7.1 Major Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.2 Recommendations for Future Work . . . . . . . . . . . . . . . . . . . . . . . 178
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
A Thru-Reflect-Line De-embedding
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References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Summary
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Samenvatting
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List of Publications
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Curriculum Vitae
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xiv
Contents
Chapter 1
Introduction
Enjoying the flexibility and comforts of the wireless world, consumer demand for increased
data throughput never pauses. The proliferation of 3G/4G wireless communication devices
and the strong investment in their research and development drive more data usage and
spectrum congestion over time, which in turn encourages alternative and complementary
technologies to be developed. Wireless communications in millimeter-wave (mm-wave) bands
promise multi-gigabit transmission rate (e.g., exceeding 1 Gb/s) over a short range because
of the availability of several gigahertz bandwidth [1] [2]. Apart from channel capacity and
the virtues of wireless connections, it is also exempt from license fees and restrictions in the
(unlicensed) 60 GHz band [3]. The emerging interests and intensive research efforts from both
academia and industry envisage high-volume consumer and commercial network applications
for the technology in the near future, such as WiGig [4], automotive radar [5] and wireless
backhaul [6].
Meanwhile, reliable and higher date rates (e.g., > 100 Gb/s) are expected from its wired
counterpart, where optical fiber communication receives considerable attention. It uses light
instead of the electrical transmission of signals to provide up to terabit per second data rates
across thousands of kilometers [7] [8]. It is enabled by the less than 0.25 dB/km of attenuation
around the emission wavelength of 1.55 µm [9], and the broadband merits of optical fibers.
The unprecedented speed expands its applications to metropolitan area, fiber-to-the-home
(FTTH), long-span backhaul and submarine networks [10] [11].
Recently, an emerging technology called ‘mm-wave fiber-wireless’ (Fi-Wi) integrates the
optical fiber network with mm-wave wireless infrastructure [12] [13]. Bimodal Fi-Wi systems
incorporate the strengths of both technologies, and are expected to thrive by offering high
transmission speed, throughput and flexible infrastructure.
However, despite the appealing transmission rate promised by mm-wave wireless and optical
fiber communications, they also pose many challenges for their hardware realizations due
to the high operating frequency and wide bandwidth requirements. Historically, mm-wave
and optical electronics have been dominated by III–V compound semiconductor technologies, such as gallium arsenide (GaAs) and indium phosphide (InP) [14] [15] [16]. However,
for low-cost, mass-market electronics, the integration density and cost/volume advantages
demonstrated by silicon technologies are superior. Technology scaling provides a transistor
cut-off frequency, fT , or gain-bandwidth product above 200 GHz for advanced SiGe-BiCMOS
1
2
Chapter 1. Introduction
240 MHz
2160 MHz 1728 MHz
120 MHz
57 58 59 60 61 62 63 64 65 66 71
China
Japan
E-band
USA/Canada/Korea
EU
Automotive radar
76
100 MHz
81
86
92
E-band
94 95
Freq, in GHz
E-band
Wireless backhaul in the E-band
Figure 1.1: Millimeter-wave spectrum allocations across 57–95 GHz.
and CMOS processes [17] [18]. However, high-speed I/O, RF and mm-wave circuit integration is challenged by the concomitant decrease in breakdown voltage and gain available in
the desired frequency band. On the other hand, up to 10 back-end-of-line (BEOL) metal
layers are offered by advanced silicon technologies, which opens up new opportunities for
high-quality passive components on-chip (e.g., low-loss and compact magnetic components).
This dissertation explores the feasibility of realizing high-performance RF and mm-wave
circuits by employing sophisticated on-chip passive components advantageously in silicon
technologies, in other words, passive-aided RF and mm-wave circuit design. The passive and
integrated circuit prototypes developed in this work to validate this methodology are primarily realized in SiGe-BiCMOS technologies, however, the proposed topologies and design
techniques are also applicable to CMOS processes.
1.1
Motivation
The advancement of a technology is pushed by its useful technical characteristics and pulled
by its potential commercial value and application. This section elaborates the motivation for
the work carried out in this thesis from both of these perspectives.
1.1.1
Multi-gigahertz Wireless Bandwidth
Theoretically, channel capacity increases with increasing channel bandwidth according to
Shannon-Hartley theorem [19]. Therefore, in order to increase throughput and avoid congestion in the ISM bands at 2.4 GHz and 5–6 GHz, wireless communications could migrate to
spectrum allocations offering a wider bandwidth at higher frequencies. The four, 1728 MHz
wide channels defined by the IEEE 802.15.3c standard are highlighted in Fig. 1.1, with the
band from 59–64 GHz available in almost all countries around the world [20] [21]. The E-band
covers 71–76, 81–86 and 92–95 GHz, offering 12.9 GHz of available bandwidth (note that
100 MHz is excluded across 94–94.1 GHz). Government regulatory organizations (e.g., the
FCC in the US, CEPT in Europe and ACMA in Australia) assign the 71–76 and 81–86 GHz
bands for point-to-point wireless communications [22]. The 76–81 GHz band is reserved by
many countries for medium- and long-range automotive radar applications [23] [24].
1.1. Motivation
3
100
200 mm/h
100 mm/h
50 mm/h
20 mm/h
Attenuation, in dB/km
10
5 mm/h
1
0 mm/h
Water vapour
0.1
Oxygen
0.01
0.001
0
20
40
60
80
100
120
Frequency, in GHz
Figure 1.2: Atmospheric attenuation of RF energy vs. frequency [26].
Apart from multi-gigahertz bandwidth and global coverage, operating license fees are also
important considerations for commercialization from cost and market acceptance perspectives. Hence, the unlicensed 60 GHz band and lightly-licensed E band (e.g., $75 for a 10-year
license in the US [25]) are favored in this regard for the next-generation of wireless communications.
1.1.2
Operational Benefits at mm-Wave Frequencies
Atmospheric absorption of radio waves varies significantly with frequency, as shown in
Fig. 1.2 [27]. Compared to the negligible attenuation at 5 GHz (i.e., 0.01 dB/km), signals in the vicinity of 60 and 120 GHz are subject to high oxygen absorption and rain
fade of RF energy, e.g., 12 dB/km across 57–63 GHz. Thus, these bands cannot support
long-distance communications, but are well-suited for short-range, point-to-point networks.
The high energy absorption and the free-space propagation losses due to a small antenna
aperture at mm-wave frequencies (e.g., 88 dB losses at 60 GHz across a 10 m link) isolate
one transceiver from another, providing immunity to interference, thereby relaxing linearity
requirements on the receiver front-end components. It also offers the potential for frequency
reuse over distance using the cellular networking concept.
Despite the decreasing antenna aperture with increasing frequency, the short wavelength
(λ = v/f , where v is the phase speed and f represents frequency) at mm-wave frequencies
permits compact on-chip passive components design (e.g., λ/4 resonators), facilitating the
implementation of fully-integrated transceivers and reducing cost. The phased-array system,
which utilizes multiple antennas and transceivers for beam steering, improves directivity,
4
Chapter 1. Introduction
compensates for high path losses and increases data rates [28]. Through N -element beam
steering, the transmitted and received signal power is increased by 20 · log10 N , while the
received noise level is increased by 10 · log10 N . It leads to an (ideal) improvement on signalto-noise ratio and receiver sensitivity by 10 · log10 N , thereby increasing channel capacity.
The decreasing antenna separation (i.e., proportional to λ [28]) with increasing frequency
and the small form factor at mm-wave frequencies support compact system designs. A 2×2
phased-array system at 60 GHz realizes 5 Gb/s data rate with 8.75 mm2 chip area [29], as
compared to 200 Mb/s and 18 mm2 for its 2.45 GHz multiple-input-multiple-output (MIMO)
counterpart [30]. One of the most challenging tasks for mm-wave phased-array systems is
the low-cost antenna and packaging solutions [31]. The antenna size shrinks with increasing
frequency, encouraging its on-chip realization [32]. However, it significantly increases chip
area with the number of array cells and may suffer from low gain and radiation efficiency [31].
Alternatively, the antennas could be embedded into a package at the expense of packaging
complexity (e.g., low-loss interconnection between chip and antenna) [31].
1.1.3
mm-Wave Standardization and Applications
Point-to-point, multi-Gb/s wireless communications over a short range (< 10 m) is the
targeted application for the license-free 60 GHz-band spectrum. SiBEAM (Silicon Image’s
subsidiary) has demonstrated a 32-element, 60 GHz phased-array system capable of 6–7 Gb/s
non-line of sight communication across a 10 m range [33]. The IEEE 802.15.3c task group
standardizes mm-wave radio for high-data-rate wireless personal-area networks (WPANs)
[34]. The European computer manufacturers association (ECMA) TC–48 standard works
towards using the 60 GHz band for bulk data and multimedia streaming applications [35].
The WirelessHD consortium is also promoting 60 GHz technology for high-speed, highquality, uncompressed audio/video streaming [36]. Several Wi-Fi chip makers, such as Intel,
Broadcom and Qualcomm-Atheros have established the wireless gigabit alliance (WiGig) in
order to supplement Wi-Fi networks at 2.4 GHz and 5 GHz with 60 GHz communications in
data networking (i.e., tri-band WiFi) [37]. In early 2013, Qualcomm-Atheros and Wilocity, a
leading developer of 60 GHz multi-gigabit wireless chipsets, launched industry’s first tri-band
WiFi reference design at the International Consumer Electronics Show (CES).
Unlike 60 GHz, the E-band across 70–100 GHz is capable of offering Gb/s transmission rates
over a much longer distance, because there is a transmission window where the attenuation
is below 1 dB/km (see Fig. 1.2). It is thus well-suited for wireless backhaul in urban and
residential areas across a few kilometers, such as for enterprise/campus LAN connectivity.
GigaBeam’s WiFiber radio [38] is one of the commercial products which utilize the E-band
for wireless backhaul. Potential applications also include: disaster recovery, fast access to
patient data in hospitals, and backup solution for wired networks, etc. For example, when
the service within metro access networks is unavailable due to natural disasters or other
disturbances, the wireless bridge could restore connections easily and quickly.
Fig. 1.3 shows a typical example of mm-wave wireless applications. In the outdoor environment, communications over the 70/80 GHz band provide the backhaul required to extend
1.1. Motivation
5
Figure 1.3: Application example of mm-wave wireless communications [39].
Figure 1.4: Bosch’s LRR-3 third generation long-range radar sensor [40].
the existing network without the need for wired or optical infrastructure, for example, the
1.5 Gbps link for building-to-building connectivity. On a smaller scale, the 60 GHz radio improves the indoor entertainment quality, where scenarios like uncompressed high definition
video streaming, wireless gaming, and wireless gigabit Ethernet may become feasible.
Automotive radar in the 77/79 GHz band is a major application of the mm-wave technology
[41] [42]. The increasing awareness of road safety has made automotive radar commonplace
in modern vehicles. Several companies, including Infineon Technologies [43] and Freescale
Semiconductor [44] supply silicon-based automotive radar chipsets at 77 GHz to the mar-
6
Chapter 1. Introduction
Figure 1.5: A fiber-to-the-x network [50].
ket. Systems such as adaptive cruise control, collision warning, blind-spot detection, and
automatic steering and braking intervention employ radar sensing at mm-wave frequencies.
Bosch’s third generation LRR radar (LRR3) is the world’s first 77 GHz radar sensor utilizing
SiGe technology, which has a box size of only 77 × 74 × 58 mm3 as shown in Fig. 1.4 [45].
1.1.4
Advantages of Optical Fiber Communications
Although advanced mm-wave radio systems can provide wireless ‘fiber-like’ connectivity
over a few kilometers, the performance depends on weather conditions (see Fig. 1.2). Thus,
optical fiber connectivity is better-suited for long-haul and all-weather communications.
Wavelength-division multiplexing (WDM) [46] combines different wavelengths of light onto
a single optical fiber. It thus allows optical network expansion without the need for more
fiber cables, giving it flexibility and scalability. The aggregate data throughout on a singlemode fiber could reach 100 Tb/s using multi-level multi-dimensional modulation formats
and advanced transmitters, e.g., the polarization-division multiplexed quadrature-amplitude
modulation (PDM-QAM) [47] in digital transmitters using orthogonal frequency-division
multiplexed (OFDM) signals [48]. The transmission rates are anticipated to be easily above
100 Tb/s when space division multiplexing (SDM) and multi-mode multi-core fibers are
utilized [49], which is beyond the capability of other technologies.
Unlike electrical transmission, the dielectric property of optical fiber offers several unique advantages. It presents low fiber-to-fiber crosstalk and is less susceptible to security problems.
The light weight and small size simplifies upgrading of infrastructure because no additional
space is demanded when optical fibers replace copper cables. It is also immune to electromagnetic interference, adverse temperature and moisture conditions, which is beneficial for
applications in hazardous environments (e.g., undersea and explosive areas).
Also, it is considered best for backbone/core networks in metropolitan areas (where it interconnects a number of local-area networks, see Fig. 1.6) because of its superior reliability,
security and capacity. Another emerging application is the fiber-to-the-x (FTTX) networks,
such as fiber-to-the-home (FTTH) and fiber-to-the-building (FTTB) as shown in Fig. 1.5,
1.2. Research Topics and Design Challenges
7
Figure 1.6: A hybrid optical-wireless network [12].
driven by consumer desire for quality of service and increasing speed beyond what wireless
networks can offer.
Optical fiber links potentially can be used in the same application areas as mm-wave wireless
technology, but it is not a substitute for the latter because it is not as flexible. Moreover, in
places where the initial infrastructure is not equipped with optical fiber, its application is
hindered due to the high cost in fiber installation. Thus, the hybrid optical-wireless network
shown in Fig. 1.6 becomes a promising solution. The feeding network uses optical fiber,
e.g., the connections between a central office (CO) and a remote node (RN), and between
a remote node and a base-station (BS), while the edge network from BS to customer units
uses (mm-wave) wireless connections. This combination utilizes the speed and reliability
advantages of optical fiber in the network core and the flexibility of wireless communications
for ‘last mile’ connections.
1.2
Research Topics and Design Challenges
Integrated transceivers with sufficient link margin are required in order to utilize each technology to its full capacity and ensure reliable communications. This section analyzes the
technical bottlenecks in the mm-wave electrical and Gb/s optical transmit chains, and defines the research topics in this work. The design challenges arising from technology scaling
are described in detail.
1.2.1
Electrical Transmitter and RF Power Output
Fig. 1.7 shows the simplified block diagram of a wireless broadband transceiver. The heterodyne receiver avoids flicker noise at baseband, and double downconversion with a properly
8
Chapter 1. Introduction
a) Electrical transmitter
b) Electrical receiver
Figure 1.7: Simplified block diagram of a wireless broadband transceiver.
selected intermediate frequency offers sufficient image-rejection and adjacent channel suppression [51]. On the transmit side, a power amplifier is required for RF signal amplification
in order to increase the range and margin of the communication link. The PA must deliver
sufficient RF power to the antenna (i.e., a large voltage swing across 50 Ω) with gain adequate to relax transmit driver requirements and high efficiency in order to reduce power
consumption. In addition, the targeted mm-wave applications require the PA to operate
across a few gigahertz bandwidth (e.g., 57–64 GHz).
It is observed that the RF output power and efficiency achievable on chip decreases with
increasing frequency [52]. Silicon monolithic PAs rarely deliver more than 15 dBm and 15%
power-added efficiency (PAE) from a single amplifier cell in the mm-wave bands [53] [54] [55].
For example, a SiGe-BiCMOS, 60 GHz-band PA produces 13.5 dBm saturated output power
and 9.8% peak-PAE from a 3.3 V supply voltage at 58 GHz [53]. Moreover, inadequate RF
power output at mm-wave frequencies complicates antenna and system design [56], as a larger
number of antenna and transceiver elements is often used to increase gain, which increases the
cost, complexity and DC power consumption, and could also affect bandwidth. For example,
commercial gigabit links at 60 GHz, such as the CMOS transceivers developed by SiBEAM
[33] and Intel [57], employ 32-element array antennas and beamforming to overcome high
path losses. The influences from technology scaling and the technical difficulties in realizing
high-performance mm-wave PAs are elaborated in Section 1.2.3 and Section 2.1 of Chapter
2.
1.2. Research Topics and Design Challenges
9
a) Optical transmitter using external modulation
b) Optical receiver
Figure 1.8: Simplified block diagram of an optical transceiver.
Therefore, mm-wave PAs with RF power output greater than 15 dBm are needed in order
to reduce the number of antenna cells required in a phased array from the complexity and
fabrication cost perspective. However, the targeted level of RF power output corresponds
to a voltage swing of 6.3 Vp−p across the 50 Ω load (i.e., 20 dBm power output), which
far exceeds the breakdown constraint of transistors in high-performance silicon technology.
For example, the open-base collector-emitter breakdown voltage of a HBT (i.e., BVCEO ) is
smaller than 1.6 V for 130 nm SiGe-BiCMOS in [17]).
1.2.2
Optical Transmitter and MZ Modulator Driver
The equivalent of Fig. 1.7 in the optical domain is shown in Fig. 1.8. An optical fiber
transmitter converts an electrical input to an optical signal and launches it into the fiber.
On the receive side, optical-to-electrical conversion is realized by a photodetector for further
signal processing and data recovery. Laser diodes with external modulation are typically
used as the optical source for high-capacity and long-span transmission systems [58].
The optical intensity of the semiconductor laser can be modulated internally, however, direct
(i.e., internal) modulation via the bias current causes frequency chirp (i.e., output frequency
10
Chapter 1. Introduction
varies with time) and phase modulation [59]. These impairments are mitigated by external modulation, where the laser diode is biased to produce a continuous wave output (i.e.,
unmodulated) [59] [60]. Among external optical modulators, the Mach-Zehnder (MZ) interferometer and electroabsorption (EA) modulators are the most commonly used in practice.
The MZ modulator has advantages over the latter in terms of broader optical bandwidth
and zero or tunable frequency chirp [61]. However, the traveling-wave MZ modulator, which
changes the phase of light by applying electric field, requires a large switching voltage, Vπ
(e.g., 5.1 V [62]), from the driver stage. The switching voltage Vπ is the half-wave voltage
required to induce a phase change of 180◦ .
On-off keying modulation formats (e.g., non-return-to-zero and return-to-zero) have been
used historically in optical communication systems. As the data rate increases, a more efficient modulation format such as quadrature phase-shift keying (QPSK) is preferred because
it transmits more bits per symbol. Differential QPSK (DQPSK) can tolerate noise or distortion owing to chromatic dispersion or polarized mode dispersion [63], and thus it is favored
for high-data-rate optical communications. In order to generate DQPSK modulation, both
the I and Q arms of the modulator need a differential modulator driver with a balanced output. The driver circuit must also be broadband in order to preserve signal fidelity, e.g., the
minimum required bandwidth is approximately 7.5 GHz for a 10 Gb/s system using on-off
keying modulation [59]. Thus, in order to encode the optical carrier reliably, a broadband,
balanced MZ modulator driver with a differential output voltage swing of at last Vπ needs
to be developed.
1.2.3
Influences from Technology Scaling
Although the application and system architecture are different, it is recognized in Sections
1.2.1 and 1.2.2 that both the electrical and optical transmitters demand the development
of a PA circuit and a MZ modulator driver capable of broadband operation and delivering
a wide output voltage swing in order to ensure communication quality. Silicon technology
scaling increases gain-bandwidth product, however, the concomitant trade-offs also penalize
circuit performance, imposing a number of technical difficulties for mm-wave and broadband
IC implementations. Wideband mm-wave PAs delivering greater than 20 dBm output power
are realized exclusively in compound semiconductor technologies such as InP, e.g., 26.1 dBm
in the W band from [64]. Also, the previously reported and commercial MZ modulator drivers
are typically implemented in III–V compound technologies with ≥ 5 V breakdown to provide
6 Vp−p or larger output (e.g., GaAs-InP in [65] [66]). Lower-cost implementations in silicon
remain a challenge.
Therefore, innovations in system architecture, RF circuit design, on-chip passive components
and low-cost packaging are required. This research focuses on the design of silicon-based PA
and MZ modulator driver realizations which offer performance comparable to their III–V
counterparts. Several relevant influences from process scaling are analyzed as follows.
1.2. Research Topics and Design Challenges
A.
11
Reduced Breakdown Voltage
Millimeter-wave circuits built in advanced silicon technologies can exploit the increasing fT
from device scaling, but the maximum tolerable voltage across the device terminals decreases
with scaled dimensions. Johnson’s limit (i.e., fT ·BVCEO = constant [67], where fT is transistor cut-off frequency) imposes a trade-off between bipolar device speed and breakdown
voltage, e.g., BVCEO < 1.6 V biased at peak-fT of 240 GHz in 130 nm SiGe-BiCMOS [17].
The gate oxide breakdown voltage of a MOSFET also decreases to well below 2 V as the
SiO2 layer thickness becomes 2 nm or less [68]. The supply voltage (limited by breakdown)
partly determines the RF output power from a PA circuit. Similarly, breakdown voltage also
constrains the maximum output voltage swing available to drive a MZ optical modulator.
The PA and MZ driver prototypes in this work are implemented in SiGe-BiCMOS technologies, thus an investigation of the proper device configuration in a circuit is needed in order to
exceed the BVCEO boundary. It is proven that grounding the base terminal of a BJT shunts
the impact ionization current to ground, thereby extending the device safe operating range
[69] [70]. For example, simulation predicts that a common-base topology (CB) can increase
the breakdown limit from 1.6 V to 2.6 V and thus boost the RF power output by roughly
4 dB from a 130 nm SiGe-BiCMOS technology. Thus, the CB configuration is exploited in
the circuit prototypes developed in this work for greater RF power and voltage swing (see
Chapters 4–6).
B.
Reduced Power Gain with Frequency
The decreased maximum available or stable gain (MAG or MSG) with increasing frequency
penalizes PA efficiency (e.g., ∼ 10 dB at 60 GHz vs. > 20 dB at 10 GHz in 130 nm SiGeBiCMOS). Power-added efficiency (PAE) is defined as
P AE =
Pout − Pin
1 Pout
= (1 −
)
,
PDC
Gp PDC
(1.1)
where Gp is the PA power gain, Pin and Pout are the power fed to the PA input and delivered to the load impedance (typically a 50 Ω antenna), respectively, and PDC is the DC
power consumption for a given Pout . More power gain could be realized by cascading several
amplifier stages, but this comes at the expense of higher DC power consumption and complicated interstage coupling networks, which also decreases the overall PAE. This trade-off is
examined in more detail in Chapter 4 of this thesis. A new multi-stage PA topology with the
proper gain distribution is capable of realizing 20 dB overall power gain, while minimizing
the PAE degradation from the driver stages (see Chapters 4 and 5). The PA topology is
demonstrated in two different SiGe-BiCMOS technologies.
A MZ modulator driver with a 6 Vp−p differential output swing and 100 mVp−p input sensitivity must provide 35.6 dB voltage gain when linear amplifiers are used, which requires at
least 3 gain stages in cascade (note that a lower technology node with peak-fT of 60 GHz
is selected for the 10 Gb/s demonstrator for its relatively large breakdown voltage [71], see
Section 1.3.2). However, compared to a single stage, a cascade of N stages decreases the
12
Chapter 1. Introduction
√
operating bandwidth by a factor of 21/N − 1 [72], which is undesirable for broadband optical applications. A limiting amplifier relaxes the bandwidth requirement, and can provide
sufficient gain by scaling up the operating current. Thus, it is exploited in the MZ modulator
driver circuit developed in this work (see Chapter 6).
C.
Stability
Unconditional stability needs to be guaranteed for all ICs developed in this work. It is likely
that the conditionally-stable region extends into the desired operating bands at mm-wave
frequencies due to the decreased output-to-input isolation with frequency, which thus requires
an additional network to stabilize the circuit. Improved stability often comes at the expense
of power gain, voltage swing or power consumption (e.g., using resistive loading [73] or RC
compensation [74]), which is undesirable for a high-performance PA (see Chapter 4). Proper
layout techniques in this work minimize and equalize the parasitics in series with the base
terminals of CB stages and guarantee stability (see Chapter 4).
Thermal stability is another problem in advanced silicon technology and especially in highcurrent applications. The trend towards a larger current density for scaled devices (e.g.,
20 mA/µm2 ) drives up junction temperature in a confined device area due to heat dissipation
limits. Transistors biased near peak-fT are subject to thermal runaway if proper care is not
taken. Base/emitter resistor ballasting can be used in order to promote thermal stability
in a single-stage amplifier at the expense of reduced breakdown voltage or degraded RF
performance if configured single-ended (see Chapter 4). This work explores resistor ballasting
in a differential topology, and examines the use of the cascode configuration for better thermal
behavior (see Chapters 4–6).
D.
Parasitics
On-chip interconnects and the associated wiring parasitics, which may be negligible at lower
frequencies, become critical at higher frequencies. For example, a 30 µm long interconnect
introduces roughly 30 pH inductance, which is j11.3 Ω at 60 GHz but just j0.19 Ω at 1 GHz.
The increased reactance with frequency could cause instability when in series with the base
of a common-base stage, or extra losses if it is in the signal path (e.g., in a common-emitter
configuration). Additionally, interconnections on chip behave like ‘electrically long’ transmission lines in the mm-wave range, and need proper modeling [20]. Over/under-estimating
these parasitics may decrease first-pass silicon success rate (e.g., circuit performance below
specifications). Bondpad and interconnect parasitics, especially inductance, are predicted by
electromigration simulations in the design phase for all of the circuit demonstrators.
E.
On-chip Passive Components
Passive components such as monolithic transformers and transmission lines are widely used
on chip to perform impedance matching and interstage coupling at mm-wave frequencies
[75] [76]. Compact passive dimensions are possible because of the shrinking wavelength
1.3. Passive-aided Amplifier Design Objectives
13
with increasing frequency. Also, the inductance (L) required to resonate out a fixed capacitance (C) scales down in proportional to the square of the operating frequency, f0 (i.e.,
√
L = 1/(2πf0 C)2 ), saving valuable chip area. Moreover, dedicated mm-wave technologies
further facilitate passive developments by offering thick metal options and increased dielectric thickness between the substrate and top interconnect metal layers for reduced energy
coupling to the substrate [17].
Therefore, it is anticipated that the above-mentioned limitations of active devices in deep
submicron silicon technologies could be mitigated or overcome by integrating high-quality
passive components and manipulating them in unique circuit topologies. Thus, this thesis
aims to demonstrate state-of-the-art, silicon-based, mm-wave PA and DA-based optical MZ
modulator driver by developing novel passive components on chip for this application.
Despite the fact that a CB configuration extends breakdown voltage for the chosen circuit
demonstrators as described above, their design approach and emphasis still differ. The mmwave PA prototypes are developed in 130 nm and 90 nm SiGe-BiCMOS technologies, where
the > 200 GHz gain bandwidth product has the potential to meet the band-pass, 5–13 GHz
bandwidth requirement. However, the RF power output from a single-stage is constrained
by the low supply/breakdown voltage, compared to older technology nodes (e.g., a 250 nm
process). Thus, passive power combining is exploited in the mm-wave PA design in order to
boost the output power without compromising the efficiency and bandwidth significantly.
By contrast, the frequency response of the MZ modulator driver needs to be predominantly
low-pass with a passband ranging from a few tens of kilohertz to multi-gigahertz. A proper
selection of silicon technology and the utilization of a CB configuration could meet the
output voltage swing requirement for the multi-Gb/s MZ modulator driver. However, the
parasitic capacitance from large-area devices capable of carrying high currents again limits
the bandwidth and maximum data rate [77], although the limiting amplifier operation relaxes bandwidth requirement. A traveling-wave distributed amplifier (DA) topology, which
allows serial signal combining using passive, artificial transmission lines, has bandwidth advantages over conventional lumped amplifier topologies [78] [79]. Thus, it is employed in the
MZ modulator driver circuit for broadband operation and amplification. However, several
disadvantages of the conventional DA topology compromises performance and constrain its
design flexibility (Section 1.3.2 and Chapter 6 elaborate on this subject). A new, digitallycontrolled MZ modulator driver circuit is developed in this work in order to mitigate the
performance impairments in conventional DAs (see Chapter 6).
1.3
Passive-aided Amplifier Design Objectives
This section introduces the output-combining, mm-wave PA and the distributed amplifier
based MZ modulator driver circuit topologies which are capable of achieving improved performance with the aid of passive components. The specific design difficulties in each topology
are analyzed separately, and their design objectives are defined.
14
1.3.1
Chapter 1. Introduction
mm-Wave Output-combining Power Amplifier
In principle, greater power in a PA may be generated by simply increasing the transistor
area and DC bias current of the final stage for a given output voltage swing. However, RF
power output tends to saturate, or even drop, because the optimal load impedance decreases
to the point where losses in the output matching network become larger than any increase
in output power (i.e., on the order of 2–3 Ω).
A review of the recent literature reveals that on-chip output combining using a passive
power combiner is an effective method to increase the RF power [52] [80] [81]. However, the
published output-combining PAs at mm-wave frequencies do not reach high power output and
high efficiency simultaneously (note that the maximum saturated output power and peakPAE at 60 GHz of the published PA designs can hardly reach 20 dBm and 20%, respectively
[52]). Losses from the output combiner itself directly decrease the power level and thus the
PA efficiency. For example, assuming a single PA cell with 14 dBm output power, 20% peakPAE and sufficient power gain, the total output power from a 4-way combining is 19 dBm
and peak-PAE is 14.9% when the combiner loss is 1 dB. The output power drops to 18 dBm
and PAE to 12.6% when the combiner has 2 dB loss.
Thus, one objective in this part of the work is to investigate and design low-loss and compact
passive power combiners on silicon (e.g., SiGe-BiCMOS and CMOS-SOI). The other objective is to develop a monolithic, power-combining, mm-wave PA topology capable of realizing
both high output power and efficiency simultaneously. The PA prototypes target 20 dBm
output power, larger than 15% peak-PAE and 20 dB power gain in band.
1.3.2
Silicon-based Distributed Amplifier Optical Modulator Driver
A distributed amplifier (DA) incorporates synthetic transmission lines in order to extend
its operating bandwidth. A simplified circuit model of the conventional DA is illustrated in
Fig. 1.9, where a pair of transmission lines is used to series connect several (unilateral, e.g.,
cascode) amplifier stages represented by the transconductance stages, Gm . The capacitive
parasitics (i.e., Cin and Cout ) which limit DA bandwidth are absorbed in the transmission
line design. Note that the Miller effect in an actual amplifier topology is accounted for in the
lumped capacitance calculation. Dissipation at the input (e.g., rgg for a FET, or rbb′ and re
of an HBT) is modeled by rin , while rout represents the output resistance of the Gm stage.
The outputs of individual stages are added constructively when the delay between input and
output lines are matched properly. Termination resistors ZT 1 and ZT 2 minimize unwanted
reflections from the transmission lines, and the amplifier stages are biased via resistor ZT 2 .
A survey of the recent published designs reveals that conventional DAs have been the dominant realization of the MZ modulator driver circuit [66] [65] [82]. However, the precise analog
matching required between the passive input and output transmission lines for the correct
signal phases constrains its design flexibility. The bandwidth of the driver circuit is also limited by the input transmission line and the capacitive parasitics from the back termination
resistors. The cut-off frequency of the input line, which is inversely proportional to the square
1.3. Passive-aided Amplifier Design Objectives
15
Figure 1.9: Simplified circuit model of a conventional distributed amplifier.
root of its equivalent shunt capacitance, is significantly decreased when loaded by the parasitic capacitance from the amplifier stages [78]. The 50 Ω impedance matching required for
the loaded input and output lines may translate to an unloaded line characteristic impedance
above 150 Ω, which is nearly impossible to realize in modern (Bi)CMOS technologies due
to the thin dielectric and back-end-of-line (BEOL) stack thicknesses, especially when a substrate shield is applied to reduce energy coupling to the conductive substrate. Moreover,
losses from the input line attenuate signal, cause dispersion, and limit the maximum number
of DA gain stages as well [78]. The back termination resistor capable of conducting all the
DC and AC currents often presents considerable capacitive parasitics (e.g., > 150 fF for
0.5 W power dissipation), and is typically excluded from on-chip integration [83].
Thus, the performance impairments inherent in the conventional DAs, which are analyzed
in detail in Chapter 6, require innovations at the system level in order to mitigate them,
e.g., eliminating the need for a second transmission line at the input to provide the matched
signal delay required by the output line. Therefore, the primary objective in this part of
the work is to explore different circuit architectures, propose a new power resistor design
for on-chip termination, and develop a monolithic SiGe-BiCMOS Mach-Zehnder modulator
driver circuit capable of achieving both high gain (i.e., > 20 dB, low input sensitivity) and
high output swing (i.e., differential 6 Vp−p ) over a wide bandwidth (i.e., > 7 GHz for 10 Gb/s
speed). The IBM’s 180 nm 7WL SiGe-BiCMOS process offers BVCEO of 3.3 V, thick metal
option and thick BEOL metal stack, and thus is chosen to implement the MZ modulator
driver demonstrator circuit [71].
It is generally advantageous to maximize the capacity per channel in order to reduce the
number of channels or transfer more data. However, it leads to more stringent bandwidth
requirement on optical and electronic devices and needs better optical fiber to suppress
chromatic dispersion effects [84]. As pointed out in Section 1.1.4, wavelength division multiplexing technology can overcome these problems and increase the overall data rates. It
can also lengthen the lifetime of existing service infrastructure (e.g., 10 Gb/s [85] [86]). The
targeted communication rate in this part of the work is 9.9–12.5 Gb/s. The driver demonstrator topology is expected to offer scalability to provide a wider output voltage swing (e.g.,
≥ 10 Vp−p differentially) and extend the number of communication channels when needed.
16
Chapter 1. Introduction
The proof-of-concept demonstrator is also expected to be frequency scalable, capable of
migrating to 40 Gb/s or higher when more aggregate capacity is needed.
1.4
Organization of this Thesis
Chapter 2 begins with the analysis of multi-dimensional trade-offs in a PA design. The
influences from different biasing modes (i.e., class-A, B, AB, C, etc.) on PA performance are
also discussed and compared. It concludes that a power-combining amplifier is necessary to
overcome the difficulties highlighted in Section 1.2. A review of the mm-wave PA circuits
and on-chip power combiners published in the recent literature is conducted. The problems
associated with on-chip transformer combiners are identified and explained.
Chapter 3 describes design details and characterization of the two classes of mm-wave combiners/splitters developed in STM’s 130 nm SiGe-BiCMOS and 65 nm CMOS-SOI technologies. The frequency-scalable transformer combiners in SiGe-BiCMOS successfully suppress
port impedance imbalance caused by parasitic interwinding capacitance. Coplanar waveguides (CPWs) and slow-wave propagation created by adding a floating shield underneath
CPW conductors are exploited in the 65 nm CMOS-SOI technology for wavelength reduction. A compact, low-loss, 2-way slow-wave CPW (S-CPW) combiner is fully characterized
and discussed in detail.
Chapter 4 presents the multi-stage, multi-path, power-combining, mm-wave PA architecture
developed in this work. The first half of the chapter emphasizes the active circuit design, in
which several single-stage amplifier topologies are compared. Performance limitations in a
single PA gain stage are recognized and addressed individually. These include: overcoming
the breakdown voltage constraint, promoting unconditional stability without gain or power
consumption penalties, and parasitic reduction. These active and passive circuit technologies
are applied to several PA prototypes, which include: one SiGe-BiCMOS PA and one CMOSSOI PA in the 60 GHz band, and a scaled-up SiGe-BiCMOS PA operating in the 77/79 GHz
band. The possibility of using alternative gain topologies and power combiner layouts is also
studied in IBM’s newly developed 90 nm SiGe-BiCMOS technology [87].
Chapter 5 addresses the large-signal PA measurement topic and reports the prototype experimental results. The prototypes are fully characterized across a wide frequency range and
different supply voltages. A comparison of performance with designs published in the recent
literature is also provided.
Chapter 6 presents the implementation and characterization of a distributed amplifier based
Mach-Zehnder modulator driver in IBM’s 180 nm 7WL SiGe-BiCMOS technology. It starts
with a detailed explanation of the drawbacks inherent in conventional DAs. The operating
principle of the proposed fully-digital driver architecture, which uses digital latches to replace
the passive input transmission line, is described in detail. The required signal delay at DA
output is provided by the variable-phase retiming clocks for the digital latches. A full-custom,
n+/n-well power resistor with low capacitive parasitics is developed to handle hundreds of
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17
milliwatt power. Design considerations for the quadrature clock generation, limiting amplifier
DA gain stage, output transmission line and termination resistor are described in detail.
A summary of the major research contributions in this work and a few recommendations for
future work compose Chapter 7 and complete this dissertation.
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(80×10.664 Gbit/s) WDM transmission over 5200 km of fibre employing 100 km dispersion-managed
spans,” Electronics Letters, vol. 37, no. 24, pp. 1467–1469, Nov. 2001.
[86] C. L. Schow, F. E. Doany, C. Chen, A. V. Rylyakov, C. W. Baks, and D. M. K. et al., “Low-power
16×10 Gb/s bi-directional single chip CMOS optical transceivers operating at < 5 mw/gb/s/link,” IEEE
Journal of Solid-State Circuits, vol. 44, no. 1, pp. 301–313, Jan. 2009.
[87] N. E. Lourenco, R. L. Schmid, K. A. Moen, S. D. Phillips, T. D. England, J. D. Cressler, J. Pekarik,
J. Adkisson, R. Camillo-Castillo, P. Cheng, J. E. Monaghan, P. Gray, D. Harame, M. Khater, Q. Liu,
A. Vallett, B. Zetterlund, V. Jain, and V. Kaushal, “Total dose and transient response of SiGe HBTs
from a new 4th-generation, 90 nm SiGe BiCMOS technology,” in Proc. of IEEE-REDM, Jul. 2012, pp.
1–5.
22
Chapter 1. Introduction
Chapter 2
Literature Survey of mm-Wave Power Amplifiers
Chapter 1 identifies the silicon-based power amplifier as the most challenging building block
to design and implement in a millimeter-wave transceiver. Output power, efficiency and
reliability may be the most important aspects of a PA design. However, when targeting mmwave applications, the performance compromises from technology scaling and the complex
modulation schemes employed to realize high data rates (e.g., 16QAM OFDM) complicate
the design scenario. Thus, a successful and robust PA design requires a multi-dimensional
balance of various parameters [1]. For example, power gain, knee voltage, on-chip matching
networks and transistor bias modes (e.g., class-A or AB) all affect PA power-added efficiency.
This chapter begins with an overview of the basic background knowledge of power amplifiers.
It approaches mm-wave PA design from operation classes, the power gain and efficiency
trade-off, impedance matching and reliability perspectives. It is followed by a survey of
the previously published mm-wave PAs, which ranges from single-cell to multi-path, powercombining topologies. Section 2.3 is dedicated to on-chip passive power combiners, but the
overview and conclusions also apply to interstage matching networks on chip. STM’s 130 nm
SiGe-BiCMOS technology with high-performance HBT fT /fmax of 240/270 GHz is used for
the study in this chapter [2].
2.1
Millimeter-wave Power Amplifiers
A power amplifier, as the name suggests, is used to increase the signal power fed to the
transmit antenna. Its large-signal characteristics distinguish it from small-signal amplifiers,
such as the low-noise amplifier (LNA) on the receive side. Therefore, both small- and largesignal parameters are needed in order to fully characterize and evaluate a PA.
2.1.1
Basics of Power Amplifiers
Small-signal performance of a PA is characterized using S-parameters. The PA is viewed as
a 2-port network, where for example, its input is port 1 and output is port 2. Power gain
(Gp , which equals |S21 | when input and output impedances are both matched to system
impedance, e.g., 50 Ω), input and output return losses (i.e., |S11 | and |S22 |), reverse isolation
(i.e., |S12 |), -3 dB bandwidth (BW−3dB ), stability factors (k and |∆|, or µ) and DC power
23
24
Chapter 2. Literature Survey of mm-Wave Power Amplifiers
consumption (PDC ) are parameters used to specify performance. The large-signal parameters include: saturated output power (PSAT ), -1 dB compression point (P−1dB ), power gain,
power-added efficiency (PAE), drain/collector efficiency (η), and input and output thirdorder intercept points (IIP3 and OIP3 ). Chip area, as an indicator of fabrication cost, is
another important design constraint.
PA small- and large-signal behaviors are not independent of each other. Understanding their
co-relation and interplay is important. For example, a large power gain (Gp ) decreases PAE
degradation from the PA input power, which is proportional to 1/Gp as seen in Eq. 1.1.
At low input power levels, Gp equals the small-signal gain, but the PA starts to compress
when driven large-signal. Thus, the input port is typically impedance matched to 50 Ω (i.e.,
|S11 | > 10 dB) in order to avoid power gain reduction from signal reflection. Power gain also
relaxes the transmit PA driver design because its output power required (i.e., the PA input
driving power) is reduced.
A transistor should drive the optimal load impedance required to deliver maximum power,
Ropt , which can be determined approximately from the I-V characteristics through a load-line
analysis [3] or from load-pull simulations. Setting Ropt as the load (i.e., max. power matching)
is the condition to generate the highest RF power because the output voltage and current
swings are maximized simultaneously. It is different from small-signal conjugate matching,
since a real transistor is subject to voltage breakdown. When conjugately matched, its voltage
limit is reached before the maximum current is applied, leading to a lower saturated output
power. Typically, a conjugate match yields a P−1dB about 2 dB lower than that obtained
from power matching [3]. Hence, the PA output port targets large-signal, load-line matching
instead of small-signal, conjugate impedance matching.
Unconditional stability needs to be guaranteed for a PA. At mm-wave frequencies, the
regime of conditional stability may extend well beyond the desired operating frequency
range. Fig. 2.1 plots the maximum available/stable gain (MAG/MSG) of common-emitter
(CE) and common-base (CB) stages. The 0.27×20 µm2 HBT is biased near peak-fT . The
CE stage is conditionally stable up to 50 GHz, however, the CB stage is unconditionally
stable above 150 GHz (from simulation). The difference primarily arises from the series base
resistance because it attenuates signal in the CE topology, but causes oscillation due to the
emitter gyration effect in the CB configuration. The combination of stability factors k (Rollett stability factor [4]) and ∆ (or B1 ), or a single parameter µ (Edwards-Sinsky stability
factor [5]) is typically used to evaluate stability, as defined in the following 4 equations (Eqs.
2.1–2.4),
k=
1 − |S11 |2 − |S22 |2 + |∆|2
2 · |S12 S21 |
(2.1)
∆ = S11 S22 − S12 S21
(2.2)
2.1. Millimeter-wave Power Amplifiers
25
25
CE
MAG / MSG, in dB
15
10
CB
MSG
20
MAG
13.5 dB (CB)
MSG
MAG
12.4 dB (CE)
5
0
10
20
30
40
60
80
100
200
Frequency, in GHz
Figure 2.1: Maximum stable/available gain of a CE and CB stage.
B1 = 1 + |S11 |2 − |S22 |2 − |∆|2
µ=
1 − |S11 |2
.
∗
|S22 − S11
∆| + |S21 S12 |
(2.3)
(2.4)
The necessary and sufficient conditions for a 2-port network to be unconditionally stable are
k > 1 and |∆| < 1 (or B1 > 0), or µ > 1. Different from k factor, µ represents the distance
from the center of the Smith Chart to the nearest point of instability, thus it gives insight
into how stable a circuit is. Good reverse isolation (i.e., decreasing S12 ) promotes stability
because it is the output-to-input positive feedback that is the primary cause of oscillation.
High isolation is also desired in order to tolerate antenna mismatch. It is worth pointing
out that S-parameters define small-signal behavior, therefore directly observing the output
spectrum using a spectrum analyzer under large-signal operation is a more straightforward
way to measure or observe stability experimentally.
2.1.2
Bias Classes
Different quiescent biasing schemes categorize PAs into class-A, AB, B and C modes of
operation. The modes differ in the current conduction angle, α. For example, the conduction
angle is π < α < 2π for a class-AB biased PA, while 0 < α < π for a class-C biased design.
Other PA operation classes are the switching-modes, namely, classes D, E and F. However,
the lack of fast switching devices in silicon at mm-wave frequencies prevents their application.
Despite being highly efficient, switching PAs are also strongly nonlinear [3]. Thus, they
26
Chapter 2. Literature Survey of mm-Wave Power Amplifiers
100
P
90
0
80
G
-6
m
-12
70
-18
Class AB
-24
60
Collector efficiency, in %
out
6
m
Output power, in dBm, and G , in dB
12
Class C
Class A
Class B
50
-30
2.0
1.5
1.0
Conduction angle,
0.5
0.0
, in radians
Figure 2.2: Pout , collector efficiency and Gm as a function of conduction angle.
are better suited to constant-envelope modulation signals, such as GSM. Modern wireless
communications employ spectrally efficient and higher data rate modulation formats, such
as 64QAM in OFDM, which leads to a peak-to-average power ratio (PAR) of 8–10 dB for
the transmit signal [6]. Thus, it requires highly-linear PAs to avoid generating out-of-band
signals due to distortion [7]. PA linearization techniques (e.g., feedback and predistortion
[8] [9] [10]), which are stable and do not suffer from amplitude/phase mismatches from the
extra circuitry across a broad bandwidth, are difficult to realize in the mm-wave bands [3].
For example, negative feedback decreases intermodulation components at the expense of
power gain, which is already scarce at 60 GHz and above (see Fig. 2.1). Digital adaptive
predistortion demonstrated great improvement in PA linearity (e.g., adjacent channel power
ratio of -58 dBc at 2.5 MHz for WCDMA [8]), but might be too slow for the multi-carrier
scenarios at mm-wave frequencies, and consumes extra power [11]. Therefore, this section
compares the performance trade-offs in the more linear class-A, AB, B and C biased PAs.
Pout
η=
Gm =
1
=
8π
!
α − sin α
Vmax Imax
1 − cos(α/2)
Pout
1
α − sin α
= ·
PDC
2 2 sin(α/2) − α cos(α/2)
1 2 sin(α/2)) − α cos(α/2) Imax
Iaverage
=
·
·
VT
2π
1 − cos(α/2)
VT
(2.5)
(2.6)
(2.7)
Equations 2.5–2.7 define the output power (Pout ), collector efficiency (η) and large-signal (effective) transconductance (Gm ) of class A/AB/B/C biased amplifiers under power matching
2.1. Millimeter-wave Power Amplifiers
27
0.27x20 µm2, CB, V = 1.5 V, I
cc
20
= 26 mA
DC, class A
P
(Class A)
out
G (Class A)
10
Gp (Class B)
0
P
−10
out
(Class B)
P
out
p
, in dBm, and G , in dB
p
−20
−10
−5
0
5
10
15
Input power, in dBm
a) Output power and power gain
0.27x20 µm2, CB, V = 1.5 V, I
cc
PAE and collector efficiency, in %
70
DC, class A
= 26 mA
Collector efficiency (Class B)
50
Collector efficiency (Class A)
30
PAE (Class A)
10
−10
−10
PAE (Class B)
−5
0
5
10
15
Input power, in dBm
b) Collector efficiency and PAE
Figure 2.3: Performance comparison of class-A and class-B biased CB amplifiers from simulation.
(i.e., Ropt = Vmax / Imax ) and when driven into saturation [3], where VT is the BJT thermal
voltage (i.e., 26 mV at room temperature), and Vmax and Imax are the maximum output
voltage and current, respectively. Note that the Gm in Eq. 2.7 is different from the quiescent
transconductance. The average current (Iaverage ) under large-signal operation is used in the
calculation of Gm .
28
Chapter 2. Literature Survey of mm-Wave Power Amplifiers
Fig. 2.2 plots the calculated Pout , η and Gm as a function of the current conduction angle,
assuming Vmax = 1.5 V and Imax = 50 mA. It is not straightforward to calculate power gain
accurately without the input power level. Power gain is proportional to transconductance.
Thus, Gm (in dB) is used for the gain comparison. A trade-off exists between Pout , η and
Gm as the conduction angle changes. The output power of class-C biased amplifiers drops
with decreased conduction angle. It is observed that class-A, AB, and B biased amplifiers
deliver almost the same level of maximum output power as expected. The collector efficiency
increases but Gm drops monotonically as the conduction angle decreases. Comparing class-B
to class-A bias, Gm decreases by around 4 dB. At mm-wave frequencies (e.g., 60 GHz), the
MAG/MSG of a single stage is around 13 dB (see Fig. 2.1), so a 4 dB decrease in power gain
degrades PAE, and thus class-B and class-C biases are less favored. Compared to class-B,
the class-AB biased amplifier has better linearity and higher power gain, which is potentially
beneficial for PA overall PAE (e.g., in a multi-stage PA as described in Section 2.1.3).
The comparisons above are verified from simulation. Fig. 2.3a compares the simulated output
power and gain as a function of input power for (slightly) class-AB (VBE = 880 mV and
IDC = 26 mA) and class-B (VBE = 700 mV) biased, single-stage common-base 0.27×20 µm2
HBT amplifiers in 130 nm BiCMOS. The collector efficiency and PAE are plotted in Fig. 2.3b.
Both amplifiers produce the same maximum output power, which agrees with Fig. 2.2. The
class-AB biased amplifier has a small-signal power gain of 12.5 dB (vs. MSG of 13.5 dB
in Fig. 2.1). By comparison, the class-B biased amplifier has a gain below 1 when Pin is
less than -2.5 dBm (which causes the PAE to fall below zero). As expected, the class-B
biased amplifier has higher peak collector efficiency (i.e., 66% vs. 45% for class-AB from
Fig. 2.3b). However, the advantage of class-B bias on PAE is less dramatic because of the
lower power gain, which is reflected in the large difference between its collector efficiency and
PAE observed in Fig. 2.3b. The peak-PAE is 38% at Pin = 3.9 dBm and 42% at Pin = 7.5 dBm
for the class-AB and class-B biased amplifiers, respectively. The approximately 4 dB higher
input driving power required by the class-B amplifier leads to more overall (large-signal)
power consumption in a multi-stage PA from scaling up the driver/gain stages and the
potential need for another stage in order to reduce the input driving power level (which also
complicates interstage matching). The decrease in PAE caused by the driver/gain stages in a
multi-stage PA is also larger due to the 4 dB lower power gain of the class-B biased amplifier,
as described in the next section. Thus, class-A or class-AB biased gain stages are preferred
for linear, efficient mm-wave amplification at present.
2.1.3
Power Gain and Efficiency Trade-off
Battery-powered mm-wave transceivers require the power consumption to be minimal and
the efficiency of the PA to be maximal. Hence, a single-stage PA is preferred if its gain is
sufficient, as more stages consume extra DC power. Fig. 2.1 shows that the MSG of a single
CE stage is almost 25 dB at 10 GHz, which is adequate to reach power gain above 15 dB in
the low-GHz bands assuming losses from matching networks and parasitics are within 10 dB.
However, simulations predict that the MAG of a 0.27×20 µm2 common-emitter HBT biased
near peak-fT at 60 GHz is 12.6 dB in the 130 nm BiCMOS technology used in this work
2.1. Millimeter-wave Power Amplifiers
29
(see Fig. 2.1). As described in section 2.1.1, the large-signal power gain of a single-stage
amplifier designed to deliver maximum power to a load (i.e., load-line matched) is lower
than MAG (i.e., under conjugate matching). For example, the output impedance of the
HBT described above with 50 Ω source impedance in series with the base is 20 Ω in parallel
with a reactance of -j6.7 Ω at 60 GHz, while the real part of the impedance for a load-line
match is around 46 Ω when biased at 26 mA from a 1.5 V supply, assuming that the knee
voltage is 0.3 V. Since power gain decreases when the output is not conjugately matched and
when driven into compression under large-signal operation, a final stage gain in the range
of 7–9 dB (rather than 12.6 dB) can be expected for a single-stage class-A biased amplifier
optimized to produce maximum power at the load. This is consistent with Fig. 2.3a, where
the compressed power gain at peak-PAE for class-AB and class-B biased CB amplifiers is
approximately 8.5 dB and 4.5 dB, respectively.
Moreover, the transistor models only include parasitics from the first interconnect metal
(i.e., metal 1). Biasing at a high current density requires stacking up to thicker metal layers
in the intrinsic device area. The additional parasitics may cause a drop of 15% (or more) in
fT /fmax [12], which leads to a lower power gain. Similarly, parasitics and losses from on-chip
interconnections can decrease the power gain further. The maximum device size (i.e., the
number of parallel-connected HBTs and the unit emitter length) is also limited due to the
deleterious effects from parasitics.
A cascode topology is one alternative to increase power gain [13] [14] and improve reliability
[15] [16] [17], but requires a higher supply voltage than a CE or CB stage (e.g., 4 V in
[14]). For a given supply (e.g., 1.8 V), the voltage drop across the CE transistor in the
cascode also decreases the output voltage swing across the CB transistor, which leads to
a lower collector/drain efficiency, compared to a single-transistor stage. However, its high
power gain is potentially beneficial for PAE, especially in a multi-stage topology (see Eq. 1.1
and the comparison of single-stage amplifier simulations in Chapter 4). Thus, the cascode
configuration could be a viable choice for PA implementations when the voltage headroom
required is available.
Due to the limited MAG available at mm-wave frequencies, a cascade of several single-stage
amplifiers is necessary in order to realize sufficient power gain, and has been the dominant
PA topology in this frequency range [18] [19] [20]. One disadvantage of a multi-stage topology
is the PAE degradation by additional gain stages. Eq. 2.8 defines the PAE of a N -stage PA
P AE =
·


1


 P AEN
·
(GN −1 − 1)
N
Q
i=1
(GN − 1)
N
Q
i=1
NQ
−2
i=1
Gi − 1
NQ
−1
i=1
Gi
Gi − 1
Gi
+ ··· +
+
1
P AEN −1
(2.8)
−1
(G2 − 1)G1
G1 − 1 
1
1

· N
· N

+

Q
Q
P AE2
P AE1
Gi − 1
Gi − 1
i=1
,
i=1
where Gi and PAEi (i = 1, 2, · · · N ) are the power gain and power-added efficiency of each
30
Chapter 2. Literature Survey of mm-Wave Power Amplifiers
Optimal load impedance, R
opt
12.5
5
, in Ohm
2.5
Insertion loss, in dB
4
3
2
1.58 dB
1
0
2
3
10
4
20
50
30
Impedance transformation ratio
a) L-type network
b) Insertion loss
Figure 2.4: Insertion loss of an L-type matching network as a function of impedance transformation ratio.
stage, respectively. When Gi ≫ 1, Eq. 2.8 can be simplified as



P AE ∼
=

−1
1
1
1
1
1 
1
1

+
·
+ ··· +
· N
· N
+


P AEN
P AEN −1 GN
P AE2 Q
P AE1 Q
Gi
Gi
i=3
.
(2.9)
i=2
It is observed from Eq. 2.9 that the effect on PAE from the gain stages (i.e., stages 1 to
N − 1) is suppressed by the product of the power gains from all of the stages following
each individual stage [18]. For example, the first stage contributes less than 10% to the PAE
degradation when the gain of the last two stages is more than 10 dB in a 3-stage class-A
biased PA. Thus, it is important to preserve power gain from each stage for higher efficiency
in a multi-stage PA topology. Higher power gain is also desired in order to relax the RF input
power required. For example, assuming 5 dB gain compression when saturated, a 20 dBm PA
with 20 dB small-signal gain requires less than 5 dBm input power to drive it into saturation.
2.1.4
Impedance Matching at mm-Wave
Losses from the PA output matching network directly decrease the power output and efficiency. However, apart from the quality of the components used in the matching network,
the impedance transformation ratio (m) also affects PA performance. It is the underlying
reason why simply increasing the transistor area and DC bias current does not necessarily
deliver more RF power. The impedance transformation ratio is defined in Eq. 2.10 as the
ratio of the 50 Ω load impedance (RL ) to Ropt .
2.1. Millimeter-wave Power Amplifiers
m=
31
RL
2Pout RL
=
Ropt
VCC 2
(2.10)
For a simple L-type matching network, the insertion loss (IL) is approximately given in
Eq. 2.11 [21], assuming that the capacitor has a much larger Q-factor than the inductor (i.e.,
QC ≫ QL ).
IL = 1 +
√
m−1
QL
(2.11)
Fig. 2.4 plots the IL as a function of m, assuming QL = 10. It is obvious that IL increases
with increasing impedance transformation ratio, which decreases RF power output and PAE.
The increase in IL explains why there is a limit on maximum device size for a given supply
voltage. The shaded area in Fig. 2.4 highlights the usable impedance transformation ratio
range (i.e., m < 5) in practice. An alternative solution for realizing more RF power, which
can also keep the impedance transformation ratio below 5, is thus required to address the
problem. Detailed discussions are covered in Section 2.2.
2.1.5
Reliability
Device breakdown and metal electromigration dominate the reliability of a PA. The latter
can be satisfied by adjusting metal widths and thicknesses. However, the device breakdown
voltage places a ceiling on the RF output power, and pushing the supply limit deteriorates
device reliability. A cascode of FETs (i.e., stacked-FET) connects several transistors in series
in a way that both the DC and RF signals are divided across all of the devices [22], either
via a feedback resistor [23], or a capacitive voltage divider [24], or a monolithic transformer
[25]. It allows an increase in the output impedance and voltage swing, thereby achieving
watt-level output power [26] [27]. It potentially sustains excellent reliability operating from
a supply voltage larger than the transistor drain-source breakdown voltage [28].
However, the required supply voltage is well above the typical allowed value in advanced
silicon technologies (e.g., 6.6 V in [26]). The reliability of the stacked-FET PA depends on
an even RF signal division across all of the series-connected transistors because the PA fails
if one of the devices is destroyed. By contrast, the performance of a parallel-combining PA
is compromised when part of the circuit goes to early breakdown. Also, in bulk CMOS,
the source-body capacitance and body effect progressively reduce gain of the transistors in
the upper sections of the stack. CMOS SOI technology is particularly attractive for the
stacked-FET technique due to its lack of body effect and relatively small parasitic junction
capacitance [24] [27]. However, implementations at 60 GHz or above encounter difficulties
caused by phase misalignment between the transistor outputs due to the reactive part in
the input and output impedances of the transistors [29], and thus lead to a low power
output and efficiency (e.g., peak-PAE of 9% at 89 GHz in [30]). Hence, the mm-wave SiGeBiCMOS PA prototypes developed in this work employ common-base amplification stages
in a parallel-combining configuration, which could extend the output voltage swing beyond
32
Chapter 2. Literature Survey of mm-Wave Power Amplifiers
a) Single-ended
b) Differential
Figure 2.5: A 2-stage power amplifier with parasitics in the ground and supply paths.
the (open-base) collector-emitter breakdown voltage (BVCEO ) [31] [32]. Design details are
elaborated in Chapter 4. Note that the stacked-FET topology could potentially substitute
the single-stage amplifier in order to increase the RF power output further when a proper
technology and the required supply voltage become available.
2.2
Prior-art Millimeter-Wave Power Amplifiers
This section reviews the recently published PA circuits using the key parameters introduced
in section 2.1, and pinpoints performance barriers for mm-wave PAs at the time of writing.
2.2. Prior-art Millimeter-Wave Power Amplifiers
2.2.1
33
Single-ended and Differential Topologies
From a system point of view, a PA with a differential input and a single-ended output eases
interfacing to the differential output of the transmit mixer and the single-ended 50 Ω antenna
load. Therefore, a differential PA with a differential-to-single-ended balun at the output is
the preferred topology. This section compares single-ended and differential PA topologies.
The schematics of a 2-stage, single-ended PA and a differential PA with an output balun are
plotted in Figs. 2.5a and 2.5b, respectively. Interstage matching networks are required for
maximum power generation, which are represented by monolithic transformers in Fig. 2.5b.
Fewer components, and thus smaller chip area are needed for a single-ended design, as
opposed to its differential counterpart.
Despite its simplicity, one drawback of the single-ended topology relates to parasitics in the
supply and ground paths. Due to wiring on chip and inside a package, there are considerable
parasitic impedances, especially from bondwire inductance. It causes the AC ground potential to fluctuate, which in turn reduces power gain. As described in Section 2.1.3, it should be
avoided because of the limited MAG/MSG at mm-wave frequencies. Another consequence
from the finite ground impedance is reduced output-to-input isolation. A (shared) ground
plane serves as a return path between stages, which can be a source of parasitic positive
feedback that can cause oscillations. The ground plane also increases the crosstalk between
blocks in an integrated transceiver. Sensitive analog/RF circuits might also be affected by
crosstalk and noise from the digital circuitry coupled via the common ground. Therefore, layout becomes critical to the performance of a single-ended topology. A low inductance ground
plane suppresses the crosstalk and improves isolation. Advanced packaging techniques such
as flip-chip [33] [34] [35] reduce parasitic inductance significantly and are therefore used
widely in the mm-wave frequency regime. Separation between analog and digital grounds on
chip, or between sensitive signal paths, also helps to improve isolation [36].
However, the difficulties described above are overcome more easily when a differential topology is used. A balanced, symmetric signal path creates a virtual ground along the line of
symmetry (e.g., nodes A-D in Fig. 2.5b), thereby making it less susceptible to parasitics
present in the ground and supply paths. However, the common-mode behavior of the circuit
still needs to be examined carefully to ensure stability. The output balun, which could be
incorporated into the output matching network, will be discussed in Section 2.3 and addressed in Chapter 3. It is shown in the next section that both single-ended and differential
topologies have been successfully exploited in mm-wave PAs.
2.2.2
Single-cell Amplifiers
The maximum power output from a single-cell amplifier is determined by the voltage and
current limits of the transistor. The supply voltage, which complies with the breakdown behavior, sets the voltage limit, while the maximum supply current is constrained by the device
speed (i.e., fT ) and reliability (e.g., metal electromigration). Fig. 2.6 shows typical collector current vs. collector-emitter voltage (i.e., I-V) curves with load-line matching illustrated
(from which Eq. 2.12 is derived).
34
Chapter 2. Literature Survey of mm-Wave Power Amplifiers
16
I
Loadline matching
max
C
Collector current, I , in V
20
12
8
I
DC
4
V
CC
0
V
0.0
k
0.5
1.0
1.5
2.0
Collector-emitter voltage, V
2.5
, in V
3.0
2(V
-V )
CC
k
CE
Figure 2.6: Typical I-V curves of a CE stage with an LC tank as the load.
22
Pfeiffer 07 (60G)
20
Grujic 12 (61.5G)
Glisic 08 (60G)
16
SAT
, in dBm
Hamidian 10 (60G)
18
P
Nicolson 08 (77G)
14
Valdes 10 (60G)
Chowdhury 09 (60G)
12
Kim 12 (80G)
Chan 10 (62G)
10
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Supply voltage, in V
Figure 2.7: PSAT vs. supply voltage for mm-wave PAs in the recent literature (note that the
center frequency of each PA is annotated inside the brackets).
PSAT =
(VCC − Vk )2
(VCC − Vk )Imax
(VCC − Vk )IDC
=
=
2Ropt
4
2
(2.12)
Increasing either VCC or IDC increases the power output. However, increasing VCC is often
discouraged. The co-existence of analog and low-voltage digital circuitry in a fully inte-
Hamidian 10
[37]
Grujic 12
[13]
Glisic 08
[38]
Pfeiffer 07
[14]
Valdes 10
[39]
Giamello 12
[40]
Nicolson 08
[41]
Yishay 10
[42]
Kim 12
[43]
Chowdhury 09
[44]
Chan 10
[45]
Tang 12
[46]
a.
Freq./BW−3dB
(GHz)
PSAT
(dBm)
P−1dB
(dBm)
Peak PAE
S21
(dB)
PDC /VCC
(mW/V)
Area
(mm2 )
Technology
60/-
18
-
14%
15
198/3.3
0.53
250 nm SiGe
17.4
12.2
16.3%
14.2
257/3.3
0.62
250 nm SiGe
60/-
17.4
11.7
6.9%
32.4
800/4
-
250 nm SiGe
60/7
20
13.1
12.7%
18
240/4
0.98
130 nm SiGe
60/-
> 13.5
13.5
9%
-
-/2.6
-
120 nm SiGe
14.5
9
9%
25
100/2.5
0.24
130 nm SiGe
14.5
12
15.7%
19
161/2.5
0.15
130 nm SiGe
77/15
16
14.6
12.5%
19
200/2
1.3
130 nm SiGe
80/25
12.4
12
14.2%
11
-/2
60/22
12.6
9
8.8%
5.6
-/1
0.25
90 nm CMOS
62/8.5
11.5
5
15.2%
16
50/1
0.7
65 nm CMOS
60/-
10
7
16%
5.6
27.6/1.2
0.2
40 nm CMOS
61.5/17
77/5
77/15
a
a
a
0.32
45 nm CMOS-SOI
Topology
2-stage, SE,
CE, TXL
1-stage, diff.,
CE, cascode, L-C
3-stage, diff.,
CE, cascode, TXL
1-stage, diff.
CE, cascode, TXL
3-stage, diff.,
cascode, TXL
3-stage, diff.,
CE+CE, cascode,
transformer
3-stage, SE, CE,
cascode+CE, L-C
2-stage, SE,
CE, TXL
2-stage, SE,
CS, cascode, TXL
2-stage, diff.,
CS, transformer
3-stage, diff.,
CS, transformer
1-stage, SE, CS,
slow-wave CPW
2.2. Prior-art Millimeter-Wave Power Amplifiers
Table 2.1: Performance summary of the recently published single-cell mm-wave PAs.
Value estimated from chip micrograph of plots.
35
36
Chapter 2. Literature Survey of mm-Wave Power Amplifiers
grated transceiver requires a low voltage supply, which is also the trend imposed by scaling
towards deep submicron silicon technologies for higher integration density. As explained in
Section 2.1.4, the maximum IDC is also limited because of the additional losses from output
impedance matching network.
Table 2.1 summarizes and compares single-cell, CMOS and BiCMOS mm-wave PA designs
from the recent literature. As expected, at least 2 stages (or more) are used in almost all
the designs. The exceptions are those biased at a supply voltage ≥ 3.3 V (e.g., [13] [14]),
which increases the required Ropt and thus boosts the power gain. Fig. 2.7 is a plot of PSAT
as a function of supply voltage for the designs in Table 2.1. It is predicted that PAs at a
higher supply voltage (e.g., 3.3 V in [37], and 4 V in [14]) deliver greater saturated power
(see Eq. 2.12). However, apart from the preference towards a low supply voltage, the low
breakdown voltage constraint requires a cascode of devices to tolerate the larger voltage
swing and guarantee reliability. It is also the reason why the designs biased above 2 V in
Table 2.1 all employ the cascode topology, which complicates biasing and the physical layout.
It is noted that PAs biased below 2 V in Table 2.1 deliver PSAT lower than 13 dBm. Thus,
a different mm-wave PA topology capable of generating greater PSAT but operating from a
lower supply voltage is needed.
It is also shown in Table 2.1 that on-chip transmission lines and transformers are commonly
used for interstage matching. The transformer-coupled designs tend to consume smaller
chip area (e.g., [40] and [44] vs. [14] and [42]). The advantages of on-chip transformers are
highlighted in Section 2.3.
2.2.3
Output-Combining Amplifiers
Given a fixed supply voltage and a Ropt above 10 Ω (see Section 2.1.4), on-chip power
combining becomes effective. The concept is to sum the power produced by many PA cells
using an on-chip passive combiner. The potential RF power output after combining is higher
than what can be obtained from a single amplifier cell. For ideal N -way combining, the total
PA power output is
PSAT = N
(VCC − Vk )2
(VCC − Vk )Imax
(VCC − Vk )IDC
=N
=N
2Ropt
4
2
(2.13)
where the power increase is 10 · log10 N in dB, Vcc and Vk are the supply and BJT thermal
voltages, respectively, and Imax is the maximum current.
Table 2.2 summarizes and compares the recently published power-combining, CMOS and
BiCMOS mm-wave PAs. The saturated output power in Table 2.2 reaches approximately
15 dBm or above, and is on average about 3 dB higher than that in Table 2.1, which validates
the concept of on-chip power combining. Pfeiffer, et al. [47], demonstrated a 60 GHz PA
with the highest PSAT (i.e., 23 dBm) by employing both power-combining and a high supply
voltage (i.e., 4 V). The PA in [48] achieved 21–23 dBm PSAT using wafer-level free-space
combining at the expense of a much larger chip area (i.e., 48 mm2 ). It is also observed that
Freq./BW−3dB
(GHz)
PSAT
(dBm)
P−1dB
(dBm)
Peak PAE
S21
(dB)
PDC /VCC
(mW/V)
Area
(mm2 )
Technology
Pfeiffer 07
[47]
60/-
23
-
6.3%
20
-/4
3.42
130 nm SiGe
Asetal 11
[48]
90/16
21–23
-
5.8%
21.5
3230/1.7
48
130 nm SiGe
Afshari 06
[49]
85/24
21
a
<3.5%
8
2475/(-2.5+0.8)
2.4
130 nm SiGe
77/15
17.5
14.5
12.8%
17
297/1.8
0.61
120 nm SiGe
60/16
14.5
10.5
10.2%
26.1
-/1.8
0.64
90 nm CMOS
a
> 14
14
8.3%
7
-/1.2
0.2
65 nm CMOS
60/-
14.2
12.1
5.8%
4.4
145/1
1.2
90 nm CMOS
60/-
17.7
16.8
11.1%
19.2
460/1
2.3
a
65 nm CMOS
60/8
19.9
18.2
14.2%
20.6
-/1.2
1.76
90 nm CMOS
Martineau 10
[56]
60/15
18.1
11.5
3.6%
15.5
1504/1.8
0.76
a
65 nm CMOS
Chen 11
[57]
60/9
18.6
15
15.1%
20.2
-/1
0.42
a
65 nm CMOS
Komijani 06
[50]
Jen 09
[51]
Pallotta 10
[52]
Bohsali 09
[53]
Lai 10
[54]
Law 10
[55]
a.
56/3
20
Topology
8-way transformer comb.,
2-stage, diff.,
CE cascode
3×3 free-space
comb., 4-stage, SE, CE
4-way LC ladder comb.,
8-stage, SE,
CE cascode
2-way TXL comb.,
4-stage, SE, CE
4-way transformer comb.,
3-stage, diff., CS cascode
8-way transformer comb.,
comb., 1-stage, diff., CS
4-way TXL comb.,
2-stage, SE, CS
8-way transformer comb.,
4-stage, diff., CS
4-way Wilkinson comb.,
4-stage, SE, CS
16-way transformer
comb., 2-stage,
diff., CS cascode
4-way transformer
comb., 3-stage, diff., CS
2.2. Prior-art Millimeter-Wave Power Amplifiers
Table 2.2: Performance summary of the recently published power-combining mm-wave PAs.
Value estimated from chip micrograph of plots.
37
38
Chapter 2. Literature Survey of mm-Wave Power Amplifiers
18
Grujic 12
Tang 12
15
Chan 10
Hamidian 10
Kim 12
PAE, in %
Single-cell PA
Nicolson 08
Pfeiffer 07
12
Yishay 10
9
Valdes 10
Giammello 12
Pallotta 10
Pfeiffer 07
6
Atesal 11
Bohsali 09
3
Power-combining PA
10
12
14
16
18
20
Saturated output power P
SAT
22
24
, in dBm
Figure 2.8: PAE vs. PSAT for mm-wave PAs in the recent literature (note that the center
frequency of each PA is annotated inside the brackets).
the earlier developed PAs capable of delivering 20 dBm output power (i.e., [47] in 2007, and
[49] in 2006) either consumes a large chip area (e.g., > 2.4 mm2 ), or presents a low PAE (e.g.,
< 6.5%) from a supply voltage above 2.5 V. Law, et al., [55] reported a 60 GHz, 19.9 dBm PA
in 2010, but again occupied 1.76 mm2 chip area. Transformer-combining designs in [51] and
[52] can deliver > 14 dBm output power in CMOS, while consuming smaller than 0.6 mm2
chip area. However, the measured PAE remains limited to 10%.
Fig. 2.8 plots PAE as a function of saturated output power for the designs listed in Tables 2.1
and 2.2. Despite the increase in PSAT , power-combining PAs present a relatively lower PAE
compared to the single-cell designs. Komijani, et al. [50], presented a 77 GHz PA (see Table 2.2), which reached 12.8% peak-PAE, but it remains closer to the low bound of what a
single-cell PA can achieve. The PAE degradation is most likely caused by extra losses from
the on-chip output combiner. Thus, the design of an efficient (i.e., low loss) and compact
on-chip power combiner is a priority for a power-combining PA topology.
2.3
On-chip Passive Power Combiners
Power combiners can be realized in both active and passive modes. Active designs provide
gain and better isolation [58], but are not preferred for PAs because of efficiency degradation
from extra power consumption. The passive mm-wave combiners are expected to increase the
PA overall output power by summing the outputs of several PA cells without significantly
compromising the efficiency. The design target for an efficient PA combiner at 60 GHz is to
2.3. On-chip Passive Power Combiners
39
Figure 2.9: LC balun output combiner.
perform load-line impedance matching over a wide bandwidth (e.g., 57–64 GHz) with low
loss (< 1 dB) and compact chip area (< 250×250 µm2 ).
2.3.1
LC Balun Combiner
A 2:1 balun is a 2-way power combiner. It sums differential signals to one single-ended output
with a certain impedance transformation ratio. A lattice-type LC balun [59], as shown in
Fig. 2.9, is typically used in low-GHz bands (e.g., 5.3 GHz in [60] and 2.45 GHz in [61]). The
combined output voltage (vout ) and impedance transformation ratio (m) are
vout = RL
1
− v+ − sCv− = RL
sL
and
jRL
j
=
v+ − jωCv− (v+ − v− )
1
ωL
ωL
ωC= ωL
Zin−
1 ωL
Zin+
=
=
m=
RL
RL
2 RL
2
.
(2.14)
(2.15)
√
Beyond resonance (ωo = 1/ LC), one PA output (v+ ) sees an inductive load, while the other
(v− ) drives a capacitive load as seen from Eq. 6.7. The load asymmetry causes a drop in
the maximum RF output of the PA and limits the useful bandwidth (e.g., 0.9 GHz in [60]).
Moreover, it is not area efficient due to chip area consumed by the two inductors. Combining
them into a transformer saves chip area [62], but can still suffer from load imbalance and
narrow bandwidth.
2.3.2
Marchand Balun Combiner
A Marchand balun (see Fig. 2.10a) consists of two quarter-wavelength (λ/4) transmission
lines. Its impedance transformation ratio (m) [64] [65] and port imbalance (∆) [66] are
Zin−
2
Zin+
=
=
m=
RL
RL
RL 2
Zoo Zoe
Zoe − Zoo
2
(2.16)
40
Chapter 2. Literature Survey of mm-Wave Power Amplifiers
a) Conventional Marchand balun combiner
b) Expanded Marchand balun combiner
Figure 2.10: Simplified layout of a Marchand balun combiner [63].
and
∆=
S21
Zoe − Zoo
=−
,
S31
Zoe + Zoo
(2.17)
where Zoo and Zoe represent the odd- and even-mode characteristic impedances, respectively.
It offers a wider bandwidth than the LC balun combiner when applied to a PA (e.g., 9.5 GHz
in [63] vs. 0.9 GHz in [60]). However, the difference between Zoe and Zoo needs to be maximized in order to minimize the port imbalance (note that ideally ∆ = -1 from Eq. 2.17) and
suppress even-mode propagation. Thus, the transmission line coupling coefficient (C) needs
to be increased (note that Zoe /Zoo = (1 + C)/(1 − C) [67]), which is limited by the minimum
gap between metals for edge-coupled, or the dielectric thickness for broadside-coupled designs. Cascading multiple sections can realize a very high Zoe (e.g., 300 Ω on a PCB in [66])
at the expense of greater chip area. It can also be extended to combine more amplification
paths, as shown in Fig. 2.10b [63]. However, the power loss is relatively high in advanced
silicon technologies (e.g., > 2 dB at 60 GHz in 90 nm CMOS in [63]), which hinders its
application to compact, mm-wave PAs.
2.3.3
Wilkinson Combiner
Similar to the Marchand balun, a Wilkinson combiner utilizes λ/4 transmission lines, but
provides in-phase combining. It also offers port matching and isolation [67], and is used to
sum the outputs of single-ended PAs. The impedance transformation ratio (m) is controlled
by characteristic impedance Zo (see Eq. 2.18).
m=
Zo 2
Zin+
=
RL
RL
(2.18)
2.3. On-chip Passive Power Combiners
41
a) 2-way
b) 4-way
Figure 2.11: The simplified layout (top view) of a Wilkinson combiner in microstrip
(RL = Zo ).
The original Wilkinson combiner introduced in 1960 [68] connected all of the splines and
resistors in a radial manner, and thus can be expanded as desired. However, the 2-way combiner [69] in Fig. 2.11a can only be expanded laterally in a planar silicon process. Fig. 2.11b
shows a 4-way Wilkinson combiner, which may occupy a large chip area (e.g., approximately
0.17 mm2 in [55]).
2.3.4
Generic Transmission Line based Combiner
Directly summing the currents from several in-phase PAs using a generic transmission line
matching network, as shown in Fig. 2.12, is a straightforward method to realize power combining [53] [71]. The load current is the sum of the currents in each amplification path. Thus,
the load of each branch is increased to N ·RL for N -way combining, which is undesired for
the PA output matching network because of the consequent high impedance transformation
ratio. However, this type of combiner has the potential to reduce the losses from the out-
42
Chapter 2. Literature Survey of mm-Wave Power Amplifiers
Figure 2.12: Simplified current combining PA topology using transmission lines.
Figure 2.13: Conceptual schematic of the “self-similar” PA combining topology [70].
put matching network and save chip area by integrating the transmission line interconnects
which are already present in the PA layout [53]. On-chip transmission lines are preferred
for the combiner because of the low loss and wide operating bandwidth [50] [71]. Sengupta
and Hajimiri [70] proposed a ‘self-similar’ PA power combining topology (see Fig. 2.13), in
which the number of amplification paths is increased by expanding the unit PA cell hierarchically (see Fig. 2.13). For example, 4 transistor-level amplifiers compose a 4-way PA cell
on the first level, which is then used as the unit amplifier cell on the second level for 16-way
2.3. On-chip Passive Power Combiners
43
Figure 2.14: Monolithic transformer balun.
combining, and so on. The in-phase current combining property shown in Fig. 2.12 makes it
well-suited to such a structure. Applying it to the unit amplification cell could further boost
the overall output power. One disadvantage is the complicated power distribution network,
which requires sufficient driver amplifiers. Also, the interconnects used to wire the combined
output to the next level (or output bondpad) induce uneven coupling to the amplifiers and
additional impedance transformation.
Moreover, the L-, T- or Π-type (see Fig. 2.12) matching networks are limited in layout
flexibility and occupy a relatively large chip area. Thus, it is important to reduce the physical
size of transmission lines on chip. Slow-wave propagation [72] is an effective solution since
the on-chip passive dimensions shrink with wavelength. A slow propagation velocity (vp )
decreases wavelength (i.e., λ = vp /f req), thereby leading to a compact physical size. It is
created by spatially separating electrical and magnetic fields, which could be realized by
periodically cascading a short length of high-characteristic-impedance (high-Zo ) with lowcharacteristic-impedance (low-Zo ) segments. The magnetic field concentrates in the high-Zo
sections,
q where inductance (L) is much larger than capacitance (C) per unit length because
Zo = L/C. The electrical energy is mainly stored in the low-Zo sections because of its
larger capacitance per unit length. Thus, the cascade generates both large inductance and
√
capacitance per unit length, thereby increasing the group delay (i.e., τ = LC) and slows
the phase velocity (i.e., vp ∝ 1/τ ).
Slow-wave propagation opens up new opportunities for compact transmission lines on chip.
The wavelength reduction factor is defined as the square root of the ratio of the effective
permittivities with and without slow-wave effect. This work proposes a straight quarterwavelength coplanar waveguide (CPW) based combiner which simplifies layout and exploits
in-phase signal-to-signal coupling in order to increase the wavelength reduction factor further.
More detailed design discussions are covered in Chapter 3.
44
Chapter 2. Literature Survey of mm-Wave Power Amplifiers
Secondary
Primary
Z3
v3
Cm
L11
iL
v1
L22
i1
Substrate
Ground plane
Z4
v4
Figure 2.15: Simplified layout of a transformer balun [75].
2.3.5
Monolithic Transformer Combiner
Monolithic transformers are widely used on chip because of their compact dimensions and
wideband operation from tight magnetic coupling [73] [74]. An ideal transformer in Fig. 2.14
has an impedance transformation ratio of n2 , where n is the primary-to-secondary turns
ratio. Under a differential excitation, the virtual ground shown in Fig. 2.14 can be used
to feed supply current, thereby simplifying the biasing. A transformer balun also performs
differential-to-single-ended transformation and thus serves as a 2-way output power combiner
[44] [45].
However, port imbalances exist in a balun structure due to the parasitic capacitance between
the primary and secondary windings. The effect is exacerbated when the physical layout is
scaled to operate at mm-wave frequencies. Fig. 2.15 shows elemental primary and secondary
windings of a transformer, where Cm represents the interwinding capacitance, Z3 and Z4 are
the load impedances at the secondary outputs, voltage v1 appears across Cm , and i1 is the
current flowing into primary terminal 1. The voltages at the secondary outputs (v3 and v4 )
are the superimposition of both capacitive and inductive couplings. When jωL22 ≪(Z3 + Z4 ),
v3 and v4 are given by
and
!
(2.19)
!
(2.20)
v3 ∼
=
Z3
di1
dv1
− Lm
Z4 C m
Z 3 + Z4
dt
dt
v4 ∼
=
di1
dv1
Z4
,
+ Lm
Z3 C m
Z 3 + Z4
dt
dt
√
where Lm is the mutual inductance (i.e., km L11 L22 , km is the magnetic coupling coefficient).
Ideally, Cm equals zero, and v3 and v4 are identical in magnitude but anti-phase. For Z3 = Z4
and Cm = 0, |v3 | = v4 = Lm /2 · (di1 /dt), which is the desired transformer action. However,
the coupling via Cm (i.e., the first term in Eqs. 2.19–2.20) causes v3 and v4 to differ from
Lm /2 · (di1 /dt) when Z3 k Z4 is larger than zero, leading to unequal impedances reflected at
the outputs and poor impedance uniformity between ports. Uniformity is desired in order for
2.3. On-chip Passive Power Combiners
45
Figure 2.16: Simplified schematic of PA using a series-connected transformer combiner [76].
all of the PA cells to reach their maximum power output simultaneously, thus maximizing
the total power output and PA efficiency.
At lower frequencies, Shibita or Frlan winding configurations [73] can be used. Increasing
the number of turns in these structures increases Lm more rapidly than Cm , which in turn
suppresses the deleterious influence from Cm . However, transformer combiners scaled to
operate at mm-wave frequencies are limited to a small number of turns on each winding
by the desired self-inductance, which determines the total (i.e., unwound) length of each
winding. For example, a 133 pH (self-inductance) secondary winding designed to drive a
50 Ω load at 60 GHz requires just 2 turns of 3 µm thick, 5 µm wide metal with 20 µm
transformer inner dimension. The Finlay (i.e., overlay) structure [73] is thus often employed
to enhance the magnetic coupling and reduce insertion losses at mm-wave frequencies. The
width of the windings in the Finlay structure can also be increased for tighter magnetic
coupling. However, both lead to a higher Cm , which exacerbates the port imbalance.
Additionally, more than 2 amplification paths are required in order to increase output power.
Niknejad proposed a series-connected transformer combiner (SCT) to sum 4 differential PA
outputs at 2.4 GHz and 5.8 GHz (see Fig. 2.16) [77] [76] [61]. The output swing across load
resistor RL is ideally increased by the number of transformers. Its impedance transformation
ratio is defined as
Zn
n2
m=
= ,
RL
N
(2.21)
where N is the number of series-connected stages, and n is the primary-to-secondary turns
ratio of each transformer (n ∼
= 1 in Fig. 2.16).
The major disadvantage is that this combining topology consumes a large chip area (e.g.,
0.16 mm2 and 1/5 of the overall chip area in [76]), which eliminates the area-efficient advan-
46
Chapter 2. Literature Survey of mm-Wave Power Amplifiers
Figure 2.17: Simplified layout of DAT [78].
tage of monolithic transformers. Moreover, it is not well suited to mm-wave frequencies due
to the aforementioned parasitic interwinding capacitance and coupling capacitance between
the windings and the substrate. The leakage via the parasitic capacitance to the substrate
also causes currents flowing through the secondaries of each transformer to differ (i.e., between PA cells). It leads to uneven reflected impedances seen at the PA cell outputs, which
then require separate sizing and adjustments to compensate each cell, thereby complicating
the overall design.
K.H. An, et al. [79], proposed a parallel-combining transformer (PCT), where the magnetic
fields produced by each primary winding are coupled to the secondary winding and added.
The design could be more compact than a SCT in Fig. 2.16. However, its impedance transformation ratio (i.e., m = N ×n2 ) increases with the number of amplification paths. Thus,
it requires the secondary winding to have more turns than the primary (i.e., n < 1) in order
to realize Ropt smaller than 50 Ω, which is less feasible at mm-wave frequencies.
Several designs were proposed in order to realize an area-efficient transformer combiner
with the correct impedance transformation ratio. Aoki, et al., proposed a ‘distributed active
transformer’ topology (see Fig. 2.17), which offers a much compact dimension compared
to Fig. 2.16 [78] [80]. It is a combination of N number of independent 1:1 (slab inductor)
transformers with their primaries driven by separate PA cells and secondaries connected in
series [78]. A double differential drive (i.e., one for the DC supply VCC and one for ground
connection) is utilized in order to bring the two secondary terminals (i.e., the RF output
and ground reference) into close proximity when arranging the layout for the 2N number
of independent PA cells [78]. Despite the layout elegance, the input distribution network
needs to be in the center of the layout, which causes undesired coupling to each 1:1 transformer. Moreover, the asymmetry caused by parasitic capacitance between the primary and
secondary windings remains.
2.3. On-chip Passive Power Combiners
47
Figure 2.18: Simplified layout of Cheung’s multifilament balun combiner [18].
Cheung [18] proposed a multifilament transformer balun (see Fig. 2.18), which suppresses
the influence from interwinding capacitance. The primary winding is divided into two sections, which are driven push pull from two sides, creating a virtual ground along the vertical
line of symmetry. The secondary winding consists of one complete turn (note that the two
secondaries in Fig. 2.18 are connected in parallel). The combined current from the 4 amplification paths induces a current in the secondary winding which drives the 50 Ω load,
leading to a current ratio of 1:1. The voltage ratio of each primary section starting from the
PA cell and ending at the virtual ground to the complete secondary winding is 1:4. Thus,
the primary-to-secondary impedance transformation ratio equals 1:4. Ideally, a 50 Ω load is
converted to 12.5 Ω at each PA output. The impedance uniformity is improved by dividing
the secondary into two identical parallel windings in order to balance the electric coupling
via parasitic capacitance between the secondary and primary windings. The output bondpad
is located in the center of the transformer windings. It demonstrated impedance uniformity
as good as 2.3% at 24 GHz [81].
Another practical difficulty surrounding mm-wave monolithic transformers is that the insertion losses are increased by imperfect magnetic coupling. As described before, the Finlay
structure is utilized in order to increase magnetic coupling. Additionally, substrate shielding
may be used to minimize electric energy coupling to the conductive silicon substrate. The details of substrate shielding are covered in Chapter 3. Cheung’s multifilament balun combiner
utilizes a self-shielded structure in order to minimize energy dissipation in the substrate.
However, its disadvantage is that the secondary winding encloses the output terminal in the
layout (see Fig. 2.18), which constrains its inner dimension to be larger than a bondpad.
If a 45×45 µm2 output bondpad and 80×80 µm2 inner dimension of the transformer are
assumed, an upper frequency limit of 40 GHz is predicted from electromagnetic (EM) simulation. Overlapping the bondpad with the transformer windings in order to operate in the
60 GHz band increases the uneven coupling between them, which fosters port impedance
imbalance (see Chapter 3). It makes the layout unsuitable for Gb/s wireless transceiver
48
Chapter 2. Literature Survey of mm-Wave Power Amplifiers
or automotive radar applications in the upper mm-wave range. Therefore, one objective of
this work is to develop compact transformer combiners capable of offering excellent port
impedance uniformity at mm-wave frequencies. The comparison of Cheung’s design with the
transformer combiners developed in this work is provided in Chapter 3.
2.3.6
Conclusions
This section reviewed and compared the pros and cons of several on-chip power combiners.
Transmission lines and transformers are capable of offering impedance transformation with
low losses over a wide bandwidth, and thus are well suitable for mm-wave power combiner
design. It is recognized that port uniformity remains a challenge for compact, multiport,
monolithic transformer balun combiners at mm-wave frequencies. It is also realized that chip
area and layout flexibility are critical for transmission line based combiners. The performance
of passive components closely depends on the back-end-of-line (BEOL) scheme (e.g., metal
and dielectric thicknesses). For example, realizing transformer combiners with low insertion
loss requires at least 2 thick metals, an option that is typically not available in standard or
low-cost CMOS technologies. Therefore, this work concentrates on addressing the existing
problems in transformer and transmission line types of combiners, and providing designs
which cater to the strengths inherent in the specific technology used to implement them.
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Chapter 3
On-chip mm-Wave Power Combiners and Splitters
Limited PA power output constrains transceiver dynamic range, link span, and the margin
in a wireless network. It is concluded in Chapter 2 that on-chip passive combining applied to
power amplification at mm-wave frequencies can overcome this limitation by summing the
outputs from a number of PA cells using an efficient power combiner on chip [1] [2].
Two types of combiners aimed at multi-Gb/s mm-wave wireless communication links in the
60 GHz band, namely the transformer and slow-wave coplanar waveguide (S-CPW) combiners [3] [4] are developed in this work using SiGe-BiCMOS and CMOS-SOI technologies,
respectively. The chapter begins with general design requirements for passive on-chip combining, and several techniques that reduce losses and imperfections in these combiners are
discussed. New designs that compensate for interwinding capacitive parasitics of a transformer combiner are described afterwards, together with experimental results for the prototypes. The transmission line combiners based on slow-wave propagation and characterization
of the prototype are presented in the last section of this chapter.
A passive power combiner is reciprocal and can be used as a power splitter by swapping the
input and output. In this chapter, the term ‘combiner’ is used for brevity in the text, however, the analysis and design techniques apply to power splitters and interstage impedance
matching using transformers and transmission lines as well.
3.1
mm-Wave Monolithic Passive Combiners
Linear, reactive combiners can be made resonant with the output capacitance of each amplifier cell in order to realize both high frequency operation and a wideband response. However,
an efficient combiner capable of preserving PA output power and efficiency in the desired
frequency band requires co-design with the PA circuit, which imposes several design requirements on the combiner.
3.1.1
Design Requirements
For N -way combining, where N is the number of amplification paths, the increase in output
power is 10·log10 N . A compact power combiner (i.e., outer dimensions ≪ signal wavelength)
on a silicon chip can therefore increase output power and preserve efficiency at mm-wave
53
54
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
frequencies if its insertion loss is a small fraction of 10 · log10 N . Non-uniformity in combiner
input ports should be minimized so that all PA cells attain their maximum output power
simultaneously. Imbalance in reflected load impedances, or amplitude and phase errors in
port voltages, could drive an amplifier cell into early breakdown, or otherwise limit the total
output power. Identical reflected impedances on the order of 10 Ω should be seen at each
combiner input port. Given a fixed supply voltage, transforming the 50 Ω (single ended) or
100 Ω (diff.) load to a smaller impedance (e.g., on the order of 2–3 Ω) for higher output
power typically leads to insertion loss of the matching network that is higher than the power
increase (see Section 2.1.4 in Chapter 2). In addition, the multi-Gb/s wireless communication
application requires the PA combiner to cover approximately 8 GHz bandwidth.
Thus, efficient mm-wave PA combiners are expected to transform a 50 Ω or 100 Ω load to
multiple identical port impedances with low insertion loss over a wide frequency range while
occupying little chip area. The combiner review in Chapter 2 reveals that monolithic transformers with tight magnetic coupling and also transmission lines are capable of wideband
operation [5] [6] [7], and are therefore well-suited to design of mm-wave combiners with a
target bandwidth of about 8 GHz. The two classes of combiners developed in this work are
based on monolithic transformers and slow-wave coplanar waveguides (S-CPWs).
However, realizing transformer-type combiners with low insertion loss requires at least 2
thick metals, which is an option not available in every technology. Moreover, there exists
inherent imbalance in electric coupling between windings in a transformer combiner via
interwinding capacitance (i.e., n balanced, primary windings coupled to a single secondary
driving a 50 Ω load to ground). Transmission-line-type combiners relax the requirement
on thick metal layers. However, quarter- and half-wavelength lines, such as in Wilkinson
combiners, consume a large chip area even at mm-wave frequencies (e.g., 536×150 µm2
and 305×294 µm2 in [8]). Apart from metal losses, substrate coupling and parasitics are
the main obstacles to the development of a low-loss mm-wave combiner. Proper shielding
reduces losses caused by substrate dissipation, but compromises performance because of the
increase in capacitive parasitics and reduced operating bandwidth at mm-wave frequencies.
Section 2.3.5 in Chapter 2 analyzed the influence of interwinding capacitance on port uniformity in several prevalent transformer combiners. The multifilament balun combiner proposed
by Cheung [9] demonstrated improved port balance across 22–26 GHz. The following section
examines its behavior when scaled to operate in the 60 GHz band. Agilent-MomentumTM
R
R
were used for all passive component
and Integrand-EMX
2.5-D simulator, EM-Sonnet
simulations presented in this chapter.
3.1.2
Interwinding Capacitance
The primary and secondary windings in Cheung’s multifilament design are implemented on
overlapping metal layers to strengthen the magnetic coupling between them (see Fig. 2.18
in Chapter 2). The secondary is divided into 2 identical windings in order to balance electric
coupling between it and the primary via the parasitic interwinding capacitance, thereby
reducing - but not entirely eliminating - variations in the reflected impedance. The secondary
3.1. mm-Wave Monolithic Passive Combiners
55
20
0.7
41
15
Amplitude error, in dB
0.5
0.3
10
v
21
v
31
5
0.1
v
41
Phase error, in degree
and
31
0
-0.1
41
-5
-0.3
50
55
60
65
Frequency, in GHz
Primary reflected impedance, in Ohm
Figure 3.1: Amplitude and phase errors in port voltage for the scaled, multifilament combiner
from simulation (50 Ω load).
30
Q
1
and Q
Real part
3
20
Q
2
and Q
4
10
Q
0
2
and Q
4
Imaginary part
Q
1
and Q
3
-10
50
55
60
65
Frequency, in GHz
Figure 3.2: Primary port impedances for the scaled, multifilament combiner from simulation
(50 Ω load).
winding in Cheung’s layout encloses the output bondpad, which constrains its scalability.
Scalability could be realized by implementing the windings in the two interconnect metals
below a topmetal output bondpad. However, this does not make optimal use of the thick
metal layers (usually only the top 1 or 2 metals), which are required to reduce losses in the
transformer windings.
The multifilament design is scaled to operate in the 60 GHz band (3-metal layout and
45 × 45 µm2 bondpad). Fig. 3.1 shows the voltage amplitude and phase errors at the primary
ports of this combiner across 50–65 GHz from EM simulation. One of four ports (i.e., port 1
56
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
in this case) is used as the reference. The amplitude error approaches 0.5 dB at 65 GHz, and
the phase error is as high as 15◦ due to the unequal capacitive loading and coupling between
the bondpad and the balun windings. As a result, there is more than 15% variation in the
real part of the reflected port impedance at 63 GHz (see Fig. 3.2). Moreover, the impedances
seen at the collectors of Q1,3 and at the collectors of Q2,4 (see Fig. 3.2) resonate at different
frequencies (i.e., 57.5 GHz vs. 62 GHz). Thus, the PA cells cannot develop their maximum
output power simultaneously because the impedance seen by each cell is not consistent.
3.1.3
Substrate Shielding
Leakage of the magnetic flux due to poor confinement in a planar, low-permeability transformer with 1 or 2 turns can cause insertion loss on the order of 1.5 dB (or more) at 60 GHz.
Deep submicron silicon technologies offer up to 10 metals for circuit wiring, and these layers
may also be used to shield passive components from the substrate, thus reducing attenuation. Two methods of shielding relevant to the combiner designs in this work are reviewed
in the following subsections.
A.
Self-shielding
The effectiveness of electric shields, such as the patterned ground shield [10] [11], depends
on the impedance of the ground path from the shield to the off-chip (0 V) ground reference.
The ground path impedance usually increases with increasing frequency due to inductance,
which compromises the shield’s effectiveness. In addition, the parasitic capacitance of an
explicitly-grounded shield loads a transformer combiner, and will constrain the operating
range by lowering the shielded components’ self-resonance frequency.
Self-shielding [12] places a transformer winding that is driven by a (relatively) low voltage
between the substrate and a winding (or windings) driven by higher voltages. The low-voltage
winding acts an electric shield without using a separate shield layer or ground reference. The
multiport transformer combiners in a PA are driven by amplifier cells that place a relatively
low peak voltage swing on each primary compared to the swing at the secondary winding
output (i.e., at the 50 Ω load). Therefore, the primary winding may be used to shield the
secondary from the conductive substrate. When self-shielded in this manner, the primary
can still couple electric energy to the substrate, but at a relatively low level because of the
lower voltage swing present on each primary winding. Another advantage of self-shielding
is that current crowding is mitigated if the primary winding partially, or even fully encloses
the secondary winding, despite the concomitant increase in interwinding capacitance [9].
B.
Floating Shield
Cheung, et al., proved that self-shielding could effectively minimize substrate dissipation in
monolithic transformers [13] [9] [12]. However, a properly shielded substrate is also necessary
for low-loss transmission lines on chip. Coplanar waveguide (CPW) is often preferred over
microstrip transmission lines on chip at mm-wave frequencies because crosstalk is reduced
and isolation is improved by shielding from the grounds adjacent to each signal conductor
3.1. mm-Wave Monolithic Passive Combiners
57
Figure 3.3: Isometric view of a CPW with a floating shield.
[14]. A floating shield beneath a CPW increases the capacitive loading without significantly
affecting the transmission line inductive part [12]. A relatively wide range of transmission
line characteristic impedances may be realized when a patterned, floating shield is employed,
because the magnetic field is not confined by the shield.
Fig. 3.3 shows the isometric view of a CPW with a floating electric shield. An array of narrow,
metal shield strips is placed beneath the CPW with width (Wsh ) and space (Ssh ) on the order
of a micrometer [12]. The shield has minimal effect on the magnetic field as each shield strip
is short in the direction of signal current flow on the G-S-G conductors as shown in Fig. 3.3.
Capacitive loading of the (electrically) floating shield on the CPW is lower than that of an
explicitly grounded shield, although the difference becomes small when Ssh is much smaller
than the distance between the CPW conductors and the shield (e.g., 1 µm vs. 6 µm in [15]).
With reduced loading, a wider signal conductor with greater current carrying capability may
be employed for a given CPW characteristic impedance. Thus, metal losses are reduced in
a high current application like the PA. The floating shield can also be designed to conform
with the metal pattern density rules in advanced interconnect fabrication processes.
The shield potential is established through electric induction. There is little AC signal variation on the wide coplanar ground conductors (i.e., WG ≫ WS in Fig. 3.3). Thus, the shield
potential is kept close to that of the wide coplanar grounds via capacitive couping. Although
shielding is not required to reduce substrate losses in CMOS-SOI technology (because the
substrate is insulating) [16], slow-wave propagation is induced by adding a floating shield
beneath the CPW [17], which effectively reduces the dimensions of transmission-line-type
combiners. Details are explained in Section 3.3 of this chapter.
The combiner prototypes are designed and compared in SiGe-BiCMOS and CMOS-SOI
technologies. The 130 nm SiGe-BiCMOS technology has 6 copper layers and thick metal
option (2 thick metals) with a substrate resistivity of 10 Ω·cm [18]. The 65 nm CMOS-SOI
58
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
a) Floating parasitic-compensated quadrafilar balun combiner
b) Fully-differential trifilar transformer combiner
Figure 3.4: Physical layouts of new transformer combiners.
technology has an insulating substrate (SOI) and 6 copper layers (thick topmetal only) [19].
The prototypes cater to the strengths inherent in each technology. The transformer combiners
make best use of the thick top metal layers available in the SiGe-BiCMOS technology, while
slow-wave CPW combiners utilize the entire CMOS metal stack and wavelength reduction,
and capitalize on the excellent microwave properties of the insulating substrate. The next
section describes design details of the compact, low-loss mm-wave transformer combiners in
SiGe-BiCMOS, which overcome many of the drawbacks in previous designs.
3.2
Transformer-type Power Combiners
The floating-compensated balun and the fully-differential transformer combiners are the
new designs developed in this work. The compact transformer balun combines 2 PA cell diff-
3.2. Transformer-type Power Combiners
Floating terminal output
2.5
50
2.3
30
2.1
10
1.9
-10
1.7
-30
Phase of output voltage, in degree
Magnitude of output voltage, in V
RF output
59
-50
1.5
50
55
60
65
Frequency, in GHz
Figure 3.5: Magnitude and phase comparisons of the voltages at the RF output and the
floating node in Fig. 3.4a from simulation.
erential outputs to a single 50 Ω load (i.e., 2∆:1 transformer combiner). The fully-differential
combiner interfaces with a differential 100 Ω load (i.e., 2∆:1∆ transformer combiner). Physical layouts of the new transformers are shown in Fig. 3.4. These combiners are capable of
operation well beyond the 60 GHz band, and are amenable to scaling as their output(s)
lie at the transformer periphery rather than the center of the physical layout. Differential
pairs drive each primary winding push pull, thereby creating a virtual ground along the
vertical line of symmetry in the primary windings. Ideally, the primary-to-secondary voltage
ratio is 1:4 (Fig. 3.4a) and 1:8 (Fig. 3.4b), and the current ratio is 1:1 (Fig. 3.4a) and 2:1
(Fig. 3.4b). Thus, the (drawn) impedance transformation ratio between the primary and
secondary windings is 1:4 (Fig. 3.4a) and 1:16 (Fig. 3.4b). The 2-turn secondary in both
designs provides compensation of the primary-to-secondary interwinding capacitance, which
is explained in the following section.
3.2.1
Parasitic Compensation
For the balun combiner in Fig. 3.4a, an additional ‘dummy’ filament is added to the secondary
winding for parasitic compensation. The push-pull differential pairs drive the 4 primary
terminals with the same amplitude but different phases. The RF output couples to the 4
primary winding sections with decreasing amplitude along the winding, which in turn causes
unequal electric coupling. The dummy filament (i.e., S’, the shaded winding on the top in
Fig. 3.4a) replicates the voltage swing seen at the actual RF output and along the length
of the winding. Fig. 3.5 compares the voltage outputs at the RF and the floating terminals
60
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
Figure 3.6: Simplified interwinding capacitance compensation model.
in Fig. 3.4a across 50–65 GHz from simulation, where four AC current sources with 50 mA
each drive the 4 primary terminals push pull, and 250 fF capacitance is in shunt with each
primary input to resonate at 60 GHz. Despite the difference in load condition between the
two outputs (i.e., 50 Ω vs. floating), the voltage at the floating terminal tracks the actual
RF output with good accuracy. The magnitude and phase differences across 50–65 GHz are
smaller than 9% and 17◦ , respectively. Therefore, via the winding arrangement in Fig. 3.4a, a
primary winding is coupled to the actual secondary winding with a higher voltage swing, and
to the dummy filament with a lower voltage swing, or vice versa, minimizing the difference
in voltage coupling.
Fig. 3.6 shows a simplified model to illustrate the interwinding capacitance compensation
principle. The RF output couples to the 4 primary sections via interwinding capacitance Cci ,
where i = 1, 2, 3, 4. The subscripts are consistent with the annotations in Fig. 3.4 (e.g., Cc1
w.r.t. Q1 and Cc2 w.r.t. Q2 ). The difference in voltage coupling could be represented by a
difference in capacitance Cci . Thus, Cc2 > Cc1 > Cc3 > Cc4 because the amplitude decreases
from the output to ground (see Fig. 3.4a). The scaling of capacitance related to the floating
′
′
′
′
> Cc4
> Cc2
> Cc1
. The total coupling between the secondary and each
output S ′ is: Cc3
′
′
′ ∼
′
′
′
primary winding is the sum of Cci and Cci′ . As Cc1
+ Cc1
= Cc4 + Cc4
= Cc3
+ Cc3
,
= Cc2 + Cc2
the unequal voltage coupling from interwinding capacitance is effectively equalized. Different
from the multiturn trifilar in [20], this new 4-filament balun design equalizes not only the
capacitive loading seen by one differential pair, but also the loading seen at all inverting and
non-inverting ports (i.e., 2 diff. pairs in Fig. 3.4a).
Fig. 3.4b shows a simplified layout of the fully-differential trifilar combiner. Like its floating compensated counterpart, a secondary winding of 2 turns is necessary for interwinding
capacitance compensation. If a single-turn secondary was used, the portion coupled to the
primary section connected to transistors Q1 and Q3 , (i.e., closest to the virtual ground of
secondary), would see a voltage swing smaller than the other primary section coupled to
transistors Q2 and Q4 . Interwinding capacitive coupling is mitigated by driving the 2-turn
secondary differentially. Placing the secondary portions with the lowest voltage swing (i.e.,
3.2. Transformer-type Power Combiners
61
Impedance at primary, in Ohms
20
Real
15
10
5
Imaginary
0
-5
50
55
60
65
Frequency, in GHz
a) Floating parasitic-compensated quadrafilar balun combiner (50 Ω load)
Impedance at primary, in Ohms
20
15
Real
10
5
Imaginary
0
-5
50
55
60
65
Frequency, in GHz
b) Fully-differential trifilar transformer combiner (100 Ω load)
Impedance at primary, in Ohms
30
20
10
Imaginary part
0
-10
50
55
60
65
Frequency, in GHz
c) Non-compensated transformer combiner (50 Ω load)
Figure 3.7: Simulated impedances reflected from secondary to primary.
62
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
the virtual ground) on the same side of the layout as the differential RF outputs (where the
voltage swing is largest) equalizes the average voltage coupled to the 4 primary sections.
The effectiveness of the parasitic compensation can be judged from the EM simulation results
in Fig. 3.7. The virtual grounds of the primary and the ground of the secondary winding
are connected to ports in the simulation using a 90 µm long interconnect. The real and
imaginary parts of the reflected impedances at the 4 primary ports are plotted across 50–
65 GHz. The prototypes are implemented in 130 nm SiGe-BiCMOS using top two copper
layers as windings and the aluminum capping layer (AP) as the crossover in the fullydifferential transformer. The floating-compensated balun transforms the 50 Ω output load
to 19 Ω ± 1% at each of the 4 ports on the primary windings at 60 GHz (see Fig. 3.7a).
The variation in the real part of the transformed load impedances seen between the primary
ports is less than 6% from 55–65 GHz. The fully-differential combiner converts a 100 Ω
load to 10.5 Ω at 60 GHz within 3% imbalance (see Fig. 3.7b), and the real part of the
reflected impedance exhibits only 5% variation between primaries from 55–65 GHz. Thus, the
impedance transformation ratios of the floating-compensated and fully-differential combiners
are 1:2.6 and 1:9.5, respectively. Deviations from the ideal impedance transformation ratios
are caused by leakage of the magnetic flux due to imperfect coupling between the windings.
The leakage inductance and the parasitic capacitance at the primary tends to increase the
impedance seen at each port. Compared to the multifilament balun results in Fig. 3.2, the
new balun combiner suppresses the variation in resonant frequency from 5 GHz to 1.8 GHz
(1 GHz variation for the fully-differential combiner in Fig. 3.7b). By contrast, the primary
impedances of the balun combiner without compensation (i.e., only 1 continuous turn in the
secondary winding with one terminal connected to the RF output and the other grounded)
are plotted in Fig. 3.7c. The difference in the real part of the impedances is 40% at 60 GHz
(17.1 Ω vs. 28.5 Ω).
3.2.2
Frequency Scalability
The power combiners are made resonate with shunt capacitance at the output of each PA cell
in order to provide the optimal load resistance required for maximum power output in the
desired frequency band. The center frequency of the passband scales with the self-inductance
√
and parasitic capacitance of the combiner windings (i.e., ωo = 1/ LC). Therefore, adjusting
physical parameters of a transformer combiner such as the inner dimension and winding
width could move the passband to a different frequency range (i.e., frequency scalability).
The inner dimension is defined as the distance between the inner windings on opposite
sides of the layout center, as annotated in Fig. 3.4. Enlarging the inner dimension leads to
an increase in self-inductance of the winding, thus lowering the center frequency, and vice
versa. However, the inner dimension must be large enough (e.g., 5 times the winding width
[21]) to allow the magnetic flux to pass through the center of the transformer in order to
suppress the negative magnetic coupling between the windings from two sides [21].
3.2. Transformer-type Power Combiners
63
Figure 3.8: Various cross-sections of self-shielded transformers.
A.
Self-shielding Options
Self-shielding is employed in each transformer combiner, however, a trade-off exists between
the shield effectiveness and the operating frequency of the combiner. For the transformer
balun combiners in this work, the secondary is implemented in topmetal. The primary windings in the next (second from top) level of interconnect metal overlap the secondary in plan
view, thereby (self-)shielding it from the underlying substrate (see Fig. 3.4). Fig. 3.8 shows
the various cross-sections of a self-shielded transformer. The magnetic flux is confined when
the primary winding fully encloses the secondary as shown in Fig. 3.8a, but the frequency
scalability of this design is compromised due to the increase in interwinding capacitance.
Compared to Fig. 3.8c, the primary width (Wp ) in Figs. 3.8a–3.8b is wider due to the sidewall
shield metals next to the secondary winding, leading to a larger (minimal) inner dimension
(e.g., 5×Wp [21]) necessary for the magnetic flux to go through the center. It thus limits
the maximum operating frequency of these layouts. By contrast, Fig. 3.8c eliminates the top
and sidewall shields, having a narrower primary winding and consuming less chip area, and
is therefore preferred at mm-wave frequencies because of the smaller parasitic capacitance.
B.
Lateral vs. Vertical Compensations
The dummy filament can be planar with the secondary winding (i.e., laterally-compensated,
on the same metal layer as in Fig. 3.4a), or implemented using metal layers either above or
below (i.e., vertically-compensated). The combiner in Fig. 3.9 places the dummy turn on the
metal layer below the primary. Thicker top metal layers may be used for the transformer
windings carrying the actual RF output current (e.g., Mn and Mn+1 in Fig. 3.9) in order to
lower the combiner’s insertion loss. The ground reference of the secondary winding is routed
inside the layout of the laterally-compensated balun shown in Fig. 3.4a, while it appears
at the periphery of the vertically-compensated balun of Fig. 3.9. It is easier to connect and
64
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
Figure 3.9: Physical layout of the vertically-compensated combiner.
route the ground at the periphery without disturbing the electric and magnetic fields produced by the signal windings. Thus, vertical compensation offers greater freedom to adjust
the inner dimension and metal width of the transformer windings than the lateral compensation does, thereby improving frequency scalability of the layout. The inner dimension of
a vertically-compensated transformer can be as small as 30 µm, compared to 50 µm for
its lateral counterpart, giving an operating frequency limit of about 150 GHz (note that
parasitic capacitance from active devices is excluded). However, there is asymmetry in the
coupling between the secondary winding and the substrate (e.g., the dummy is exposed to
the substrate, while the output winding is shielded by the primary). Therefore, the width of
the secondary windings should be kept narrow in order to minimize this asymmetry (e.g.,
< 10 µm). EM simulations predict that the largest imbalance between the 4 primary ports of
a 6 µm wide vertically-compensated balun is within 10%. By contrast, the laterally arranged
secondary windings in Fig. 3.4a show more effective compensation from simulation. However, the choice of shielding and parasitic compensation depends on the operating frequency
band, parasitic capacitance of the active devices, back-end-of-line (BEOL) stack thickness
and intermetal dielectric thickness.
C.
Two-Transformer Combiner
This section describes a new, current-combining transformer combiner layout, which presents
comparable insertion loss and port uniformity to the combiners described previously and
better frequency scalability. Its design also benefits from a technology back-end with 3 (relatively) thick metal layers (e.g., ∼ 1 µm), such as IBM’s 90 nm SiGe-BiCMOS technology
which offers two medium thick copper layers below the top thick copper [22].
It is noted from Figs. 3.4a and 3.9 that the primary virtual grounds of the combiners are
on the top and bottom sides of the physical layout. The difference between the two virtual
grounds must be minimized (especially at mm-wave frequencies) in order to suppress the
influence from uneven interconnections for supply feeding on the balance between a diff-
3.2. Transformer-type Power Combiners
65
Figure 3.10: Physical layout of the new 2-transformer combiner.
erential pair (e.g., Q1 and Q2 in Fig. 3.4a), as they are the AC grounds for the positive and
negative paths of a differential pair, respectively. There is a finite AC signal swing on the
virtual grounds because the transistors driving the primary push pull from two sides (e.g.,
Q1 and Q3 in Fig. 3.4a) do not form a perfect differential pair due to the small but nonzero
port imbalance. Thus, the two virtual grounds are connected together by a transverse metal
along the combiner’s vertical line of symmetry in the center of the layout (see Fig. 3.4a)
[23] [24]. Coupling between the supply connection at the layout center and the transformer
windings may be minimized by increasing the inner dimension at the expense of frequency
scalability.
Current combining realized by connecting the outputs of two separate transformer baluns
in parallel places the primary virtual grounds (and the secondary ground reference) in close
proximity at the layout periphery as shown in Fig. 3.10 [25]. However, the port impedances
reflected to the primaries are doubled. Two 1:1 transformer baluns with their outputs connected in parallel (ideally) reflects a 50 Ω load to 50 Ω impedance at each primary port,
which drives the PA load away from its optimal range of 10–20 Ω. Therefore, the secondaryto-primary (drawn) turns ratio needs to be larger than 1:1, requiring at least 2 turns and
a crossover on the secondary winding becomes necessary. However, the crossover requires
a (relatively) large chip area because there must be sufficient number of metal vias in the
crossover to handle the output current in PA applications.
The simplified layout of the proposed balun with a 2-turn secondary, which mitigates the
aforementioned limitations on frequency scalability and number of metal vias, is shown in
Fig. 3.10. The secondary windings from both transformers are laid out so that the crossover
is placed at the combiner periphery where there is enough area available for the number of
vias required to meet electromigration rules. A differential PA drives each primary winding
push pull, thereby creating a virtual ground at its center tap for supply feeding. Unlike
the combiners in Fig. 3.4, the impedances at the primary ports with the same polarity
66
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
Primary reflected impedance, in Ohm
30
20
Real part
10
0
Imaginary part
-10
60
70
80
90
Frequency, in GHz
Figure 3.11: Primary port impedances for the new 2-transformer combiner in Fig. 3.10 (50 Ω
load).
(e.g., collectors of Q1 and Q4 ) are almost identical as they experience equal primary-tosecondary coupling because of symmetry along the line indicated in Fig. 3.10. Therefore, the
uniformity between the 4 primary ports is realized if the differential primary ports within
each transformer is balanced (i.e., collectors of Q1 and Q2 in Xf mr1 , and Q3 and Q4 in
Xf mr2 ). The current in the secondary winding is reduced to approximately one-half of
the PA output current in the primary due to the 2:1 turns ratio, which allows narrowing
of the secondary width. This decreases the interwinding capacitance, while still meeting
electromigration rules. In addition, the longer coupled length of the windings in Fig. 3.10
(compared to Fig. 3.4a) offers tighter magnetic coupling, which can be traded-off for a smaller
interwinding capacitance by varying the vertical spacing between the primary and secondary
windings. The primary winding can be implemented in either of the two medium thick metal
layers in IBM’s 90 nm SiGe-BiCMOS technology without increasing the combiner insertion
loss significantly.
Fig. 3.11 plots the simulated reflected port impedances at the primaries of the combiner in
Fig. 3.10 across 60–90 GHz (i.e., 32.5 µm inner dimension and 12.5 µm wide primary on the
second medium thick metal from the top). It transforms the 50 Ω output load to 25 Ω ± 1.2%
at each of the 4 primary ports at 74 GHz. The variation in the real part of the transformed
load impedances seen between the primary ports is less than 5% from 70–90 GHz. Thus,
this combiner layout can provide excellent port uniformity with good frequency scalability
at mm-wave frequencies. The insertion loss is 0.75 dB at 74 GHz from simulation. The
reflected primary port impedance level makes it well suit to combine 4 cascode amplifiers,
which have a higher optimal load impedance required for maximum power generation than
3.2. Transformer-type Power Combiners
67
1.5
Combiner insertion loss, in dB
Cheung's combiner
Compensated balun in Fig. 3.4a
(2 :1)
Compensated balun in Fig. 3.9
1.3
Fully-differential combiner in Fig. 3.4b (2 :1 )
1.1
0.9
0.7
0.5
50
55
60
65
Frequency, in GHz
Figure 3.12: Simulated insertion loss of the transformer combiners.
a single-transistor stage due to operating from a higher supply voltage (see Chapter 4). Its
application to a cascode PA prototype will be described in Section 4.4 of Chapter 4.
3.2.3
Prototypes and Characterization
Fig. 3.12 shows the simulated insertion loss across the 50–65 GHz frequency range for the two
prototype combiners in the 130 nm SiGe-BiCMOS technology. This simulation includes a
35 µm long transmission line connection at each primary terminal, which is approximately the
length that would be used in an actual PA layout to connect to the 4 output transistors. EM
simulation predicts that the insertion losses of the parasitic-compensated balun (Fig. 3.4a)
and fully-differential (Fig. 3.4b) combiners at 60 GHz are 0.81 dB and 0.73 dB, respectively.
An insertion loss of 0.96 dB is predicted from simulation for Cheung’s multifilament balun
using the same SiGe-BiCMOS BEOL (scaled to 60 GHz as described in Section 3.1.2).
Thus, the new combiners outperform the previously reported design with lower insertion loss
and better port-to-port impedance uniformity. By contrast, the insertion loss of a floatingcompensated balun in CMOS-SOI is 1.5 dB from simulation, which is 0.7 dB higher than
the prototypes in SiGe-BiCMOS. It confirms that a thick metal option is beneficiary for the
self-shielded transformer combiner design. The 130 nm BiCMOS technology backend has
both top and second metals thicker than the other interconnect metals. Aside from lower
insertion loss, this also minimizes the width of metal required for each winding in order to
satisfy current density limits due to electromigration (e.g., max. current density of about
10 mA/µm2 for Cu).
For stand alone test structures used to characterize the transformer combiners, the virtual
(i.e., AC) ground of the primary winding and the ground reference of the secondary winding
(i.e., the DC, connecting to ground bondpads) are connected together on chip and both set
68
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
Table 3.1: Transformer power combiner prototypes.
1
2
3
4
f0
(GHz)
40
60
60
60
Primary
width (µm)
30
20
18.5
6
5
77
12
6
7
60
60
18.5
20
Prototype
SiGe-BiCMOS
CMOS-SOI
Compensation style
(cross-section reference)
Lateral comp. (Fig. 3.8b)
Fully-diff. combiner in Fig. 3.4b
Lateral comp. (Fig. 3.8c)
Vertical comp. (layout as Fig. 3.9)
Lateral comp. (Fig. 3.8c) with an
AC-coupling cap. inside bondpads
Cheung’s balun in Fig. 2.18
Lateral comp. (Fig. 3.8c)
at 0 V DC. However, the DC supply voltage of the PA output stage is fed via the virtual
ground of the primary, requiring AC coupling between the virtual and DC grounds. In
this work, an AC-coupling capacitor is embedded into the PA output ground-signal-ground
(GSG) bondpads in order to conserve chip area and minimize coupling to the combiner.
Design details are reported in Chapter 4.
Six transformer combiners are fabricated in the 130 nm SiGe-BiCMOS technology to verify
the design frequency scalability and their application to PA circuits. A 60 GHz laterallycompensated balun is also implemented in the 65 nm CMOS-SOI for comparison. It uses
topmetal and aluminum capping layers for the secondary, and a stack of all other interconnect
metals for the primary winding. Table 3.1 lists all the combiner prototypes and highlights
their difference. The prototypes in SiGe-BiCMOS operate in the 40 GHz, 60 GHz and 77 GHz
bands. The 77 GHz combiner prototype also includes the aforementioned AC-coupling capacitor embedded into GSG test pads to check the agreement between measurement and
simulation of the complicated layout. An up-banded version of Cheung’s multifilament balun
described previously in Section 3.1.2 is also included for comparison. Photomicrographs of the
transformer combiner prototypes are shown in Fig. 3.13. The 40 GHz, 60 GHz and 77 GHz
balun combiners in SiGe-BiCMOS employ the same back-to-back test structure layout as
the CMOS-SOI combiner, so their photomicrographs are cropped for greater clarity.
Each combiner has either 5 or 6 terminals (plus ground), depending upon the design. In
order to simplify RF testing, two identical transformers are configured with their primary
terminals connected in a ‘back-to-back’ configuration. Thus, the balun prototypes can be
tested as a 2-port, and the fully-differential combiner as a 4-port device. The insertion
loss of each combiner is determined from measurement in order to verify predictions from
simulation and validate the performance of each prototype combiner. The thru-reflect-line
(TRL) procedure is used to de-embed the frequency-dependent behavior of test pads and
the interconnect parasitics of the test structure [26] (refer to Appendix A for details).
Coupled transmission lines (∼ 400 µm long) connect the primaries of the transformers in the
back-to-back configuration. Fully-symmetric metal crossovers [27] maintain symmetry of the
transmission lines in the test structures. Impedance mismatch at the interface between the
combiner and the cross-coupled transmission lines causes reflection, increasing the measured
3.2. Transformer-type Power Combiners
a) Prototype 1
b) Prototype 3
e) Prototype 6, Cheung’s balun
69
c) Prototype 4
d) Prototype 5
f) Prototype 7, CMOS-SOI balun
g) Prototype 2, fully-differential combiner
Figure 3.13: Photomicrographs of the transformer combiner prototypes (see Table 3.1 for
details).
70
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
Measurement
Simulation
-0.5
S11 : 30-44 GHz
-0.3
-0.1
0.1
0.3
0.5
S21 : 30-44 GHz
a) 40 GHz floating-compensated combiner (i.e., prototype 1 in Table 3.1)
Simulation
Measurement
Prototype 3
Prototype 3
Prototype 2
-0.6 -0.4 -0.2
0.2
0.4 0.6
Prototype 2
S11 : 50-65 GHz
S21 : 50-65 GHz
b) 60 GHz transformer combiners (i.e., prototypes 2, 3 in Table 3.1)
Simulation
Measurement
-0.6 -0.4 -0.2
S11 : 70-90 GHz
0.2
0.4 0.6
S21 : 70-90 GHz
c) 77 GHz floating-compensated combiner (i.e., prototype 5 in Table 3.1)
Figure 3.14: Measured and simulated S11 and S21 of the laterally-compensated transformer
combiners from back-to-back testing (note that S22 = S11 , and S12 = S21 .
3.2. Transformer-type Power Combiners
71
Simulation
Measurement
S11
S21
50-65 GHz
Figure 3.15: Measured and simulated S11 and S21 of the 60 GHz vertically-compensated
combiner (i.e., prototype 4) from back-to-back testing.
power loss (which is not part of the combiner insertion loss). Parallel capacitors could be
added at the interface in order to realize a real resistance at the primary ports to match the
characteristic impedance of the transmission line in order to minimize the measured loss. It is
implemented and verified for the combiner used in the 60 GHz SiGe-BiCMOS PA prototype,
and details are described in Section 4.3.3 of Chapter 4.
All combiner prototypes were characterized using a 2-port vector network analyzer. The fullydifferential combiner 4-port test structure was characterized using a ‘round robin’ procedure
with a 2-port analyzer. Two of the 4 ports are excited for each measurement, with the
remaining 2 ports terminated by wideband 50 Ω loads. Four ports taken two at a time for
measurement requires a total of six 2-port measurements (i.e., C(4, 2) = 4!/2!2! = 6) in
order to collect all of the S-parameter data. The 6 datasets measured using (non-ideal) 50 Ω
termination resistors are then renormalized to ideal 50 Ω terminations in order to correct
the measured S-parameters for termination imperfections [28]. A 4-port network analyzer
was used to verify the accuracy of the measurement approach.
Fig. 3.14 shows the measured S-parameters of the 40 GHz, 60 GHz and 77 GHz combiners
(i.e., combiners 1, 2, 3, and 5 in Table 3.1), compared to EM simulation results from ADSMomentum. Excellent agreement (i.e., both the amplitude and phase) is observed between
measurement and simulation for all of the prototypes. The measured data at 40 GHz, 60 GHz
and 77 GHz shows that the combiner layouts are scalable and that the transformer design
principles are applicable to multiple frequency bands.
Fig. 3.15 plots the measured S-parameters of the 60 GHz vertically-compensated balun
combiner (i.e., prototype 4 in Table 3.1). Like its laterally-compensated counterparts, good
agreement is achieved between measurement and simulation, which validates the simulation
settings for different passive layouts.
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
Maximum available gain, MAG, in dB
Simulation
Measurement
-3
1
Compensated balun
Fully-differential combiner
-2
-5
4-port NA
2-port NA
-4
-5
Multifilament combiner
-8
-6
-11
-7
Compensated balun in CMOS-SOI
-8
-14
50
55
60
Maximum available gain, MAG, in dB
72
65
Frequency, in GHz
Figure 3.16: Measured and simulated MAG of transformer combiners (i.e., prototypes 2, 3,
6 and 7) in back-to-back testing (‘NA’-Network Analyzer).
Maximum available gain (MAG) is the metric used to determine the minimum insertion
loss of the transformer combiners. MAG in the back-to-back test configuration is twice that
of a single combiner, plus the losses from the coupled transmission lines interconnecting
the 4 primary terminals of each transformer (including reflection). Fig. 3.16 compares the
measured and simulated MAG (back-to-back) for the 60 GHz SiGe-BiCMOS combiner prototypes 2, 3 and 6 in Table 3.1. The measured MAG for the CMOS-SOI combiner (i.e.,
prototype 7 in Table 3.1) is included for comparison. Good agreement is seen in the 50–
65 GHz frequency range, while the discrepancy between measurement and simulation seen
across 50–55 GHz for the fully-differential combiner may arise from errors accumulated in
the multi-step S-parameter measurement procedure described previously. Measurement errors in the 6 measured 2-port datasets are magnified by the sensitivity of MAG to errors
in the S-parameters. MAG of the fully-differential combiner extracted from a true 4-port
S-parameters measurement using a 4-port vector network analyzer (4-port NA in Fig. 3.16)
is consistent with the 2-port measurement across 50–65 GHz, and validates the ‘round robin’
procedure, although less variation is seen.
The single compensated balun and fully-differential combiners achieve an insertion loss of
1.62 dB and 1.8 dB at 60 GHz, respectively. The fully-differential combiner loss is higher
as the secondary winding is implemented using both top and second (thick) copper metal
layers, leaving the primary in relatively thin and lossy third metal (i.e., third from the top in
the metal stack). Measured insertion loss for the scaled, multifilament combiner is 1.9 dB at
60 GHz, which is the highest among the fabricated prototypes. The difference in measured
insertion loss between the combiners agrees very well with the simulated results shown in
3.2. Transformer-type Power Combiners
73
Fig. 3.12. The 40 GHz compensated balun has a measured insertion loss of 2.1 dB versus
1.96 dB from simulation. The CMOS-SOI balun combiner exhibits a measured MAG of
4.7 dB at 60 GHz, which is 3 dB higher than its SiGe-BiCMOS counterparts. It confirms
that thick metal layers are critical for a low-loss transformer design. Despite the insulating
substrate, the 65 nm CMOS-SOI technology is not suitable for transformer designs due to the
lack of thick metal layers. Note that the insertion loss (measured or simulated) for each backto-back test structure is pessimistic in that it includes the loss of a 200 µm long transmission
line used to connect the primaries. The interconnect between the primary terminals of the
transformer combiner and the 4 amplifier cells in a PA would likely be much shorter than
200 µm, and less loss would be seen from a PA cell via the combiner to the output load. In
addition, the impedance mismatch between the combiner and the transmission line further
decreases the measured MAG.
The good agreement between measurement and simulation validates the EM simulation
settings and accuracy. The insertion loss of the combiners developed in this work is below
1 dB at 60 GHz as seen in Fig. 3.12. Thus, the frequency-scalable, parasitic-compensated,
4-way balun combiner implemented in the SiGe-BiCMOS technology backend with 2 thick
topmetal layers, which performs both impedance matching and power combining, could
effectively increase the 60 GHz PA power output by 5.5 dB, assuming 0.5 dB loss from
a conventional PA output matching network. The footprint for this 2-differential-to-singleended output balun combiner (2∆:1) is just 120× 120 µm2 .
3.2.4
Lumped-element Model
A lumped-element circuit model of the combiners’ electrical behavior is required for largesignal, time-domain circuit simulation. A number of lumped-element sub-circuits in cascade
are used to model the distributed parameter behavior of the power combiners. Fig. 3.17 shows
a simplified schematic of the floating compensated balun combiner, which consists of eight 1:1
transformer sub-circuits (schematic in Fig. 3.17b). The interwinding capacitance between the
turns in the secondary winding is not included in Fig. 3.17a for clarity. The complete model
has primary inputs P1 to P4 , secondary output S, and the floating node S’ in the case of the
floating-compensated balun. The lumped-element model for the fully-differential transformer
combiner is similar, except that the differential output is taken between terminals S and S’.
In each transformer subcircuit, inductors LP and LS represent the primary and secondary
self-inductances. These inductors, taken together with the magnetic coupling coefficient (k)
define the turns ratio of the transformer sub-circuit [6]. Inductor Lk in the primary loop
models leakage of the magnetic flux due to imperfect coupling. Ohmic losses of the metal
windings are represented by resistors rP and rS in series with the primary and secondary,
respectively. Interwinding capacitance is modeled by 4 bridging capacitors (Co1 to Co4 in
Fig. 3.17b), while CP and CS capture the stray capacitive coupling in each winding. Substrate
parasitic capacitances and losses are modeled at the primary terminals by a shunt network
consisting of Cox in series with the parallel combination of capacitor Csub and resistor Rsub .
The substrate network (i.e., Cox , Csub and Rsub ) is only used at the terminals of the primary
74
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
a) Floating-compensated balun combiner
b) 1:1 xfmr cell in Fig. 3.17a
Figure 3.17: Simplified lumped-element model of the floating-compensated balun.
winding, as the secondary is shielded by the primary from the substrate (i.e., self-shielding
of the secondary by the primary).
The equivalent circuit parameters are refined from seed values using iterative fitting of the
multiport parameters to EM simulation (or measured) data with the Agilent-ADS simulator. Behaviors for both the differential and single-ended excitations are captured by the
model. The difference (in percent) between the reflected port impedance and the insertion
loss predicted by the lumped-element model after parameter fitting and EM simulation for
the floating-compensated balun is illustrated in Fig. 3.18. The mismatch between the two
is smaller than 5% across the entire band from 55 to 65 GHz for both single-ended and
differential excitations at the primary.
3.3. S-CPW-type Power Combiners
75
between model and simulation
Normalized difference
5%
Differential excitation
Single-ended excitation
4%
Reflected port impedance
3%
2%
1%
55.0
Insertion loss
57.5
60.0
62.5
65.0
Frequency, in GHz
Figure 3.18: Difference between lumped-element model and simulation in the reflected port
impedance and insertion loss of the floating-compensated balun.
3.3
S-CPW-type Power Combiners
It is clear from the measured data and comparison in Section 3.2 that the transformer combiners perform best when implemented in the SiGe-BiCMOS technology backend with 2 thick
topmetal layers. Transformer combiners exhibit relatively high insertion loss in the technology with only thin metal layers, which consequently reduces the combined PA output power
and degrades efficiency. Increasing the transformer winding width could reduce conductor
losses, however, the resulting increase in interwinding capacitance and shunt capacitance to
the substrate constrains the combiner’s passband and operating bandwidth.
On the other hand, transmission lines can also exhibit a wideband response and low insertion
losses can be realized by stacking thin metal conductor layers and using substrate shielding.
It imposes a compromise between metal ohmic and substrate losses, that best suits CMOSSOI used in this work as the substrate losses in this technology are negligible. The impedance
transformation required in a PA combiner is controlled via the characteristic impedance (Zo ).
Moreover, slow-wave propagation can be exploited in order to design quarter-wavelength
(λ/4) power combiners with compact on-chip dimensions that require less chip area compared
to conventional transmission line combiners. This section describes the design of a 2-way
slow-wave CPW combiner in the CMOS-SOI technology. It sums two single-ended PA cell
outputs to a single 50 Ω load (i.e., 2SE:1 S-CPW combiner). The simulated performance of
slow-wave CPWs in CMOS-SOI and SiGe-BiCMOS backends is also compared.
3.3.1
Slow-wave Propagation
A cross-section of the proposed floating-shielded, quarter-wavelength ground-signal-signalground (GSSG) S-CPW combiner (SC) [4] is shown in Fig. 3.19a. The CPWs are imple-
76
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
a) Cross section
b) Top view
Figure 3.19: Cross-section and top view of the S-CPW combiner.
mented using a metal stack consisting of the top few layers. Adding floating shield metal
strips or increasing WS increases the capacitance (C) per unit length, while increasing dGS
increases the inductance (L) per unit length of the CPW. Increasing the LC product slows
√
down the signal, as the wave velocity vp = 1/ LC, yielding a slow-wave mode. The electrical
length of the combiner at a given frequency (f ) also shrinks with the decreasing velocity of
propagation, as wavelength λ = vp /f . The slowing factor is defined as the square root of the
√
effective permittivity εef f = c/vp .
The increase in capacitance from shielding narrows the usable range of the characteristic
impedance of the S-CPWs. However, the inductance per unit length is increased by almost
a factor of 2 (compared to conventional CPW) through the (in-phase) signal-to-signal line
coupling, which leads to an increase in Zo and the slowing factor. EM simulation predicts
a magnetic coupling coefficient of 0.75 at 60 GHz between the signal conductors for dSS of
2 µm and 6 metal layers in the conductor stack (i.e., from AP to metal 2).
The shield density is defined as Wsh /(Wsh + Ssh ) (see annotations in Fig. 3.3). For a given
3.3. S-CPW-type Power Combiners
77
signal conductor width WS , the wave slowing factor and insertion losses depend on the shield
density and the distance from the CPW to the shield (i.e., h in Fig. 3.19a). The larger the
shield density, the larger the increase in shunt capacitance. Thus, the wave slowing factor
increases, making the λ/4 S-CPW combiners more compact in area. The distance from the
shield to the substrate (i.e., h1 in Fig. 3.19a) also influences the S-CPW characteristics when
the gap between the shield strips (Ssh ) and the dielectric thickness between the CPW and
the shield (h) are on the same order.
3.3.2
S-CPW Comparison in SiGe-BiCMOS and SOI-CMOS
Transmission lines can be modeled by a lumped-element (i.e., RLGC) network [29], where
series inductor L represents the loop inductance, shunt capacitor C represents the total
capacitance to the ground reference, series resistor R accounts for the metal losses, and
shunt conductance G models loss in the multi-layer dielectric and the substrate. Losses from
the floating shield strips of S-CPWs are also reflected in the shunt conductance G. Quality
factors of the series RL and shunt GC sections in the model are given by QRL = 2πf L/R
and QGC = 2πf C/G, respectively. The overall Q factor of the transmission line is given by
Q = 1/(1/QRL + 1/QGC ).
Fig. 3.20a compares the QGC of S-CPWs over conductive and insulating substrates (i.e.,
10 Ω·cm in SiGe-BiCMOS vs. 3500 Ω·cm in CMOS-SOI) across 40–80 GHz with different h
and h1 values. Figs. 3.20b and 3.20c plot QRL and the overall Q factor of the same S-CPWs,
respectively. The back-end-of-line schemes of STM’s 130 nm SiGe-BiCMOS [18] and 65 nm
CMOS-SOI [19] are used in the simulations. The CPWs in both technologies are realized
using a stack of the aluminum capping and top copper layers, except the CMOS-SOI S-CPW
with h = 0.16 µm and h1 = 0.4 µm and the SiGe-BiCMOS S-CPW with h = 0.4 µm and
h1 = 0.62 µm where all the metal layers above metal-1 are stacked. The floating shield strips
are 1 µm wide spaced 1 µm apart. It is clear from Fig. 3.20a that more energy is dissipated in
the conductive substrate, as QGC in SiGe-BiCMOS is smaller in all cases even though more
conductive metal shield layers are used [30]. The S-CPW in SiGe-BiCMOS with h = 0.4 µm
and h1 = 0.62 µm has a higher QGC than that with h = 6 µm and h1 = 3.03 µm, because
the shunt capacitance increases more rapidly than the shunt conductance. The advantage of
lower losses from an insulating substrate is suppressed when QGC ≫QRL because Q is then
dominated by QRL . With exactly the same physical layout (h = 1.5 µm and h1 = 5.53 µm)
and metal layer properties, the S-CPW in CMOS-SOI has Q factor of 32.5 at 60 GHz vs. 30
in SiGe-BiCMOS.
The thick top copper layer in SiGe-BiCMOS leads to a higher QRL than CMOS-SOI when the
shield is kept more than 3 µm from the substrate. Fig. 3.21 shows the effective permittivity of
the S-CPWs in both technologies. It is observed that εef f from the S-CPW with h = 0.16 µm
and h1 = 0.4 µm in CMOS-SOI doubles the maximum εef f in SiGe-BiCMOS (i.e., h = 0.4 µm
and h1 = 0.62 µm). Recall that the effective permittivity increases with decreasing h. Thus,
the slow-wave transmission lines in CMOS-SOI exhibit a relatively larger εef f because the
intermetal dielectric is thinner compared to the SiGe-BiCMOS technology used in this work.
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
Q-factor of the shunt GC section, Q
GC
78
SiGe-BiCMOS
104
CMOS-SOI
h = 0.6
h = 0.16
m, h
1
= 0.4
m, h
1
= 1.88
m
m
103
m, h
h = 0.98
= 1.5
m
= 3.03
m
1
102
h = 1.5
m, h
1
= 5.49
h = 0.4
101
m
m, h
1
= 0.62
m
h = 6
40
50
m, h
1
60
70
80
Frequency, in GHz
a) Quality factor of the shunt GC section
SiGe-BiCMOS
40
RL
Q-factor of the series RL section, Q
CMOS-SOI
h = 0.6
m, h
1
h = 0.98
35
h = 1.5
h = 6
30
m, h
1
m, h
= 5.49
= 3.03
1
m, h
= 1.88
m
= 1.5
m
1
m
m
25
h = 0.16
15
10
m, h
h = 0.4
20
40
m, h
1
= 0.4
50
1
= 0.62
m
m
60
70
80
Frequency, in GHz
b) Quality factor of the series RL section
SiGe-BiCMOS
35
CMOS-SOI
Q-factor of the CPW
h = 0.6
h = 0.98
30
m, h
1
1
= 1.5
20
m, h
h = 0.4
40
50
m, h
1
m, h
1
m, h
= 0.62
m
= 5.49
1
h = 6
h = 0.16
= 1.88
m
h = 1.5
25
15
m, h
1
= 0.4
= 3.03
m
m
m
m
60
70
80
Frequency, in GHz
c) Overall quality factor of the CPW
Figure 3.20: Simulated Q factors of S-CPWs in SiGe-BiCMOS and CMOS-SOI technologies.
3.3. S-CPW-type Power Combiners
79
SiGe-BiCMOS
40
CMOS-SOI
Effective permittivity
35
h = 0.16
m, h
30
25
h = 0.6
m, h
1
= 1.88
m
m, h
h = 0.4
= 0.4
m
= 0.62
m
= 1.5
m
1
1
20
h = 0.98
15
m, h
1
10
h = 1.5
5
0
m, h
1
= 5.49
m
h = 6
40
50
m, h
60
1
70
= 3.03
m
80
Frequency, in GHz
Figure 3.21: Simulated effective permittivity of S-CPWs in SiGe-BiCMOS and CMOS-SOI.
In addition, the metal thickness of the CPW conductors in the CMOS-SOI metal stack
is thinner. Thus, it suffers less from the negative magnetic coupling for a given groundsignal gap (dGS ), thereby having a larger series inductance than the SiGe-BiCMOS S-CPW.
Therefore, when a small h (e.g., < 0.5 µm in the simulations) suppresses the difference in
metal ohmic losses due to current crowding in the bottom plane of the CPW conductors,
the QRL of the S-CPW in CMOS-SOI becomes larger than that in SiGe-BiCMOS because
of the larger series inductance per unit length.
The insulating substrate and the strong slow-wave effect combine to give a larger overall Q
factor for the S-CPWs in CMOS-SOI, as shown in Fig. 3.20c. The exception is the S-CPW
with h = 1.5 µm and h1 = 5.49 µm in SiGe-BiCMOS. It has a comparable Q factor but
consumes 41% more chip area for a λ/4 resonator compared to the S-CPW in CMOS-SOI
with h = 0.6 µm and h1 = 1.88 µm. The trade-off between slowing factor and Q factor is
stronger in SiGe-BiCMOS than in CMOS-SOI. For example, the S-CPW with h = 0.16 µm
√
and h1 = 0.4 µm in CMOS-SOI exhibits the largest slowing factor (i.e., 32 = 5.65) and
Q factor is above 20 from 47 GHz to 80 GHz (see Fig. 3.20c), giving a good compromise
between chip area and losses. Moreover, EM simulation predicts that insertion loss of S-CPW
combiners in CMOS-SOI is less than 0.6 dB in the 60 GHz band. Thus, the CMOS-SOI
backend is more favorable than the 130 nm SiGe-BiCMOS for the transmission-line-type
combiner designed in this work. Note that a more comprehensive comparison between SCPWs including the influence from the floating shield strips can be carried out using a
physical-based equivalent circuit model, e.g., the RLRC model in [30].
Unlike the transformer combiners described in Section 3.2, the fully-symmetric S-CPW combiner (see Fig. 3.19a) guarantees excellent port-to-port impedance uniformity. The outputs
80
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
Table 3.2: 60 GHz CMOS-SOI S-CPW combiner prototypes.
Prototype
Ws (µm)
dSS (µm)
dGS (µm)
SC1
4.4
2
100
SC2
SC3
SC4
C5
C6
SC7
SC8
SC9
SC10
S-CPW
4.4
4.4
4.4
4.4
6.5
6.5
6.5
6.5
6.5
6.5
2
2
2
2
2
2
2
2
2
2
100
30
100
100
20
20
20
20
20
20
h (µm)
h1 (µm)
0.16
0.61
-
-
0.16
0.61
Shield (µm)
Grounded shield
Wsh = 2, Ssh = 1
Wsh = 2, Ssh = 1
Wsh = 2, Ssh = 1
Wsh = 1, Ssh = 1
No shield
No shield
Wsh = 1, Ssh = 4
Wsh = 1, Ssh = 2
Wsh = 1, Ssh = 1
Wsh = 2, Ssh = 1
Wsh = 2, Ssh = 1
of two or more 2-way S-CPW combiners could be connected in parallel to extend the number
of PA cells combined. For example, two S-CPW combiners can share one ground conductor
in the center and form a G-S-S-G-S-S-G configuration for 4-way combining.
3.3.3
Prototypes and Characterization
The impedance transformation ratio of a S-CPW combiner depends upon WS , WG , dSS ,
dGS , h, h1 , Ssh and Wsh (see Figs. 3.3 and 3.19a). Each path sees an input impedance of
Zo2 /(2 × ZL ) (see Fig. 3.19b), where Zo is the characteristic impedance of one S-CPW path,
and ZL is the load impedance (e.g., a 50 Ω antenna). A targeted characteristic impedance
of 50 Ω was selected for the S-CPW combiners, which transforms the 50 Ω load to 25 Ω.
Two groups of S-CPW combiners operating in the 60 GHz band were fabricated in the 65 nm
CMOS-SOI technology. One group has a signal width of 4.4 µm with different ground-signal
gaps and shielding types. The other group, with a fixed signal width of 6.5 µm, investigates
the influence of shield density on S-CPW combiner performance. All of the combiners use
a metal stack from AP to metal 2 as the CPW conductors, and metal 1 as the floating
shield. Table 3.2 lists the physical parameters of the S-CPW combiner prototypes. Floatingshielded combiners SC2, SC3 and SC4 have different ground-signal gaps (i.e., dGS = 30 µm
for SC3 vs. 100 µm for SC2 and SC4). Combiner SC1 designed with an explicitly-grounded
shield, and C5 and C6 without shielding are included for benchmarking and comparison.
A floating-shielded CPW with one signal conductor (i.e., the last prototype in Table 3.2)
is also implemented in order to verify the increase in slowing factor via the in-phase signal
coupling of the 2-way S-CPW combiner. All combiners are approximately 150 µm long and
consume about the same chip area (i.e., ∼ 490×350 µm2 ). A 500 µm long S-CPW combiner
with the same physical parameters as SC10 in Table 3.2 was implemented in IBM’s 90 nm
SiGe-BiCMOS technology, and its performance is compared with the CMOS-SOI prototypes.
Fig. 3.22 shows photomicrographs of all of the CMOS-SOI prototypes. The two combiner
inputs (i.e., S1 and S2 in Fig. 3.19a) are shorted together to form a 2-port network for
3.3. S-CPW-type Power Combiners
81
a) SC1
b) SC2
c) SC3
d) SC4
e) SC5
f) SC6
g) SC7
h) SC8
i) SC9
j) SC10
k) SC11
Figure 3.22: Photomicrographs of the S-CPW combiner prototypes implemented in 65 nm
CMOS-SOI (listed in Table 3.2).
82
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
Simulation
SC2
Measurement
C5
-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2
C5
SC3
SC2
SC3
S11 : 50-62 GHz
S21 : 50-62 GHz
Figure 3.23: Measured and simulated S11 and S21 of the S-CPW combiners SC2, SC3 and
C5 in Table 3.2 (note S22 = S11 , and S12 = S21 ).
Characteristic impedance, in Ohm
26
SC4
24
SC2
SC3
22
SC1
20
SC8
18
50
52
54
56
58
60
62
Frequency, in GHz
Figure 3.24: Measured characteristic impedance of the S-CPW prototypes.
measurement and characterization. These combiner inputs would also be driven in-phase by
amplifier cells when used in a PA application.
The measured S-parameters for combiners SC2, SC3 and C5 across 50–62 GHz are compared
with simulation in Fig. 3.23. Data for the 3 combiners are displayed on the same Smith chart
for clarity, and excellent agreement is seen between the measurements and simulations for
all of the prototypes. Ripples observed in the measured data arise from the limited dynamic
range of the network analyzer and losses in the measurement setup (e.g., cables, connectors
and probes).
The characteristic impedance (Zo ), attenuation coefficient (α), effective permittivity (εef f ),
and quality factor over the frequency range from 50–62 GHz were determined from measured
3.3. S-CPW-type Power Combiners
83
80
Effective permittivity
SC10
60
S-CPW
40
SC10 in BiCMOS (sim.)
20
C6
0
20
30
40
50
60
70
Frequency, in GHz
Figure 3.25: Measured effective permittivity of the SC10, C6 and S-CPW prototypes.
160
Effective permittivity
SC1
120
SC2
SC4
80
SC3
SC7
40
SC8
0
50
52
54
56
58
60
62
Frequency, in GHz
Figure 3.26: Measured effective permittivity of the prototypes SC1–SC4, SC7 and SC8.
S-parameter data. The TRL procedure was used to de-embed the frequency-dependent behavior of test pads and the interconnect parasitics of the test structure [26]. The measured
Zo for S-CPW combiners SC1–SC4 and SC8 is compared in Fig. 3.24. Note that since the
two inputs of each combiner are shorted, Zo is one-half of that seen at each input separately.
The characteristic impedance varies from highest (SC4) to lowest (SC1) for the three S-CPW
combiners with 100 µm dGS (i.e., SC1, SC2 and SC4) because of the difference in loading from
the shield on the transmission line in each case. As the capacitive loading from the shield
decreases from SC1 to SC2 and to SC4, the characteristic impedance increases accordingly.
84
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
40
80
SC10
60
35
SC8
SC7
40
30
25
20
Quality factor at 60 GHz
Effective permittivity
SC9
C6
0
0.00
0.15
0.30
0.45
0.60
20
0.75
Shield density
Figure 3.27: Measured effective permittivity and simulated Q factor versus shield density.
Combiner SC3 has a smaller Zo than SC2 or SC4, because its 30 µm ground-signal gap (vs.
100 µm for SC2 and SC4) reduces the inductance per unit length of the S-CPW. Despite
the lower shield density, combiner SC8 has the lowest Zo due to the larger conductor width
and narrower ground-signal gap. By contrast, the prototype C5 has the highest Zo of 110 Ω,
as no shield is used.
Fig. 3.25 compares the measured effective relative permittivity, εef f , of prototypes C6, SC10
and S-CPW (from Table 3.2) across 50–62 GHz. Note that these 3 prototypes have the same
design parameters except for the difference in shielding. In addition, the S-CPW prototype
is a floating shielded CPW with only one input (i.e., not a 2-way combiner). The slow-wave
effect created by adding a floating shield increases εef f from 6 to about 45 (i.e., C6 vs. S-CPW
in Fig. 3.25). The in-phase coupling between the 2 signal paths in a S-CPW combiner further
increases εef f to 67 (i.e., SC6), which effectively reduces the λ/4 length by a factor of 3.34
√ √
(i.e., 67/ 6), compared to the unshielded combiner C6. Measured εef f across 20–30 GHz
for the 500 µm long, SiGe-BiCMOS version of SC10 is included in Fig. 3.25 for comparison.
The CMOS-SOI combiner has an εef f that is twice the value realized in SiGe-BiCMOS.
This is consistent with the simulation results in Section 3.3.2. The reduced thicknesses of
the intermetal dielectric and CPW conductors from metal stacking in CMOS-SOI lead to
a larger shunt capacitance and series inductance (in that the signal and ground magnetic
coupling coefficient is smaller), respectively.
The relative effective permittivity of the prototypes SC1–SC4, SC7 and SC8 measured across
50–62 GHz is shown in Fig. 3.26. Combiner SC1 has the highest εef f of 141, which results from
capacitance added by the explicitly-grounded shield. The combiners with floating shields
realize comparable εef f (i.e., as high as 116) with no explicit ground connectionq for their
shields. The electrical wavelength for the shielded combiners is reduced by 4.4 = 116/6 at
3.3. S-CPW-type Power Combiners
85
3.0
3.0
Attenuation, in dB/mm
2.5
Attenuation
2.5
2.0
2.0
1.5
1.5
1.0
1.0
Insertion loss, in dB
SC1
SC2
Insertion loss
0.5
0.5
0.0
50
52
54
56
58
60
0.0
62
Frequency, in GHz
a) Simulation
3.0
3.0
SC1
SC2
2.5
Attenuation
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
Insertion loss, in dB
Attenuation, in dB/mm
2.5
Insertion loss
0.0
50
52
54
56
58
60
0.0
62
Frequency, in GHz
b) Measurement
Figure 3.28: Attenuation and insertion loss of the S-CPW combiners SC1 and SC2.
60 GHz compared to the unshielded reference design, C5, which has a much lower εef f of 6.
Compared to SC1–SC4, combiners SC7 and SC8 show lower εef f despite the larger signal
width (i.e., 6.5 µm vs. 4.4 µm). This is because the decrease in inductance per unit length
via a narrower ground-signal gap is larger than the increase in capacitance.
The measured εef f and simulated Q factor of the S-CPW combiners are plotted as a function
of shield density in Fig. 3.27. It is expected that εef f increases with increasing shield density.
A denser shielding increases current crowding at the bottom side of the signal conductor,
leading to an increase in the resistive losses. Moreover, losses contributed by the floating
86
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
80
C5
Quality factor
70
60
50
SC4
40
SC1
SC2
SC7
30
SC9
20
SC3
50
52
54
56
58
60
62
Frequency, in GHz
Figure 3.29: Simulated Q factor of the CMOS-SOI combiner prototypes.
shield metal strips also increase with the increasing capacitance between the CPW and shield
[30], lowering the Q factor with the increasing shield density (see Fig. 3.27). In addition, SCPW combiners tend to resonate above 100 GHz due to the capacitive loading from the
narrow distance between the CPW conductors and the shield (i.e., h in Fig. 3.19a), and
the attenuation climbs rapidly as resonance is approached [31]. Adjusting the shield density
(e.g., < 70%) and the distance between the shield fingers and the substrate increases εef f
and the wavelength reduction factor, without significantly compromising the Q factor. The
Q factor at 60 GHz in Fig. 3.27 remains above 20 for all of the prototypes from simulation.
The simulated and measured attenuation coefficient (α) and insertion loss for combiners SC1
and SC2 are shown in Fig. 3.28. The measured α is sensitive to uncertainties (± 0.15 dB)
and noise in the S-parameter data. Combiners SC2 and SC4 have lower α compared to SC1
at 60 GHz, as the grounded metal-1 shield of SC1 introduces extra losses. The prototype SC3
is considerably narrower in dimension (i.e., dGS = 30 µm for SC3 vs. 100 µm for combiners
SC1, SC2 and SC4) at the expense of only a small increase in α (∼ 0.1 dB per λ/4 compared
to SC4). Measured insertion loss is < 0.6 dB at 60 GHz for all of the 150 µm long S-CPW
combiner prototypes.
The good agreement observed between measurement and simulation for the S-CPW prototypes again justifies the use of EM simulation to compare the prototypes further. Fig. 3.29
shows the simulated Q factor across 50–62 GHz. As expected, shielding does not improve
the Q factor for combiners implemented on an insulating substrate. However, the unshielded
combiner C5 does not support slow-wave propagation, so its physical length is greater than
the S-CPW combiners for the same electrical length (note that a quarter-wavelength for
C5 is 506 µm vs. approximately 110 µm for the shielded S-CPW combiners in Table 3.2).
Combiner SC1 has a smaller Q factor than SC2 and SC4 because losses in the metal-1 shield
3.3. S-CPW-type Power Combiners
87
Table 3.3: Performance summary of the S-CPW combiners at 60 GHz.
SC1
SC2
SC3
SC4
C5
C6
SC7
SC8
SC9
SC10
CPW
εef f
sim. meas.
154.3 140.1
116.2 115.1
64.7
60.2
101.0 108.4
5.9
6.1
5.4
6
31.5
31
45
42
61
54
69
65
46.5
42
α (dB/(λ/4))
sim. meas.
0.21
0.22
0.19
0.20
0.27
0.25
0.15
0.12
0.09
0.17
0.17
0.50
0.20
0.30
0.21
0.30
0.21
0.20
0.28
0.30
0.32
0.40
Q
sim.
32.4
35.8
25.4
46.7
73.2
38.0
31.4
31.6
30.6
23.7
21.6
Width (µm)
Area (µm2 )
250
37500
110
16500
250
37500
95
15675
86.5
14272.5
Length (µm)
150
165
are incurred in the current return loop. Prototypes SC2 and SC4 have a Q factor above 35
and wavelength reduction factor greater than 4 at 60 GHz. Combiner SC3 has the lowest
Q factor, likely due to current crowding caused by the relatively small coplanar conductor
gap (i.e., smallest dGS ). The 100 µm gap in SC2 and SC4 mitigates crowding and allows
current to spread across the (more conductive) top metal layers, resulting in lower losses.
By contrast, combiners SC7 and SC9 have a comparable ground-signal gap with SC3, but a
higher Q factor. This is because the resistive losses are reduced by the larger signal width
(6.5 µm vs. 4.4 µm).
Measured and simulated parameters for the S-CPW combiners at 60 GHz are listed in
Table 3.3 for comparison. Attenuation as low as ∼ 0.2 dB is reached for the 2SE:1 S-CPW
combiners implemented in CMOS-SOI (e.g., SC1), which clearly demonstrates their potential
for excellent performance in a mm-wave PA despite the relatively thin metals used in the
SOI technology backend. Wavelength reduction from slow-wave propagation supports the
design of compact transmission line combiners at mm-wave frequencies (e.g., 150–165 µm
long and 95–250 µm wide at 60 GHz in Table 3.3).
3.3.4
Lumped-element Model
Similar to the transformer combiner model, a number of RLCG sub-circuits in cascade are
required to model the distributed effects in a slow-wave transmission line accurately [12]
[29]. Simulation predicts that 5 sub-circuits in cascade are sufficient to model the S-CPW
combiners across 55–65 GHz with very good accuracy. Fig. 3.30 shows the simplified lumpedelement model of the S-CPW combiner, where N is the number of cascaded RLGC sections.
Fig. 3.31 plots the measured S-parameters of combiner SC3 and the simulated results from
a 5-section equivalent circuit model across 50–62 GHz. Excellent agreement is observed
across the entire range, verifying the accuracy of the extracted model. Table 3.4 compares
the transmission line parameters extracted from measurements for combiner SC3 with the
equivalent circuit model at 60 GHz. The percent difference between measurement and model
for all of the parameters listed in the table is less than 2%.
88
Chapter 3. On-chip mm-Wave Power Combiners and Splitters
Figure 3.30: Simplified lumped-element model of the S-CPW combiner.
-2.0
Model
Meas.
, in dB
-2.5
S
-3.0
S
11
and S
21
21
-3.5
S
11
-4.0
50
52
54
56
58
60
62
Frequency, in GHz
Figure 3.31: S-parameters of combiner SC3 from measurement and the lumped-element
model.
3.4
Summary
This chapter describes the design details and full characterization of two types of high-quality
mm-wave power combiners implemented in SiGe-BiCMOS and CMOS-SOI technologies. The
combiners developed in this work offer insertion losses ranging from 0.2 dB to 1 dB at 60 GHz,
excellent uniformity of the transformed impedances, and consume little chip area. The experimental results show that the transformer-type combiner performs best in the 130 nm SiGeBiCMOS technology with the thick metal option, while the transmission-line-type combiner
benefits from a technology backend with thin intermetal dielectric layers and a high resistivity substrate, such as the 65 nm CMOS-SOI technology. The compact, frequency-scalable,
4-way transformer combiners enable fully-monolithic mm-wave power amplifiers with up to
5.5 dB greater output power for wireless communication and radar/imaging applications.
Their application to mm-wave power-combining PA prototypes will be described in the next
two chapters.
References
89
Table 3.4: Measurement vs. model for S-CPW combiner SC3 at 60 GHz.
Z0 (Ω)
εef f
λ/4 (µm)
α (dB/mm)
α (dB/quarter-λ)
IL (dB)
Meas.
21.9
60.2
161.1
1.58
0.25
0.25
Model
21.8
61.3
159.7
1.54
0.246
0.30
Mismatch
< 0.5%
< 2%
< 1%
< 0.5%
< 0.5%
< 1%
References
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broadband distributed active transformer power amplifier in 90-nm CMOS process,” IEEE Transactions
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[25] Q. J. Gu, Z. W. Xu, and M. C. F. Chang, “Two-way current-combining W-band power amplifier in
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Chapter 4
Multi-stage and Output-combining Power Amplifier
Design
A multi-stage, multi-path, output-combining PA topology is desired at mm-wave frequencies
in order to realize sufficient RF power and gain when parasitic losses and on-chip interstage
coupling networks are considered. Active amplifier stages and passive matching networks
are the key building blocks. Chapter 3 addressed the design problems associated with onchip combining/splitting. This chapter continues with a study of active amplification stages.
The selection of amplifier topologies is justified by comparing their power gain, breakdown
behavior, thermal and electrical stability, and large-signal behavior. Design details of the
power-combining, SiGe-BiCMOS and CMOS-SOI PA prototypes in the 60 and 77 GHz bands
complete this chapter.
4.1
Single-stage Topology Comparison
Fig. 4.1 shows simplified schematics of several commonly used single-stage amplifier topologies, which are connected in common-emitter (CE), common-base (CB) and cascode configurations. The following subsections compare their performance in terms of power gain,
isolation across 40-100 GHz, breakdown voltage and large-signal behavior. Transistor Q1 in
the CE and cascode stages (see Figs. 4.1a and 4.1b) is voltage biased at the base by a series
resistance (RB ) of 1 kΩ, and its emitter is ideally grounded. The CB stage in Fig. 4.1c is
base biased via an ideal voltage source (i.e., forced-VBE ), and it is current biased at the
emitter by an ideal current source as in Fig. 4.1d. The bases of transistors Q1 in the two
CB configurations and Q2 in Fig. 4.1b are connected to AC ground. Inductance L1 and L2
are selected large enough to be considered as AC open circuits in band. Both the input and
output of all the circuits are connected to an AC voltage with 50 Ω source impedance and
AC-coupled via capacitors Cc1 and Cc2 , respectively. High-performance CBEB 0.27×10 µm2
NPN devices from STM’s 130 nm SiGe-BiCMOS technology [1] are used in the following
simulations. The transistors are biased near peak-fT from a 1.5 V supply for the CE and
voltage-biased CB stages. The CB stage in Fig. 4.1d operates from a 1.8 V supply because
0.3 V headroom is assumed for the biasing current source. A 2.3 V supply is used for the
cascode topology due to the extra voltage headroom required by the CE transistor Q1 in
series with the CB stage (see Fig. 4.1b).
91
92
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
a) CE stage
c) Voltage-biased CB stage (CB V)
b) Cascode stage
d) Current-biased CB stage (CB I)
Figure 4.1: Simplified schematics of the single-stage amplifier topologies.
4.1.1
Power Gain, Stability and Reverse Isolation
Fig. 4.2a compares the simulated maximum available and stable gains (MAG/MSG) for each
topology shown in Fig. 4.1 across 40–100 GHz (note that MAG equals MSG when the circuit
is potentially unstable). The CE and CB stages have comparable MSG, while the cascode
topology provides ∼ 10 dB higher power gain across 60–100 GHz because of its greater
output impedance (i.e., less parasitic loading).
Stability factors, k and B1f , are plotted in Figs. 4.2b and 4.2c, respectively. Note that for
unconditional stability it is required that k > 1 and B1f > 0. It is observed that the cascode
configuration is conditionally stable up to 92 GHz, compared to 54 GHz for the CE stage.
It is expected that a cascode stage with an excellent reverse isolation (see Fig. 4.2d) is more
stable, however, its larger power gain and greater output impedance mismatch to the 50 Ω
load degrade stability (see Eq. 2.1 in Chapter 2). Simulation predicts that the S22 of the
CE stage at 80 GHz is -11.1 dB vs. -0.7 dB of the cascode stage. The regime of conditional
4.1. Single-stage Topology Comparison
93
30
2.0
Cascode, MSG
k
1.5
MAG
20
MSG
15
CB_I/CB_V, MSG
Stability factor,
MAG/MSG, in dB
25
CE
1.0
CB_I/CB_V
0.5
0.0
Cascode
10
-0.5
CE, MAG
5
40
50
60
70
80
90
-1.0
100
40
50
60
70
a) MSG/MAG
90
100
b) Stability factor, k
-15
1.5
CE
CE
-20
1.2
CB_I/CB_V
, in dB
-25
-30
12
0.9
0.6
S
Stability factor, B1f
80
Frequency, in GHz
Frequency, in GHz
-35
Cascode
CB_I/CB_V
0.3
-40
Cascode
0.0
-45
40
50
60
70
80
Frequency, in GHz
c) Stability factor, B1f
90
100
40
50
60
70
80
90
100
Frequency, in GHz
d) Reverse isolation, S12
Figure 4.2: Simulated MAG/MSG, stability factors and reverse isolation of the amplifier
configurations in Fig. 4.1.
stability for the CB amplifier extends up to 170 GHz from simulation, which is well beyond
the desired operating frequency range (note that the targeted maximum operating frequency
in this work is ∼ 80 GHz for the E-band, wireless backhaul applications). Thus, additional
networks are needed in order to promote unconditional stability. Improved stability often
comes at the expense of power gain, voltage swing or power consumption (e.g., using resistive
loading [2] or RC compensation [3]), which will be discussed in Section 4.2.
Good reverse isolation is required for a PA in order to tolerate antenna impedance mismatch
and promote unconditional stability. Fig. 4.2d compares their reverse isolation, S12 , from
40 to 100 GHz. Note that parasitic coupling from layout interconnects which potentially
degrade S12 is not included in the simulation. The CE configuration suffers from feedback
via the base-collector capacitance, Cµ , leading to a reverse isolation of ∼ 20 dB across the
entire band. The relatively flat frequency dependence reveals that it is the capacitance ratio
of Cµ and Cπ which dominates the feedback at frequencies above 40 GHz. It appears that
there is no parasitic capacitance connecting the input and output of a CB stage. However,
the intrinsic and extrinsic base resistances (rbi and rbx ) form an R-C feedback path with
94
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
30
30
Vb range : 872 mV −− 960 mV
25
Collector current, in mA
Collector current, in mA
Vb range : 861 mV −− 936 mV
20
15
10
5
0
0
25
20
15
10
5
0.5
1
1.5
2
0
0
2.5
1
Collector−emitter voltage, in V
a) CE topology
4
30
Vb range : 852 mV −− 884 mV
IE range : 5 mA −− 15 mA
25
Collector current, in mA
Collector current, in mA
3
b) Cascode topology
30
20
15
10
5
0
0
2
Collector−emitter voltage, in V
25
20
15
10
5
0.5
1
1.5
2
2.5
0
0
1
Collector−emitter voltage, in V
c) Voltage-biased CB topology (CB V)
2
3
4
Collector−emitter voltage, in V
d) Current-biased CB topology (CB I)
Figure 4.3: Simulated collector I-V curves of the amplifier topologies in Fig. 4.1.
the parasitic capacitance. Another feedback path is via the transistor output impedance and
the impedance at the emitter terminal. The ratio of the 50 Ω source impedance to (roughly)
1/gm defines how much feedback current flows back towards the input. By contrast, the
cascode configuration suppresses the Miller effect and has a reverse isolation of better than
36 dB across 40–100 GHz. Despite the advantages in power gain and reverse isolation, the
cascode topology is unstable below 92 GHz, and requires a larger supply voltage (2.3 V vs.
1.5 V in this comparison).
4.1.2
Collector-Emitter Breakdown Voltage
Open-base, collector-emitter breakdown (BVCEO ) and open-emitter, collector-base breakdown voltages (BVCBO ) define a bipolar transistor’s terminal voltage limits, but BVCBO is
typically several volts higher than BVCEO [4]. The transistors used in the simulations have
BVCEO of 1.52 V [1]. Transistor Q1 in the CE stage in Fig. 4.1a has 1 kΩ DC resistance in
series with the base and 0 Ω with the emitter, which resembles more the open-base biased
4.1. Single-stage Topology Comparison
95
200
200
V range : 861 mV −− 936 mV
V range : 872 mV −− 960 mV
b
b
100
Base current, in uA
Base current, in uA
100
0
−100
−200
0
−100
−200
−300
0
0.5
1
1.5
2
−300
0
2.5
Collector−emitter voltage, in V
1
a) CE topology
3
4
b) Cascode topology
200
200
V range : 852 mV −− 884 mV
I range : 5 mA −− 15 mA
b
E
100
Base current, in uA
100
Base current, in uA
2
Collector−emitter voltage, in V
0
−100
−200
0
−100
−200
−300
0
0.5
1
1.5
2
Collector−emitter voltage, in V
c) Voltage-biased CB topology (CB V)
2.5
−300
0
1
2
3
4
Collector−emitter voltage, in V
d) Current-biased CB topology (CB I)
Figure 4.4: Simulated base I-V curves of the amplifier topologies in Fig. 4.1.
scenario. The CB stage in Fig. 4.1d has an open emitter at DC because it is biased by an
ideal current source. Note that the transistor Q2 in Fig. 4.1b is equivalent to a currentbiased CB configuration because its current is set by transistor Q1 . The forced-VBE biased
CB stage in Fig. 4.1c is different from the rest because both its base and emitter present 0 Ω
impedance at DC. Studies reveal that only the time-average (i.e., root mean squared) value
of the collector-emitter voltage should not exceed BVCEO [5]. However, the peak collectoremitter voltage can be as high as BVCBO for a properly-biased amplifier topology [5] [6],
which is validated in the following simulations.
Figs. 4.3 and 4.4 show the respective collector and base currents vs. collector-emitter voltage
(i.e., IC -VCE and IB -VCE curves) of the output transistors in Fig. 4.1 (i.e., Q2 for the cascode
topology) at different biasing conditions. The base voltage (i.e., Vb ) of transistor Q1 is swept
in each case, except for the amplifier in Fig. 4.1d where the emitter current (i.e., IE ) is
varied. The range of parameter variation is also annotated on Figs. 4.3 and 4.4. The collectoremitter breakdown voltage of the HBT in the cascode and current-biased CB configurations
is ∼ 1.5 V greater than when connected common-emitter (compare Figs. 4.3a vs. 4.3b and
96
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
Collector current, in mA
50
40
10
200
30
500
50
20
V
CE
10
0
1
2
~ 3 V
3
4
5
Collector-emitter voltage, in V
a) Simplified schematic
b) IC vs. VCE with Rsh as a parameter
Figure 4.5: Simulated IC -VCE curve of a CB stage as a function of the emitter current source
output resistance, Rsh .
4.3d). Excess base current generated by impact ionization in the collector-base region (i.e.,
IB < 0 when VCE > 2 V) for the CB transistor in Figs. 4.4b and 4.4d is shunted to ground.
Hence, this current does not increase the base-emitter bias voltage or the collector current,
and the transistor can operate reliably above BVCEO (e.g., > 3 V). Thus, a properly driven
CB stage can operate with a collector-emitter voltage near BVCBO without a degradation in
reliability [7] [8]. However, for the CE topology in Fig. 4.1a, the current generated by impact
ionization sees a 1 kΩ impedance in series with the base to ground due to biasing resistor
RB . It causes the current to flow towards the device (i.e., IB remains above 0 in Fig. 4.4a),
leading to an increase in base and collector currents (see Figs. 4.3a and 4.4a) and eventually
device failure at VCE above 2 V.
Although the circuit in Fig. 4.1c is also CB configured for AC signals, inductor L2 does not
provide any local negative feedback at DC (i.e., emitter degeneration). It exhibits poorer
IC -VCE behavior than a CE stage (see Figs. 4.3c vs. 4.3a). The degradation is caused by the
self-heating effect, which is suppressed by the series base resistor RB in the CE configuration
(via negative feedback), and will be discussed in more detail in the next subsection. At
relatively low collector currents (e.g., 5 mA in Fig. 4.3c), the influence of self-heating is
less prominent, and therefore the collector-emitter voltage range can be extended by simply
grounding the base terminal directly. The corresponding negative base current observed
in Fig. 4.4c reveals that the impact ionization current is flowing out of the base to the
ground. However, as the biasing current increases, the junction temperature also increases
dramatically, which reduces the base-emitter junction voltage (e.g., -2 mV/◦ C [9]). The
device then tends to thermal runaway, leading to a sharp increase in both base and collector
currents when forced-VBE biased (see Figs. 4.3c and 4.4c). Hence, there is no breakdown
voltage improvement observed for the amplifier in Fig. 4.1c.
4.1. Single-stage Topology Comparison
a) Single-ended
97
b) Differential
Figure 4.6: Schematics of a single-stage amplifier with base and emitter ballasting.
The current-biased CB stage in Fig. 4.1d is driven by an ideal current source at the emitter
(i.e., maximum negative feedback), however, a practical current source has a finite output
resistance. Fig. 4.5 plots its IC -VCE curves for different current source output resistances,
Rsh . It is observed that the collector-emitter breakdown voltage is ∼ 3 V for Rsh above 50 Ω,
compared to less than 2 V when Rsh = 0 Ω.
4.1.3
Temperature Dependence
The substrate and chip temperatures rise because power is dissipated by transistors as heat.
It affects device behavior partly because of the DC current flowing in the transistor itself (i.e.,
self-heating) and partly due to the effect of heat generated by the surrounding circuitry (i.e.,
global heating). The current gain of a SiGe bipolar transistor has a negative (or weak [10])
temperature dependence [11]. Thus, the collector current decreases with (or is insensitive
to) increasing temperature when DC current is forced into the base, which promotes thermal stability. However, as described in Section 4.1.2, open-base biasing strictly confines the
collector-emitter breakdown voltage to less than BVCEO , which limits the maximum voltage
swing. Biasing the base with a voltage source maximizes the collector-emitter voltage swing
as VCE can now rise above BVCEO , but the transistor is subject to thermal instability because the voltage drop across the internal base-emitter junction has a negative temperature
coefficient [12]. As the junction temperature increases, the collector current increases, which
in turn raises the transistor temperature further, thereby creating an unstable operating
point.
As shown in Fig. 4.3c for a forced-VBE topology, self-heating causes the collector current
to increase faster than shown in Fig. 4.3a. A ballasting resistor in series with the base
or the emitter suppresses the increase in base-emitter voltage via negative feedback [13].
However, for modern HBTs operating at a high current density (e.g., 20 mA/µm2 for peakfT ), base ballasting resistor alone is insufficient to guarantee thermal stability. Moreover,
98
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
100
R = 0, R
B
=0
gnd
R = 1kΩ, R
Collector current, in mA
B
80
gnd
R = 0, R
B
gnd
= 8Ω
R = 400Ω, R
B
=0
gnd
o
100 C
75oC
o
50 C
= 8Ω
60
25oC
40
20
0
0
0.5
1
1.5
2
2.5
3
Collector−emitter voltage, in V
Figure 4.7: Simulated I-V curves of the single-ended amplifier in Fig. 4.6a.
global heating limits the effectiveness of the ballasting, which is a localized feedback. Also,
base ballasting reduces the collector-emitter breakdown voltage as discussed in Section 4.1.2.
Thus, an emitter ballasting resistor is a better and more effective way of ensuring thermal
stability locally [14]. However, the voltage headroom is reduced due to the voltage drop across
the emitter ballasting resistor. Thus, a proper combination of base and emitter ballasting
can potentially provide the best thermal stability. Fig. 4.6a shows the schematic of a singleended, forced-VBE biased stage with base and emitter ballasting resistors (i.e., RB and Rgnd ).
Apart from the DC voltage drops across the ballasting resistors, AC performance in either
CE or CB configurations (e.g., power gain) is also degraded by these resistors for the singleended circuit of Fig. 4.6a. The problem is overcome when the device is driven differentially,
as shown for a CB configuration in Fig. 4.6b. A virtual ground is created at the center tap
of the transformer, which eliminates the deleterious influence of any resistance (e.g., Rgnd )
in the path of the AC signals. A virtual ground also exists at the common-base node of the
two transistors in Fig. 4.6b, leading to 0 Ω base impedance for the differential AC signals.
The simulated IC -VCE curves at different substrate temperatures and ballasting conditions
for the single-ended amplifier in Fig. 4.6a are compared in Fig. 4.7. A good compromise for
thermal stability is reached with a combination of base and emitter ballasting resistors, i.e.,
when Rgnd = 8 Ω and RB = 400 Ω. Self- and global heatings cause the collector current
to change dramatically with temperature (i.e., when Rgnd = 0 and RB = 0). Applying only
base (i.e., Rgnd = 0) or emitter (i.e., RB = 0) ballasting significantly improves the IC -VCE
behavior. The collector-emitter breakdown voltage is indeed extended when emitter rather
than base ballasting is used (i.e., Rgnd = 8 Ω and RB = 0 Ω), but the current variation across
different temperatures is larger than that when both ballasting resistors are present. Only
99
15
25
10
20
Power gain, in dB
Output power, in dBm
4.1. Single-stage Topology Comparison
5
0
CE
-5
15
10
CE
5
Cascode
CB_I
CB_I
0
-10
-20
Cascode
CB_V_ballasting
CB_V_ballasting
-15
-10
-5
0
5
-20
10
-15
Input power, in dBm
a) RF power transfer
CE
Cascode
Cascode
Power-added efficiency, in %
Collector efficiency, in %
0
5
10
5
10
40
CE
CB_V_ballasting
CB_I
40
30
20
10
0
-20
-5
b) Power gain
60
50
-10
Input power, in dBm
CB_V_ballasting
30
CB_I
20
10
0
-15
-10
-5
0
5
10
Input power, in dBm
c) Collector efficiency
-20
-15
-10
-5
0
Input power, in dBm
d) PAE
Figure 4.8: Comparison of simulated large-signal behavior for the topologies in Fig. 4.1 at
60 GHz.
using emitter ballasting to maintain the same current variation, the resistance required is
doubled from simulation, which reduces the collector-emitter voltage swing for a given supply
voltage. Base ballasting trades collector-emitter breakdown voltage for a smaller current
change with temperature and lowers the value required for Rgnd and the DC voltage drop
across it. Thermal stability can also be guaranteed by a temperature independent current
biasing scheme (i.e., constant current [15] [16]). However, ballasting using base and emitter
resistors is chosen in this work for its simplicity.
4.1.4
Output Power and Efficiency
Fig. 4.8 compares the large-signal behavior of the single-stage amplifiers at 60 GHz. All
of the topologies are biased at 15 mA DC current, and drive the optimal load impedances
for maximum RF power output derived from load-pull simulations. The input is impedance
matched to 50 Ω via a L-C network. The CE stage operates from a 1.3 V supply. Base and
emitter ballasting resistors of 250 Ω and 10 Ω are added to the forced-VBE CB stage for
100
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
thermal stability. Its supply voltage is increased to 1.95 V. Both the cascode and currentbiased CB configurations are biased at 2.3 V because of the extra voltage headroom required
by the CE transistor and the current source, respectively. Thus, their optimal load resistance
at resonance is larger than that of the CE stage (i.e., ∼110 Ω vs. 70 Ω).
The CE stage produces (maximum) 11 dBm saturated output power, as opposed to ∼ 12 dBm
from the other three topologies (see Fig. 4.8a), which makes it least favorable as the PA
output stage from the power output perspective. This trend is consistent with the breakdown
voltage observations from Fig. 4.3a. The collector-emitter breakdown voltage of the HBT
in the common-base configuration is greater than when connected common-emitter, giving
a larger output voltage swing and greater output power from the PA. Fig. 4.8b illustrates
the transducer power gain, which equals the operating gain in this case because the input
is impedance matched. The cascode stage exhibits the greatest power gain; ∼ 8 dB higher
than the rest at low input power, because power lost to the transistor output impedance is
reduced, and both transistors in the cascode provide power amplification. The power gain
shown in Fig. 4.8b (under load-line matching) is always smaller than the MAG in Fig. 4.2
for the conjugately-matched condition, and also compresses as input power level increases.
The CE stage has a lower -1 dB compression point at the output than the two CB stages
because its gain compresses at a lower input power level (see Fig. 4.8b).
Fig. 4.8c compares their collector efficiency, ηc = Pout /PDC , where Pout and PDC are the
RF output power and DC power consumption, respectively. The voltage-biased CB topology
has the highest collector efficiency. Biased at the same supply, the CE configuration shows
a collector efficiency lower than that of the voltage-biased CB amplifier, in that the base
series resistor (RB ) limits the collector-emitter voltage to less than BVCEO , resulting in a
lower Pout . The cascode and current-biased CB stages have a lower efficiency because of the
higher supply voltage.
Fig. 4.8d illustrates the influence of power gain on amplifier efficiency by comparing their
PAEs. At peak-PAE, the peak voltage swing of the voltage-biased CB and the CE topologies
is 1.78 V and 1.07 V from simulation, respectively. The voltage-biased CB topology exhibits
the highest PAE with a peak value of 38% at an input power of 5 dBm. The current-biased
CB and the cascode topologies demonstrate comparable power output, but their PAE is 5%
lower due to the voltage headroom required by current source IE in Fig. 4.1d (CB) and
the transistor Q1 in Fig. 4.1b (Cascode). However, it is observed that the cascode topology
achieves a PAE above 32%, even at an input power level below 0 dBm, which demonstrates
the advantage of a higher power gain that relaxes PA driver requirements. At peak-PAE the
power gain is 7.5 dB for the CB topologies, and 13 dB for the cascode amplifier. Thus, the
collector efficiency is reduced by 18% in the CE configuration and just 5% when configured
as a cascode. Moreover, from the analysis of a multi-stage PA described in Chapter 2, the
higher power gain supplied by a cascode output stage can suppress PAE degradation from
the preceding driver stages, leading to a higher PAE overall. Hence, the voltage-biased CB
and the cascode amplifiers are preferred topologies for a mm-wave PA design when RF power
output and PAE are considered.
4.2. Electrical Stability
4.1.5
101
Summary
It is concluded from the previous sections of this chapter that the voltage-biased CB or the
cascode topologies should be selected for a mm-wave PA design because of their superior
large-signal behavior. Base and emitter ballastings guarantee thermal stability for both configurations. However, they still require additional design effort to promote electrical stability,
because the regime of conditional stability tends to extend well beyond the desired operating frequency range (see Figs. 4.2b and 4.2c). Although the cascode configuration achieves
excellent reverse isolation, parasitics from the physical layouts could potentially cause undesired feedback and performance degradation. Therefore, output-to-input feedback from
interconnect wiring parasitics must be compensated in order to promote stability and good
input-to-output isolation of the PA. The techniques used to achieve better stability in this
work are discussed in the next section.
4.2
Electrical Stability
The large emitter area transistors in a PA consist generally of multiple, shorter emitter length
devices connected in parallel, so it is important that bias currents flowing in all transistors in
the same stage are balanced. Otherwise, local heating caused by current hogging or thermal
runaway may occur, degrading the circuit performance or ultimately destroying the active
devices [14] [17].
To ensure bias and thermal stability, parallel-connected transistors of equal area are laid out
physically close to each other. The physical layout minimizes any differences in interconnect
lengths, and requires a stack of metals (1 to 4) for the collector and emitter interconnects
in order to meet the reliability guidelines for electromigration in the 130 nm BiCMOS technology. However, parasitic collector-to-emitter capacitance from the interconnect introduces
positive feedback between the output and input of a CB stage, degrading reverse isolation and stability and (potentially) narrowing the bandwidth. This section elaborates on
frequency compensation of the CB stage, and parasitic reduction and equalization in the
physical layouts that do not degrade performance significantly.
4.2.1
Neutralization
Fig. 4.9a shows the simplified schematic of a CB topology with parasitic collector-emitter
coupling capacitor due to metal stack, Cp , and a parallel R-L load. Its small-signal equivalent
circuit model is given in Fig. 4.9b. The voltage gain at resonance (i.e., ω0 ) in the frequency
(i.e., s) domain is derived as
vout
sLgm R + s2 Cp LR
= 2
|s=jω0 = gm R + sCp R,
vin
s RL(Cp + Cµ + Cc + sL + R)
(4.1)
where gm and C are the small-signal transistor parameters, Cc represents the parasitic
collector-to-substrate capacitance, and R is the parallel equivalent resistance of the load
102
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
a) Single-ended CB topology
b) Small-signal equivalent circuit model
Figure 4.9: Simplified schematic and small-signal equivalent circuit model of a CB stage.
seen by the transistor at resonance (note than ro is neglected for simplicity). The second
term in Eq. 4.1 leads to increasing voltage gain with frequency, which can ultimately result
in instability and oscillation. The feedback from the output to input via Cp when the input
is shorted to ground via the source impedance (ZS ) is given by
sCp (rπ ||Zs )
vout
| Cp =
,
vin
1 + s(rπ ||ZS )(Cπ + Cp )
(4.2)
where Cπ and rπ are the small-signal transistor parameters. The feedback is positive and
increases with increasing frequency. At frequencies much greater than 1/[2π(rπ ||ZS )(Cπ +Cp )]
(e.g., in the 60 GHz band), Eq. 4.2 can be approximated by Cp /(Cp +Cπ ). Thus, the feedback
becomes positive-real in the high frequency regime and increases with increasing Cp . It fosters
instability at higher frequencies.
Fig. 4.10a shows the simulated S21 and S12 for the circuit of Fig. 4.9a across 40–80 GHz
for 3 different Cp values. Fig. 4.10b shows the Edwards-Sinsky stability parameter µ [18]. µ
represents the distance from the center of the Smith Chart to the nearest point of instability,
and must be larger than 1 for unconditional stability. A 0.27×20 µm2 HBT is biased at
peak-fT in the simulations. The input is impedance matched to 50 Ω with a simple L-section
network, while a 50 Ω resistor (R in Fig. 4.9a) sets the load impedance when the output
is tuned to 60 GHz (L = 120 pH). Peak-S21 increases by 2 dB, and the frequency for peak
gain is shifted down by 4 GHz when a Cp of just 20 fF is introduced. Note that the overall
load capacitance at the output also increases due to the addition of parasitic capacitance Cp ,
which reduces the -3 dB bandwidth of the tuned load, and also affects the common-mode
frequency response. Reverse isolation (S12 ) is degraded by 5 dB across the entire frequency
range, making the PA susceptible to antenna mismatch and instability. This is confirmed
from examination of Fig. 4.10b, where the stability factor µ is seen to deteriorate as Cp
increases, moving well into the regime of potential instability.
Neutralization, which cancels the internal feedback present in the amplifier by adding an
4.2. Electrical Stability
103
15
C
p
= 20 fF
C
p
5
= 0 fF
S
-5
p
-15
S
21
and S
= 20 fF
C
12
, in dB
21
C
p
S
= 10 fF
-25
C
p
12
= 0 fF
-35
40
50
60
70
80
70
80
Frequency, in GHz
a) S21 and S12
Edwards-Sinsky stability factor,
1.0
0.8
C
= 0 fF
C
= 10 fF
C
= 20 fF
p
0.6
p
0.4
p
0.2
40
50
60
Frequency, in GHz
b) Stability factor µ
Figure 4.10: Simulated S21 , S12 , and stability factor µ for the circuit of Fig. 4.9a for 3 values
of parasitic collector-to-emitter capacitance, Cp .
external feedback path, can mitigate the undesired output-to-input feedback [19]. It is wellsuited to a differential topology, as simply cross-connecting a compensating capacitor to
the anti-phase output minimizes the net current flowing through the parasitic capacitance.
Neutralization is often applied to a common-emitter or common-source topology in order to
overcome the influence of Miller capacitance (i.e., Cµ in BJTs and Cgd in MOSFETs) [20]
[21] [22]. In this work, neutralization is used to improve isolation by minimizing feedback via
104
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
a) Neutralized differential CB pair
b) Neutralized differential CE pair
Figure 4.11: Schematics of a neutralized differential CB and CE pair.
parasitic collector-emitter capacitance (i.e., Cp in Fig. 4.11a). In Fig. 4.11, the schematics
of neutralized CB and CE stages with a parallel R-L load are shown, where Cf represents
the neutralization capacitor. Neutralizing capacitors can be realized by vertical parallelplate BEOL metal capacitors, or dummy transistors of the same type in order to track
the parasitic capacitance variation with processing and temperature. The collector-emitter
neutralization in Fig. 4.11a introduces negative, rather than positive feedback in Fig. 4.11b,
which eliminates the potential for oscillation due to over-compensation. As stated in [20],
over-compensating the base-collector feedback which causes the Miller effect (as in Fig. 4.11b
for Cf > Cµ ) will result in a net positive feedback, which likely triggers oscillation. By
contrast, increasing the negative feedback by adding more neutralization capacitance in
Fig. 4.11a (i.e., Cf > Cp ) promotes amplifier stability even further. Hence, the collectoremitter capacitance neutralization of Fig. 4.11a is more robust against process variation,
and sufficient Cp can be added in order to avoid under compensation. The drawback of
over-compensation in Fig. 4.11a is that the power gain is decreased. However, simulations
predict that a variation of ± 10% for the neutralization capacitor causes only 0.4 dB and
0.4 GHz changes in peak gain and center frequency of the 3-stage PA, respectively. A ± 40%
variation in neutralization capacitance causes only a 1 dB drop in peak gain. Post-layout
simulations under common-mode (CM) and differential-mode (DM) operation are used to
verify the unconditional stability of the PA.
4.2.2
Parasitic Reduction and Equalization
Another factor critical to the stability of a CB stage is the impedance in series with the
base, especially base inductance, LB . Because of the emitter gyration effect, inductance in
series with the base appears as a negative resistance with a small-signal value of -ωT LB at
the emitter, where ωT is the radian transit frequency of the transistor. As the inductance
increases, the real part of the entire CB stage input impedance can become negative, making it potentially unstable and prone to oscillation. Thus, inductance at the base must be
4.2. Electrical Stability
105
Figure 4.12: Simplified layout of a differential CB pair with parasitic impedance reduction
and equalization at the base.
controlled and minimized in the amplifier layout.
The base terminals of the parallel-connected transistors in the same amplification path are
not connected together, instead they are connected to their counterparts in the differential
path as shown in Fig. 4.12 [6]. This layout avoids base inductance being multiplied by the
number of transistors in parallel. A virtual ground lies along the line of symmetry in the
layout (as shown in Fig. 4.12), and the base inductance contributed by the interconnect is
determined by the physical distance between the base terminal and virtual ground.
The base inductance seen by transistors far away from the virtual ground can be large, and
the inductance varies with the interconnect length (annotated ’short, medium and long’ in
Fig. 4.12). PA stages with unequal base interconnect impedances are susceptible to current
hogging, so an adjacent current-return loop is introduced to reduce the base inductance
through magnetic coupling [6]. This is realized by placing metal 1 beneath the longer base
interconnects. Assuming a magnetic coupling factor of 0.8, the base inductance is reduced
to 20% of its original value using this layout. The bases of the CB stages are AC grounded
because of the differential operation and symmetry of the layout, and the increased parasitic
capacitance from adding the metal-1 ground paths suppresses any AC signal swing at the
bases. The metal width and thickness (i.e, via metal stacking) of the longer interconnects
are also increased to further reduce and balance the base inductances between transistors.
Moreover, the base resistances are also equalized by these same layout modifications. Fig. 4.12
shows the layout of a transistor array incorporating both series base impedance reduction
and equalization schemes. By adjusting metal width, thickness and the magnetic coupling
simultaneously, the base inductance of the largest transistors in the final stage is kept to
approximately 10 pH.
106
4.2.3
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
On-chip Isolation
Cross-coupled capacitive neutralization improves the isolation of an individual stage, however, the coupling from one stage to another in a multi-stage topology, or between circuit
blocks when integrated on chip, remains a potential source of instability. Thus, it requires
designers to identify and suppress the unwanted sources of feedback in order to prevent
oscillation.
The most problematic feedback paths are typically through the on-chip supply and ground
paths, since they are often shared by multiple stages or circuits. Differential operation is
immune to parasitics from the supply and ground interconnects. However, common-mode
signals appearing at the AC virtual grounds tend to circulate and cause instability because
there can still be sufficient common-mode gain. Some designs have the potential of keeping
the common-mode gain low in the operating frequency range of interests without affecting
the differential-mode frequency response. For example, a multi-turn differential inductor
under common-mode excitation has a much lower inductance than when driven differentially.
However, the active device itself presents a very high gain at low frequencies (e.g., > 25 dB
seen in Fig. 2.1 in Chapter 2), which could exacerbate the potential for parasitic oscillation
out of band. Therefore, the grounds of sensitive stages and high-power blocks (e.g., the
analog and digital grounds) should be separated on chip. The overall isolation can be further
improved by separating the supply buses if needed.
On-chip and off-chip supply decoupling is of equal importance for the same reason. Inadequate decoupling can potentially increase common-mode gain. Sufficient supply decoupling
capacitance must be placed before the long supply interconnects to the bondpads and near
the supply feeding points (e.g., the collector of a HBT). Proper damping resistors are required in order to suppress peaking of a supply decoupling network impedance, which could
also affect stability. Proper decoupling also prevents noise from affecting the circuit.
Electric and magnetic coupling via on-chip passive components is another source of unwanted
crosstalk between stages. It is reduced by separating components physically. A patterned
ground shield underneath a component reduces electric coupling to the substrate, but it
needs an explicit ground reference on chip [23] [24]. Any impedance in the ground path
compromises the shield’s effectiveness and also reduces isolation (e.g., due to coupling via
the common ground). As described in Chapter 2, a self-shielding structure does not require
an explicit ground reference but can still reduce substrate coupling for lower losses and
improved on-chip isolation.
4.3
Power-combining PA Prototypes
A multi-stage PA is optimized by properly selecting the topology for each stage, the number
of stages, gain distribution, transistor sizing in each stage and the interstage matching network [6]. Chapter 3 discussed the matching network design for the PA final stage, and the
previous sections in this chapter addressed the topology selection for amplification stages.
4.3. Power-combining PA Prototypes
107
Table 4.1: Specifications of the mm-wave PA demonstrators in this work.
Parameter
Topology
Freq. (GHz)
BW−3dB (GHz)
PSAT (dBm)
Peak PAE
S21
S11 (dB)
VCC (V)
Area (mm2 )
Technology
SiGe-BiCMOS PA
4-way combining
60/77/(71–76) GHz band
8–10
> 18
> 15%
20
< -10
1.8–2.5
<1
130 nm and 90 nm SiGe-BiCMOS
CMOS-SOI PA
2-way combining
60 GHz band
8
15
> 15%
10
< -10
1.2
<1
65 nm CMOS-SOI
This section continues with the PA top-level design, interstage coupling and prototype implementation.
4.3.1
Prototype Specifications
The technologies available for PA prototypes in this work include: STM’s 130 nm SiGe
BiCMOS [1], IBM’s 90 nm SiGe BiCMOS [25] and STM’s 65 nm CMOS-SOI [26]. The SiGeBiCMOS mm-wave PA prototypes with parasitic-compensated, 4-way transformer combiners
described in Chapter 3 aim at greater than 18 dBm output power and larger than 15% peakPAE with 20 dB power gain in band. A bandwidth of 8–10 GHz is targeted for multi-Gb/s
wireless communication, automotive radar (min. 5 GHz) and wireless backhaul applications.
The transmission-line based, slow-wave coplanar waveguide (S-CPW) combiner described in
Chapter 3 is demonstrated in a two-stage, 60 GHz-band PA. Fabricated in 65 nm CMOSSOI, the PA prototype targets 15 dBm output power, 15% peak-PAE and 15 dB power
gain in band operating from a 1.2 V supply using 2-way (instead of 4-way) combining. The
proof-of-concept design can be employed as the unit amplifier cell in the multi-way, in-phase
PA combining topology [27] described in Chapter 2 for even greater power output and gain.
Table 4.1 summarizes the detailed design specifications.
4.3.2
Top-level Design Considerations
Fig. 4.13 shows a top-level block diagram of a multi-stage, output-combining PA, where a CB
or cascode configuration is used as the gain stage, and monolithic transformers or transmission lines are employed for interstage matching. Amplifier topologies such as (neutralized)
common-emitter stage and their CMOS equivalents could be utilized in the gain stages as
well. However, this work concentrates on the CB and cascode stages for the reasons described
in Section 4.1. The PA is designed using a bottom-up and an output-to-input (i.e., reverse
to the signal flow) approach in this work. After the single-stage amplifier comparisons in
Section 4.1, the number of stages is chosen in order to meet the power gain target (e.g.,
20 dB) and the gain distribution is arranged so that the PAE is maximized (i.e., bottom-up
development). The interstage coupling is designed to transform the input impedance of one
108
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
Figure 4.13: Block diagram of a multi-stage, output-combining, differential PA topology.
stage to the optimal load impedance required by its preceding stage for maximum power
generation. Transistors in the final stage are sized and biased for an optimal load impedance
between 10 Ω and 20 Ω (see Section 2.1.4). The impedance transformation from the 50 Ω
load to 10–20 Ω can be realized by the power combiner as presented in Chapter 3. The driver
stage is sized and biased in order to provide the driving power required by the final stage,
and a coupling network is developed to perform the impedance conversion between these
two stages. A similar design procedure continues back to the input of the PA (i.e., from the
output back towards the input).
From the single-stage amplifier data shown in Fig. 4.8, it is reasonable to assume that a
small-signal gain per CB stage of 10–12 dB is attainable at 60 GHz, and that peak-PAE
of the last stage is projected to be 28%–35% at 4 dB gain compression. The incremental
compression in power gain is 1 dB per stage. The transistors are scaled 1:2 in area, and
each stage develop power sufficient to drive the next stage. Therefore, one stage consumes
one-half of the chip area and one-half of the DC power consumption of the subsequent stage.
Losses of the matching networks are estimated to be 1 dB at the input and output, and
2 dB for the interstage coupling network. Thus, the power gain of a 1-stage CB amplifier at
peak-PAE is 4–6 dB, after considering the 2 dB of loss from the input and output matching
networks. The PAE of a multi-stage PA is normalized to that of the final (single) CB stage
using Eqs. 4.3 and 4.4,
PAEN =
PAE =
(GN − 1)Pin,N
Pout − Pin,N
=
PDC,N
PDC,N
(GN − GN1−1 ! )Pin,N
(GN − GN1−1 ! ) PDC,N
Pout − Pin,1
=
=
P AEN ,
PDC,tot
PDC,tot
GN − 1 PDC,tot
(4.3)
(4.4)
4.3. Power-combining PA Prototypes
109
Final stage gain at peak-PAE = 4 dB
= 6 dB
36
32
33
22
20
30
12
27
2
1
2
3
4
5
Peak-PAE, in %
Large-signal gain, in dB
42
24
Number of gain stages
a) Power gain and peak-PAE
= 6 dB
2.0
12
1.8
4
1.6
0
-4
1.4
-12
1.2
-20
1.0
1
2
3
4
DC power consumption
Input power at peak-PAE, in dBm
20
(Normalized to power of the last stage)
Final stage gain at peak-PAE = 4 dB
5
Number of gain stages
b) Input power at peak-PAE and DC power consumption
Figure 4.14: Estimated multi-stage PA performance with respect to the number of stages.
where parameters with the subscript N represent the data for the N th stage of a N -stage
stage, GN and PDC,N are the power gain and DC power consumption of the N th stage,
respectively. Pin,1 is the power input to the first stage, Pin,N is the power input to the N th
stage, and P AE is the PAE of the multi-stage PA overall.
110
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
Fig. 4.14 investigates the influence of the number of stages on power gain, PAE, input power
and DC power consumption for a 60 GHz PA. The dashed lines are for CB stages with smallsignal power gain of 12 dB and the solid lines are for the scenario of 10 dB power gain. The
targeted output power, Pout , is 20 dBm and the maximum input driving power is desired
at near 0 dBm in order to relax the transmit driver design. It is obvious that the power
gain and DC power consumption increase (see Fig. 4.14), and thus the required input power
decreases with the increase in the number of stages (see Fig. 4.14b). On the other hand, the
PA efficiency drops with the extra power consumed by the driver stages as the number of
stages increases (see the 6 dB curves in Fig. 4.14a). Thus, in order to preserve high efficiency,
the minimum number of stages in cascade which meets the desired power gain requirement
should be employed. Fewer stages offer insufficient power gain, while more stages decrease
the efficiency by consuming greater DC power. It should be noted that the 2-stage PA has a
(slightly) higher PAE than a 1-stage PA when the power gain is assumed to be 4 dB. That
is because the additional driver stage decreases the RF input power more than the increase
in DC power consumption. In other words, the factor (GN − 1/GN −1 ! ) in Eq. 4.4 is larger
than the increase in power consumption of 1.5 times in this case. The decreasing slope of
the PAE with the increasing number of stages indicates that the degradation in efficiency
by adding more driver stages is suppressed by the greater power gain, which agrees with the
prediction of Eq. 2.8 in Chapter 2.
The optimal number of stages in cascade is approximately 3 when the compressed power gain
per stage is near 6 dB. With a lower power gain (e.g., 3 dB) a 4-stage PA topology offers
the best trade-off. A cascode output stage provides ∼ 6 dB higher power gain per stage (see
Section 4.1), which leads to an optimal PA design of 2 stages in cascade. A smaller number of
stages in cascade also simplifies the interstage coupling network design. It is worth pointing
out that the analysis shown in Fig. 4.14 assumes a transistor size scaling factor of 1:2. This
factor changes with the power gain per stage, and in turn affects the DC power consumption
of the driver stages and their influence on the PAE of the multi-stage PA (e.g., the slope of
PAE curve might be different). However, the relationship between overall PA performance
and the number of gain stages remains valid.
4.3.3
Transformer Output Combining and Interstage Coupling
The DC supply voltage of the PA output stage is fed via the virtual ground of the primary
winding of the floating-compensated transformer combiner shown in Fig. 3.4a, requiring AC
coupling between the AC (virtual) and DC grounds. As the ground of the secondary winding
in the laterally-compensated balun is routed inside the combiner layout (see Fig. 3.4a), the
tight inner dimension and limited number of thick metal layers make separation of the virtual
and DC grounds difficult without compromising performance significantly (e.g., coupling
between the ground routing and the transformer windings). Connecting the AC ground at
the center tap of the primary and the DC ground within the combiner layout and separating
them via an AC-coupling capacitor (Cc ) in series with the RF output solves this problem at
the expense of increased chip area and parasitic coupling. This section describes the solution
for the AC-coupling capacitor (see capacitor Cc in Fig. 4.15) developed in this work to avoid
4.3. Power-combining PA Prototypes
111
Figure 4.15: Physical layout of the RF output AC-coupling capacitor, Cc .
a) Prototype 1 with AC-coupling cap.
b) Prototype 2 with AC-coupling and parallel cap.
Figure 4.16: Photomicrographs of the combiner prototypes with the AC-coupling capacitor
embedded in bondpads.
these compromises, and the discussion is then extended to the on-chip interstage coupling
network using transformers.
A.
Co-design of the Output Combiner and Bondpads
Fig. 4.15 shows the implementation of the AC-coupling capacitor. It is embedded in the
output ground-signal-ground (GSG) bondpads in order to conserve chip area and minimize
coupling to the combiner. The combiner grounds are routed in metal 5, while the ground
bondpads are implemented in metals 4 and 6. Enclosing metal 5 with the other metals
top and bottom creates a parallel-plate coupling capacitor. The area of the bondpads and
feedlines determine the total capacitance. EM simulations predict that the total capacitance
112
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
Simulation
Measurement
0
S
, in dB
-4
11
of combiner 1
and S
21
-8
S
21
of combiner 1
S
11
-12
-16
S
11
of combiner 2
-20
50
55
60
65
Frequency, in GHz
a) S11 and S21
Simulation
-2
MAG of combiner 2
-3
-4
S
21
of combiner 2
MAG and S
21
, in dB
Measurement
-5
-6
MAG of combiner 1
-7
-8
50
55
60
65
Frequency, in GHz
b) MAG and S21
Figure 4.17: Measured and simulated MAG, S11 and S21 of the combiner prototypes from
back-to-back testing (note that S22 = S11 , and S12 = S21 ).
from two 100×100 µm2 ground bondpads is approximately 1.5 pF, which has a reactance of
only −j1.77 Ω at 60 GHz.
Photomicrographs of the two transformer combiner prototypes with embedded AC-coupling
capacitors are shown in Fig. 4.16. Their measured S-parameters and MAG across 50–65 GHz
are compared in Fig. 4.17. One difference between the two prototypes is that four parallel
capacitors are inserted at the primary terminals of prototype 2 to resonate at 60 GHz (see
Fig. 4.16b). This matches the real part of the primary impedance reflected by the combiner
from the 50 Ω load to the characteristic impedance of the transmission lines in order to min-
4.3. Power-combining PA Prototypes
113
Figure 4.18: A transformer coupling network.
imize power reflection. Good agreement is observed between measurement and simulation.
The measured S21 and MAG of prototype 2 are close to each other, as expected, because
of the symmetric test structure and impedance matching at the interface (note that S11 of
combiner 2 is < -10 dB across 50–65 GHz in Fig. 4.17a). The measured back-to-back MAG
at 60 GHz is -4.3 dB for prototype 1, and -3.3 dB for prototype 2. The 1 dB increase in
MAG quantifies the effectiveness of eliminating the reflection at the interface between the
combiner and the transmission lines. The measured MAG of a single combiner is 1.65 dB
from Fig. 4.17b. Excluding losses from the parallel capacitors and the additional transmission line interconnect for back-to-back testing, simulations predict that the insertion loss of
the entire PA output combining network is below 1 dB at 60 GHz (including losses from
bondpads and the AC-coupling capacitor).
B.
Interstage Coupling Networks
The conventional L-, Π- and T-type matching networks using lumped passive components
or transmission lines are not discussed here, and information can be found in [28]. Instead,
transformer coupling, which suits the common-base gain stages well is explained in detail.
The use of a monolithic transformer for interstage coupling is also justified by its wide
bandwidth and the simplicity of DC biasing active devices via the transformer center taps
[29] [30] [20].
Fig. 4.18 illustrates two CB stages coupled by a transformer on chip, where the signal is
coupled from the collectors of the first stage to the emitters of the second stage. A CB stage
has no current amplification, so power amplification can only be realized via impedance
transformation between its input and output. Assuming that the transistor area ratio is 1:2
and that the second stage has 10 dB gain, it is estimated that the required load impedance
of the first stage is 2Ropt and the input impedance of the second stage is 0.1Ropt , where
114
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
Width=10 m
Width=25 m
Diff. impedance at primary, in
250
150
Real part
50
Imaginary part
-50
-150
50
55
60
65
70
Frequency, in GHz
Figure 4.19: An example of transformer impedance transformation with different winding
widths.
Ropt represents the optimal load impedance for the second stage. Therefore, the transformer
must provide a 20:1 impedance transformation ratio. This impedance transformation leads
to a (minimal) 4.5 times smaller voltage swing at the input of the second stage, compared
to the output of the first stage (n.b., voltage gain is larger when transformer losses are
considered). Thus, the self-shielding structure described in Chapter 3 can be applied. The
winding connecting to the input of the second CB stage is placed beneath that of the first
stage (see Fig. 4.18), shielding it from the conductive substrate, thereby decreasing the energy
losses.
A 20:1 impedance transformation requires a transformer drawn turns ratio of 4.5:1, which
is unrealistic at mm-wave frequencies, where the self-inductance needed is small (e.g., below
200 pH). However, the leakage inductance from imperfect magnetic coupling together with
the shunt parasitic capacitance from device and interconnects at the primary terminals, forms
a L-type step-up impedance transformation network [28] [31], which relaxes the requirement
on transformer turns ratio. Moreover, Cheung [32] has analyzed the transformer operation at
higher frequencies using a coupled-line model. Beyond the well-known transformer impedance
transformation determined by the drawn turns ratio, there is another operating region. It
is similar to a quarter-wave transmission line, where the transformed primary impedance is
inversely proportionally to the secondary load impedance, and proportional to the square
of the characteristic impedance (Zo ) of the coupled windings. Hence, an increase in the
impedance transformation ratio of the transformer in Fig. 4.18 is anticipated because Zo of
the coupled lines can be designed to be (much) larger than the secondary load impedance,
0.1Ropt . The width of the transformer windings and the gap between them are adjusted
in order to realize the desired characteristic impedance. Hence, the electrical turns ratio is
potentially much larger than the drawn turns ratio at mm-wave frequencies when Zo is larger
4.3. Power-combining PA Prototypes
115
Figure 4.20: Simplified schematic of the 3-stage, transformer-coupled, 4-way combining differential SiGe-BiCMOS PA.
than the load impedance of the secondary winding.
The differential impedance seen at the primary winding of a 1:1 (drawn) turns ratio transformer is plotted in Fig. 4.19 for winding widths of 10 µm and 25 µm. The differential load
impedance at the secondary winding is set at 5 Ω. Both transformers are sized to resonate at
60 GHz with 75 fF shunt capacitance across the primary terminals. Impedances at resonance
are 200 Ω for the 10 µm, and 106 Ω for the 25 µm wide transformer windings. Increasing
the winding width decreases the characteristic impedance of the coupled-line transformer,
and thus the transformed impedance seen across the primary terminals decreases. The combined step-up impedance transformation (i.e., L-type network and coupled transmission line)
reaches an electrical transformer turns ratio as high as 6.3:1 in this example.
Design considerations for each individual block of the multi-stage, output-combining PA
shown in Fig. 4.13 have been addressed at this point. Two complete PA prototypes in SiGeBiCMOS and CMOS-SOI technologies following this design approach will be described in
the next section.
4.3.4
60 and 77/79 GHz-band SiGe-BiCMOS PA Prototypes
A minimum of 3 cascaded stages is necessary to realize the targeted 20 dB in-band power
gain in the 130 nm BiCMOS technology. A 3 stage cascade also realizes larger than 15%
PAE. The simplified schematic of the 3-stage, transformer-coupled, 4-way combining PA
with a single-ended input and output is shown in Fig. 4.20 [33] [34]. It consists of a single
input stage followed by two, 2-stage amplifiers operating in parallel. A differential amplifier
116
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
topology is preferred, as it is insensitive to common-mode signals (e.g., supply noise and
crosstalk) and parasitics in the supply and ground paths. Moreover, a PA with a differential
input and single-ended output eases interfacing to the transmit mixer at the input, and a
50 Ω antenna load at the output. However, a single-ended input is used in this work in order
to simplify testing of a stand alone PA prototype, so an input balun is included on chip.
Differential CB pairs are employed in each stage to extend the collector-emitter breakdown
(BVCER ) beyond BVCEO (i.e., > 3 V) for increased collector voltage swing and output
power. The first amplifier demonstrator is designed for operation in the 60 GHz band. The
transistors for the 3 gain stages (i.e., Q1,2 :Q3a/b,4a/b :Q5a/b,6a/b ) are scaled 1:2:8 in area, which
provide sufficient driving power for each stage without over-sizing the devices and introducing
unwanted parasitics. Neutralizing capacitors Cf 1 and Cf 2 (see Fig. 4.20) are added to the first
two stages to increase the isolation and guarantee stability. They are vertical parallel-plate
backend (BEOL) metal capacitors implemented in metals 4-6 of the 7-metal interconnect
stack in the 130 nm BiCMOS technology. The minimum compensating capacitance required
for unconditional stability predicted from simulation is 4 fF and 8 fF for Cf 1 and Cf 2 ,
respectively. Post-layout simulations predict that the stability factor (k) of the neutralized
60 GHz-band PA is larger than 11.6 and, | ∆ | is lower than 0.8 across 1–100 GHz. Under
common-mode operation, k is larger than 30, and | ∆ | is lower than 0.9 across 1–100 GHz.
Coupling between the PA stages is implemented using monolithic transformers as described
in Chapter 3 and Section 4.3.3 of this chapter. They provide current gain and impedance
transformation via the turns ratio in order to yield maximum power from the CB stages in
each path. They also realize multi-way power splitting and combining in a compact physical
layout on chip. Supply current is fed to the transistors through the virtual ground present
in each transformer winding when driven by a balanced signal. The 4-way output power
combiner couples differential signals from each path to drive a 50 Ω off-chip load. On-chip
balun (T1 ) matches the input stage to a 50 Ω source, simplifying testing and characterization
as mentioned previously. Resonating the self-inductance of T1 with parasitic capacitance from
the input bondpad (i.e., CP AD ) minimizes the attenuation of the input balun.
Magnetic components T1 to T5 in Fig. 4.20 are implemented using two top (thick copper)
metal layers for lower insertion loss and greater PA efficiency. Inter-stage transformers T2 , T3
and T4 are designed to present the optimal load to the transistors in each stage for maximum
power generation (i.e., class-A loadline matching). As described earlier, self-shielding is used
to limit the losses from each transformer to the substrate. To implement self-shielding, the
winding with the lowest voltage swing (i.e., secondary, at emitters of Q5a,6a in Fig. 4.20) is
placed beneath the winding with the highest swing (i.e., primary, at collectors of Q3a,4a ) in
the physical layout. The secondary is therefore shielded by the primary, minimizing energy
loss to the substrate. Fully-differential power splitter T2 [35] couples the first stage to each
of the amplifier gain paths (i.e., a differential 2:4 splitter). Self-shielded transformers T3 and
T4 with a turns ratio of 6:1 (electrical) couple the 2nd and 3rd stages in each path. Power
splitting after the 1st stage maintains power gain from the last two stages for efficiency, as
transformers T3 and T4 in each path are easier to optimize for losses. A compact 4:1 combiner
(T5 ) [35] sums the power from each output in the final stages and delivers it to the load.
4.3. Power-combining PA Prototypes
117
Figure 4.21: Simplified schematic of the 2-stage, transmission-line-coupled, 2-way combining
CMOS-SOI PA.
The 50 Ω load is AC-coupled to ground by capacitor Cc embedded in the bondpad area (see
Fig. 4.15), thereby ensuring that supply current flows through the output stages only.
The multi-path, multi-stage, transformer-coupled PA topology is scalable in frequency by
adjusting the dimensions of the transformers. A 77/79 GHz-band prototype was therefore
implemented in order to verify the scalability of the design [36]. Similar to the wideband
60 GHz-band PA just described, it is a 3-stage amplifier with 2 parallel paths consisting of
cascaded CB stages. However, in contrast to the 60 GHz-band PA, it uses a combination
of high-speed transistors (fT = 240 GHz, BVCEO = 1.52 V [1]) in the input stage, and
medium-breakdown-voltage HBTs (fT = 150 GHz, BVCEO = 2.01 V [1]) in the last
2 stages to maximize gain-bandwidth and increase the collector voltage swing and output
power. Compensation of the interwinding capacitance effects in the power splitting and
combining transformers is also reoptimized for operation in the 77/79 GHz band, which
utilizes the vertical compensation illustrated in Fig. 3.9. Experimental results for these two
SiGe-BiCMOS PA prototypes are reported in Sections A. and B. of Chapter 5.
4.3.5
60 GHz-band CMOS-SOI PA Prototype
Fig. 4.21 shows a simplified schematic of the CMOS-SOI PA, where a S-CPW combiner
sums the outputs of two amplification paths with low loss and compact dimensions on chip.
A cascode, common-source input stage increases the overall PA power gain, while a single
common-source stage maximizes the voltage swing at the output for a given supply voltage
(i.e., no headroom across other devices). The in-phase inputs of the two amplifier units are
connected together on chip and impedance matched to the 50 Ω source. On-chip coplanar
waveguides are used extensively for matching and interstage coupling. A T-type matching
network couples the two gain stages, where the AC-shorted terminals of the CPWs are used
16
0
15
-6
14
-12
13
-18
12
-24
11
-30
BW -3dB = 12.7GHz
-36
65
10
50
S11, in dB
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
S21, in dB
118
55
60
Frequency, in GHz
a) S21 and S11
Output power, in dBm, power gain,
in dB and PAE, in %
20
PAE
16
Power gain
12
8
Output power
4
0
-20
-15
-10
-5
0
5
10
Input power, in dBm
b) Output power, gain and PAE
Figure 4.22: Simulated performance of the CMOS-SOI PA prototype.
to feed the supply and DC biasing (e.g., VDD1 and Vg2 in Fig. 4.21). The optimal load
impedance is inductive, as an inductance is required to resonate with the output parasitic
capacitance. For the PA designs described in the previous section (4.3.4), output matching
network using a transformer balun in Fig. 4.20 is viewed as an RLC parallel equivalent
circuit. The reflected port resistance determined by the balun turns ratio is in shunt with
the parasitic capacitance, which resonates with the magnetizing inductance. However, in
this design, the quarter-wavelength S-CPW combiner has a real resistance at its inputs at
the desired frequency. Thus, inductors LL1 and LL2 are added in series with the inputs
4.4. Study Case - Cascode, Output-Combining PA
119
of the combiner to provide the inductance required (40 pH). The 2-way S-CPW combiner
transforms the 50 Ω load to 12.8 Ω at each input of the combiner at 60 GHz. The load
impedance of each PA cell is 20 Ω at resonance.
Fig. 4.22 shows the simulated PA performance from a 1.2 V supply (note that a 2 V supply
is used for the first cascode stage). The small-signal gain, (S21 ) and input return loss (S11 )
across 50–65 GHz are shown in Fig. 4.22a and the large-signal behavior at 60 GHz is given in
Fig. 4.22b. Peak S21 is 15 dB at 57.5 GHz, and the -3 dB bandwidth ranges from 50.5 GHz
to 63.2 GHz. The saturated output power is 15 dBm and peak-PAE is near 20% with the
input driving power at 0 dBm. The compressed power gain at peak-PAE is 10 dB.
Simulations have predicted that the performance of the CMOS-SOI PA prototype meets the
design specifications summarized in Table 4.1 in Section 4.3.1. Its experimental results are
presented in Section C. of the next chapter.
4.4
Study Case - Cascode, Output-Combining PA
The SiGe-BiCMOS PA circuits described in previous sections incorporate CB active stages
and the passive transformer components illustrated in Figs. 3.4 and 3.9 in Chapter 3 for
power splitting and combining. However, alternative designs of the gain cell and passive
components show promising performance as well. Section 4.1 in this chapter points out the
possibility of PAE improvement by using the cascode amplifier in a multi-stage PA. Section
C. in Chapter 3 described a two-transformer combiner, which presented low insertion loss
and good primary port uniformity at mm-wave frequencies. Thus, this section describes the
design details of a output-combining PA variant which incorporates the cascode amplifier
topology and the new transformer combiner shown in Fig. 3.10. The PA prototype targeting
the 71–76 GHz band for E-band wireless backhaul is designed and implemented in IBM’s
newly developed 90 nm BiCMOS technology (i.e., BiMCOS-9HP) [25]. The 90 nm BiCMOS9HP technology has a targeted fT and fmax of 300 GHz and 350 GHz, respectively [25]. An
advanced BEOL backend suitable for mm-wave passive components has also been developed
for this technology [25].
The simplified schematic of the 2-stage, 4-way combining PA is shown in Fig. 4.23. It utilizes a
multi-stage, parallel-path amplifier similar to the wideband mm-wave 130 nm SiGe-BiCMOS
PA described in Section 4.3.4. However, it has a number of important differences: 1) a
differential cascode amplifier in each stage to reduce the number of stages in cascade from
3 to 2, which requires fewer interstage coupling components and has a broader bandwidth
(see Section B.), 2) optimization of transistor layout configurations to maximize power gain
and reverse isolation simultaneously, and 3) a new 4-way output power combiner as shown
in Fig. 3.10 to ease the interconnects to bondpads and for good frequency scalability.
The PA consists of a single input, cascode stage followed by another cascode amplifier operating in a parallel-path configuration. As explained in Chapter 1, a cascade of N stages
√
decreases the operating bandwidth by a factor of 21/N − 1 [28], compared to a single-stage
amplifier. Thus, the 2-stage amplifier has the potential for a broader bandwidth than the
120
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
Figure 4.23: Simplified schematic of the 4-way combining, cascode PA in BiCMOS-9HP.
3-stage PA in Section 4.3.4. An on-chip balun (T1 ) resonating with the bondpad parasitic
capacitance is also used to match the input to a 50 Ω source impedance for testing purposes.
The CB transistors in each cascode stage extend the collector-emitter breakdown beyond
BVCEO . The CE transistors operate at a low quiescent bias (i.e., 0.75 V) and have a small
collector voltage swing because of cascoding, which suppresses self-heating. Thus, a ballasting resistor in series with the base of the CE transistor is used in each stage to guarantee
thermal stability. The cascode amplifier in the output stage uses a C-B-E-B-C HBT for the
CE transistor and a C-B-E HBT for the CB transistor. The C-B-E-B-C configured HBT
has higher power gain but more coupling capacitance between junctions from layout (e.g.,
stacked metal for interconnects). By contrast, the C-B-E HBT layout suppresses the junction
capacitive coupling but has slightly lower power gain due to the increase in resistive parasitics. The reduced collector-emitter capacitive coupling in the CB transistor physical layout
improves reverse isolation for unconditional stability. The transistors for the 2 gain stages
are scaled 1:4 in area. The 4-way output combiner T4 in Fig. 4.23 couples the differential
outputs from each path to the 50 Ω load and employs the layout illustrated in Fig. 3.10.
A shorted stub (i.e., inductive) is added in parallel with the output to resonate with the
signal bondpad capacitive parasitics. Simulated insertion loss of the combiner is 1.07 dB at
73 GHz, including losses from the tuning stub, interconnects and bondpads.
The small-signal gain and input return loss across 60–90 GHz and the large-signal behavior
at 73 GHz from post-layout simulations are plotted in Fig. 4.24a and 4.24b, respectively.
The quiescent current is 215 mA from a 2.2 V supply voltage. The input return loss is better
than 10 dB across 70.8–85.5 GHz, and peak S21 is 32 dB at 75 GHz. The -3 dB bandwidth
is 16.5 GHz, covering from 65.9 GHz to 82.4 GHz. A full coverage of the E-band (i.e.,
15 GHz from 71 to 86 GHz) is viable using this topology by slightly increasing the resonant
frequencies of the two stages. However, achieving good large-signal performance over the
4.4. Study Case - Cascode, Output-Combining PA
121
0
30
-10
25
-20
S
S
21
11
, dB
, dB
35
BW
-3dB
= 16.5 GHz
20
-30
60
70
80
90
Frequency, in GHz
a) S21 and S11
35
Power gain
20
15
32
Output power
29
26
10
PAE
23
5
20
0
-25
Power gain, in dB
Output power, in dBm, and PAE, in %
25
-20
-15
-10
-5
0
Input power, in dBm
b) Output power, gain and PAE
Figure 4.24: Simulated performance of the 9HP cascode PA prototype at 73 GHz.
entire band remains challenging, as a wideband load-line impedance matching is required
for each stage for maximum power generation. Thus, the design targets the lower E-band,
namely 71–76 GHz. The saturated output power at 73 GHz is 19.7 dBm, peak-PAE is 20%
and compressed power gain at peak-PAE is 22.5 dB. The required input driving power for
peak-PAE is -2.5 dBm.
Simulations predict that the transformer-coupled, 4-way output-combining, differential PA
122
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
topology developed in this work is capable of delivering 20 dBm saturated output power and
near 20% peak-PAE at frequencies at 60 GHz and above. Chapter 5 will describe the PA
prototype characterization and analyze the agreement between simulation and measurement.
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[17] G. Liu, T. J. K. Liu, and A. M. Niknejad, “A 1.2V, 2.4GHz fully integrated linear CMOS power amplifier
with efficiency enhancement,” in Proc. of IEEE-CICC, Sept. 2006.
[18] M. L. Edwards and J. H. Sinsky, “A new criterion for linear 2-port stability using a single geometrically
derived parameter,” IEEE Transactions on Microwave Theory and Techniques, vol. 40, no. 12, pp.
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Sons, 1984.
[20] W. L. Chan and J. R. Long, “A 58-65 GHz neutralized CMOS power amplifier with PAE above 10% at
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power and 29.3% PAE in 40-nm CMOS,” in Proc. of IEEE-ESSCIRC, Sept. 2012, pp. 337–340.
[23] C. P. Yue and S. S. Wong, “On-chip spiral inductors with patterned grounded shields for Si based RF
ICs,” IEEE Journal of Solid-State Circuits, vol. 33, no. 5, pp. 743–752, May 1998.
[24] O. El-Gharniti, E. Kerherve, and J. B. Begueret, “Characterization of Si-based monolithic transformers
with patterned ground shield,” in Proc. of IEEE-RFIC, Jun. 2006.
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J. Adkisson, R. Camillo-Castillo, P. Cheng, J. E. Monaghan, P. Gray, D. Harame, M. Khater, Q. Liu,
A. Vallett, B. Zetterlund, V. Jain, and V. Kaushal, “Total dose and transient response of SiGe HBTs
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1–5.
[26] F. Gianesello, S. Montusclat, B. Martineau, D. Gloria, C. Raynaud, S. Boret, G. Dambrine, S. Lepilliet,
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IEEE-RFIC, Jun. 2007, pp. 555–558.
[27] K. Sengupta and A. Hajimiri, “A compact self-similar power combining topology,” in Proc. of IEEEMTT-S, May 2010, pp. 244–247.
[28] T. H. Lee, The Design of CMOS Radio-Frequency Intergrated Circuits, 2nd ed. Cambridge University
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[29] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE Journal of Solid-State Circuits,
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[30] D. Chowdhury, P. Reynaert, and A. M. Niknejad, “Design considerations for 60 GHz transformercoupled CMOS power amplifiers,” IEEE Journal of Solid-State Circuits, vol. 44, no. 10, pp. 2733–2744,
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[31] T. S. D. Cheung, J. R. Long, Y. V. Tretiakov, and D. L. Harame, “A 21-27GHz self-shielded 4-way
power-combining PA balun,” in Proc. of IEEE-CICC, Oct. 2004, pp. 617–620.
[32] T. S. D. Cheung and J. R. Long, “Design and modeling of mm-wave monolithic transformers,” in Proc.
of IEEE-BCTM, Oct. 2006, pp. 1–4.
[33] Y. Zhao and J. R. Long, “A wideband, dual-path, millimeter-wave power amplifier with 20 dBm output
power and PAE above 15% in 130 nm SiGe-BiCMOS,” IEEE Journal of Solid-State Circuits, vol. 47,
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[34] Y. Zhao, J. R. Long, and M. Spirito, “A 60GHz-band 20dBm power amplifier with 20% peak PAE,” in
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[36] Y. Zhao, J. R. Long, M. Spirito, and A. B. Akhnoukh, “A +18dBm, 79–87.5GHz bandwband power
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124
Chapter 4. Multi-stage and Output-combining Power Amplifier Design
Chapter 5
Power Amplifier Prototype Testing and Performance
All the design-related aspects of the PA prototypes have been dealt with in Chapters 3
and 4. Both the SiGe-BiCMOS and CMOS-SOI PAs developed in this work have a singleended input and output, which simplifies their testing as a 2-port network. A vector network
analyzer (VNA) is used to capture the small-signal reflection coefficients and frequency
response of the PA prototypes. However, characterization of the large-signal behavior under
frequency and power sweeps remains difficult because an absolute power measurement at the
input and output of the device-under-test (DUT) is required. A power meter could detect
the power level at its input where the calibration reference plane is. However, the influences
from the test fixtures, such as cables and adapters, must be removed in order to shift the
measurement reference planes to the input and output of the DUT. Ferrero, et al., reported
an improved calibration technique [1] which addresses this problem and allows one to perform
both the vector and power calibrations at the RF wafer probe tips. This chapter explains this
technique briefly and illustrates its implementation in the lab test setup. The experimental
results for the PA prototypes described in Section 4.3 of Chapter 4 are presented in the
second half of the chapter.
5.1
Large-signal Measurement Setup
The large-signal measurement setup is based on a vector network analyzer, two dual directional couplers and two planar RF probes. The technique in [1] is automated in order to
realize both power and frequency sweeps in a reproducible way.
5.1.1
Three-step Calibration Procedure
Fig. 5.1 shows the basic test scheme, the calibration reference planes and the required calibration methods. In order to obtain the reflection coefficient at the input port (i.e., P1 in
Fig. 5.1), a 1-port, short-open-load (SOL) calibration needs to be performed at the input
probe tip using an impedance standard substrate (ISS), as shown in Fig. 5.1a. A coaxial
SOL calibration is then performed at the thru port of the dual directional coupler at the
output (i.e., P2 in Fig.5.1b) with a on-substrate thru standard connected between the two
RF probes. The modified output error box model proposed in [1] provides information for the
125
126
Chapter 5. Power Amplifier Prototype Testing and Performance
a) Input port calibration
b) Output port and power calibrations
Figure 5.1: Three-step PA large-signal calibration procedure.
absolute power levels at the probe tips. Through a power calibration using a power sensor
and meter at the same reference plane as the coaxial SOL calibration, the power levels at
both the input and output probe tips can be derived. Detailed flow graphs, derivations and
explanations can be found in [1].
5.1.2
V- and W-band Test Setups
Fig. 5.2 shows the test setup used to characterize the 60 GHz-band PA prototypes in the
laboratory. An external power amplifier (Millitech AMP-15-020100) with an isolator at the
output was used to amplify the RF power from the VNA and drive the PA into saturation.
The isolator provides a broadband 50 Ω load for the external power amplifier. The Agilent
67 GHz vector network analyzer is configured to bypass the internal couplers (i.e., by opening
jumpers on the front panel). Two WR-10 waveguide couplers form a dual directional coupler
at the input and output of the setup, allowing sampling of the forward and reflected signals
separately and simultaneously.
A similar test setup was built for characterization of PAs in the W-band, where two mmwave module heads are used in order to source and detect the desired frequency range. The
6th and 8th harmonics of the RF and local oscillator signals lie in the 67–110 GHz band.
An external waveguide power amplifier can be inserted after the mm-wave module head in
order to boost the power driving the PA if needed.
5.2. PA Prototype Performance
127
Figure 5.2: V-band PA large-signal characterization setup.
5.2
PA Prototype Performance
The two differential, transformer-coupled, mm-wave PA circuit demonstrators described in
Chapter 4 were fabricated using STM’s SiGe-BiCMOS 130 nm technology [2]. The 60 GHz
single-ended PA prototype in Fig. 4.21 was implemented in STM’s 65 nm CMOS-SOI process
[3]. The 130 nm technology has 6 thin and 2 thick (topmetal) interconnect layers. The highspeed HBT exhibits fT /fmax of 240/270 GHz. The 65 nm CMOS-SOI technology has a
standard back-end which features 6 copper metal layer and an aluminum capping layer [4].
The top copper is thicker than the lower metal layers. The MOSFET demonstrates fT /fmax
of 220/240 GHz, which is comparable to the 130 nm SiGe HBT.
Fig. 5.3 shows chip photomicrographs of the prototypes. The 60 and 77/79 GHz-band SiGeBiCMOS PAs occupy chip areas of 0.72 mm2 and 0.68 mm2 , respectively. Excluding bondpads
and the input balun (required for characterization), the active areas are 0.25 mm2 and
0.23 mm2 , respectively. Area of the CMOS-SOI PA is 0.58 mm2 including the bondpads.
5.2.1
Experimental Results
This section presents the small-signal S-parameters and large-signal behavior of all the PA
circuit demonstrators, and compares their performance with designs published in the recent
literature.
128
Chapter 5. Power Amplifier Prototype Testing and Performance
a) 60 GHz-band SiGe-BiCMOS PA
b) 77/79 GHz-band SiGe-BiCMOS PA
c) 60 GHz-band CMOS-SOI PA
Figure 5.3: Chip photomicrographs of the PA prototypes using STM technologies.
A.
60 GHz-band SiGe-BiCMOS PA Prototype
Measured and simulated S21 of the 60 GHz-band SiGe-BiCMOS PA across 50–65 GHz are
shown in Fig. 5.4 versus supply voltages (196 mA total bias current in each case). The
measured result at 1.8 V agrees well with simulation. The approximately 2 dB difference
in peak-S21 is likely due to misalignment in the center frequency of the bandpass response
in the gain stages. Measured peak-S21 and the -3 dB bandwidth for 1.5 V < VCC < 2.0 V
exceed 20 dB and 10 GHz, respectively. At 1.8 V (nominal supply), peak-S21 is 20.6 dB at
60 GHz, and the -3 dB bandwidth ranges from 54.6 GHz to above 65 GHz, which is the
upper limit of the test equipment.
5.2. PA Prototype Performance
129
25
S21, in dB
20
Vcc = 1.2 V, meas.
15
Vcc = 1.5 V, meas.
Vcc = 1.8 V, meas.
Vcc = 2.0 V, meas.
Vcc = 1.8 V, sim.
10
50
55
60
65
Frequency, in GHz
Figure 5.4: Measured and simulated S21 of the 60 GHz-band PA.
0
S-parameter, in dB
Measured S22
-20
Simulated S22
Simulated S11
Measured S11
-40
Measured S12
-60
-80
50
55
60
65
Frequency, in GHz
Figure 5.5: Measured S11 , S12 , and S22 of the 60 GHz-band PA at 1.8 V.
Fig. 5.5 shows the measured S11 , S12 , and S22 from 50–65 GHz for a 1.8 V supply. The
simulated S11 and S22 are also shown for comparison. Both the input and output return
losses follow the trends predicted by simulation. It can be seen that the input return loss is
better than 12 dB across 50–65 GHz, with a slight shift in the minimum frequency value.
The output is not matched to 50 Ω, as the output combiner reflects the load (50 Ω) to the
optimal impedance required for maximum power output from the final stages. The reverse
130
Chapter 5. Power Amplifier Prototype Testing and Performance
0.8
Stability factor, k
1000
0.6
100
∆ < 1
0.4
10
0.2
k>8
50
55
60
0.0
65
50
55
60
65
1
10
15
20
25
30
35
40
45
Determinant of the S-matrix, ∆
1.0
10000
Frequency, in GHz
a) Stability factors k and |∆|
2.0
Stability factor,
1.8
1.6
1.4
1.2
1.0
10
15
20
25
30
35
40
45
Frequency, in GHz
b) Stability factor µ
Figure 5.6: Stability parameters for the 60 GHz PA at 1.8 V extracted from measurement.
isolation is more than 51 dB across the measured band, which validates the effectiveness
of the capacitively-neutralized CB stages (see Chapter 4). Stability factors (k, |∆| and µ)
extracted from measured S-parameters are plotted in Fig. 5.6 across 10–65 GHz. Both the
Rollett and Edwards-Sinsky stability parameters show the unconditional stability of the PA.
5.2. PA Prototype Performance
Ref
131
0 dBm
EXTMIX V
RBW 3 MHz
VBW 10 MHz
SWT 20 ms
Delta 2 [T1 ]
-53.05 dB
-100.000000000 MHz
0
-10
1 SA
AVG
Marker 1 [T1 ]
-14.07 dBm
61.000000000 GHz
1
A
-20
-30
-40
-50
SWP
32 of
32
3DB
-60
2
-70
-80
-90
-100
Center 61.05 GHz
40 MHz/
Span 400 MHz
a) RF output spectrum of the PA from the 2-tone test
30
23.5
OIP3
Output power, in dBm
10
-10
-30
-50
IIP3
-70
-25
-20
-15
-10
-5
0
2.9 5
Input power, in dBm
b) IIP3 and OIP3 of the PA
Figure 5.7: Measured two-tone intermodulation for the 60 GHz-band PA with tones at
61 GHz and 61.1 GHz (VCC = 1.8 V).
It was also observed on a wideband spectrum analyzer that the PA is unconditionally stable,
which agrees well with the extracted values of k > 8, |∆| < 0.82 and µ > 1 in the entire
band.
Fig. 5.7a is a plot of the RF output spectrum, and Fig. 5.7b shows the IIP3 and OIP3 from
a two-tone measurement (tones at 61 GHz and 61.1 GHz). The third-order intermodulation
132
Chapter 5. Power Amplifier Prototype Testing and Performance
PAE, in %, and power gain, in dB
Pout, in dBm,
25
PSAT = 20.1 dBm
Power gain
20
18
peak-PAE = 18%
15
Pout
10
PAE
5
0
-5
-20
Pin = 1.5 dBm
-15
-10
-5
0 1.5
5
Input power, in dBm
Figure 5.8: Measured output power, gain and PAE versus input power for the 60 GHz-band
PA at 62 GHz (VCC = 1.8 V).
and power gain at peak-PAE, in dB
PSAT, in dBm, peak-PAE, in %,
22
20
PSAT
Power gain at peak-PAE
Peak-PAE
18
16
14
12
1.0
1.2
1.4
1.6
1.8
2.0
2.2
Supply voltage, in V
Figure 5.9: Measured saturated output power, peak-PAE, and power gain at peak-PAE versus
supply voltage for the 60 GHz-band PA.
distortion (IM3 ) is 53 dB below the fundamental. The measured IIP3 and OIP3 are 2.9 dBm
and 23.5 dBm, respectively (see Fig. 5.7b).
Fig. 5.8 illustrates the measured output power (Pout ), gain and PAE versus input power at
62 GHz from a 1.8 V supply. The maximum output power is 20.1 dBm with 18% peak-PAE
5.2. PA Prototype Performance
133
and power gain at peak-PAE, in dB
PSAT, in dBm, peak-PAE, in %,
24
PSAT
Power gain at peak-PAE
Peak-PAE
21
18
15
12
57
58
59
60
61
62
63
64
Frequency, in GHz
Figure 5.10: Measured saturated output power, peak-PAE and power gain at peak-PAE
versus frequency for the 60 GHz-band PA (VCC = 1.8 V).
for 1.5 dBm input power. The power consumption at peak-PAE is 521 mW. The power
gain at low RF input levels is identical to the measured S21 in Fig. 5.4. Note that 0.5 dB
lower measured output power leads to 2% lower PAE when the peak-PAE is above 16% and
power gain at peak-PAE is greater than 10 dB. Therefore, measurement accuracy is crucial
to the reported PA performance, and repeated measurements have confirmed that the PA
prototype has a peak-PAE of 18% or greater at 62 GHz.
The saturated output power (PSAT ) and peak-PAE measured at different supply voltages
are plotted in Fig. 5.9. The peaks occur at around 60 GHz, which is in accordance with
the small-signal response of Fig. 5.4. Maximum output power increases monotonically from
15 dBm to 21 dBm as the supply voltage increases from 1.0 V to 2.2 V, with a peak-PAE
ranging from 12% to 18%.
The saturated output power, peak-PAE and power gain at peak-PAE measured across 57–
64 GHz (i.e., as per IEEE 802.15.3c) for a 1.8 V supply are plotted in Fig. 5.10. The PA
output power is approximately 20 dBm, and PAE is 15% or better from 58–65 GHz. A
maximum input power of just 2 dBm is required to drive the amplifier to peak-PAE, which
relaxes the transmit driver requirements in a 60 GHz wireless application. Fluctuations in the
measured data arise from calibration error and inaccuracy in the RF power measurements.
B.
77/79 GHz-band SiGe-BiCMOS PA Prototype
Measured and simulated S21 across 70–90 GHz for the 77/79 GHz SiGe-BiCMOS PA prototype operating from a 2.5 V supply are compared in Fig. 5.11. The shape of the frequency
response and peak-S21 agree well, however, the peak frequency is higher in measurement
134
Chapter 5. Power Amplifier Prototype Testing and Performance
30
Sim. with 30 fF smaller parasitic caps
S21, in dB
25
Measurement
20
15
Simulation with
nominal parasitic caps
10
70
75
80
85
90
Frequency, in GHz
Figure 5.11: Measured and simulated S21 for the 77/79 GHz-band PA at VCC = 2.5 V.
PSAT
18
and peak-PAE, in %
PSAT, P-1dB, Pin at PSAT, in dBm,
22
P-1dB
14
10
Peak-PAE
6
Pin at PSAT
2
-2
75
80
85
90
Frequency, in GHz
Figure 5.12: Measured PSAT , P−1dB , Pin at PSAT and peak-PAE versus frequency for the
77/79 GHz-band PA (VCC = 2.5 V).
than in simulation (83 GHz vs. 74 GHz). Reducing the equivalent shunt capacitance at the
output of each stage by ∼ 30 fF matches the simulated S21 to the measurement, as shown
in Fig. 5.11.
Measured peak-S21 exceeds 27 dB, which relaxes the power required to drive the PA to saturation. The -3 dB bandwidth is larger than 8 GHz, covering 78.9–87.5 GHz. The saturated
5.2. PA Prototype Performance
135
20
Measurement
Simulation
S21, in dB
15
10
5
0
50
55
60
65
Frequency, in GHz
Figure 5.13: Measured and simulated S21 of the 60 GHz-band CMOS-SOI PA.
output power, -1 dB compression point (P−1dB ), required input power for saturated output,
and peak-PAE measured across 75–90 GHz for a 2.5 V supply are plotted in Fig. 5.12. The
PA output power is greater than 16.5 dBm and peak-PAE is 7–9% in this frequency range.
Less than 2 dBm input power is required to drive the amplifier to its maximum output power
across this band. The maximum output power is 18 dBm with ∼ 9% peak-PAE at 84 GHz.
The differences seen between simulation and measurement for the 77/79 GHz prototype in
Fig. 5.11 likely come from misalignment of the center frequencies between the 3 gain stages
in the PA. Measurements of the medium-voltage transistor from stand alone test structures
revealed that the parasitic collector capacitance on the testchip is 30 fF lower than the
simulation model predicts, which is consistent with the simulation vs. measurement of the PA
shown in Fig. 5.11 (i.e., sim. with 30 fF smaller parasitic cap. matches measurement). Another
source of error could be the EM simulation settings used for the vertically-compensated
power splitter and combiner, as they were not characterized stand alone. The validity of
the high-speed transistor model has been proven by the excellent agreement seen between
measurement and simulation for the 60 GHz-band PA prototype. Thus, the power driving
capability of the first 2 stages drops due to the frequency misalignment, which constrains
the saturated output power. Approximately 3–4 dB more power and > 15% PAE can be
expected when the responses of the 3 stages are aligned properly.
C.
60 GHz-band CMOS-SOI PA Prototype
Measured and simulated S21 across 50–65 GHz for the CMOS-SOI PA prototype operating
from a 1.2 V supply (note that the cascode input stage is biased at 2 V) are compared
in Fig. 5.13. The measured, peak small-signal gain is 12 dB at 56 GHz, which is about
136
Chapter 5. Power Amplifier Prototype Testing and Performance
in dB, PAE and drain efficiency, in %
Output power, in dBm, power gain,
20
Drain efficiency
15
14
PAE
10
Power gain
Output power
5
0
-15
-10
-5
0
5
10
Input power, in dBm
Figure 5.14: Measured output power, gain and PAE versus input power for the 60 GHz-band
CMOS-SOI PA at 56 GHz (VCC = 1.2 V).
20
PAE
SAT
Drain efficiency
16
SAT
, in dBm,
18
and P
Drain efficiency and PAE, in %,
P
14
12
10
1.0
1.1
1.2
1.3
1.4
1.5
1.6
Supply voltage, in V
Figure 5.15: Measured saturated output power, peak-PAE, and power gain at peak-PAE
versus supply voltage for the 60 GHz-band CMOS-SOI PA.
3 dB smaller than simulations predict. Model inaccuracy for the transistors is the most
likely cause for the discrepancy between measurement and simulation because a production
designkit was not available from the foundry during the design phase. The device model was
ADS fits provided by project partner CEA-LETI. Other factors which could account for this
difference include: an underestimate of the source degeneration from parasitics in the ground
5.2. PA Prototype Performance
137
20
2
0.72mm
SiGe-BiCMOS
60GHz PA
0.7mm
Peak-PAE, in %
15
2
0.4mm
2
Chen11
Chan10
0.22mm
2
1,76mm
Chowdhury09
10
0.98mm
0.83mm
0.25mm
2
2
2
Law10
Pfeiffer07
Lai10*
2
Chowdhury08
5
1.68mm
2
Floyd05
3.42mm
2
Pfeiffer07
0.46mm
0
2
Martineau10
10
15
20
25
Saturated output power, in dBm
Figure 5.16: PSAT , peak-PAE and chip area comparison for silicon 60 GHz-band PAs from
the recent literature. Solid symbols represent BiCMOS and hollow symbols CMOS PAs. *
chip area excludes driving amplifiers.
path, and misalignment in the resonant frequencies of the two stages. It is observed that the
peak-gain frequency is also shifted to below 60 GHz. The measured -3 dB bandwidth is
∼ 9 GHz, ranging from 52.1 GHz to 61.4 GHz.
The saturated output power, peak-PAE, drain efficiency and power gain measured at 56 GHz
from a 1.2 V supply are plotted in Fig. 5.14. The measured saturated output power is 14 dBm
with a peak-PAE of 14% at 56 GHz (note that the first cascode stage is biased at 2 V).
The drain efficiency approaches 18%. In addition to the gain drop, the frequency response
misalignment in small-signal behavior also affects the power driving capability of the input
driver stage. It is expected that the peak-PAE could reach 20% when the resonant frequencies
are aligned properly.
The output power as a function of the supply voltage plotted in Fig. 5.15 shows very limited
power increase with increasing supply voltage. The weak dependence on supply voltage in
Fig. 5.15 also indicates that there might not be sufficient power available from the input
stage to drive the output stage. Consequently, the PAE and drain efficiency drop with the
supply voltage because of the increase in DC power consumption. The behavior observed is
markedly different from the SiGe-BiCMOS HBT amplifier result in Fig. 5.9, where the RF
power output increases from 15 dBm to 19 dBm with the supply voltage changing from 1 V
to 1.6 V.
138
Table 5.1: mm-Wave power amplifier performance comparison.
PSAT
(dBm)
P−1dB
(dBm)
Peak
PAE
S21
(dB)
PDC /VCC
(mW/V)
Area
(mm2 )
60/>22
12.3
9
8.8%
15
88/1
0.25
60/8
19.9
18.2
14.2%
20.6
-/1.2
1.76
60/-
11
-
14.6%
13.8
-/(1+1.2)
0.22
60/>8.5
11.5
5
15.2%
16
50/1
0.7
60/-
17.7
15.1
11.1%
19.2
460/1
(ex. DA)
0.83
60.5/15
18.1
11.5
3.6%
15.5
1504/1.8
0.46
Chowdhury 08
[5]
Law 10
[6]
Chowdhury 09
[7]
Chan 10
[8]
Lai 10
[9]
Martineau 10
[10]
Chen 11
[11]
Atesal 11
[12]
Floyd 05
[13]
Pfeiffer 07
[14]
Afshari 06
[15]
Valdes 06
[16]
Pfeiffer 07
[17]
This work
[18]
This work
[19]
60/9
18.6
15
15.1%
20.3
-/1
∼ 0.4
94/16
(PA cell)
23
-
5.8%
21.5
3320/2
48
61.5/-
16.2
11.2
4.3%
10.8
375/2.5
1.68
60/-
20
13.1
12.7%
18
240/4
0.98
85/24
21
11.5
3%
8
2475/(-2.5+0.8)
2.4
58/-
11.5
∼ 11
20.9%
4.2
26.4/1.2
0.98
60/-
23
∼ 21
6.3%
20
1200/4
3.42
62/> 10
20.1
19.7
18%
20.6
353/1.8
0.72
84/> 8
18
16
9%
27
395/2.5
0.68
This work
56/> 9.3
14
12
14%
12.2
135.5/1.2
0.58
Technology
Topology
90 nm
CMOS
90 nm
CMOS
90 nm
CMOS
65 nm
CMOS
65 nm
CMOS
65 nm
CMOS
65 nm
CMOS
130 nm
SiGe-BiCMOS
120 nm
SiGe-BiCMOS
130 nm
SiGe-BiCMOS
130 nm
SiGe-BiCMOS
130 nm
SiGe-BiCMOS
130 nm
SiGe-BiCMOS
130 nm
SiGe-BiCMOS
130 nm
SiGe-BiCMOS
65 nm
CMOS-SOI
3-stage transformer-coupled,
diff CS
4-way combining,
2-stage CS
2-way combining, 3-stage
transformer-coupled, CS
3-stage transformer-coupled,
diff CS
8-way combining,
3-stage CS
8-way combining, 2-stage
cascode CS
4-way combining, 3-stage
transformer-coupled CS
Quasi-optical 9-way
combining, 4-stage CE
2-stage diff CE with
open/short-circuited stubs
1-stage cascode CE,
No combining
4-way combining, 2-stage
cascode CE
1-stage Class-E CE
4-way combining, diff
cascode CE
4-way combining, 3-stage
transformer-coupled CB
4-way combining, 3-stage
transformer-coupled CB
2-way combining, 2-stage
transmission-line-coupled cascode+CS
Chapter 5. Power Amplifier Prototype Testing and Performance
Freq./BW−3dB
(GHz)
References
5.2.2
139
Performance Comparisons
Table 5.1 summarizes and compares the performance of the PAs developed in this work
with other PAs reported in the recent literature. The 60 GHz SiGe-BiCMOS prototype
produces the highest output power, PAE, and gain at the same (or lower) supply voltage
through 4-way combining. In addition, the transformer-coupled PA topology adopted in this
work occupies a relatively small chip area [5] [8] [11], and it is also frequency scalable. The
wafer-scale, free-space power combining PA [12] realizes approximately 3 dB greater output
power at the cost of a factor of 66 times larger chip area and 9 times higher DC power
consumption. The PA using open/short circuited stubs for matching [13] also consumes
more than twice the chip area and reaches just 4.3% peak-PAE. The SiGe PA reported
in [14] delivers 20 dBm output power without combining, but requires a 4 V supply and
peak-PAE is 5.3% lower. This validates the suitability of our power combining PA topology
for operation from relatively low supply voltages. The PA in [16] reaches a peak-PAE of
20.9% using a single-stage class-E design, but has 8.6 dB lower output power and 16.4 dB
lower power gain. Although 8-way combining can ideally provide 3 dB higher power than
4-way combining, both the PAs in [9] and [10] realize approximately 2 dB lower saturated
power and poorer peak-PAE of 11.1% and 3.6%, respectively. The efficiency of our low-loss
transformers at mm-wave is advantageous compared to the 8-way design from [9][10]. The
amplifiers developed in this work have also achieved excellent reverse isolation (> 51 dB)
through the use of cross-coupled capacitive neutralization, which guarantees unconditional
stability of the mm-wave PA.
Fig. 5.16 highlights and compares the saturated output power, peak-PAE and chip area of
all the 60 GHz-band PAs in Table 5.1. A cost-effective mm-wave PA design should achieve
high output power and efficiency with a small chip area. Located at the top right corner of
Fig. 5.16, the PA developed in this work has attained the best compromise between these
performance metrics at the current time of writing.
References
[1] A. Ferrero and U. Pisani, “An improved calibration technique for on-wafer large-signal transistor characterization,” IEEE Transactions on Instrumentation and Measurement, vol. 42, no. 2, pp. 360–364,
Apr. 1993.
[2] G. Avenier, M. Diop, P. Chevalier, G. Troillard, N. Loubet, J. Bouvier, L. Depoyan, N. Derrier,
M. Buczko, C. Leyris, S. Boret, S. Montusclat, A. Margain, S. Pruvost, S. T. Nicolson, K. H. K.
Yau, N. Revil, D. Gloria, D. Dutartre, S. P. Voinigescu, and A. Chantre, “0.13µm SiGe BiCMOS technology fully dedicated to mm-wave applications,” IEEE Journal of Solid-State Circuits, vol. 44, no. 9,
pp. 2312–2321, Sept. 2009.
[3] F. Gianesello, S. Montusclat, B. Martineau, D. Gloria, C. Raynaud, S. Boret, G. Dambrine, S. Lepilliet,
and R. Pilard, “65nm HR SOI CMOS technology: emergence of millimeter-wave SoC,” in Proc. of
IEEE-RFIC, Jun. 2007, pp. 555–558.
[4] A. Siligaris, Y. Hamada, C. Mount, C. Raynaud, B. Martineau, N. Deparis, N. Rolland, M. Fukaishi,
and P. Vincent, “A 60 GHz power amplifier with 14.5 dBm saturation power and 25% peak-PAE in
CMOS 65 nm SOI,” IEEE Journal of Solid-State Circuits, vol. 45, no. 7, pp. 1286–1294, Jul. 2010.
[5] D. Chowdhury, P. Reynaert, and A. M. Niknejad, “A 60GHz 1V + 12.3dBm transformer-coupled wideband PA in 90nm CMOS,” in Technical Digest of IEEE-ISSCC, Feb. 2008, pp. 560–635.
140
Chapter 5. Power Amplifier Prototype Testing and Performance
[6] C. Y. Law and A. V. Pham, “A high-gain 60GHz power amplifier with 20dBm output power in 90nm
CMOS,” in Technical Digest of IEEE-ISSCC, 2010, pp. 426–427.
[7] D. Chowdhury, P. Reynaert, and A. M. Niknejad, “Design considerations for 60 GHz transformercoupled CMOS power amplifiers,” IEEE Journal of Solid-State Circuits, vol. 44, no. 10, pp. 2733–2744,
Oct. 2009.
[8] W. L. Chan and J. R. Long, “A 58-65 GHz neutralized CMOS power amplifier with PAE above 10% at
1-V supply,” IEEE Journal of Solid-State Circuits, vol. 45, no. 3, pp. 554–564, Mar. 2010.
[9] J. W. Lai and A. Valdes-Garcia, “A 1V 17.9dBm 60GHz power amplifier in standard 65nm CMOS,” in
Technical Digest of IEEE-ISSCC, Feb. 2010, pp. 424–425.
[10] B. Martineau, V. Knopik, A. Siligaris, F. Gianesello, and D. Belot, “A 53-to-68GHz 18dBm power
amplifier with and 8-way combiner in standard 65nm CMOS,” in Technical Digest of IEEE-ISSCC,
Feb. 2010, pp. 428–429.
[11] J. S. Chen and A. M. Niknejad, “A compact 1V 18.6dBm 60GHz power amplifier in 65nm CMOS,” in
Technical Digest of IEEE-ISSCC, Feb. 2011, pp. 432–433.
[12] Y. A. Atesal, B. Cetinoneri, M. Chang, R. Alhalabi, and G. M. Rebeiz, “Millimeter-wave wafer-scale
silicon BiCMOS power amplifiers using free-space power combining,” IEEE Transactions on Microwave
Theory and Techniques, vol. 59, no. 4, pp. 954–965, Apr. 2011.
[13] B. A. Floyd, S. K. Reynolds, U. R. Pfeiffer, T. Zwick, T. Beukema, and B. Gaucher, “SiGe bipolar
transceiver circuits operating at 60 GHz,” IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp.
156–167, Jan. 2005.
[14] U. R. Pfeiffer and D. Goren, “A 20 dBm fully-integrated 60 GHz SiGe power amplifier with automatic
level control,” IEEE Journal of Solid-State Circuits, vol. 42, pp. 1455–1463, 2007.
[15] E. Afshari, H. Bhat, X. F. Li, and A. Hajimiri, “Electrical funnel: A broadband signal combining
method,” in Technical Digest of IEEE-ISSCC, 2006, pp. 751–760.
[16] A. Valdes-Garcia, S. Reynolds, and U. R. Pfeiffer, “60GHz class-E power amplifier in SiGe,” in Proc.
of IEEE-ASSCC, Nov. 2006, pp. 199–202.
[17] U. R. Pfeiffer and D. Goren, “A 23-dBm 60-GHz distributed active transformer in a silicon process
technology,” IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 5, pp. 857–865, May
2007.
[18] Y. Zhao and J. R. Long, “A wideband, dual-path, millimeter-wave power amplifier with 20 dBm output
power and PAE above 15% in 130 nm SiGe-BiCMOS,” IEEE Journal of Solid-State Circuits, vol. 47,
no. 9, pp. 1981–1997, Sept. 2012.
[19] Y. Zhao, J. R. Long, M. Spirito, and A. B. Akhnoukh, “A +18dBm, 79–87.5GHz bandwidth power
amplifier in 0.13µm SiGe-BiCMOS,” in Proc. of IEEE-BCTM, Oct. 2011, pp. 17–20.
Chapter 6
A Digitally-Controlled, Differential Distributed
Amplifier MZM Driver
Previous chapters described a wideband PA power combining technique realized by integrating compact, monolithic transformers on chip. Another potential circuit application example
is the distributed amplifier (DA), which incorporates a signal-splitting transmission line at
the input and a power-combining transmission line at the output. The gain-bandwidth advantage of the DA has enabled its application in ultra-wideband (UWB) and high-speed
systems, such as pulse-based imaging [1], optical communications (e.g., modulator driver [2],
or baseband amplifier [3]), and high-speed instrumentation [4]. The modulator driver is the
focus of the work described in this chapter.
Electronics for optical communication have been dominated historically by III–V compound
semiconductor technologies, such as gallium arsenide (GaAs) and indium phosphide (InP) [5]
[6] [7]. The research objective in this section of the thesis is to demonstrate a fully-integrated
DA suitable for driving a balanced, Mach-Zehnder (MZ) optical modulator in a production
silicon IC technology. The chapter begins with a review of the previously published driver
designs and an analysis of the limitations inherent in conventional DA-based MZ modulator driver circuits. The proposed driver topology, its operating principle and design details
of the building blocks are then described. The layout, lab test setup, experimental results
of the driver prototype, and a comparison of performance with commercial products and
other recently published designs are presented afterwards. A detailed analysis of the power
consumption distribution in the prototype and recommendations for a lower-power implementation finalize the chapter.
6.1
Mach-Zehnder Modulator Driver
Modern multi-Gb/s optical systems rely upon external modulation in the transmit chain to
encode the optical carrier. The Mach-Zehnder interferometer is favored over electroabsorption
modulators because of its broader optical bandwidth, a large extinction ratio (i.e., ratio of
on to off intensity) and zero or tunable output frequency chirp [8]. However, the electronic
driver circuit remains one of the most challenging blocks to design in an optical transceiver
for two primary reasons. Firstly, the MZ modulator requires a relatively large switching
141
142
Chapter 6. A Digitally-Controlled, Differential Distributed Amplifier MZM Driver
Figure 6.1: Transistor cut-off frequency as a function of collector-emitter breakdown voltage
open base (i.e., BVCEO ) for a variety of commercial and prototype SiGe-BiCMOS technologies [16].
voltage, Vπ , from the driver stage (e.g., 5.1 V [9]). Thus, commercial MZ modulator drivers
are usually implemented in IC technologies with greater than 5 V breakdown (e.g., GaAs),
such as the examples from references [10] and [11]. Secondly, the driver circuit is required to
be broadband in order to preserve signal fidelity, e.g., the minimum required bandwidth is
∼ 7.5 GHz in a 10 Gb/s system using on-off keying modulation [11]. A traveling-wave MZ
modulator with 50 Ω characteristic impedance also requires the driver circuit to have return
loss better than 10 dB across the entire signal bandwidth.
6.1.1
Design Challenges
The trade-off between gain-bandwidth product and device terminal breakdown voltage (i.e.,
Johnson’s limit [12]) is a barrier to high-performance optical modulator driver circuit implementation in silicon technology, as described in Chapter 1. The original limit of the product
of bipolar junction transistor cut-off frequency and BVCEO was estimated to be around
200 GHz·V [12]. Although it has been proven that this limit can be exceeded [13] (e.g.,
500 GHz·V in [14] [15]), modern SiGe-BiCMOS technologies with fT above 200 GHz still
have BVCEO smaller than 2 V (see Fig. 6.1) [16]. Consequently, the RF power output and
voltage swing are compromised. Transformer power combiners may be used to increase the
voltage swing across a 50 Ω load beyond BVCEO in power amplifiers, however, the bandpass nature of the transformer frequency response makes it inapplicable to the MZ modulator driver, which is required to have a predominantly low-pass frequency response. The
circuit prototype developed in this work targets 3 Vp−p single-ended output swing across
50 Ω at the 10 Gb/s data rate. The IBM 180 nm SiGe-BiCMOS 7WL technology with
fT ·BVCEO = 198 GHz·V features high-performance NPN transistors and BVCEO of 3.3 V
6.1. Mach-Zehnder Modulator Driver
143
Table 6.1: Performance summary of the modulator driver designs from the recent literature.
AlGaAs/GaAs
50 GHz fT [10]
0.15 µm GaAs
[21]
0.18 µm BiCMOS
120 GHz fT [22]
0.18 µm
CMOS [23]
0.25 µm
BiCMOS [24]
AlGaAs-InGaAsAlGaAs [18]
1.5 µm
InP-DHBT [25]
BiCMOS
80 GHz fT [26]
0.25 µm BiCMOS
180 GHz fT [27]
1
Data
rate
(Gbps)
Output
swing
(Vp−p )
RMS/Pk
jitter (ps)
Rise/fall
20-80%
(ps)
10
6
1–2
38/38
10
7.4
2.5/-
<25
10
7.6
-/-
40/40
10
8
0.7/14
10
5
40
Output
return
loss (dB)
>10
(<20 GHz)
>10
(15 GHz)
PDC
(W)
Area
(mm2 )
3.2
13.2
2.6
2.1
-
3.7
1.2
42/42
-
0.6
0.68
-/-
45/30
-
0.68
0.54
6
1.1/5.6
<10
1.1
6.7
43
6
0.7/-
9/9
2.7
5.4
40
2.5
-/-
15/15
1
>10
(32 GHz)
1.13
1.2
40
6
1.4/-
15/15
1
-
1.35
0.72
1
1
>10
(45 GHz)
-
Amplifier
topology
DA,
diff.
DA,
SE.
Lumped,
diff.
Lumped,
diff.
Lumped,
diff.
DA,
SE.
DA,
diff.
DA,
diff.
Lumped,
diff.
Value estimated from eye diagrams.
[17]. It is selected for the prototype realization in this work. However, this technology has
a relatively large parasitic capacitance compared to newer technology nodes with fT above
300 GHz (see Fig. 6.1) that (potentially) limits the driver’s operating bandwidth. Therefore,
distributed amplifiers, which absorb the capacitive parasitics of active devices into the passive transmission line design, are often utilized in order to meet the broadband operation
required for the MZ modulator driver circuit [18] [19] [20].
6.1.2
Literature Review
Table 6.1 summarizes and compares the previously published MZ modulator driver designs
in the recent literature. The designs in both III-V and silicon technologies are capable of
delivering an output swing of 6 Vp−p . However, the 10 Gb/s silicon drivers show more eye
closure due to slower rise/fall times and larger timing jitter [22] [23], or waveform asymmetry
[24], compared to their III-V counterpart in [21]. At 40 Gb/s, the III-V drivers in [18] and [25]
demonstrate rise and fall times smaller than 10 ps, as opposed to 15 ps for the silicon designs
in [26] and [27]. It is also noticed that the distributed amplifier driver designs have a faster
edge speed (i.e., rise and fall times) than lumped amplifier drivers, especially at a higher data
rate (e.g., 40 Gb/s vs. 10 Gb/s). The lumped amplifier driver design in [27] exhibits similar
edge speed as the DA in [26], however, it was fabricated in a SiGe-BiCMOS technology with
more than double the transistor cut-off frequency (i.e., 180 GHz vs. 80 GHz). The drivers
for 80 Gb/s and 100 Gb/s communications rely (exclusively) on the distributed amplifier
topology because of its broad bandwidth advantage [2] [28]. Moreover, the wideband return
loss of the lumped amplifiers in [22] [23] is insufficient to drive a traveling-wave, MachZehnder modulator. Therefore, this work targets development of a silicon-based distributed
144
Chapter 6. A Digitally-Controlled, Differential Distributed Amplifier MZM Driver
Figure 6.2: Simplified circuit model of a conventional distributed amplifier.
amplifier which performance comparable to its III-V counterparts, and excellent output
return loss as required for driving the Mach-Zehnder interferometer.
However, several drawbacks of the conventional DA topology, which are elaborated in the
next section, constrain its design flexibility and applications, especially in a differential implementation where balanced outputs are required to drive a push-pull MZ modulator. For
example, two differential drivers are needed when differential quadrature phase-shift keying modulation (i.e., DQPSK) is used for higher data rates. Therefore, a new DA topology
which can mitigate the performance impairments of conventional DAs is needed. The target
data rate for the proof-of-concept prototype fabricated in the IBM’s 180 nm SiGe-BiCMOS
technology is 10 Gb/s. However, the proposed topology is applicable to higher date rates if
a higher performance technology node is used. The development trend for silicon-based MZ
modulators with a lower switching voltage also relaxes the requirement on device breakdown
voltage, thereby facilitating the migration towards more advanced silicon technologies for
higher data rates [29] [30].
6.2
Limitations of the Conventional MZ Modulator Driver
A simplified schematic of the conventional DA topology shown in Chapter 1 is re-visited
again in Fig. 6.2. Transconductor Gm is a unilateral amplifier (e.g., cascode) with lumped
parasitic capacitances at the input and output (Cin and Cout in Fig. 6.2). Dissipation at the
input (e.g., rgg for a FET, or rbb′ and re of an HBT) is modeled by rin , while rout represents
the output resistance of the Gm stage. The output transmission line sums the currents
produced by the N amplifying stages. The outputs of stages 1 to N add constructively
when the time delay between stages along the input line (tin ) and along the output line
(tout ) are synchronized. Distortion that degrades rise/fall times seen at the load results
when tin and tout are not equal. The quality and integrity of the output waveform is also
affected by mismatch between the characteristic impedance of either transmission line and
its termination impedance (typically 50 Ω), with waveform distortion and timing jitter being
typical impairments caused by mismatch. Resistor ZT 1 terminates the input line, while ZT 2
6.2. Limitations of the Conventional MZ Modulator Driver
145
terminates the wave traveling away from the load on the output line. Mismatches arising from
non-ideal packaging parasitics can be minimized when ZT 1 and ZT 2 are wideband resistors
fabricated on chip. The following section presents the design difficulties associated with this
conventional DA topology in detail from perspectives of the operating bandwidth and the
number of DA gain stages.
6.2.1
Bandwidth Limitations
The maximum bandwidth of the conventional DA in Fig. 6.2 is largely determined by the
cut-off frequencies of the capacitively loaded input and output transmission lines. Another
bandwidth limiting factor is the back termination resistor (i.e., ZT 1 and ZT 2 ) due to its
capacitive parasitics.
A.
Input Transmission Line
The cut-off frequency (ωc ) of a lossless transmission line may be defined by Eq. 6.1 [31]
q
ωc = 2/ L(C + Cload )] = 2/(Zo,load (C + Cload )),
(6.1)
where L and C are the series inductance and shunt capacitance from the transmission line
in between two amplifier stages, respectively. Cload is the capacitive loading added to the
transmission line by the active device, and Zo,load is the loaded characteristic impedance of
the line. Given a common-emitter (CE) or cascode configured amplifier stage in a SiGeBiCMOS technology, the input capacitance at the base terminal is generally much larger
than that at the collector. For example, simulation predicts that a 0.24×20 µm2 cascode
stage has Cin and Cout of 800 fF and 62 fF, respectively. Thus, the input transmission line
in Fig. 6.2 limits the DA bandwidth, because the output line presents a 10 times higher cutoff frequency for a given Zo,load (i.e., Cin ≫Cout ). Moreover, in order to match signal delay
between the input and output, extra capacitance needs to be added at the DA output [32].
Consequently, it reduces the output line cut-off frequency and narrows the DA bandwidth.
The large loading capacitance for the input transmission line also poses a difficulty in modern
(Bi)CMOS technologies when realizing the required 50 Ω input impedance matching. Eq. 6.2
relates the unloaded transmission line characteristic impedance (Zo for Cload = 0) to the
loaded value (Zo,load with Cload )
q
Zo,load = Zo / 1 + Cload /C,
(6.2)
where Zo,load equals 50 Ω. Given a 600 µm long, 10 µm wide transmission line on 3 µm top
copper layer sitting 5 µm above 10 Ω·cm silicon substrate, simulations predict that C and
Cload in Eq. 6.2 when loaded by a 0.24×20 µm2 sized HBT amplifier biased near peak-fT are
69 fF and 800 fF, respectively. When Zo,load is 50 Ω, it leads to an unloaded TXL characteristic
impedance of 177 Ω. However, Zo for the 10 µm wide transmission line
q described above is
just 85 Ω from simulation. High-characteristic-impedance lines (Zo = L/C) are difficult to
146
Chapter 6. A Digitally-Controlled, Differential Distributed Amplifier MZM Driver
realize in that the thin dielectric and back-end-of-line stack thickness leads to a relatively
large parasitic capacitance ‘C’. Moreover, substrate shielding, which inhibits energy coupling
to minimize signal losses, reduces the characteristic impedance further due to the additional
capacitive loading, making it impossible to implement in some technologies. By contrast,
the unloaded characteristic impedance of the output line is 69 Ω, since Cload from the same
transistor is just 62 fF.
Another disadvantage of the conventional DA using a pair of transmission lines is that layout
flexibility is also compromised by the time delay matching required between the input and
output lines. It is exacerbated when implemented differentially, and often leads to a large chip
area (e.g., 13.2 mm2 in [10] and > 3.5 mm2 in [33]). From this analysis, it can be concluded
that the input, rather than the output transmission line, tends to limit the performance of
a conventional DA. Thus, design innovations are needed at the DA input interface in order
to maximize its operating gain and bandwidth, save chip area, and promote silicon process
compatibility.
B.
Back Termination Resistor
The analyses above assume that the input and output transmission lines are terminated
at both ends with ideal 50 Ω resistors. Simulations predict that a lossless 50 Ω artificial
transmission line (e.g., 150 fF capacitance and 375 pH inductance per section) realizes a
return loss of 10 dB up to 30 GHz with an ideal 50 Ω termination. However, it drops to
21 GHz when 100 fF shunt capacitance is added to the termination. Thus, if an improved
DA input interface eliminates the bandwidth limitation imposed by the input line, parasitic
capacitance associated with the back termination resistor could decrease the cut-off frequency
of the output line significantly. This problem becomes more severe when the resistor power
handling capacity is also taken into account, because a larger area resistor capable of handling
high power levels may have even more parasitic capacitance.
As shown in Fig. 6.2, the amplifier stages are biased via the termination resistor ZT 2 , which
conducts all of the DC and AC currents. Assuming a single-ended, peak-to-peak output
voltage swing of 3–5 V in a differential limiting amplifier (i.e., 120–200 mA total DC current), ZT 2 needs to dissipate 270–750 mW of power. This high level of power dissipation
across conventional polysilicon or TaN metal resistors increases its operating temperature
significantly (e.g., 150◦ C temperature rise for a 30 µm wide TaN resistor with 0.5 mA/µm
current density [34]), causing a large variation in resistance or even resistor failure due to
self-heating [34] [35]. A 50 Ω polysilicon resistor capable of dissipating 0.5 W power has a
parasitic capacitance of approximately 150 fF from simulation.
Bias-Ts could be used to supply DC bias current and reduce the power dissipated in the
termination resistor. However, it must be broadband and integrable for a monolithic design.
Previous attempts to build on-chip, wideband bias-Ts for DAs have failed to cover the lowGHz frequency band (e.g., below 15 GHz in [36]). Hence, a power resistor, that is capable of
dissipating 0.5–1 W power and has lower than 100 fF parasitic capacitance is required for a
wideband distributed amplifier that could be used in a multi-Gb/s optical system.
6.3. Digitally-Controlled DA Modulator Driver
6.2.2
147
Maximum Number of DA Stages
Assuming that the active devices are unilateral and that the input and output transmission
lines are terminated at their characteristic impedances, the current delivered to the load
from a N -stage DA is given by Eq. 6.3 [31] [37]
N
X
1
Iload,N = gm e−γo /2 [ Vin,k e−(N −k)γo ],
2
k=1
(6.3)
where γo is the propagation coefficient of the output line, Vin,k is the input voltage of the
kth amplifier stage and N is the total number of DA stages. Due to signal attenuation by
the loaded input and output lines, there is a maximum number of stages beyond which the
increase in signal output by adding another stage is smaller than the loss of signal due to the
added output line length for a conventional DA. This leads to a maximum gain at a given
frequency [31]. When the input and output time delays are synchronized, Eq. 6.4 defines the
upper limit on the number of stages (Nmax ) [31]
Nmax =
ln(αo /αi )
,
αo − αi
(6.4)
where αi and αo are the attenuation coefficients per section of the input and output transmission lines, respectively. Given a fixed output voltage swing (Vout ), the total DC current
(IDC ) drawn by a limiting amplifier remains the same (i.e., IDC = Vout /RL , where RL is the
load resistance), regardless of the number of stages. However, a smaller number of stages
leads to a higher current per amplifier stage and thus a larger transistor size in each stage.
The DA then requires a higher inductance (i.e., high characteristic impedance lines) in order
to absorb the increased parasitic capacitance, which narrows the DA bandwidth overall as
seen from Eqs. 6.1 and 6.2. Similarly, the current and device sizes need to be scaled up if a
higher gain per stage is desired for linear amplification in order to compensate for losses in
the passive transmission lines.
6.3
Digitally-Controlled DA Modulator Driver
Theoretically, increasing the number of amplifier stages in a DA is an effective method to extend the operating bandwidth and ease the transmission line design because the size of each
amplification device can be scaled down for smaller parasitic capacitance. However, Eq. 6.4
limits the viability of this approach. Therefore, it is expected that a DA with a lossless input transmission line (i.e., αi = 0) could overcome the limitations on operating bandwidth
and maximum number of DA stages described in the previous section. A new distributed
amplifier topology interfacing with an active, lossless input stage that is controlled digitally
is developed in this work, in order to mitigate the aforementioned disadvantages of conventional DAs. The differential output of the DA is intended to drive a balanced Mach-Zehnder
modulator.
148
Chapter 6. A Digitally-Controlled, Differential Distributed Amplifier MZM Driver
Assuming a lossless input line, the input signals for all of the stages are identical (i.e., Vin,k
is constant in Eq. 6.3), and thus the maximum number of stages is determined only by the
output line. As defined in Eq. 6.3, the load current and thus the output voltage increase
monotonically with an increase in the number of stages. However, the incremental current,
which is defined as the increase in current realized by adding an addition stage (i.e., the load
current difference between DAs with (N + 1) stages and N stages) normalized to the current
of a single-stage DA (i.e., Iload,1 ), tends to zero as the number of stages becomes large, as
seen from Eq. 6.5,
∆=
Iload,N +1 − Iload,N
= e−N ·αo .
Iload,1
(6.5)
Thus, the maximum number of stages can be expressed as a function of this normalized
current increment, as given by Eq. 6.6
Nmax,αi =0 = −
ln(∆)
.
αo
(6.6)
The maximum number of DA stages with a lossless input transmission line (i.e., αi = 0)
equals 3/αo when ∆ is 5%. For example, assume that the output line is 5 µm wide in 3 µm
thick copper, 5 µm above a 10 Ω·cm substrate, and a line length of 500 µm is needed between
two DA gain amplifiers to absorb the parasitic capacitance, simulation predicts that the total
attenuation coefficient is 0.03 Np at 5 GHz. Assuming that the input and output lines are
loaded by Rin = 300 Ω and Rout = 150 Ω, respectively, αi and αo are 0.15 Np and 0.23 Np
for this 500 µm long line, respectively. It is calculated from Eqs. 6.4 and 6.6 that Nmax and
Nmax,αi =0 when ∆ is 5% are 5 and 13, respectively. The Nmax,αi =0 increases to 20 when ∆ is
set to 1%. Therefore, the maximum number of stages increases significantly when the input
transmission line is made lossless. As described previously, such a configuration also has the
potential to increase the DA operating bandwidth and thus the data rate.
A block diagram of the proposed modulator driver prototype with a fully-digital input interface is shown in Fig. 6.3 [38]. It is a wideband DA consisting of 3 differential limiting
amplifier cells embedded in a synthetic transmission line. Signal current produced by each
cell is added constructively as it flows towards the 50 Ω loads. Two on-chip n+/n-well 50 Ω
termination resistors supply bias current to each DA cell and suppress back-traveling waves
on the output line, eliminating the need for external bias-Ts. Digital data latches replicate
the 10 Gb/s digital input signal. Each replica is equal in the amplitude and waveshape, but
its phase is defined by the latch retiming clock. A D-type latch instead of a D flip-flop (i.e., a
cascade of 2 latches) is used in order to save power and chip area. Synchronization between
the input and output is realized by phase shifting the latch retiming clocks under digital
control. Thus, the proposed modulator driver is scalable in the number of amplifier cells
within the limit defined in Eq. 6.6, as the attenuation and bandwidth limitations from the
analog input passive line in the conventional DA described in the previous section (Section
6.2) are eliminated. Moreover, precise analog matching between the input and output lines
6.3. Digitally-Controlled DA Modulator Driver
149
Vcc
DB2
DB3
CB2
CB3
CB1
DAC and
Current Adder
2:1 Selector
Figure 6.3: Block diagram of the digitally-controlled modulator driver prototype.
is not required, and thus the layout restrictions and chip area consumed by the input line in
a conventional DA are no longer design constraints.
The operating bandwidth of the new driver topology proposed in this work is likely limited
by the speed of the input logic (i.e., digital latches) rather than the output line. Since each
limiting amplifier in the DA chain is driven by a copy of the input data with an identical
amplitude, the number of DA stages can be increased in order to minimize the capacitive
loading for the output line, maximizing its cut-off frequency (see Eq. 6.1). Simulations predict
that the cut-off frequency of the output line in this 3-stage prototype driver is 40 GHz (see
Section 6.3.6). It could reach 80 GHz if a 6-stage DA is employed as both the series inductance
and shunt capacitance for the output line reduces by one half, which is beyond the peak-fT of
60 GHz for the HBT in the 180 nm SiGe-BiCMOS technology. The summed emitter length
of the output transistors in all of the limiting amplifiers remains the same regardless of the
number of DA stages because the transistors need to conduct a fixed, total DC current for a
given output voltage swing across a 50 Ω or 100 Ω load. Its associated parasitic capacitance
at the DA output therefore does not change dramatically. As a result, the total physical
length of the output line required to absorb the parasitic capacitance should not be affected
with the number of stages as well. Thus, losses from the output line are not increased as the
number of stages increases. A stand alone simulation of the limiting amplifier designed for the
10 Gb/s demonstrator shows that it can support full swing at its output for 32.5 Gb/s data
rate. However, the digital latch, which is loaded by a limiting amplifier in each stage, must
provide sufficient voltage output required by the limiting amplifier for full switching. Thus,
150
Chapter 6. A Digitally-Controlled, Differential Distributed Amplifier MZM Driver
it suffers from a more stringent performance trade-off between speed, output voltage swing
and power consumption, thereby potentially limiting the DA bandwidth. Simulations predict
that the maximum data rate for the digital latch loaded by the limiting amplifier designed
for the 10 Gb/s prototype driver (see Fig. 6.9) is 20 Gb/s, which is the lowest compared to
the limiting amplifier and the output line. Note that the analysis above assumes that the
clock phase shifter and buffers in the driver topology do not (and should not) become the
speed limiting factor.
6.3.1
Distributed LA with a Periodically-Loaded Output Line
The output voltage and efficiency of the distributed limiting amplifier topology is projected
in this section. In order to simplify the derivation of a compact result, it is assumed that
amplification is distributed across the length of the output line in the DA. Given that assumption, the total voltage at the load (vout ) from Fig. 6.3 can be written as:
vout =
Zo Z N lout
Idriver (x)e−γout (N lout −x) dx,
2 0
(6.7)
where the incremental current Idriver (x) produced by N limiting stages (N = 3 in Fig. 6.3)
is summed from the back termination (x = 0) to the load (x = N lout ). The propagation
constant γout for each section of the output line between stages (length, lout ) is assumed
identical. Note that only one-half of the driver current flows through the load, and that the
DA is properly terminated as the load is equal to the characteristic impedance (Zo ) of the
output line. The uniformly distributed driver current can be expressed as
Idriver (x) =
IBias −j(φin /lout )x
e
.
N lout
(6.8)
The exponential term in Eq. 6.8 accounts for the phase of the current injected into the output
line (φin , referenced to x = 0) defined by the digital input to each stage. For an ideal LA,
the incremental current Idriver (x) is the total bias current (IBias ) divided by the total line
length (N lout ). Substitution of Eq. 6.8 into Eq. 6.7 and evaluation of the integral gives
vout
Zo IBias −jN φin (1 − e−N αout lout )
=
e
,
2N
αout lout
(6.9)
where the input amplitude driving each stage is assumed identical for the digitally-controlled
DA and that the input and output signals at each stage are phase synchronized (i.e.,
βout lout = φin ). This implies that: γout lout − jφin = αout lout , as γout = αout + jβout .
Approximating the decaying exponential in Eq. 6.9 by a Taylor series expansion gives a
compact expression for the magnitude of the single-ended output voltage |vout |,
|vout |=
Zo IBias
N αout lout (N αout lout )2
[1 −
+
− · · ·].
2
2
8
(6.10)
6.3. Digitally-Controlled DA Modulator Driver
151
Note that Eq. 6.10 predicts that the effect of the output line is negligible when the total
attenuation across the line, N αout lout , is much less than 2. The power at the load (assuming
random transmit data with an equal density of 1’s and 0’s) is
Pout =
( 21 |vout |)2
Zo (IBias )2
N αout lout (N αout lout )2
=
[1 −
+
− · · ·]2 .
Zo
16
2
8
(6.11)
As long as the attenuation of the output line is sufficiently low (i.e., N αout lout ≪ 2), Pout
approaches Zo (IBias )2 /16, which is also the driver power output at low frequency. Note that
Pout for a differential driver is two times the power of Eq. 6.11, as the same bias current is
steered between the 2 outputs.
The efficiency of a digitally-controlled DA with differential outputs is given by
ηdriver =
Vsupply [1 +
(IBias Zo )/8
Ioverhead
+ (N
IBias
− 1) IIinput
]
Bias
,
(6.12)
where Vsupply is the global supply voltage, Ioverhead is the current consumed by all circuits
shared by the driver stages (e.g., input data retiming and I/Q generation in Fig. 6.3), and
Iinput is the current drawn by the digital circuitry supplying the signal to each LA stage (e.g.,
latch, phase shifter and predriver in Fig. 6.3). The efficiency of just the driver output stages
alone, IBias Zo /(8VSupply ), is typically well below 10%. DAs are ultrawideband circuits, and
as such do not offer efficiencies comparable to narrowband RF power amplifiers. Eq. 6.12
indicates that the driver should be operated from the lowest supply voltage possible in order
to maximize efficiency, and that the fixed power consumption terms: N , Ioverhead and Iinput
should be kept as small as possible through efficient digital design techniques. A detailed
power analysis of the driver prototype is provided in Section 6.4.4.
6.3.2
Clock and Data Timing Control
As shown in Fig. 6.3, the external data and clock are 50 Ω terminated at the chip periphery,
and then re-synchronized on chip by a D latch. The synchronized data signal is buffered
before input to the second and third latches. Fig. 6.4 illustrates the timing control in the
data and clock paths, where Din1 –Din3 and Clk1 –Clk3 are the data and retiming clock
inputs for the first, second and third latches, respectively. The rising edges of the 3 clocks
are indicated by upward pointing arrows for simplicity. The propagation delay between the
data inputs of two adjacent latches is represented by tdata , and the phase difference between
two clocks (i.e., tclk ) is defined by the transmission line delay at the DA output. The buffered,
external clock is used to retime the input data, but its opposite phase (Clk1 ) is fed to the
latch in the first stage of the DA. This ensures that the clock samples almost exactly at
the middle of the bit interval (i.e., Din1 ). The time difference between Clk1 and Din1 equals
(Tclk /2)-tsyn , where tsyn is the propagation delay time of the synchronization latch. In order
to avoid sampling ambiguity (e.g., a data transition near the clock edges) and to ensure the
correct retiming (as shown in Fig. 6.4a), the following relationships in Eqs. 6.13 and 6.14
must be satisfied simultaneously for the second and third latches, respectively.
152
Chapter 6. A Digitally-Controlled, Differential Distributed Amplifier MZM Driver
a) Correct timing alignment
b) Improper timing due to excessive data delay
Figure 6.4: Clock and data timing of the 3 digital latches.
and
tdata < Tclk /2 − tsyn + tclk
(6.13)
2tdata < Tclk /2 − tsyn + 2tclk
(6.14)
Thus, the data delay (tdata ) must be kept smaller than Tclk /4 − tsyn /2 + tclk (as seen in
Fig. 6.4a). Otherwise, as highlighted by the dashed circle in Fig. 6.4b, the clock of the third
latch (Clk3 ) misses the data ‘1’ due to excessive data delay. Simulations predict that the
propagation delay of the synchronization latch is 15 ps at 10 Gb/s. Assuming that the time
delay between two adjacent DA output stages is 10 ps, tdata must be smaller than 27.5 ps.
Delay time in the data path arises from the ECL buffer between 2 latch inputs (i.e., DB1 and
DB2 in Fig. 6.3) and the propagation delay from interconnects on chip. Simulations predict
that the ECL data buffer delay is 12 ps, which requires that the additional propagation delay
from interconnects to be smaller than 15.5 ps. Phase alignment between the 3 clocks is easily
realized using a vector-sum phase shifter that covers a 360◦ phase range [39].
Replicating the 10 Gb/s data digitally ensures that each DA cell is driven to saturation
by an identical copy of the input signal, thereby eliminating the dispersion, attenuation,
ringing and pulse distortion inherent in an analog implementation. The clock retiming the
input data on chip is the phase reference for the first latch, and it is used to generate the
differential, quadrature (I, Q) clocks on chip. The quadrature clocks are summed vectorially
to realize the retiming clocks for the second and third latches which define the signal phase
at each latch output for the DA cells [39]. The most significant bits b4,5 (or b10,11 ) in Fig. 6.3
control the phase shifter to 90◦ resolution using a 2:1 ECL selector. At 10 GHz, the currentweighted summation of the I and Q clocks under control of the 4 LSBs (b0−3 or b6−9 in
Fig. 6.3) produces a variable-phase, low-jitter clock with 1.56 ps (ideal) timing resolution
and 360◦ of clock phase control.
6.3. Digitally-Controlled DA Modulator Driver
a) Quadrature VCO
153
b) RC-CR single-stage polyphase filter
c) Doubler-divider chain
Figure 6.5: On-chip quadrature clock generation options.
6.3.3
Quadrature Clock Generation
On-chip quadrature signals can be generated in many ways, of which three of the most
commonly used methods are shown in Fig. 6.5. The first topology uses a quadrature voltagecontrolled oscillator (i.e., IQ-VCO), which consists of two VCOs cross-coupled to each other
in a positive feedback [40]. The IQ-VCO has 90◦ phase difference between its two outputs.
However, a low-jitter clock signal is available in optical systems, thereby eliminating the
need to regenerate it from a VCO in the driver circuit. Thus, an RC-CR polyphase filter in
Fig. 6.5b can be used to split the differential clock into two balanced quadrature outputs [41].
154
Chapter 6. A Digitally-Controlled, Differential Distributed Amplifier MZM Driver
a) Frequency doubler
b) Quadrature divider
Figure 6.6: Schematic of the regenerative frequency doubler and quadrature divider.
However, it is susceptible to component mismatch, narrow bandwidth and signal losses, and
requires additional buffers in order to drive the two 2:1 selectors in Fig. 6.3. Therefore, the I
and Q clocks in this work are generated by a third method consisting of a frequency doubler
followed by a quadrature divide-by-two circuit (see Fig. 6.5c) [42]. The external input clock
at frequency f0 is injected into the doubler, and its output at 2f0 is used to lock the divider.
Both the frequency doubler and divider in this work utilize a regenerative scheme [42]. Each
circuit consists of two active multipliers connected in a positive feedback loop.
Fig. 6.6 shows simplified schematics of the frequency doubler and divider. Transistors Q3−6
and Q7−12 in Fig. 6.6a form the two multipliers in a positive feedback loop. Each multiplier
contributes 90◦ phase shift and produces quadrature outputs across load resistors RL1,L2 and
RL3,L4 . The differential 10 GHz timing clock is injected via transistors Q1,2 . The current
outputs of Q1,2 are fed to the output of the first multiplier to injection lock the feedback
6.3. Digitally-Controlled DA Modulator Driver
155
Differential voltage swing, in mV
300
200
Q
I
100
0
-100
-200
100 ps
-300
9.6
9.7
9.8
9.9
10.0
Time, in ns
Figure 6.7: Simulated quadrature signal at the output of the doubler-divider chain.
loop. Extra transistors Q7,10 are added to the second multiplier in order to minimize the
asymmetry between the two multipliers caused by the addition of injecting transistor pair
Q1,2 . A differential, double-frequency output at 20 GHz is generated at the emitters of
transistors Q3,4 with respect to Q8,9 .
The regenerative divider in Fig. 6.6b reverses the doubler operation. The 20 GHz signal is
pre-amplified by differential pair Q13,14 , and is then injected into the loop via transistors
Q25,26 after emitter follower buffering via Q15,16 . The balanced, quadrature clocks are taken
from the emitters of transistors Q19,20 and Q23,24 .
The cumulative delay in the positive feedback loop, which is dominated by the RC delay at
the output nodes of each multiplier, determines the self-oscillating frequency of the doubler
and divider circuits. Devices are sized to sustain oscillation above 10 GHz without the loading from the subsequent block (e.g., 14.7 GHz for the divider), and near 10 GHz when fully
loaded. A trade-off exists between the operating frequency and the output signal amplitude
(which is proportional to the load resistance). Post-layout simulations predict that the minimum differential amplitudes of the injecting signal required to lock the loop at 10 GHz are
15 mV and 40 mV for the frequency doubler and divider, respectively. Note that the doubler
is loaded by the divider, and that two, 2:1 selectors are connected to the divider as shown
in Fig. 6.3. The low level of signal required to injection lock the circuits validates that the
doubler and divider self-oscillate close to 10 GHz when their outputs are loaded. Fig. 6.7
plots the simulated differential quadrature outputs from the doubler-divider chain with the
single-ended, injected clock swing of 100 mVp−p . Biasing currents for the doubler and divider
are 12 mA and 7 mA, respectively. The pre-amplifier and the 20 GHz signal buffer (i.e.,
156
Chapter 6. A Digitally-Controlled, Differential Distributed Amplifier MZM Driver
Figure 6.8: Schematics of the clock phase control blocks.
Q13,14 and Q15,16 in Fig. 6.6b) consume 4 mA each. The output signal frequency shown in
Fig. 6.7 is 10 GHz, and the peak-to-peak voltage swing is 420 mV. The amplitude difference
between the I and Q paths is within 5% with precise quadrature of 89.7◦ . The frequency
locking range of the divider-doubler chain is from 7.6 GHz to 11.8 GHz with single-ended,
injected clock swing of 500 mVp−p from post-layout simulation.
6.3.4
Clock Phase Control
Note that this part of the work (and the digital latch below in Section 6.3.5) are designed
by a colleague, Leonardo Vera. It is included for documentation of the complete design.
Simplified schematics of the 2:1 selectors, 4-bit DAC, current adder and clock buffer are
given in Fig. 6.8. Transistors Q9−12 form a comparator, combinations of whose inputs (i.e.,
b4,5 and Vref 1 ) select one of the four quadrature phases. The selected quadrature clock signals
are generated across load resistors R1−4 . A current steering 4-bit DAC (i.e., b0−3 ) controls
the tail currents of differential pairs formed by transistors Q13,14 and Q15,16 . The summed
current is then converted to a voltage by differential amplifier Q17,18 with resistive feedback
(i.e., R6−9 ). A clock buffer re-shapes the signal waveform, and emitter followers Q27,28 and
Q33,34 DC-couple the buffer output to the latch clock input.
6.3.5
Digital Latch and Limiting Amplifier Stage
Fig. 6.9 shows a simplified schematic of the digital latch and DA limiting amplifier (LA).
The data input to the bases of transistors Q1,2 propagates to the outputs when the clock
is low, and held by latch transistors Q3,4 when the clock goes high. The latch outputs are
buffered by double emitter followers with feedback to reduce transient ringing effects.
A limiting amplifier is less sensitive to impairments such as overshoot and ringing in its
input signal compared to a linear amplifier [10]. Limiting or clipping of the binary input
signal also increases the harmonic content at the LA output, indicative of a fast edge speed
6.3. Digitally-Controlled DA Modulator Driver
157
Figure 6.9: Schematics of the latch and limiting amplifier cell.
(i.e., rise and fall times). The limiting amplifier used in the DA gain cell consists of a preamplifier, a Darlington pair and a differential common-base output stage. Transistors Q15,17
and Q16,18 compose a Darlington pair to minimize loading on buffer transistors Q13,14 and thus
reduce current consumption. Diode connected transistors Q19,20 are used for level shifting.
Compared to a simple differential pair, the input voltage swing required by a Darlington pair
for a full-swing of the tail current is approximately doubled. Thus, the latch output signal
is pre-amplified by transistors Q11,12 and buffered by Q13,14 to ensure the fastest edge speed
before feeding the signal to the limiting amplifier (i.e., transistors Q15−22 ).
A 3 Vp−p output swing across a 50 Ω load requires a total current swing of 120 mA from
the limiting amplifier stages. Approximately one-half of the signal current switched by each
LA stage is dissipated in the 50 Ω back termination resistor. The current consumption in
each LA stage, the number of DA stages, the cut-off frequency of the output line and the
chip area are interdependent. Three LA stages is used in this work. Each Darlington pair
consumes 40 mA and adds 1 V to the output voltage swing. Each common-base transistor
in the LA output stage presents total shunt capacitance at the collector of approximately
160 fF that must be absorbed in the output transmission line design.
The BVCEO of the HBT is 3.3 V for the technology used for this work [43]. Grounding the
(common) bases of the transistors in the final output stage extends the collector-emitter
breakdown voltage of Q21,22 to near BVCBO (as described in Chapter 4) [44]. A differential
output voltage swing beyond the targeted 6 Vp−p could therefore be realized by adding more
DA cells and extending the output line. Using a cascode in the LA stages raises the output
impedance and reduces resistive loading on the output transmission line, thus leading to a
more efficient DA overall.
6.3.6
Output Transmission Line and On-chip Back Termination
The differential DA cell outputs are connected to a balanced output line over patterned metal
shield fingers as shown in Fig. 6.10. Electric induction creates a virtual ground (∼ 0 V) on
the floating shield [45], thereby suppressing attenuation and dispersion caused by coupling of
the electric field from the transmission line to the silicon substrate. Adding an explicit shield
158
Chapter 6. A Digitally-Controlled, Differential Distributed Amplifier MZM Driver
Figure 6.10: Simplified layout of the substrate-shielded output line.
to the transmission line increases output capacitance loading, however, the relatively low
capacitance (i.e., 160 fF) at the collectors of transistors Q21,22 (see Fig. 6.9) allows shielding
to be added to lower substrate losses while still realizing Zo,load of 50 Ω. Fig. 6.11 compares
the attenuation coefficient and shunt capacitance to ground for a 500 µm long and 5 µm
wide transmission line without, and with different metal layers as the shield. The unshielded
line is 7 µm above the 10 Ω·cm substrate, and the shielded lines are 2 µm and 5.7 µm away
from the 0.5 µm thick, 2 µm wide and 1 µm spaced shield metal fingers. It is expected that
shielding reduces substrate losses and thus decreases attenuation. The unshielded output line
exhibits the highest attenuation, as seen in Fig. 6.11a. Decreasing the distance between the
line and the shield tends to increase current crowding at the bottom of the transmission line
conductors, thereby increasing losses (i.e., 2 µm vs. 5.7 µm). Moreover, capacitive loading
of the line increases as the distance from the shield to the transmission line decreases, as
illustrated in Fig. 6.11b. The increased shunt capacitance decreases the cut-off frequency of
the output line (see Eq. 6.1) and thus narrows the DA operating bandwidth. Thus, there is
a trade-off between the decrease in substrate losses and the increase in shunt capacitance. It
is observed from Fig. 6.11 that a distance of 5.7 µm is a good compromise. The attenuation
coefficient at 10 GHz is reduced from 0.25 dB to 0.1 dB, and the increase in shunt capacitance
is around 25%, rather than 60% for the 2 µm distance.
The output line in the prototype is implemented in 3.5 µm wide copper topmetal conductors
spaced 120 µm apart. Each segment is 445 µm long, and the shield strips are 2 µm wide
and spaced 1 µm apart. Using metal-2 as the shield minimizes the capacitive loading of the
output transmission line and effectively reduces losses to the substrate. Metal-1 is used for
interconnect wiring underneath the shield. An inductance of 400 pH is required to absorb
the 160 fF shunt parasitic capacitance at each DA cell output (i.e., collectors of transistors
Q21,22 in Fig. 6.9), leading to a cut-off frequency of approximately 40 GHz for the output
6.3. Digitally-Controlled DA Modulator Driver
159
0.5
Attenuation coefficient, in dB
No shield
0.4
0.3
shield 2 m from line
0.2
shield 5.7 m from line
0.1
0.0
0
10
20
30
40
Frequency, in GHz
a) Attenuation coefficient
Shunt capacitance to ground, in fF
35
shield 2 m from line
30
shield 5.7 m from line
25
20
15
No shield
0
10
20
30
40
Frequency, in GHz
b) Shunt capacitance
Figure 6.11: Attenuation and shunt capacitance comparison between unshielded and shielded
transmission lines.
line, and 8–10 ps group delay between stages. A multi-section, RLGC lumped-element model
captures the single-ended and differential behaviors of the output line, and it is used for all
transient simulations. Transistors Q1,2 in Fig. 6.10 represent the differential CB output stage
in the limiting amplifier cell. It is centered in the gap between the transmission line top
160
Chapter 6. A Digitally-Controlled, Differential Distributed Amplifier MZM Driver
a) Magnetic coupling factor of 0.05
b) Magnetic coupling factor of 0.25
Figure 6.12: Simulated prototype eye diagrams with two different magnetic coupling coefficients for the output line (Ls = 420 pH).
conductors in order to preserve layout symmetry and minimize parasitics from interconnects
between the transistor outputs and the output line.
The large space (i.e., 120 µm) between the top conductors minimizes negative mutual coupling and its effect on the self-inductance of the output line. Fig. 6.12 compares the simulated
output eye diagrams of the complete prototype driver for magnetic coupling coefficients (km )
of 0.25 and 0.05. Lower rise/fall times and distortion are observed in the eye diagram when
the coupling between the differential path increases (e.g., km = 0.25 in this simulation).
6.3. Digitally-Controlled DA Modulator Driver
161
Figure 6.13: Simplified cross-section of the on-chip back termination resistor.
Impedance magnitude, in
60
N-well resistor (meas.)
50
40
Poly-silicon resistor (sim.)
30
20
0
10
20
30
40
Frequency, in GHz
Figure 6.14: Measured termination resistor frequency response.
Coupling causes one output to respond to the change in the other path when a transition
happens. Therefore, the output which experiences a low-to-high transition (i.e., a rising edge)
tends to settle to a slightly lower signal level at the beginning of the data interval because of
pulling from the other output with the opposite transition (i.e., a falling edge), and vice versa.
Hence, coupling between the two output paths must be kept minimal. Magnetic coupling
between the lines also lowers the self-inductance of the output line (e.g., 400 pH for km = 0.05
vs. 315 pH for km = 0.25). It should therefore be noted that a lower self-inductance than
required to absorb the line and amplifier stage capacitance could also cause the distortion
observed in the eye diagram in Fig. 6.12b.
162
Chapter 6. A Digitally-Controlled, Differential Distributed Amplifier MZM Driver
Fig. 6.13 shows the simplified cross-section of the n+/n-well termination resistor (note that
the cross-section is not drawn to scale). The shallow n-well just beneath the substrate surface
has a smaller parasitic coupling capacitance to the substrate than the buried layer. Resistor
contacts are made at the two ends of the resistor body with respect to the second contact at
the center of the resistor body (i.e., Terminal 2 in Fig. 6.13). Current flowing into ‘Terminal
2’ is therefore divided into 2 parallel (electrical) paths, which decreases the width of the
resistor body while complying with the maximum current limit for the n-well. ‘Terminal 1’
in Fig. 6.13 is also an AC ground in the prototype driver (i.e., VCC in Fig. 6.3), which shortcircuits its associated parasitic capacitance. The metal interconnects for resistor contacts use
a stack from metal-1 to top copper layer in order to meet electromigration rules.
The 120×180 µm2 , full-custom n+/n-well termination resistor could not be modeled a priori.
The impedance measured from a stand alone test structure shows a first-order roll-off from
53 Ω at 40 MHz to 41 Ω at 40 GHz, as shown in Fig. 6.14. The frequency response from
simulation of a 50 Ω polysilicon resistor equivalent capable of dissipating the same power
(i.e., 0.5 W) is included for comparison. The impedance of the polysilicon resistor rolls-off
much faster and it has a -3 dB bandwidth of just 7.5 GHz. Characterization reveals that
the n+/n-well resistor developed in this work presents 100 fF lower parasitic capacitance
and thus has a much wider bandwidth than the polysilicon resistor (i.e., beyond 40 GHz in
Fig. 6.14).
6.4
Prototype Characterization
The driver prototype is implemented in IBM’s 180 nm SiGe-BiCMOS 7WL technology
(BVCEO = 3.3 V). It features high-performance HBTs with peak-fT /fmax of 60/85 GHz
and 6 interconnect metal layers (i.e., 1 thick copper and 5 aluminum layers) [17].
Fig. 6.15 shows a chip photomicrograph of the prototype. In order to minimize loading
effects on the data and clock paths for a faster edge speed, each D latch is placed close to
the limiting amplifier cell in the same stage, and the variable-phase clock control blocks (i.e.,
the DAC, 2:1 selectors, current adders and clock buffers in Fig. 6.3) are located above the
corresponding D latch. The doubler-divider chain feeds the second and third stages, and thus
it is laid out in between the two stages, having the same physical distance to each stage. As
mentioned previously, the output transistors of the limiting amplifiers (i.e., Q21,22 in Fig. 6.9)
are located along the horizontal line of symmetry in the output line in order to maintain the
same loading on each device. The input data propagates across the entire chip, that is from
left to right in Fig. 6.15. The ground for the limiting amplifiers and the digital grounds are
separated on chip, but connected together at the bondpads. Metal-2 is used in both ground
planes, and bottom metal-1 is used to wire the 12 clock control bits to the bondpads aligned
at the bottom of the chip in Fig. 6.15. The prototype occupies 2.8 mm2 total chip area,
and 1.7 mm2 active area excluding the bondpads. The current consumption is 295 mA from
-5.2 V, and 120 mA from 5 V for a total power consumption of 2.13 W.
6.4. Prototype Characterization
163
Figure 6.15: Chip photomicrograph of the driver prototype.
Figure 6.16: Test setup for the driver prototype.
6.4.1
Test Setup
Fig. 6.16 illustrates the lab experiment setup used to characterize the driver prototype. The
chip is mounted on a heat sink and all of the DC supplies are wirebonded to a test PCB. The
differential clock, data and output are laid out on three different sides of the chip (as shown
in Fig. 6.15), and three GSGSG probes are used to contact the high-speed I/Os on-wafer.
The Anritsu MP1763C pulse pattern generator provides differential data and clock signals
to feed to the chip via two pairs of phase-matched cables. The outputs are connected to
70 GHz sampling modules (i.e., Tektronix 80E09) via 10 cm of semi-rigid coax, ac-coupling
164
Chapter 6. A Digitally-Controlled, Differential Distributed Amplifier MZM Driver
-10
Output return loss,
S
22
, in dB
-5
-15
Differential
(meas.)
-20
Single-ended
(meas.)
-25
Single-ended (sim.)
-30
0
10
20
30
40
Frequency, in GHz
Figure 6.17: Simulated and measured modulator driver output return loss.
capacitors, and 50 Ω attenuators. The on-wafer probe, components and connectors used in
the output path are configured for broad bandwidth with a cut-off frequency greater than
60 GHz. All transient waveforms and the eye patterns are captured on the digital sampling
oscilloscope (i.e., Tektronix TDS8000). A micro-controller driven by Matlab codes provides
the digital signals used to adjust the clock phases for stages 2 and 3 in order to optimize the
output waveforms.
6.4.2
Experimental Results
Fig. 6.17 plots the measured driver output return loss from 10 MHz to 40 GHz. Both the
single-ended and differential results are better than 10 dB up to 35 GHz. Prediction using
an RLC model of the back termination resistor and an RLGC model of the output line from
simulation (as shown in Fig. 6.17) agrees well with the measured data. The misalignment
in frequency between measurement and simulation is likely due to inaccuracy in the selfinductance and capacitive loading parasitics used for the output line in simulation. For
example, unaccounted coupling between the two outputs or between the outputs and the
ground would cause the self-inductance to vary. Non-ideal supply decoupling causes spikes
in the single-ended measured result at frequencies below 1 GHz, but this common-mode
imperfection is eliminated from the measured differential return loss.
The single-ended output transient waveforms at 10 Gb/s measured using the test setup in
Fig. 6.16 are shown in Fig. 6.18. The signal amplitude is 3.1 V at each output across 50 Ω
at 10 Gb/s data rates.
Fig. 6.19 shows the measured eye patterns at different clock phase settings for a 231 -1 length
non-return-to-zero (NRZ), pseudorandom bit sequence (PRBS) data at 10 Gb/s. Duty cycle
distortion is below 1% for a single-ended input amplitude larger than 120 mVp−p . The slight
distortion seen in the initial rise/fall of the eye pattern in Fig. 6.19 is likely caused by the
6.4. Prototype Characterization
165
Figure 6.18: Measured output waveforms at 10 Gb/s.
unaccounted coupling between the two differential paths. It is consistent with the eye diagram
observation in Fig. 6.12 when the line coupling is intentionally increased. Further output
line modeling revealed that km is near 0.15 for the output line, which was underestimated
in the design phase at km = 0.05. The total rise/fall times (20-80%, including the output
interconnections in Fig. 6.16) are 15 ps (min), and can be increased to 50 ps (max) by varying
the latch clock phases digitally, as shown in Fig. 6.19.
The eye pattern measured directly from the data output of the pulse pattern generator (i.e.,
when a thru is connected between the RF probes) is shown in Fig. 6.20. The 20–80% rise/fall
times for the 10 Gb/s data input are 12 ps. Compared to Fig. 6.19, the driver prototype
presents eye patterns with a much smaller jitter. The measured root mean squared (RMS)
and pk-pk jitters for the driver prototype are 0.9 ps and 5 ps, respectively, compared to 1.9 ps
and 13.2 ps for the data output of the pulse pattern generator. Setting the required signal
delay between stages by retiming the D latch data inputs in the proposed driver topology
eliminates jitter in the data path. Note that the clock and data are well aligned in time
so that the sampling action happens after the data is settled. Thus, the timing jitter for
the driver prototype is determined exclusively by the clock jitter. The additive jitter of the
prototype is also negligible, as the measured RMS and pk-pk jitters are identical to that
measured directly from clock output of the pattern generator.
Fig. 6.21 plots the measured edge speed and jitter as a function of the single-ended amplitude
for a 231 -1 length NRZ, PRBS data at 10 Gb/s. The 20-80% rise/fall times are still smaller
than 25 ps when the single-ended input amplitude is decreased to 80 mVp−p . The minimum
single-ended input data amplitude measured for full output swing is 65 mVp−p . The measured
input data rate range is 7.24–11.8 Gb/s, which tracks the locking range of the frequency
doubler-divider chain. The 9.9–12.5 Gbps range could be covered by increasing the selfresonant frequency of the doubler-divider chain slightly.
166
Chapter 6. A Digitally-Controlled, Differential Distributed Amplifier MZM Driver
a) Clock phases for max. rise/fall time
b) Clock phases for medium rise/fall time
c) Clock phases for min. rise/fall time
Figure 6.19: Measured electrical eye patterns for 231 -1 length NRZ PRBS data at 10 Gb/s
(note that the timing indicators are for 20–80% rise and fall times).
6.4. Prototype Characterization
167
Figure 6.20: Measured data eye pattern from the pulse pattern generator at 10 Gb/s (231 -1
PRBS).
Jitter and edge speed, in ps
25
20
Rise time
15
Fall time
10
Pk-Pk jitter
5
RMS jitter
0
80
100
120
140
160
Input data amplitude, in mVp-p
Figure 6.21: Measured rise/fall times and jitter as a function of input data amplitude at
10 Gb/s (231 -1 PRBS).
6.4.3
Performance Comparison
Table 6.2 compares the prototype driver’s performance with (III-V) commercial products
and recently published modulator driver designs. The SiGe prototype produces 6 Vp−p swing
with excellent waveform symmetry between outputs, the fastest (and trimmable) edge speeds
and negligible additive timing jitter. The TGA4954-SL from TriQuint consumes half of the
prototype power consumption (i.e., 1.1 W vs. 2.13 W). However, it should be noted that
2 single-ended amplifiers or a wideband balun (which attenuates output voltage swing) are
required to drive a balanced MZ modulator using these commercial designs. By contrast, the
168
Chapter 6. A Digitally-Controlled, Differential Distributed Amplifier MZM Driver
differential driver TGA4957-SM from TriQuint dissipates as much power as the differential
prototype driver. Designs in [18] and [26] dissipate less power than the prototype driver
because their input and output biasing voltages are supplied by external bias-Ts, which
increases cost and packaging complexity. The prototype demonstrates a wider eye opening
compared to the other silicon drivers [22] [23] because of its faster edge speed and lower
jitter, although the design from [23] consumes less power and chip area. Compared to [22],
the prototype driver consumes 1.6 W less power while implemented in a technology that
has one-half of the transistor fT (i.e., 60 GHz vs. 120 GHz). The digitally-controlled SiGe
DA driver also presents excellent output return loss up to 35 GHz, which makes it well suit
to drive a balanced Mach-Zehnder modulator, and it consumes 1/5 of the chip area of a
(typical) conventional DA [10].
6.4.4
Prototype Power Dissipation Analysis
Despite the very good electrical performance, the power consumption of the proof-of-concept
demonstrator is relatively large compared to silicon implementations such as reported in
[23] and [24]. Table 6.3 summarizes the current distribution and supply voltages for each
building block in the driver prototype shown in Fig. 6.3. The circuit blocks are categorized
into two groups: the digital (i.e., the clock phase control blocks) and analog parts (i.e., the
doubler-divider chain, DA gain cells including the back termination resistors and biasing).
The possibility of realizing a prototype driver with comparable power consumption as the
DA designs in [18] [26] is analyzed in this section.
The Darlington pairs in the 3 limiting amplifiers consume 1.22 W power, which is more
than one-half of the total consumption. However, the required output swing across a 50 Ω
load defines the total current consumption of the DA gain cells (i.e., IDC of 120 mA for
3 Vp−p ). Thus, an effective way to save power is to operate the driver from a lower supply
voltage. A single negative supply (-5.2 V) is used in the prototype for voltage headroom, and
enables directly coupling between different blocks. Integrating the back termination resistors
on chip minimizes parasitics and maximizes the DA bandwidth. However, the two resistors
dissipate 0.36 W DC power since they are in the DC bias path for the output transistors
(i.e., VCC − IDC · RL /2). Consequently, the minimum positive supply voltage required is 5 V
in this work because there is a 3 V drop across each 50 Ω back termination resistor for IDC
of 120 mA. It is shown in Table 6.2 that designs using external bias-Ts eliminate the DC
power consumed by the back termination, and therefore consume approximately 1 W less
power [18] [26]. An alternative method of back termination, such as using an active load [46]
[47], could also be considered to save power.
Assuming that the minimum collector-base (VCB ) and collector-emitter (VCE ) bias voltage
and the voltage headroom across the tail current source are 0.5 V, 1 V and 0.5 V, respectively,
the minimum negative supply voltage for the LA circuit in Fig. 6.9 is -3.7 V. The minimum
positive supply for 3 Vp−p output voltage swing is 2 V using external bias-Ts. Hence, the
power dissipated by the LA Darlington pairs would be reduced from 1.22 W to 0.68 W. It
is noted that 23.4 mA current is drawn by the pre-amplifier and emitter follower between
a.
Data rate
(Gbps)
Output
swing (Vp−p )
Sensitivity
(mV)
RMS/Pk
jitter (ps)
Rise/fall
(ps, 20-80%)
Output return
loss (dB)
>10
(<20 GHz)
>10
(<20 GHz)
>10
(30 GHz)
>10
(<20 GHz)
>10
(45 GHz)
>10
(32 GHz)
PDC
(W)
Area
(mm2 )
Topology
Technology
1.1
-
SE.
-
2.3
-
SE.
-
2.3
-
Diff.
-
3.2
13.2
1.1
6.7
1.13
1.2
-
3.7
1.2
Distributed
amplifier, diff.
Distributed
amplifier, SE.
Distributed
amplifier, diff.
Lumped
amplifier, diff.
Lumped
amplifier, diff.
Lumped
amplifier, diff.
Lumped
amplifier, diff.
Digitallycontrolled DA, diff.
AlGaAs/GaAs
(50 GHz fT )
AlGaAs-InGaAsAlGaAs
BiCMOS
(80 GHz fT )
0.18 µm BiCMOS
(120 GHz fT )
TGA4954-SL
TriQuint
5865 Picosecond
Pulse Labs
TGA4957-SM
TriQuint
10
6
250
1.61/10
25
12.5
8
250
0.7/4
32/36
(10-90%)
28
4–8
-
0.7/-
13/13
[10]
10
6
-
1–2
38/38
[18]
40
6
-
1.1/5.6
<10/<10
[26]
40
2.5
-
-/-
15/15
a
[22]
10
7.6
250
-/-
40/40
a
[23]
10
8
600
0.7/14
42/42
-
0.6
0.68
[24]
10
5
100
-/-
45/30
-
0.68
0.54
[27]
40
6
-
1.4/-
-
1.35
0.72
This work
10
6
65
0.9/5
>10
(<35 GHz)
2.13
2.8
15/15
a
15/15
6.4. Prototype Characterization
Table 6.2: Modulator driver performance comparison.
0.18 µm CMOS
0.25 µm BiCMOS
0.25 µm BiCMOS
(180 GHz fT )
0.18 µm BiCMOS
(60 GHz fT )
Value estimated from eye diagrams.
169
170
Chapter 6. A Digitally-Controlled, Differential Distributed Amplifier MZM Driver
Table 6.3: Modulator driver power consumption breakdown.
Circuit block
Analog
part
Digital
part
Total
Darlington
pair
Pre-amp. and
EF in LA
Doubler
Divider
Biasing
Syn. latch
Latch
DAC and
current adder
2:1 selector
Data buffer
Clock buffer
Driver
prototype
Current (mA)
Power
(W)
+/supply (V)
Expected
power (W)
Scaled +/Supply (V)
3×40 = 120
1.22
5/-5.2
0.68
2/-4
3×23.4 = 70.2
0.37
0.2
20.5
8.7
6
3.8
3×10.5 = 31.5
0.11
0.045
0.031
0.02
0.16
0.082
0.035
0.024
0.015
0.13
2×3.6 = 7.2
0.037
0.029
2×2.7 = 5.4
7.3
24.2
0.028
0.038
0.13
0.022
0.020
0.068
304.8
2.19
0/-5.2
(0 and 5)
/-5.2
1.31
0/-4
(0 and 2)
/-4
the latch and the Darlington pair in each DA stage for re-shaping the latch output signal
and increasing the edge speed. The prototype demonstrates sufficiently fast edge speed for
the 10 Gb/s data rates because of the fast switching in the limiting amplifiers. Thus, the
power budgeted for the pre-amplifier and emitter follower could be reduced in order to lower
the consumption overall. Operated from a 4 V supply with 30% less current, the power
consumption of these two circuits would decrease from 0.37 W to 0.2 W.
Thus, the total power consumption of the prototype would drop from 2.2 W to 1.49 W, as
opposed to 1.1 W for the designs also using external bias-Ts [18] [26]. Approximately 0.1 W
power could also be saved in the digital part from scaling the supply voltage. Following the
same junction bias voltage assumption, the minimum required supply voltage for the digital
part is approximately 4 V, which is constrained by the digital latches, the current adder
and DAC circuits. Therefore, the power consumption from the digital part (excluding the
data and clock buffers) could drop from 0.27 W to 0.21 W, which leads to a total driver
power consumption of 1.43 W. Finally, in order to guarantee first-pass silicon success for
the proof-of-concept prototype, clock and data buffers are used across the whole chip and
sufficient current is consumed in the clock buffers for speed (i.e., 24.2 mA). Operated from
a 4 V supply with 30% less current, all of the clock buffers consume 58 mW less power.
As a result, the lower-power version of the proposed driver topology is expected to consume
slightly larger than 1.3 W total power, operating from a -4 V negative and a 2 V positive
supply voltages with off-chip bias-Ts, which is comparable to the designs in [18] [26] using a
passive input transmission line (i.e., no DC power consumption). The scaled supply voltages
and power consumptions of each block in the driver circuit are summarized in the last two
columns of Table 6.3. On top of it, different circuit architectures capable of operating from
an even lower supply voltage are beneficial for further saving power consumption. System
6.5. Summary
171
simulations are needed to ensure that the edge speed and bandwidth are not compromised
significantly by lowering the supply voltage.
6.5
Summary
A novel, digitally-controlled distributed amplifier suitable for driving a balanced, optical
Mach-Zehnder optical modulator has been successfully demonstrated in IBM’s 180 nm SiGeBiCMOS technology. The proposed topology eliminates many major drawbacks of conventional DAs by employing digital latches at the input in order to replace the passive input
transmission line. The variable-phase clocks retiming the input data stream provide the
correct delay required at the DA output for signal construction. Each data replica at the
latch outputs is identical in waveform and amplitude, and drives the DA cell into saturation,
eliminating the dispersion, attenuation, ringing and pulse distortion inherent in an analog
implementation. The operating bandwidth is also no longer dominated by the input line, but
rather by the digital latches, which support operating data rates higher than that imposed
by the cut-off frequency of the loaded input line. The operating bandwidth limit from the
back termination resistors was also addressed by implementing a full-custom, broadband
n+/n-well resistor on chip.
The proof-of-concept, 2.8 mm2 prototype produces 6 Vp−p differential output swing at 10 Gb/s
using 231 -1 length PRBS. The 20-80% rise/fall times are less than 20 ps with negligible additive jitter. The prototype integrates a substrate-shielded output transmission line, and two
n+/n-well back termination resistors on chip. Measured output return loss is better than
20 dB below 10 GHz and more than 10 dB up to 35 GHz. The inputs are ECL-compatible
with minimum sensitivity of 65 mVp−p , single-ended, at 10 Gb/s data rates. The fully-digital
input interface also supports scalability to: more DA stages, higher output swings, and multiple channels if needed. The total power dissipation is 2.13 W operating from -5.2 V and 5 V
supply voltages. The power dissipation analysis concludes that the proposed driver topology
is capable of operating from a lower supply voltage, and that a lower-power driver design with
tighter design margins than this prototype operating above the 10 Gb/s range is anticipated
with further development.
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Chapter 7
Conclusions and Recommendations
The design challenges presented by silicon technology scaling described in Chapter 1 call
for innovations in system architecture, RF circuit topology and passive component design in
order to develop low-cost SoCs for mass-market applications. The research work in this thesis
concentrated on improving RF and mm-wave circuit performance by integrating advanced
on-chip passive components into new circuit and system configurations. The research was
validated by successful demonstrations of both stand alone passive components and stateof-the-art, wideband power and distributed amplifiers for millimeter-wave wireless and highspeed optical communication applications. Details of the work were reported in Chapters
3–6. The demonstrators in this thesis were implemented primarily in STM’s and IBM’s
SiGe-BiCMOS processes [1] [2], but the analyses and design approaches are also applicable
to other silicon technologies (e.g., CMOS).
7.1
Major Contributions
This section summarizes the major contributions in this thesis from the perspectives of onchip passive components, mm-wave power amplifiers and a multi-Gb/s Mach-Zehnder optical
modulator driver.
A.
On-chip Passive Components
On-chip compact passive components, including self-shielded transformers, baluns, slowwave coplanar waveguides (S-CPWs), substrate-shielded transmission lines and two classes of
multiple-way transformer power combiners were designed, simulated and fully characterized
in this work [3] [4].
The impedance imbalance between primary ports due to interwinding capacitance in a balun
structure is exacerbated as the operating frequency increases which compromises the performance of a power-combining PA. This thesis is the first to propose two new, parasiticcompensated balun and fully-differential transformer combiners that equalize the coupling
via interwinding capacitance for multiple differential inputs. A balun combiner prototype
with port uniformity better than 6% across 50–65 GHz was demonstrated. Combined with
175
176
Chapter 7. Conclusions and Recommendations
self-shielding, the proposed floating-compensated balun and fully-differential transformer
combiner prototypes reached power loss below 1 dB at 60 GHz.
The combiner prototypes developed in this work connect to the RF bondpad at the layout
periphery rather than at the center of the transformer, which minimizes unequal coupling
between the bondpad and the transformer windings. It also eases interconnection between
the combiner and the active devices in an actual PA layout.
A third balun combiner layout was proposed and developed in IBM’s 90 nm SiGe-BiCMOS
process. The crossover required in the secondary (with 2 continuous turns) and the ground
references for both transformer windings are moved outside of the balun layout, allowing more
freedom to scale the passband frequency by adjusting the transformer inner dimension.
The high resistivity substrate in a SOI technology was exploited advantageously for slow-wave
coplanar waveguide (S-CPW) design. The losses imposed by relatively thin metal layers were
solved by stacking several metal layers. The intermetal dielectric (i.e., IMD) close to the IMDsilicon interface was also utilized to maximize the slowing factor. Two-way S-CPW combiners
developed in a 65 nm CMOS-SOI process [5] reached a record-high effective permittivity of
116 and slowing factor of 4.4 in the 60 GHz band. The first CMOS-SOI PA utilizing the
proposed S-CPW combiner was also realized in the same technology.
Thru-reflect-line (TRL) de-embedding test structures used to extract parasitics from bondpads and interconnects in the 60 GHz (and above) bands were included on chip for the first
time. The relevant S-parameter de-embedding algorithm realized in Agilent’s ADS environment was tested on a number of passive prototypes. A ‘round robin’ procedure that enables
measurement of a 4-port passive device using a 2-port vector network analyzer was also
verified in this work.
B.
Millimeter-Wave Power Amplifiers
Millimeter-wave, output-combining power amplifier prototypes were designed for the frequency bands ranging from 60–90 GHz that integrated new passive component designs developed in this work with common-base amplifiers [6] [7] [8]. A transformer-coupled, differential SiGe-BiCMOS PA using a floating-compensated, 4-way balun combiner proposed in
this thesis reached state-of-the-art performance in gain, PAE, RF output power level with
minimal die size. The 3 stage cascade PA realizes greater than 20 dB small-signal power
gain, delivers 20 dBm saturated RF output at 62 GHz with just 2 dBm input driving power
from a 1.8 V supply, and consumes only 0.72 mm2 chip area.
Apart from enabling signal amplification and great RF power output generation from a low
supply voltage at mm-wave frequencies, the parallel-combining PA topologies in this work
also feature favorable reliability. Operating in parallel, the single PA cells in the prototypes
support soft failure when part of the cells breaks down (i.e., compromised performance), as
opposed to the catastrophic failure for the series-combining PA topologies (e.g., stacked-FET
PA), which also require a higher supply voltage (e.g., > 6 V in [9]).
Unconditional stability of the 60 GHz-band PA prototype was promoted by employing crosscoupled capacitive neutralization in differential CB amplifier stages. The potential oscillation
7.1. Major Contributions
177
caused by the output-to-input positive feedback via parasitic collector-emitter coupling was
suppressed by negative feedback via the neutralization capacitors. A fully-differential power
splitter after the PA input stage minimized the amplitude and phase differences in each
differential signal path, thereby suppressing the AC signal on the (shared) supply and ground
paths, ensuring stability.
The PA topologies developed in this work are frequency scalable, and a scaled-up PA prototype operating in the 77/79 GHz band was also demonstrated in the 130 nm SiGe-BiCMOS
technology. This PA demonstrator incorporated both high-performance and medium-breakdown
voltage HBTs for high gain and high collector-emitter breakdown voltage simultaneously in
one gain stage.
Investigations in this work have shown that the cascode amplifier has similar breakdown
behavior to the common-base topology, and can potentially maintain a high PAE in a multistage PA design because of its large power gain. A PA prototype which used the cascode gain
configuration was studied in IBM’s 90 nm SiGe-BiCMOS process. Simulations predict that
it reaches performance similar to the PA demonstrators using the common-base topology,
but with fewer stages and a smaller chip area.
The PA large-signal testing procedure was fully automated (with support from Dr. Marco
Spirito). The 3-step measurement technique described in [10] was implemented in the laboratory test setup. It realizes both power and frequency sweeps.
C.
Distributed Amplifier Multi-Gb/s Optical Modulator Driver
This thesis is the first to introduce a distributed amplifier topology with a fully-digital input
interface. The passive input transmission line in a conventional DA is replaced by digital
latches that provide the required signal delay between stages. Matching of the time delay
between the input and output of the DA can be realized to an arbitrary level of precision
using digital circuitry, which is not possible using analog techniques. Also, replicating the
data stream digitally ensures that each DA cell is driven into saturation by an identical copy
of the input signal, thereby eliminating the dispersion, attenuation, ringing and pulse distortion inherent in an all-analog implementation. In addition, the fully-digital input interface
increases the maximum number of DA stages that can be used, and therefore supports scalability to more stages that can extend the DA cut-off frequency and enable even higher data
rates. The fully-digital input can also be leveraged to drive multiple channels, if needed. In
summary, the proposed DA topology eliminates many drawbacks of the conventional DAs,
as described in Chapter 6.
The 2.8 mm2 digitally-controlled modulator driver prototype integrated the quadrature clock
generator, phase shifters, digital latches, limiting amplifier DA cells, broadband n+/n-well
back termination resistors and a substrate-shielded output line on chip in IBM’s 180 nm
SiGe-BiCMOS technology (i.e., all of the driver building blocks in Fig. 6.3 in Chapter 6).
The full-custom n+/n-well power resistor developed in this work had minimal shunt parasitic
capacitance for broad bandwidth, that is necessary as the on-chip back termination. Its
temperature dependence was also considered in order to avoid a large resistance variation.
178
Chapter 7. Conclusions and Recommendations
The driver produced 6 Vp−p differential swing across a 100 Ω (diff.) load with excellent
waveform symmetry between outputs and an output return loss better than 10 dB below
35 GHz. The output edge speed demonstrated experimentally for the prototype is faster than
many existing commercial products operating at 10 Gb/s implemented in more expensive
III-V technologies.
The Mach-Zehnder modulator driver prototype is also the first to offer a trimmable edge
speed via digital clock phase control. Retiming the input data via digital latches also eliminates jitter in the data path. The prototype jitter is dominated solely by the clock path, and
negligible additive timing jitter is observed.
7.2
Recommendations for Future Work
Despite the many successful passive component and circuit demonstrators in this work,
there is still room for further performance enhancement and innovation in many aspects.
This section lists a few recommendations for future work.
A.
On-chip Passive Components
The passive modeling in this thesis enabled circuit simulations in the time domain. Any
future efforts to develop a more generalized, physically-scalable, lumped-element passive
circuit model would minimize the design iterations required using EM simulations and be
beneficial to both device, circuit and system designers.
A power combiner capable of summing 8 or more PA cells without (significantly) increased
insertion loss needs to be developed in order to deliver the same power output and PAE
from the lower supply voltages imposed by technology scaling (i.e., 1–1.5 V). Connecting
two 4-way combiners in parallel is one possible solution, but the design must suppress the
unwanted influence from the additional interconnects at the primary inputs and secondary
output which are used to connect the combiner to PA active devices. A corresponding 8-way
signal splitting network is also required at the input of the power-combining PA.
The maximum operating frequency of the transformer combiners in this work is in the range
of 100 GHz due to limitations on the inner dimension, assuming 200–250 fF shunt parasitic
capacitance at each primary input from the PA cell. However, an 8-way combining PA with
the same power output as its 4-way counterpart presents lower parasitic capacitance to
the output combiner because each PA cell theoretically needs to deliver 3 dB less power
(and thus uses a smaller transistor size). Therefore, a transformer combiner with the same
primary self-inductance can operate to an even higher frequency with an increasing number of
amplification paths (e.g., 16-way combining), potentially approaching the range for emerging
(sub)terahertz applications.
7.2. Recommendations for Future Work
B.
179
Millimeter-Wave Power Amplifiers
As silicon technology scaling continues, the maximum available gain and fT /fmax of the
active devices continue to increase. It may become worthwhile to investigate the viability of
utilizing class-B or class-C biased, or even switching-mode PAs for mm-wave applications.
When technology scaling increases the power gain of a class-B biased amplifier to 8.5 dB, its
peak-PAE could reach 57% (assuming that its peak collector efficiency remains 66% as shown
in Fig. 2.3b), which is beyond the theoretical maximum PAE of 50% when an amplifier is
class-A biased. Therefore, a multi-stage PA with a class-B biased final stage would provide
a higher overall PAE in that case.
Another problem facing the mm-wave PAs published in the recent literature is the low average
efficiency (or PAE at back-off), because linear amplification requires the PA to operate well
below its maximum power output (e.g., 6–10 dB back-off from PSAT ). Thus, a PA with
good linearity and high efficiency in back-off at mm-wave frequencies is needed. Simulations
predict that a hybrid-class biased amplifier cell, where part of the transistors are biased
with a larger current conduction angle for higher power gain (e.g., class-AB), and part are
biased with a smaller conduction angle for higher efficiency at low power output levels (e.g.,
class-B), has the potential to improve back-off efficiency without significantly compromising
power gain.
This work assumes that the transmit antenna is an ideal 50 Ω load for the PA. Efforts were
made to maximize the reverse isolation of the PA for stability and good tolerance to antenna
impedance mismatch. However, the antenna mismatch can cause the PA load impedance to
deviate considerably from its optimal value, degrading performance. Co-design of the PA
and its output impedance matching network (e.g., the power combiner) with the transmit
antenna behavior is likely to yield a more robust solution. Therefore, if the antenna behavior
is unknown beforehand, the design of a stand alone PA could be assuming a voltage standing
wave ratio (VSWR, e.g., 4:1) to account for the antenna impedance variation.
Ballasting resistors were used in this work to ensure PA thermal stability, but this comes at
the expense of reduced collector-emitter breakdown voltage and headroom. Silicon technology
scaling towards a smaller transistor feature size with a higher current density for peakfT exacerbates thermal stability. More in-depth research on the related subjects, such as
ensuring uniformity of current distribution within a large-area power transistor is therefore
necessary. Improving thermal management locally and globally is likely to enhance the overall
PA performance further.
C.
Distributed Amplifier Multi-Gb/s Optical Modulator Driver
A new version of the driver circuit with lower power consumption is desired and viable,
according to the analysis in the last section of Chapter 6. Also, different circuit architectures
capable of operating from an even lower supply voltage are favored for the lower-power
design. For example, the limiting amplifier DA output stages consume half of the overall
driver power, thus a topology which presents reasonable capacitive loading on the preceding
stage, but avoids the increase in supply voltage from using a Darlington pair could save
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Chapter 7. Conclusions and Recommendations
power. The vector-sum clock phase shifter in the prototype covers a phase control range of
360◦ , however, the DA output line requires just 72–90◦ range in total (i.e., 20–25 ps). Thus,
a clock phase shifter with a reduced control range might potentially simplify the design and
save power.
The active chip area of the prototype is 1.7 mm2 excluding bondpads compared to 2.8 mm2
overall area. A serial-in/parallel-out shifted register (e.g., SP1) [11] to reduce the number of
bondpads for clock control bits and biasing references will make the design more compact.
A transmission line layout with a different aspect ratio (i.e., the ratio of the design width to
length) and dimension could save chip area, and reduce the physical length that data and
clock signals need to propagate on chip.
A future driver design suitable for 40–100 Gb/s optical systems fabricated in a more advanced silicon technology with less parasitic capacitance is also desired. The transmission
line between two DA stages in this work is 445 µm long in order to absorb the 160 fF parasitic
capacitance at the collector of each LA output transistor. Assuming that a newer technology
node reduces the capacitive parasitics to 80 fF, the length of the output line is thus halved to
provide 200 pH inductance needed for 50 Ω impedance matching, leading to a more compact
design. Also, the technique for doubling device breakdown voltage reported in [12] and [13]
may be incorporated in the DA gain cell implementation for the fully-digital driver topology
proposed in this work in order to increase the output voltage swing reliably, if needed.
The exact phase relationship between the quadrature clocks from the doubler-divider chain
generated locally on chip and the clock reference for the first DA stage is unknown in the
10 Gb/s prototype driver. Thus, optimization of the eye patterns was performed manually, and the measurement setup and test procedure are rather complicated. Therefore, it is
preferred that a new version of the driver is designed to have a defined phase relationship
between the external clock and the local clocks generated on chip, so that a fully-automated,
more sophisticated test procedure could be implemented. This would simplify testing, especially when the number of stages is increased to extend the cut-off frequency of the output
line for higher data rates (i.e., more control bits required).
D.
CMOS Implementation and System Integration
This thesis presented several passive component and circuit demonstrators with excellent
performance in SiGe-BiCMOS technologies for mm-wave wireless and high-speed optical
communication applications. The passive and active design techniques developed in this work
are also applicable to submicron CMOS technologies. Thus, future work could integrate the
recommendations described above into CMOS implementations.
In addition, extensive stand alone prototype characterizations were performed to ensure their
reliability and robustness in this work. However, the performance of these building blocks is
not validated in a fully-integrated transceiver, although full system integration is not in the
scope of this work. Therefore, one last recommendation for future work is to demonstrate
the performance and functionality of these circuits in a more integrated system.
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[13] C. Knochenhauer, J. C. Scheytt, and F. Ellinger, “A compact, low-power 40-GBit/s modulator driver
with 6-V differential output swing in 0.25-µm SiGe BiCMOS,” IEEE Journal of Solid-State Circuits,
vol. 46, no. 5, pp. 1137–1146, May 2011.
182
Chapter 7. Conclusions and Recommendations
Appendix A
Thru-Reflect-Line De-embedding
Accurate de-embedding of the pad and interconnect parasitics using dedicated pad-open
and interconnect-short test structures is not possible in the 60 GHz band due to unknowns
(e.g., fringing capacitance and parasitic inductance associated with the test structures), and
distributed parameter effects not captured by the de-embedding procedure. EM simulation
of pads and interconnect as a method of de-embedding is compromised by the complexity of silicon CMOS and BiCMOS back-end technologies, which affects accuracy. Thus, the
test structures in this work (see Fig. A.1) are designed to use the thru-reflect-line (TRL)
de-embedding [1] to extract the frequency dependant behavior of pad and interconnect parasitics. The unknown nature of the standards is accounted for in the calibration procedure
and software algorithm, requiring only that Zo of the line standard to be known a-priori.
A separate CPW (annotated as ‘CPW’ in Fig. A.1a) is included to extract this parameter. Fig. A.2 compares the characteristic impedance extracted from the measured data to
EM simulation across 50–65 GHz, where good agreement is observed. Zo extracted from
measurement is 41 Ω versus 42 Ω predicted from simulation.
The accuracy of de-embedding also depends upon the reflection coefficient of the pad and
interconnections to the device-under-test (DUT). Single-port ground-signal-ground (GSG)
and dual-port ground-signal-ground-signal-ground (GSGSG) probes with a contact pitch of
150 µm were used to measure the DUTs. To transition the ground-signal gap from 150 µm to
∼ 10 µm at the input of the DUT smoothly, the pad and interconnection regions are divided
into 3 parts: a floating-shielded CPW in the pad area, a topmetal/metal-1 microstrip at
the center, and a ground-shielded CPW connecting to the DUT, as shown in Fig. A.3. The
overall Zo is designed to be 50 Ω single-ended, and 100 Ω differential.
Accuracy of TRL de-embedding is verified and validated by measuring a 350 µm long coupled
transmission line (‘Coupled TXL’ in Fig. A.1a). The measured and simulated S-parameters
and MAG are shown in Fig. A.4. Good agreement is observed between simulation and measurement across the 50–65 GHz band. The MAG measured at 60 GHz (i.e., minimal loss
when both the input and output are matched to the system impedance 50 Ω) is -0.35 dB.
MAG extracted from measurement for the transformer power combiners in back-to-back
testing is larger than the insertion loss predicted from EM simulation. This is caused in part
by attenuation from the transmission lines used to implement the back-to-back connection
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184
Appendix A: Thru-Reflect-Line De-embedding
a) SiGe-BiCMOS
b) CMOS-SOI
Figure A.1: Photomicrographs of the de-embedding structures.
between primaries, and also by impedance mismatch between these transmission lines and
the primary terminals.
References
[1] G. F. Engen and C. A. Hoer, ““Thru-Reflect-Line”: An improved technique for calibrating the dual
six-port automatic network analyzer,” IEEE Transactions on Microwave Theory and Techniques, vol. 27,
no. 12, pp. 987–993, Dec. 1979.
185
Characteristic impedance, in Ohm
References
43
Simulation
Measurement
42
41
40
50
55
60
65
Frequency, in GHz
Figure A.2: Measured and simulated Zo of the stand alone CPW in Fig. A.1a.
Figure A.3: Layout within the pad and interconnection regions.
0.8
-10
0.4
MAG
-15
0.0
-20
-0.4
-25
-0.8
and MAG, in dB
Measurement
S
21
-30
50
S
21
S
11
, in dB
Simulation
-5
-1.2
55
60
65
Frequency, in GHz
Figure A.4: Measured and simulated S11 , S21 , and MAG of the coupled TXL in Fig. A.1a
(note that S22 = S11 , and S12 = S21 ).
186
Appendix A: Thru-Reflect-Line De-embedding
Summary
High-Performance mm-Wave and Wideband Large-Signal Amplifiers
The increasing speed of active devices from technology scaling promises silicon-based integrated circuits (ICs) in the RF, millimeter-wave and terahertz regimes. However, the imperfect realities of these technologies, as described in Chapter 1, raise many circuit design
challenges. Nevertheless, advanced (and flexible) silicon back-end-of-line schemes offer new
opportunities for high-quality passive components on chip. Their dimensions shrink with
increasing frequency. Moreover, reducing their physical size further minimizes chip area and
cost in a fully-monolithic circuit implementation. Recognizing the evolving trends for active and passive devices with technology and frequency scaling, the main objective of this
research is to integrate novel, compact passive components on chip, and exploit any new
opportunities that enhance RF and mm-wave silicon IC performance. Innovations in system
and circuit architecture are devised in order to overcome performance impairments inherent
in widely accepted, conventional topologies.
Passive power combining has demonstrated its strength in increasing RF power output and
signal amplification, and found applications in power amplifiers (PAs) for Gb/s mm-wave
wireless communications and distributed amplifiers (DAs) for high-speed optical communications. However, PAs using on-chip transformer combiners suffer from port asymmetry
arising from interwinding capacitance, which can degrade power output and efficiency, as
described in Chapter 2. Conventional DAs are subject to limited bandwidth, signal attenuation and layout inflexibility, primarily caused by the passive transmission line at the input
side, as elaborated in Chapter 6. Wideband PA and DA circuits using passive combiners on
chip are thus chosen as the application examples to prove our research methodology. The
first part of the work in this thesis highlights the developments on passive components and
addresses their associated problems. The second part concentrates on integration of the passive devices developed in this work into PA and DA circuit prototypes. Considerable efforts
are also made on the active circuit design in order to maximize the overall performance.
The demonstrators in this thesis were implemented primarily in SiGe-BiCMOS processes,
however, the active and passive design techniques developed are also applicable to submicron
CMOS technologies.
Chapter 3 presents the design and full characterization of the transformer and slow-wave
coplanar waveguide (S-CPW) power combiners. The passives cater to the strengths of the
back-end-of-line in each technology. The transformers make best use of the thick top metal
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Summary
layers available in the 130 nm SiGe-BiCMOS technology, while the S-CPWs utilize the entire
metal stack and shielding to realize wavelength reduction, and capitalize on the excellent
microwave properties of the insulating substrate in the 65 nm CMOS-SOI process. A new
compensation technique overcomes the deleterious effects of interwinding capacitance in
the transformer combiners at mm-wave frequencies, while self-shielding of the transformers
minimizes substrate loss without adding extra parasitic capacitance. Two new transformer
combiner designs, namely the floating-compensated balun and fully-differential combiners,
realize measured insertion loss below 1 dB and reflected port-to-port impedance uniformity
better than 3% at 60 GHz. They enable fully-monolithic mm-wave PAs with up to 5.5 dB
greater output power for wireless communication, radar and imaging applications. On the
other hand, the physical size of a λ/4 coplanar waveguide combiner in 65 nm CMOS-SOI
is shrunk significantly thanks to slow-wave propagation promoted by adding floating metal
strips beneath the CPW conductors. The in-phase signal coupling within a S-CPW combiner
is also exploited in order to increase the slowing factor even further. The measured wavelength
reduction factor is as high as 4.4 in the 60 GHz band, with just 0.6 dB insertion loss.
Chapter 4 analyzes the selection of single-stage amplifier topologies, covers all of the PA
design aspects and completes several PA prototype implementations. Chapter 5 discusses
the prototype testing and experimental results. The transformer-coupled, 4-way combining,
differential PAs integrate transmission lines, the magnetic components described in Chapter 3 and common-base (CB) or cascode configured amplifiers. Neutralized CB gain stages
maximize output swing from each stage (avoiding breakdown) for greater power output and
promote unconditional stability. Layout techniques which minimize and equalize base series
impedances further ensure PA stability. The measured results - implemented in a 130 nm
SiGe-BiCMOS technology - reach excellent performance trade-off at the time of publishing,
which are ∼ 20 dBm output power, 20 dB small-signal power gain and peak-PAE higher
than 15% from a 1.8 V supply voltage across 58–65 GHz. The PA topology is also frequency
scalable. Several up-banded prototypes operating in the 70–80 GHz-band (applicable to automotive collision avoidance radar and wireless backhaul in the E-band) validate frequency
scalability of the transformer-coupled topology.
The fully digitally-controlled DA prototype described in Chapter 6, is intended for driving a
balanced Mach-Zehnder optical modulator at 10 Gb/s. Many drawbacks from the input, passive transmission line of the conventional DA are mitigated by the proposed driver topology,
which employs digital latches for delay control between DA stages. The variable-phase clocks
of the digital latches retime the input data stream and provide the correct delay required at
the DA output for signal reconstruction. Each data replica at the latch outputs is identical
in waveform and amplitude and drives the DA cell into saturation, eliminating the dispersion, attenuation, ringing and pulse distortion inherent in an all-analog implementation. The
operating bandwidth is no longer limited by the input line but by the digital latches, which
support higher data rates than that imposed by the cut-off frequency of the loaded input
line. Another bandwidth limit from the back termination resistors is addressed by the integration of a full-custom, broadband n+/n-well resistor on chip. The performance achieved
is comparable to, or even better than, many existing commercial products operating at the
Summary
189
same data rates built in III-V technologies. The fully-digital input interface also supports
scalability to more DA stages and multiple channels if needed. A compact, low-power version
of the DA driver operating in the 40 Gb/s or above range is predicted and recommended in
Chapter 7 as future work.
The major contributions in this thesis are listed in Chapter 7. The successful demonstration
of several on-chip passives components and their circuit applications in mm-wave PAs and
multi-Gb/s DA proves the viability of the research ideas proposed and developed in this work.
The approach of passive-aided RF and mm-wave circuit design is capable of enabling novelty
in circuit and system architectures and enhancing their performance overall. Therefore, with
continued technology scaling, it is anticipated that this approach can extend the performance
of systems on chip (SoCs) in low-cost (Bi)CMOS technologies beyond the present state of
the art for mass-market applications.
190
Summary
Samenvatting
Hoogstaande mm-Golf en Breedband Groot-Signaal Versterkers
De toenemende snelheid van actieve componenten als gevolg van voortdurend kleiner wordende technologie suggereert het gebruik van silicium-gebaseerde geı̈ntegreerde circuits (IC’s)
op radiofrequentie-(RF), millimeter-golf- en terahertz-banden. Echter, de suboptimale eigenschappen van deze technologieën, zoals beschreven in hoofdstuk 1, zorgen voor vele uitdagingen in circuitdesign. Geavanceerde (en flexibele) silicium back-end-of-line schema’s geven
niettemin nieuwe mogelijkheden voor hoogstaande passieve componenten op chip. Hun fysieke
afmetingen nemen af met toenemende frequentie. Daarnaast zijn kleine afmetingen wenselijk
voor het minimaliseren van het chipoppervlak en dus kosten bij een volledig monolithische
circuitimplementatie. Voortschrijdende trends in technologie en frequentieschaling voor actieve en passieve componenten in ogenschouw nemend, is het hoofddoel in dit onderzoek de
integratie van nieuwe compacte passieve componenten op chip en het uitbuiten van nieuwe
mogelijkheden welke de RF en mm-golf silicium IC-prestaties verbetert. Daartoe zijn innovaties in systeem- en circuitarchitectuur bedacht om de tekortkomingen in de prestaties van
breed geaccepteerde conventionele topologieën op te lossen.
Het combineren van passieve vermogens heeft potentie laten zien in het vergroten van RF vermogensoutput en signaalversterking, en de techniek wordt gebruikt in vermogensversterkers
(PA’s) voor Gb/s mm-golf draadloze communicatie en distributed versterkers (DA’s) voor
hoge-snelheid optische communicatie. Echter, PA’s gebruiken op-chip transformator combiners welke een poortasymmetrie hebben veroorzaakt door capacitieve koppeling tussen
de windingen, welke de vermogensuitgang en efficiëntie verminderen, zoals besproken in
hoofdstuk 2. Conventionele DA’s zijn onderhevig aan een gelimiteerde bandbreedte, signaalverzwakking en lay-out-inflexibiliteit welke voornamelijk veroorzaakt wordt door de
passieve transmissielijn aan de kant van de ingang, zoals uitgewerkt in hoofdstuk 6. Breedband PA- en DA-circuits die gebruik maken van passieve combiners op chip zijn daarom
gekozen als toepassingsvoorbeelden voor het bewijs van onze onderzoeksmethode. Het eerste
gedeelte van het werk legt de nadruk op de ontwikkelingen van passieve componenten
en de aanpak van daaraan gerelateerde problemen. Het tweede gedeelte concentreert zich
op de integratie van de passieve componenten die in dit werk zijn ontwikkeld in PA- en
DA-circuit prototypes. Verder is uitermate veel aandacht besteed aan het ontwerp van actieve circuits ten einde de algehele prestaties te maximaliseren. De ontwerpen in dit proefschrift zijn voornamelijk geı̈mplementeerd in SiGe-BiCMOS processen, maar de actieve en
191
192
Samenvatting
passieve ontwerptechnieken die zijn ontwikkeld zijn ook toe te passen in sub-micron CMOStechnologieën.
Hoofdstuk 3 bespreekt het ontwerp en laat de volledige details van de transformator- en
‘slow-wave coplanar waveguide’ (S-CPW) -vermogenscombiners zien. De passieven komen
tegemoet aan de voordelen van de back-end-of-line in elke technologie. De transformatoren
maken goed gebruik van de dikke bovenste metaallagen welke beschikbaar zijn in 130 nm
SIGe-BiCMOS technologie, terwijl de S-CPW’s alle metaallagen en afscherming gebruiken
om golflengtereductie te realiseren en voordeel hebben van de uitstekende microgolfeigenschappen van het isolerende substraat in het 65 nm CMOS-SOI-proces. Een nieuwe compensatietechniek lost de schadelijke effecten van de capacitieve koppeling tussen de windingen
van de transformator combiners in de mm-golffrequenties op, terwijl zelfafscherming van de
transformatoren het substraatverlies minimaliseert zonder dat extra parasitaire capaciteit
wordt toegevoegd. Twee nieuwe transformator-combiner-ontwerpen, namelijk de zwevend
gecompenseerde balun en de volledig differentieel combiner, realiseren een gemeten inkoppelverlies onder 1 dB en een gereflecteerde poort-naar-poort impedantie-uniformiteit die
beter is dan 3% bij 60GHz. Ze maken volledig-monolithisch mm-golf PA’s mogelijk met
een groter uitgangsvermogen tot 5,5 dB voor draadloze communicatie, radar en imagingtoepassingen. Aan de andere kant is de fysieke grootte van een λ/4 coplanaire golfgeleidercombiner in 65 nm CMOS-SOI aanzienlijk gekrompen dankzij de slow-wave propagatie welke
wordt bevorderd door het toevoegen van metaalstroken onder de CPW-geleiders. De in-fase
signaalkoppeling binnen een S-CPW combiner is ook gebruikt om de traagheidsfactor verder
te verhogen. De gemeten golflengte-reductiefactor is 4,4 in de 60 GHz band met maar 0,6 dB
inkoppelingsverlies.
Hoofdstuk 4 analyseert de selectie van enkeltraps versterkertopologieën, behandelt alle PA
ontwerpaspecten en laat verschillende afgeronde PA-prototype implementaties zien. Hoofdstuk 5 bespreekt het testen van de prototypen en de experimentele resultaten. De transformatorgekoppelde, 4-weg combinerende differentiële PA’s integreren de transmissielijnen,
de magnetische componenten beschreven in hoofdstuk 3 en common-base (CB) of cascodegeconfigureerde versterkers. Geneutraliseerde CB-versterkertrappen maximaliseren de uitgangszwaai van elke trap (defecten worden voorkomen) voor grotere vermogensoutputs en
bevorderen een onvoorwaardelijke stabiliteit. Lay-out-technieken welke de basis-serie-impedanties minimaliseren en egaliseren waarborgen de PA-stabiliteit verder. De gemeten resultaten geı̈mplementeerd in een 130 nm SiGe-BiCMOS technologie bereiken een (op het
moment van publiceren) uitstekende prestatie-afweging, namelijk ∼ 20 dBm uitgangsvermogen, 20 dB klein-signaal vermogensversterking en een peak-PAE > 15% van een 1,8 V
voedingsspanning bij 58–65 GHz. De PA-topologie is ook schaalbaar in frequentie. Verschillende in frequentie opgeschaalde prototypes werkend in de 70–80 GHz band (toepasbaar op
botsingspreventie-radar op auto’s en draadloze backhaul in de E-band) valideren de frequentieschaalbaarheid van de transformatorgekoppelde topologie.
Het volledig digitaal bestuurde DA-prototype beschreven in hoofdstuk 6 is bedoeld voor het
aansturen van een gebalanceerde Mach-Zehnder optische modulator op 10 Gb/s. Veel nadelen
van de conventionele passieve DA transmissielijningang zijn verbeterd door de voorgestelde
Samenvatting
193
besturingstopologie, waarbij digitale latches zorgen voor vertragingsbeheersing tussen de
DA-trappen. De variabele faseklokken van de digitale latches herklokken de ingangsdatastroom en geven de juiste vertraging benodigd bij de DA-uitgang voor signaalreconstructie. Elke datareplicatie aan de latch-uitgangen is identiek in golfvorm en amplitude en
brengt de DA-cel in verzadiging waardoor dispersie, verzwakking, rondzingen en pulsvervorming, welke inherent zijn aan alle analoge implementaties, worden geëlimineerd. De operationele bandbreedte is niet langer gelimiteerd door de ingangslijn maar door de latches,
welke hogere datasnelheden ondersteunen dan opgelegd door de cut-off frequentie van de
belaste ingangslijn. Een andere bandbreedte-limiet, veroorzaakt door de back-terminationweerstanden, wordt aangepakt door de integratie van een volledig aangepaste, breedband
n+/n-well weerstand op chip. Het resultaat dat is bereikt, is vergelijkbaar met, of zelfs beter
dan, vele van de bestaande commerciële producten die draaien op dezelfde datasnelheden
zoals ingebouwd in III-V technologieën. De volledig digitale ingangsinterface ondersteunt ook
schaalbaarheid naar meer DA trappen en meerdere kanalen wanneer benodigd. Een compacte
laag-vermogensversie van de DA-driver werkend op 40 Gb/s of hoger wordt beredeneerd en
in hoofdstuk 7 aangeraden voor toekomstig onderzoek.
De belangrijkste bijdragen in dit proefschrift zijn opgesomd in hoofdstuk 7. De succesvolle
demonstratie van verschillende op-chip passieve componenten en hun circuittoepassingen in
mm-golf PA’s en multi-Gb/s DA bewijst het belang van de onderzoeksideeën die voorgesteld
en ontwikkeld zijn in dit proefschrift. De benadering van passief geholpen RF en mm-golf
circuitontwerp is geschikt om nieuwe circuits- en systeemarchitecturen mogelijk te maken
en algemene prestaties te verbeteren. Met de voortdurend kleiner wordende schaal van de
technologie is het mogelijk dat deze benadering de prestaties van systemen op chip (SoCs)
in goedkope (Bi)CMOS technologieën verder kunnen verbeteren voor markttoepassingen op
grote schaal.
194
Samenvatting
List of Publications
Journal Papers
Y. Zhao and J. R. Long, “A wideband, dual-path, millimeter-wave power amplifier with
20 dBm output power and PAE above 15% in 130 nm SiGe-BiCMOS,” IEEE Journal of
Solid-State Circuits, vol. 47, no. 9, pp. 1981–1997, Sept. 2012.
Y. Zhao, L. Vera, and J. R. Long, “A 10 Gb/s, 6 Vp−p , digitally-controlled, differential
distributed amplifier MZM driver,” submitted to IEEE Journal of Solid-State Circuits, Aug.
2013.
J. R. Long, Y. Zhao, W. Wu, M. Spirito, L. Vera, and E. Gordon, “Passive circuit technologies for mm-wave wireless systems on silicon,” IEEE Transactions on Circuits and Systems
I : Regular papers, vol. 59, no. 8, pp. 1680–1693, Aug. 2012.
J. R. Long, W. L. Chan, Y. Zhao, and M. Spirito, “Silicon VLSI catches the millimeter
wave,” IEEE Communications Magazine, vol. 49, no. 10, pp. 182–189, Oct. 2011.
Conference Papers
Y. Zhao, L. Vera, J. R. Long, and D. L. Harame, “A 10 Gb/s 6 Vpp differential modulator
driver in 0.18 µm SiGe-BiCMOS,” in Technical Digest of IEEE-ISSCC, Feb. 2013, pp. 132–
133.
Y. Zhao, J. R. Long, M. Spirito, and A. B. Akhnoukh, “A +18 dBm, 79–87.5 GHz bandwidth power amplifier in 0.13 µm SiGe-BiCMOS,” in Proc. of IEEE-BCTM, Oct. 2011, pp.
17–20.
Y. Zhao, J. R. Long, and M. Spirito, “A 60 GHz-band 20 dBm power amplifier with 20%
peak PAE,” in Proc. of IEEE-RFIC, Jun. 2011, pp. 1–4.
Y. Zhao, J. R. Long, and M. Spirito, “Compact mm-wave power combiners in 65 nm
CMOS-SOI,” in Proc. of IEEE-SiRF, Jan. 2011, pp. 33–36.
Y. Zhao, J. R. Long, and M. Spirito, “Compact transformer combiners for millimeter-wave
wireless applications,” in Proc. of IEEE-RFIC, May 2010, pp. 223–226.
195
196
List of Publications
Y. Zhao, Y. Jin, M. Spirito, and J. R. Long, “Millimeter-wave passive components on silicon
for wireless communication applications,” in Proc. of IEEE-ICECS, Dec. 2009, pp. 972–975.
J. R. Long, Y. Zhao, W. L. Chan, K.-C. Kwok, Y. Jin, and D. Zhao, “Silicon millimeter-wave
technologies and circuits,” in Proc. of IEEE-ICECS, Dec. 2009, pp. 956–959.
J. R. Long, Y. Zhao, Y. Jin, W.Wu, and M. Spirito, “Circuit technologies for mm-wave
wireless systems on silicon,” in Proc. of IEEE-CICC, Sept. 2011, pp. 1–8.
Workshop Papers
Y. Zhao, M. Spirito, and J. R. Long, “Millimeter-wave Power Combiner for Wireless Communication Applications,” in Proc. of ProRISC Workshop, Veldhoven, the Netherlands, Nov.
2009.
Y. Zhao, and J. R. Long, “A 60GHz SiGe-BiCMOS Transformer-coupled Power Amplifier
for Wireless Communication Applications,” in Proc. of ProRISC Workshop, Veldhoven, the
Netherlands, Nov. 2010.
Other Papers
Y. Zhao, G. van Veenendaal, H. Bonakdar, J. F. M. Gerrits, and J. R. Long, “3.6mW,
30dB gain preamplifiers for an FM-UWB receiver,” in Proc. of IEEE-BCTM, Oct. 2008, pp.
216–219.
Y. Zhao, Y. Dong, J. F. M. Gerrits, G. van Veenendaal, J. R. Long, and J. R. Farserotu, “A
short range, low data rate, 7.2 GHz–7.7 GHz FM-UWB receiver front- end,” IEEE Journal
of Solid-State Circuits, vol. 44, no. 7, pp. 1872–1882, Jul. 2009.
Y. Dong, Y. Zhao, J. F. M. Gerrits, G. van Veenendaal, and J. R. Long, “A 9mW high
band FM-UWB receiver front-end,” in Proc. of IEEE-ESSCIRC, Sept. 2008, pp. 302–305.
J. F. M. Gerrits, M. Danesh, Y. Zhao, Y. Dong, G. van Veenendaal, J. R. Long, and
J. R. Farserotu, “System and circuit considerations for low-complexity constant-envelope
FM-UWB,” in Proc. of IEEE-ISCAS, May/Jun. 2010, pp. 3300–3303.
J. R. Long, W. Wu, Y. Dong, Y. Zhao, M. A. T. Sanduleanu, J. F. M. Gerrits, and G.
van Veenendaal, “Energy-efficient wireless front-end concepts for ultra lower power radio,”
in Proc. of IEEE-CICC, Sept. 2008, pp. 587–590.
J. F. M. Gerrits, H. Bonakdar, M. Detratti, E. Perez, M. Lobeira, Y. Zhao, Y. Dong, G.
van Veenendaal, J. R. Long, J. R. Farserotu, E. Leroux, and C. Hennemann, “A 7.2–7.7 GHz
FM-UWB transceiver prototype,” in Proc. of IEEE-ICUWB, Sept. 2009, pp. 580–585.
Curriculum Vitae
Yi Zhao was born on February 8, 1983 in Mengzhou, Henan, China. She pursued studies in
Electrical Engineering in Fudan University, Shanghai, China, where she received the B.Sc.
degree with distinction in 2005. She came to the Netherlands in 2006 and started her master
thesis with NXP Semiconductors in 2007. She received the M.Sc. degree in Microelectronics
from the Delft University of Technology, the Netherlands, in 2008.
In 2008, she worked for NXP Semiconductors in Eindhoven, the Netherlands, on ultrawideband RF circuit design. Later that year, she commenced her Ph.D. work in Microelectronics at the Delft University of Technology. Her current research interests include
integrated transceiver circuits for wireless and high-speed communication in the RF and
mm-wave domains. From January 2012 to May 2013, she was with IBM Microelectronics
in Essex Junction, Vermont, USA, where she continued working on her research topic and
benchmarking the newly developed SiGe-BiCMOS technology.
She is the recipient of Best Paper Awards from the IEEE Radio Frequency Integrated Circuits
Symposium (RFIC) and the Topical Meeting on Silicon Monolithic Integrated Circuits in RF
Systems (SiRF) in 2011. She also received the Best New Hire Poster in IBM’s 2nd Annual
Burlington Technology Symposium in 2012.
197
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