Combining Different Configuration Schemes

Combining Different Configuration Schemes
8. Combining Different Configuration
Schemes
December 2009
CF52009-2.5
CF52009-2.5
This chapter describes how to configure Altera® FPGAs using multiple configuration
schemes on the same board. Combining JTAG configuration with passive serial (PS)
or active serial (AS) configuration on your board is useful in the prototyping
environment because it allows multiple methods to configure your FPGA. For
example, if your production environment calls for PS configuration using a
configuration device, you must reprogram your configuration device every time you
wanted to test a design change in your FPGA. If you include the FPGA in the same
JTAG chain as the configuration device, the FPGA can be reconfigured via JTAG
without having to reprogram the configuration device.
In this chapter, the generic term “download cable” includes the Altera USB Blaster
universal serial bus (USB) port download cable, MasterBlaster™ serial/USB
communications cable, EthernetBlaster, ByteBlaster™ II parallel port download cable,
and the ByteBlasterMV ™ parallel port download cable. In this section, the generic
term “FPGA” includes ACEX® 1K, APEX™ 20K, APEX II, Arria® series, Cyclone®
series, FLEX® 10K, Mercury™, and Stratix® series devices.
1
The figures in this chapter will only show the configuration interface connections.
f For detailed information about pull-up resistor values or other pins on the specific
FPGA or configuration device, refer to appropriate chapter in the Configuration
Handbook.
© 2009 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
Volume 2: Configuration Handbook
December 2009
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8–2
Chapter 8: Combining Different Configuration Schemes
Passive Serial and JTAG
Passive Serial and JTAG
Figure 8–1 shows the configuration interface connections when you are using a
download cable to JTAG program a configuration device and the configuration device
is used to configure the FPGAs. In Figure 8–1, multiple FPGAs are daisy-chained
together and the MSEL pins should be set to select PS as the configuration mode.
Figure 8–1. JTAG Programming of Configuration Device with PS Configuration of FPGA Using a Configuration Device
VCC (1)
VCC (1)
1 kΩ
VCC (1)
1 kΩ
Download Cable
(JTAG Mode)
10-Pin Male Header
(2)
(2)
VCC (1)
FPGA
VCC (1)
(2)
n
MSEL
nCE
DCLK
CONF_DONE
nCONFIG
nSTATUS
DATA0
VCC
VIO
GND
nCEO
GND
FPGA
1 kΩ
n
MSEL
DCLK
CONF_DONE
nCONFIG
nSTATUS
DATA0
GND
Configuration Device
DATA
DCLK
OE
nCS
TMS
TCK
TDI
nINIT_CONF
TDO
nCE
nCEO
FPGA
n
MSEL
DCLK
CONF_DONE
nCONFIG
nSTATUS
DATA0
nCE
nCEO N.C.
Notes to Figure 8–1:
(1) VCC should be connected to the same supply voltage as the configuration device. For APEX 20KE devices, nCONFIG should be pulled up to VCCINT.
(2) If the internal pull-up resistors of the configuration device are used, external pull-up resistors should not be used on these pins.
Figure 8–2 shows the configuration interface connections when the configuration
device and the FPGA are in the same JTAG chain. Make sure the TDO signal drives out
a high enough voltage to meet the next device's TDI minimum high-level input
voltage (VIH). The TDO output will drive out the voltage of the I/O bank’s VCCIO where
it resides. For example, if the TDO pin resides in an I/O bank whose VCCIO is set to 3.3
V, the TDO pin will drive out 3.3 V. The download cable is used to JTAG program the
configuration device and the FPGA. The configuration device is used to configure the
FPGA. The MSEL pins should be set to select PS as the configuration mode.
Volume 2: Configuration Handbook
December 2009
Altera Corporation
Chapter 8: Combining Different Configuration Schemes
Passive Serial and JTAG
1
8–3
If there is a configuration device on board, upon power-up you should allow the
FPGA to finish configuration before attempting JTAG configuration.
Figure 8–2. JTAG Programming of Configuration Device and FPGA with PS Configuration of FPGA Using a Configuration
Device
VCC (1)
1 kΩ
VCC (1)
Download Cable
(JTAG Mode)
10-Pin Male Header
VCC (1)
(2)
VCC (1)
(2)
1 kΩ
VCC (1)
(2)
VCC
VIO
FPGA
n
MSEL
GND
DCLK
CONF_DONE
nCONFIG
nSTATUS
DATA0
1 kΩ
nCEO
nCE
N.C.
GND
Configuration Device
DATA
DCLK
OE
nCS
TMS
TCK
TDI
GND
VCC
nINIT_CONF
TDO
TDI
TRST
TMS
TCK
TDO
Notes to Figure 8–2:
(1) VCC should be connected to the same supply voltage as the configuration device. For APEX 20KE devices, nCONFIG should be pulled up to VCCINT.
(2) If the internal pull-up resistors of the configuration device are used, external pull-up resistors should not be used on these pins.
December 2009
Altera Corporation
Volume 2: Configuration Handbook
8–4
Chapter 8: Combining Different Configuration Schemes
Passive Serial and JTAG
The download cables can be used in different modes (e.g., JTAG mode or PS mode)
and in each mode, the header of the download cable connects to different pins on the
FPGA. Therefore, two separate 10-pin headers are required on your board in order to
support two different modes of the download cable. Figure 8–3 shows a schematic
with two download cables. One download cable is used in JTAG mode to JTAG
program the configuration device. The second download cable is used in PS mode to
configure the FPGA using PS configuration. The MSEL pins should be set to select PS as
the configuration mode.
Figure 8–3. JTAG Programming of Configuration Device with PS Configuration of FPGA Using a Configuration Device and
Download Cable
Download Cable
(JTAG Mode)
10-Pin Male Header
VCC (1)
VCC (1)
1 kΩ
(2)
(1) VCC
Download Cable
(PS Mode)
10-Pin Male Header
VCC (1)
VCC (1)
(2)
(2)
1 kΩ
VCC
VCC
VIO
VIO
FPGA
n
MSEL
GND
GND
DCLK
CONF_DONE
nCONFIG
nSTATUS
DATA0
1 kΩ
N.C.
nCEO
nCE
GND
Configuration Device
(3) (3)
(3) (3)
DATA
DCLK
OE
nCS
TMS
TCK
TDI
GND
(3)
nINIT_CONF
TDO
Notes to Figure 8–3:
(1) VCC should be connected to the same supply voltage as the configuration device. For APEX 20KE devices, nCONFIG should be pulled up to VCCINT.
(2) If the internal pull-up resistors of the configuration device are used, external pull-up resistors should not be used on these pins.
(3) To configure the FPGA with a download cable, you should either remove the configuration device from its socket or place a switch on the five
common signals between the download cable and the configuration device.
1
You should not attempt PS configuration with a download cable while a configuration
device is connected to an FPGA.
Volume 2: Configuration Handbook
December 2009
Altera Corporation
Chapter 8: Combining Different Configuration Schemes
Passive Serial and JTAG
8–5
If you try to configure the FPGA using the download cable while the configuration
device is connected to the FPGA, the low signals driven on the nSTATUS and
CONF_DONE pins will pull the OE and nCS pins of the configuration device low. This will
reset the configuration device and cause it to try to configure the FPGA. To perform
PS configuration with the download cable, you should either remove the
configuration device from its socket when using the download cable, or place a switch
on the five common signals between the download cable and the configuration
device.
Figure 8–4 shows a schematic that allows configuration of the FPGA with either a PS
mode download cable or JTAG mode download cable. Additionally, the FPGA can be
configured using the configuration device. One download cable is used in JTAG mode
to JTAG program the configuration device and FPGA. In Figure 8–4 the configuration
device and FPGA are in the same JTAG chain. Make sure the TDO signal drives out a
high enough voltage to meet the next device’s TDI minimum high-level input voltage
(VIH). The TDO output will drive out the voltage of the I/O bank’s V CCIO where it
resides. For example, if the TDO pin resides in an I/O bank whose VCCIO is set to 3.3 V,
the TDO pin will drive out 3.3 V. The second download cable is used in PS mode to
configure the FPGA using PS configuration. The MSEL pins should be set to select PS as
the configuration mode.
Figure 8–4. Combining JTAG Programming of Configuration Device and FPGA with PS Configuration of FPGA Using a
Configuration Device and Download Cable
VCC (1)
Download Cable
(JTAG Mode)
10-Pin Male Header
VCC (1)
1 kΩ
(2)
(1) VCC
Download Cable
(PS Mode)
10-Pin Male Header
VCC (1)
VCC (1)
(2)
(2)
1 kΩ
VCC
VCC
VIO
VIO
FPGA
n
MSEL
GND
GND
DCLK
CONF_DONE
nCONFIG
nSTATUS
DATA0
1 kΩ
nCEO
N.C.
nCE
GND
Configuration Device
(3) (3)
(3) (3)
DATA
DCLK
OE
nCS
TMS
TCK
TDI
GND
VCC
(3)
nINIT_CONF
TDO
TDI
TRST
TMS
TCK
TDO
Notes to Figure 8–4:
(1) VCC should be connected to the same supply voltage as the configuration device. For APEX 20KE devices, nCONFIG should be pulled up to VCCINT.
(2) If the internal pull-up resistors of the configuration device are used, external pull-up resistors should not be used on these pins.
(3) To configure the FPGA with a download cable, you should either remove the configuration device from its socket or place a switch on the five
common signals between the download cable and the configuration device.
December 2009
Altera Corporation
Volume 2: Configuration Handbook
8–6
Chapter 8: Combining Different Configuration Schemes
Active Serial and JTAG
Figure 8–1 on page 8–2 and Figure 8–4 also apply for fast passive parallel (FPP) mode,
except DATA[7..0] is connected from the enhanced configuration device to the FPGAs
that support FPP configuration. The MSEL pins must be set accordingly.
Active Serial and JTAG
For devices that support AS configuration (e.g. Stratix series, Cyclone series, or Arria
series devices), you can combine the AS configuration scheme with JTAG-based
configuration (refer to Figure 8–5). This setup uses two 10-pin download cable
headers on the board. One download cable is used in JTAG mode to configure the
Stratix II or Cyclone series FPGA directly via the JTAG interface. The other download
cable is used in AS mode to program the serial configuration device in-system via the
AS programming interface. The MSEL pins should be set to select the AS configuration
mode. If you try configuring the device using both schemes simultaneously, JTAG
configuration takes precedence and AS configuration will be terminated.
Figure 8–5. Combining JTAG Programming of Configuration Device and FPGA with AS Configuration of FPGA Using a
Configuration Device and Download Cable
(1) VCC
10 kΩ
VCC (1)
VCC (1)
10 kΩ
10 kΩ
Serial Configuration
Device
Stratix II or Cyclone series FPGA
nSTATUS
CONF_DONE nCEO
nCONFIG
nCE
10 kΩ
VCC
N.C.
10 kΩ
VCC
n
MSEL
10 kΩ
GND
DATA
DATA
TCK
DCLK
DCLK
TDO
nCS
nCSO
TMS
ASDI
ASDO
TDI
Download Cable
(JTAG Mode)
10-Pin Male Header (top View)
Pin 1
Pin 1
VCC
VCC (1)
VIO
1 kΩ
ByteBlaster II
(AS Mode)
10-Pin Male Header
GND
Note to Figure 8–5:
(1) VCC should be connected to 3.3 V.
Volume 2: Configuration Handbook
December 2009
Altera Corporation
Chapter 8: Combining Different Configuration Schemes
Document Revision History
8–7
Document Revision History
Table 8–1 lists the revision history for this chapter.
Table 8–1. Chapter Revision History
Date
Version
December 2009
October 2008
2.5
2.4
Changes
■
Updated Table 8–1.
■
Removed “Referenced Documents” section.
■
Updated “Introduction” and “Active Serial and JTAG” sections.
■
Added “Referenced Documents” section.
■
Updated new document format.
January 2008
2.3
Corrected figure title in Figure 9–5.
April 2007
2.2
Added document revision history.
August 2005
2.1
Removed active cross references referring to document outside Chapter 9.
July 2004
2.0
Added Stratix II and Cyclone II device information throughout chapter.
September 2003
1.0
Initial Release.
December 2009
Altera Corporation
Volume 2: Configuration Handbook
8–8
Volume 2: Configuration Handbook
Chapter 8: Combining Different Configuration Schemes
Document Revision History
December 2009
Altera Corporation
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