ValiFrame N5990A MIPI® M-PHY® Receiver Test

ValiFrame N5990A MIPI® M-PHY® Receiver Test
ValiFrame N5990A
MIPI® M-PHY® Receiver Test
Method of Implementation
The ValiFrame Test Automation software provides physical testing of MIPI ® M-PHY® devices with
test instruments listed in 1. The tests are implemented according to the requirements of the
“MIPI Alliance Conformance Test Suite for M-PHY physical layer” version 1.0 and “MIPI Alliance
DRAFT Conformance Test Suite for M-PHY physical layer” version 3.0 (still in
development/approval). The software also offers some custom characterization tests to provide
more details on DUT behavior beyond the limits of the specification.
The MIPI M-PHY Receiver testing supports automatic control of the J-BERT M8020A and the JBERT N4903B high-performance serial BERTs (Bit Error Ratio Tester). It calibrates the stress
conditions and controls all test electronic equipment for automated receiver tolerance tests. For
UniPro and UFS testing the BERT equipment can be combined with the BIT-3000 DSGA to put
the DUT into UniPro Test Mode and retrieve the Frame and Error Counters.
MIPI® and MIPI M-PHY® are registered trademarks owned by MIPI Alliance
1
Content
Required Test Instrumentation.....................................................................................................4
Required Software.......................................................................................................................6
Modes of Operation.....................................................................................................................6
Loopback Mode...............................................................................................................................7
Offline BER Mode.............................................................................................................................7
UniPro Test Mode............................................................................................................................7
Custom BER Reader Mode...............................................................................................................8
System Setup and Operation........................................................................................................8
Step 1. Configuring the Station........................................................................................................8
Step 2. Configuring the DUT..........................................................................................................12
Step 3. Selecting Procedures.........................................................................................................17
Step 4. Modifying Procedure Parameters......................................................................................17
Step 5. Start the Testing.................................................................................................................18
Step 6. Connecting the Setup........................................................................................................18
Step 7: Saving the Project..............................................................................................................19
Result Description......................................................................................................................20
Run-Time Data Display...................................................................................................................20
Interpreting Results.......................................................................................................................20
Test report Document....................................................................................................................21
Appendix A: UniPro Test Mode...................................................................................................22
UniPro Script Generation..............................................................................................................24
Appendix B: Special Parameters Configuration...........................................................................27
Appendix C: Connection Setups..................................................................................................30
M8020A stand-alone Setup...........................................................................................................30
M8020A + DSGA Setup..................................................................................................................31
J-BERT N4903B standalone Setup..................................................................................................32
J-BERT N4903B + DSGA..................................................................................................................33
Appendix D: Test Coverage.........................................................................................................35
HS Tests..........................................................................................................................................35
Squelch Tests..................................................................................................................................39
PWM Tests.....................................................................................................................................40
SYS Burst Tests................................................................................................................................43
Interference Tests..........................................................................................................................45
2
List of Figures
Figure 1: Station Selection dialog.........................................................................................................9
Figure 2: Station Configuration dialog..................................................................................................9
Figure 3: Instrument Configuration dialog.........................................................................................11
Figure 4: Selecting Configure DUT......................................................................................................12
Figure 5: Configure DUT dialog...........................................................................................................13
Figure 6: Custom HS DR dialog...........................................................................................................15
Figure 7: Select M-PHY Sequences dialog..........................................................................................16
Figure 8: Modifying Procedure Parameters........................................................................................18
Figure 9: Showing Connection Diagram dialog...................................................................................19
Figure 10: UniPro Test Mode implementation...................................................................................22
Figure 11: M8020A + DSGA UniPro Test Mode setup........................................................................23
Figure 12: UniPro Script Generator dialog..........................................................................................24
Figure 13: UniPro Files dialog.............................................................................................................25
Figure 14: Select M-PHY Sequences dialog........................................................................................26
Figure 15: Special Parameters dialog..................................................................................................27
Figure 16: Connection Diagram for M8020A stand-alone Setup.......................................................30
Figure 17: Connection Diagram for M8020A + DSGA Setup..............................................................31
Figure 18: Connection Diagram for J-BERT N4903B stand-alone Setup.............................................32
Figure 19: Connection Diagram for J-BERT N4903B + DSGA Setup....................................................33
3
Required Test Instrumentation
The following table lists all the hardware required. The three last columns show the quantity
necessary depending on the test mode (see Modes of Operation).
Module
Module Description
Loopback
UniPro
Offline/
Custom
For M8020A as High performance BERT
M8020A with options:
M8020A-BU1 or BU2
M8070A-0TP
M8041A-0G3
M8041A-0G7
J-BERT M8020A High-performance BERT:
Pattern Generator 1 channel, 8Gb/s,
jitter sources, AXIe chassis,
embedded PC (optional), M8000 SW
1
1
1
M8041A-C08
BERT one channel, data rate up to 8.5 Gb/s.
Required for G1, G2 and G3
1
1
1
M8041A-C16
BERT one channel, data rate up to 16 Gb/s.
1
1
1
M8041A-0G4
Multi-tap de-emphasis, module-wide license.
* Recommended
1*
1*
1*
M8041A-0G5
Internal ISI Generation. * Recommended
1*
1*
1*
M8041A-0A3
J-BERT M8020A analyzer equalizer.
1
M8041A-0G6
Reference clock input with multiplying PLL,
clock group wide license
1
1
1
1
1
1
1
For N4903B J-BERT as High performance BERT
N4903B with options:
J-BERT N4903B High-Performance Serial BERT
N4903B-C13
13 Gbit BERT. Only required for M-PHY Gear4
N4902B-C07
13 Gbit BERT. Only required for M-PHY Gear1
to Gear3
N4903B-J10
N4903B-002
N4915B
Needed for 2 lane measurement support
De-emphasis Signal Converter – only required
for Gear3 and Gear4
If Separate Low Speed Generator is used
4
BIT-4000-3000-0
(Mainframe)
BIT-4000-3001-0
(Clock Module)
BIT-4000-3002-0
(Generator Module)
BIT-4000-3003-0
(Analyzer Module)
BIT-4000-3004-0
(Trigger Module)
DSGA (BIT-3000) set up
1
BIT-4000-2100-0
(Mainframe)
Switch System (BIT-2100) set up
1
BIT-4000-2101-0
(Master Controller)
BIT-4000-2122-0 (2x
2:1 Module)
BIT-1004-0003-0
Matched cable pair, +/- 2ps. For connecting
DSGA to M8020A to the Switch System and
the DUT
3
Oscilloscope for Calibrations
DSO90604A or
DSAV804A
Digital Signal Analyzer with 13 GHz or higher
bandwidth. For testing Gear 1 and 2
1
1
1
DSAV254A or
DSAZ254A
Infiniium V-Series Oscilloscope: 20 GHz, 4
Analog Channels any other instument with
higher bandwidth. For testing Gear 3 and
Gear 4.
1
1
1
E2688A
High-speed SDA
1
1
1
N5400A
EZJIT Plus
1
1
1
N5465A with option
-001
InfniiSim basic. For Embedding package
mode.
1
1
1
1169B
Infinimax II Series Probe Amplifier.
*Recommended for differential connections
2*
2*
2*
N5426A
12GHz InfiniiMax ZIF Tip
1
1
1
N5425B
12 GHz InfiniiMax Differential ZIF Probe Head
1
1
1
E2669B
Differential probe connectivity kit
1
1
1
N5442A
Precision BNC Adapter
1
1
1
M8041A-801
Matched cable pair, +/- 5ps for Gear 1 and
Gear 2
2
2
2
BIT-1004-0003-0
Matched cable pair, +/- 2ps for Gear 3 and
Gear 4
2
2
2
15442A
SMA-SMA cable
1
1
1
Cables
Adapters and Accessories
15432B
250 ps Transition Time Converter
2
2
2
BIT-1001-0002-0
120 ps Transition Time Converter
2
2
2
BIT-1001-0000-0
60 ps Transition Time Converter
2
2
2
N4915A-60001
SATA-Test-Channels for G1 and G2.
For G3 use the M8020A option: MIPI M-PHY
G3 CH3 (required M8041A-0G5)
1
1
1
Switching (for use with DSGA)
5
BIT-4000-2100-0
Switch System (BIT-2100) Mainframe
1
BIT-4000-2101-0
Switch System (BIT-2100) Master Controller
1
BIT-4000-2122-0
Switch System (BIT-2100) 2x 2:1 Module)
1
BIT-1004-0003-0
Matched cable pair, +/- 2ps
3
BIT-1004-0007-0
Single Cable, Connection DUT to the DSGA
Analyser Module
1
Table 1: Instrumentation Requirement List
Required Software
1. Windows XP or 7 operating system
2. Current Keysight IO libraries
3. .Net Framework redistributable 2.0
4. N5990A-010: Test Automation Software Platform Core Product
5. N5990A-165: MIPI M-PHY for J-BERT M8020A and N4903B
6. N5990A-018: Upgrade to MIPI M-PHY Compliance Test Specification Standard and JBERT M8020A Support
7. N5990A-167: UFS / UniPro(1) CTM Rx Test option. Only required for UniPro Test Mode
8. BIT-2001-0002-0: Switch System and DSGA Platform Support
9. For debugging (optional): N5990A-366: MIPI M-PHY Frame Generator for J-BERT
M8020A and N4903B
10. For debugging (optional): N5990A-367: MIPI M-PHY/UniPro Error Counter and Test Script
Wizard for J-BERT M8020A
11. For debugging (optional): N5990A-368: MIPI M-PHY Protocol-Specific Macros for LLI,
SSIC and DigRF v4 for J-BERT M8020A and N4903B
Modes of Operation
The basic principle of all MIPI M-PHY receiver tests is as follows:
1. Configure the DUT for the appropriate test mode
2. Send the stressed test signal
3. Calculate the BER to determinate if the DUT passes or fails the test
There are four modes of operation that mainly affect steps one and three:
6
•
Loopback Mode
•
Offline BER Mode
•
UniPro Test Mode
•
Custom BER Reader Mode
(1) "MIPI, DIGRF, M-PHY, and UNIPRO are registered service marks of MIPI Alliance. All other MIPI specification names are service
marks of MIPI Alliance. [Third party marks are the property of their respective owners.]"
Loopback Mode
The DUT is configured in loopback mode, so it will loop back the received test pattern. Then the
Error Detector (ED) compares the pattern returned by the DUT with the generated pattern to
detect bit errors and compute the BER.
The pattern must match and be in phase. This is ensured by a common reference clock. The
same pattern is loaded to the generators and the ED. When the received bits are not
synchronized with the pattern of the ED, the computed BER will be very high. In this case, the
synchronization algorithm in the ED is restarted.
It is important to note that the ED of the BERT compares the whole pattern, including the Sleep,
Stall and Prepare states. This makes Loopback Mode testing a not ideal solution for bursted
pattern test. If e.g. the Prepare length that the DUT sends back is different to that coming from
the BERT generator, the computed BER will be high and the test will fail, even if the returned
test pattern matches the original pattern.
Offline BER Mode
For each step of the test procedure, ValiFrame shows pop-up dialogs requesting the user to
reset and initialize the device and also asks the user if the DUT is working properly for the
current test step. This method is applicable to the devices that allow a visual check, e.g. a Digital
Serial Interface (DSI) device connected to a display. It is also possible to connect the DUT to the
scope and verify if the output data is valid with help of the serial decoder. Using an offline BER
reader will result in a semi-automated test as at each test point the user has to enter the pass /
fail information.
UniPro Test Mode
The DUT is configured to Test Mode and Frame and Error counters requests are interleaved with
the test pattern.
Then ValiFrame decodes the responses captured with the test equipment and calculates the
BER.
For more details about UniPro Test Mode mode refer to Appendix A: UniPro Test Mode.
7
Custom BER Reader Mode
The usage of a Custom BER Reader enables fully automated testing for all transmission modes
(HS and LS) without the need for a BER ED or UniPro Test Mode support. This method requires
the implementation of a dll supporting the IBerReader interface by the user, as defined in
Appendix H of the M-PHY CTS for M-PHY Version 3. Through this interface, the DUT can be set
to the appropriate test mode and also the pass/fail information can be retrieved. For example,
by reading the DUT's internal error counter registers.
For selecting the operation mode set the parameter “BER reader” from “Configure DUT” dialog
→ “Special parameters” dialog → “BER Settings”. (See BER Settings).
System Setup and Operation
Step 1. Configuring the Station
First step, prior to start with the testing, is to choose the instruments setup and connect to
them. Then start the ValiFrame M-PHY Station Configuration software by clicking on the icon or
acceding from “All Programs/ BitifEye / M-PHY / ValiFrame M-PHY Station Configuration”.
8
•
Database Option: When the N5990A opt. 001 was purchased, the interface to SQL is
available and the test configurations and results will be saved on the server.
•
Results Viewer: Select here the test results to be represented in Excel or HTML format.
•
Sounds: Configure the sound options
Figure 1: Station Selection dialog
2. After pressing “Next” the Station Configuration window allows to select the instrument
setup.
Figure 2: Station Configuration dialog
For receiver testing the following configuration can be chosen:
•
M8020A (stand-alone)
To use this setup, select “M8020A” configuration and leave the “Separate Low Speed
Generator” option unchecked.
This system configuration only requires the M8020A. The instrument works as generator
and as Error Detector if necessary.
It supports the four operation modes: Loopback, Offline, UniPro and Custom BER mode.
For UniPro Test Mode, the M8020A Error Detector requires that the DUT responses are
sent in HS Continuous Mode, meaning with FILLER symbols in between the counter values.
9
Furthermore, for the training pattern generation memory restrictions apply, as described
below under “M8020A + DSGA”.
If the “Use Switch” option is selected the switch can be used to test receiver devices with
up to 4 data lanes.
•
M8020A + DSGA
To use this setup, select “M8020A” configuration and check the “Separate Low Speed
Generator” option.
This system configuration is recommended for the UniPro Test Mode. In this case the DSGA
is used for the DUT configuration and to receive the frame and error counters, while the
M8020A is used to generate the test pattern as well as the frame and error counter
requests. If DUT configuration must happen in the same lane that will be tested, it is
mandatory to use a switch to alternate the DUT inputs between the two generators.
The advantage of M8020A + DSGA setup with respect to the standalone M8020A comes
from the much lower DSGA data rate. Since PWM data with M8020A is generated by bit
multiplication, and depending on the test conditions the M8020A can be running at 9,984
Gbps, the generation of the training sequence will take much longer than with the DSGA,
and the pattern may not even fit into the M8020A instrument's memory.
The DSGA Error Detector requires that the DUT responses come in PWM Mode, either
Bursted or Continuous.
•
J-BERT N4903B (stand-alone)
To use this setup, select “JBERT” configuration and leave the “Separate Low Speed
Generator” option unchecked.
This system configuration only requires the N4903B J-BERT. The instrument works as
generator and as Error Detector if necessary.
It supports the Loopback, Offline and Custom BER operation modes. The J-BERT standalone is not able to operate in UniPro Test Mode, it requires the combination with the
DSGA.
If the “Use Switch” option is selected the switch can be used to test receiver devices with
up to 4 data lanes.
•
J-BERT N4903B + DSGA
To use this setup, select “JBERT” configuration and check the “Separate Low Speed
Generator” option.
10
This system configuration works similarly to the M8020A + DSGA configuration. See section
“M8020A + DSGA” for more information on the system configuration.
NOTE: The DSGA standalone configuration is only supported for transmitter testing.
3. Once the desired setup is selected continue to the instrument configuration window. Here all
the instruments that need to be connected are listed.
Figure 3: Instrument Configuration dialog
All instruments are configured by default in “Offline” mode. In this simulation mode, hardware
does not need to be physically connected to the test controller PC. ValiFrame can not connect to
any instrument in this mode. In order to control the instruments that are connected to the PC,
the instrument address must be entered. The address depends on the bus type used for the
connection, for example, GPIB (General Purpose Interface Bus) or LAN (Local Area Network).
Most of the instruments used in the M-PHY station require a VISA (Virtual Instrument System
Architecture) connection. To determine the VISA address, run the “VISA Connection Expert”
(right-click on the Keysight IO Control icon in the task bar and select the first entry “Keysight
Connection Expert”). Enter the instrument addresses in the “Station Configuration Wizard”, for
example, by copying and pasting the address strings from the Connection Expert entries. After
the address strings have been entered, click on the “Apply Address” button before checking the
“Offline” box to set the instruments needed to be online and then press “Check Connections”
button to verify that the connections for the instruments are established successfully. If
anything is wrong with the instrument address, a window is displayed with a message
describing the problem.
11
If “Separate Low Speed Generator” was checked the BIT-3000 DSGA and the BIT-2100 Switch
will appear in the instrument list and require online connection.
For receiver testing the MIPI M-PHY U7249C/U7249D (Tx automation software) and the
AgDigRF4Exerciser do not need to be connected.
Step 2. Configuring the DUT
After the Station is configured open the ValiFrame M-PHY software by clicking in the icon or
acceding from “Start / All Programs / Bitifeye / M-PHY / ValiFrame M-PHY”.
First step in ValiFrame is to configure the DUT and test options. Click on the “Configure DUT”
button to open the dialog.
12
For product properties select:
1. Receiver as product type
2. Phy Test as Test Type
3. The desired protocol: DigRF v4, LLI, UniPro, SSIC, PCIe, UFS
NOTE: To operate in UniPro Test Mode only UniPro or UFS protocols can be selected.
4. Num of Channels: Select the number of DUT input channels from 1 to 4
The rest of properties to be selected are described below:
Test parameters
13
•
User Name: User name text field (user input).
•
Comment: Text field for user comments.
•
Initial Start Date: Time stamp of the start of the current test session.
•
Last Test Date: Time stamp of the last test conducted in the current session.
•
Compliance Mode: In this mode, the tests are conducted as mandated by the CTS, the test
parameters used in the calibration and test procedures are shown but cannot be modified
by the user.
•
Expert Mode: Calibrations and tests can be conducted beyond the limits and constraints of
the CTS; the test parameters used in the calibration and test procedures can be modified by
the user.
Receiver Test Configuration
•
HS Gears: The HS-Gears that are available:
◦ GEAR 1-A
◦ GEAR 1-B
◦ GEAR 2-A
◦ GEAR 2-B
◦ GEAR 3-A
◦ GEAR 3-B
The selection of gears is not limited. If “x” number of gears are selected, the HS terminated
and non-terminated tests are available “x” times in respective test sub-groups. For receiver
test the GEAR 3-A and 3-B are only available for spec. 3.00.
•
14
Custom HS DR: It allows custom data rates to be added to the tested data rates list.
The list of procedures that are data rate dependent will be increased by the number of
additional data rates that are selected and appear under the respective test groups. The
reference clock frequency value and the “Nominal Data Rate” or “Nominal Ref. Clock” can
also be selected here as well as in the Configure DUT panel.
•
Custom Data Rate: It displays the custom data rates added by the user using the
“Custom HS DR” button.
•
Nominal Data Rate: It sets the reference clock frequency to achieve the nominal Gear xB data rate value as given in the specification. In case of custom data rates, the reference
clock is adjusted to achieve the HS data rate that the user provided.
•
Nominal Ref. Clock: For the selected reference clock frequency, the generated data rate is
calculated as a multiple of the reference clock.
•
Device Type: The type of the DUT can be selected as:
◦ Type I (PWM): PWM: pulse width modulation
◦ Type II (SYS Burst): system-clock synchronous Burst
•
PWM G1 DR (Min;Max), Additional Gears: These two options are enabled when the device
type is selected as Type I (PWM) The minimum and maximum PWM Gear 1 data rate are
given in the text box. The additional PWM Gears can be selected from Gear 2 to 7 by
selecting the check boxes.
If the device type is selected as Type II (SYS), the two options (PWM Data Rate and
Additional Gears) are disabled.
•
15
Spec Version: Select the version using the drop down menu:
◦ 2.00
◦ 3.00
•
Default Levels: It allows the voltage levels to be changed or set to default.
•
Default Timing: It allows the timing parameters (Prepare Length, Stall, Sleep, Sync Length)
to be set.
•
Default Sequences: It allows the HS, LS, and Squelch sequence files to be selected.
◦ The D10.5 and D26.5 symbols are used as default for sync pattern.
◦ The word size can be selected as 8 bit, 10 bit, 16 bit and 20 bit with the drop-down
menu.
◦ If the “Re-Init Sequence” check-box is checked, the pattern generator sequencer will be
restarted for every test step. It will bring up the link while the signal impairments are
being applied, which can be harder on the DUT. If is not checked, the sequencer will
bring up the link only once during the Initialization.
◦ Click on “Generate UniPro Scripts” to generate the scripts required for the UniPro Test
Mode (see for more details UniPro Script Generation). IMPORTANT: This step is
mandatory and only necessary for this test mode and requires a license for option 167.
•
Special Parameters: Brings up a dialog where advanced parameters can be selected. For
more details, see Appendix B: Special Parameters Configuration.
•
Ref Clock Frequency: The frequency can be chosen as:
◦ 19.2 MHz
◦ 26 MHz
◦ 38.4 MHz
16
◦ 52 MHz
•
Target BER HS: It can be selected using the drop-down menu.
•
Target BER LS: It can be selected using the drop-down menu.
Step 3. Selecting Procedures
When the Configure DUT dialog is closed, the ValiFrame main window shows the corresponding
test tree. All calibration and test procedures are included in the respective groups in a way
similar to how they are organized in the CTS. The main groups are:
•
Calibrations
•
HS Tests
•
Squelch Tests
•
PWM Tests
•
Interference Tests
All the procedures can be selected globally by clicking on the check box at the top of the group.
Alternatively, you can expand each test group with the ‘+’ marker in front of each group so that
the individual procedure can be selected by checking the specific selection boxes in front of the
tests. Only the procedures which are selected will be executed.
Before any test procedure can be run, the MIPI M-PHY test system must be calibrated.
Therefore, at least the first time the software is run, the group of calibration procedures must
be selected and executed.
Step 4. Modifying Procedure Parameters
For most procedures specific parameters can be set. These parameters are shown on the right
side of the ValiFrame User Interface when a specific calibration or test procedure is selected.
These values are editable when the “Expert Mode” was chosen in the configuration. If the
parameters are not displayed press the “Properties” button of the main menu.
17
For detailed description of all the parameters refer to section 3.4 of the MIPI M-PHY Manual
Step 5. Start the Testing
Once the tests are selected the “Start” button is enabled and colored in green. When clicking on
the “Start” button the test are run in the order shown in the test procedure selection tree.
Step 6. Connecting the Setup
The connection diagram is displayed automatically when the selected procedure is started. It
can also be displayed by right-clicking on the desired test or calibration and selecting “Show
Connection”.
18
Refer to Appendix C: Connection Setups for detailed description of the setup connection for the
different system configurations.
When the setup is correctly connected press “OK” and the procedure will continue.
Step 7: Saving the Project
It is possible to save the current state of the project in “File → Save Project / Configuration...”. This
will save the selected DUT configuration, the value of all procedure parameters and the results of
all the test executed until that time.
That allows to close ValiFrame and continue with the testing on another moment by loading the
project (File → Load Configuration…).
19
Result Description
Run-Time Data Display
While the program is running the data is displayed in a temporary MS Excel or HTML worksheet,
which opens automatically for each individual test
The worksheet is closed once the specific test is finished. As long as the Test Automation
Software is running, each worksheet can be reopened by double clicking on the procedure
name. However, the individual worksheets will be lost when ValiFrame is closed, unless
individual worksheets or a collection of them were saved by the user.
Interpreting Results
Once the selected procedures are run successfully, the smiley at the front of each individual
procedure indicates the result (Pass / Fail / Incomplete) by displaying it's face in specific ways as
given below.
Smiley
Description
It indicates that the procedure passed successfully in a previous run and the results are available.
It indicates that the procedures passed in offline mode in a previous run and the results are available
It indicates that the procedure is passed successfully in the present run
It indicates that the procedure was not run completely in the previous run.
It indicates that the procedure could not be run in the present run. Most likely the DUT failed during
initialization, so no test(s) were conducted.
It indicates that the procedure failed in the previous run.
It indicates that the procedure is failed in the present run.
Generally, this kind of smiley displays two results such as the first half indicates that the result of the
present run and the second half shows the result of the previous run. In this example, the first half
indicates that the procedure is passed successfully in the present run and the second half means that
it was not completely run in the previous run.
Table 2: Smiley's Result Description table
The DUT will be considered conformant when all required CTS tests are passed successfully.
Tests which are not part of the CTS can be easily recognized because the procedure name does
not contain the test number (for example “Jitter Sensitivity Test”). Please refer to the Appendix
D: Test Coverage for more detailed information the performed tests.
20
Test report Document
After all tests have been run, a test report document can be generated. All individual
worksheets are combined in a summary Excel/HTML workbook at the end of the test run. The
workbook must be saved explicitly (File > Save Results as Workbook...), otherwise the data will
be lost.
21
Appendix A: UniPro Test Mode
The main characteristics of this mode are:
•
Do not use loopback to Error Detector
•
Set the device to Test Mode by means of UniPro PACP packets
•
Interleave PACP Frame and Error Counter requests in between the Test Pattern
•
PACP Packets can be HS or PWM
•
Data transmission can be bursts or continuous mode (bursts with FILLERS in between)
Figure 10 summarizes the implementation of the UniPro test mode
The implementation depends on the instrument setup selected in the Station Configuration:
22
•
M8020A stand-alone: The M8020A is used as generator and to capture the DUT
response. It will send the entire sequence. The DUT must transmit the responses in HS
Continuous mode.
•
M8020A + DSGA: The training sequence is sent by the DSGA. The M8020A sends the test
pattern and the Frame and Error Counter Request. The DSGA captures the Frame and
Error Counter responses. The DSGA can receive the DUT responses in PWM mode
(Continuous or Burst).
Figure 11 shows the setup required for this configuration.
Note that in addition to the M8020A and the DSGA a BIT-2100 Switch system is required
to alternate the DUT Rx input between the two generators.
•
J-BERT N4903B + DSGA: Works similar to M8020A + DSGA.
The training sequence needs to have the following structure:
23
•
Send PACP Test Mode Request (TestModeReq() macro)
•
Bring TX out of HIBERN8 (SetReq(…) macro, set register 2B)
•
Configure Rx transmission Mode, Gear, etc
•
Configure Tx transmission Mode, Gear, etc
•
Transmit Test Pattern with Equipment (TestDataFrame macro)
•
Request Frame and Error Counter (GetReq(…) macro, registers 15C0 and 15C1)
UniPro Script Generation
To operate in UniPro Test Mode it is necessary to replace the default scripts by UniPro scripts.
These are generated in the “UniPro Script Generator” dialog in the N49990A enhancement of
option 167.
From the “Configure DUT” dialog, click on the button “Default Sequence” and then on
“Generate UniPro Scripts” and the “UniPro Script Generator” dialog will open.
Here several properties can be selected:
•
Test Pattern: Chose between the two test patterns supported by the UniPro Adapter Layer:
◦ CJTPAT
◦ CRPAT
•
Tx Response: The DUT can be configured to transmit the response in high or low speed.
◦ PWM Gear 1: The DUT will transmit the signal in low speed PWM. This option must be
selected for the setups that include the DSGA instrument as Error Detector (M8020A +
DSGA or N4903B + DSGA setups).
◦ HS Gear 1-A: The DUT will transmit the signal in high speed. This option must be
selected for the stand-alone M8020A setup.
•
Tx Amplitude Mode: The DUT can be configured to transmit with two different amplitude
modes
◦ Large
24
◦ Small
Select the desired amplitude mode. If both are selected different scripts will be
generated for each mode.
•
Transmission mode: The two transmission modes can be selected
◦ Burst
◦ Continuous
Different scripts will be generated for each transmission mode. Both modes should be
selected because there are procedures that requires burst mode and there are procedures
that requires continuous mode.
•
Idle Line States: Specify the time of the different Idle signals
•
Gaps Length: Specify the length of the different GAPs that are used in the training
sequence
After pressing the “Generate Patterns” button all the scripts will be created and listed. A script
for each HS and LS test mode is generated and the generic name selected in the Configure DUT
dialog.
When the dialog is closed, the HS and LS default sequences are replaced in the “Select M-PHY
Sequences” window. Now the HS and LS sequence names make use of Wildcards.
25
This word between in brackets is replaced in run time by the current parameters. Therefore a
different script is loaded depending on the test conditions.
Wildcard
Value
[Type]
RX, TX
[LsGear]
PWM1, PWM2, PWM3,..PWM7
[HsGear]
Gear1A, Gear1B,...Gear3B
[Mode]
Cont, Burst
[Channel]
Data0, Data1, Data2, and Data3
[Amplitude]
Large, Small
Table 3: Wildcards Description
Example: When running a receiver test for:
•
HS Gear 1A
•
in burst transmission mode
•
large amplitude
•
channel 1
The Unipro[Type][HsGear][Mode][Amplitude][Channel].seq sequence name will be replaced by:
•
26
UniproRxGear1ABurstLargeData0.seq
Appendix B: Special Parameters Configuration
BER Settings
For automated receiver testing, it is necessary to determine whether the DUT receives the data
properly. This can be achieved by reading pass / fail information from the device. The Bit Error
Ratio (BER) is measured and read. ValiFrame supports four different BER Reader
implementations. Each BER Reader option will determinate a different test mode:
27
•
BERT Analyzer: Select BER Analyzer to operate in Loopback mode (see Loopback Mode ).
•
Offline BER Reader: See (see Offline BER Mode).
•
UniPro BER Reader: For operation in UniPro Test Mode (see UniPro Test Mode).
•
Custom BER Reader: See Custom BER Reader Mode ). Choosing the Custom BER Reader,
a new option “Get Errors from BERT” is visible. If it is enabled, the BER is calculated
based on the BERT ED, otherwise it's received from the DUT.
Calibrations and Files directories
By using the “Browse” button, a directory can be selected to save and load the calibrations.
Pressing on the “Default” button sets the default calibrations files directory to:
C\ProgramData\BitifEye\ValiFrame\Calibrations\MPhy”.
Error Detector Settings
Configure here the parameters of the Error Detector's CDR, when used.
•
Loop Bandwidth
•
Loop Order
•
Transition Density
•
Peaking
Also select Input Termination to “Balanced” or “Unbalanced” in case of M8020A setup.
Infiniium Settings
It allows to select a transference function for the different oscilloscope channels. This is used
during calibration in order to embed a channel model.
Other Settings
•
Reduced Amplitude at Init: If the box is checked, the amplitude of the generator will be
set to the value defined by the user at the beginning of each test procedure while the
generators are being initialized.
•
Setup procedure in each test subgroup: If it is enabled, the “Setup Procedure Full” is
available for each test sub group in the ValiFrame User Interface during Tx test, allowing
the user to configure the DUT before the tests are started.
•
Use De-Emphasis: If selected Transmitter De-emphasis will be used.
•
User external Ref Clock: The reference clock that is generated by the BERT is not
continuous when the generators are stopped because of some reasons such as a new
pattern is loaded to it and the jitter sources are enabled. In this case, the user can use an
external reference clock source by selecting the “Use external Ref Clock” check-box and
it can be either an additional instrument or the reference clock output from the DUT. All
the instruments need to be connected as shown in the connection diagram window.
The available options are:
28
◦ PLL (only HS tests): The External PLL mode is used to lock the generator to an
external clock and the provided clock must not be modulated. A clock multiplication
with x/y is possible, with x/y = 1, 2, 3, to 255 for N4903B and x/y = 2 to 162 for
M8020A. It can not be used for PWM tests because of the hardware limitation.
◦ Direct: In External clock mode, all output signals follow the external clock and it's
modulation. For the J-BERT N4903B system configuration, the modulation range is
from 6.75 Gbps to 12.5 Gbps and below 6.75 GHz, SJ and SSC are not available.
However, the external clock can optionally be divided by 1, 2, 4, 8, or 16. For
M8020A generator, the modulation range is from 8.1 GHz to 16.207 GHz.
◦ External 10Mhz: The generator will lock to an external 10MHz reference clock.
For more details about the external clock refer to the J-BERT N4903B manual and the
M8020A manual.
29
•
Manual break at the sequence start: If selected, the sequence will start with an infinite
loop over DIF-N until manual break.
•
Manual break at the sequence end: If selected, the sequence will end with an infinite
loop over DIF-N until manual break.
Appendix C: Connection Setups
M8020A stand-alone Setup
Figure 16: Connection Diagram for M8020A stand-alone Setup
30
•
Connect the M8020A DATA OUT and DATA OUT complement outputs to the DUT Rx
inputs.
•
Add TTCs of 250/120/60 ps (for G1/G2/G3) to this signal path.
•
Connect the M8020A TRIG OUT output to the reference clock input of the DUT.
•
Connect the DUT Tx outputs to DATA IN and DATA IN complement inputs of the M8020A.
M8020A + DSGA Setup
31
•
Connect the DSGA, first module, second generator Dp to the first SPDT, (2:1 Switch
Module) connector 1.
•
Connect the DSGA, first module, second generator Dn to the second SPDT, connector 1.
•
Connect the M8020A, first module, DATA OUT to the first SPDT, connector 2.
•
Connect the M8020A, first module, DATA OUT complement to the second SPDT,
connector 2.
•
Connect the Switch, first SPDT connector C to the Rx positive input of the DUT
•
Connect the Switch, second SPDT connector C to the Rx positive input of the DUT
•
Add TTCs of 250/120/60 ps (for G1/G2/G3) to this signal path.
•
Connect the M8020A TRIG OUT complement output to the reference clock input of the
DUT.
•
Connect the DUT Tx outputs to DATA IN and DATA IN complement inputs of the DSGA.
J-BERT N4903B standalone Setup
Figure 18: Connection Diagram for J-BERT N4903B stand-alone Setup
32
•
Connect the J-BERT Data and Data complement outputs to the Rx inputs of the DUT
•
Add TTCs of 250/120/60 ps (for G1/G2/G3) to this signal path.
•
Connect the J-BERT Trigger/Ref Clk output to the reference clock input of the DUT.
•
Connect Clk complement output of the J-BERT generator to the Clk input of the J-BERT
Error Detector
•
Connect the DUT Tx outputs to DATA IN and DATA IN complement inputs of the J-BERT
Error Detector.
J-BERT N4903B + DSGA
33
•
Connect the DSGA, first module, second generator Dp to the first SPDT, (2:1 Switch
Module) connector 1.
•
Connect the DSGA, first module, second generator Dn to the second SPDT, connector 1.
•
Connect the J-BERT data output to the first SPDT, connector 2.
•
Connect the J-BERT data output complement to the second SPDT, connector 2.
•
Connect the Switch, first SPDT connector C to the Rx positive input of the DUT
•
Connect the Switch, second SPDT connector C to the Rx positive input of the DUT
•
Add TTCs of 250/120/60 ps (for G1/G2/G3) to this signal path.
•
Connect the J-BERT Trigger/Ref Clk output to the reference clock input of the DUT.
•
Connect Clk complement output of the J-BERT generator to the Clk input of the J-BERT
Error Detector
•
34
Connect the DUT Tx outputs to DATA IN and DATA IN complement inputs of the DSGA
Error Detector.
Appendix D: Test Coverage
HS Tests
Test 2.1.1 – HS-RX Differential Input Voltage Amplitude
This procedure implements the CTS test “2.1.1 HS-RX Differential DC Input Voltage Amplitude
Tolerance (VDIF-DC-HS-RX)”. The purpose is to verify that the Unit Interval (UI HS) and Frequency Offset
(fOFFSET-TX) of the DUT’s HS-TX are within the conformance limits.
There are two test cases defined: VCM-RX = 150mV, VDIF-RX = 245mV and VCM-RX = 150mV, VDIF-RX =
60mV. The test pass when for both test cases the DUT meets the target BER (1E-10); otherwise
fails.
It must be performed for each supported gear and lane.
Test 2.1.2 - HS-RX Accumulated Differential Input Voltage Tolerance
This procedure implements the CTS “Test 2.1.2 – HS-RX Accumulated Differential Input Voltage
Tolerance (VDIF-ACC-HS-G1/G2/G3-RX)”. The purpose is to verify that the DUT is able to successfully
receive HS signaling that meets the minimum conformance requirements for Accumulated
Differential Input Voltage Amplitude (VDIF-ACC-RX).
The test pass if for the accumulated differential voltage defined in the specs, the DUT meets the
target BER (1E-10); otherwise fails.
It must be performed for each supported gear and lane.
For UFS certification this test is not required.
Test 2.1.3 – HS-RX Common-Mode Input Voltage Tolerance
This procedure implements the CTS “Test 2.1.3 – HS-RX Common-Mode Input Voltage Tolerance
(VCM-RX)”. The purpose is to verify that the DUT is able to successfully receive HS signaling that
meets the conformance requirements for Common-Mode Input Voltage (VCM-RX).
There are four test cases defined: VCM-RX = 330mV, VDIF-RX = 150mV; VCM-RX = 25mV, VDIF-RX = 150mV;
VCM-RX = 330mV, VDIF-RX = 245mV; and VCM-RX = 25mV, VDIF-RX = 60mV. The test pass when for all test
cases the DUT meets the target BER (1E-10); otherwise fails.
35
It must be performed for each supported gear and lane.
Test 2.1.4 - HS-RX Differential Termination Enable Time (T TERM-ON-HS-RX)
It implements the CTS “Test 2.1.4 – HS-RX Differential Termination Enable Time (T TERM-ON-HS-RX)”.
The purpose is to verify that the DUT’s HS-RX is able to properly enable its HS-RX termination
within the required time, as bounded by its advertised RX_HS_PREPARE_LENGTH_Capability
attribute value.
The test pass when the maximum T TERM-ON-HS-RX measured value is less than the
RX_HS_Gx_PREPARE_LENGTH_Capability attribute value; otherwise fails.
It must be performed for each supported gear and lane.
For UFS certification this test is not required.
Test 2.1.5 - HS-RX Differential Termination Disable Time (T TERM-ON-HS-RX)
It implements the CTS “Test 2.1.5 – HS-RX Differential Termination Disable Time (T TERM-OFF-HS-RX)”.
The purpose is to verify that the DUT’s HS-RX is able to properly disable its HS-RX termination
within
the
required
time,
as
defined
by
its
configured
RX_Min_STALL_NoConfig_Time_Capability attribute value.
The test pass when the maximum T TERM-OFF-HS-RX measured value is less than the
RX_Min_STALL_NoConfig_Time_Capability attribute; otherwise fails.
It must be performed for each supported gear and lane.
For UFS certification this test is not required.
Test 2.1.6 - HS-RX Lane-to-Lane Skew
This procedure implements the CTS “Test 2.1.6 – HS-RX Lane-to-Lane Skew (T L2L-SKEW-HS-RX)”. The
purpose is to verify that the DUT’s HS-RX is able to successfully receive HS signaling having
worst-case Lane-toLane skew.
The test pass when the maximum lane-to-lane skew value that meets the target BER is within
the skew tolerance specifications. Otherwise fails.
It must be performed for each supported gear and lane.
36
For DigRf v4, PCIe and UFS protocols the test is not available. The J-BERT N4903B configuration
does not support this test.
For UFS certification this test is not required.
Test 2.1.7 – Receiver Jitter Tolerance
This procedure implements the CTS “Test 2.1.7 – HS-RX Receiver Jitter Tolerance (TJ RX, DJRX, RJRX,
STTJRX, STDJRX)”. The purpose is to verify that the DUT’s HS-RX is able to successfully receive HS
signaling having worst-case jitter characteristics.
The test will pass if for all test cases, and with the worst-case jitter characteristics applied, the
DUT meets the target BER (1E-10); otherwise fails.
It must be performed for each supported gear and lane.
Test 2.1.8a - HS-RX Frequency Offset Tolerance (fOFFSET-RX) during HSBurst
It implements the CTS “Test 2.1.8 – HS-RX Frequency Offset Tolerance (fO FFSET-RX)” for Burstmode. The purpose is to verify that the DUT’s HS-RX is able to successfully receive HS Burst
signaling having worst-case frequency offset characteristics.
There are two test cases: VOFFSET-RX = +2000ppm, VCM-RX=200mV, VDIF-RX=200mV and VOFFSET-RX =
-2000ppm, VCM-RX=200mV, VDIF-RX=200mV. The test pass when for both test cases the DUT meets
the target BER (1E-10); otherwise fails.
It must be performed for each supported gear and lane.
For UFS certification this test is not required.
Test 2.1.8b - HS-RX Frequency Offset Tolerance (fOFFSET-RX) during HSContinuous Mode
It implements the CTS “Test 2.1.8 – HS-RX Frequency Offset Tolerance (fO FFSET-RX)” for
Continuous-mode. The purpose is to verify that the DUT’s HS-RX is able to successfully receive
HS Continuous signaling having worst-case frequency offset characteristics.
There are two test cases: VOFFSET-RX = +2000ppm, VCM-RX=200mV, VDIF-RX=200mV and VOFFSET-RX =
-2000ppm, VCM-RX=200mV, VDIF-RX=200mV. The test pass when for both test cases the DUT meets
the target BER (1E-10); otherwise fails.
37
It must be performed for each supported gear and lane.
For UFS certification this test is not required..
Test 2.1.9 – HS-RX Prepare Length Verification
It implements the CTS “Test 2.1.9 – HS-RX PREPARE Length Capability Verification (T HS-PREPARE-RX)”.
The purpose is to verify that the DUT is capable of receiving HS bursts with an HS-PREPARE
length that is consistent with the value indicated by its RX_HS_Gx_PREPARE_LENGTH_Capability
attribute.
The test pass if, for a PREPARE length within +/- 1UI of the value indicated by its
RX_HS_Gn_PREPARE_LENGTH_Capability, the DUT meets the target BER(1E-10). Otherwise fails.
It must be performed for each supported gear and lane.
For UFS certification this test is not required.
Test 2.1.10 – HS-RX Sync Length Verification
It implements the CTS “Test 2.1.10 – HS-RX Sync Length Capability Verification (T SYNC-RX)”. The
purpose is to verify that the DUT is capable of receiving HS bursts with a SYNC length that is
consistent with the value indicated by its RX_HS_Gx_SYNC_LENGTH_Capability attribute.
The test pass if, for a SYNC length within +/- 1UI of the value indicated by its RX_HS_Gn_
SYNC_LENGTH_Capability attribute, the DUT meets the target BER(1E-10). Otherwise fails.
It must be performed for each supported gear and lane.
For UFS certification this test is not required.
Jitter Sensitivity
This is an informative test that is not defined in the CTS. The purpose is to characterize the Jitter
Tolerance of the DUT in a range of SJ frequencies.
The test will pass if, for all SJ frequencies, the maximum TJ that meets the target BER (1E-10) is
within the wort-case jitter scenario defined by the user (Min User-Defined SJ Amplitude
property).
38
Low Frequency Jitter Sensitivity
This is an informative test that is not defined in the CTS. The purpose is to characterize the Jitter
Tolerance of the DUT in a range of low frequencies.
The test will pass if, for all SJ frequencies, the maximum TJ that meets the target BER (1E-10) is
within the wort-case jitter scenario defined by the user (Min User-Defined SJ Amplitude
property).
Squelch Tests
Test 2.4.3 - SQ-RX Squelch Exit Voltage
It implements the CTS “Test 2.4.3 – SQ-RX Squelch Exit Voltage (V SQ)”. The purpose is to verify
that the DUT’s M-RX exits squelch upon detection of an appropriate Squelch Exit Voltage (VSQ).
The test pass when the measured VSQ is within the conformance limits (50-140mV); otherwise
fails.
For UFS certification this test is not required.
Test 2.4.4 – SQ-RX Squelch Exit Time (T_SQ)
It implements the CTS “Test 2.4.4 – SQ-RX Squelch Exit Time (T SQ) ”. The purpose is to verify that
the DUT’s M-RX exits squelch upon detection of a DIF-N pulse of appropriate duration (TSQ).
The test pass when the measured TSQ is less than or equal to TACTIVA; otherwise fails.
For UFS certification this test is not required.
Test 2.4.5 – SQ-RX Squelch Noise Pulse Width (T_PULSE-SQ)
It implements the CTS “Test 2.4.5 – SQ-RX Squelch Noise Pulse Width (T PULSE-SQ)”. The purpose is
to verify that the DUT’s M-RX does not exit squelch upon detection of an appropriate Squelch
Noise Pulse with duration (TPULSE-SQ).
The test pass when the measured TPULSE-SQ is less than or equal to 20ns; otherwise fails.
For UFS certification this test is not required.
39
Test 2.4.6 – SQ-RX Squelch Noise Pulse Spacing (T_SPACE-SQ)
It implements the CTS “Test 2.4.6 – SQ-RX Squelch Noise Pulse Spacing (T SPACE-SQ)”. The purpose is
to verify that the DUT’s M-RX does not exit squelch upon detection of appropriate Squelch
Noise Pulses with spacing (TSPACE-SQ).
The test pass when the measured TSPACE-SQ is greater than or equal to 500ns; otherwise fails.
For UFS certification this test is not required.
PWM Tests
Test 2.2.1 – PWM-RX Differential DC Input Voltage Amplitude
This procedure implements the CTS test “2.2.1 PWM-RX Differential DC Input Voltage Amplitude
Tolerance (VDIF-DC-PWM-RX)”. The purpose is to verify that the DUT is able to successfully receive
PWM signaling that meets the maximum and minimum conformance requirements for
Differential DC Input Voltage Amplitude (VDIF-RX).
There are two test cases defined for terminated line: V CM-RX = 150mV, VDIF-RX = 245mV and VCM-RX =
150mV, VDIF-RX = 60mV; and two test cases for unterminated line: V CM-RX = 150mV, VDIF-RX = 490mV
and VCM-RX = 150mV, VDIF-RX = 120mV. The test pass when, for both test cases and for maximum
and minimum bitrate, the DUT meets the target BER (1E-7). Otherwise fails.
It must be performed for terminated and unterminated line and for each supported gear and
lane.
For UFS certification this test is not required..
Test 2.2.2 - PWM-RX Accumulated Differential Input Voltage Tolerance
This procedure implements the CTS “Test 2.2.2 – PWM-RX Accumulated Differential Input
Voltage Tolerance (VDIF-ACC-PWM-G1/G2/G3-RX)” (only for spec version 2.00). The purpose is to verify that
the DUT is able to successfully receive PWM signaling that meets the minimum conformance
requirements for Accumulated Differential Input Voltage Amplitude (VDIF-ACC-PWM-RX).
The test pass if for the minimum AC differential conformance limit (40mV) accumulated
differential voltage defined in the specs (40mV), the DUT meets the target BER (1E-7);
otherwise fails.
It must be performed for each supported gear and lane.
40
For UFS certification this test is not required.
Test 2.2.3 – PWM-RX Common-Mode Input Voltage Tolerance
This procedure implements the CTS “Test 2.2.3 – PWM-RX Common-Mode Input Voltage
Tolerance (VCM-RX)”. The purpose is to verify that the DUT is able to successfully receive PWM
signaling that meets the conformance requirements for Common-Mode Input Voltage (VCM-RX).
There are two test cases defined for terminated line: V CM-RX = 330mV, VDIF-RX = 245mV and VCM-RX =
25mV, VDIF-RX = 60mV; and two test cases for unterminated line: V CM-RX = 330mV, VDIF-RX = 490mV
and VCM-RX = 25mV, VDIF-RX = 120mV. The test pass when, for both test cases and for maximum and
minimum bitrate, the DUT meets the target BER (1E-7); otherwise fails.
It must be performed for terminated and unterminated line and for each supported gear and
lane.
For UFS certification this test is not required.
Test 2.2.4 - PWM-RX Differential Termination Enable Time (T TERM-ON-PWMRX)
It implements the CTS “Test 2.2.4 – PWM-RX Differential Termination Enable Time (T TERM-ON-PWMRX)”. The purpose is to verify that the DUT’s M-RX is able to properly enable its PWM-RX
termination
within
the
required
time,
as
bounded
by
its
advertised
RX_HS_PREPARE_LENGTH_Capability attribute value.
The test pass when the maximum measured T TERM-ON-PWM-RX value, for minimum and maximum
bitrate, is less than the RX_HS_Gx_PREPARE_LENGTH_Capability attribute; otherwise fails.
It must be performed for terminated line, and for each supported gear and lane.
For UFS certification this test is not required.
Test 2.2.5 - PWM-RX Differential Termination Disable Time (T TERM-ON-PWMRX)
It implements the CTS “Test 2.2.5 – PWM-RX Differential Termination Disable Time (T TERM-OFF-PWMRX”. The purpose is to verify that the DUT’s M-RX is able to properly disable its PWM-RX
termination
within
the
required
time,
as
defined
by
its
configured
RX_Min_STALL_NoConfig_Time_Capability attribute value.
41
The test pass when the maximum measured T TERM-OFF-PWM-RX value, for minimum and maximum
bitrate, is less than the RX_Min_STALL_NoConfig_Time_Capability attribute; otherwise fails.
It must be performed for terminated line and for each supported gear and lane.
For UFS certification this test is not required.
Test 2.2.6 - PWM-RX Lane-to-Lane Skew
This procedure implements the CTS “Test 2.2.6 – PWM-RX Lane-to-Lane Skew (T L2L-SKEW-PWM-RX)”.
The purpose is to verify that the DUT’s M-RX is able to successfully receive PWM signaling
having worst-case Lane-toLane skew.
The test pass when the maximum lane-to-lane skew value that meets the target BER (1E-7) is
within the skew tolerance specifications. Otherwise fails.
It must be performed for unterminated line and for each supported gear and lane.
It is only available for Unipro protocol. The J-BERT N4903B configuration does not support this
test.
For UFS certification this test is not required.
Test 2.2.7a – PWM-RX Receive Bit Duration Tolerance (TOLPWM-RX)
This procedure implements the CTS “Test 2.2.7 – PWM-RX Receive Bit Duration Tolerance
(TOLPWM-RX, TOLPWM-G1-LR-RX)” for non-OMC DUTs. The purpose is to verify that the Receive Bit
Duration Tolerance (TOLPWM-RX) of the DUT’s PWM-RX is within the conformance limits.
The test will pass if the DUT meets the target BER (1E-7) for values of TOL PWM-RX between 0.82
and 1.1; otherwise fails.
It must be performed for terminated and unterminated lines and for each supported gear and
lane.
For UFS certification this test is not required.
42
Test 2.2.7b – PWM-RX Receive Bit Duration Tolerance, During LINE-READ
(TOLPWM—G1-RX)
This procedure implements the CTS “Test 2.2.7 – PWM-RX Receive Bit Duration Tolerance
(TOLPWM-RX, TOLPWM-G1-LR-RX)” for OMC DUTs. The purpose is to verify that the Receive Bit Duration
Tolerance (TOLPWM-G1-LR-RX) of the DUT’s PWM-RX is within the conformance limits.
The test will pass if the DUT meets the target BER (1E-7) for values of TOL PWM-G1-LR-RX between
0.89 and 1.1; otherwise fails.
It must be performed for terminated and unterminated lines, only for PWM-G1, and for each
lane.
For UFS certification this test is not required.
Test 2.2.8 - PWM-RX Receive Ratio, PWM-G1 and Above (kPWM-RX)
It implements the CTS “ PWM-RX Receive Ratio, PWM-G1 and Above (k PWM-RX)” for Burst-mode.
The purpose is to verify that the Receive Ratio tolerance (k PWM-RX) of the DUT’s PWM-RX is within
the conformance limits.
The test will pass if the DUT meets the target BER (1E-7) for the minimum and maximum
conformance kPWM-RX values (0.6/0.4 and 0.75/0.25). Otherwise fails.
It must be performed for terminated and unterminated lines and for each supported gear and
lane.
For UFS certification this test is informative.
SYS Burst Tests
Test 2.3.1 – SYS-RX Differential Input Voltage Amplitudes
This procedure implements the CTS test “Test 2.3.1 – SYS-RX Differential Input Voltage
Amplitude Tolerance (VDIF-DC-SYS-RX)”. The purpose is to verify that the DUT’s M-RX is able to
successfully receive SYS signaling that meets the maximum and minimum conformance
requirements for Differential Input Voltage Amplitude (VDIF-RX).
There are two test cases defined for terminated line: V CM-RX = 330mV, VDIF-RX = 245mV and VCM-RX =
25mV, VDIF-RX = 60mV; and two test cases for unterminated line: V CM-RX = 330mV, VDIF-RX = 490mV
and VCM-RX = 25mV, VDIF-RX = 120mV. The test pass when for both test cases the DUT meets the
target BER (1E-7). Otherwise fails.
43
It must be performed for terminated and interminated line and for each supported gear and
lane.
Test 2.3.3 – SYS-RX Common Mode Input Voltage Tolerance
This procedure implements the CTS “Test 2.3.3 – SYS-RX Common-Mode Input Voltage
Tolerance (VCM-RX)”. The purpose is to verify that the DUT’s M-RX is able to successfully receive
SYS signaling that meets the conformance requirements for Common-Mode Input Voltage (V CMRX).
There are two test cases defined for terminated line: V CM-RX = 330mV, VDIF-RX = 245mV and VCM-RX =
25mV, VDIF-RX = 60mV; and two test cases for unterminated line: V CM-RX = 330mV, VDIF-RX = 490mV
and VCM-RX = 25mV, VDIF-RX = 120mV. The test pass when for both test cases the DUT meets the
target BER (1E-7); otherwise fails.
It must be performed for terminated and unterminated line and for each supported gear and
lane.
Test 2.3.4 – SYS-RX Differential Termination Enable Time (T TERM-ON-SYSRX)
It implements the CTS “Test 2.3.4 – SYS-RX Differential Termination Enable Time (T TERM-ON-SYS-RX)”.
The purpose is to verify that the DUT’s M-RX is able to properly enable its SYS-RX termination
within the required time, as bounded by its advertised RX_HS_PREPARE_LENGTH_Capability
attribute value.
The test pass when the maximum measured T TERM-ON-SYS-RX value is less than the
RX_HS_Gx_PREPARE_LENGTH_Capability attribute; otherwise fails.
It must be performed for terminated line, and for each supported gear and lane.
Test 2.3.5 - SYS-RX Differential Termination Disable Time (T TERM-OFF-SYSRX)
It implements the CTS “Test 2.3.5 – SYS-RX Differential Termination Disable Time (T TERM-OFF-SYS-RX)”.
The purpose is to verify that the DUT’s M-RX is able to properly disable its SYS-RX termination
within
the
required
time,
as
defined
by
its
configured
RX_Min_STALL_NoConfig_Time_Capability attribute value.
44
The test pass when the maximum measured T TERM-OFF-PWM-RX value is less than the
RX_Min_STALL_NoConfig_Time_Capability attribute; otherwise fails.
It must be performed for terminated line and for each supported gear and lane.
Interference Tests
Test 2.4.7 – SQ-RX Squelch RF Interference Tolerance (V_INT-SQ, f_INT-SQ)
It implements the CTS “Test 2.4.7 – SQ-RX Squelch RF Interference Tolerance (V INT-SQ, fINT-SQ)”. The
purpose is to verify that the DUT’s M-RX does not exit squelch upon reception of signaling
containing superimposed RF interferences of appropriate voltage and frequency (VINT-SQ, fINT-SQ).
The test pass if the DUT meets the target BER (1E-10) when is superimposed a common-mode
noise of 200mVpk, from 500MHz to 1500M. Otherwise fails.
It must be performed for each lane.
For UFS certification this test is not required.
Common Mode Interference
This is an informative test that is not defined in the CTS. The purpose is to characterize the
Common Mode Tolerance of the DUT in a range of jitter frequencies.
The test will pass if, for all frequencies, the maximum common mode that meets the target BER
(1E-10) is within the wort-case defined by the user (Min User-Defined Interference Amplitude
property).
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